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/td> -rw-r--r--tool/mbed/mbed-sdk/MANIFEST.in3
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-rw-r--r--tool/mbed/mbed-sdk/workspace_tools/host_tests/example/BroadcastReceive.py25
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4198 files changed, 2016457 insertions, 0 deletions
diff --git a/tool/mbed/mbed-sdk/.gitattributes b/tool/mbed/mbed-sdk/.gitattributes
new file mode 100644
index 000000000..05491d630
--- /dev/null
+++ b/tool/mbed/mbed-sdk/.gitattributes
@@ -0,0 +1,15 @@
+*.c text
+*.cpp text
+*.h text
+*.s text
+*.sct text
+*.ld text
+*.txt text
+*.xml text
+*.py text
+*.md text
+*.json text
+*.tmpl text
+*.dia binary
+*.elf binary
+*.bin binary
diff --git a/tool/mbed/mbed-sdk/.gitignore b/tool/mbed/mbed-sdk/.gitignore
new file mode 100644
index 000000000..b66af8ba4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/.gitignore
@@ -0,0 +1,75 @@
+*.py[cod]
+
+# Distribution dir
+dist
+
+# MANIFEST file
+MANIFEST
+
+# Private settings
+private_settings.py
+
+# Default Build Directory
+build/
+
+# Eclipse Project Files
+.cproject
+.project
+.pydevproject
+
+# C extensions
+*.so
+
+# Packages
+*.egg
+*.egg-info
+dist
+build
+eggs
+parts
+bin
+var
+sdist
+develop-eggs
+.installed.cfg
+lib
+lib64
+
+# Installer logs
+pip-log.txt
+
+# Unit test / coverage reports
+.coverage
+.tox
+nosetests.xml
+
+# Translations
+*.mo
+
+# Mr Developer
+.mr.developer.cfg
+
+output.txt
+uVision Project/
+
+# Sublime Text Project Files
+*.sublime*
+
+*.bak
+debug.log
+
+# Ignore OS X Desktop Services Store files
+.DS_Store
+
+# Orig diff files
+*.orig
+
+# PyCharm
+*.idea
+
+# Cscope
+cscope.*
+
+# vim swap files
+*.swp
+
diff --git a/tool/mbed/mbed-sdk/.travis.yml b/tool/mbed/mbed-sdk/.travis.yml
new file mode 100644
index 000000000..a26edf15a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/.travis.yml
@@ -0,0 +1,9 @@
+---
+python:
+ - "2.7"
+script: "python workspace_tools/build_travis.py"
+install:
+ - "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
+ - sudo pip install colorama
+ - sudo pip install prettytable
+ - sudo pip install jinja2
diff --git a/tool/mbed/mbed-sdk/CONTRIBUTING.md b/tool/mbed/mbed-sdk/CONTRIBUTING.md
new file mode 100644
index 000000000..353cd58c0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/CONTRIBUTING.md
@@ -0,0 +1,45 @@
+# Description
+This document is cheat sheet for everyone who wants to contribute to mbedmicro/mbed GitHub repository at GitHub.
+All changes in code base should originate from GitHub Issues and take advantage of existing GitHub flows. Goal is to attract contributors and allow them contribute to code and documentation at the same time.
+
+Guidelines from this document are created to help new and existing contributors understand process workflow and align to project rules before pull request is submitted. It explains how a participant should do things like format code, test fixes, and submit patches.
+
+## Where to get more information?
+You can for example read more in our ```docs``` section in [mbedmicro/mbed/doc](https://github.com/PrzemekWirkus/mbed/tree/docs/docs) directory.
+
+# How to contribute
+We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things.
+
+Before a pull request will be merged, the [mbed Contributor Agreement](http://developer.mbed.org/contributor_agreement/) must be signed.
+
+You can pick up existing [mbed GitHub Issue](https://github.com/mbedmicro/mbed/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality.
+
+# Enhancements vs Bugs
+Enhancements are:
+* New features implementation.
+* Code refactoring.
+* Coding rules, coding styles improvements.
+* Code comments improvement.
+* Documentation work.
+
+Bugs are:
+* Issues rose internally or externally by mbedmicro/mbed users.
+* Internally (within mbed team) created issues from Continuous Integration pipeline and build servers.
+* Issues detected using automation tools such as compilers, sanitizers, static code analysis tools etc.
+
+# Gate Keeper role
+Gate Keeper is a person responsible for GitHub process workflow execution and is responsible for repository / project code base. Gate Keeper is also responsible for code (pull request) quality stamp and approves or rejects code changes in project’s code base.
+
+Gate Keepers will review your pull request code, give you comments in pull request comment section and in the end if everything goes well merge your pull request to one of our branches (most probably default ```master``` branch).
+
+Please be patient, digest Gate Keeper's feedback and respond promptly :)
+
+# mbed SDK porting
+* For more information regarding mbed SDK porting please refer to [mbed SDK porting](http://developer.mbed.org/handbook/mbed-SDK-porting) handbook.
+* Before starting the mbed SDK porting, you might want to familiarize with the [mbed SDK library internals](http://developer.mbed.org/handbook/mbed-library-internals) first.
+
+# Glossary
+* Gate Keeper – persons responsible for overall code-base quality of mbedmicro/mbed project.
+* Enhancement – New feature deployment, code refactoring actions or existing code improvements.
+* Bugfix – Issues originated from GitHub Issues pool, raised internally within mbed classic team or issues from automated code validators like linters, static code analysis tools etc.
+* Mbed classic – mbed SDK 2.0 located in GitHub at mbedmicro/mbed.
diff --git a/tool/mbed/mbed-sdk/LICENSE b/tool/mbed/mbed-sdk/LICENSE
new file mode 100644
index 000000000..59cd3f8a3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/LICENSE
@@ -0,0 +1,165 @@
+Apache License
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+http://www.apache.org/licenses/
+
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+In no event and under no legal theory, whether in tort (including negligence),
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diff --git a/tool/mbed/mbed-sdk/MANIFEST.in b/tool/mbed/mbed-sdk/MANIFEST.in
new file mode 100644
index 000000000..17993153c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/MANIFEST.in
@@ -0,0 +1,3 @@
+graft workspace_tools
+recursive-exclude workspace_tools *.pyc
+include LICENSE
diff --git a/tool/mbed/mbed-sdk/README.md b/tool/mbed/mbed-sdk/README.md
new file mode 100644
index 000000000..d8afa8c8e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/README.md
@@ -0,0 +1,115 @@
+mbed SDK
+========
+
+[![Build Status](https://travis-ci.org/mbedmicro/mbed.png)](https://travis-ci.org/mbedmicro/mbed/builds)
+
+The mbed Software Development Kit (SDK) is a C/C++ microcontroller software platform relied upon by tens of thousands of
+developers to build projects fast.
+
+The SDK is licensed under the permissive Apache 2.0 licence, so you can use it in both commercial and personal projects
+with confidence.
+
+The mbed SDK has been designed to provide enough hardware abstraction to be intuitive and concise, yet powerful enough
+to build complex projects. It is built on the low-level ARM CMSIS APIs, allowing you to code down to the metal if needed.
+In addition to RTOS, USB and Networking libraries, a cookbook of hundreds of reusable peripheral and module libraries
+have been built on top of the SDK by the mbed Developer Community.
+
+Documentation
+-------------
+* [Tools](http://developer.mbed.org/handbook/mbed-tools): how to setup and use the build system.
+* [mbed library internals](http://developer.mbed.org/handbook/mbed-library-internals)
+* [Adding a new target microcontroller](http://developer.mbed.org/handbook/mbed-SDK-porting)
+
+Supported Microcontrollers and Boards
+-------------------------------------
+View all on the [mbed Platforms](https://developer.mbed.org/platforms/) page.
+
+NXP:
+* [mbed LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) (Cortex-M3)
+* [u-blox C027 LPC1768](http://developer.mbed.org/platforms/u-blox-C027/) (Cortex-M3)
+* [mbed LPC11U24](http://developer.mbed.org/platforms/mbed-LPC11U24/) (Cortex-M0)
+* [EA LPC11U35](http://developer.mbed.org/platforms/EA-LPC11U35/) (Cortex-M0)
+* mbed LPC2368 (ARM7TDMI-S)
+* LPC810 (Cortex-M0+)
+* [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
+* [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)
+* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F)
+* LPC4330 (Cortex-M4F + Cortex-M0)
+* [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
+* [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0)
+* LPC11C24 (Cortex-M0)
+* [LPC1549](https://developer.mbed.org/platforms/LPCXpresso1549/) (Cortex-M3)
+* [LPC800-MAX](https://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
+* [DipCortex-M0](https://developer.mbed.org/platforms/DipCortex-M0/) (Cortex-M0)
+* [DipCortex-M3](https://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
+* [BlueBoard-LPC11U24](https://developer.mbed.org/platforms/BlueBoard-LPC11U24/) (Cortex-M0)
+* LPCCAPPUCCINO (Cortex-M0)
+* [Arch](https://developer.mbed.org/platforms/Seeeduino-Arch/) (Cortex-M0)
+* [Arch GPRS](https://developer.mbed.org/platforms/Seeed-Arch-GPRS/) (Cortex-M0)
+* [Arch Pro](https://developer.mbed.org/platforms/Seeeduino-Arch-Pro/) (Cortex-M3)
+
+Freescale:
+* [FRDM-KL05Z](https://developer.mbed.org/platforms/FRDM-KL05Z/) (Cortex-M0+)
+* [FRDM-KL25Z](http://developer.mbed.org/platforms/KL25Z/) (Cortex-M0+)
+* FRDM-KL43Z (Cortex-M0+)
+* [FRDM-KL46Z](https://developer.mbed.org/platforms/FRDM-KL46Z/) (Cortex-M0+)
+* [FRDM-K20D50M](https://developer.mbed.org/platforms/FRDM-K20D50M/) (Cortex-M4)
+* [FRDM-K22F](https://developer.mbed.org/platforms/FRDM-K22F/) (Cortex-M4F)
+* [FRDM-K64F](https://developer.mbed.org/platforms/FRDM-K64F/) (Cortex-M4F)
+
+STMicroelectronics:
+* [Nucleo-F030R8](https://developer.mbed.org/platforms/ST-Nucleo-F030R8/) (Cortex-M0)
+* [Nucleo-F072RB](https://developer.mbed.org/platforms/ST-Nucleo-F072RB/) (Cortex-M0)
+* [Nucleo-L053R8](https://developer.mbed.org/platforms/ST-Nucleo-L053R8/) (Cortex-M0+)
+* [Nucleo-F103RB](https://developer.mbed.org/platforms/ST-Nucleo-F103RB/) (Cortex-M3)
+* [Nucleo-L152RE](https://developer.mbed.org/platforms/ST-Nucleo-L152RE/) (Cortex-M3)
+* [Nucleo-F302R8](https://developer.mbed.org/platforms/ST-Nucleo-F302R8/) (Cortex-M4F)
+* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
+* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
+* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
+* STM32F4XX (Cortex-M4F)
+* STM32F3XX (Cortex-M4F)
+* STM32F0-Discovery (Cortex-M0)
+* STM32VL-Discovery (Cortex-M3)
+* STM32F3-Discovery (Cortex-M4F)
+* STM32F4-Discovery (Cortex-M4F)
+* STM32F429-Discovery (Cortex-M4F)
+* STM32L0-Discovery (Cortex-M0+)
+* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)
+
+
+Nordic:
+* [nRF51822-mKIT](https://developer.mbed.org/platforms/Nordic-nRF51822/) (Cortex-M0)
+* [Arch BLE](https://developer.mbed.org/platforms/Seeed-Arch-BLE/) (Cortex-M0)
+
+Renesas:
+* [RZ-A1H](http://developer.mbed.org/platforms/Renesas-GR-PEACH/) (Cortex-A9)
+
+
+Supported Toolchains and IDEs
+-----------------------------
+* GCC ARM: [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded/4.7/4.7-2012-q4-major)
+* ARMCC (standard library and MicroLib): [uVision](http://www.keil.com/uvision/)
+* IAR: [IAR Embedded Workbench](http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/)
+* GCC code_red: [Red Suite](http://www.code-red-tech.com/)
+* GCC CodeSourcery: [Sourcery CodeBench](http://www.mentor.com/embedded-software/codesourcery)
+* GCC ARM: [Em::Blocks](http://www.emblocks.org/web/)
+* GCC ARM: [CooCox CoIDE](http://www.coocox.org/)
+
+API Documentation
+-----------------
+* [RTOS API](http://developer.mbed.org/handbook/RTOS)
+* [TCP/IP Socket API](http://developer.mbed.org/handbook/Socket) (Transports: Ethernet, WiFi, 3G)
+* [USB Device API](http://developer.mbed.org/handbook/USBDevice)
+* [USB Host API](http://developer.mbed.org/handbook/USBHost)
+* [DSP API](http://developer.mbed.org/users/mbed_official/code/mbed-dsp/docs/tip/)
+* Flash File Systems: [SD](http://developer.mbed.org/handbook/SDFileSystem), [USB MSD](http://developer.mbed.org/handbook/USBHostMSD), [semihosted](http://developer.mbed.org/handbook/LocalFileSystem)
+* [Peripheral Drivers API](http://developer.mbed.org/handbook/Homepage)
+
+Community
+---------
+For discussing the development of the mbed SDK itself (Addition/support of microcontrollers/toolchains, build and test system, Hardware Abstraction Layer API, etc) please join our [mbed-devel mailing list](https://groups.google.com/forum/?fromgroups#!forum/mbed-devel).
+
+For every topic regarding the use of the mbed SDK, rather than its development, please post on the [mbed.org forum](http://mbed.org/forum/), or the [mbed.org Q&A](http://mbed.org/questions/).
+
+For reporting issues in the mbed libraries please open a ticket on the issue tracker of the relevant [mbed official library](http://mbed.org/users/mbed_official/code/).
diff --git a/tool/mbed/mbed-sdk/docs/BUILDING.md b/tool/mbed/mbed-sdk/docs/BUILDING.md
new file mode 100644
index 000000000..243bea5cd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/docs/BUILDING.md
@@ -0,0 +1,601 @@
+# Mbed SDK build script environment
+## Introduction
+Mbed test framework allows users to test their mbed devices’ applications, build mbed SDK library, re-run tests, run mbed SDK regression, add new tests and get all this results automatically. Everything is done on your machine so you have a full control over compilation, and tests you run.
+
+It's is using Python 2.7 programming language to drive all tests so make sure Python 2.7 is installed on your system and included in your system PATH. To compile mbed SDK and tests you will need one or more supported compilers installed on your system.
+
+To follow this short introduction you should already:
+* Know what mbed SDK is in general.
+* Know how to install Python 2.7, ARM target cross compilers.
+* You have C/C++ programming experience and at least willingness to learn a bit about Python.
+
+## Test automation
+Currently our simple test framework allows users to run tests on their machines (hosts) in a fully automated manner. All you need to do is to prepare two configuration files.
+
+## Test automation limitations
+Note that for tests which require connected external peripherals, for example Ethernet, SD flash cards, external EEPROM tests, loops etc. you need to:
+
+* Modify test source code to match components' pin names to actual mbed board pins where peripheral is connected or
+* Wire your board the same way test defines it.
+
+## Prerequisites
+mbed test suite and build scripts are Python 2.7 applications and require Python 2.7 runtime environment and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) to install dependencies.
+
+What we need:
+* Installed [Python 2.7](https://www.python.org/download/releases/2.7) programming language.
+* Installed [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install)
+* Optionally you can install [pip](https://pip.pypa.io/en/latest/installing.html) which is the PyPA recommended tool for installing Python packages from command line.
+
+mbed SDK in its repo root directory specifies ```setup.py``` file which holds information about all packages which are dependencies for it. Bear in mind only few simple steps are required to install all dependencies.
+
+First, clone mbed SDK repo and go to mbed SDk repo's directory:
+```
+$ git clone https://github.com/mbedmicro/mbed.git
+$ cd mbed
+```
+
+Second, invoke ```setup.py``` so ```setuptools``` can install mbed SDK's dependencies (external Python modules required by mbed SDK):
+```
+$ python setup.py install
+```
+or
+```
+$ sudo python setup.py install
+```
+when your system requires administrator rights to install new Python packages.
+
+## Prerequisites (manual Python package dependency installation)
+**Please only read this chapter if you had problems installing mbed SDK dependencies to Python packages**.
+
+Below you can find the list of mbed SDK dependencies to Python modules with instructions how to install them manually.
+
+You can skip this part if you've already install [Python 2.7](https://www.python.org/download/releases/2.7) and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) and successfully [installed all dependencies](#prerequisites).
+
+* Please make sure you've installed [pip](https://pip.pypa.io/en/latest/installing.html) or [easy_install](https://pythonhosted.org/setuptools/easy_install.html#installing-easy-install)
+Note: Easy Install is a python module (easy_install) bundled with [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install) that lets you automatically download, build, install, and manage Python packages.
+
+* Installed [pySerial](https://pypi.python.org/pypi/pyserial) module for Python 2.7.
+pySerial can be installed from PyPI, either manually downloading the files and installing as described below or using:
+```
+$ pip install pyserial
+```
+or:
+```
+easy_install -U pyserial
+```
+* Installed [prettytable](https://code.google.com/p/prettytable/wiki/Installation) module for Python 2.7.
+prettytable can be installed from PyPI, either manually downloading the files and installing as described below or using:
+```
+$ pip install prettytable
+```
+* Installed [IntelHex](https://pypi.python.org/pypi/IntelHex) module.
+IntelHex may be downloaded from https://launchpad.net/intelhex/+download or http://www.bialix.com/intelhex/.
+Assuming Python is properly installed on your platform, installation should just require running the following command from the root directory of the archive:
+```
+sudo python setup.py install
+```
+This will install the intelhex package into your system’s site-packages directory. After that is done, any other Python scripts or modules should be able to import the package using:
+```
+$ python
+Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32
+Type "help", "copyright", "credits" or "license" for more information.
+>>> from intelhex import IntelHex
+>>>
+```
+* You can check if you have correctly installed the above modules (or you already have them) by starting Python and importing both modules.
+```
+$ python
+Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32
+Type "help", "copyright", "credits" or "license" for more information.
+>>> import serial
+>>> import prettytable
+>>> from intelhex import IntelHex
+>>>
+```
+* Installed Git open source distributed version control system.
+* Installed at least one of the supported by Mbed SDK workspace tools compilers:
+
+Compiler | Mbed SDK Abbreviation | Example Version
+-----------------------|-----------------------|-----------
+Keil ARM Compiler | ARM, uARM | ARM C/C++ Compiler, 5.03 [Build 117]
+GCC ARM | GCC_ARM | gcc version 4.8.3 20131129 (release)
+GCC CodeSourcery | GCC_CS | gcc version 4.8.1 (Sourcery CodeBench Lite 2013.11-24)
+GCC CodeRed | GCC_CR | gcc version 4.6.2 20121016 (release)
+IAR Embedded Workbench | IAR | IAR ANSI C/C++ Compiler V6.70.1.5641/W32 for ARM
+
+* Mbed board. You can find list of supported platforms [here](https://mbed.org/platforms/).
+
+### Getting Mbed SDK sources with test suite
+So you have already installed Python (with required modules) together with at least one supported compiler you will use with your mbed board. Great!
+
+Now let's go further and try to get Mbed SDK with test suite together. So let's clone latest Mbed SDK source code and configure path to our compiler(s) in next few steps.
+
+* Open console and run command below to clone Mbed SDK repository hosted on [Github](https://github.com/mbedmicro/mbed).
+```
+$ git clone https://github.com/mbedmicro/mbed.git
+Cloning into 'mbed'...
+remote: Counting objects: 37221, done.
+remote: Compressing objects: 100% (3/3), done.
+remote: Total 37221 (delta 0), reused 0 (delta 0), pack-reused 37218
+Receiving objects: 100% (37221/37221), 20.38 MiB | 511.00 KiB/s, done.
+Resolving deltas: 100% (24455/24455), done.
+Checking connectivity... done.
+Checking out files: 100% (3994/3994), done.
+```
+* Now you can go to mbed directory you've just cloned and you can see root directory structure of our Mbed SDK library sources. Just type following commands:
+```
+$ cd mbed
+$ ls
+LICENSE MANIFEST.in README.md libraries setup.py travis workspace_tools
+```
+Directory structure we are interested in:
+```
+ mbed/workspace_tools/ - test suite scripts, build scripts etc.
+ mbed/library/tests/ - mbed SDK tests,
+ mbed/library/tests/mbed/ - tests for mbed SDK and peripherals tests,
+ mbed/library/tests/net/echo/ - tests for Ethernet interface,
+ mbed/library/tests/rtos/mbed/ - tests for RTOS.
+```
+
+### Workspace tools
+Workspace tools are set of Python scripts used off-line by Mbed SDK team to:
+* Compile and build mbed SDK,
+* Compile and build libraries included in mbed SDK repo like e.g. ETH (Ethernet), USB, RTOS or CMSIS,
+* Compile, build and run mbed SDK tests,
+* Run test regression locally and in CI server,
+* Get library, target, test configuration (paths, parameters, names etc.).
+
+### Configure workspace tools to work with your compilers
+Before we can run our first test we need to configure our test environment a little!
+Now we need to tell workspace tools where our compilers are.
+
+* Please to go ```mbed/workspace_tools/``` directory and create empty file called ```private_settings.py```.
+```
+$ touch private_settings.py
+```
+* Populate this file the Python code below:
+```python
+from os.path import join
+
+# ARMCC
+ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows"
+ARM_BIN = join(ARM_PATH, "bin")
+ARM_INC = join(ARM_PATH, "include")
+ARM_LIB = join(ARM_PATH, "lib")
+
+ARM_CPPLIB = join(ARM_LIB, "cpplib")
+MY_ARM_CLIB = join(ARM_PATH, "lib", "microlib")
+
+# GCC ARM
+GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin"
+
+# GCC CodeSourcery
+GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# GCC CodeRed
+GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin"
+
+# IAR
+IAR_PATH = "C:/Work/toolchains/iar_6_5/arm"
+
+SERVER_ADDRESS = "127.0.0.1"
+LOCALHOST = "127.0.0.1"
+
+# This is moved to separate JSON configuration file used by singletest.py
+MUTs = {
+}
+```
+
+Note: You need to provide the absolute path to your compiler(s) installed on your host machine. Replace corresponding variable values with paths to compilers installed in your system:
+* ```ARM_PATH``` for armcc compiler.
+* ```GCC_ARM_PATH``` for GCC ARM compiler.
+* ```GCC_CS_PATH``` for GCC CodeSourcery compiler.
+* ```GCC_CR_PATH``` for GCC CodeRed compiler.
+* ```IAR_PATH``` for IAR compiler.
+
+If for example you do not use ```IAR``` compiler you do not have to modify anything. Workspace tools will use ```IAR_PATH`` variable only if you explicit ask for it from command line. So do not worry and replace only paths for your installed compilers.
+
+Note: Because this is a Python script and ```ARM_PATH```, ```GCC_ARM_PATH```, ```GCC_CS_PATH```, ```GCC_CR_PATH```, ```IAR_PATH``` are Python string variables please use double backlash or single slash as path's directories delimiter to avoid incorrect path format. For example:
+```python
+ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows"
+GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin"
+GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin"
+IAR_PATH = "C:/Work/toolchains/iar_6_5/arm"
+```
+
+Note: Settings in ```private_settings.py``` will overwrite variables with default values in ```mbed/workspace_tools/settings.py``` file.
+
+## Build Mbed SDK library from sources
+Let's build mbed SDK library off-line from sources using your compiler. We've already cloned mbed SDK sources, we've also installed compilers and added their paths to ```private_settings.py```.
+We now should be ready to use workspace tools script ```build.py``` to compile and build mbed SDK from sources.
+
+We are still using console. You should be already in ```mbed/workspace_tools/``` directory if not go to ```mbed/workspace_tools/``` and type below command:
+```
+$ python build.py -m LPC1768 -t ARM
+```
+or if you want to take advantage from multi-threaded compilation please use option ```-j X``` where ```X``` is number of cores you want to use to compile mbed SDK. See below:
+```
+$ python build.py -m LPC1768 -t ARM -j 4
+Building library CMSIS (LPC1768, ARM)
+Copy: core_ca9.h
+Copy: core_caFunc.h
+...
+Compile: us_ticker_api.c
+Compile: wait_api.c
+Library: mbed.ar
+Creating archive 'C:\temp\x\mbed\build\mbed\TARGET_LPC1768\TOOLCHAIN_ARM_STD\mbed.ar'
+Copy: board.o
+Copy: retarget.o
+
+Completed in: (42.58)s
+
+Build successes:
+ * ARM::LPC1768
+```
+Above command will build mbed SDK for [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) platform using ARM compiler.
+
+Let's have a look at directory structure under ```mbed/build/```. We can see for ```LPC1768``` new directory ```TARGET_LPC1768``` was created. This directory contains all build primitives.
+Directory ```mbed/TARGET_LPC1768/TOOLCHAIN_ARM_STD/``` conteins mbed SDK library ```mbed.ar```. This directory structure also stores all needed headers which you should use with ```mbed.ar``` when building your own software.
+```
+$ tree ./mbed/build/
+Folder PATH listing
+Volume serial number is 006C006F 6243:3EA9
+./MBED/BUILD
++---mbed
+ +---.temp
+ ¦ +---TARGET_LPC1768
+ ¦ +---TOOLCHAIN_ARM_STD
+ ¦ +---TARGET_NXP
+ ¦ +---TARGET_LPC176X
+ ¦ +---TOOLCHAIN_ARM_STD
+ +---TARGET_LPC1768
+ +---TARGET_NXP
+ ¦ +---TARGET_LPC176X
+ ¦ +---TARGET_MBED_LPC1768
+ +---TOOLCHAIN_ARM_STD
+```
+
+Note: Why ```LCP1768```? For this example we are using ```LPC1768``` because this platform supports all compilers so you are sure you only need to specify proper compiler.
+
+If you are not using ARM Compiler replace ```ARM``` with your compiler nickname: ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` or ```IAR```. For example if you are using IAR type command:
+```
+$ python build.py -m LPC1768 -t IAR
+```
+
+Note: Workspace tools track changes in source code. So if for example mbed SDK or test source code changes ```build.py``` script will recompile project with all dependencies. If there are no changes in code consecutive mbed SDK re-builds using build.py will not rebuild project if this is not necessary. Try to run last command once again, we can see script ```build.py``` will not recompile project (there are no changes):
+```
+$ python build.py -m LPC1768 -t ARM
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+
+Completed in: (0.15)s
+
+Build successes:
+ * ARM::LPC1768
+```
+
+### build.py script
+
+Build script located in mbed/workspace_tools/ is our core script solution to drive compilation, linking and building process for:
+
+* mbed SDK (with libs like Ethernet, RTOS, USB, USB host).
+* Tests which also can be linked with libraries like RTOS or Ethernet.
+
+Note: Test suite also uses the same build script, inheriting the same properties like auto dependency tracking and project rebuild in case of source code changes.
+
+Build.py script is a powerful tool to build mbed SDK for all available platforms using all supported by mbed cross-compilers. Script is using our workspace tools build API to create desired platform-compiler builds. Use script option ```--h``` (help) to check all script parameters.
+```
+$ python build.py --help
+```
+
+* The command line parameter ```-m``` specifies the MCUs/platforms for which you want to build the mbed SDK. More than one MCU(s)/platform(s) may be specified with this parameter using comma as delimiter.
+Example for one platform build:
+```
+$ python build.py -m LPC1768 -t ARM
+```
+or for many platforms:
+```
+$ python build.py -m LPC1768,NUCLEO_L152RE -t ARM
+```
+
+* Parameter ```-t``` defined which toolchain should be used for mbed SDK build. You can build Mbed SDK for multiple toolchains using one command.
+Below example (note there is no space after commas) will compile mbed SDK for Freescale Freedom KL25Z platform using ARM and GCC_ARM compilers:
+```
+$ python build.py -m KL25Z -t ARM,GCC_ARM
+```
+
+* You can combine this technique to compile multiple targets with multiple compilers.
+Below example will compile mbed SDK for Freescale's KL25Z and KL46Z platforms using ARM and GCC_ARM compilers:
+```
+$ python build.py -m KL25Z,KL46Z -t ARM,GCC_ARM
+```
+
+* Building libraries included in mbed SDK's source code. Parameters ```-r```, ```-e```, ```-u```, ```-U```, ```-d```, ```-b``` will add ```RTOS```, ```Ethernet```, ```USB```, ```USB Host```, ```DSP```, ```U-Blox``` libraries respectively.
+Below example will build Mbed SDK library for for NXP LPC1768 platform together with RTOS (```-r``` switch) and Ethernet (```-e``` switch) libraries.
+```
+$ python build.py -m LPC1768 -t ARM -r -e
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+Building library RTX (LPC1768, ARM)
+Building library RTOS (LPC1768, ARM)
+Building library ETH (LPC1768, ARM)
+
+Completed in: (0.48)s
+
+Build successes:
+ * ARM::LPC1768
+```
+
+* If you’re unsure which platforms and toolchains are supported please use switch ```-S``` to print simple matrix of platform to compiler dependencies.
+```
+$ python python build.py -S
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| APPNEARME_MICRONFCBOARD | Supported | Default | Supported | - | - | - | - | - |
+| ARCH_BLE | Default | - | Supported | Supported | - | - | - | - |
+| ARCH_GPRS | Supported | Default | Supported | Supported | Supported | - | - | - |
+...
+| UBLOX_C029 | Supported | Default | Supported | Supported | - | - | - | - |
+| WALLBOT_BLE | Default | - | Supported | Supported | - | - | - | - |
+| XADOW_M0 | Supported | Default | Supported | Supported | Supported | - | - | - |
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 90
+Total permutations: 297
+```
+
+Above list can be overwhelming so please do not hesitate to use switch ```-f``` to filter ```Platform``` column.
+```
+$ python build.py -S -f ^K
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+| K20D50M | Default | - | Supported | Supported | - | - | - | - |
+| K22F | Default | - | Supported | Supported | - | - | - | - |
+| K64F | Default | - | Supported | Supported | - | - | - | - |
+| KL05Z | Supported | Default | Supported | Supported | - | - | - | - |
+| KL25Z | Default | - | Supported | Supported | - | - | Supported | Supported |
+| KL43Z | Default | - | Supported | - | - | - | - | - |
+| KL46Z | Default | - | Supported | Supported | - | - | - | - |
+| NRF51_DK | Default | - | Supported | Supported | - | - | - | - |
+| NRF51_DK_OTA | Default | - | Supported | - | - | - | - | - |
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 9
+Total permutations: 28
+```
+or just give platform name:
+```
+$ python build.py -S -f LPC1768
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| LPC1768 | Default | Supported | Supported | Supported | Supported | Supported | - | - |
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 1
+Total permutations: 6
+```
+
+* You can be more verbose ```-v``` especially if you want to see each compilation / linking command build.py is executing:
+```
+$ python build.py -t GCC_ARM -m LPC1768 -j 8 -v
+Building library CMSIS (LPC1768, GCC_ARM)
+Copy: LPC1768.ld
+Compile: startup_LPC17xx.s
+[DEBUG] Command: C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin\arm-none-eabi-gcc
+-x assembler-with-cpp -c -Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers
+-fmessage-length=0 -fno-exceptions -fno-builtin -ffunction-sections -fdata-sections -MMD
+-fno-delete-null-pointer-checks -fomit-frame-pointer -mcpu=cortex-m3 -mthumb -O2
+-DTARGET_LPC1768 -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_NXP -DTARGET_LPC176X
+-DTARGET_MBED_LPC1768 -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3
+-DMBED_BUILD_TIMESTAMP=1424903604.77 -D__MBED__=1 -IC:\Work\mbed\libraries\mbed\targets\cmsis
+-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP
+-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X -IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM
+-o C:\Work\mbed\build\mbed\.temp\TARGET_LPC1768\TOOLCHAIN_GCC_ARM\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.o
+C:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.s
+[DEBUG] Return: 0
+...
+```
+
+## CppUCheck analysis
+[Cppcheck](http://cppcheck.sourceforge.net/) is a static analysis tool for C/C++ code. Unlike C/C++ compilers and many other analysis tools it does not detect syntax errors in the code. Cppcheck primarily detects the types of bugs that the compilers normally do not detect. The goal is to detect only real errors in the code (i.e. have zero false positives).
+
+Prerequisites:
+* Please install ```CppCheck``` on your system before you want to use it with build scripts.
+* You should also add Cppcheck to your system path.
+
+```build.py``` script supports switching between compilation and building and just static code analysis testing. You can use switch ```--cppcheck``` to perform CppCheck static code analysis.
+
+* When you are using --cppcheck switch all macros, toolchain dependencies etc. are preserved so you are sure you are checking exactly the same code you would compile for your application.
+
+* Cppcheck analysis can take up to few minutes on slower machines.
+
+* Usually you will use switches ```-t``` and ```-m``` to define toolchain and MCU (platform) respectively. You should do the same in case of CppCheck analysis. Please note that build script can also compile and build RTOS, Ethernet library etc. If you want to check those just use corresponding build script switches (e.g. ```-r```, ```-e```, ...).
+
+Example:
+```
+$ python build.py -t uARM -m NUCLEO_F334R8 --cppcheck
+```
+
+# make.py script
+```make.pt``` is a ```mbed/workspace_tools/``` script used to build tests (we call them sometimes 'programs') one by one manually. Script allows you to flash board with test and execute it. This is deprecated functionality and will not be described here. Instead please use ```singletest.py``` file to build mbed SDK, tests and run automation for test cases included in ```mbedmicro/mbed```.
+Note: ```make.py``` script depends on existing already built mked SDK and library sources so you need to pre-build mbed SDK and for example RTOS library to link 'program' (test) with mebd SDK and RTOS library. To pre-build mbed SDK please use ```build.py``` script.
+
+Just for sake of example please see few ways to use ```make.py``` together with Freedom K64F board.
+
+* We need to build mbed SDK (in directory ```mbed/build/```:
+```
+$ python build.py -t GCC_ARM -m K64F -j 8
+Building library CMSIS (K64F, GCC_ARM)
+Building library MBED (K64F, GCC_ARM)
+
+Completed in: (0.59)s
+
+Build successes:
+ * GCC_ARM::K64F
+```
+* We can print all 'programs' (test cases) ```make.py``` can build for us:
+```
+$ python make.py
+.
+[ 0] MBED_A1: Basic
+[ 1] MBED_A2: Semihost file system
+[ 2] MBED_A3: C++ STL
+[ 3] MBED_A4: I2C TMP102
+.
+```
+For example 'program' under index ```2``` is ```MBED_A3``` test case we can build and flash onto K64F board.
+* Building test with ```make.py``` by specifying test case name with ```-n``` option:
+```
+$ python make.py -t GCC_ARM -m K64F -n MBED_A3
+Building project STL (K64F, GCC_ARM)
+Compile: main.cpp
+[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings]
+.
+.
+.
+[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings]
+Compile: test_env.cpp
+Link: stl
+Elf2Bin: stl
+Image: C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin
+```
+Because we previously have built mbed SDK we are now able to drive test case compilation and linking with mbed SDK and produce ```MBED_A3``` test case binary in build directory:
+```
+C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin
+```
+
+For more help type ```$ python make.py --help``` in your command line.
+
+# project.py script
+```project.py``` script is used to export test cases ('programs') from test case portfolio to off-line IDE. This is a easy way to export test project to IDEs such as:
+* codesourcery.
+* coide.
+* ds5_5.
+* emblocks.
+* gcc_arm.
+* iar.
+* kds.
+* lpcxpresso.
+* uvision.
+
+You can export project using command line. All you need to do is to specify mbed platform name (option ```-m```), your IDE (option ```-i```) and project name you want to export (option ```-n``` or (option ```-p```).
+
+In below example we export our project so we can work on it using GCC ARM cross-compiler. Building mechanism used to drive exported build will be ```Make```.
+```
+$ python project.py -m K64F -n MBED_A3 -i gcc_arm
+Copy: test_env.h
+Copy: AnalogIn.h
+Copy: AnalogOut.h
+.
+.
+.
+Copy: K64FN1M0xxx12.ld
+Copy: main.cpp
+
+Successful exports:
+ * K64F::gcc_arm C:\Work\mbed\build\export\MBED_A3_gcc_arm_K64F.zip
+```
+You can see exporter placed compressed project export in ```zip``` file in ```mbed/build/export/``` directory.
+
+Example export file ```MBED_A3_gcc_arm_K64F.zip``` structure:
+```
+MBED_A3
+├───env
+└───mbed
+ ├───api
+ ├───common
+ ├───hal
+ └───targets
+ ├───cmsis
+ │ └───TARGET_Freescale
+ │ └───TARGET_MCU_K64F
+ │ └───TOOLCHAIN_GCC_ARM
+ └───hal
+ └───TARGET_Freescale
+ └───TARGET_KPSDK_MCUS
+ ├───TARGET_KPSDK_CODE
+ │ ├───common
+ │ │ └───phyksz8081
+ │ ├───drivers
+ │ │ ├───clock
+ │ │ ├───enet
+ │ │ │ └───src
+ │ │ ├───interrupt
+ │ │ └───pit
+ │ │ ├───common
+ │ │ └───src
+ │ ├───hal
+ │ │ ├───adc
+ │ │ ├───can
+ │ │ ├───dac
+ │ │ ├───dmamux
+ │ │ ├───dspi
+ │ │ ├───edma
+ │ │ ├───enet
+ │ │ ├───flextimer
+ │ │ ├───gpio
+ │ │ ├───i2c
+ │ │ ├───llwu
+ │ │ ├───lptmr
+ │ │ ├───lpuart
+ │ │ ├───mcg
+ │ │ ├───mpu
+ │ │ ├───osc
+ │ │ ├───pdb
+ │ │ ├───pit
+ │ │ ├───pmc
+ │ │ ├───port
+ │ │ ├───rcm
+ │ │ ├───rtc
+ │ │ ├───sai
+ │ │ ├───sdhc
+ │ │ ├───sim
+ │ │ ├───smc
+ │ │ ├───uart
+ │ │ └───wdog
+ │ └───utilities
+ │ └───src
+ └───TARGET_MCU_K64F
+ ├───device
+ │ ├───device
+ │ │ └───MK64F12
+ │ └───MK64F12
+ ├───MK64F12
+ └───TARGET_FRDM
+```
+
+After unpacking exporter ```zip``` file we can go to directory and see files inside MBED_A3 directory:
+```
+$ ls
+GettingStarted.htm Makefile env main.cpp mbed
+```
+Exporter generated for us ```Makefile``` so now we can build our software:
+```
+$ make -j 8
+.
+.
+.
+ text data bss dec hex filename
+ 29336 184 336 29856 74a0 MBED_A3.elf
+```
+
+We can see root directory of exporter project is now populated with binary files:
+* MBED_A3.bin.
+* MBED_A3.elf .
+* MBED_A3.hex.
+You have also map file ```MBED_A3.map``` for your disposal.
+```
+$ ls
+GettingStarted.htm MBED_A3.bin MBED_A3.elf MBED_A3.hex MBED_A3.map Makefile env main.cpp main.d main.o mbed
+```
+
diff --git a/tool/mbed/mbed-sdk/docs/COMMITTERS.md b/tool/mbed/mbed-sdk/docs/COMMITTERS.md
new file mode 100644
index 000000000..ecb092dad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/docs/COMMITTERS.md
@@ -0,0 +1,269 @@
+# Committing changes to mbedmicro/mbed
+* Our current branching model is very simple. We are using ```master``` branch to merge all pull requests.
+* Based on stable ```SHA``` version of ```master``` branch we decide to release and att he same time ```tag``` our build release.
+* Our current release versioning follows simple integer version: ```94```, ```95```, ```96``` etc.
+
+# Committer Guide
+
+## How to decide what release(s) should be patched
+This section provides a guide to help a committer decide the specific base branch that a change set should be merged into.
+
+Currently our default branch is ```master``` branch. All pull requests should be created against ```master``` branch.
+mbed SDK is released currently on master branch under certain tag name (see [Git tagging basics]( http://git-scm.com/book/en/v2/Git-Basics-Tagging)). You can see mbed SDK tags and switch between them to for example go back to previous mbed SDK release.
+```
+$ git tag
+```
+
+Please note: mebd SDK ```master``` branch's ```HEAD``` is our latest code and may not be as stable as you expect. We are putting our best effort to run regression testing (in-house) against pull requests and latest code.
+Each commit to ```master``` will trigger [GitHub's Travis Continuous Integration](https://travis-ci.org/mbedmicro/mbed/builds).
+
+### Pull request
+Please send pull requests with changes which are:
+* Complete (your code will compile and perform as expected).
+* Tested on hardware.
+ * You can use included mbed SDK test suite to perform testing. See TESTING.md.
+ * If your change, feature do not have a test case included please add one (or more) to cover new functionality.
+ * If you can't test your functionality describe why.
+* Documented source code:
+ * New, modified functions have descriptive comments.
+ * You follow coding rules and styles provided by mbed SDK project.
+* Documented pull request description:
+ * Description of changes is added - explain your change / enhancement.
+ * References to existing issues, other pull requests or forum discussions are included.
+ * Test results are added.
+
+After you send us your pull request our Gate Keeper will change the state of pull request to:
+• ``` enhancement``` or ```bug``` when pull request creates new improvement or fixed issue.
+Than we will set for you labels:
+• ```review``` to let you know your pull request is under review and you can expect review related comments from us.
+• ```in progress``` when you pull request requires some additional change which will for now block this pull request from merging.
+At the end we will remove ```review``` label and merge your change if everything goes well.
+
+## C++ coding rules & coding guidelines
+### Rules
+* The mbed SDK code follows K&R style (Reference: [K&R style](http://en.wikipedia.org/wiki/Indent_style#K.26R_style)) with at least 2 exceptions which can be found in the list below the code snippet:
+
+```c++
+static const PinMap PinMap_ADC[] = {
+ {PTC2, ADC0_SE4b, 0},
+ {NC , NC , 0}
+};
+
+uint32_t adc_function(analogin_t *obj, uint32_t options)
+{
+ uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+ switch (options) {
+ case 1:
+ timeout = 6;
+ break;
+ default:
+ timeout = 10;
+ break;
+ }
+
+ while (!adc_hal_is_conversion_completed(instance, 0)) {
+ if (timeout == 0) {
+ break;
+ } else {
+ timeout--;
+ }
+ }
+
+ if (obj->adc == ADC_CHANNEL0) {
+ adc_measure_channel(instance);
+ adc_stop_channel(instance);
+ } else {
+ error("channel not available");
+ }
+
+#if DEBUG
+ for (uint32_t i = 0; i < 10; i++) {
+ printf("Loop : %d", i);
+ }
+#endif
+ return adc_hal_get_conversion_value(instance, 0);
+}
+```
+* Indentation - 4 spaces. Please do not use tabs!
+* Braces - K&R, except for functions where the opening brace is on the new line.
+* 1 TBS - use braces for statements ```if```, ```else```, ```while```, ```for``` (exception from K&R) Reference: [1TBS](http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS)).
+* One line per statement.
+* Preprocessor macro starts at the beginning of a new line, the code inside is indented accordingly the code above it.
+* Cases within switch are indented (exception from K&R).
+* Space after statements if, while, for, switch, same applies to binary and ternary operators.
+* Each line has preferably at most 120 characters.
+* For pointers, ```*``` is adjacent to a name (analogin_t *obj).
+* Don't leave trailing spaces at the end of lines.
+* Empty lines should have no trailing spaces.
+* Unix line endings are default option for files.
+* Use capital letters for macros.
+* A file should have an empty line at the end.
+and:
+* We are not using C++11 yet so do not write code compliant to this standard.
+* We are not using libraries like ```BOOST``` so please so not include any ```BOOST``` headers to your code.
+* C++ & templates: please take under consideration templates are not fully supported by cross-compilers. You may have difficulties compiling template code few cross-compilers so make sure your template code compilers for more than one compiler.
+
+### Naming conventions
+Classes:
+* Begins with a capital letter, and each word in it begins also with a capital letter (```AnalogIn```, ```BusInOut```).
+* Methods contain small letters, distinct words separated by underscore.
+* Private members starts with an underscore.
+
+User defined types (typedef):
+* Structures - suffix ```_t``` - to denote it is user defined type
+* Enumeration - the type name and values name - same naming convention as classes (e.g ```MyNewEnum```)
+
+Functions:
+* Contain lower case letters (as methods within classes)
+* Distinct words separated by underscore (```wait_ms```, ```read_u16```)
+* Please make sure that in your module all functions have unique prefix so when your module is compiled with other modules function names (and e.g. extern global variable names) are not in naming conflict.
+
+Example code look&feel:
+```c++
+#define ADC_INSTANCE_SHIFT 8
+
+class AnalogIn {
+public:
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ AnalogIn(PinName pin) {
+ analogin_init(&_adc, pin);
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns
+ * A floating-point value representing the current input voltage, measured as a percentage
+ */
+ uint32_t read() {
+ return analogin_read(&_adc, operation);
+ }
+
+protected:
+ analogin_t _adc;
+};
+
+typedef enum {
+ ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0,
+} ADCName;
+
+struct analogin_s {
+ ADCName adc;
+};
+
+typedef struct analogin_s analogin_t;
+```
+### Doxygen documentation
+All functions / methods should contain a documentation using doxygen javadoc in a header file. More information regarding writing API Documentation, follow [this](https://mbed.org/handbook/API-Documentation) link.
+
+Example of well documentet code:
+```c++
+#ifndef ADC_H
+#define ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ADC Measurement method
+ *
+ * @param obj Pointer to the analogin object.
+ * @param options Options to be enabled by ADC peripheral.
+ *
+ * @returns
+ * Measurement value on defined ADC channel.
+ */
+uint32_t adc_function(analogin_t *obj, uint32_t options)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+```
+### C/C++ Source code indenter
+In Mbed project you can use AStyle (Reference: [Artistic Style](http://astyle.sourceforge.net/)) source code indenter to help you auto format your source code. It will for sure not correct all your coding styles but for sure will eliminate most of them. You can download AStyle from this location.
+
+Official Mbed SDK styles include below AStyle styles (defined by command line switched):
+```
+--style=kr --indent=spaces=4 --indent-switches
+```
+To format your file you can execute below command. Just replace ```$(FULL_CURRENT_PATH)``` with path to your source file.
+```
+$ astyle.exe --style=kr --indent=spaces=4 --indent-switches $(FULL_CURRENT_PATH)
+```
+
+## Python coding rules & coding guidelines
+Some of our tools in workspace_tools are written in ```Python 2.7```. In case of developing tools for python we prefer to keep similar code styles across all Python source code. Please note that not all rules must be enforced. For example we do not limit you to 80 characters per line, just be sure your code can fit to widescreen display.
+
+Please stay compatible with ```Python 2.7``` but nothing stops you to write your code so in the future it will by Python 3 friendly.
+
+Please check our Python source code (especially ```test_api.py``` and ```singletest.py```) to get notion of how your new code should look like). We know our code is not perfect but please try to fit the same coding style to existing code so source looks consistent and is not series of different flavors.
+
+Some general guidelines:
+* Use Python idioms, please refer to one of many on-line guidelines how to write Pythonic code: [Code Like a Pythonista: Idiomatic Python](http://python.net/~goodger/projects/pycon/2007/idiomatic/handout.html).
+* Please do not use TABs. Please use 4 spaces instead for indentations.
+* Please put space character between operators, after comma etc.
+* Please document your code, write comments and ```doc``` sections for each function or class you implement.
+
+### Static Code Analizers for Python
+If you are old-school developer for sure you remember tools like lint. "lint was the name originally given to a particular program that flagged some suspicious and non-portable constructs (likely to be bugs) in C language source code." Now lint-like programs are used to check similar code issues for multiple languages, also for Python. Please do use them if you want to commit new code to workspace_tools and other mbed SDK Python tooling.
+
+Below is the list Python lint tools you may want to use:
+
+* [pyflakes](https://pypi.python.org/pypi/pyflakes) - Please scan your code with pyflakes and remove all issues reported by it. If you are unsure if something should be modified or not you can skip lint report related fix and report this issue as possible additional commit in your pull request description.
+
+* [pylint](http://www.pylint.org/) - Please scan your code with pylint and check if there are any issues which can be resolved and are obvious "to fix" bugs. For example you may forgot to add 'self' as first parameter in class method parameter list or you are calling unknown functions / functions from not imported modules.
+
+* [pychecker](http://pychecker.sourceforge.net/) - optional, but more the merrier ;)
+
+Example Python look&feel:
+```python
+class HostRegistry:
+ """ Class stores registry with host tests and objects representing them
+ """
+ HOST_TESTS = {} # host_test_name -> host_test_ojbect
+
+ def register_host_test(self, ht_name, ht_object):
+ """ Registers (removes) host test by name from HOST_TESTS registry
+ if host test is not already registered (check by name).
+ """
+ if ht_name not in self.HOST_TESTS:
+ self.HOST_TESTS[ht_name] = ht_object
+
+ def unregister_host_test(self):
+ """ Unregisters (removes) host test by name from HOST_TESTS registry.
+ """
+ if ht_name in HOST_TESTS:
+ self.HOST_TESTS[ht_name] = None
+
+ def get_host_test(self, ht_name):
+ """ Returns HOST_TEST if host name is valid.
+ In case no host test is available return None
+ """
+ return self.HOST_TESTS[ht_name] if ht_name in self.HOST_TESTS else None
+
+ def is_host_test(self, ht_name):
+ """ Function returns True if host name is valid (is in HOST_TESTS)
+ """
+ return ht_name in self.HOST_TESTS
+```
+
+## Testing
+Please refer to TESTING.md document for detais regarding mbed SDK test suite and build scripts included in ```mbed/workspace_tools/```.
+
+## Before pull request checklist
+* Your pull request description section contains:
+ * Rationale – tell us why you submitted this pull request. This is your change to write us summary of your change.
+ * Description – describe changes you’ve made and tell us which new features / functionalities were implemented.
+ * Manual / Cookbook / Handbook – you can put here manual, cookbook or handbook related to your change / enhancement. Your documentation can stay with pull request.
+ * Test results (if applicable).
+* Make sure you followed project's coding rules and styles.
+* No dependencies are created to external C/C++ libraries which are not included already in our repository.
+* Please make sure that in your module all functions have unique prefix (no name space collisions).
+* You reused existing functionality, please do not add or rewrite existing code. E.g. use mbed’s ```FunctionPointer``` if possible to store your function pointers. Do not write another wrapper for it. We already got one. If some functionality is missing, just add it! Extend our APIs wisely!
+* Were you consistent? Please continue using style / code formatting, variables naming etc. in file they are modifying.
+* Your code compiles and links. Also doesn’t generate additional compilation warnings.
diff --git a/tool/mbed/mbed-sdk/docs/TESTING.md b/tool/mbed/mbed-sdk/docs/TESTING.md
new file mode 100644
index 000000000..9d17e4d90
--- /dev/null
+++ b/tool/mbed/mbed-sdk/docs/TESTING.md
@@ -0,0 +1,877 @@
+# Mbed SDK automated test suite
+## Introduction
+
+Test suit allows users to run locally on their machines Mbed SDK’s tests included in Mbed SDK repository. It also allows users to create their own tests and for example add new tests to test set as they progress with their project. If test is generic enough it could be included into official Mbed SDK test pool just do it via normal pull request!
+
+Each test is supervised by python script called “host test†which will at least Test suite is using build script API to compile and build test source together with required by test libraries like CMSIS, Mbed, Ethernet, USB etc.
+
+## What is host test?
+Test suite supports test supervisor concept. This concept is realized by separate Python script called ```host test```. Host tests can be found in ```mbed/workspace_tools/host_tests/``` directory. Note: In newer mbed versions (mbed OS) host tests will be separate library.
+
+Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner is test passed or failed. It all depends on test itself.
+
+In some cases host test can be TCP server echoing packets from test runner and judging packet loss. In other cases it can just check if values returned from accelerometer are actually valid (sane).
+
+## Test suite core: singletest.py script
+
+```singletest.py``` script located in ```mbed/workspace_tools/``` is a test suite script which allows users to compile, build tests and test runners (also supports CppUTest unit test library). Script also is responsible for test execution on devices selected by configuration files.
+
+### Parameters of singletest.py
+
+Test execution script ```singletest.py``` is a fairly powerful tool to run tests for mbed SDK platform. It is flexible and allows users to configure test execution process and define which mbed platforms will be tested.
+
+By specifying external configuration files (in JSON format) you can gain flexibility and prepare many different test scenarios. Just pass configuration file names to your script and run it.
+
+#### MUTs Specification
+You can easily configure your MUTs (Mbed Under Test) by creating configuration file with MUTs description.
+Note: This configuration file must be in [JSON format](http://www.w3schools.com/json/).
+Note: Unfortunately JSON format is not allowing you to have comments inside JSON code.
+
+Let’s see some example and let's try to configure small "test farm" with three devices connected to your host computer. In this example no peripherals (like SD card or EEPROM) are connected to our Mbed boards. We will use three platforms in this example:
+* [NXP LPC1768](https://mbed.org/platforms/mbed-LPC1768) board.
+* \[Freescale KL25Z](https://mbed.org/platforms/KL25Z) board and
+* [STMicro Nucleo F103RB](https://mbed.org/platforms/ST-Nucleo-F103RB) board.
+After connecting boards to our host machine (PC) we can check which serial ports and disks they occupy. For our example let's assume that:
+* ```LPC1768``` serial port is on ```COM4``` and disk drive is ```J:```.
+* ```KL25Z``` serial port is on ```COM39``` and disk drive is ```E:```.
+* ```NUCLEO_F103RB``` serial port is on ```COM11``` and disk drive is ```I:```.
+If you are working under Linux your port and disk could look like /dev/ttyACM5 and /media/usb5.
+
+This information is needed to create ```muts_all.json``` configuration file. You can create in in ```mbed/workspace_tools/``` directory:
+```
+$ touch muts_all.json
+```
+
+Its name will be passed to ```singletest.py``` script after ```-M``` (MUTs specification) switch. Let’s see how this file's content would look like in our example below:
+```json
+{
+ "1" : {"mcu": "LPC1768",
+ "port":"COM4",
+ "disk":"J:\\",
+ "peripherals": []
+ },
+
+ "2" : {"mcu": "KL25Z",
+ "port":"COM39",
+ "disk":"E:\\",
+ "peripherals": []
+ },
+
+ "3" : {"mcu": "NUCLEO_F103RB",
+ "port":"COM11",
+ "disk":"I:\\",
+ "peripherals": []
+ }
+}
+```
+
+Note: We will leave field ```peripherals``` empty for the sake of this example. We will explain it later. All you need to do now is to properly fill fields ```mcu```, ```port``` and ```disk```.
+
+Note: Please make sure files muts_all.json and test_spec.json are in workspace_tools/ directory. We will assume in this example they are.
+Where to find ```mcu``` names? You can use option ```-S``` of ```build.py``` script (in ```mbed/workspace_tools/``` directory) to check all supported off-line MCUs names.
+
+Note: If you update mbed device firmware or even disconnect / reconnect mbed device you may find that serial port / disk configuration changed. You need to update configuration file accordingly or you will face connection problems and obviously tests will not run.
+
+#### Peripherals testing
+When using MUTs configuration file (switch ```-M```) you can define in MUTs JSON file peripherals connected to your device:
+```json
+{
+ "1" : {"mcu" : "KL25Z",
+ "port" : "COM39",
+ "disk" : "E:\\",
+ "peripherals" : ["SD", "24LC256"]}
+}
+```
+You can force test suite to run only common tests (switch ```-C```) or only peripheral tests (switch ```-P```).
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -C
+```
+will not include tests for SD card and EEPROM 24LC256.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -P
+```
+will only run tests bind to SD card and EEPROM 24LC256.
+
+Note: option ```-P``` is useful for example in cases when you have same platform and different shields you want to test. No need to test common part all the time (timers, RTC, RTOS etc.). You can force to test peripherals only on some devices and for example only common tests on other devices.
+
+#### Additional MUTs configuration file settings
+You can add extra information to each MUT configuration. In particular you can specify which flashing (binary copy method) should be used, how to reset target and for example set reset timeout (used to delay test execution just after reset).
+
+muts_all.json:
+```json
+{
+ "1" : {"mcu" : "LPC1768",
+ "port" : "COM77",
+ "disk" : "G:\\",
+ "peripherals" : ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]},
+
+ "2" : {"mcu" : "KL25Z",
+ "port" : "COM89",
+ "disk" : "F:\\",
+ "peripherals" : ["SD", "24LC256", "KL25Z"],
+ "copy_method" : "copy",
+ "reset_type" : "default",
+ "reset_tout" : "2"},
+
+ "3" : {"mcu" : "LPC11U24",
+ "port" : "COM76",
+ "disk" : "E:\\",
+ "peripherals" : []}
+}
+```
+Please note that for MUT no. 2 few extra parameters were defined: ```copy_method```, ```reset_type``` and ```reset_tout```. Using this extra options you can tell test suite more about MUT you are using. This will allow you to be more flexible in terms of how you configure and use your MUTs.
+
+* ```copy_method``` - STRING - tells test suite which binary copy method should be used.
+You may notice that ```singletest.py``` command line help contains description about:
+ * Option ```-c``` (in MUTs file called ```copy_method```) with available copy methods supported by test suite plugin system.
+ * Option ```-r``` (in MUTs file called reset_type) with available reset methods supported by test suite plugin system.
+* ```reset_type``` - STRING - some boards may require special reset handling, for example vendor specific command must be executed to reset device.
+* ```reset_tout``` - INTEGER - extra timeout just after device is reseted. May be used to wait for few seconds so device may finish booting, flashing data internally etc.
+
+Part of help listing for singletest.py:
+```
+ -c COPY_METHOD, --copy-method=COPY_METHOD
+ Select binary copy (flash) method. Default is Python's
+ shutil.copy() method. Plugin support: copy, cp,
+ default, eACommander, eACommander-usb, xcopy
+ -r MUT_RESET_TYPE, --reset-type=MUT_RESET_TYPE
+ Extra reset method used to reset MUT by host test
+ script. Plugin support: default, eACommander,
+ eACommander-usb
+```
+
+----
+
+Now we've already defined how our devices are connected to our host PC. We can continue and define which of this MUTs will be tested and which compilers we will use to compile and build Mbed SDK and tests. To do so we need to create test specification file (let's call it ```test_spec.json```) and put inside our configuration file information about which MUTs we actually want to test. We will pass this file's name to ```singletest.py``` script using ```-i``` switch.
+
+Below we can see how sample ```test_spec.json``` file content could look like. (I've included all possible toolchains, we will change it in a moment):
+```json
+{
+ "targets": {
+ "LPC1768" : ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"],
+ "KL25Z" : ["ARM", "GCC_ARM"],
+ "NUCLEO_F103RB" : ["ARM", "uARM"]
+ }
+}
+```
+Above example configuration will force tests for LPC1768, KL25Z, NUCLEO_F103RB platforms and:
+
+* Compilers: ```ARM```, ```uARM```, ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` and ```IAR``` will be used to compile tests for NXP's ```LPC1768```.
+* Compilers: ```ARM``` and ```GCC_ARM``` will be used for Freescales' ```KL25Z``` platform.
+* Compilers: ```ARM``` and ```uARM``` will be used for STMicro's ```NUCLEO_F103RB``` platform.
+
+For our example purposes let's assume we only have Keil ARM compiler, so let's change configuration in ```test_spec.json``` file and reduce number of compiler to those we actually have:
+```json
+{
+ "targets": {
+ "LPC1768" : ["ARM", "uARM"],
+ "KL25Z" : ["ARM"],
+ "NUCLEO_F103RB" : ["ARM", "uARM"]
+ }
+}
+```
+#### Run your tests
+
+After you configure all your MUTs and compilers you are ready to run tests. Make sure your devices are connected and your configuration files reflect your current configuration (serial ports, devices). Go to workspace_tools directory in your mbed location.
+```
+$ cd workspace_tools/
+```
+and execute test suite script.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json
+```
+To check your configuration before test execution please use ```--config``` switch:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --config
+MUTs configuration in m.json:
++-------+-------------+---------------+------+-------+
+| index | peripherals | mcu | disk | port |
++-------+-------------+---------------+------+-------+
+| 1 | | LPC1768 | J:\ | COM4 |
+| 3 | | NUCLEO_F103RB | I:\ | COM11 |
+| 2 | | KL25Z | E:\ | COM39 |
++-------+-------------+---------------+------+-------+
+
+Test specification in t.json:
++---------------+-----+------+
+| mcu | ARM | uARM |
++---------------+-----+------+
+| NUCLEO_F103RB | Yes | Yes |
+| KL25Z | Yes | - |
+| LPC1768 | Yes | Yes |
++---------------+-----+------+
+```
+It should help you localize basic problems with configuration files and toolchain configuration.
+Note: Configurations with issues will be marked with ```*``` sign.
+
+Having multiple configuration files allows you to manage your test scenarios in more flexible manner. You can:
+
+* Set up all platforms and toolchains used during testing.
+* Define (using script's ```-n``` switch) which tests you want to run during testing.
+* Just run regression (all tests). Regression is default setting for test script.
+
+You can also force ```singletest.py``` script to:
+* Run only peripherals' tests (switch ```-P```) or
+* Just skip peripherals' tests (switch ```-C```).
+* Build mbed SDK, libraries and corresponding tests with multiple cores, just use ```-j X``` option where ```X``` is number of cores you want to use for compilation.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -j 8
+```
+* Print test cases console output using ```-V``` option.
+* Only build mbed SDK, tests and dependant libraries with switch ```-O```:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -j 8 -O
+```
+* Execute each test case multiple times with ```--global-loops X``` option, where ```X``` number of repeats. Additionally use option ```-W``` to continue repeating test cases execution only if they continue to fail.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --global-loops 3 -W
+```
+* Option ```--loops``` can be used to overwrite global loop count and redefine loop count for particular tests. Define test loops as ```TEST_ID=X``` where ```X``` is integer and separate loops count definitions by comma if necessary. E.g. ```TEST_1=5,TEST_2=20,TEST_3=2```.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json RTOS_1=10,RTOS_2=5
+```
+This will execute test ```RTOS_1``` ten (10) times and test ```RTOS_2``` five (5) times.
+* Force non default copy method. Note that mbed platforms can be flashed with just binary drag&drop. We simply copy file onto mbed's disk and interface chip flashes target MCU with given binary. Force non standard (Python specific) copy method by using option ```-c COPY_METHOD``` where ```COPY_METHOD``` can be shell, command line copy command like: ```cp```, ```copy````, ```xcopy``` etc. Make sure those commands are available from command line!
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -c cp
+```
+* Run only selected tests. You can select which tests should be executed when you run test suite. Use ```-n``` switch to define tests by their ids you want to execute. Use comma to separate test ids:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11
+```
+* Set common output binary name for all tests. In some cases you would like to have the same name for all tests. You can use switch ```--firmware-name``` to specify (without extension) build script output binary name.
+In below example we would like to have all test binaries called ```firmware.bin`` (or with other extension like .elf, .hex depending on target accepted format).
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --firmware-name firmware
+```
+* Where to find test list? Tests are defined in file ```tests.py``` in ```mbed/workspace_tools/``` directory. ```singletest.py``` uses test metadata in ```tests.py``` to resolve libraries dependencies and build tests for proper platforms and peripherals. Option ```-R``` can be used to get test names and direct path and test configuration.
+```
+$ python singletest.py -R
++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+
+| id | automated | description | peripherals | host_test | duration | source_dir |
++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+
+| MBED_1 | False | I2C SRF08 | SRF08 | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\i2c_SRF08 |
+| MBED_10 | True | Hello World | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\hello |
+| MBED_11 | True | Ticker Int | - | host_test | 20 | C:\Work\mbed\libraries\tests\mbed\ticker |
+| MBED_12 | True | C++ | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\cpp |
+| MBED_13 | False | Heap & Stack | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\heap_and_stack |
+| MBED_14 | False | Serial Interrupt | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt |
+| MBED_15 | False | RPC | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\rpc |
+| MBED_16 | True | RTC | - | host_test | 15 | C:\Work\mbed\libraries\tests\mbed\rtc |
+| MBED_17 | False | Serial Interrupt 2 | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt_2 |
+| MBED_18 | False | Local FS Directory | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\dir |
+...
+```
+Note: you can filter tests by ```id``` column, just use ```-f``` option and give test name or regular expression:
+```
+$ python singletest.py -R -f RTOS
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+| id | automated | description | peripherals | host_test | duration | source_dir |
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+| CMSIS_RTOS_1 | False | Basic | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\basic |
+| CMSIS_RTOS_2 | False | Mutex | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mutex |
+| CMSIS_RTOS_3 | False | Semaphore | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\semaphore |
+| CMSIS_RTOS_4 | False | Signals | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\signals |
+| CMSIS_RTOS_5 | False | Queue | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\queue |
+| CMSIS_RTOS_6 | False | Mail | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mail |
+| CMSIS_RTOS_7 | False | Timer | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\timer |
+| CMSIS_RTOS_8 | False | ISR | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\isr |
+| RTOS_1 | True | Basic thread | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\basic |
+| RTOS_2 | True | Mutex resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\mutex |
+| RTOS_3 | True | Semaphore resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\semaphore |
+| RTOS_4 | True | Signals messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\signals |
+| RTOS_5 | True | Queue messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\queue |
+| RTOS_6 | True | Mail messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\mail |
+| RTOS_7 | True | Timer | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\timer |
+| RTOS_8 | True | ISR (Queue) | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\isr |
+| RTOS_9 | True | SD File write-read | SD | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\file |
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+```
+
+* Shuffle your tests. We strongly encourage you to shuffle your test order each time you execute test suite script.
+Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```–u``` (or ```--shuffle```):
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --shuffle
+```
+Above command with force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```.
+
+You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle```} switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --shuffle --shuffle-seed 0.4041028336
+```
+Note: You can also supply your own randomly generated shuffle seed to drive particular test execution order scenarios. Just make sure shuffle seed is float in ```[0.0, 1.0)```.
+You can find test shuffle seed in test summary:
+```
+...
+| OK | LPC1768 | ARM | MBED_A9 | Serial Echo at 115200 | 2.84 | 10 | 1/1 |
++--------+---------+-----------+-----------+-----------------------------+--------------------+---------------+-------+
+Result: 1 FAIL / 22 OK
+Shuffle Seed: 0.4041028336
+
+Completed in 234.85 sec
+```
+
+### Exmple of device configuration (one device connected to host computer)
+
+This example will show you how to configure single device, run general tests or only peripheral tests. We will also show some real test result examples.
+
+1. We will test only one board STMIcro Nucleo ```F334R8``` board connected to our PC (port ```COM46``` and disk is ```E:```).
+2. We will also connect EEPROM ```24LC256``` to SDA, SCL pins of our Nucleo board and define 24LC256 peripheral to make sure our test suite will run all available tests for ```24LC256```.
+
+Let's configure our one MUT and set uARM as the only compiler we will use to compiler Mbed SDK and tests.
+We also need to create two configuration files ```muts_all.json``` and ```test_spec.json``` to pass our small testbed configuration to test script.
+
+muts_all.json:
+```json
+{
+ "1" : {
+ "mcu": "NUCLEO_F334R8",
+ "port":"COM46",
+ "disk":"E:\\",
+ "peripherals": ["24LC256"]
+ }
+}
+```
+Note: By defining ```"peripherals": ["24LC256"]``` we are passing to test suite information that this particular board has EEPROM 24LC256 connected to our board.
+
+test_spec.json:
+```json
+{
+ "targets": {
+ "NUCLEO_F334R8" : ["uARM"]
+ }
+}
+```
+Note:
+* Please make sure device is connected before we will start running tests.
+* Please make sure files ```muts_all.json``` and ```test_spec.json``` are in ```mbed/workspace_tools/``` directory.
+Now you can call test suite and execute tests:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json
+...
+Test summary:
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) |
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+| OK | NUCLEO_F334R8 | uARM | MBED_A25 | I2C EEPROM line read/write test | 12.41 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_A1 | Basic | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | EXAMPLE_1 | /dev/null | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_24 | Timeout Int us | 11.47 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_25 | Time us | 11.43 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_26 | Integer constant division | 3.37 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_23 | Ticker Int us | 12.43 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_A19 | I2C EEPROM read/write test | 11.42 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_11 | Ticker Int | 12.43 | 20 |
+| OK | NUCLEO_F334R8 | uARM | MBED_10 | Hello World | 2.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_12 | C++ | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_16 | RTC | 4.76 | 15 |
+| UNDEF | NUCLEO_F334R8 | uARM | MBED_2 | stdio | 20.42 | 20 |
+| UNDEF | NUCLEO_F334R8 | uARM | MBED_A9 | Serial Echo at 115200 | 10.37 | 10 |
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+Result: 2 UNDEF / 12 OK
+
+Completed in 160 sec
+```
+
+If we want to get additional test summary with results in separate columns please use option ```-t```.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -t
+...
+Test summary:
++---------------+-----------+---------------------------------+-------+
+| Target | Test ID | Test Description | uARM |
++---------------+-----------+---------------------------------+-------+
+| NUCLEO_F334R8 | EXAMPLE_1 | /dev/null | OK |
+| NUCLEO_F334R8 | MBED_10 | Hello World | OK |
+| NUCLEO_F334R8 | MBED_11 | Ticker Int | OK |
+| NUCLEO_F334R8 | MBED_12 | C++ | OK |
+| NUCLEO_F334R8 | MBED_16 | RTC | OK |
+| NUCLEO_F334R8 | MBED_2 | stdio | UNDEF |
+| NUCLEO_F334R8 | MBED_23 | Ticker Int us | OK |
+| NUCLEO_F334R8 | MBED_24 | Timeout Int us | OK |
+| NUCLEO_F334R8 | MBED_25 | Time us | OK |
+| NUCLEO_F334R8 | MBED_26 | Integer constant division | OK |
+| NUCLEO_F334R8 | MBED_A1 | Basic | OK |
+| NUCLEO_F334R8 | MBED_A19 | I2C EEPROM read/write test | OK |
+| NUCLEO_F334R8 | MBED_A25 | I2C EEPROM line read/write test | OK |
+| NUCLEO_F334R8 | MBED_A9 | Serial Echo at 115200 | UNDEF |
++---------------+-----------+---------------------------------+-------+
+```
+----
+Please do not forget you can combine few options together to get result you want. For example you want to repeat few tests multiple number of times, shuffle test ids execution order and select only tests which are critical for you at this point. You can do it using switch -n, --global-loops with --loops and --shuffle:
+
+Execute above command to:
+
+* Run only tests: ```RTOS_1```, ```RTOS_2```, ```RTOS_3```, ```MBED_10```, ```MBED_16```, ```MBED_11```.
+* Shuffle test execution order. Note tests in loops will not be shuffled.
+* Set global loop count to 3 - each test will repeated 3 times.
+* Overwrite global loop count (set above to 3) and:
+ * Force to loop test RTOS_1 to execute 3 times.
+ * Force to loop test RTOS_2 to execute 4 times.
+ * Force to loop test RTOS_3 to execute 5 times.
+ * Force to loop test MBED_11 to execute 5 times.
+
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11 --shuffle --global-loops 3 --loops RTOS_1=3,RTOS_2=4,RTOS_3=5,MBED_11=5
+```
+
+# CppUTest unit test library support
+## CppUTest in Mbed SDK testing introduction
+[CppUTest](http://cpputest.github.io/) is a C / C++ based unit xUnit test framework for unit testing and for test-driving your code. It is written in C++ but is used in C and C++ projects and frequently used in embedded systems but it works for any C / C++ project.
+
+Mbed SDK test suite supports writing tests using CppUTest. All you need to do it to provide CppUTest sources and includes with Mbed SDK port. This is already done for you so all you need to do it to get proper sources in your project directory.
+CppUTest’s core design principles are:
+* Simple in design and simple in use.
+* Portable to old and new platforms.
+* Build with Test-driven Development in mind.
+
+## From where you can get more help about CppUTest library and unit testing
+• You can read [CppUTest manual](http://cpputest.github.io/manual.html)
+* [CppUTest forum](https://groups.google.com/forum/?fromgroups#!forum/cpputest)
+* [CppUTest on GitHub](https://github.com/cpputest/cpputest)
+* Finally, if you think unit testing is new concept for you, you can have a grasp of it on Wikipedia pages about [unit testing](http://en.wikipedia.org/wiki/Unit_testing) and continue from there.
+
+## How to add CppUTest to your current Mbed SDK installation
+
+### Do I need CppUTest port for Mbed SDK?
+Yes, you do. If you want to use CppUTest with Mbed SDK you need to have CppUTest version with ARMCC compiler (only ARM flavor for now) port and Mbed SDK console port (if you want to have output on serial port). All is already prepared by Mbed engineers and you can get it for example here: http://mbed.org/users/rgrover1/code/CppUTest/
+
+### Prerequisites
+* Installed [git client](http://git-scm.com/downloads/).
+* Installed [Mercurial client](http://mercurial.selenic.com/).
+
+### How / where to install
+We want to create directory structure similar to one below:
+```
+\your_project_directory
+│
+├───cpputest
+│ ├───include
+│ └───src
+└───mbed
+ ├───libraries
+ ├───travis
+ └───workspace_tools
+```
+
+Please go to directory with your project. For example it could be c:\Projects\Project.
+```
+$ cd c:\Projects\Project
+```
+If your project directory already has your mbed SDK repository included just execute below command (Mercurial console client). It should download CppUTest with Mbed SDK port.
+```
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+```
+
+You should see something like this after you execute Mercurial clone command:
+```
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+destination directory: cpputest
+requesting all changes
+adding changesets
+adding manifests
+adding file changes
+added 3 changesets with 69 changes to 42 files
+updating to branch default
+41 files updated, 0 files merged, 0 files removed, 0 files unresolved
+```
+
+Confirm your project structure. It should look more or less like this:
+```
+$ ls
+cpputest mbed
+```
+From now on CppUTest is in correct path. Each time you want to compile unit tests for CppUTest build script will always look for CppUTest library in the same directory where mbed library is.
+
+## New off-line mbed SDK project with CppUTest support
+
+If you are creating new mbed SDK project and you want to use CppUTest with it you need to download both mbed SDK and CppUTest with mbed port to the same directory. You can do it like this:
+```
+$ cd c:\Projects\Project
+$ git clone https://github.com/mbedmicro/mbed.git
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+```
+
+After above three steps you should have proper directory structure. All you need to do now is to configure your ```private_settings.py``` in ```mbed/workspace_tools/``` directory. Please refer to mbed SDK build script documentation for details.
+
+## CppUTest with mbed port
+To make sure you actualy have CppUTest library with mbed SDK port you can go to CppUTest ```armcc``` platform directory:
+```
+$ cd c:/Projects/Project/cpputest/src/Platforms/armcc/
+```
+And open file ```UtestPlatform.cpp```.
+
+You should find part of code responsible for porting console on default serial port of the mbed device:
+```c++
+#include "Serial.h"
+using namespace mbed;
+
+int PlatformSpecificPutchar(int c)
+{
+ /* Please modify this block for test results to be reported as
+ * console output. The following is a sample implementation using a
+ * Serial object connected to the console. */
+#define NEED_TEST_REPORT_AS_CONSOLE_OUTPUT 1
+#if NEED_TEST_REPORT_AS_CONSOLE_OUTPUT
+ extern Serial console;
+
+ #define NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE 1
+ #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE
+ /* CppUTest emits \n line terminators in its reports; some terminals
+ * need the linefeed (\r) in addition. */
+ if (c == '\n') {
+ console.putc('\r');
+ }
+ #endif /* #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE */
+
+ return (console.putc(c));
+#else /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */
+ return (0);
+#endif /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */
+}
+```
+
+You can find cpputest UT test runner main function in mbed sources: ```c:/Projects/Project/mbed/libraries/tests/utest/testrunner/testrunner.cpp```. Test runner code (in ```testrunner.cpp```) only defined console object and executes all unit tests:
+```c++
+#include "CommandLineTestRunner.h"
+#include <stdio.h>
+#include "mbed.h"
+#include "testrunner.h"
+#include "test_env.h"
+
+/**
+Object 'mbed_cpputest_console' is used to show prints on console.
+It is declared in \cpputest\src\Platforms\armcc\UtestPlatform.cpp
+*/
+Serial mbed_cpputest_console(STDIO_UART_TX, STDIO_UART_RX);
+
+int main(int ac, char** av) {
+ MBED_HOSTTEST_TIMEOUT(20);
+ MBED_HOSTTEST_SELECT(default_auto);
+ MBED_HOSTTEST_DESCRIPTION(Unit test);
+ MBED_HOSTTEST_START("UT");
+
+ unsigned failureCount = 0;
+ {
+ // Some compilers may not pass ac, av so we need to supply them ourselves
+ int ac = 2;
+ char* av[] = {__FILE__, "-v"};
+ failureCount = CommandLineTestRunner::RunAllTests(ac, av);
+ }
+
+ MBED_HOSTTEST_RESULT(failureCount == 0);
+ return failureCount;
+}
+```
+
+## Unit test location
+Unit tests source code is located in below directory: ```c:/Projects/Project/mbed/libraries/tests/utest/```
+
+Each sub directory except testrunner contains compilable unit test source files with test groups and test cases. You can see utest structure below. Please note this is just example and in the future this directory will contain many sub directories with unit tests.
+```
+$ c:\Projects\Project\mbed\libraries\tests\utest> tree
+utest
+├───basic
+├───semihost_fs
+└───testrunner
+```
+
+## Define unit tests in mbed SDK test suite structure
+All tests defined in test suite are described in ```mbed/workspace_tools/tests.py``` file. This file stores data structure ```TESTS``` which is a list of simple structures describing each test. Below you can find example of ```TESTS``` structure which is configuring one of the unit tests.
+```
+.
+.
+.
+ {
+ "id": "UT_2", "description": "Semihost file system",
+ "source_dir": join(TEST_DIR, "utest", "file"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": False,
+ "mcu": ["LPC1768", "LPC2368", "LPC11U24"]
+ },
+.
+.
+.
+```
+Note: In dependency section we've added library ```CPPUTEST_LIBRARY``` which is pointing build script to CppUTest library with mbed port. This is a must for unit tests to be compiled with CppUTest library.
+
+### Tests are now divided into two types:
+#### 'Hello world' tests
+First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. Yo can find this tests in below example directories:
+
+* ```mbed/libraries/tests/mbed/```
+* ```mbed/libraries/tests/net/```
+* ```mbed/libraries/tests/rtos/```
+* ```mbed/libraries/tests/usb/```
+
+Usually ‘hello world’ test cases are using ```test_env.cpp``` and ```test_env.h``` files which implement simple test framework used to communicate with host test and help test framework instrument your tests.
+
+Below you can see listing of ```test_env.h``` file which contains simple macro definitions used to communicate (via serial port printouts) between test case (on hardware) and host test script (on host computer).
+Each use case should print on console basic information like:
+* Default test case timeout.
+* Which host test should be used to supervise test case execution.
+* Test description and test case ID (short identifier).
+
+```c++
+.
+.
+.
+// Test result related notification functions
+void notify_start();
+void notify_completion(bool success);
+bool notify_completion_str(bool success, char* buffer);
+void notify_performance_coefficient(const char* measurement_name, const int value);
+void notify_performance_coefficient(const char* measurement_name, const unsigned int value);
+void notify_performance_coefficient(const char* measurement_name, const double value);
+
+// Host test auto-detection API
+void notify_host_test_name(const char *host_test);
+void notify_timeout(int timeout);
+void notify_test_id(const char *test_id);
+void notify_test_description(const char *description);
+
+// Host test auto-detection API
+#define MBED_HOSTTEST_START(TESTID) notify_test_id(TESTID); notify_start()
+#define MBED_HOSTTEST_SELECT(NAME) notify_host_test_name(#NAME)
+#define MBED_HOSTTEST_TIMEOUT(SECONDS) notify_timeout(SECONDS)
+#define MBED_HOSTTEST_DESCRIPTION(DESC) notify_test_description(#DESC)
+#define MBED_HOSTTEST_RESULT(RESULT) notify_completion(RESULT)
+
+/**
+ Test auto-detection preamble example:
+ main() {
+ MBED_HOSTTEST_TIMEOUT(10);
+ MBED_HOSTTEST_SELECT( host_test );
+ MBED_HOSTTEST_DESCRIPTION(Hello World);
+ MBED_HOSTTEST_START("MBED_10");
+ // Proper 'host_test.py' should take over supervising of this test
+
+ // Test code
+ bool result = ...;
+
+ MBED_HOSTTEST_RESULT(result);
+ }
+*/
+.
+.
+.
+```
+
+Example of 'hello world' test:
+```c++
+#include "mbed.h"
+#include "test_env.h"
+
+#define CUSTOM_TIME 1256729737
+
+int main() {
+ MBED_HOSTTEST_TIMEOUT(20);
+ MBED_HOSTTEST_SELECT(rtc_auto);
+ MBED_HOSTTEST_DESCRIPTION(RTC);
+ MBED_HOSTTEST_START("MBED_16");
+
+ char buffer[32] = {0};
+ set_time(CUSTOM_TIME); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ while(1) {
+ time_t seconds = time(NULL);
+ strftime(buffer, 32, "%Y-%m-%d %H:%M:%S %p", localtime(&seconds));
+ printf("MBED: [%ld] [%s]\r\n", seconds, buffer);
+ wait(1);
+ }
+}
+```
+
+#### 'Unit test' test cases
+Second group of tests are unit tests. They are using CppUTest library and require you to write ```TEST_GROUP```s and ```TEST```s in your test files. Test suite will add test runner sources to your test automatically so you can concentrate on writing tests.
+
+Example of unit test:
+```c++
+#include "TestHarness.h"
+#include <utility>
+#include "mbed.h"
+
+TEST_GROUP(BusOut_mask)
+{
+};
+
+TEST(BusOut_mask, led_1_2_3)
+{
+ BusOut bus_data(LED1, LED2, LED3);
+ CHECK_EQUAL(0x07, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_nc_nc_nc_nc)
+{
+ BusOut bus_data(NC, NC, NC, NC);
+ CHECK_EQUAL(0x00, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_1_2_3_nc_nc)
+{
+ BusOut bus_data(LED1, LED2, LED3, NC, NC);
+ CHECK_EQUAL(0x07, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_1_nc_2_nc_nc_3)
+{
+ BusOut bus_data(LED1, NC, LED2, NC, NC, LED3);
+ CHECK_EQUAL(0x25, bus_data.mask());
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+#ifdef MBED_OPERATORS
+TEST_GROUP(BusOut_digitalout_write)
+{
+};
+
+TEST(BusOut_digitalout_write, led_nc)
+{
+ BusOut bus_data(NC);
+ CHECK_EQUAL(false, bus_data[0].is_connected())
+}
+
+TEST(BusOut_digitalout_write, led_1_2_3)
+{
+ BusOut bus_data(LED1, LED2, LED3);
+ bus_data[0].write(1);
+ bus_data[1].write(1);
+ bus_data[2].write(1);
+ CHECK(bus_data[0].read());
+ CHECK(bus_data[1].read());
+ CHECK(bus_data[2].read());
+}
+
+TEST(BusOut_digitalout_write, led_1_2_3_nc_nc)
+{
+ BusOut bus_data(LED1, LED2, LED3, NC, NC);
+ bus_data[0].write(0);
+ bus_data[1].write(0);
+ bus_data[2].write(0);
+ CHECK(bus_data[0].read() == 0);
+ CHECK(bus_data[1].read() == 0);
+ CHECK(bus_data[2].read() == 0);
+}
+
+TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3)
+{
+ BusOut bus_data(LED1, NC, LED2, NC, NC, LED3);
+ bus_data[0].write(1);
+ bus_data[2].write(0);
+ bus_data[5].write(0);
+ CHECK(bus_data[0].read());
+ CHECK(bus_data[2].read() == 0);
+ CHECK(bus_data[5].read() == 0);
+}
+#endif
+```
+
+## Example
+In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also should stop you from writing and executing your own unit tests!
+
+### Example configuration
+By default unit tests ```UT_1``` and ```UT_2``` are not automated - simply test suite will ignore them. Also we do not want to create dependency to CppUTest library each time someone executes automation.
+
+Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components.
+
+Bellow snippet shows how to modify 'automated' flag so test suite will consider unit tests ```UT_1``` and ```UT_2``` as part of "automated test portfolio". Just change flag 'automated' from ```False``` to ```True```.
+
+```tests.py``` listing related to ```UT_1``` and ```UT_2```:
+```python
+.
+.
+.
+ # CPPUTEST Library provides Unit testing Framework
+ #
+ # To write TESTs and TEST_GROUPs please add CPPUTEST_LIBRARY to 'dependencies'
+ #
+ # This will also include:
+ # 1. test runner - main function with call to CommandLineTestRunner::RunAllTests(ac, av)
+ # 2. Serial console object to print test result on serial port console
+ #
+
+ # Unit testing with cpputest library
+ {
+ "id": "UT_1", "description": "Basic",
+ "source_dir": join(TEST_DIR, "utest", "basic"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": True,
+ },
+ {
+ "id": "UT_2", "description": "Semihost file system",
+ "source_dir": join(TEST_DIR, "utest", "semihost_fs"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": True,
+ "mcu": ["LPC1768", "LPC2368", "LPC11U24"]
+ },
+.
+.
+.
+```
+
+### Execute tests
+In my test I will use common [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) mbed-enabled board because unit test ```UT_2``` is checking semi-host functionality which is available on this board and handful of others.
+
+Configure your ```test_spec.json``` and ```muts_all.json``` files (refer to test suite build script and automation description) and set mbed disk and serial port.
+
+```
+$ singletest.py -i test_spec.json -M muts_all.json -n UT_1,UT_2 -V
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+Building library CPPUTEST (LPC1768, ARM)
+Building project BASIC (LPC1768, ARM)
+Executing 'python host_test.py -p COM77 -d E:\ -t 10'
+Test::Output::Start
+Host test instrumentation on port: "COM77" and disk: "E:\"
+TEST(FirstTestGroup, FirstTest) - 0 ms
+
+OK (1 tests, 1 ran, 3 checks, 0 ignored, 0 filtered out, 3 ms)
+
+{{success}}
+{{end}}
+Test::Output::Finish
+TargetTest::LPC1768::ARM::UT_1::Basic [OK] in 2.43 of 10 sec
+Building library CPPUTEST (LPC1768, ARM)
+Building project SEMIHOST_FS (LPC1768, ARM)
+Executing 'python host_test.py -p COM77 -d E:\ -t 10'
+Test::Output::Start
+Host test instrumentation on port: "COM77" and disk: "E:\"
+TEST(FirstTestGroup, FirstTest) - 9 ms
+
+OK (1 tests, 1 ran, 10 checks, 0 ignored, 0 filtered out, 10 ms)
+
+{{success}}
+{{end}}
+Test::Output::Finish
+TargetTest::LPC1768::ARM::UT_2::Semihost file system [OK] in 2.43 of 10 sec
+Test summary:
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+Result: 2 OK
+
+Completed in 12.02 sec
+```
+
+You can compile unit tests using various number of supported compilers, below just few examples with working solutions:
+```
+Test summary:
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | uARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | uARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_CR | UT_1 | Basic | 3.44 | 10 | 1/1 |
+| OK | LPC1768 | GCC_CR | UT_2 | Semihost file system | 3.43 | 10 | 1/1 |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+Result: 8 OK
+
+Completed in 55.85 sec
+```
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp
new file mode 100644
index 000000000..aab9e774e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp
@@ -0,0 +1,618 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBAudio.h"
+#include "USBAudio_Types.h"
+
+
+
+USBAudio::USBAudio(uint32_t frequency_in, uint8_t channel_nb_in, uint32_t frequency_out, uint8_t channel_nb_out, uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) {
+ mute = 0;
+ volCur = 0x0080;
+ volMin = 0x0000;
+ volMax = 0x0100;
+ volRes = 0x0004;
+ available = false;
+
+ FREQ_IN = frequency_in;
+ FREQ_OUT = frequency_out;
+
+ this->channel_nb_in = channel_nb_in;
+ this->channel_nb_out = channel_nb_out;
+
+ // stereo -> *2, mono -> *1
+ PACKET_SIZE_ISO_IN = (FREQ_IN / 500) * channel_nb_in;
+ PACKET_SIZE_ISO_OUT = (FREQ_OUT / 500) * channel_nb_out;
+
+ // STEREO -> left and right
+ channel_config_in = (channel_nb_in == 1) ? CHANNEL_M : CHANNEL_L + CHANNEL_R;
+ channel_config_out = (channel_nb_out == 1) ? CHANNEL_M : CHANNEL_L + CHANNEL_R;
+
+ SOF_handler = false;
+
+ buf_stream_out = NULL;
+ buf_stream_in = NULL;
+
+ interruptOUT = false;
+ writeIN = false;
+ interruptIN = false;
+ available = false;
+
+ volume = 0;
+
+ // connect the device
+ USBDevice::connect();
+}
+
+bool USBAudio::read(uint8_t * buf) {
+ buf_stream_in = buf;
+ SOF_handler = false;
+ while (!available || !SOF_handler);
+ available = false;
+ return true;
+}
+
+bool USBAudio::readNB(uint8_t * buf) {
+ buf_stream_in = buf;
+ SOF_handler = false;
+ while (!SOF_handler);
+ if (available) {
+ available = false;
+ buf_stream_in = NULL;
+ return true;
+ }
+ return false;
+}
+
+bool USBAudio::readWrite(uint8_t * buf_read, uint8_t * buf_write) {
+ buf_stream_in = buf_read;
+ SOF_handler = false;
+ writeIN = false;
+ if (interruptIN) {
+ USBDevice::writeNB(EP3IN, buf_write, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ } else {
+ buf_stream_out = buf_write;
+ }
+ while (!available);
+ if (interruptIN) {
+ while (!writeIN);
+ }
+ while (!SOF_handler);
+ return true;
+}
+
+
+bool USBAudio::write(uint8_t * buf) {
+ writeIN = false;
+ SOF_handler = false;
+ if (interruptIN) {
+ USBDevice::writeNB(EP3IN, buf, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ } else {
+ buf_stream_out = buf;
+ }
+ while (!SOF_handler);
+ if (interruptIN) {
+ while (!writeIN);
+ }
+ return true;
+}
+
+
+float USBAudio::getVolume() {
+ return (mute) ? 0.0 : volume;
+}
+
+
+bool USBAudio::EPISO_OUT_callback() {
+ uint32_t size = 0;
+ interruptOUT = true;
+ if (buf_stream_in != NULL) {
+ readEP(EP3OUT, (uint8_t *)buf_stream_in, &size, PACKET_SIZE_ISO_IN);
+ available = true;
+ buf_stream_in = NULL;
+ }
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ return false;
+}
+
+
+bool USBAudio::EPISO_IN_callback() {
+ interruptIN = true;
+ writeIN = true;
+ return true;
+}
+
+
+
+// Called in ISR context on each start of frame
+void USBAudio::SOF(int frameNumber) {
+ uint32_t size = 0;
+
+ if (!interruptOUT) {
+ // read the isochronous endpoint
+ if (buf_stream_in != NULL) {
+ if (USBDevice::readEP_NB(EP3OUT, (uint8_t *)buf_stream_in, &size, PACKET_SIZE_ISO_IN)) {
+ if (size) {
+ available = true;
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ buf_stream_in = NULL;
+ }
+ }
+ }
+ }
+
+ if (!interruptIN) {
+ // write if needed
+ if (buf_stream_out != NULL) {
+ USBDevice::writeNB(EP3IN, (uint8_t *)buf_stream_out, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ buf_stream_out = NULL;
+ }
+ }
+
+ SOF_handler = true;
+}
+
+
+// Called in ISR context
+// Set configuration. Return false if the configuration is not supported.
+bool USBAudio::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure isochronous endpoint
+ realiseEndpoint(EP3OUT, PACKET_SIZE_ISO_IN, ISOCHRONOUS);
+ realiseEndpoint(EP3IN, PACKET_SIZE_ISO_OUT, ISOCHRONOUS);
+
+ // activate readings on this endpoint
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ return true;
+}
+
+
+// Called in ISR context
+// Set alternate setting. Return false if the alternate setting is not supported
+bool USBAudio::USBCallback_setInterface(uint16_t interface, uint8_t alternate) {
+ if (interface == 0 && alternate == 0) {
+ return true;
+ }
+ if (interface == 1 && (alternate == 0 || alternate == 1)) {
+ return true;
+ }
+ if (interface == 2 && (alternate == 0 || alternate == 1)) {
+ return true;
+ }
+ return false;
+}
+
+
+
+// Called in ISR context
+// Called by USBDevice on Endpoint0 request
+// This is used to handle extensions to standard requests and class specific requests.
+// Return true if class handles this request
+bool USBAudio::USBCallback_request() {
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ // Process class-specific requests
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+
+ // Feature Unit: Interface = 0, ID = 2
+ if (transfer->setup.wIndex == 0x0200) {
+
+ // Master Channel
+ if ((transfer->setup.wValue & 0xff) == 0) {
+
+ switch (transfer->setup.wValue >> 8) {
+ case MUTE_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_GET_CUR:
+ transfer->remaining = 1;
+ transfer->ptr = &mute;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+
+ case REQUEST_SET_CUR:
+ transfer->remaining = 1;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ default:
+ break;
+ }
+ break;
+ case VOLUME_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_GET_CUR:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volCur;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_MIN:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volMin;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_MAX:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volMax;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_RES:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volRes;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+
+ case REQUEST_SET_CUR:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_MIN:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_MAX:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_RES:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ }
+ return success;
+}
+
+
+// Called in ISR context when a data OUT stage has been performed
+void USBAudio::USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {
+ if ((length == 1) || (length == 2)) {
+ uint16_t data = (length == 1) ? *buf : *((uint16_t *)buf);
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ switch (transfer->setup.wValue >> 8) {
+ case MUTE_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_SET_CUR:
+ mute = data & 0xff;
+ updateVol.call();
+ break;
+ default:
+ break;
+ }
+ break;
+ case VOLUME_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_SET_CUR:
+ volCur = data;
+ volume = (float)volCur/(float)volMax;
+ updateVol.call();
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (5 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1) \
+ + (2 * INPUT_TERMINAL_DESCRIPTOR_LENGTH) \
+ + (1 * FEATURE_UNIT_DESCRIPTOR_LENGTH) \
+ + (2 * OUTPUT_TERMINAL_DESCRIPTOR_LENGTH) \
+ + (2 * STREAMING_INTERFACE_DESCRIPTOR_LENGTH) \
+ + (2 * FORMAT_TYPE_I_DESCRIPTOR_LENGTH) \
+ + (2 * (ENDPOINT_DESCRIPTOR_LENGTH + 2)) \
+ + (2 * STREAMING_ENDPOINT_DESCRIPTOR_LENGTH) )
+
+#define TOTAL_CONTROL_INTF_LENGTH (CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1 + \
+ 2*INPUT_TERMINAL_DESCRIPTOR_LENGTH + \
+ FEATURE_UNIT_DESCRIPTOR_LENGTH + \
+ 2*OUTPUT_TERMINAL_DESCRIPTOR_LENGTH)
+
+uint8_t * USBAudio::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // Configuration 1
+ CONFIGURATION_DESCRIPTOR_LENGTH, // bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x03, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ 0x80, // bmAttributes
+ 50, // bMaxPower
+
+ // Interface 0, Alternate Setting 0, Audio Control
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOCONTROL, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+
+ // Audio Control Interface
+ CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1,// bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_HEADER, // bDescriptorSubtype
+ LSB(0x0100), // bcdADC (LSB)
+ MSB(0x0100), // bcdADC (MSB)
+ LSB(TOTAL_CONTROL_INTF_LENGTH), // wTotalLength
+ MSB(TOTAL_CONTROL_INTF_LENGTH), // wTotalLength
+ 0x02, // bInCollection
+ 0x01, // baInterfaceNr
+ 0x02, // baInterfaceNr
+
+ // Audio Input Terminal (Speaker)
+ INPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_INPUT_TERMINAL, // bDescriptorSubtype
+ 0x01, // bTerminalID
+ LSB(TERMINAL_USB_STREAMING), // wTerminalType
+ MSB(TERMINAL_USB_STREAMING), // wTerminalType
+ 0x00, // bAssocTerminal
+ channel_nb_in, // bNrChannels
+ (uint8_t)(LSB(channel_config_in)), // wChannelConfig
+ (uint8_t)(MSB(channel_config_in)), // wChannelConfig
+ 0x00, // iChannelNames
+ 0x00, // iTerminal
+
+ // Audio Feature Unit (Speaker)
+ FEATURE_UNIT_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_FEATURE_UNIT, // bDescriptorSubtype
+ 0x02, // bUnitID
+ 0x01, // bSourceID
+ 0x01, // bControlSize
+ CONTROL_MUTE |
+ CONTROL_VOLUME, // bmaControls(0)
+ 0x00, // bmaControls(1)
+ 0x00, // iTerminal
+
+ // Audio Output Terminal (Speaker)
+ OUTPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_OUTPUT_TERMINAL, // bDescriptorSubtype
+ 0x03, // bTerminalID
+ LSB(TERMINAL_SPEAKER), // wTerminalType
+ MSB(TERMINAL_SPEAKER), // wTerminalType
+ 0x00, // bAssocTerminal
+ 0x02, // bSourceID
+ 0x00, // iTerminal
+
+
+ // Audio Input Terminal (Microphone)
+ INPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_INPUT_TERMINAL, // bDescriptorSubtype
+ 0x04, // bTerminalID
+ LSB(TERMINAL_MICROPHONE), // wTerminalType
+ MSB(TERMINAL_MICROPHONE), // wTerminalType
+ 0x00, // bAssocTerminal
+ channel_nb_out, // bNrChannels
+ (uint8_t)(LSB(channel_config_out)), // wChannelConfig
+ (uint8_t)(MSB(channel_config_out)), // wChannelConfig
+ 0x00, // iChannelNames
+ 0x00, // iTerminal
+
+ // Audio Output Terminal (Microphone)
+ OUTPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_OUTPUT_TERMINAL, // bDescriptorSubtype
+ 0x05, // bTerminalID
+ LSB(TERMINAL_USB_STREAMING), // wTerminalType
+ MSB(TERMINAL_USB_STREAMING), // wTerminalType
+ 0x00, // bAssocTerminal
+ 0x04, // bSourceID
+ 0x00, // iTerminal
+
+
+
+
+
+
+ // Interface 1, Alternate Setting 0, Audio Streaming - Zero Bandwith
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x01, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Interface 1, Alternate Setting 1, Audio Streaming - Operational
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x01, // bInterfaceNumber
+ 0x01, // bAlternateSetting
+ 0x01, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Audio Streaming Interface
+ STREAMING_INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ STREAMING_GENERAL, // bDescriptorSubtype
+ 0x01, // bTerminalLink
+ 0x00, // bDelay
+ LSB(FORMAT_PCM), // wFormatTag
+ MSB(FORMAT_PCM), // wFormatTag
+
+ // Audio Type I Format
+ FORMAT_TYPE_I_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ STREAMING_FORMAT_TYPE, // bDescriptorSubtype
+ FORMAT_TYPE_I, // bFormatType
+ channel_nb_in, // bNrChannels
+ 0x02, // bSubFrameSize
+ 16, // bBitResolution
+ 0x01, // bSamFreqType
+ (uint8_t)(LSB(FREQ_IN)), // tSamFreq
+ (uint8_t)((FREQ_IN >> 8) & 0xff), // tSamFreq
+ (uint8_t)((FREQ_IN >> 16) & 0xff), // tSamFreq
+
+ // Endpoint - Standard Descriptor
+ ENDPOINT_DESCRIPTOR_LENGTH + 2, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPISO_OUT), // bEndpointAddress
+ E_ISOCHRONOUS, // bmAttributes
+ (uint8_t)(LSB(PACKET_SIZE_ISO_IN)), // wMaxPacketSize
+ (uint8_t)(MSB(PACKET_SIZE_ISO_IN)), // wMaxPacketSize
+ 0x01, // bInterval
+ 0x00, // bRefresh
+ 0x00, // bSynchAddress
+
+ // Endpoint - Audio Streaming
+ STREAMING_ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType
+ ENDPOINT_GENERAL, // bDescriptor
+ 0x00, // bmAttributes
+ 0x00, // bLockDelayUnits
+ LSB(0x0000), // wLockDelay
+ MSB(0x0000), // wLockDelay
+
+
+
+
+
+
+
+ // Interface 1, Alternate Setting 0, Audio Streaming - Zero Bandwith
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x02, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Interface 1, Alternate Setting 1, Audio Streaming - Operational
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x02, // bInterfaceNumber
+ 0x01, // bAlternateSetting
+ 0x01, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Audio Streaming Interface
+ STREAMING_INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ SUBCLASS_AUDIOCONTROL, // bDescriptorSubtype
+ 0x05, // bTerminalLink (output terminal microphone)
+ 0x01, // bDelay
+ 0x01, // wFormatTag
+ 0x00, // wFormatTag
+
+ // Audio Type I Format
+ FORMAT_TYPE_I_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ SUBCLASS_AUDIOSTREAMING, // bDescriptorSubtype
+ FORMAT_TYPE_I, // bFormatType
+ channel_nb_out, // bNrChannels
+ 0x02, // bSubFrameSize
+ 0x10, // bBitResolution
+ 0x01, // bSamFreqType
+ (uint8_t)(LSB(FREQ_OUT)), // tSamFreq
+ (uint8_t)((FREQ_OUT >> 8) & 0xff), // tSamFreq
+ (uint8_t)((FREQ_OUT >> 16) & 0xff), // tSamFreq
+
+ // Endpoint - Standard Descriptor
+ ENDPOINT_DESCRIPTOR_LENGTH + 2, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPISO_IN), // bEndpointAddress
+ E_ISOCHRONOUS, // bmAttributes
+ (uint8_t)(LSB(PACKET_SIZE_ISO_OUT)), // wMaxPacketSize
+ (uint8_t)(MSB(PACKET_SIZE_ISO_OUT)), // wMaxPacketSize
+ 0x01, // bInterval
+ 0x00, // bRefresh
+ 0x00, // bSynchAddress
+
+ // Endpoint - Audio Streaming
+ STREAMING_ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType
+ ENDPOINT_GENERAL, // bDescriptor
+ 0x00, // bmAttributes
+ 0x00, // bLockDelayUnits
+ LSB(0x0000), // wLockDelay
+ MSB(0x0000), // wLockDelay
+
+ // Terminator
+ 0 // bLength
+ };
+ return configDescriptor;
+}
+
+uint8_t * USBAudio::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x0c, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBAudio::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h
new file mode 100644
index 000000000..5038f053c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h
@@ -0,0 +1,287 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBAudio_H
+#define USBAudio_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+
+/**
+* USBAudio example
+*
+* @code
+* #include "mbed.h"
+* #include "USBAudio.h"
+*
+* Serial pc(USBTX, USBRX);
+*
+* // frequency: 48 kHz
+* #define FREQ 48000
+*
+* // 1 channel: mono
+* #define NB_CHA 1
+*
+* // length of an audio packet: each ms, we receive 48 * 16bits ->48 * 2 bytes. as there is one channel, the length will be 48 * 2 * 1
+* #define AUDIO_LENGTH_PACKET 48 * 2 * 1
+*
+* // USBAudio
+* USBAudio audio(FREQ, NB_CHA);
+*
+* int main() {
+* int16_t buf[AUDIO_LENGTH_PACKET/2];
+*
+* while (1) {
+* // read an audio packet
+* audio.read((uint8_t *)buf);
+*
+*
+* // print packet received
+* pc.printf("recv: ");
+* for(int i = 0; i < AUDIO_LENGTH_PACKET/2; i++) {
+* pc.printf("%d ", buf[i]);
+* }
+* pc.printf("\r\n");
+* }
+* }
+* @endcode
+*/
+class USBAudio: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param frequency_in frequency in Hz (default: 48000)
+ * @param channel_nb_in channel number (1 or 2) (default: 1)
+ * @param frequency_out frequency in Hz (default: 8000)
+ * @param channel_nb_out_in channel number (1 or 2) (default: 1)
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBAudio(uint32_t frequency_in = 48000, uint8_t channel_nb_in = 1, uint32_t frequency_out = 8000, uint8_t channel_nb_out = 1, uint16_t vendor_id = 0x7bb8, uint16_t product_id = 0x1111, uint16_t product_release = 0x0100);
+
+ /**
+ * Get current volume between 0.0 and 1.0
+ *
+ * @returns volume
+ */
+ float getVolume();
+
+ /**
+ * Read an audio packet. During a frame, only a single reading (you can't write and read an audio packet during the same frame)can be done using this method. Warning: Blocking
+ *
+ * @param buf pointer on a buffer which will be filled with an audio packet
+ *
+ * @returns true if successfull
+ */
+ bool read(uint8_t * buf);
+
+ /**
+ * Try to read an audio packet. During a frame, only a single reading (you can't write and read an audio packet during the same frame)can be done using this method. Warning: Non Blocking
+ *
+ * @param buf pointer on a buffer which will be filled if an audio packet is available
+ *
+ * @returns true if successfull
+ */
+ bool readNB(uint8_t * buf);
+
+ /**
+ * Write an audio packet. During a frame, only a single writing (you can't write and read an audio packet during the same frame)can be done using this method.
+ *
+ * @param buf pointer on the audio packet which will be sent
+ * @returns true if successful
+ */
+ bool write(uint8_t * buf);
+
+ /**
+ * Write and read an audio packet at the same time (on the same frame)
+ *
+ * @param buf_read pointer on a buffer which will be filled with an audio packet
+ * @param buf_write pointer on the audio packet which will be sent
+ * @returns true if successful
+ */
+ bool readWrite(uint8_t * buf_read, uint8_t * buf_write);
+
+
+ /** attach a handler to update the volume
+ *
+ * @param function Function to attach
+ *
+ */
+ void attach(void(*fptr)(void)) {
+ updateVol.attach(fptr);
+ }
+
+ /** Attach a nonstatic void/void member function to update the volume
+ *
+ * @param tptr Object pointer
+ * @param mptr Member function pointer
+ *
+ */
+ template<typename T>
+ void attach(T *tptr, void(T::*mptr)(void)) {
+ updateVol.attach(tptr, mptr);
+ }
+
+
+protected:
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Called by USBDevice layer. Set interface/alternate of the device.
+ *
+ * @param interface Number of the interface to be configured
+ * @param alternate Number of the alternate to be configured
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setInterface(uint16_t interface, uint8_t alternate);
+
+ /*
+ * Called by USBDevice on Endpoint0 request completion
+ * if the 'notify' flag has been set to true. Warning: Called in ISR context
+ *
+ * In this case it is used to indicate that a HID report has
+ * been received from the host on endpoint 0
+ *
+ * @param buf buffer received on endpoint 0
+ * @param length length of this buffer
+ */
+ virtual void USBCallback_requestCompleted(uint8_t * buf, uint32_t length);
+
+ /*
+ * Callback called on each Start of Frame event
+ */
+ virtual void SOF(int frameNumber);
+
+ /*
+ * Callback called when a packet is received
+ */
+ virtual bool EPISO_OUT_callback();
+
+ /*
+ * Callback called when a packet has been sent
+ */
+ virtual bool EPISO_IN_callback();
+
+private:
+
+ // stream available ?
+ volatile bool available;
+
+ // interrupt OUT has been received
+ volatile bool interruptOUT;
+
+ // interrupt IN has been received
+ volatile bool interruptIN;
+
+ // audio packet has been written
+ volatile bool writeIN;
+
+ // FREQ
+ uint32_t FREQ_OUT;
+ uint32_t FREQ_IN;
+
+ // size of the maximum packet for the isochronous endpoint
+ uint32_t PACKET_SIZE_ISO_IN;
+ uint32_t PACKET_SIZE_ISO_OUT;
+
+ // mono, stereo,...
+ uint8_t channel_nb_in;
+ uint8_t channel_nb_out;
+
+ // channel config: master, left, right
+ uint8_t channel_config_in;
+ uint8_t channel_config_out;
+
+ // mute state
+ uint8_t mute;
+
+ // Volume Current Value
+ uint16_t volCur;
+
+ // Volume Minimum Value
+ uint16_t volMin;
+
+ // Volume Maximum Value
+ uint16_t volMax;
+
+ // Volume Resolution
+ uint16_t volRes;
+
+ // Buffer containing one audio packet (to be read)
+ volatile uint8_t * buf_stream_in;
+
+ // Buffer containing one audio packet (to be written)
+ volatile uint8_t * buf_stream_out;
+
+ // callback to update volume
+ FunctionPointer updateVol;
+
+ // boolean showing that the SOF handler has been called. Useful for readNB.
+ volatile bool SOF_handler;
+
+ volatile float volume;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h
new file mode 100644
index 000000000..1151a7200
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h
@@ -0,0 +1,97 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBAUDIO_TYPES_H
+#define USBAUDIO_TYPES_H
+
+
+#define DEFAULT_CONFIGURATION (1)
+
+// Audio Request Codes
+#define REQUEST_SET_CUR 0x01
+#define REQUEST_GET_CUR 0x81
+#define REQUEST_SET_MIN 0x02
+#define REQUEST_GET_MIN 0x82
+#define REQUEST_SET_MAX 0x03
+#define REQUEST_GET_MAX 0x83
+#define REQUEST_SET_RES 0x04
+#define REQUEST_GET_RES 0x84
+
+#define MUTE_CONTROL 0x01
+#define VOLUME_CONTROL 0x02
+
+
+// Audio Descriptor Sizes
+#define CONTROL_INTERFACE_DESCRIPTOR_LENGTH 0x09
+#define STREAMING_INTERFACE_DESCRIPTOR_LENGTH 0x07
+#define INPUT_TERMINAL_DESCRIPTOR_LENGTH 0x0C
+#define OUTPUT_TERMINAL_DESCRIPTOR_LENGTH 0x09
+#define FEATURE_UNIT_DESCRIPTOR_LENGTH 0x09
+#define STREAMING_ENDPOINT_DESCRIPTOR_LENGTH 0x07
+
+// Audio Format Type Descriptor Sizes
+#define FORMAT_TYPE_I_DESCRIPTOR_LENGTH 0x0b
+
+#define AUDIO_CLASS 0x01
+#define SUBCLASS_AUDIOCONTROL 0x01
+#define SUBCLASS_AUDIOSTREAMING 0x02
+
+// Audio Descriptor Types
+#define INTERFACE_DESCRIPTOR_TYPE 0x24
+#define ENDPOINT_DESCRIPTOR_TYPE 0x25
+
+// Audio Control Interface Descriptor Subtypes
+#define CONTROL_HEADER 0x01
+#define CONTROL_INPUT_TERMINAL 0x02
+#define CONTROL_OUTPUT_TERMINAL 0x03
+#define CONTROL_FEATURE_UNIT 0x06
+
+// USB Terminal Types
+#define TERMINAL_USB_STREAMING 0x0101
+
+// Predefined Audio Channel Configuration Bits
+// Mono
+#define CHANNEL_M 0x0000
+#define CHANNEL_L 0x0001 /* Left Front */
+#define CHANNEL_R 0x0002 /* Right Front */
+
+// Feature Unit Control Bits
+#define CONTROL_MUTE 0x0001
+#define CONTROL_VOLUME 0x0002
+
+// Input Terminal Types
+#define TERMINAL_MICROPHONE 0x0201
+
+// Output Terminal Types
+#define TERMINAL_SPEAKER 0x0301
+#define TERMINAL_HEADPHONES 0x0302
+
+// Audio Streaming Interface Descriptor Subtypes
+#define STREAMING_GENERAL 0x01
+#define STREAMING_FORMAT_TYPE 0x02
+
+// Audio Data Format Type I Codes
+#define FORMAT_PCM 0x0001
+
+// Audio Format Types
+#define FORMAT_TYPE_I 0x01
+
+// Audio Endpoint Descriptor Subtypes
+#define ENDPOINT_GENERAL 0x01
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
new file mode 100644
index 000000000..d319e60f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
@@ -0,0 +1,365 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : devdrv_usb_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_FUNCTION_API_H
+#define USB_FUNCTION_API_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <MBRZA1H.h>
+#include "r_typedefs.h"
+#include "usb0_function_api.h"
+#include "usb1_function_api.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct
+{
+ uint32_t fifo;
+ uint32_t buffer;
+ uint32_t bytes;
+ uint32_t dir;
+ uint32_t size;
+} USB_FUNCTION_DMA_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USBFCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */
+#define USBFCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */
+
+#define DEVDRV_USBF_ON (1)
+#define DEVDRV_USBF_OFF (0)
+#define DEVDRV_USBF_YES (1)
+#define DEVDRV_USBF_NO (0)
+
+#define DEVDRV_USBF_STALL (-2)
+
+#define DEVDRV_USBF_WRITEEND (0)
+#define DEVDRV_USBF_WRITESHRT (1)
+#define DEVDRV_USBF_WRITING (2)
+#define DEVDRV_USBF_WRITEDMA (3)
+
+#define DEVDRV_USBF_FIFOERROR (0xffff)
+
+#define DEVDRV_USBF_PIPE_IDLE (0x00)
+#define DEVDRV_USBF_PIPE_WAIT (0x01)
+#define DEVDRV_USBF_PIPE_DONE (0x02)
+#define DEVDRV_USBF_PIPE_NORES (0x03)
+#define DEVDRV_USBF_PIPE_STALL (0x04)
+
+#define DEVDRV_USBF_PID_NAK (0x0000u)
+#define DEVDRV_USBF_PID_BUF (0x0001u)
+#define DEVDRV_USBF_PID_STALL (0x0002u)
+#define DEVDRV_USBF_PID_STALL2 (0x0003u)
+
+#define USB_FUNCTION_NON_SPEED (0)
+#define USB_FUNCTION_LOW_SPEED (1)
+#define USB_FUNCTION_FULL_SPEED (2)
+#define USB_FUNCTION_HIGH_SPEED (3)
+
+#define USB_FUNCTION_READEND (0)
+#define USB_FUNCTION_READSHRT (1)
+#define USB_FUNCTION_READING (2)
+#define USB_FUNCTION_READOVER (3)
+#define USB_FUNCTION_READZERO (4)
+
+#define USB_FUNCTION_MAX_PIPE_NO (15u)
+#define USB_FUNCTION_PIPE0 (0)
+#define USB_FUNCTION_PIPE1 (1)
+#define USB_FUNCTION_PIPE2 (2)
+#define USB_FUNCTION_PIPE3 (3)
+#define USB_FUNCTION_PIPE4 (4)
+#define USB_FUNCTION_PIPE5 (5)
+#define USB_FUNCTION_PIPE6 (6)
+#define USB_FUNCTION_PIPE7 (7)
+#define USB_FUNCTION_PIPE8 (8)
+#define USB_FUNCTION_PIPE9 (9)
+#define USB_FUNCTION_PIPEA (10)
+#define USB_FUNCTION_PIPEB (11)
+#define USB_FUNCTION_PIPEC (12)
+#define USB_FUNCTION_PIPED (13)
+#define USB_FUNCTION_PIPEE (14)
+#define USB_FUNCTION_PIPEF (15)
+
+#define USB_FUNCTION_ISO (0xc000u)
+#define USB_FUNCTION_INTERRUPT (0x8000u)
+#define USB_FUNCTION_BULK (0x4000u)
+
+#define USB_FUNCTION_NONE (0x0000u)
+#define USB_FUNCTON_BFREFIELD (0x0400u)
+#define USB_FUNCTION_BFREON (0x0400u)
+#define USB_FUNCTION_BFREOFF (0x0000u)
+#define USB_FUNCTION_DBLBFIELD (0x0200u)
+#define USB_FUNCTION_DBLBON (0x0200u)
+#define USB_FUNCTION_DBLBOFF (0x0000u)
+#define USB_FUNCTION_CNTMDFIELD (0x0100u)
+#define USB_FUNCTION_CNTMDON (0x0100u)
+#define USB_FUNCTION_CNTMDOFF (0x0000u)
+#define USB_FUNCTION_SHTNAKON (0x0080u)
+#define USB_FUNCTION_SHTNAKOFF (0x0000u)
+#define USB_FUNCTION_DIRFIELD (0x0010u)
+#define USB_FUNCTION_DIR_P_OUT (0x0000u)
+#define USB_FUNCTION_DIR_P_IN (0x0010u)
+#define USB_FUNCTION_EPNUMFIELD (0x000fu)
+#define USB_FUNCTION_MAX_EP_NO (15u)
+#define USB_FUNCTION_EP0 (0u)
+#define USB_FUNCTION_EP1 (1u)
+#define USB_FUNCTION_EP2 (2u)
+#define USB_FUNCTION_EP3 (3u)
+#define USB_FUNCTION_EP4 (4u)
+#define USB_FUNCTION_EP5 (5u)
+#define USB_FUNCTION_EP6 (6u)
+#define USB_FUNCTION_EP7 (7u)
+#define USB_FUNCTION_EP8 (8u)
+#define USB_FUNCTION_EP9 (9u)
+#define USB_FUNCTION_EP10 (10u)
+#define USB_FUNCTION_EP11 (11u)
+#define USB_FUNCTION_EP12 (12u)
+#define USB_FUNCTION_EP13 (13u)
+#define USB_FUNCTION_EP14 (14u)
+#define USB_FUNCTION_EP15 (15u)
+
+#define USB_FUNCTION_EPTABLE_LENGTH (5u)
+
+#define USB_FUNCTION_CUSE (0)
+#define USB_FUNCTION_D0USE (1)
+#define USB_FUNCTION_D0DMA (2)
+#define USB_FUNCTION_D1USE (3)
+#define USB_FUNCTION_D1DMA (4)
+
+#define USB_FUNCTION_CFIFO_USE (0x0000)
+#define USB_FUNCTION_D0FIFO_USE (0x1000)
+#define USB_FUNCTION_D1FIFO_USE (0x2000)
+#define USB_FUNCTION_D0FIFO_DMA (0x5000)
+#define USB_FUNCTION_D1FIFO_DMA (0x6000)
+
+#define USB_FUNCTION_BUF2FIFO (0)
+#define USB_FUNCTION_FIFO2BUF (1)
+
+#define USB_FUNCTION_DVST_POWERED (0x0001)
+#define USB_FUNCTION_DVST_DEFAULT (0x0002)
+#define USB_FUNCTION_DVST_ADDRESS (0x0003)
+#define USB_FUNCTION_DVST_CONFIGURED (0x0004)
+#define USB_FUNCTION_DVST_SUSPEND (0x0005)
+#define USB_FUNCTION_DVST_CONFIGURED_SUSPEND (0x0006)
+
+#define USB_FUNCTION_FUNCTION_TEST_SELECT (0xff00u)
+#define USB_FUNCTION_FUNCTION_TEST_J (0x0100u)
+#define USB_FUNCTION_FUNCTION_TEST_K (0x0200u)
+#define USB_FUNCTION_FUNCTION_TEST_SE0_NAK (0x0300u)
+#define USB_FUNCTION_FUNCTION_TEST_PACKET (0x0400u)
+#define USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE (0x0500u)
+#define USB_FUNCTION_FUNCTION_TEST_STSelectors (0x0600u)
+#define USB_FUNCTION_FUNCTION_TEST_Reserved (0x4000u)
+#define USB_FUNCTION_FUNCTION_TEST_VSTModes (0xc000u)
+
+#define USB_FUNCTION_DT_TYPE (0xff00u)
+#define USB_FUNCTION_DT_INDEX (0xff)
+#define USB_FUNCTION_DT_DEVICE (0x01)
+#define USB_FUNCTION_DT_CONFIGURATION (0x02)
+#define USB_FUNCTION_DT_STRING (0x03)
+#define USB_FUNCTION_DT_INTERFACE (0x04)
+#define USB_FUNCTION_DT_ENDPOINT (0x05)
+#define USB_FUNCTION_DT_DEVICE_QUALIFIER (0x06)
+#define USB_FUNCTION_DT_OTHER_SPEED_CONFIGURATION (0x07)
+#define USB_FUNCTION_DT_INTERFACE_POWER (0x08)
+
+#define USB_FUNCTION_CF_RESERVED (0x80)
+#define USB_FUNCTION_CF_SELF (0x40)
+#define USB_FUNCTION_CF_RWUP (0x20)
+#define USB_FUNCTION_CF_NORWUP (0x00)
+#define USB_FUNCTION_EP_ERROR (0xff)
+
+#define USB_FUNCTION_EP_OUT (0x00)
+#define USB_FUNCTION_EP_IN (0x80)
+#define USB_FUNCTION_EP_CNTRL (0x00)
+#define USB_FUNCTION_EP_ISO (0x01)
+#define USB_FUNCTION_EP_BULK (0x02)
+#define USB_FUNCTION_EP_INT (0x03)
+
+#define USB_FUNCTION_STANDARD_REQUEST (0x0000u)
+#define USB_FUNCTION_CLASS_REQUEST (0x0020u)
+#define USB_FUNCTION_VENDOR_REQUEST (0x0040u)
+#define USB_FUNCTION_DEVICE_REQUEST (0x0000u)
+#define USB_FUNCTION_INTERFACE_REQUEST (0x0001u)
+#define USB_FUNCTION_ENDPOINT_REQUEST (0x0002u)
+
+#define USB_FUNCTION_GETSTATUS_BUSPOWERD (0x0000u)
+#define USB_FUNCTION_GETSTATUS_SELFPOWERD (0x0001u)
+#define USB_FUNCTION_GETSTATUS_REMOTEWAKEUP (0x0002u)
+#define USB_FUNCTION_GETSTATUS_NOTHALT (0x0000u)
+#define USB_FUNCTION_GETSTATUS_HALT (0x0001u)
+
+#define USB_FUNCTION_FEATURE_ENDPOINT_HALT (0x0000u)
+#define USB_FUNCTION_FEATURE_REMOTE_WAKEUP (0x0001u)
+#define USB_FUNCTION_FEATURE_TEST_MODE (0x0002u)
+
+#define USB_FUNCTION_bRequest (0xff00u) /* b15-8:bRequest */
+#define USB_FUNCTION_bmRequestType (0x00ffu) /* b7-0: bmRequestType */
+#define USB_FUNCTION_bmRequestTypeDir (0x0080u) /* b7 : Data transfer direction */
+#define USB_FUNCTION_bmRequestTypeType (0x0060u) /* b6-5: Type */
+#define USB_FUNCTION_bmRequestTypeRecip (0x001fu) /* b4-0: Recipient */
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+#if 0
+void R_USB_api_function_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t R_USB_api_function_IsConfigured(uint16_t root);
+uint16_t R_USB_api_function_CtrlReadStart(uint16_t root, uint32_t size, uint8_t *data);
+void R_USB_api_function_CtrlWriteStart(uint16_t root, uint32_t size, uint8_t *data);
+uint16_t R_USB_api_function_start_send_transfer(uint16_t root, uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t R_USB_api_function_check_pipe_status(uint16_t root, uint16_t pipe, uint32_t *size);
+void R_USB_api_function_clear_pipe_status(uint16_t root, uint16_t pipe);
+void R_USB_api_function_start_receive_transfer(uint16_t root, uint16_t pipe, uint32_t size, uint8_t *data);
+void R_USB_api_function_set_pid_buf(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_pid_nak(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_pid_stall(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_pid_stall(uint16_t root, uint16_t pipe);
+uint16_t R_USB_api_function_get_pid(uint16_t root, uint16_t pipe);
+int32_t R_USB_api_function_check_stall(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_sqclr(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_sqset(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_csclr(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_curpipe(uint16_t root, uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void R_USB_api_function_clear_brdy_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_bemp_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_nrdy_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_brdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_brdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_bemp_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_bemp_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_nrdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_nrdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_stop_transfer(uint16_t root, uint16_t pipe);
+#endif
+
+#ifdef USB0_FUNCTION_API_H
+void usb0_function_interrupt(uint32_t int_sense);
+void usb0_function_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb0_function_dma_interrupt_d1fifo(uint32_t int_sense);
+
+void usb0_function_Class0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_ResetDescriptor(uint16_t mode);
+
+IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid(void);
+IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_function_attach(void);
+void Userdef_USB_usb0_function_detach(void);
+void Userdef_USB_usb0_function_delay_1ms(void);
+void Userdef_USB_usb0_function_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_function_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_function_delay_500ns(void);
+void Userdef_USB_usb0_function_start_dma(USB_FUNCTION_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_function_stop_dma0(void);
+uint32_t Userdef_USB_usb0_function_stop_dma1(void);
+
+void usb0_function_stop_transfer(uint16_t pipe);
+void usb0_function_enable_brdy_int(uint16_t pipe);
+void usb0_function_disable_brdy_int(uint16_t pipe);
+void usb0_function_enable_bemp_int(uint16_t pipe);
+void usb0_function_disable_bemp_int(uint16_t pipe);
+void usb0_function_enable_nrdy_int(uint16_t pipe);
+void usb0_function_disable_nrdy_int(uint16_t pipe);
+#endif
+
+#ifdef USB1_FUNCTION_API_H
+void usb1_function_interrupt(uint32_t int_sense);
+void usb1_function_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb1_function_dma_interrupt_d1fifo(uint32_t int_sense);
+
+void usb1_function_Class0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_ResetDescriptor(uint16_t mode);
+
+uint16_t Userdef_USB_usb1_function_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_function_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_function_attach(void);
+void Userdef_USB_usb1_function_detach(void);
+void Userdef_USB_usb1_function_delay_1ms(void);
+void Userdef_USB_usb1_function_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_function_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_function_delay_500ns(void);
+void Userdef_USB_usb1_function_start_dma(USB_FUNCTION_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_function_stop_dma0(void);
+uint32_t Userdef_USB_usb1_function_stop_dma1(void);
+
+void usb1_function_stop_transfer(uint16_t pipe);
+void usb1_function_enable_brdy_int(uint16_t pipe);
+void usb1_function_disable_brdy_int(uint16_t pipe);
+void usb1_function_enable_bemp_int(uint16_t pipe);
+void usb1_function_disable_bemp_int(uint16_t pipe);
+void usb1_function_enable_nrdy_int(uint16_t pipe);
+void usb1_function_disable_nrdy_int(uint16_t pipe);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h
new file mode 100644
index 000000000..090e51c10
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_FUNCTION_H
+#define USB_FUNCTION_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_FUNCTION_ALT_NO (255)
+#define USB_FUNCTION_ALT_SET (0xff)
+
+#define USB_FUNCTION_BITUPLLE (0x0002u)
+#define USB_FUNCTION_BITUCKSEL (0x0004u)
+#define USB_FUNCTION_BITBWAIT (0x003fu)
+
+#define USB_FUNCTION_BUSWAIT_02 (0x0000u)
+#define USB_FUNCTION_BUSWAIT_03 (0x0001u)
+#define USB_FUNCTION_BUSWAIT_04 (0x0002u)
+#define USB_FUNCTION_BUSWAIT_05 (0x0003u)
+#define USB_FUNCTION_BUSWAIT_06 (0x0004u)
+#define USB_FUNCTION_BUSWAIT_07 (0x0005u)
+#define USB_FUNCTION_BUSWAIT_08 (0x0006u)
+#define USB_FUNCTION_BUSWAIT_09 (0x0007u)
+#define USB_FUNCTION_BUSWAIT_10 (0x0008u)
+#define USB_FUNCTION_BUSWAIT_11 (0x0009u)
+#define USB_FUNCTION_BUSWAIT_12 (0x000au)
+#define USB_FUNCTION_BUSWAIT_13 (0x000bu)
+#define USB_FUNCTION_BUSWAIT_14 (0x000cu)
+#define USB_FUNCTION_BUSWAIT_15 (0x000du)
+#define USB_FUNCTION_BUSWAIT_16 (0x000eu)
+#define USB_FUNCTION_BUSWAIT_17 (0x000fu)
+
+#define USB_FUNCTION_BITRESUME (0x0020u)
+#define USB_FUNCTION_BITUACT (0x0010u)
+#define USB_FUNCTION_HSPROC (0x0004u)
+#define USB_FUNCTION_HSMODE (0x0003u)
+#define USB_FUNCTION_FSMODE (0x0002u)
+#define USB_FUNCTION_LSMODE (0x0001u)
+#define USB_FUNCTION_UNDECID (0x0000u)
+
+#define USB_FUNCTION_BITRCNT (0x8000u)
+#define USB_FUNCTION_BITDREQE (0x1000u)
+#define USB_FUNCTION_BITMBW (0x0c00u)
+#define USB_FUNCTION_BITMBW_8 (0x0000u)
+#define USB_FUNCTION_BITMBW_16 (0x0400u)
+#define USB_FUNCTION_BITMBW_32 (0x0800u)
+#define USB_FUNCTION_BITBYTE_LITTLE (0x0000u)
+#define USB_FUNCTION_BITBYTE_BIG (0x0100u)
+#define USB_FUNCTION_BITISEL (0x0020u)
+#define USB_FUNCTION_BITCURPIPE (0x000fu)
+
+#define USB_FUNCTION_CFIFO_READ (0x0000u)
+#define USB_FUNCTION_CFIFO_WRITE (0x0020u)
+
+#define USB_FUNCTION_BITBVAL (0x8000u)
+#define USB_FUNCTION_BITBCLR (0x4000u)
+#define USB_FUNCTION_BITFRDY (0x2000u)
+#define USB_FUNCTION_BITDTLN (0x0fffu)
+
+#define USB_FUNCTION_BITVBSE (0x8000u)
+#define USB_FUNCTION_BITRSME (0x4000u)
+#define USB_FUNCTION_BITSOFE (0x2000u)
+#define USB_FUNCTION_BITDVSE (0x1000u)
+#define USB_FUNCTION_BITCTRE (0x0800u)
+#define USB_FUNCTION_BITVBINT (0x8000u)
+#define USB_FUNCTION_BITRESM (0x4000u)
+#define USB_FUNCTION_BITSOFR (0x2000u)
+#define USB_FUNCTION_BITDVST (0x1000u)
+#define USB_FUNCTION_BITCTRT (0x0800u)
+
+#define USB_FUNCTION_BITBEMPE (0x0400u)
+#define USB_FUNCTION_BITNRDYE (0x0200u)
+#define USB_FUNCTION_BITBRDYE (0x0100u)
+#define USB_FUNCTION_BITBEMP (0x0400u)
+#define USB_FUNCTION_BITNRDY (0x0200u)
+#define USB_FUNCTION_BITBRDY (0x0100u)
+
+#define USB_FUNCTION_BITDVSQ (0x0070u)
+#define USB_FUNCTION_BITDVSQS (0x0030u)
+#define USB_FUNCTION_DS_SPD_CNFG (0x0070u)
+#define USB_FUNCTION_DS_SPD_ADDR (0x0060u)
+#define USB_FUNCTION_DS_SPD_DFLT (0x0050u)
+#define USB_FUNCTION_DS_SPD_POWR (0x0040u)
+#define USB_FUNCTION_DS_CNFG (0x0030u)
+#define USB_FUNCTION_DS_ADDS (0x0020u)
+#define USB_FUNCTION_DS_DFLT (0x0010u)
+#define USB_FUNCTION_DS_POWR (0x0000u)
+#define USB_FUNCTION_BITVALID (0x0008u)
+#define USB_FUNCTION_BITCTSQ (0x0007u)
+#define USB_FUNCTION_CS_SQER (0x0006u)
+#define USB_FUNCTION_CS_WRND (0x0005u)
+#define USB_FUNCTION_CS_WRSS (0x0004u)
+#define USB_FUNCTION_CS_WRDS (0x0003u)
+#define USB_FUNCTION_CS_RDSS (0x0002u)
+#define USB_FUNCTION_CS_RDDS (0x0001u)
+#define USB_FUNCTION_CS_IDST (0x0000u)
+
+#define USB_FUNCTION_PIPExBUF (64u)
+
+#define USB_FUNCTION_D0FIFO (0)
+#define USB_FUNCTION_D1FIFO (1)
+#define USB_FUNCTION_DMA_READY (0)
+#define USB_FUNCTION_DMA_BUSY (1)
+#define USB_FUNCTION_DMA_BUSYEND (2)
+
+#define USB_FUNCTION_FIFO_USE (0x7000)
+
+#endif /* USB_FUNCTION_FUNCTION_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h
new file mode 100644
index 000000000..d26e3b083
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_function_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+
+#define USB_FUNCTION_LOCAL_Rev "VER080_140709"
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h
new file mode 100644
index 000000000..02855eb13
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h
@@ -0,0 +1,171 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_H
+#define USB0_FUNCTION_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_function_api.h"
+#include "usb_function.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb0_function_bit_set[];
+extern uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb0_function_PipeIgnore[];
+extern uint16_t g_usb0_function_PipeTbl[];
+extern uint16_t g_usb0_function_pipe_status[];
+extern uint32_t g_usb0_function_PipeDataSize[];
+
+extern USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[];
+extern uint16_t g_usb0_function_DmaPipe[];
+extern uint16_t g_usb0_function_DmaBval[];
+extern uint16_t g_usb0_function_DmaStatus[];
+
+extern uint16_t g_usb0_function_CtrZeroLengthFlag;
+
+extern uint16_t g_usb0_function_ConfigNum;
+extern uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO];
+extern uint16_t g_usb0_function_RemoteWakeupFlag;
+extern uint16_t g_usb0_function_TestModeFlag;
+extern uint16_t g_usb0_function_TestModeSelectors;
+
+extern uint16_t g_usb0_function_ReqType;
+extern uint16_t g_usb0_function_ReqTypeType;
+extern uint16_t g_usb0_function_ReqTypeRecip;
+extern uint16_t g_usb0_function_ReqRequest;
+extern uint16_t g_usb0_function_ReqValue;
+extern uint16_t g_usb0_function_ReqIndex;
+extern uint16_t g_usb0_function_ReqLength;
+
+extern uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+extern uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+/* ==== common ==== */
+void usb0_function_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb0_function_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb0_function_is_hispeed(void);
+uint16_t usb0_function_is_hispeed_enable(void);
+uint16_t usb0_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_function_write_buffer(uint16_t pipe);
+uint16_t usb0_function_write_buffer_c(uint16_t pipe);
+uint16_t usb0_function_write_buffer_d0(uint16_t pipe);
+uint16_t usb0_function_write_buffer_d1(uint16_t pipe);
+void usb0_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_function_read_buffer(uint16_t pipe);
+uint16_t usb0_function_read_buffer_c(uint16_t pipe);
+uint16_t usb0_function_read_buffer_d0(uint16_t pipe);
+uint16_t usb0_function_read_buffer_d1(uint16_t pipe);
+uint16_t usb0_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb0_function_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb0_function_read_dma(uint16_t pipe);
+void usb0_function_brdy_int(uint16_t status, uint16_t int_enb);
+void usb0_function_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb0_function_bemp_int(uint16_t status, uint16_t int_enb);
+void usb0_function_setting_interrupt(uint8_t level);
+void usb0_function_reset_module(uint16_t clockmode);
+uint16_t usb0_function_get_buf_size(uint16_t pipe);
+uint16_t usb0_function_get_mxps(uint16_t pipe);
+void usb0_function_clear_brdy_sts(uint16_t pipe);
+void usb0_function_clear_bemp_sts(uint16_t pipe);
+void usb0_function_clear_nrdy_sts(uint16_t pipe);
+void usb0_function_set_pid_buf(uint16_t pipe);
+void usb0_function_set_pid_nak(uint16_t pipe);
+void usb0_function_set_pid_stall(uint16_t pipe);
+void usb0_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_function_get_pid(uint16_t pipe);
+void usb0_function_set_sqclr(uint16_t pipe);
+void usb0_function_set_sqset(uint16_t pipe);
+void usb0_function_set_csclr(uint16_t pipe);
+void usb0_function_aclrm(uint16_t pipe);
+void usb0_function_set_aclrm(uint16_t pipe);
+void usb0_function_clr_aclrm(uint16_t pipe);
+uint16_t usb0_function_get_sqmon(uint16_t pipe);
+uint16_t usb0_function_get_inbuf(uint16_t pipe);
+
+/* ==== function ==== */
+void usb0_function_init_status(void);
+void usb0_function_InitModule(uint16_t mode);
+uint16_t usb0_function_CheckVBUStaus(void);
+void usb0_function_USB_FUNCTION_Attach(void);
+void usb0_function_USB_FUNCTION_Detach(void);
+void usb0_function_USB_FUNCTION_BusReset(void);
+void usb0_function_USB_FUNCTION_Resume(void);
+void usb0_function_USB_FUNCTION_Suspend(void);
+void usb0_function_USB_FUNCTION_TestMode(void);
+void usb0_function_ResetDCP(void);
+void usb0_function_ResetEP(uint16_t num);
+uint16_t usb0_function_EpToPipe(uint16_t ep);
+void usb0_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num);
+uint16_t usb0_function_GetConfigNum(void);
+uint16_t usb0_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num);
+uint16_t usb0_function_CheckRemoteWakeup(void);
+void usb0_function_clear_alt(void);
+void usb0_function_clear_pipe_tbl(void);
+void usb0_function_clear_ep_table_index(void);
+uint16_t usb0_function_GetInterfaceNum(uint16_t num);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB0_FUNCTION_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h
new file mode 100644
index 000000000..c33b3e63e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_API_H
+#define USB0_FUNCTION_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb0_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t usb0_api_function_IsConfigured(void);
+uint16_t usb0_function_GetDeviceState(void);
+uint16_t usb0_api_function_CtrlReadStart(uint32_t size, uint8_t *data);
+void usb0_api_function_CtrlWriteStart(uint32_t size, uint8_t *data);
+uint16_t usb0_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_api_function_check_pipe_status(uint16_t pipe, uint32_t *size);
+void usb0_api_function_clear_pipe_status(uint16_t pipe);
+void usb0_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+void usb0_api_function_set_pid_buf(uint16_t pipe);
+void usb0_api_function_set_pid_nak(uint16_t pipe);
+void usb0_api_function_set_pid_stall(uint16_t pipe);
+void usb0_api_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_api_function_get_pid(uint16_t pipe);
+int32_t usb0_api_function_check_stall(uint16_t pipe);
+void usb0_api_function_set_sqclr(uint16_t pipe);
+void usb0_api_function_set_sqset(uint16_t pipe);
+void usb0_api_function_set_csclr(uint16_t pipe);
+void usb0_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_api_function_clear_brdy_sts(uint16_t pipe);
+void usb0_api_function_clear_bemp_sts(uint16_t pipe);
+void usb0_api_function_clear_nrdy_sts(uint16_t pipe);
+
+void usb0_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB0_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h
new file mode 100644
index 000000000..d74bac718
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_DMACDRV_H
+#define USB0_FUNCTION_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb0_function_DMAC1_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_function_DMAC1_Open(uint32_t req);
+void usb0_function_DMAC1_Close(uint32_t *remain);
+void usb0_function_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_function_DMAC2_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_function_DMAC2_Open(uint32_t req);
+void usb0_function_DMAC2_Close(uint32_t *remain);
+void usb0_function_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB0_FUNCTION_DMACDRV_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c
new file mode 100644
index 000000000..2f283c738
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c
@@ -0,0 +1,2933 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)];
+
+static void usb0_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_function_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_function_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_function_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_function_write_dma_d1(uint16_t pipe);
+
+static void usb0_function_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb0_function_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb0_function_clear_transaction_counter(uint16_t pipe);
+static void usb0_function_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_function_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_function_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ usb0_function_clear_bemp_sts(pipe);
+ usb0_function_clear_brdy_sts(pipe);
+ usb0_function_clear_nrdy_sts(pipe);
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ case USB_FUNCTION_D0FIFO_DMA:
+ usefifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ case USB_FUNCTION_D1FIFO_DMA:
+ usefifo = USB_FUNCTION_D1USE;
+ break;
+
+ default:
+ usefifo = USB_FUNCTION_CUSE;
+ break;
+ };
+
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_clear_transaction_counter(pipe);
+
+ usb0_function_aclrm(pipe);
+
+ status = usb0_function_write_buffer(pipe);
+
+ if (status != DEVDRV_USBF_FIFOERROR)
+ {
+ usb0_function_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ status = usb0_function_write_buffer_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ status = usb0_function_write_buffer_d1(pipe);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ status = usb0_function_write_dma_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ status = usb0_function_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb0_function_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb0_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEEND: /* End of data write */
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_function_clear_nrdy_sts(pipe);
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ /* for last transfer */
+ usb0_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEDMA: /* DMA write */
+ usb0_function_clear_nrdy_sts(pipe);
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ if (g_usb0_function_CtrZeroLengthFlag == 1)
+ {
+ g_usb0_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */
+ return DEVDRV_USBF_WRITEEND;
+ }
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+ }
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ g_usb0_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0;
+ }
+
+ dfacc = usb0_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb0_function_data_count[pipe] = 0;
+ g_usb0_function_data_pointer[pipe] += count;
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe;
+ if ((count % size) != 0)
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0;
+ }
+
+ dfacc = usb0_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb0_function_data_count[pipe] = 0;
+ g_usb0_function_data_pointer[pipe] += count;
+
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb0_function_clear_bemp_sts(pipe);
+ usb0_function_clear_brdy_sts(pipe);
+ usb0_function_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb0_function_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb0_function_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ usb0_function_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ usb0_function_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb0_function_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_function_read_dma(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_function_read_dma(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ status = usb0_function_read_buffer_d0(pipe);
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ status = usb0_function_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb0_function_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ status = usb0_function_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb0_function_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READZERO: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ }
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ }
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ g_usb0_function_data_pointer[pipe] += count;
+ g_usb0_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+ uint16_t pipebuf_size;
+
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ g_usb0_function_data_pointer[pipe] += count;
+ g_usb0_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : DEVDRV_USBF_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb0_function_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOCTR;
+ break;
+
+ case USB_FUNCTION_D0USE:
+ case USB_FUNCTION_D0DMA:
+ buffer = USB200.D0FIFOCTR;
+ break;
+
+ case USB_FUNCTION_D1USE:
+ case USB_FUNCTION_D1DMA:
+ buffer = USB200.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return DEVDRV_USBF_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb0_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB200.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB200.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb0_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB200.D0FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D0FIFO.UINT32;
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB200.D1FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.CFIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D0FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D1FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+* : return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb0_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit
+* : : USB_FUNCTION_BITMBW_16 16bit
+* : : USB_FUNCTION_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb0_function_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb0_function_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_FUNCTION_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_FUNCTION_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_FUNCTION_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEATRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEBTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPECTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEDTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEETRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEFTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+ uint16_t fifo;
+
+ usb0_function_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1USE;
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0DMA;
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1DMA;
+ break;
+
+ default:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_CUSE;
+ break;
+ }
+
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16);
+
+ /* Interrupt of pipe set is disabled */
+ usb0_function_disable_brdy_int(pipe);
+ usb0_function_disable_nrdy_int(pipe);
+ usb0_function_disable_bemp_int(pipe);
+
+ usb0_function_aclrm(pipe);
+ usb0_function_set_csclr(pipe);
+
+ if ( g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT )
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_function_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_dfacc_d1
+* Description : Set the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_function_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c
new file mode 100644
index 000000000..cfc8d0f49
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c
@@ -0,0 +1,346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_function_dmaint(uint16_t fifo);
+static void usb0_function_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_function_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB200.D0FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain);
+ g_usb0_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB200.D1FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain);
+ g_usb0_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb0_function_dmaint(USB_FUNCTION_D0FIFO);
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb0_function_dmaint(USB_FUNCTION_D1FIFO);
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_FUNCTION_D0FIFO
+* : ; USB_FUNCTION_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb0_function_DmaPipe[fifo];
+
+ if (g_usb0_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO)
+ {
+ usb0_function_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb0_function_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb0_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb0_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+
+ if (g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+
+ if (g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb0_function_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c
new file mode 100644
index 000000000..827efaed7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c
@@ -0,0 +1,249 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_brdy_int
+* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb0_function_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB200.BRDYSTS = (uint16_t)~pipebit;
+ USB200.BEMPSTS = (uint16_t)~pipebit;
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb0_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_function_read_dma(pipe);
+ usb0_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb0_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_function_read_dma(pipe);
+ usb0_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb0_function_read_buffer(pipe);
+ }
+ else
+ {
+ usb0_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_nrdy_int
+* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_function_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT)
+ {
+ pid = usb0_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ g_usb0_function_PipeIgnore[pipe]++;
+ if (g_usb0_function_PipeIgnore[pipe] == 3)
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+ else
+ {
+ usb0_function_set_pid_buf(pipe);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_bemp_int
+* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_function_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe])
+ {
+ pid = usb0_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ inbuf = usb0_function_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb0_function_disable_bemp_int(pipe);
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c
new file mode 100644
index 000000000..e3d318b98
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c
@@ -0,0 +1,2026 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB200.BRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB200.BRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB200.BRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB200.BEMPENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB200.BEMPENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB200.BEMPSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB200.NRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB200.NRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB200.NRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed
+* : USB_FUNCTION_FULL_SPEED ; Full-Speed
+* : LOW_SPEED ; Low-Speed
+* : USB_FUNCTION_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb0_function_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST);
+
+ if (rhst == USB_FUNCTION_HSMODE)
+ {
+ speed = USB_FUNCTION_HIGH_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_FSMODE)
+ {
+ speed = USB_FUNCTION_FULL_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_LSMODE)
+ {
+ speed = USB_FUNCTION_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_FUNCTION_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable
+* : DEVDRV_USBF_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_function_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = DEVDRV_USBF_NO;
+
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1)
+ {
+ ret = DEVDRV_USBF_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb0_function_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb0_function_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+ Userdef_USB_usb0_function_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_pid_stall (uint16_t pipe)
+{
+ usb0_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pid = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ /* PIPEA-F have not CSCLR */
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_function_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_aclrm (uint16_t pipe)
+{
+ usb0_function_set_aclrm(pipe);
+ usb0_function_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_function_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ;interrupt level
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_setting_interrupt (uint8_t level)
+{
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_function_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI0, level);
+ R_INTC_Enable(INTC_ID_USBI0);
+
+ d0fifo_dmaintid = Userdef_USB_usb0_function_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_function_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb0_function_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_function_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_function_reset_module (uint16_t clockmode)
+{
+ /* UPLLE bit is only USB0 */
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB200.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_function_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb0_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_function_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ return size;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c
new file mode 100644
index 000000000..369b2bea6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c
@@ -0,0 +1,441 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_function_init
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint8_t int_level ; interruput level
+* : uint16_t mode : Speed modes
+* : : USB_FUCNTION_HIGH_SPEED: High-speed device
+* : : USB_FUCNTION_FULL_SPEED: Full-speed device
+* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfd; /* The clock of USB0 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ usb0_function_setting_interrupt(int_level);
+
+ usb0_function_reset_module(clockmode); /* reset USB module with setting tranciever */
+ /* and HSE=1 */
+
+ usb0_function_init_status(); /* clear variables */
+
+ usb0_function_InitModule(mode); /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_function_IsConfigured
+* Description : Checks if the USB device is configured to return the result as
+* : the return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend
+* : DEVDRV_USBF_NO : not Configured
+*******************************************************************************/
+uint16_t usb0_api_function_IsConfigured (void)
+{
+ uint16_t dvst;
+
+ dvst = usb0_function_GetDeviceState();
+
+ if ((dvst == USB_FUNCTION_DVST_CONFIGURED) ||
+ (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND))
+ {
+ return DEVDRV_USBF_YES;
+ }
+
+ return DEVDRV_USBF_NO;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_GetDeviceState
+* Description : Returns the state of USB device.
+* Arguments : none
+* Return Value : Device States
+*******************************************************************************/
+uint16_t usb0_function_GetDeviceState (void)
+{
+ uint16_t dvsq;
+ uint16_t dvst;
+
+ dvsq = USB200.INTSTS0;
+ switch(dvsq & USB_FUNCTION_BITDVSQ)
+ {
+ case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */
+ dvst = USB_FUNCTION_DVST_POWERED;
+ break;
+
+ case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */
+ dvst = USB_FUNCTION_DVST_DEFAULT;
+ break;
+
+ case USB_FUNCTION_DS_ADDS: /* Address state */
+ dvst = USB_FUNCTION_DVST_ADDRESS;
+ break;
+
+ case USB_FUNCTION_DS_CNFG: /* Configured state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED;
+ break;
+
+ case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND;
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */
+ case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */
+ case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+
+ default: /* error */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+ }
+
+ return dvst;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ usb0_function_start_receive_transfer(pipe, size, data);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+
+ status = usb0_function_start_send_transfer(pipe, size, data);
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_check_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *size ; Data Size
+* Return Value : Pipe Status
+*******************************************************************************/
+uint16_t usb0_api_function_check_pipe_status (uint16_t pipe, uint32_t * size)
+{
+ if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE)
+ {
+ *size = g_usb0_function_PipeDataSize[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_DONE;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_NORES;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_STALL;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_FIFOERROR;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return g_usb0_function_pipe_status[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Pipe Status
+*******************************************************************************/
+void usb0_api_function_clear_pipe_status (uint16_t pipe)
+{
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_buf (uint16_t pipe)
+{
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_nak (uint16_t pipe)
+{
+ usb0_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_stall (uint16_t pipe)
+{
+ usb0_function_set_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_pid_stall (uint16_t pipe)
+{
+ usb0_function_clear_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_api_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_check_stall
+* Description :
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+int32_t usb0_api_function_check_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL)
+ {
+ return DEVDRV_USBF_STALL;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_sqclr (uint16_t pipe)
+{
+ usb0_function_set_sqclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_sqset (uint16_t pipe)
+{
+ usb0_function_set_sqset(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_csclr (uint16_t pipe)
+{
+ usb0_function_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_curpipe
+* Description : Allocates FIF0 specifed by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ usb0_function_set_curpipe(pipe, fifosel, isel, mbw);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_brdy_sts (uint16_t pipe)
+{
+ usb0_function_clear_brdy_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_bemp_sts (uint16_t pipe)
+{
+ usb0_function_clear_bemp_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_nrdy_sts (uint16_t pipe)
+{
+ usb0_function_clear_nrdy_sts(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c
new file mode 100644
index 000000000..0a9121ab8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_function_CtrlReadStart
+* Description : Executes the USB control read transfer.
+* : USB host controller <- USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; End of data write
+* : DEVDRV_USBF_WRITESHRT ; End of short data write
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_api_function_CtrlReadStart (uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ status = usb0_function_write_buffer_c(USB_FUNCTION_PIPE0);
+
+ /* Peripheral Control sequence */
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */
+ usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_CtrlWriteStart
+* Description : Executes the USB control write transfer.
+* : USB host controller -> USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_CtrlWriteStart (uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb0_function_enable_brdy_int(USB_FUNCTION_PIPE0);
+ usb0_function_set_pid_buf(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c
new file mode 100644
index 000000000..5f1ff018f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c
@@ -0,0 +1,144 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+const uint16_t g_usb0_function_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+uint16_t g_usb0_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint32_t g_usb0_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[2];
+uint16_t g_usb0_function_DmaPipe[2];
+uint16_t g_usb0_function_DmaBval[2];
+uint16_t g_usb0_function_DmaStatus[2];
+
+uint16_t g_usb0_function_CtrZeroLengthFlag;
+
+//uint16_t g_usb0_function_ConfigNum;
+//uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO];
+//uint16_t g_usb0_function_RemoteWakeupFlag;
+uint16_t g_usb0_function_TestModeFlag;
+uint16_t g_usb0_function_TestModeSelectors;
+
+//uint16_t g_usb0_function_ReqType;
+//uint16_t g_usb0_function_ReqTypeType;
+//uint16_t g_usb0_function_ReqTypeRecip;
+//uint16_t g_usb0_function_ReqRequest;
+//uint16_t g_usb0_function_ReqValue;
+//uint16_t g_usb0_function_ReqIndex;
+//uint16_t g_usb0_function_ReqLength;
+
+//uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+* Function Name: usb0_function_init_status
+* Description : Initialization USB Sample Driver Variable.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_init_status (void)
+{
+ uint16_t pipe;
+
+ //g_usb0_function_ConfigNum = 0;
+ //g_usb0_function_RemoteWakeupFlag = DEVDRV_USBF_OFF;
+ g_usb0_function_TestModeFlag = DEVDRV_USBF_OFF;
+ g_usb0_function_CtrZeroLengthFlag = 0;
+
+#if 0
+ usb0_function_clear_alt();
+#endif
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_data_count[pipe] = 0;
+
+ /* pipe configuration in usb0_function_ResetEP() */
+ g_usb0_function_pipecfg[pipe] = 0;
+ g_usb0_function_pipebuf[pipe] = 0;
+ g_usb0_function_pipemaxp[pipe] = 0;
+ g_usb0_function_pipeperi[pipe] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c
new file mode 100644
index 000000000..66949dee6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c
@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_sig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_function_EnableINTModule(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_InitModule
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
+* : ; other ; Full-speed Mode
+* Return Value : none
+*******************************************************************************/
+void usb0_function_InitModule (uint16_t mode)
+{
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* USB function */
+
+ /* USB module operation enabled */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ if (mode == USB_FUNCTION_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE); /* Hi-Speed Mode */
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+
+ /* for power-on */
+ if (usb0_function_CheckVBUStaus() == DEVDRV_USBF_ON)
+ {
+ usb0_function_EnableINTModule(); /* Interrupt Enable */
+ usb0_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
+ }
+ else
+ {
+ usb0_function_USB_FUNCTION_Detach(); /* USB Detach */
+ /* with Interrupt Enable */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_CheckVBUStaus
+* Description : Checks the USB-VBUS state to returns the connection state to
+* : the USB host.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : VBUS ON
+* : DEVDRV_USBF_OFF : VBUS OFF
+*******************************************************************************/
+uint16_t usb0_function_CheckVBUStaus (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ /* monitor VBUS pins */
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb0_function_delay_10us(1);
+ buf2 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb0_function_delay_10us(1);
+ buf3 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ } while ((buf1 != buf2) || (buf2 != buf3));
+
+ if (buf1 == DEVDRV_USBF_OFF)
+ {
+ return DEVDRV_USBF_OFF; /* detach */
+ }
+
+ return DEVDRV_USBF_ON; /* attach */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Attach
+* Description : Connects to the USB host controller.
+* : This function pulls up D+.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_Attach (void)
+{
+ Userdef_USB_usb0_function_attach();
+
+ Userdef_USB_usb0_function_delay_xms(10);
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Detach
+* Description : Disconnects from the USB host controller.
+* : This function opens D+/D-.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_Detach (void)
+{
+ uint16_t pipe;
+
+ Userdef_USB_usb0_function_detach();
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
+ {
+ usb0_function_stop_transfer(pipe);
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* open D+ and D- */
+
+ /* Detach Recovery */
+ Userdef_USB_usb0_function_delay_500ns(); /* need 1us=500ns * 2 wait */
+ Userdef_USB_usb0_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+ Userdef_USB_usb0_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE); /* soft reset module */
+ Userdef_USB_usb0_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ usb0_function_EnableINTModule(); /* Interrupt Enable */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_BusReset
+* Description : This function is executed when the USB device is transitioned
+* : to POWERD_STATE. Sets the device descriptor according to the
+* : connection speed determined by the USB reset hand shake.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_BusReset (void)
+{
+ usb0_function_init_status(); /* memory clear */
+
+ if (usb0_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED)
+ {
+ usb0_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */
+ }
+ else
+ {
+ usb0_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */
+ }
+
+ usb0_function_ResetDCP(); /* Default Control PIPE reset */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Resume
+* Description : This function is executed when the USB device detects a resume
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_Resume (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Suspend
+* Description : This function is executed when the USB device detects a suspend
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_Suspend (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_TestMode
+* Description : This function is executed when the USB device is transitioned U
+* : to TEST_MODE by the USB standard request.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_TestMode (void)
+{
+ switch (g_usb0_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT)
+ {
+ case USB_FUNCTION_FUNCTION_TEST_J:
+ case USB_FUNCTION_FUNCTION_TEST_K:
+ case USB_FUNCTION_FUNCTION_TEST_SE0_NAK:
+ case USB_FUNCTION_FUNCTION_TEST_PACKET:
+ RZA_IO_RegWrite_16(&USB200.TESTMODE,
+ (g_usb0_function_TestModeSelectors >> 8),
+ USB_TESTMODE_UTST_SHIFT,
+ USB_TESTMODE_UTST);
+ break;
+
+ case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE:
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_EnableINTModule
+* Description : Enables USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_EnableINTModule (void)
+{
+ uint16_t buf;
+
+ buf = USB200.INTENB0;
+ buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE |
+ USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE);
+ USB200.INTENB0 = buf;
+
+ usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c
new file mode 100644
index 000000000..df7fbf5bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c
@@ -0,0 +1,453 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_sub.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#if 0
+extern const uint16_t *g_usb0_function_EndPntPtr[];
+extern uint8_t g_usb0_function_DeviceDescriptor[];
+extern uint8_t *g_usb0_function_ConfigurationPtr[];
+#endif
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_ResetDCP
+* Description : Initializes the default control pipe(DCP).
+* Outline : Reset default control pipe
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_ResetDCP (void)
+{
+ USB200.DCPCFG = 0;
+#if 0
+ USB200.DCPMAXP = g_usb0_function_DeviceDescriptor[7];
+#else
+ USB200.DCPMAXP = 64;
+#endif
+
+ USB200.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB200.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB200.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_ResetEP
+* Description : Initializes the end point.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_ResetEP (uint16_t num)
+{
+ uint16_t pipe;
+ uint16_t ep;
+ uint16_t index;
+ uint16_t buf;
+ uint16_t * tbl;
+
+ tbl = (uint16_t *)(g_usb0_function_EndPntPtr[num - 1]);
+
+ for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ if (g_usb0_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR)
+ {
+ index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb0_function_EPTableIndex[ep]);
+ pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE);
+
+ g_usb0_function_PipeTbl[pipe] = (uint16_t)( ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) |
+ ep |
+ (tbl[index + 0] & USB_FUNCTION_FIFO_USE) );
+
+ if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT)
+ {
+ tbl[index + 1] |= USB_FUNCTION_SHTNAKON;
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) ||
+ ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA))
+ {
+ tbl[index + 1] |= USB_FUNCTION_BFREON;
+ }
+#endif
+ }
+
+ /* Interrupt Disable */
+ buf = USB200.BRDYENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.BRDYENB = buf;
+ buf = USB200.NRDYENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.NRDYENB = buf;
+ buf = USB200.BEMPENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.BEMPENB = buf;
+
+ usb0_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.CFIFOSEL,
+ 0,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB200.PIPESEL = pipe;
+ USB200.PIPECFG = tbl[index + 1];
+ USB200.PIPEBUF = tbl[index + 2];
+ USB200.PIPEMAXP = tbl[index + 3];
+ USB200.PIPEPERI = tbl[index + 4];
+
+ g_usb0_function_pipecfg[pipe] = tbl[index + 1];
+ g_usb0_function_pipebuf[pipe] = tbl[index + 2];
+ g_usb0_function_pipemaxp[pipe] = tbl[index + 3];
+ g_usb0_function_pipeperi[pipe] = tbl[index + 4];
+
+ /* Buffer Clear */
+ usb0_function_set_sqclr(pipe);
+ usb0_function_aclrm(pipe);
+
+ /* init Global */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_EpToPipe
+* Description : Returns the pipe which end point specified by the argument is
+* : allocated to.
+* Arguments : uint16_t ep ; Direction + Endpoint Number
+* Return Value : USB_FUNCTION_EP_ERROR : Error
+* : Others : Pipe Number
+*******************************************************************************/
+uint16_t usb0_function_EpToPipe (uint16_t ep)
+{
+ uint16_t pipe;
+
+ for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((g_usb0_function_PipeTbl[pipe] & 0x00ff) == ep)
+ {
+ return pipe;
+ }
+ }
+
+ return USB_FUNCTION_EP_ERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_InitEPTable
+* Description : Sets the end point by the Alternate setting value of the
+* : configuration number and the interface number specified by the
+* : argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* : uint16_t Alt_Num ; Alternate Setting
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num)
+{
+ uint8_t * ptr;
+ uint16_t point_interface;
+ uint16_t point_endpoint;
+ uint16_t length;
+ uint16_t start;
+ uint16_t numbers;
+ uint16_t endpoint;
+
+ ptr = (uint8_t *)g_usb0_function_ConfigurationPtr[Con_Num - 1];
+ point_interface = *ptr;
+ length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2));
+ ptr += *ptr;
+ start = 0;
+ numbers = 0;
+ point_endpoint = 0;
+
+ for (; point_interface < length;)
+ {
+ switch (*(ptr + 1)) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num))
+ {
+ numbers = *(ptr + 4);
+ }
+ else
+ {
+ start += *(ptr + 4);
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ if (point_endpoint < numbers)
+ {
+ endpoint = (uint16_t)(*(ptr + 2) & 0x0f);
+ g_usb0_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint);
+ ++point_endpoint;
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ default: /* Class, Vendor, else */
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetConfigNum
+* Description : Returns the number of configuration referring to the number of
+* : configuration described in the device descriptor.
+* Arguments : none
+* Return Value : Number of possible configurations (bNumConfigurations).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetConfigNum (void)
+{
+ return (uint16_t)g_usb0_function_DeviceDescriptor[17];
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetInterfaceNum
+* Description : Returns the number of interface referring to the number of
+* : interface described in the configuration descriptor.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : Number of this interface (bNumInterfaces).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetInterfaceNum (uint16_t num)
+{
+ return (uint16_t)(*(g_usb0_function_ConfigurationPtr[num - 1] + 4));
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetAltNum
+* Description : Returns the Alternate setting value of the configuration number
+* : and the interface number specified by the argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* Return Value : Value used to select this alternate setting(bAlternateSetting).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num)
+{
+ uint8_t * ptr;
+ uint16_t point;
+ uint16_t alt_num = 0;
+ uint16_t length;
+
+ ptr = (uint8_t *)(g_usb0_function_ConfigurationPtr[Con_Num - 1]);
+ point = ptr[0];
+ ptr += ptr[0]; /* InterfaceDescriptor[0] */
+ length = (uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 2));
+ length |= (uint16_t)((uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8);
+
+ for (; point < length;) /* Search Descriptor Table size */
+ {
+ switch (ptr[1]) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if (Int_Num == ptr[2])
+ {
+ alt_num = (uint16_t)ptr[3]; /* Alternate Number count */
+ }
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ default: /* Class, Vendor, else */
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+ }
+ }
+ return alt_num;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_CheckRemoteWakeup
+* Description : Returns the result of the remote wake up function is supported
+* : or not referring to the configuration descriptor.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup
+* : DEVDRV_USBF_OFF : not Support Remote Wakeup
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_CheckRemoteWakeup (void)
+{
+ uint8_t atr;
+
+ if (g_usb0_function_ConfigNum == 0)
+ {
+ return DEVDRV_USBF_OFF;
+ }
+
+ atr = *(g_usb0_function_ConfigurationPtr[g_usb0_function_ConfigNum - 1] + 7);
+
+ if (atr & USB_FUNCTION_CF_RWUP)
+ {
+ return DEVDRV_USBF_ON;
+ }
+
+ return DEVDRV_USBF_OFF;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_alt
+* Description : Initializes the Alternate setting area.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_clear_alt (void)
+{
+ int i;
+
+ for (i = 0; i < USB_FUNCTION_ALT_NO; ++i)
+ {
+ g_usb0_function_Alternate[i] = 0; /* Alternate */
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_pipe_tbl
+* Description : Initializes pipe definition table.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_pipe_tbl (void)
+{
+ int pipe;
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb0_function_PipeTbl[pipe] = 0;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_ep_table_index
+* Description : Initializes the end point table index.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_clear_ep_table_index (void)
+{
+ int ep;
+
+ for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ g_usb0_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR;
+ }
+}
+#endif
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c
new file mode 100644
index 000000000..5b46b68ee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_function_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID,AM,LVL,REQD */
+ {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC1_CHCFG_n_DAD_SHIFT,
+ DMAC1_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC1_CHCFG_n_SAD_SHIFT,
+ DMAC1_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->dst_size,
+ DMAC1_CHCFG_n_DDS_SHIFT,
+ DMAC1_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->src_size,
+ DMAC1_CHCFG_n_SDS_SHIFT,
+ DMAC1_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DMS_SHIFT,
+ DMAC1_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSEL_SHIFT,
+ DMAC1_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_SBE_SHIFT,
+ DMAC1_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DEM_SHIFT,
+ DMAC1_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_TM_SHIFT,
+ DMAC1_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_SEL_SHIFT,
+ DMAC1_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_HIEN_SHIFT,
+ DMAC1_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_LOEN_SHIFT,
+ DMAC1_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC1_CHCFG_n_AM_SHIFT,
+ DMAC1_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC1_CHCFG_n_LVL_SHIFT,
+ DMAC1_CHCFG_n_LVL);
+
+ if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ req_direction,
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC01_DMARS_CH1_RID_SHIFT,
+ DMAC01_DMARS_CH1_RID);
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC01_DMARS_CH1_MID_SHIFT,
+ DMAC01_DMARS_CH1_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Open
+* Description : Enables DMAC channel 1 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_function_DMAC1_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SETEN_SHIFT,
+ DMAC1_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_STG_SHIFT,
+ DMAC1_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Close
+* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_CLREN_SHIFT,
+ DMAC1_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 1 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 1 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_SR_SHIFT,
+ DMAC1_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+*******************************************************************************/
+void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC2_CHCFG_n_DAD_SHIFT,
+ DMAC2_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC2_CHCFG_n_SAD_SHIFT,
+ DMAC2_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->dst_size,
+ DMAC2_CHCFG_n_DDS_SHIFT,
+ DMAC2_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->src_size,
+ DMAC2_CHCFG_n_SDS_SHIFT,
+ DMAC2_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DMS_SHIFT,
+ DMAC2_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSEL_SHIFT,
+ DMAC2_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_SBE_SHIFT,
+ DMAC2_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DEM_SHIFT,
+ DMAC2_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_TM_SHIFT,
+ DMAC2_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 2,
+ DMAC2_CHCFG_n_SEL_SHIFT,
+ DMAC2_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_HIEN_SHIFT,
+ DMAC2_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_LOEN_SHIFT,
+ DMAC2_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC2_CHCFG_n_AM_SHIFT,
+ DMAC2_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC2_CHCFG_n_LVL_SHIFT,
+ DMAC2_CHCFG_n_LVL);
+ if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ req_direction,
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH2_RID_SHIFT,
+ DMAC23_DMARS_CH2_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH2_MID_SHIFT,
+ DMAC23_DMARS_CH2_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Open
+* Description : Enables DMAC channel 2 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_function_DMAC2_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SETEN_SHIFT,
+ DMAC2_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_STG_SHIFT,
+ DMAC2_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Close
+* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC2_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_CLREN_SHIFT,
+ DMAC2_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 2 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 2 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_SR_SHIFT,
+ DMAC2_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c
new file mode 100644
index 000000000..5449f60c7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c
@@ -0,0 +1,762 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_function_api.h"
+#include "usb0_function_dmacdrv.h" /* common DMAC driver for USB */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_function_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_attach (void)
+{
+ printf("\n");
+ printf("channel 0 attach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_detach (void)
+{
+ printf("\n");
+ printf("channel 0 detach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_1ms (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /*
+ * Wait 1ms (Please change for your MCU).
+ */
+ for (i = 0; i < 1440; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_xms (uint32_t msec)
+{
+ volatile unsigned short i;
+
+ for (i = 0; i < msec; ++i)
+ {
+ Userdef_USB_usb0_function_delay_1ms();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb0_function_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_function_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_FUNCTION_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ usb0_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb0_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_function_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb0_function_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_function_DMAC1_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC1 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_function_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb0_function_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_function_DMAC2_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC2 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_stop_dma0
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_function_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_function_DMAC1_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_function_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_function_DMAC2_Close(&remain);
+
+ return remain;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h
new file mode 100644
index 000000000..de51053c0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h
@@ -0,0 +1,171 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_H
+#define USB1_FUNCTION_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_function_api.h"
+#include "usb_function.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb1_function_bit_set[];
+extern uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb1_function_PipeIgnore[];
+extern uint16_t g_usb1_function_PipeTbl[];
+extern uint16_t g_usb1_function_pipe_status[];
+extern uint32_t g_usb1_function_PipeDataSize[];
+
+extern USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[];
+extern uint16_t g_usb1_function_DmaPipe[];
+extern uint16_t g_usb1_function_DmaBval[];
+extern uint16_t g_usb1_function_DmaStatus[];
+
+extern uint16_t g_usb1_function_CtrZeroLengthFlag;
+
+extern uint16_t g_usb1_function_ConfigNum;
+extern uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
+extern uint16_t g_usb1_function_RemoteWakeupFlag;
+extern uint16_t g_usb1_function_TestModeFlag;
+extern uint16_t g_usb1_function_TestModeSelectors;
+
+extern uint16_t g_usb1_function_ReqType;
+extern uint16_t g_usb1_function_ReqTypeType;
+extern uint16_t g_usb1_function_ReqTypeRecip;
+extern uint16_t g_usb1_function_ReqRequest;
+extern uint16_t g_usb1_function_ReqValue;
+extern uint16_t g_usb1_function_ReqIndex;
+extern uint16_t g_usb1_function_ReqLength;
+
+extern uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+extern uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+/* ==== common ==== */
+void usb1_function_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb1_function_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb1_function_is_hispeed(void);
+uint16_t usb1_function_is_hispeed_enable(void);
+uint16_t usb1_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_function_write_buffer(uint16_t pipe);
+uint16_t usb1_function_write_buffer_c(uint16_t pipe);
+uint16_t usb1_function_write_buffer_d0(uint16_t pipe);
+uint16_t usb1_function_write_buffer_d1(uint16_t pipe);
+void usb1_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_function_read_buffer(uint16_t pipe);
+uint16_t usb1_function_read_buffer_c(uint16_t pipe);
+uint16_t usb1_function_read_buffer_d0(uint16_t pipe);
+uint16_t usb1_function_read_buffer_d1(uint16_t pipe);
+uint16_t usb1_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb1_function_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb1_function_read_dma(uint16_t pipe);
+void usb1_function_brdy_int(uint16_t status, uint16_t int_enb);
+void usb1_function_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb1_function_bemp_int(uint16_t status, uint16_t int_enb);
+void usb1_function_setting_interrupt(uint8_t level);
+void usb1_function_reset_module(uint16_t clockmode);
+uint16_t usb1_function_get_buf_size(uint16_t pipe);
+uint16_t usb1_function_get_mxps(uint16_t pipe);
+void usb1_function_clear_brdy_sts(uint16_t pipe);
+void usb1_function_clear_bemp_sts(uint16_t pipe);
+void usb1_function_clear_nrdy_sts(uint16_t pipe);
+void usb1_function_set_pid_buf(uint16_t pipe);
+void usb1_function_set_pid_nak(uint16_t pipe);
+void usb1_function_set_pid_stall(uint16_t pipe);
+void usb1_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_function_get_pid(uint16_t pipe);
+void usb1_function_set_sqclr(uint16_t pipe);
+void usb1_function_set_sqset(uint16_t pipe);
+void usb1_function_set_csclr(uint16_t pipe);
+void usb1_function_aclrm(uint16_t pipe);
+void usb1_function_set_aclrm(uint16_t pipe);
+void usb1_function_clr_aclrm(uint16_t pipe);
+uint16_t usb1_function_get_sqmon(uint16_t pipe);
+uint16_t usb1_function_get_inbuf(uint16_t pipe);
+
+/* ==== function ==== */
+void usb1_function_init_status(void);
+void usb1_function_InitModule(uint16_t mode);
+uint16_t usb1_function_CheckVBUStaus(void);
+void usb1_function_USB_FUNCTION_Attach(void);
+void usb1_function_USB_FUNCTION_Detach(void);
+void usb1_function_USB_FUNCTION_BusReset(void);
+void usb1_function_USB_FUNCTION_Resume(void);
+void usb1_function_USB_FUNCTION_Suspend(void);
+void usb1_function_USB_FUNCTION_TestMode(void);
+void usb1_function_ResetDCP(void);
+void usb1_function_ResetEP(uint16_t num);
+uint16_t usb1_function_EpToPipe(uint16_t ep);
+void usb1_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num);
+uint16_t usb1_function_GetConfigNum(void);
+uint16_t usb1_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num);
+uint16_t usb1_function_CheckRemoteWakeup(void);
+void usb1_function_clear_alt(void);
+void usb1_function_clear_pipe_tbl(void);
+void usb1_function_clear_ep_table_index(void);
+uint16_t usb1_function_GetInterfaceNum(uint16_t num);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB1_FUNCTION_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h
new file mode 100644
index 000000000..7e78076d9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_API_H
+#define USB1_FUNCTION_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb1_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t usb1_api_function_IsConfigured(void);
+uint16_t usb1_function_GetDeviceState(void);
+uint16_t usb1_api_function_CtrlReadStart(uint32_t size, uint8_t *data);
+void usb1_api_function_CtrlWriteStart(uint32_t size, uint8_t *data);
+uint16_t usb1_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_api_function_check_pipe_status(uint16_t pipe, uint32_t *size);
+void usb1_api_function_clear_pipe_status(uint16_t pipe);
+void usb1_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+void usb1_api_function_set_pid_buf(uint16_t pipe);
+void usb1_api_function_set_pid_nak(uint16_t pipe);
+void usb1_api_function_set_pid_stall(uint16_t pipe);
+void usb1_api_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_api_function_get_pid(uint16_t pipe);
+int32_t usb1_api_function_check_stall(uint16_t pipe);
+void usb1_api_function_set_sqclr(uint16_t pipe);
+void usb1_api_function_set_sqset(uint16_t pipe);
+void usb1_api_function_set_csclr(uint16_t pipe);
+void usb1_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_api_function_clear_brdy_sts(uint16_t pipe);
+void usb1_api_function_clear_bemp_sts(uint16_t pipe);
+void usb1_api_function_clear_nrdy_sts(uint16_t pipe);
+
+void usb1_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB1_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h
new file mode 100644
index 000000000..a4882f8fa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_DMACDRV_H
+#define USB1_FUNCTION_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb1_function_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_function_DMAC3_Open(uint32_t req);
+void usb1_function_DMAC3_Close(uint32_t *remain);
+void usb1_function_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_function_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_function_DMAC4_Open(uint32_t req);
+void usb1_function_DMAC4_Close(uint32_t *remain);
+void usb1_function_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB1_FUNCTION_DMACDRV_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c
new file mode 100644
index 000000000..cf088b60f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c
@@ -0,0 +1,2932 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)];
+
+static void usb1_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_function_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_function_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_function_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_function_write_dma_d1(uint16_t pipe);
+
+static void usb1_function_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb1_function_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb1_function_clear_transaction_counter(uint16_t pipe);
+static void usb1_function_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_function_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_function_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ usb1_function_clear_bemp_sts(pipe);
+ usb1_function_clear_brdy_sts(pipe);
+ usb1_function_clear_nrdy_sts(pipe);
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ case USB_FUNCTION_D0FIFO_DMA:
+ usefifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ case USB_FUNCTION_D1FIFO_DMA:
+ usefifo = USB_FUNCTION_D1USE;
+ break;
+
+ default:
+ usefifo = USB_FUNCTION_CUSE;
+ break;
+ };
+
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_clear_transaction_counter(pipe);
+
+ usb1_function_aclrm(pipe);
+
+ status = usb1_function_write_buffer(pipe);
+
+ if (status != DEVDRV_USBF_FIFOERROR)
+ {
+ usb1_function_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ status = usb1_function_write_buffer_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ status = usb1_function_write_buffer_d1(pipe);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ status = usb1_function_write_dma_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ status = usb1_function_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb1_function_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb1_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEEND: /* End of data write */
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_function_clear_nrdy_sts(pipe);
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ /* for last transfer */
+ usb1_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEDMA: /* DMA write */
+ usb1_function_clear_nrdy_sts(pipe);
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ if (g_usb1_function_CtrZeroLengthFlag == 1)
+ {
+ g_usb1_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */
+ return DEVDRV_USBF_WRITEEND;
+ }
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+ }
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ g_usb1_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0;
+ }
+
+ dfacc = usb1_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb1_function_data_count[pipe] = 0;
+ g_usb1_function_data_pointer[pipe] += count;
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe;
+ if ((count % size) != 0)
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0;
+ }
+
+ dfacc = usb1_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb1_function_data_count[pipe] = 0;
+ g_usb1_function_data_pointer[pipe] += count;
+
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb1_function_clear_bemp_sts(pipe);
+ usb1_function_clear_brdy_sts(pipe);
+ usb1_function_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb1_function_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb1_function_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ usb1_function_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ usb1_function_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb1_function_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_function_read_dma(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_function_read_dma(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ status = usb1_function_read_buffer_d0(pipe);
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ status = usb1_function_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb1_function_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ status = usb1_function_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb1_function_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READZERO: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ }
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ }
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ g_usb1_function_data_pointer[pipe] += count;
+ g_usb1_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ g_usb1_function_data_pointer[pipe] += count;
+ g_usb1_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : DEVDRV_USBF_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb1_function_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOCTR;
+ break;
+
+ case USB_FUNCTION_D0USE:
+ case USB_FUNCTION_D0DMA:
+ buffer = USB201.D0FIFOCTR;
+ break;
+
+ case USB_FUNCTION_D1USE:
+ case USB_FUNCTION_D1DMA:
+ buffer = USB201.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return DEVDRV_USBF_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb1_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB201.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB201.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb1_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB201.D0FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D0FIFO.UINT32;
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB201.D1FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.CFIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D0FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D1FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+* : return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb1_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit
+* : : USB_FUNCTION_BITMBW_16 16bit
+* : : USB_FUNCTION_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb1_function_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb1_function_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_FUNCTION_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_FUNCTION_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_FUNCTION_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEATRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEBTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPECTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEDTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEETRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEFTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+ uint16_t fifo;
+
+ usb1_function_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1USE;
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0DMA;
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1DMA;
+ break;
+
+ default:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_CUSE;
+ break;
+ }
+
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16);
+
+ /* Interrupt of pipe set is disabled */
+ usb1_function_disable_brdy_int(pipe);
+ usb1_function_disable_nrdy_int(pipe);
+ usb1_function_disable_bemp_int(pipe);
+
+ usb1_function_aclrm(pipe);
+ usb1_function_set_csclr(pipe);
+
+ if ( g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT )
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_function_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_dfacc_d1
+* Description : Set the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_function_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c
new file mode 100644
index 000000000..c6f3f1472
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c
@@ -0,0 +1,346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_function_dmaint(uint16_t fifo);
+static void usb1_function_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_function_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB201.D0FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
+ g_usb1_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB201.D1FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
+ g_usb1_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb1_function_dmaint(USB_FUNCTION_D0FIFO);
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb1_function_dmaint(USB_FUNCTION_D1FIFO);
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_FUNCTION_D0FIFO
+* : ; USB_FUNCTION_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb1_function_DmaPipe[fifo];
+
+ if (g_usb1_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO)
+ {
+ usb1_function_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb1_function_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb1_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb1_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+
+ if (g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+
+ if (g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb1_function_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c
new file mode 100644
index 000000000..bdcc9a8f7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c
@@ -0,0 +1,249 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_brdy_int
+* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb1_function_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB201.BRDYSTS = (uint16_t)~pipebit;
+ USB201.BEMPSTS = (uint16_t)~pipebit;
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb1_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_function_read_dma(pipe);
+ usb1_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb1_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_function_read_dma(pipe);
+ usb1_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb1_function_read_buffer(pipe);
+ }
+ else
+ {
+ usb1_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_nrdy_int
+* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_function_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT)
+ {
+ pid = usb1_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ g_usb1_function_PipeIgnore[pipe]++;
+ if (g_usb1_function_PipeIgnore[pipe] == 3)
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+ else
+ {
+ usb1_function_set_pid_buf(pipe);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_bemp_int
+* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_function_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
+ {
+ pid = usb1_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ inbuf = usb1_function_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb1_function_disable_bemp_int(pipe);
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c
new file mode 100644
index 000000000..d448dc599
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c
@@ -0,0 +1,2044 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB201.BRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB201.BRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB201.BRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB201.BEMPENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB201.BEMPENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB201.BEMPSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB201.NRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB201.NRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB201.NRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed
+* : USB_FUNCTION_FULL_SPEED ; Full-Speed
+* : LOW_SPEED ; Low-Speed
+* : USB_FUNCTION_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb1_function_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST);
+
+ if (rhst == USB_FUNCTION_HSMODE)
+ {
+ speed = USB_FUNCTION_HIGH_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_FSMODE)
+ {
+ speed = USB_FUNCTION_FULL_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_LSMODE)
+ {
+ speed = USB_FUNCTION_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_FUNCTION_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable
+* : DEVDRV_USBF_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_function_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = DEVDRV_USBF_NO;
+
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1)
+ {
+ ret = DEVDRV_USBF_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb1_function_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb1_function_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+ Userdef_USB_usb1_function_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_pid_stall (uint16_t pipe)
+{
+ usb1_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pid = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ /* PIPEA-F have not CSCLR */
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_function_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_aclrm (uint16_t pipe)
+{
+ usb1_function_set_aclrm(pipe);
+ usb1_function_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_function_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_setting_interrupt (uint8_t level)
+{
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_function_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI1, level);
+ R_INTC_Enable(INTC_ID_USBI1);
+
+ d0fifo_dmaintid = Userdef_USB_usb1_function_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_function_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb1_function_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_function_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_function_reset_module (uint16_t clockmode)
+{
+ /* UPLLE bit is only USB0 */
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB201.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_function_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb1_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_function_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ return size;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c
new file mode 100644
index 000000000..6edb9d2bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c
@@ -0,0 +1,441 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_function_init
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint8_t int_level ; interruput level
+* : uint16_t mode : Speed modes
+* : : USB_FUCNTION_HIGH_SPEED: High-speed device
+* : : USB_FUCNTION_FULL_SPEED: Full-speed device
+* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ usb1_function_setting_interrupt(int_level);
+
+ usb1_function_reset_module(clockmode); /* reset USB module with setting tranciever */
+ /* and HSE=1 */
+
+ usb1_function_init_status(); /* clear variables */
+
+ usb1_function_InitModule(mode); /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_function_IsConfigured
+* Description : Checks if the USB device is configured to return the result as
+* : the return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend
+* : DEVDRV_USBF_NO : not Configured
+*******************************************************************************/
+uint16_t usb1_api_function_IsConfigured (void)
+{
+ uint16_t dvst;
+
+ dvst = usb1_function_GetDeviceState();
+
+ if ((dvst == USB_FUNCTION_DVST_CONFIGURED) ||
+ (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND))
+ {
+ return DEVDRV_USBF_YES;
+ }
+
+ return DEVDRV_USBF_NO;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_GetDeviceState
+* Description : Returns the state of USB device.
+* Arguments : none
+* Return Value : Device States
+*******************************************************************************/
+uint16_t usb1_function_GetDeviceState (void)
+{
+ uint16_t dvsq;
+ uint16_t dvst;
+
+ dvsq = USB201.INTSTS0;
+ switch (dvsq & USB_FUNCTION_BITDVSQ)
+ {
+ case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */
+ dvst = USB_FUNCTION_DVST_POWERED;
+ break;
+
+ case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */
+ dvst = USB_FUNCTION_DVST_DEFAULT;
+ break;
+
+ case USB_FUNCTION_DS_ADDS: /* Address state */
+ dvst = USB_FUNCTION_DVST_ADDRESS;
+ break;
+
+ case USB_FUNCTION_DS_CNFG: /* Configured state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED;
+ break;
+
+ case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND;
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */
+ case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */
+ case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+
+ default: /* error */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+ }
+
+ return dvst;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ usb1_function_start_receive_transfer(pipe, size, data);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+
+ status = usb1_function_start_send_transfer(pipe, size, data);
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_check_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *size ; Data Size
+* Return Value : Pipe Status
+*******************************************************************************/
+uint16_t usb1_api_function_check_pipe_status (uint16_t pipe, uint32_t * size)
+{
+ if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE)
+ {
+ *size = g_usb1_function_PipeDataSize[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_DONE;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_NORES;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_STALL;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_FIFOERROR;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return g_usb1_function_pipe_status[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Pipe Status
+*******************************************************************************/
+void usb1_api_function_clear_pipe_status (uint16_t pipe)
+{
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_buf (uint16_t pipe)
+{
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_nak (uint16_t pipe)
+{
+ usb1_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_stall (uint16_t pipe)
+{
+ usb1_function_set_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_pid_stall (uint16_t pipe)
+{
+ usb1_function_clear_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_api_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_check_stall
+* Description :
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+int32_t usb1_api_function_check_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL)
+ {
+ return DEVDRV_USBF_STALL;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_sqclr (uint16_t pipe)
+{
+ usb1_function_set_sqclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_sqset (uint16_t pipe)
+{
+ usb1_function_set_sqset(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_csclr (uint16_t pipe)
+{
+ usb1_function_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_curpipe
+* Description : Allocates FIF0 specifed by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ usb1_function_set_curpipe(pipe, fifosel, isel, mbw);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_brdy_sts (uint16_t pipe)
+{
+ usb1_function_clear_brdy_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_bemp_sts (uint16_t pipe)
+{
+ usb1_function_clear_bemp_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_nrdy_sts (uint16_t pipe)
+{
+ usb1_function_clear_nrdy_sts(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c
new file mode 100644
index 000000000..45f8fa485
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_function_CtrlReadStart
+* Description : Executes the USB control read transfer.
+* : USB host controller <- USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; End of data write
+* : DEVDRV_USBF_WRITESHRT ; End of short data write
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_api_function_CtrlReadStart (uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ status = usb1_function_write_buffer_c(USB_FUNCTION_PIPE0);
+
+ /* Peripheral Control sequence */
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */
+ usb1_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_CtrlWriteStart
+* Description : Executes the USB control write transfer.
+* : USB host controller -> USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_CtrlWriteStart (uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb1_function_enable_brdy_int(USB_FUNCTION_PIPE0);
+ usb1_function_set_pid_buf(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c
new file mode 100644
index 000000000..2ca4dac59
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c
@@ -0,0 +1,144 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+const uint16_t g_usb1_function_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+uint16_t g_usb1_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint32_t g_usb1_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[2];
+uint16_t g_usb1_function_DmaPipe[2];
+uint16_t g_usb1_function_DmaBval[2];
+uint16_t g_usb1_function_DmaStatus[2];
+
+uint16_t g_usb1_function_CtrZeroLengthFlag;
+
+//uint16_t g_usb1_function_ConfigNum;
+//uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
+//uint16_t g_usb1_function_RemoteWakeupFlag;
+uint16_t g_usb1_function_TestModeFlag;
+uint16_t g_usb1_function_TestModeSelectors;
+
+//uint16_t g_usb1_function_ReqType;
+//uint16_t g_usb1_function_ReqTypeType;
+//uint16_t g_usb1_function_ReqTypeRecip;
+//uint16_t g_usb1_function_ReqRequest;
+//uint16_t g_usb1_function_ReqValue;
+//uint16_t g_usb1_function_ReqIndex;
+//uint16_t g_usb1_function_ReqLength;
+
+//uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+* Function Name: usb1_function_init_status
+* Description : Initialization USB Sample Driver Variable.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_init_status (void)
+{
+ uint16_t pipe;
+
+ //g_usb1_function_ConfigNum = 0;
+ //g_usb1_function_RemoteWakeupFlag = DEVDRV_USBF_OFF;
+ g_usb1_function_TestModeFlag = DEVDRV_USBF_OFF;
+ g_usb1_function_CtrZeroLengthFlag = 0;
+
+#if 0
+ usb1_function_clear_alt();
+#endif
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_data_count[pipe] = 0;
+
+ /* pipe configuration in usb1_function_ResetEP() */
+ g_usb1_function_pipecfg[pipe] = 0;
+ g_usb1_function_pipebuf[pipe] = 0;
+ g_usb1_function_pipemaxp[pipe] = 0;
+ g_usb1_function_pipeperi[pipe] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c
new file mode 100644
index 000000000..9c0b4af89
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c
@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_sig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_function_EnableINTModule(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_InitModule
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
+* : ; other ; Full-speed Mode
+* Return Value : none
+*******************************************************************************/
+void usb1_function_InitModule (uint16_t mode)
+{
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* USB function */
+
+ /* USB module operation enabled */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ if (mode == USB_FUNCTION_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE); /* Hi-Speed Mode */
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+
+ /* for power-on */
+ if (usb1_function_CheckVBUStaus() == DEVDRV_USBF_ON)
+ {
+ usb1_function_EnableINTModule(); /* Interrupt Enable */
+ usb1_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
+ }
+ else
+ {
+ usb1_function_USB_FUNCTION_Detach(); /* USB Detach */
+ /* with Interrupt Enable */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_CheckVBUStaus
+* Description : Checks the USB-VBUS state to returns the connection state to
+* : the USB host.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : VBUS ON
+* : DEVDRV_USBF_OFF : VBUS OFF
+*******************************************************************************/
+uint16_t usb1_function_CheckVBUStaus (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ /* monitor VBUS pins */
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb1_function_delay_10us(1);
+ buf2 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb1_function_delay_10us(1);
+ buf3 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ } while ((buf1 != buf2) || (buf2 != buf3));
+
+ if (buf1 == DEVDRV_USBF_OFF)
+ {
+ return DEVDRV_USBF_OFF; /* detach */
+ }
+
+ return DEVDRV_USBF_ON; /* attach */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Attach
+* Description : Connects to the USB host controller.
+* : This function pulls up D+.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_Attach (void)
+{
+ Userdef_USB_usb1_function_attach();
+
+ Userdef_USB_usb1_function_delay_xms(10);
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Detach
+* Description : Disconnects from the USB host controller.
+* : This function opens D+/D-.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_Detach (void)
+{
+ uint16_t pipe;
+
+ Userdef_USB_usb1_function_detach();
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
+ {
+ usb1_function_stop_transfer(pipe);
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* open D+ and D- */
+
+ /* Detach Recovery */
+ Userdef_USB_usb1_function_delay_500ns(); /* need 1us=500ns * 2 wait */
+ Userdef_USB_usb1_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+ Userdef_USB_usb1_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE); /* soft reset module */
+ Userdef_USB_usb1_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ usb1_function_EnableINTModule(); /* Interrupt Enable */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_BusReset
+* Description : This function is executed when the USB device is transitioned
+* : to POWERD_STATE. Sets the device descriptor according to the
+* : connection speed determined by the USB reset hand shake.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_BusReset (void)
+{
+ usb1_function_init_status(); /* memory clear */
+
+ if (usb1_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED)
+ {
+ usb1_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */
+ }
+ else
+ {
+ usb1_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */
+ }
+
+ usb1_function_ResetDCP(); /* Default Control PIPE reset */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Resume
+* Description : This function is executed when the USB device detects a resume
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_Resume (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Suspend
+* Description : This function is executed when the USB device detects a suspend
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_Suspend (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_TestMode
+* Description : This function is executed when the USB device is transitioned U
+* : to TEST_MODE by the USB standard request.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_TestMode (void)
+{
+ switch (g_usb1_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT)
+ {
+ case USB_FUNCTION_FUNCTION_TEST_J:
+ case USB_FUNCTION_FUNCTION_TEST_K:
+ case USB_FUNCTION_FUNCTION_TEST_SE0_NAK:
+ case USB_FUNCTION_FUNCTION_TEST_PACKET:
+ RZA_IO_RegWrite_16(&USB201.TESTMODE,
+ (g_usb1_function_TestModeSelectors >> 8),
+ USB_TESTMODE_UTST_SHIFT,
+ USB_TESTMODE_UTST);
+ break;
+
+ case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE:
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_EnableINTModule
+* Description : Enables USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_EnableINTModule (void)
+{
+ uint16_t buf;
+
+ buf = USB201.INTENB0;
+ buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE |
+ USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE);
+ USB201.INTENB0 = buf;
+
+ usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c
new file mode 100644
index 000000000..bdb548a5f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c
@@ -0,0 +1,453 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_sub.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#if 0
+extern const uint16_t *g_usb1_function_EndPntPtr[];
+extern uint8_t g_usb1_function_DeviceDescriptor[];
+extern uint8_t *g_usb1_function_ConfigurationPtr[];
+#endif
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_ResetDCP
+* Description : Initializes the default control pipe(DCP).
+* Outline : Reset default control pipe
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_ResetDCP (void)
+{
+ USB201.DCPCFG = 0;
+#if 0
+ USB201.DCPMAXP = g_usb1_function_DeviceDescriptor[7];
+#else
+ USB201.DCPMAXP = 64;
+#endif
+
+ USB201.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB201.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB201.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_ResetEP
+* Description : Initializes the end point.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_ResetEP (uint16_t num)
+{
+ uint16_t pipe;
+ uint16_t ep;
+ uint16_t index;
+ uint16_t buf;
+ uint16_t * tbl;
+
+ tbl = (uint16_t *)(g_usb1_function_EndPntPtr[num - 1]);
+
+ for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ if (g_usb1_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR)
+ {
+ index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb1_function_EPTableIndex[ep]);
+ pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE);
+
+ g_usb1_function_PipeTbl[pipe] = (uint16_t)(((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) |
+ ep |
+ (tbl[index + 0] & USB_FUNCTION_FIFO_USE));
+
+ if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT)
+ {
+ tbl[index + 1] |= USB_FUNCTION_SHTNAKON;
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) ||
+ ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA))
+ {
+ tbl[index + 1] |= USB_FUNCTION_BFREON;
+ }
+#endif
+ }
+
+ /* Interrupt Disable */
+ buf = USB201.BRDYENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.BRDYENB = buf;
+ buf = USB201.NRDYENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.NRDYENB = buf;
+ buf = USB201.BEMPENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.BEMPENB = buf;
+
+ usb1_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.CFIFOSEL,
+ 0,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB201.PIPESEL = pipe;
+ USB201.PIPECFG = tbl[index + 1];
+ USB201.PIPEBUF = tbl[index + 2];
+ USB201.PIPEMAXP = tbl[index + 3];
+ USB201.PIPEPERI = tbl[index + 4];
+
+ g_usb1_function_pipecfg[pipe] = tbl[index + 1];
+ g_usb1_function_pipebuf[pipe] = tbl[index + 2];
+ g_usb1_function_pipemaxp[pipe] = tbl[index + 3];
+ g_usb1_function_pipeperi[pipe] = tbl[index + 4];
+
+ /* Buffer Clear */
+ usb1_function_set_sqclr(pipe);
+ usb1_function_aclrm(pipe);
+
+ /* init Global */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_EpToPipe
+* Description : Returns the pipe which end point specified by the argument is
+* : allocated to.
+* Arguments : uint16_t ep ; Direction + Endpoint Number
+* Return Value : USB_FUNCTION_EP_ERROR : Error
+* : Others : Pipe Number
+*******************************************************************************/
+uint16_t usb1_function_EpToPipe (uint16_t ep)
+{
+ uint16_t pipe;
+
+ for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((g_usb1_function_PipeTbl[pipe] & 0x00ff) == ep)
+ {
+ return pipe;
+ }
+ }
+
+ return USB_FUNCTION_EP_ERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_InitEPTable
+* Description : Sets the end point by the Alternate setting value of the
+* : configuration number and the interface number specified by the
+* : argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* : uint16_t Alt_Num ; Alternate Setting
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num)
+{
+ uint8_t * ptr;
+ uint16_t point_interface;
+ uint16_t point_endpoint;
+ uint16_t length;
+ uint16_t start;
+ uint16_t numbers;
+ uint16_t endpoint;
+
+ ptr = (uint8_t *)g_usb1_function_ConfigurationPtr[Con_Num - 1];
+ point_interface = *ptr;
+ length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2));
+ ptr += *ptr;
+ start = 0;
+ numbers = 0;
+ point_endpoint = 0;
+
+ for (; point_interface < length;)
+ {
+ switch (*(ptr + 1)) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num))
+ {
+ numbers = *(ptr + 4);
+ }
+ else
+ {
+ start += *(ptr + 4);
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ if (point_endpoint < numbers)
+ {
+ endpoint = (uint16_t)(*(ptr + 2) & 0x0f);
+ g_usb1_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint);
+ ++point_endpoint;
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ default: /* Class, Vendor, else */
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetConfigNum
+* Description : Returns the number of configuration referring to the number of
+* : configuration described in the device descriptor.
+* Arguments : none
+* Return Value : Number of possible configurations (bNumConfigurations).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetConfigNum (void)
+{
+ return (uint16_t)g_usb1_function_DeviceDescriptor[17];
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetInterfaceNum
+* Description : Returns the number of interface referring to the number of
+* : interface described in the configuration descriptor.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : Number of this interface (bNumInterfaces).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetInterfaceNum (uint16_t num)
+{
+ return (uint16_t)(*(g_usb1_function_ConfigurationPtr[num - 1] + 4));
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetAltNum
+* Description : Returns the Alternate setting value of the configuration number
+* : and the interface number specified by the argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* Return Value : Value used to select this alternate setting(bAlternateSetting).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num)
+{
+ uint8_t * ptr;
+ uint16_t point;
+ uint16_t alt_num = 0;
+ uint16_t length;
+
+ ptr = (uint8_t *)(g_usb1_function_ConfigurationPtr[Con_Num - 1]);
+ point = ptr[0];
+ ptr += ptr[0]; /* InterfaceDescriptor[0] */
+ length = (uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 2));
+ length |= (uint16_t)((uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8);
+
+ for (; point < length;) /* Search Descriptor Table size */
+ {
+ switch (ptr[1]) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if (Int_Num == ptr[2])
+ {
+ alt_num = (uint16_t)ptr[3]; /* Alternate Number count */
+ }
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ default: /* Class, Vendor, else */
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+ }
+ }
+ return alt_num;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_CheckRemoteWakeup
+* Description : Returns the result of the remote wake up function is supported
+* : or not referring to the configuration descriptor.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup
+* : DEVDRV_USBF_OFF : not Support Remote Wakeup
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_CheckRemoteWakeup (void)
+{
+ uint8_t atr;
+
+ if (g_usb1_function_ConfigNum == 0)
+ {
+ return DEVDRV_USBF_OFF;
+ }
+
+ atr = *(g_usb1_function_ConfigurationPtr[g_usb1_function_ConfigNum - 1] + 7);
+
+ if (atr & USB_FUNCTION_CF_RWUP)
+ {
+ return DEVDRV_USBF_ON;
+ }
+
+ return DEVDRV_USBF_OFF;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_alt
+* Description : Initializes the Alternate setting area.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_clear_alt (void)
+{
+ int i;
+
+ for (i = 0; i < USB_FUNCTION_ALT_NO; ++i)
+ {
+ g_usb1_function_Alternate[i] = 0; /* Alternate */
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_pipe_tbl
+* Description : Initializes pipe definition table.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_pipe_tbl (void)
+{
+ int pipe;
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb1_function_PipeTbl[pipe] = 0;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_ep_table_index
+* Description : Initializes the end point table index.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_clear_ep_table_index (void)
+{
+ int ep;
+
+ for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ g_usb1_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR;
+ }
+}
+#endif
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c
new file mode 100644
index 000000000..809f682a0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_function_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID,AM,LVL,REQD */
+ {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC3_CHCFG_n_DAD_SHIFT,
+ DMAC3_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC3_CHCFG_n_SAD_SHIFT,
+ DMAC3_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->dst_size,
+ DMAC3_CHCFG_n_DDS_SHIFT,
+ DMAC3_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->src_size,
+ DMAC3_CHCFG_n_SDS_SHIFT,
+ DMAC3_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DMS_SHIFT,
+ DMAC3_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSEL_SHIFT,
+ DMAC3_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_SBE_SHIFT,
+ DMAC3_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DEM_SHIFT,
+ DMAC3_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_TM_SHIFT,
+ DMAC3_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 3,
+ DMAC3_CHCFG_n_SEL_SHIFT,
+ DMAC3_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_HIEN_SHIFT,
+ DMAC3_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_LOEN_SHIFT,
+ DMAC3_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC3_CHCFG_n_AM_SHIFT,
+ DMAC3_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC3_CHCFG_n_LVL_SHIFT,
+ DMAC3_CHCFG_n_LVL);
+
+ if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ req_direction,
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH3_RID_SHIFT,
+ DMAC23_DMARS_CH3_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH3_MID_SHIFT,
+ DMAC23_DMARS_CH3_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Open
+* Description : Enables DMAC channel 3 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_function_DMAC3_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SETEN_SHIFT,
+ DMAC3_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_STG_SHIFT,
+ DMAC3_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Close
+* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_CLREN_SHIFT,
+ DMAC3_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 3 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 3 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_SR_SHIFT,
+ DMAC3_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+*******************************************************************************/
+void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC4_CHCFG_n_DAD_SHIFT,
+ DMAC4_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC4_CHCFG_n_SAD_SHIFT,
+ DMAC4_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->dst_size,
+ DMAC4_CHCFG_n_DDS_SHIFT,
+ DMAC4_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->src_size,
+ DMAC4_CHCFG_n_SDS_SHIFT,
+ DMAC4_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DMS_SHIFT,
+ DMAC4_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSEL_SHIFT,
+ DMAC4_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_SBE_SHIFT,
+ DMAC4_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DEM_SHIFT,
+ DMAC4_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_TM_SHIFT,
+ DMAC4_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 4,
+ DMAC4_CHCFG_n_SEL_SHIFT,
+ DMAC4_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_HIEN_SHIFT,
+ DMAC4_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_LOEN_SHIFT,
+ DMAC4_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC4_CHCFG_n_AM_SHIFT,
+ DMAC4_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC4_CHCFG_n_LVL_SHIFT,
+ DMAC4_CHCFG_n_LVL);
+ if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ req_direction,
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC45_DMARS_CH4_RID_SHIFT,
+ DMAC45_DMARS_CH4_RID);
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC45_DMARS_CH4_MID_SHIFT,
+ DMAC45_DMARS_CH4_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Open
+* Description : Enables DMAC channel 4 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_function_DMAC4_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SETEN_SHIFT,
+ DMAC4_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_STG_SHIFT,
+ DMAC4_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Close
+* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC4_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_CLREN_SHIFT,
+ DMAC4_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 4 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 4 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_SR_SHIFT,
+ DMAC4_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c
new file mode 100644
index 000000000..77c62132d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c
@@ -0,0 +1,762 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_function_api.h"
+#include "usb1_function_dmacdrv.h" /* common DMAC driver for USB */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_function_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb1_function_d0fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb1_function_d1fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_attach (void)
+{
+ printf("\n");
+ printf("channel 1 attach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_detach (void)
+{
+ printf("\n");
+ printf("channel 1 detach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_1ms (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /*
+ * Wait 1ms (Please change for your MCU).
+ */
+ for (i = 0; i < 1440; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_xms (uint32_t msec)
+{
+ volatile unsigned short i;
+
+ for (i = 0; i < msec; ++i)
+ {
+ Userdef_USB_usb1_function_delay_1ms();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb1_function_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_function_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_FUNCTION_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ usb1_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb1_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_function_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb1_function_DMAC3_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_function_DMAC3_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC3 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_function_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb1_function_DMAC4_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_function_DMAC4_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC4 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_stop_dma0
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_function_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_function_DMAC3_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_function_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_function_DMAC4_Close(&remain);
+
+ return remain;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h
new file mode 100644
index 000000000..fc940c477
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_FUNCTION_SETTING_H
+#define USB_FUNCTION_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_FUNCTION_CH 0
+#define USB_FUNCTION_HISPEED 1
+
+#if (USB_FUNCTION_CH == 0)
+#include "usb0_function.h"
+#define USB20X USB200
+#define USBIX_IRQn USBI0_IRQn
+#define g_usbx_function_bit_set g_usb0_function_bit_set
+#define g_usbx_function_PipeDataSize g_usb0_function_PipeDataSize
+#define g_usbx_function_data_count g_usb0_function_data_count
+#define g_usbx_function_PipeTbl g_usb0_function_PipeTbl
+#define g_usbx_function_DmaStatus g_usb0_function_DmaStatus
+#define g_usbx_function_pipecfg g_usb0_function_pipecfg
+#define g_usbx_function_pipe_status g_usb0_function_pipe_status
+#define g_usbx_function_data_pointer g_usb0_function_data_pointer
+#define g_usbx_function_pipebuf g_usb0_function_pipebuf
+#define g_usbx_function_pipemaxp g_usb0_function_pipemaxp
+#define g_usbx_function_pipeperi g_usb0_function_pipeperi
+#define g_usbx_function_TestModeFlag g_usb0_function_TestModeFlag
+#define usbx_function_BRDYInterruptPIPE0 usb0_function_BRDYInterruptPIPE0
+#define usbx_function_BRDYInterrupt usb0_function_BRDYInterrupt
+#define usbx_function_NRDYInterruptPIPE0 usb0_function_NRDYInterruptPIPE0
+#define usbx_function_NRDYInterrupt usb0_function_NRDYInterrupt
+#define usbx_function_BEMPInterruptPIPE0 usb0_function_BEMPInterruptPIPE0
+#define usbx_function_BEMPInterrupt usb0_function_BEMPInterrupt
+#define usbx_function_read_buffer_c usb0_function_read_buffer_c
+#define usbx_function_set_pid_buf usb0_function_set_pid_buf
+#define usbx_function_disable_brdy_int usb0_function_disable_brdy_int
+#define usbx_function_set_pid_stall usb0_function_set_pid_stall
+#define usbx_function_dma_interrupt_d0fifo usb0_function_dma_interrupt_d0fifo
+#define usbx_function_read_dma usb0_function_read_dma
+#define usbx_function_dma_interrupt_d1fifo usb0_function_dma_interrupt_d1fifo
+#define usbx_function_write_buffer usb0_function_write_buffer
+#define usbx_function_set_pid_nak usb0_function_set_pid_nak
+#define usbx_function_get_mbw usb0_function_get_mbw
+#define usbx_function_set_curpipe usb0_function_set_curpipe
+#define usbx_function_aclrm usb0_function_aclrm
+#define usbx_function_enable_nrdy_int usb0_function_enable_nrdy_int
+#define usbx_function_enable_brdy_int usb0_function_enable_brdy_int
+#define usbx_function_get_pid usb0_function_get_pid
+#define usbx_function_get_inbuf usb0_function_get_inbuf
+#define usbx_function_disable_bemp_int usb0_function_disable_bemp_int
+#define usbx_function_EpToPipe usb0_function_EpToPipe
+#define usbx_function_clear_pipe_tbl usb0_function_clear_pipe_tbl
+#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb0_function_d0fifo_dmaintid
+#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb0_function_d1fifo_dmaintid
+#define usbx_function_reset_module usb0_function_reset_module
+#define usbx_function_init_status usb0_function_init_status
+#define usbx_function_InitModule usb0_function_InitModule
+#define usbx_function_clear_alt usb0_function_clear_alt
+#define usbx_function_set_sqclr usb0_function_set_sqclr
+#define usbx_api_function_CtrlWriteStart usb0_api_function_CtrlWriteStart
+#define usbx_api_function_CtrlReadStart usb0_api_function_CtrlReadStart
+#define usbx_function_write_buffer_c usb0_function_write_buffer_c
+#define usbx_api_function_check_pipe_status usb0_api_function_check_pipe_status
+#define usbx_api_function_set_pid_nak usb0_api_function_set_pid_nak
+#define usbx_api_function_clear_pipe_status usb0_api_function_clear_pipe_status
+#define usbx_api_function_start_receive_transfer usb0_api_function_start_receive_transfer
+#define usbx_function_read_buffer usb0_function_read_buffer
+#define usbx_api_function_start_send_transfer usb0_api_function_start_send_transfer
+#define usbx_function_stop_transfer usb0_function_stop_transfer
+#define usbx_function_clear_pid_stall usb0_function_clear_pid_stall
+#define usbx_function_CheckVBUStaus usb0_function_CheckVBUStaus
+#define usbx_function_USB_FUNCTION_Attach usb0_function_USB_FUNCTION_Attach
+#define usbx_function_USB_FUNCTION_Detach usb0_function_USB_FUNCTION_Detach
+#define usbx_function_is_hispeed usb0_function_is_hispeed
+#define usbx_function_ResetDescriptor usb0_function_ResetDescriptor
+#define usbx_function_USB_FUNCTION_Suspend usb0_function_USB_FUNCTION_Suspend
+#define usbx_function_USB_FUNCTION_TestMode usb0_function_USB_FUNCTION_TestMode
+#else
+#include "usb1_function.h"
+#define USB20X USB201
+#define USBIX_IRQn USBI1_IRQn
+#define g_usbx_function_bit_set g_usb1_function_bit_set
+#define g_usbx_function_PipeDataSize g_usb1_function_PipeDataSize
+#define g_usbx_function_data_count g_usb1_function_data_count
+#define g_usbx_function_PipeTbl g_usb1_function_PipeTbl
+#define g_usbx_function_DmaStatus g_usb1_function_DmaStatus
+#define g_usbx_function_pipecfg g_usb1_function_pipecfg
+#define g_usbx_function_pipe_status g_usb1_function_pipe_status
+#define g_usbx_function_data_pointer g_usb1_function_data_pointer
+#define g_usbx_function_pipebuf g_usb1_function_pipebuf
+#define g_usbx_function_pipemaxp g_usb1_function_pipemaxp
+#define g_usbx_function_pipeperi g_usb1_function_pipeperi
+#define g_usbx_function_TestModeFlag g_usb1_function_TestModeFlag
+#define usbx_function_BRDYInterruptPIPE0 usb1_function_BRDYInterruptPIPE0
+#define usbx_function_BRDYInterrupt usb1_function_BRDYInterrupt
+#define usbx_function_NRDYInterruptPIPE0 usb1_function_NRDYInterruptPIPE0
+#define usbx_function_NRDYInterrupt usb1_function_NRDYInterrupt
+#define usbx_function_BEMPInterruptPIPE0 usb1_function_BEMPInterruptPIPE0
+#define usbx_function_BEMPInterrupt usb1_function_BEMPInterrupt
+#define usbx_function_read_buffer_c usb1_function_read_buffer_c
+#define usbx_function_set_pid_buf usb1_function_set_pid_buf
+#define usbx_function_disable_brdy_int usb1_function_disable_brdy_int
+#define usbx_function_set_pid_stall usb1_function_set_pid_stall
+#define usbx_function_dma_interrupt_d0fifo usb1_function_dma_interrupt_d0fifo
+#define usbx_function_read_dma usb1_function_read_dma
+#define usbx_function_dma_interrupt_d1fifo usb1_function_dma_interrupt_d1fifo
+#define usbx_function_write_buffer usb1_function_write_buffer
+#define usbx_function_set_pid_nak usb1_function_set_pid_nak
+#define usbx_function_get_mbw usb1_function_get_mbw
+#define usbx_function_set_curpipe usb1_function_set_curpipe
+#define usbx_function_aclrm usb1_function_aclrm
+#define usbx_function_enable_nrdy_int usb1_function_enable_nrdy_int
+#define usbx_function_enable_brdy_int usb1_function_enable_brdy_int
+#define usbx_function_get_pid usb1_function_get_pid
+#define usbx_function_get_inbuf usb1_function_get_inbuf
+#define usbx_function_disable_bemp_int usb1_function_disable_bemp_int
+#define usbx_function_EpToPipe usb1_function_EpToPipe
+#define usbx_function_clear_pipe_tbl usb1_function_clear_pipe_tbl
+#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb1_function_d0fifo_dmaintid
+#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb1_function_d1fifo_dmaintid
+#define usbx_function_reset_module usb1_function_reset_module
+#define usbx_function_init_status usb1_function_init_status
+#define usbx_function_InitModule usb1_function_InitModule
+#define usbx_function_clear_alt usb1_function_clear_alt
+#define usbx_function_set_sqclr usb1_function_set_sqclr
+#define usbx_api_function_CtrlWriteStart usb1_api_function_CtrlWriteStart
+#define usbx_api_function_CtrlReadStart usb1_api_function_CtrlReadStart
+#define usbx_function_write_buffer_c usb1_function_write_buffer_c
+#define usbx_api_function_check_pipe_status usb1_api_function_check_pipe_status
+#define usbx_api_function_set_pid_nak usb1_api_function_set_pid_nak
+#define usbx_api_function_clear_pipe_status usb1_api_function_clear_pipe_status
+#define usbx_api_function_start_receive_transfer usb1_api_function_start_receive_transfer
+#define usbx_function_read_buffer usb1_function_read_buffer
+#define usbx_api_function_start_send_transfer usb1_api_function_start_send_transfer
+#define usbx_function_stop_transfer usb1_function_stop_transfer
+#define usbx_function_clear_pid_stall usb1_function_clear_pid_stall
+#define usbx_function_CheckVBUStaus usb1_function_CheckVBUStaus
+#define usbx_function_USB_FUNCTION_Attach usb1_function_USB_FUNCTION_Attach
+#define usbx_function_USB_FUNCTION_Detach usb1_function_USB_FUNCTION_Detach
+#define usbx_function_is_hispeed usb1_function_is_hispeed
+#define usbx_function_ResetDescriptor usb1_function_ResetDescriptor
+#define usbx_function_USB_FUNCTION_Suspend usb1_function_USB_FUNCTION_Suspend
+#define usbx_function_USB_FUNCTION_TestMode usb1_function_USB_FUNCTION_TestMode
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_FUNCTION_SETTING_H */
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h
new file mode 100644
index 000000000..9d4ce849f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+/* Standard descriptor types */
+#define DEVICE_DESCRIPTOR (1)
+#define CONFIGURATION_DESCRIPTOR (2)
+#define STRING_DESCRIPTOR (3)
+#define INTERFACE_DESCRIPTOR (4)
+#define ENDPOINT_DESCRIPTOR (5)
+#define QUALIFIER_DESCRIPTOR (6)
+
+/* Standard descriptor lengths */
+#define DEVICE_DESCRIPTOR_LENGTH (0x12)
+#define CONFIGURATION_DESCRIPTOR_LENGTH (0x09)
+#define INTERFACE_DESCRIPTOR_LENGTH (0x09)
+#define ENDPOINT_DESCRIPTOR_LENGTH (0x07)
+
+
+/*string offset*/
+#define STRING_OFFSET_LANGID (0)
+#define STRING_OFFSET_IMANUFACTURER (1)
+#define STRING_OFFSET_IPRODUCT (2)
+#define STRING_OFFSET_ISERIAL (3)
+#define STRING_OFFSET_ICONFIGURATION (4)
+#define STRING_OFFSET_IINTERFACE (5)
+
+/* USB Specification Release Number */
+#define USB_VERSION_2_0 (0x0200)
+
+/* Least/Most significant byte of short integer */
+#define LSB(n) ((n)&0xff)
+#define MSB(n) (((n)&0xff00)>>8)
+
+/* Convert physical endpoint number to descriptor endpoint number */
+#define PHY_TO_DESC(endpoint) (((endpoint)>>1) | (((endpoint) & 1) ? 0x80:0))
+
+/* bmAttributes in configuration descriptor */
+/* C_RESERVED must always be set */
+#define C_RESERVED (1U<<7)
+#define C_SELF_POWERED (1U<<6)
+#define C_REMOTE_WAKEUP (1U<<5)
+
+/* bMaxPower in configuration descriptor */
+#define C_POWER(mA) ((mA)/2)
+
+/* bmAttributes in endpoint descriptor */
+#define E_CONTROL (0x00)
+#define E_ISOCHRONOUS (0x01)
+#define E_BULK (0x02)
+#define E_INTERRUPT (0x03)
+
+/* For isochronous endpoints only: */
+#define E_NO_SYNCHRONIZATION (0x00)
+#define E_ASYNCHRONOUS (0x04)
+#define E_ADAPTIVE (0x08)
+#define E_SYNCHRONOUS (0x0C)
+#define E_DATA (0x00)
+#define E_FEEDBACK (0x10)
+#define E_IMPLICIT_FEEDBACK (0x20)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp
new file mode 100644
index 000000000..dc3efc96f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp
@@ -0,0 +1,1005 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+
+#include "USBEndpoints.h"
+#include "USBDevice.h"
+#include "USBDescriptor.h"
+
+//#define DEBUG
+
+/* Device status */
+#define DEVICE_STATUS_SELF_POWERED (1U<<0)
+#define DEVICE_STATUS_REMOTE_WAKEUP (1U<<1)
+
+/* Endpoint status */
+#define ENDPOINT_STATUS_HALT (1U<<0)
+
+/* Standard feature selectors */
+#define DEVICE_REMOTE_WAKEUP (1)
+#define ENDPOINT_HALT (0)
+
+/* Macro to convert wIndex endpoint number to physical endpoint number */
+#define WINDEX_TO_PHYSICAL(endpoint) (((endpoint & 0x0f) << 1) + \
+ ((endpoint & 0x80) ? 1 : 0))
+
+
+bool USBDevice::requestGetDescriptor(void)
+{
+ bool success = false;
+#ifdef DEBUG
+ printf("get descr: type: %d\r\n", DESCRIPTOR_TYPE(transfer.setup.wValue));
+#endif
+ switch (DESCRIPTOR_TYPE(transfer.setup.wValue))
+ {
+ case DEVICE_DESCRIPTOR:
+ if (deviceDesc() != NULL)
+ {
+ if ((deviceDesc()[0] == DEVICE_DESCRIPTOR_LENGTH) \
+ && (deviceDesc()[1] == DEVICE_DESCRIPTOR))
+ {
+#ifdef DEBUG
+ printf("device descr\r\n");
+#endif
+ transfer.remaining = DEVICE_DESCRIPTOR_LENGTH;
+ transfer.ptr = deviceDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ }
+ break;
+ case CONFIGURATION_DESCRIPTOR:
+ if (configurationDesc() != NULL)
+ {
+ if ((configurationDesc()[0] == CONFIGURATION_DESCRIPTOR_LENGTH) \
+ && (configurationDesc()[1] == CONFIGURATION_DESCRIPTOR))
+ {
+#ifdef DEBUG
+ printf("conf descr request\r\n");
+#endif
+ /* Get wTotalLength */
+ transfer.remaining = configurationDesc()[2] \
+ | (configurationDesc()[3] << 8);
+
+ transfer.ptr = configurationDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ }
+ break;
+ case STRING_DESCRIPTOR:
+#ifdef DEBUG
+ printf("str descriptor\r\n");
+#endif
+ switch (DESCRIPTOR_INDEX(transfer.setup.wValue))
+ {
+ case STRING_OFFSET_LANGID:
+#ifdef DEBUG
+ printf("1\r\n");
+#endif
+ transfer.remaining = stringLangidDesc()[0];
+ transfer.ptr = stringLangidDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IMANUFACTURER:
+#ifdef DEBUG
+ printf("2\r\n");
+#endif
+ transfer.remaining = stringImanufacturerDesc()[0];
+ transfer.ptr = stringImanufacturerDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IPRODUCT:
+#ifdef DEBUG
+ printf("3\r\n");
+#endif
+ transfer.remaining = stringIproductDesc()[0];
+ transfer.ptr = stringIproductDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_ISERIAL:
+#ifdef DEBUG
+ printf("4\r\n");
+#endif
+ transfer.remaining = stringIserialDesc()[0];
+ transfer.ptr = stringIserialDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_ICONFIGURATION:
+#ifdef DEBUG
+ printf("5\r\n");
+#endif
+ transfer.remaining = stringIConfigurationDesc()[0];
+ transfer.ptr = stringIConfigurationDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IINTERFACE:
+#ifdef DEBUG
+ printf("6\r\n");
+#endif
+ transfer.remaining = stringIinterfaceDesc()[0];
+ transfer.ptr = stringIinterfaceDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ }
+ break;
+ case INTERFACE_DESCRIPTOR:
+#ifdef DEBUG
+ printf("interface descr\r\n");
+#endif
+ case ENDPOINT_DESCRIPTOR:
+#ifdef DEBUG
+ printf("endpoint descr\r\n");
+#endif
+ /* TODO: Support is optional, not implemented here */
+ break;
+ default:
+#ifdef DEBUG
+ printf("ERROR\r\n");
+#endif
+ break;
+ }
+
+ return success;
+}
+
+void USBDevice::decodeSetupPacket(uint8_t *data, SETUP_PACKET *packet)
+{
+ /* Fill in the elements of a SETUP_PACKET structure from raw data */
+ packet->bmRequestType.dataTransferDirection = (data[0] & 0x80) >> 7;
+ packet->bmRequestType.Type = (data[0] & 0x60) >> 5;
+ packet->bmRequestType.Recipient = data[0] & 0x1f;
+ packet->bRequest = data[1];
+ packet->wValue = (data[2] | (uint16_t)data[3] << 8);
+ packet->wIndex = (data[4] | (uint16_t)data[5] << 8);
+ packet->wLength = (data[6] | (uint16_t)data[7] << 8);
+}
+
+
+bool USBDevice::controlOut(void)
+{
+ /* Control transfer data OUT stage */
+ uint8_t buffer[MAX_PACKET_SIZE_EP0];
+ uint32_t packetSize;
+
+ /* Check we should be transferring data OUT */
+ if (transfer.direction != HOST_TO_DEVICE)
+ {
+#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+ /*
+ * We seem to have a pending device-to-host transfer. The host must have
+ * sent a new control request without waiting for us to finish processing
+ * the previous one. This appears to happen when we're connected to certain
+ * USB 3.0 host chip set. Do a zeor-length send to tell the host we're not
+ * ready for the new request - that'll make it resend - and then just
+ * pretend we were successful here so that the pending transfer can finish.
+ */
+ uint8_t buf[1] = { 0 };
+ EP0write(buf, 0);
+
+ /* execute our pending ttransfer */
+ controlIn();
+
+ /* indicate success */
+ return true;
+ #else
+ /* for other platforms, count on the HAL to handle this case */
+ return false;
+ #endif
+ }
+
+ /* Read from endpoint */
+ packetSize = EP0getReadResult(buffer);
+
+ /* Check if transfer size is valid */
+ if (packetSize > transfer.remaining)
+ {
+ /* Too big */
+ return false;
+ }
+
+ /* Update transfer */
+ transfer.ptr += packetSize;
+ transfer.remaining -= packetSize;
+
+ /* Check if transfer has completed */
+ if (transfer.remaining == 0)
+ {
+ /* Transfer completed */
+ if (transfer.notify)
+ {
+ /* Notify class layer. */
+ USBCallback_requestCompleted(buffer, packetSize);
+ transfer.notify = false;
+ }
+ /* Status stage */
+ EP0write(NULL, 0);
+ }
+ else
+ {
+ EP0read();
+ }
+
+ return true;
+}
+
+bool USBDevice::controlIn(void)
+{
+ /* Control transfer data IN stage */
+ uint32_t packetSize;
+
+ /* Check if transfer has completed (status stage transactions */
+ /* also have transfer.remaining == 0) */
+ if (transfer.remaining == 0)
+ {
+ if (transfer.zlp)
+ {
+ /* Send zero length packet */
+ EP0write(NULL, 0);
+ transfer.zlp = false;
+ }
+
+ /* Transfer completed */
+ if (transfer.notify)
+ {
+ /* Notify class layer. */
+ USBCallback_requestCompleted(NULL, 0);
+ transfer.notify = false;
+ }
+
+ EP0read();
+ EP0readStage();
+
+ /* Completed */
+ return true;
+ }
+
+ /* Check we should be transferring data IN */
+ if (transfer.direction != DEVICE_TO_HOST)
+ {
+ return false;
+ }
+
+ packetSize = transfer.remaining;
+
+ if (packetSize > MAX_PACKET_SIZE_EP0)
+ {
+ packetSize = MAX_PACKET_SIZE_EP0;
+ }
+
+ /* Write to endpoint */
+ EP0write(transfer.ptr, packetSize);
+
+ /* Update transfer */
+ transfer.ptr += packetSize;
+ transfer.remaining -= packetSize;
+
+ return true;
+}
+
+bool USBDevice::requestSetAddress(void)
+{
+ /* Set the device address */
+ setAddress(transfer.setup.wValue);
+
+ if (transfer.setup.wValue == 0)
+ {
+ device.state = DEFAULT;
+ }
+ else
+ {
+ device.state = ADDRESS;
+ }
+
+ return true;
+}
+
+bool USBDevice::requestSetConfiguration(void)
+{
+
+ device.configuration = transfer.setup.wValue;
+ /* Set the device configuration */
+ if (device.configuration == 0)
+ {
+ /* Not configured */
+ unconfigureDevice();
+ device.state = ADDRESS;
+ }
+ else
+ {
+ if (USBCallback_setConfiguration(device.configuration))
+ {
+ /* Valid configuration */
+ configureDevice();
+ device.state = CONFIGURED;
+ }
+ else
+ {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+bool USBDevice::requestGetConfiguration(void)
+{
+ /* Send the device configuration */
+ transfer.ptr = &device.configuration;
+ transfer.remaining = sizeof(device.configuration);
+ transfer.direction = DEVICE_TO_HOST;
+ return true;
+}
+
+bool USBDevice::requestGetInterface(void)
+{
+ /* Return the selected alternate setting for an interface */
+
+ if (device.state != CONFIGURED)
+ {
+ return false;
+ }
+
+ /* Send the alternate setting */
+ transfer.setup.wIndex = currentInterface;
+ transfer.ptr = &currentAlternate;
+ transfer.remaining = sizeof(currentAlternate);
+ transfer.direction = DEVICE_TO_HOST;
+ return true;
+}
+
+bool USBDevice::requestSetInterface(void)
+{
+ bool success = false;
+ if(USBCallback_setInterface(transfer.setup.wIndex, transfer.setup.wValue))
+ {
+ success = true;
+ currentInterface = transfer.setup.wIndex;
+ currentAlternate = transfer.setup.wValue;
+ }
+ return success;
+}
+
+bool USBDevice::requestSetFeature()
+{
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Remote wakeup feature not supported */
+ break;
+ case ENDPOINT_RECIPIENT:
+ if (transfer.setup.wValue == ENDPOINT_HALT)
+ {
+ /* TODO: We should check that the endpoint number is valid */
+ stallEndpoint(
+ WINDEX_TO_PHYSICAL(transfer.setup.wIndex));
+ success = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestClearFeature()
+{
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Remote wakeup feature not supported */
+ break;
+ case ENDPOINT_RECIPIENT:
+ /* TODO: We should check that the endpoint number is valid */
+ if (transfer.setup.wValue == ENDPOINT_HALT)
+ {
+ unstallEndpoint( WINDEX_TO_PHYSICAL(transfer.setup.wIndex));
+ success = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestGetStatus(void)
+{
+ static uint16_t status;
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Currently only supports self powered devices */
+ status = DEVICE_STATUS_SELF_POWERED;
+ success = true;
+ break;
+ case INTERFACE_RECIPIENT:
+ status = 0;
+ success = true;
+ break;
+ case ENDPOINT_RECIPIENT:
+ /* TODO: We should check that the endpoint number is valid */
+ if (getEndpointStallState(
+ WINDEX_TO_PHYSICAL(transfer.setup.wIndex)))
+ {
+ status = ENDPOINT_STATUS_HALT;
+ }
+ else
+ {
+ status = 0;
+ }
+ success = true;
+ break;
+ default:
+ break;
+ }
+
+ if (success)
+ {
+ /* Send the status */
+ transfer.ptr = (uint8_t *)&status; /* Assumes little endian */
+ transfer.remaining = sizeof(status);
+ transfer.direction = DEVICE_TO_HOST;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestSetup(void)
+{
+ bool success = false;
+
+ /* Process standard requests */
+ if ((transfer.setup.bmRequestType.Type == STANDARD_TYPE))
+ {
+ switch (transfer.setup.bRequest)
+ {
+ case GET_STATUS:
+ success = requestGetStatus();
+ break;
+ case CLEAR_FEATURE:
+ success = requestClearFeature();
+ break;
+ case SET_FEATURE:
+ success = requestSetFeature();
+ break;
+ case SET_ADDRESS:
+ success = requestSetAddress();
+ break;
+ case GET_DESCRIPTOR:
+ success = requestGetDescriptor();
+ break;
+ case SET_DESCRIPTOR:
+ /* TODO: Support is optional, not implemented here */
+ success = false;
+ break;
+ case GET_CONFIGURATION:
+ success = requestGetConfiguration();
+ break;
+ case SET_CONFIGURATION:
+ success = requestSetConfiguration();
+ break;
+ case GET_INTERFACE:
+ success = requestGetInterface();
+ break;
+ case SET_INTERFACE:
+ success = requestSetInterface();
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+bool USBDevice::controlSetup(void)
+{
+ bool success = false;
+
+ /* Control transfer setup stage */
+ uint8_t buffer[MAX_PACKET_SIZE_EP0];
+
+ EP0setup(buffer);
+
+ /* Initialise control transfer state */
+ decodeSetupPacket(buffer, &transfer.setup);
+ transfer.ptr = NULL;
+ transfer.remaining = 0;
+ transfer.direction = 0;
+ transfer.zlp = false;
+ transfer.notify = false;
+
+#ifdef DEBUG
+ printf("dataTransferDirection: %d\r\nType: %d\r\nRecipient: %d\r\nbRequest: %d\r\nwValue: %d\r\nwIndex: %d\r\nwLength: %d\r\n",transfer.setup.bmRequestType.dataTransferDirection,
+ transfer.setup.bmRequestType.Type,
+ transfer.setup.bmRequestType.Recipient,
+ transfer.setup.bRequest,
+ transfer.setup.wValue,
+ transfer.setup.wIndex,
+ transfer.setup.wLength);
+#endif
+
+ /* Class / vendor specific */
+ success = USBCallback_request();
+
+ if (!success)
+ {
+ /* Standard requests */
+ if (!requestSetup())
+ {
+#ifdef DEBUG
+ printf("fail!!!!\r\n");
+#endif
+ return false;
+ }
+ }
+
+ /* Check transfer size and direction */
+ if (transfer.setup.wLength>0)
+ {
+ if (transfer.setup.bmRequestType.dataTransferDirection \
+ == DEVICE_TO_HOST)
+ {
+ /* IN data stage is required */
+ if (transfer.direction != DEVICE_TO_HOST)
+ {
+ return false;
+ }
+
+ /* Transfer must be less than or equal to the size */
+ /* requested by the host */
+ if (transfer.remaining > transfer.setup.wLength)
+ {
+ transfer.remaining = transfer.setup.wLength;
+ }
+ }
+ else
+ {
+
+ /* OUT data stage is required */
+ if (transfer.direction != HOST_TO_DEVICE)
+ {
+ return false;
+ }
+
+ /* Transfer must be equal to the size requested by the host */
+ if (transfer.remaining != transfer.setup.wLength)
+ {
+ return false;
+ }
+ }
+ }
+ else
+ {
+ /* No data stage; transfer size must be zero */
+ if (transfer.remaining != 0)
+ {
+ return false;
+ }
+ }
+
+ /* Data or status stage if applicable */
+ if (transfer.setup.wLength>0)
+ {
+ if (transfer.setup.bmRequestType.dataTransferDirection \
+ == DEVICE_TO_HOST)
+ {
+ /* Check if we'll need to send a zero length packet at */
+ /* the end of this transfer */
+ if (transfer.setup.wLength > transfer.remaining)
+ {
+ /* Device wishes to transfer less than host requested */
+ if ((transfer.remaining % MAX_PACKET_SIZE_EP0) == 0)
+ {
+ /* Transfer is a multiple of EP0 max packet size */
+ transfer.zlp = true;
+ }
+ }
+
+ /* IN stage */
+ controlIn();
+ }
+ else
+ {
+ /* OUT stage */
+ EP0read();
+ }
+ }
+ else
+ {
+ /* Status stage */
+ EP0write(NULL, 0);
+ }
+
+ return true;
+}
+
+void USBDevice::busReset(void)
+{
+ device.state = DEFAULT;
+ device.configuration = 0;
+ device.suspended = false;
+
+ /* Call class / vendor specific busReset function */
+ USBCallback_busReset();
+}
+
+void USBDevice::EP0setupCallback(void)
+{
+ /* Endpoint 0 setup event */
+ if (!controlSetup())
+ {
+ /* Protocol stall */
+ EP0stall();
+ }
+
+ /* Return true if an OUT data stage is expected */
+}
+
+void USBDevice::EP0out(void)
+{
+ /* Endpoint 0 OUT data event */
+ if (!controlOut())
+ {
+ /* Protocol stall; this will stall both endpoints */
+ EP0stall();
+ }
+}
+
+void USBDevice::EP0in(void)
+{
+#ifdef DEBUG
+ printf("EP0IN\r\n");
+#endif
+ /* Endpoint 0 IN data event */
+ if (!controlIn())
+ {
+ /* Protocol stall; this will stall both endpoints */
+ EP0stall();
+ }
+}
+
+bool USBDevice::configured(void)
+{
+ /* Returns true if device is in the CONFIGURED state */
+ return (device.state == CONFIGURED);
+}
+
+void USBDevice::connect(bool blocking)
+{
+ /* Connect device */
+ USBHAL::connect();
+
+ if (blocking) {
+ /* Block if not configured */
+ while (!configured());
+ }
+}
+
+void USBDevice::disconnect(void)
+{
+ /* Disconnect device */
+ USBHAL::disconnect();
+
+ /* Set initial device state */
+ device.state = POWERED;
+ device.configuration = 0;
+ device.suspended = false;
+}
+
+CONTROL_TRANSFER * USBDevice::getTransferPtr(void)
+{
+ return &transfer;
+}
+
+bool USBDevice::addEndpoint(uint8_t endpoint, uint32_t maxPacket)
+{
+ return realiseEndpoint(endpoint, maxPacket, 0);
+}
+
+bool USBDevice::addRateFeedbackEndpoint(uint8_t endpoint, uint32_t maxPacket)
+{
+ /* For interrupt endpoints only */
+ return realiseEndpoint(endpoint, maxPacket, RATE_FEEDBACK_MODE);
+}
+
+uint8_t * USBDevice::findDescriptor(uint8_t descriptorType)
+{
+ /* Find a descriptor within the list of descriptors */
+ /* following a configuration descriptor. */
+ uint16_t wTotalLength;
+ uint8_t *ptr;
+
+ if (configurationDesc() == NULL)
+ {
+ return NULL;
+ }
+
+ /* Check this is a configuration descriptor */
+ if ((configurationDesc()[0] != CONFIGURATION_DESCRIPTOR_LENGTH) \
+ || (configurationDesc()[1] != CONFIGURATION_DESCRIPTOR))
+ {
+ return NULL;
+ }
+
+ wTotalLength = configurationDesc()[2] | (configurationDesc()[3] << 8);
+
+ /* Check there are some more descriptors to follow */
+ if (wTotalLength <= (CONFIGURATION_DESCRIPTOR_LENGTH+2))
+ /* +2 is for bLength and bDescriptorType of next descriptor */
+ {
+ return NULL;
+ }
+
+ /* Start at first descriptor after the configuration descriptor */
+ ptr = &(configurationDesc()[CONFIGURATION_DESCRIPTOR_LENGTH]);
+
+ do {
+ if (ptr[1] /* bDescriptorType */ == descriptorType)
+ {
+ /* Found */
+ return ptr;
+ }
+
+ /* Skip to next descriptor */
+ ptr += ptr[0]; /* bLength */
+ } while (ptr < (configurationDesc() + wTotalLength));
+
+ /* Reached end of the descriptors - not found */
+ return NULL;
+}
+
+
+void USBDevice::connectStateChanged(unsigned int connected)
+{
+}
+
+void USBDevice::suspendStateChanged(unsigned int suspended)
+{
+}
+
+
+USBDevice::USBDevice(uint16_t vendor_id, uint16_t product_id, uint16_t product_release){
+ VENDOR_ID = vendor_id;
+ PRODUCT_ID = product_id;
+ PRODUCT_RELEASE = product_release;
+
+ /* Set initial device state */
+ device.state = POWERED;
+ device.configuration = 0;
+ device.suspended = false;
+};
+
+
+bool USBDevice::readStart(uint8_t endpoint, uint32_t maxSize)
+{
+ return endpointRead(endpoint, maxSize) == EP_PENDING;
+}
+
+
+bool USBDevice::write(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if (size > maxSize)
+ {
+ return false;
+ }
+
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Send report */
+ result = endpointWrite(endpoint, buffer, size);
+
+ if (result != EP_PENDING)
+ {
+ return false;
+ }
+
+ /* Wait for completion */
+ do {
+ result = endpointWriteResult(endpoint);
+ } while ((result == EP_PENDING) && configured());
+
+ return (result == EP_COMPLETED);
+}
+
+
+bool USBDevice::writeNB(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if (size > maxSize)
+ {
+ return false;
+ }
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Send report */
+ result = endpointWrite(endpoint, buffer, size);
+
+ if (result != EP_PENDING)
+ {
+ return false;
+ }
+
+ result = endpointWriteResult(endpoint);
+
+ return (result == EP_COMPLETED);
+}
+
+
+
+bool USBDevice::readEP(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Wait for completion */
+ do {
+ result = endpointReadResult(endpoint, buffer, size);
+ } while ((result == EP_PENDING) && configured());
+
+ return (result == EP_COMPLETED);
+}
+
+
+bool USBDevice::readEP_NB(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if(!configured()) {
+ return false;
+ }
+
+ result = endpointReadResult(endpoint, buffer, size);
+
+ return (result == EP_COMPLETED);
+}
+
+
+
+uint8_t * USBDevice::deviceDesc() {
+ static uint8_t deviceDescriptor[] = {
+ DEVICE_DESCRIPTOR_LENGTH, /* bLength */
+ DEVICE_DESCRIPTOR, /* bDescriptorType */
+ LSB(USB_VERSION_2_0), /* bcdUSB (LSB) */
+ MSB(USB_VERSION_2_0), /* bcdUSB (MSB) */
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceprotocol */
+ MAX_PACKET_SIZE_EP0, /* bMaxPacketSize0 */
+ (uint8_t)(LSB(VENDOR_ID)), /* idVendor (LSB) */
+ (uint8_t)(MSB(VENDOR_ID)), /* idVendor (MSB) */
+ (uint8_t)(LSB(PRODUCT_ID)), /* idProduct (LSB) */
+ (uint8_t)(MSB(PRODUCT_ID)), /* idProduct (MSB) */
+ (uint8_t)(LSB(PRODUCT_RELEASE)), /* bcdDevice (LSB) */
+ (uint8_t)(MSB(PRODUCT_RELEASE)), /* bcdDevice (MSB) */
+ STRING_OFFSET_IMANUFACTURER, /* iManufacturer */
+ STRING_OFFSET_IPRODUCT, /* iProduct */
+ STRING_OFFSET_ISERIAL, /* iSerialNumber */
+ 0x01 /* bNumConfigurations */
+ };
+ return deviceDescriptor;
+}
+
+uint8_t * USBDevice::stringLangidDesc() {
+ static uint8_t stringLangidDescriptor[] = {
+ 0x04, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 0x09,0x04, /*bString Lang ID - 0x0409 - English*/
+ };
+ return stringLangidDescriptor;
+}
+
+uint8_t * USBDevice::stringImanufacturerDesc() {
+ static uint8_t stringImanufacturerDescriptor[] = {
+ 0x12, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'm',0,'b',0,'e',0,'d',0,'.',0,'o',0,'r',0,'g',0, /*bString iManufacturer - mbed.org*/
+ };
+ return stringImanufacturerDescriptor;
+}
+
+uint8_t * USBDevice::stringIserialDesc() {
+ static uint8_t stringIserialDescriptor[] = {
+ 0x16, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ '0',0,'1',0,'2',0,'3',0,'4',0,'5',0,'6',0,'7',0,'8',0,'9',0, /*bString iSerial - 0123456789*/
+ };
+ return stringIserialDescriptor;
+}
+
+uint8_t * USBDevice::stringIConfigurationDesc() {
+ static uint8_t stringIconfigurationDescriptor[] = {
+ 0x06, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ '0',0,'1',0, /*bString iConfiguration - 01*/
+ };
+ return stringIconfigurationDescriptor;
+}
+
+uint8_t * USBDevice::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'U',0,'S',0,'B',0, /*bString iInterface - USB*/
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBDevice::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'U',0,'S',0,'B',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 /*bString iProduct - USB DEVICE*/
+ };
+ return stringIproductDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h
new file mode 100644
index 000000000..a25ca1adf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h
@@ -0,0 +1,271 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBDEVICE_H
+#define USBDEVICE_H
+
+#include "mbed.h"
+#include "USBDevice_Types.h"
+#include "USBHAL.h"
+
+class USBDevice: public USBHAL
+{
+public:
+ USBDevice(uint16_t vendor_id, uint16_t product_id, uint16_t product_release);
+
+ /*
+ * Check if the device is configured
+ *
+ * @returns true if configured, false otherwise
+ */
+ bool configured(void);
+
+ /*
+ * Connect a device
+ *
+ * @param blocking: block if not configured
+ */
+ void connect(bool blocking = true);
+
+ /*
+ * Disconnect a device
+ */
+ void disconnect(void);
+
+ /*
+ * Add an endpoint
+ *
+ * @param endpoint endpoint which will be added
+ * @param maxPacket Maximum size of a packet which can be sent for this endpoint
+ * @returns true if successful, false otherwise
+ */
+ bool addEndpoint(uint8_t endpoint, uint32_t maxPacket);
+
+ /*
+ * Start a reading on a certain endpoint.
+ * You can access the result of the reading by USBDevice_read
+ *
+ * @param endpoint endpoint which will be read
+ * @param maxSize the maximum length that can be read
+ * @return true if successful
+ */
+ bool readStart(uint8_t endpoint, uint32_t maxSize);
+
+ /*
+ * Read a certain endpoint. Before calling this function, USBUSBDevice_readStart
+ * must be called.
+ *
+ * Warning: blocking
+ *
+ * @param endpoint endpoint which will be read
+ * @param buffer buffer will be filled with the data received
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize);
+
+ /*
+ * Read a certain endpoint.
+ *
+ * Warning: non blocking
+ *
+ * @param endpoint endpoint which will be read
+ * @param buffer buffer will be filled with the data received (if data are available)
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP_NB(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize);
+
+ /*
+ * Write a certain endpoint.
+ *
+ * Warning: blocking
+ *
+ * @param endpoint endpoint to write
+ * @param buffer data contained in buffer will be write
+ * @param size the number of bytes to write
+ * @param maxSize the maximum length that can be written on this endpoint
+ */
+ bool write(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize);
+
+
+ /*
+ * Write a certain endpoint.
+ *
+ * Warning: non blocking
+ *
+ * @param endpoint endpoint to write
+ * @param buffer data contained in buffer will be write
+ * @param size the number of bytes to write
+ * @param maxSize the maximum length that can be written on this endpoint
+ */
+ bool writeNB(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize);
+
+
+ /*
+ * Called by USBDevice layer on bus reset. Warning: Called in ISR context
+ *
+ * May be used to reset state
+ */
+ virtual void USBCallback_busReset(void) {};
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request() { return false; };
+
+ /*
+ * Called by USBDevice on Endpoint0 request completion
+ * if the 'notify' flag has been set to true. Warning: Called in ISR context
+ *
+ * In this case it is used to indicate that a HID report has
+ * been received from the host on endpoint 0
+ *
+ * @param buf buffer received on endpoint 0
+ * @param length length of this buffer
+ */
+ virtual void USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {};
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration) { return false; };
+
+ /*
+ * Called by USBDevice layer. Set interface/alternate of the device.
+ *
+ * @param interface Number of the interface to be configured
+ * @param alternate Number of the alternate to be configured
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setInterface(uint16_t interface, uint8_t alternate) { return false; };
+
+ /*
+ * Get device descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the device descriptor
+ */
+ virtual uint8_t * deviceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc(){return NULL;};
+
+ /*
+ * Get string lang id descriptor
+ *
+ * @return pointer to the string lang id descriptor
+ */
+ virtual uint8_t * stringLangidDesc();
+
+ /*
+ * Get string manufacturer descriptor
+ *
+ * @returns pointer to the string manufacturer descriptor
+ */
+ virtual uint8_t * stringImanufacturerDesc();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string serial descriptor
+ *
+ * @returns pointer to the string serial descriptor
+ */
+ virtual uint8_t * stringIserialDesc();
+
+ /*
+ * Get string configuration descriptor
+ *
+ * @returns pointer to the string configuration descriptor
+ */
+ virtual uint8_t * stringIConfigurationDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get the length of the report descriptor
+ *
+ * @returns length of the report descriptor
+ */
+ virtual uint16_t reportDescLength() { return 0; };
+
+
+
+protected:
+ virtual void busReset(void);
+ virtual void EP0setupCallback(void);
+ virtual void EP0out(void);
+ virtual void EP0in(void);
+ virtual void connectStateChanged(unsigned int connected);
+ virtual void suspendStateChanged(unsigned int suspended);
+ uint8_t * findDescriptor(uint8_t descriptorType);
+ CONTROL_TRANSFER * getTransferPtr(void);
+
+ uint16_t VENDOR_ID;
+ uint16_t PRODUCT_ID;
+ uint16_t PRODUCT_RELEASE;
+
+private:
+ bool addRateFeedbackEndpoint(uint8_t endpoint, uint32_t maxPacket);
+ bool requestGetDescriptor(void);
+ bool controlOut(void);
+ bool controlIn(void);
+ bool requestSetAddress(void);
+ bool requestSetConfiguration(void);
+ bool requestSetFeature(void);
+ bool requestClearFeature(void);
+ bool requestGetStatus(void);
+ bool requestSetup(void);
+ bool controlSetup(void);
+ void decodeSetupPacket(uint8_t *data, SETUP_PACKET *packet);
+ bool requestGetConfiguration(void);
+ bool requestGetInterface(void);
+ bool requestSetInterface(void);
+
+ CONTROL_TRANSFER transfer;
+ USB_DEVICE device;
+
+ uint16_t currentInterface;
+ uint8_t currentAlternate;
+};
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h
new file mode 100644
index 000000000..19bc1c2f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h
@@ -0,0 +1,83 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBDEVICE_TYPES_H
+#define USBDEVICE_TYPES_H
+
+/* Standard requests */
+#define GET_STATUS (0)
+#define CLEAR_FEATURE (1)
+#define SET_FEATURE (3)
+#define SET_ADDRESS (5)
+#define GET_DESCRIPTOR (6)
+#define SET_DESCRIPTOR (7)
+#define GET_CONFIGURATION (8)
+#define SET_CONFIGURATION (9)
+#define GET_INTERFACE (10)
+#define SET_INTERFACE (11)
+
+/* bmRequestType.dataTransferDirection */
+#define HOST_TO_DEVICE (0)
+#define DEVICE_TO_HOST (1)
+
+/* bmRequestType.Type*/
+#define STANDARD_TYPE (0)
+#define CLASS_TYPE (1)
+#define VENDOR_TYPE (2)
+#define RESERVED_TYPE (3)
+
+/* bmRequestType.Recipient */
+#define DEVICE_RECIPIENT (0)
+#define INTERFACE_RECIPIENT (1)
+#define ENDPOINT_RECIPIENT (2)
+#define OTHER_RECIPIENT (3)
+
+/* Descriptors */
+#define DESCRIPTOR_TYPE(wValue) (wValue >> 8)
+#define DESCRIPTOR_INDEX(wValue) (wValue & 0xff)
+
+typedef struct {
+ struct {
+ uint8_t dataTransferDirection;
+ uint8_t Type;
+ uint8_t Recipient;
+ } bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} SETUP_PACKET;
+
+typedef struct {
+ SETUP_PACKET setup;
+ uint8_t *ptr;
+ uint32_t remaining;
+ uint8_t direction;
+ bool zlp;
+ bool notify;
+} CONTROL_TRANSFER;
+
+typedef enum {ATTACHED, POWERED, DEFAULT, ADDRESS, CONFIGURED} DEVICE_STATE;
+
+typedef struct {
+ volatile DEVICE_STATE state;
+ uint8_t configuration;
+ bool suspended;
+} USB_DEVICE;
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h
new file mode 100644
index 000000000..48950986a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBENDPOINTS_H
+#define USBENDPOINTS_H
+
+/* SETUP packet size */
+#define SETUP_PACKET_SIZE (8)
+
+/* Options flags for configuring endpoints */
+#define DEFAULT_OPTIONS (0)
+#define SINGLE_BUFFERED (1U << 0)
+#define ISOCHRONOUS (1U << 1)
+#define RATE_FEEDBACK_MODE (1U << 2) /* Interrupt endpoints only */
+
+/* Endpoint transfer status, for endpoints > 0 */
+typedef enum {
+ EP_COMPLETED, /* Transfer completed */
+ EP_PENDING, /* Transfer in progress */
+ EP_INVALID, /* Invalid parameter */
+ EP_STALLED, /* Endpoint stalled */
+} EP_STATUS;
+
+/* Include configuration for specific target */
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
+#include "USBEndpoints_LPC17_LPC23.h"
+#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
+#include "USBEndpoints_LPC11U.h"
+#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+#include "USBEndpoints_KL25Z.h"
+#elif defined (TARGET_STM32F4)
+#include "USBEndpoints_STM32F4.h"
+#elif defined (TARGET_RZ_A1H)
+#include "USBEndpoints_RZ_A1H.h"
+#elif defined(TARGET_Maxim)
+#include "USBEndpoints_Maxim.h"
+#else
+#error "Unknown target type"
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h
new file mode 100644
index 000000000..87721a21c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h
@@ -0,0 +1,99 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. */
+/* ---------------- */
+#define EP0OUT (0)
+#define EP0IN (1)
+#define EP1OUT (2)
+#define EP1IN (3)
+#define EP2OUT (4)
+#define EP2IN (5)
+#define EP3OUT (6)
+#define EP3IN (7)
+#define EP4OUT (8)
+#define EP4IN (9)
+#define EP5OUT (10)
+#define EP5IN (11)
+#define EP6OUT (12)
+#define EP6IN (13)
+#define EP7OUT (14)
+#define EP7IN (15)
+#define EP8OUT (16)
+#define EP8IN (17)
+#define EP9OUT (18)
+#define EP9IN (19)
+#define EP10OUT (20)
+#define EP10IN (21)
+#define EP11OUT (22)
+#define EP11IN (23)
+#define EP12OUT (24)
+#define EP12IN (25)
+#define EP13OUT (26)
+#define EP13IN (27)
+#define EP14OUT (28)
+#define EP14IN (29)
+#define EP15OUT (30)
+#define EP15IN (31)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (1023)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (64)
+#define MAX_PACKET_SIZE_EP7 (64)
+#define MAX_PACKET_SIZE_EP8 (64)
+#define MAX_PACKET_SIZE_EP9 (64)
+#define MAX_PACKET_SIZE_EP10 (64)
+#define MAX_PACKET_SIZE_EP11 (64)
+#define MAX_PACKET_SIZE_EP12 (64)
+#define MAX_PACKET_SIZE_EP13 (64)
+#define MAX_PACKET_SIZE_EP14 (64)
+#define MAX_PACKET_SIZE_EP15 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h
new file mode 100644
index 000000000..b4ddaa514
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h
@@ -0,0 +1,71 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (5)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP4OUT (8) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP4IN (9) /* Int/Bulk/Iso 64/64/1023 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP4 (64) /* Int/Bulk */
+
+#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP4_ISO (1023) /* Isochronous */
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoint */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoint */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoint */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h
new file mode 100644
index 000000000..383b7e36f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h
@@ -0,0 +1,99 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Interrupt 64 No */
+#define EP1IN (3) /* Interrupt 64 No */
+#define EP2OUT (4) /* Bulk 64 Yes */
+#define EP2IN (5) /* Bulk 64 Yes */
+#define EP3OUT (6) /* Isochronous 1023 Yes */
+#define EP3IN (7) /* Isochronous 1023 Yes */
+#define EP4OUT (8) /* Interrupt 64 No */
+#define EP4IN (9) /* Interrupt 64 No */
+#define EP5OUT (10) /* Bulk 64 Yes */
+#define EP5IN (11) /* Bulk 64 Yes */
+#define EP6OUT (12) /* Isochronous 1023 Yes */
+#define EP6IN (13) /* Isochronous 1023 Yes */
+#define EP7OUT (14) /* Interrupt 64 No */
+#define EP7IN (15) /* Interrupt 64 No */
+#define EP8OUT (16) /* Bulk 64 Yes */
+#define EP8IN (17) /* Bulk 64 Yes */
+#define EP9OUT (18) /* Isochronous 1023 Yes */
+#define EP9IN (19) /* Isochronous 1023 Yes */
+#define EP10OUT (20) /* Interrupt 64 No */
+#define EP10IN (21) /* Interrupt 64 No */
+#define EP11OUT (22) /* Bulk 64 Yes */
+#define EP11IN (23) /* Bulk 64 Yes */
+#define EP12OUT (24) /* Isochronous 1023 Yes */
+#define EP12IN (25) /* Isochronous 1023 Yes */
+#define EP13OUT (26) /* Interrupt 64 No */
+#define EP13IN (27) /* Interrupt 64 No */
+#define EP14OUT (28) /* Bulk 64 Yes */
+#define EP14IN (29) /* Bulk 64 Yes */
+#define EP15OUT (30) /* Bulk 64 Yes */
+#define EP15IN (31) /* Bulk 64 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (1023)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (1023)
+#define MAX_PACKET_SIZE_EP7 (64)
+#define MAX_PACKET_SIZE_EP8 (64)
+#define MAX_PACKET_SIZE_EP9 (1023)
+#define MAX_PACKET_SIZE_EP10 (64)
+#define MAX_PACKET_SIZE_EP11 (64)
+#define MAX_PACKET_SIZE_EP12 (1023)
+#define MAX_PACKET_SIZE_EP13 (64)
+#define MAX_PACKET_SIZE_EP14 (64)
+#define MAX_PACKET_SIZE_EP15 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h
new file mode 100644
index 000000000..5cd3905c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (8)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+#define DIR_OUT 0x00
+#define DIR_IN 0x01
+#define EP_NUM(ep) (ep >> 1)
+#define IN_EP(ep) (ep & DIR_IN)
+#define OUT_EP(ep) (!(ep & DIR_IN))
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. */
+/* ---------------- */
+#define EP0OUT ((0 << 1) | DIR_OUT)
+#define EP0IN ((0 << 1) | DIR_IN)
+#define EP1OUT ((1 << 1) | DIR_OUT)
+#define EP1IN ((1 << 1) | DIR_IN)
+#define EP2OUT ((2 << 1) | DIR_OUT)
+#define EP2IN ((2 << 1) | DIR_IN)
+#define EP3OUT ((3 << 1) | DIR_OUT)
+#define EP3IN ((3 << 1) | DIR_IN)
+#define EP4OUT ((4 << 1) | DIR_OUT)
+#define EP4IN ((4 << 1) | DIR_IN)
+#define EP5OUT ((5 << 1) | DIR_OUT)
+#define EP5IN ((5 << 1) | DIR_IN)
+#define EP6OUT ((6 << 1) | DIR_OUT)
+#define EP6IN ((6 << 1) | DIR_IN)
+#define EP7OUT ((7 << 1) | DIR_OUT)
+#define EP7IN ((7 << 1) | DIR_IN)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (64)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (64)
+#define MAX_PACKET_SIZE_EP7 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP1OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP1_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP3OUT)
+#define EPINT_IN (EP4IN)
+#define EPINT_OUT_callback EP3_OUT_callback
+#define EPINT_IN_callback EP4_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (64)
+#define MAX_PACKET_SIZE_EPINT (64)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h
new file mode 100644
index 000000000..f25a3d862
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h
@@ -0,0 +1,85 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxSiz DoubleBuf pipe */
+/* ---------------- --------- ------ --------- ---- */
+#define EP0OUT (0) /* Control 256 No 0 */
+#define EP0IN (1) /* Control 256 No 0 */
+#define EP1OUT (2) /* Int 64 No 6 */
+#define EP1IN (3) /* Int 64 No 7 */
+#define EP2OUT (4) /* Bulk 2048 Yes 3 */
+#define EP2IN (5) /* Bulk 2048 Yes 4 */
+#define EP3OUT (6) /* Bulk/Iso 2048 Yes 1 */
+#define EP3IN (7) /* Bulk/Iso 2048 Yes 2 */
+/*following EP is not configured in sample program*/
+#define EP6IN (8) /* Bulk 2048 Yes 5 */
+#define EP8IN (9) /* Int 64 No 8 */
+#define EP9IN (10) /* Bulk 512 Bulk 9 */
+#define EP10IN (11) /* Int/Bulk 2048 Bulk 10 */
+#define EP11IN (12) /* Bulk 2048 Yes 11 */
+#define EP12IN (13) /* Bulk 2048 Yes 12 */
+#define EP13IN (14) /* Bulk 2048 Yes 13 */
+#define EP14IN (15) /* Bulk 2048 Yes 14 */
+#define EP15IN (16) /* Bulk 2048 Yes 15 */
+
+/* Maximum Packet sizes */
+#define MAX_PACKET_SIZE_EP0 (64) /*pipe0/pipe0: control */
+#define MAX_PACKET_SIZE_EP1 (64) /*pipe6/pipe7: interrupt */
+#define MAX_PACKET_SIZE_EP2 (512) /*pipe3/pipe4: bulk */
+#define MAX_PACKET_SIZE_EP3 (512) /*pipe1/pipe2: isochronous */
+#define MAX_PACKET_SIZE_EP6 (64) /*pipe5: Note *1 */
+#define MAX_PACKET_SIZE_EP8 (64) /*pipe7: Note *1 */
+#define MAX_PACKET_SIZE_EP9 (512) /*pipe8: Note *1 */
+#define MAX_PACKET_SIZE_EP10 (512) /*pipe9: Note *1 */
+#define MAX_PACKET_SIZE_EP11 (512) /*pipe10: Note *1 */
+#define MAX_PACKET_SIZE_EP12 (512) /*pipe11: Note *1 */
+#define MAX_PACKET_SIZE_EP13 (512) /*pipe12: Note *1 */
+#define MAX_PACKET_SIZE_EP14 (512) /*pipe13: Note *1 */
+#define MAX_PACKET_SIZE_EP15 (512) /*pipe14: Note *1 */
+/* Note *1: This pipe is not configure in sample program */
+
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
+
+/*EOF*/
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h
new file mode 100644
index 000000000..1d520d11c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (4)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
+
+#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoint */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoint */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoint */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h
new file mode 100644
index 000000000..faf22e8d5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h
@@ -0,0 +1,121 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBBUSINTERFACE_H
+#define USBBUSINTERFACE_H
+
+#include "mbed.h"
+#include "USBEndpoints.h"
+#include "toolchain.h"
+
+//#ifdef __GNUC__
+//#define __packed __attribute__ ((__packed__))
+//#endif
+
+class USBHAL {
+public:
+ /* Configuration */
+ USBHAL();
+ ~USBHAL();
+ void connect(void);
+ void disconnect(void);
+ void configureDevice(void);
+ void unconfigureDevice(void);
+ void setAddress(uint8_t address);
+ void remoteWakeup(void);
+
+ /* Endpoint 0 */
+ void EP0setup(uint8_t *buffer);
+ void EP0read(void);
+ void EP0readStage(void);
+ uint32_t EP0getReadResult(uint8_t *buffer);
+ void EP0write(uint8_t *buffer, uint32_t size);
+ void EP0getWriteResult(void);
+ void EP0stall(void);
+
+ /* Other endpoints */
+ EP_STATUS endpointRead(uint8_t endpoint, uint32_t maximumSize);
+ EP_STATUS endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead);
+ EP_STATUS endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size);
+ EP_STATUS endpointWriteResult(uint8_t endpoint);
+ void stallEndpoint(uint8_t endpoint);
+ void unstallEndpoint(uint8_t endpoint);
+ bool realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options);
+ bool getEndpointStallState(unsigned char endpoint);
+ uint32_t endpointReadcore(uint8_t endpoint, uint8_t *buffer);
+
+protected:
+ virtual void busReset(void){};
+ virtual void EP0setupCallback(void){};
+ virtual void EP0out(void){};
+ virtual void EP0in(void){};
+ virtual void connectStateChanged(unsigned int connected){};
+ virtual void suspendStateChanged(unsigned int suspended){};
+ virtual void SOF(int frameNumber){};
+
+ virtual bool EP1_OUT_callback(){return false;};
+ virtual bool EP1_IN_callback(){return false;};
+ virtual bool EP2_OUT_callback(){return false;};
+ virtual bool EP2_IN_callback(){return false;};
+ virtual bool EP3_OUT_callback(){return false;};
+ virtual bool EP3_IN_callback(){return false;};
+#if !defined(TARGET_STM32F4)
+ virtual bool EP4_OUT_callback(){return false;};
+ virtual bool EP4_IN_callback(){return false;};
+#if !(defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549))
+ virtual bool EP5_OUT_callback(){return false;};
+ virtual bool EP5_IN_callback(){return false;};
+ virtual bool EP6_OUT_callback(){return false;};
+ virtual bool EP6_IN_callback(){return false;};
+ virtual bool EP7_OUT_callback(){return false;};
+ virtual bool EP7_IN_callback(){return false;};
+ virtual bool EP8_OUT_callback(){return false;};
+ virtual bool EP8_IN_callback(){return false;};
+ virtual bool EP9_OUT_callback(){return false;};
+ virtual bool EP9_IN_callback(){return false;};
+ virtual bool EP10_OUT_callback(){return false;};
+ virtual bool EP10_IN_callback(){return false;};
+ virtual bool EP11_OUT_callback(){return false;};
+ virtual bool EP11_IN_callback(){return false;};
+ virtual bool EP12_OUT_callback(){return false;};
+ virtual bool EP12_IN_callback(){return false;};
+ virtual bool EP13_OUT_callback(){return false;};
+ virtual bool EP13_IN_callback(){return false;};
+ virtual bool EP14_OUT_callback(){return false;};
+ virtual bool EP14_IN_callback(){return false;};
+ virtual bool EP15_OUT_callback(){return false;};
+ virtual bool EP15_IN_callback(){return false;};
+#endif
+#endif
+
+private:
+ void usbisr(void);
+ static void _usbisr(void);
+ static USBHAL * instance;
+
+#if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+ bool (USBHAL::*epCallback[10 - 2])(void);
+#elif defined(TARGET_STM32F4)
+ bool (USBHAL::*epCallback[8 - 2])(void);
+#else
+ bool (USBHAL::*epCallback[32 - 2])(void);
+#endif
+
+
+};
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
new file mode 100644
index 000000000..f92a99979
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
@@ -0,0 +1,551 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+
+#include "USBHAL.h"
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete = 0;
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1<<(endpoint))
+
+// Convert physical to logical
+#define PHY_TO_LOG(endpoint) ((endpoint)>>1)
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+#define BD_OWN_MASK (1<<7)
+#define BD_DATA01_MASK (1<<6)
+#define BD_KEEP_MASK (1<<5)
+#define BD_NINC_MASK (1<<4)
+#define BD_DTS_MASK (1<<3)
+#define BD_STALL_MASK (1<<2)
+
+#define TX 1
+#define RX 0
+#define ODD 0
+#define EVEN 1
+// this macro waits a physical endpoint number
+#define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
+
+#define SETUP_TOKEN 0x0D
+#define IN_TOKEN 0x09
+#define OUT_TOKEN 0x01
+#define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
+
+// for each endpt: 8 bytes
+typedef struct BDT {
+ uint8_t info; // BD[0:7]
+ uint8_t dummy; // RSVD: BD[8:15]
+ uint16_t byte_count; // BD[16:32]
+ uint32_t address; // Addr
+} BDT;
+
+
+// there are:
+// * 16 bidirectionnal endpt -> 32 physical endpt
+// * as there are ODD and EVEN buffer -> 32*2 bdt
+__attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
+uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
+uint8_t * endpoint_buffer_iso[2*2];
+
+static uint8_t set_addr = 0;
+static uint8_t addr = 0;
+
+static uint32_t Data1 = 0x55555555;
+
+static uint32_t frameNumber() {
+ return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
+}
+
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ return 0;
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB0_IRQn);
+
+#if defined(TARGET_K64F)
+ MPU->CESR=0;
+#endif
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+#if defined(TARGET_KL43Z)
+ // enable USBFS clock
+ SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
+
+ // enable the IRC48M clock
+ USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
+
+ // enable the USB clock recovery tuning
+ USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+
+ // choose usb src clock
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
+#else
+ // choose usb src as PLL
+ SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
+ SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT));
+
+ // enable OTG clock
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
+#endif
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
+ NVIC_EnableIRQ(USB0_IRQn);
+
+ // USB Module Configuration
+ // Reset USB Module
+ USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+ while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+ // Set BDT Base Register
+ USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
+ USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
+ USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
+
+ // Clear interrupt flag
+ USB0->ISTAT = 0xff;
+
+ // USB Interrupt Enablers
+ USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
+ USB_INTEN_SOFTOKEN_MASK |
+ USB_INTEN_ERROREN_MASK |
+ USB_INTEN_USBRSTEN_MASK;
+
+ // Disable weak pull downs
+ USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
+
+ USB0->USBTRC0 |= 0x40;
+}
+
+USBHAL::~USBHAL(void) { }
+
+void USBHAL::connect(void) {
+ // enable USB
+ USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
+ // Pull up enable
+ USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
+}
+
+void USBHAL::disconnect(void) {
+ // disable USB
+ USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
+ // Pull up disable
+ USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+
+ //Free buffers if required:
+ for (int i = 0; i<(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2; i++) {
+ free(endpoint_buffer[i]);
+ endpoint_buffer[i] = NULL;
+ }
+ free(endpoint_buffer_iso[2]);
+ endpoint_buffer_iso[2] = NULL;
+ free(endpoint_buffer_iso[0]);
+ endpoint_buffer_iso[0] = NULL;
+}
+
+void USBHAL::configureDevice(void) {
+ // not needed
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // not needed
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ // we don't set the address now otherwise the usb controller does not ack
+ // we set a flag instead
+ // see usbisr when an IN token is received
+ set_addr = 1;
+ addr = address;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ uint32_t handshake_flag = 0;
+ uint8_t * buf;
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return false;
+ }
+
+ uint32_t log_endpoint = PHY_TO_LOG(endpoint);
+
+ if ((flags & ISOCHRONOUS) == 0) {
+ handshake_flag = USB_ENDPT_EPHSHK_MASK;
+ if (IN_EP(endpoint)) {
+ if (endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] == NULL)
+ endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] = (uint8_t *) malloc (64*2);
+ buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)][0];
+ } else {
+ if (endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] == NULL)
+ endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] = (uint8_t *) malloc (64*2);
+ buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)][0];
+ }
+ } else {
+ if (IN_EP(endpoint)) {
+ if (endpoint_buffer_iso[2] == NULL)
+ endpoint_buffer_iso[2] = (uint8_t *) malloc (1023*2);
+ buf = &endpoint_buffer_iso[2][0];
+ } else {
+ if (endpoint_buffer_iso[0] == NULL)
+ endpoint_buffer_iso[0] = (uint8_t *) malloc (1023*2);
+ buf = &endpoint_buffer_iso[0][0];
+ }
+ }
+
+ // IN endpt -> device to host (TX)
+ if (IN_EP(endpoint)) {
+ USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
+ USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
+ bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
+ bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
+ }
+ // OUT endpt -> host to device (RX)
+ else {
+ USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
+ USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
+ bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
+ }
+
+ Data1 |= (1 << endpoint);
+
+ return true;
+}
+
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer) {
+ uint32_t sz;
+ endpointReadResult(EP0OUT, buffer, &sz);
+}
+
+void USBHAL::EP0readStage(void) {
+ Data1 &= ~1UL; // set DATA0
+ bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
+}
+
+void USBHAL::EP0read(void) {
+ uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
+ bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ uint32_t sz;
+ endpointReadResult(EP0OUT, buffer, &sz);
+ return sz;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+}
+
+void USBHAL::EP0stall(void) {
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ endpoint = PHY_TO_LOG(endpoint);
+ uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
+ bdt[idx].byte_count = maximumSize;
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+ uint32_t n, sz, idx, setup = 0;
+ uint8_t not_iso;
+ uint8_t * ep_buf;
+
+ uint32_t log_endpoint = PHY_TO_LOG(endpoint);
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return EP_INVALID;
+ }
+
+ // if read on a IN endpoint -> error
+ if (IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ idx = EP_BDT_IDX(log_endpoint, RX, 0);
+ sz = bdt[idx].byte_count;
+ not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
+ return EP_PENDING;
+ }
+
+ if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
+ setup = 1;
+ }
+
+ // non iso endpoint
+ if (not_iso) {
+ ep_buf = endpoint_buffer[idx];
+ } else {
+ ep_buf = endpoint_buffer_iso[0];
+ }
+
+ for (n = 0; n < sz; n++) {
+ buffer[n] = ep_buf[n];
+ }
+
+ if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
+ if (setup && (buffer[6] == 0)) // if no setup data stage,
+ Data1 &= ~1UL; // set DATA0
+ else
+ Data1 ^= (1 << endpoint);
+ }
+
+ if (((Data1 >> endpoint) & 1)) {
+ bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
+ }
+ else {
+ bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
+ }
+
+ USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ *bytesRead = sz;
+
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t idx, n;
+ uint8_t * ep_buf;
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return EP_INVALID;
+ }
+
+ // if write on a OUT endpoint -> error
+ if (OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
+ bdt[idx].byte_count = size;
+
+
+ // non iso endpoint
+ if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
+ ep_buf = endpoint_buffer[idx];
+ } else {
+ ep_buf = endpoint_buffer_iso[2];
+ }
+
+ for (n = 0; n < size; n++) {
+ ep_buf[n] = data[n];
+ }
+
+ if ((Data1 >> endpoint) & 1) {
+ bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
+ } else {
+ bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
+ }
+
+ Data1 ^= (1 << endpoint);
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
+ return (stall) ? true : false;
+}
+
+void USBHAL::remoteWakeup(void) {
+ // [TODO]
+}
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t i;
+ uint8_t istat = USB0->ISTAT;
+
+ // reset interrupt
+ if (istat & USB_ISTAT_USBRST_MASK) {
+ // disable all endpt
+ for(i = 0; i < 16; i++) {
+ USB0->ENDPOINT[i].ENDPT = 0x00;
+ }
+
+ // enable control endpoint
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+
+ Data1 = 0x55555555;
+ USB0->CTL |= USB_CTL_ODDRST_MASK;
+
+ USB0->ISTAT = 0xFF; // clear all interrupt status flags
+ USB0->ERRSTAT = 0xFF; // clear all error flags
+ USB0->ERREN = 0xFF; // enable error interrupt sources
+ USB0->ADDR = 0x00; // set default address
+
+ return;
+ }
+
+ // resume interrupt
+ if (istat & USB_ISTAT_RESUME_MASK) {
+ USB0->ISTAT = USB_ISTAT_RESUME_MASK;
+ }
+
+ // SOF interrupt
+ if (istat & USB_ISTAT_SOFTOK_MASK) {
+ USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
+ // SOF event, read frame number
+ SOF(frameNumber());
+ }
+
+ // stall interrupt
+ if (istat & 1<<7) {
+ if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
+ USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+ USB0->ISTAT |= USB_ISTAT_STALL_MASK;
+ }
+
+ // token interrupt
+ if (istat & 1<<3) {
+ uint32_t num = (USB0->STAT >> 4) & 0x0F;
+ uint32_t dir = (USB0->STAT >> 3) & 0x01;
+ uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
+
+ // setup packet
+ if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
+ Data1 &= ~0x02;
+ bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
+ bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
+
+ // EP0 SETUP event (SETUP data received)
+ EP0setupCallback();
+
+ } else {
+ // OUT packet
+ if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
+ if (num == 0)
+ EP0out();
+ else {
+ epComplete |= (1 << EP(num));
+ if ((instance->*(epCallback[EP(num) - 2]))()) {
+ epComplete &= ~(1 << EP(num));
+ }
+ }
+ }
+
+ // IN packet
+ if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
+ if (num == 0) {
+ EP0in();
+ if (set_addr == 1) {
+ USB0->ADDR = addr & 0x7F;
+ set_addr = 0;
+ }
+ }
+ else {
+ epComplete |= (1 << (EP(num) + 1));
+ if ((instance->*(epCallback[EP(num) + 1 - 2]))()) {
+ epComplete &= ~(1 << (EP(num) + 1));
+ }
+ }
+ }
+ }
+
+ USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
+ }
+
+ // sleep interrupt
+ if (istat & 1<<4) {
+ USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
+ }
+
+ // error interrupt
+ if (istat & USB_ISTAT_ERROR_MASK) {
+ USB0->ERRSTAT = 0xFF;
+ USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
+ }
+}
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
new file mode 100644
index 000000000..1a5fa8c0f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
@@ -0,0 +1,738 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+
+#if defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+#define USB_IRQ USB_IRQ_IRQn
+#else
+#define USB_IRQ USB_IRQn
+#endif
+
+#include "USBHAL.h"
+
+USBHAL * USBHAL::instance;
+#if defined(TARGET_LPC1549)
+static uint8_t usbmem[2048] __attribute__((aligned(2048)));
+#endif
+
+// Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
+#define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Convert physical to logical
+#define PHY_TO_LOG(endpoint) ((endpoint)>>1)
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// USB RAM
+#if defined(TARGET_LPC1549)
+#define USB_RAM_START ((uint32_t)usbmem)
+#define USB_RAM_SIZE sizeof(usbmem)
+#else
+#define USB_RAM_START (0x20004000)
+#define USB_RAM_SIZE (0x00000800)
+#endif
+
+// SYSAHBCLKCTRL
+#if defined(TARGET_LPC1549)
+#define CLK_USB (1UL<<23)
+#else
+#define CLK_USB (1UL<<14)
+#define CLK_USBRAM (1UL<<27)
+#endif
+
+// USB Information register
+#define FRAME_NR(a) ((a) & 0x7ff) // Frame number
+
+// USB Device Command/Status register
+#define DEV_ADDR_MASK (0x7f) // Device address
+#define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
+#define DEV_EN (1UL<<7) // Device enable
+#define SETUP (1UL<<8) // SETUP token received
+#define PLL_ON (1UL<<9) // PLL enabled in suspend
+#define DCON (1UL<<16) // Device status - connect
+#define DSUS (1UL<<17) // Device status - suspend
+#define DCON_C (1UL<<24) // Connect change
+#define DSUS_C (1UL<<25) // Suspend change
+#define DRES_C (1UL<<26) // Reset change
+#define VBUSDEBOUNCED (1UL<<28) // Vbus detected
+
+// Endpoint Command/Status list
+#define CMDSTS_A (1UL<<31) // Active
+#define CMDSTS_D (1UL<<30) // Disable
+#define CMDSTS_S (1UL<<29) // Stall
+#define CMDSTS_TR (1UL<<28) // Toggle Reset
+#define CMDSTS_RF (1UL<<27) // Rate Feedback mode
+#define CMDSTS_TV (1UL<<27) // Toggle Value
+#define CMDSTS_T (1UL<<26) // Endpoint Type
+#define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
+#define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
+
+#define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
+
+// USB Non-endpoint interrupt sources
+#define FRAME_INT (1UL<<30)
+#define DEV_INT (1UL<<31)
+
+static volatile int epComplete = 0;
+
+// One entry for a double-buffered logical endpoint in the endpoint
+// command/status list. Endpoint 0 is single buffered, out[1] is used
+// for the SETUP packet and in[1] is not used
+typedef struct {
+ uint32_t out[2];
+ uint32_t in[2];
+} PACKED EP_COMMAND_STATUS;
+
+typedef struct {
+ uint8_t out[MAX_PACKET_SIZE_EP0];
+ uint8_t in[MAX_PACKET_SIZE_EP0];
+ uint8_t setup[SETUP_PACKET_SIZE];
+} PACKED CONTROL_TRANSFER;
+
+typedef struct {
+ uint32_t maxPacket;
+ uint32_t buffer[2];
+ uint32_t options;
+} PACKED EP_STATE;
+
+static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
+
+// Pointer to the endpoint command/status list
+static EP_COMMAND_STATUS *ep = NULL;
+
+// Pointer to endpoint 0 data (IN/OUT and SETUP)
+static CONTROL_TRANSFER *ct = NULL;
+
+// Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
+// initiating a remote wakeup event.
+static volatile uint32_t devCmdStat;
+
+// Pointers used to allocate USB RAM
+static uint32_t usbRamPtr = USB_RAM_START;
+static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
+
+#define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
+
+void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
+void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
+ if (size > 0) {
+ do {
+ *dst++ = *src++;
+ } while (--size > 0);
+ }
+}
+
+
+USBHAL::USBHAL(void) {
+ NVIC_DisableIRQ(USB_IRQ);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+
+#if defined(TARGET_LPC1549)
+ /* Set USB PLL input to system oscillator */
+ LPC_SYSCON->USBPLLCLKSEL = 0x01;
+
+ /* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
+ MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+ FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+ FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+ LPC_SYSCON->USBPLLCTRL = (0x3 | (1UL << 6));
+
+ /* Powerup USB PLL */
+ LPC_SYSCON->PDRUNCFG &= ~(CLK_USB);
+
+ /* Wait for PLL to lock */
+ while(!(LPC_SYSCON->USBPLLSTAT & 0x01));
+
+ /* enable USB main clock */
+ LPC_SYSCON->USBCLKSEL = 0x02;
+ LPC_SYSCON->USBCLKDIV = 1;
+
+ /* Enable AHB clock to the USB block. */
+ LPC_SYSCON->SYSAHBCLKCTRL1 |= CLK_USB;
+
+ /* power UP USB Phy */
+ LPC_SYSCON->PDRUNCFG &= ~(1UL << 9);
+
+ /* Reset USB block */
+ LPC_SYSCON->PRESETCTRL1 |= (CLK_USB);
+ LPC_SYSCON->PRESETCTRL1 &= ~(CLK_USB);
+
+#else
+ #if defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501)
+ // USB_VBUS input with pull-down
+ LPC_IOCON->PIO0_3 = 0x00000009;
+ #endif
+
+ // nUSB_CONNECT output
+ LPC_IOCON->PIO0_6 = 0x00000001;
+
+ // Enable clocks (USB registers, USB RAM)
+ LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
+
+ // Ensure device disconnected (DCON not set)
+ LPC_USB->DEVCMDSTAT = 0;
+#endif
+ // to ensure that the USB host sees the device as
+ // disconnected if the target CPU is reset.
+ wait(0.3);
+
+ // Reserve space in USB RAM for endpoint command/status list
+ // Must be 256 byte aligned
+ usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
+ ep = (EP_COMMAND_STATUS *)usbRamPtr;
+ usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
+ LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
+
+ // Reserve space in USB RAM for Endpoint 0
+ // Must be 64 byte aligned
+ usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
+ ct = (CONTROL_TRANSFER *)usbRamPtr;
+ usbRamPtr += sizeof(CONTROL_TRANSFER);
+ LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
+
+ // Setup command/status list for EP0
+ ep[0].out[0] = 0;
+ ep[0].in[0] = 0;
+ ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
+
+ // Route all interrupts to IRQ, some can be routed to
+ // USB_FIQ if you wish.
+ LPC_USB->INTROUTING = 0;
+
+ // Set device address 0, enable USB device, no remote wakeup
+ devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
+ instance = this;
+
+ //attach IRQ handler and enable interrupts
+ NVIC_SetVector(USB_IRQ, (uint32_t)&_usbisr);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected (DCON not set)
+ LPC_USB->DEVCMDSTAT = 0;
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQ);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQ);
+ devCmdStat |= DCON;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQ);
+ devCmdStat &= ~DCON;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+void USBHAL::configureDevice(void) {
+ // Not required
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // Not required
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ // Copy setup packet data
+ USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
+}
+
+void USBHAL::EP0read(void) {
+ // Start an endpoint 0 read
+
+ // The USB ISR will call USBDevice_EP0out() when a packet has been read,
+ // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
+ // read the data.
+
+ ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ // Complete an endpoint 0 read
+ uint32_t bytesRead;
+
+ // Find how many bytes were read
+ bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
+
+ // Copy data
+ USBMemCopy(buffer, ct->out, bytesRead);
+ return bytesRead;
+}
+
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ // Start and endpoint 0 write
+
+ // The USB ISR will call USBDevice_EP0in() when the data has
+ // been written, the USBDevice layer then calls
+ // USBBusInterface_EP0getWriteResult() to complete the transaction.
+
+ // Copy data
+ USBMemCopy(ct->in, buffer, size);
+
+ // Start transfer
+ ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
+}
+
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ uint8_t bf = 0;
+ uint32_t flags = 0;
+
+ //check which buffer must be filled
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ }
+
+ // if isochronous endpoint, T = 1
+ if(endpointState[endpoint].options & ISOCHRONOUS)
+ {
+ flags |= CMDSTS_T;
+ }
+
+ //Active the endpoint for reading
+ ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
+
+ uint8_t bf = 0;
+
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ else {
+ epComplete &= ~EP(endpoint);
+
+ //check which buffer has been filled
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered (here we read the previous buffer which was used)
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 0;
+ } else {
+ bf = 1;
+ }
+ }
+
+ // Find how many bytes were read
+ *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
+
+ // Copy data
+ USBMemCopy(data, ct->out, *bytesRead);
+ return EP_COMPLETED;
+ }
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ ep[0].in[0] = CMDSTS_S;
+ ep[0].out[0] = CMDSTS_S;
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ devCmdStat &= ~DEV_ADDR_MASK;
+ devCmdStat |= DEV_ADDR(address);
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t flags = 0;
+ uint32_t bf;
+
+ // Validate parameters
+ if (data == NULL) {
+ return EP_INVALID;
+ }
+
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return EP_INVALID;
+ }
+
+ if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
+ return EP_INVALID;
+ }
+
+ if (size > endpointState[endpoint].maxPacket) {
+ return EP_INVALID;
+ }
+
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ } else {
+ // Single buffered
+ bf = 0;
+ }
+
+ // Check if already active
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
+ return EP_INVALID;
+ }
+
+ // Check if stalled
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
+ return EP_STALLED;
+ }
+
+ // Copy data to USB RAM
+ USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
+
+ // Add options
+ if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
+ flags |= CMDSTS_RF;
+ }
+
+ if (endpointState[endpoint].options & ISOCHRONOUS) {
+ flags |= CMDSTS_T;
+ }
+
+ // Add transfer
+ ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
+ endpointState[endpoint].buffer[bf]) \
+ | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ uint32_t bf;
+
+ // Validate parameters
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return EP_INVALID;
+ }
+
+ if (OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered // TODO: FIX THIS
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ } else {
+ // Single buffered
+ bf = 0;
+ }
+
+ // Check if endpoint still active
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
+ return EP_PENDING;
+ }
+
+ // Check if stalled
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
+ return EP_STALLED;
+ }
+
+ return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+
+ // FIX: should this clear active bit?
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
+ ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
+ ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
+ ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
+
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
+ ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
+
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ }
+ } else {
+ // Single buffered
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ }
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint) {
+ if (IN_EP(endpoint)) {
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
+ return true;
+ }
+ } else {
+ if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
+ return true;
+ }
+ }
+ } else {
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
+ return true;
+ }
+ } else {
+ if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
+ uint32_t tmpEpRamPtr;
+
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return false;
+ }
+
+ // Not applicable to the control endpoints
+ if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
+ return false;
+ }
+
+ // Allocate buffers in USB RAM
+ tmpEpRamPtr = epRamPtr;
+
+ // Must be 64 byte aligned
+ tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
+
+ if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
+ // Out of memory
+ return false;
+ }
+
+ // Allocate first buffer
+ endpointState[endpoint].buffer[0] = tmpEpRamPtr;
+ tmpEpRamPtr += maxPacket;
+
+ if (!(options & SINGLE_BUFFERED)) {
+ // Must be 64 byte aligned
+ tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
+
+ if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
+ // Out of memory
+ return false;
+ }
+
+ // Allocate second buffer
+ endpointState[endpoint].buffer[1] = tmpEpRamPtr;
+ tmpEpRamPtr += maxPacket;
+ }
+
+ // Commit to this USB RAM allocation
+ epRamPtr = tmpEpRamPtr;
+
+ // Remaining endpoint state values
+ endpointState[endpoint].maxPacket = maxPacket;
+ endpointState[endpoint].options = options;
+
+ // Enable double buffering if required
+ if (options & SINGLE_BUFFERED) {
+ LPC_USB->EPBUFCFG &= ~EP(endpoint);
+ } else {
+ // Double buffered
+ LPC_USB->EPBUFCFG |= EP(endpoint);
+ }
+
+ // Enable interrupt
+ LPC_USB->INTEN |= EP(endpoint);
+
+ // Enable endpoint
+ unstallEndpoint(endpoint);
+ return true;
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Clearing DSUS bit initiates a remote wakeup if the
+ // device is currently enabled and suspended - otherwise
+ // it has no effect.
+ LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
+}
+
+
+static void disableEndpoints(void) {
+ uint32_t logEp;
+
+ // Ref. Table 158 "When a bus reset is received, software
+ // must set the disable bit of all endpoints to 1".
+
+ for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
+ ep[logEp].out[0] = CMDSTS_D;
+ ep[logEp].out[1] = CMDSTS_D;
+ ep[logEp].in[0] = CMDSTS_D;
+ ep[logEp].in[1] = CMDSTS_D;
+ }
+
+ // Start of USB RAM for endpoints > 0
+ epRamPtr = usbRamPtr;
+}
+
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+void USBHAL::usbisr(void) {
+ // Start of frame
+ if (LPC_USB->INTSTAT & FRAME_INT) {
+ // Clear SOF interrupt
+ LPC_USB->INTSTAT = FRAME_INT;
+
+ // SOF event, read frame number
+ SOF(FRAME_NR(LPC_USB->INFO));
+ }
+
+ // Device state
+ if (LPC_USB->INTSTAT & DEV_INT) {
+ LPC_USB->INTSTAT = DEV_INT;
+
+ if (LPC_USB->DEVCMDSTAT & DSUS_C) {
+ // Suspend status changed
+ LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
+ if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
+ suspendStateChanged(1);
+ }
+ }
+
+ if (LPC_USB->DEVCMDSTAT & DRES_C) {
+ // Bus reset
+ LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
+
+ suspendStateChanged(0);
+
+ // Disable endpoints > 0
+ disableEndpoints();
+
+ // Bus reset event
+ busReset();
+ }
+ }
+
+ // Endpoint 0
+ if (LPC_USB->INTSTAT & EP(EP0OUT)) {
+ // Clear EP0OUT/SETUP interrupt
+ LPC_USB->INTSTAT = EP(EP0OUT);
+
+ // Check if SETUP
+ if (LPC_USB->DEVCMDSTAT & SETUP) {
+ // Clear Active and Stall bits for EP0
+ // Documentation does not make it clear if we must use the
+ // EPSKIP register to achieve this, Fig. 16 and NXP reference
+ // code suggests we can just clear the Active bits - check with
+ // NXP to be sure.
+ ep[0].in[0] = 0;
+ ep[0].out[0] = 0;
+
+ // Clear EP0IN interrupt
+ LPC_USB->INTSTAT = EP(EP0IN);
+
+ // Clear SETUP (and INTONNAK_CI/O) in device status register
+ LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
+
+ // EP0 SETUP event (SETUP data received)
+ EP0setupCallback();
+ } else {
+ // EP0OUT ACK event (OUT data received)
+ EP0out();
+ }
+ }
+
+ if (LPC_USB->INTSTAT & EP(EP0IN)) {
+ // Clear EP0IN interrupt
+ LPC_USB->INTSTAT = EP(EP0IN);
+
+ // EP0IN ACK event (IN data sent)
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 5*2; num++) {
+ if (LPC_USB->INTSTAT & EP(num)) {
+ LPC_USB->INTSTAT = EP(num);
+ epComplete |= EP(num);
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp
new file mode 100644
index 000000000..8bffe10ac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp
@@ -0,0 +1,623 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
+
+#include "USBHAL.h"
+
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Power Control for Peripherals register
+#define PCUSB (1UL<<31)
+
+// USB Clock Control register
+#define DEV_CLK_EN (1UL<<1)
+#define AHB_CLK_EN (1UL<<4)
+
+// USB Clock Status register
+#define DEV_CLK_ON (1UL<<1)
+#define AHB_CLK_ON (1UL<<4)
+
+// USB Device Interupt registers
+#define FRAME (1UL<<0)
+#define EP_FAST (1UL<<1)
+#define EP_SLOW (1UL<<2)
+#define DEV_STAT (1UL<<3)
+#define CCEMPTY (1UL<<4)
+#define CDFULL (1UL<<5)
+#define RxENDPKT (1UL<<6)
+#define TxENDPKT (1UL<<7)
+#define EP_RLZED (1UL<<8)
+#define ERR_INT (1UL<<9)
+
+// USB Control register
+#define RD_EN (1<<0)
+#define WR_EN (1<<1)
+#define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
+
+// USB Receive Packet Length register
+#define DV (1UL<<10)
+#define PKT_RDY (1UL<<11)
+#define PKT_LNGTH_MASK (0x3ff)
+
+// Serial Interface Engine (SIE)
+#define SIE_WRITE (0x01)
+#define SIE_READ (0x02)
+#define SIE_COMMAND (0x05)
+#define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
+
+// SIE Command codes
+#define SIE_CMD_SET_ADDRESS (0xD0)
+#define SIE_CMD_CONFIGURE_DEVICE (0xD8)
+#define SIE_CMD_SET_MODE (0xF3)
+#define SIE_CMD_READ_FRAME_NUMBER (0xF5)
+#define SIE_CMD_READ_TEST_REGISTER (0xFD)
+#define SIE_CMD_SET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_ERROR_CODE (0xFF)
+#define SIE_CMD_READ_ERROR_STATUS (0xFB)
+
+#define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
+#define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
+#define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
+
+#define SIE_CMD_CLEAR_BUFFER (0xF2)
+#define SIE_CMD_VALIDATE_BUFFER (0xFA)
+
+// SIE Device Status register
+#define SIE_DS_CON (1<<0)
+#define SIE_DS_CON_CH (1<<1)
+#define SIE_DS_SUS (1<<2)
+#define SIE_DS_SUS_CH (1<<3)
+#define SIE_DS_RST (1<<4)
+
+// SIE Device Set Address register
+#define SIE_DSA_DEV_EN (1<<7)
+
+// SIE Configue Device register
+#define SIE_CONF_DEVICE (1<<0)
+
+// Select Endpoint register
+#define SIE_SE_FE (1<<0)
+#define SIE_SE_ST (1<<1)
+#define SIE_SE_STP (1<<2)
+#define SIE_SE_PO (1<<3)
+#define SIE_SE_EPN (1<<4)
+#define SIE_SE_B_1_FULL (1<<5)
+#define SIE_SE_B_2_FULL (1<<6)
+
+// Set Endpoint Status command
+#define SIE_SES_ST (1<<0)
+#define SIE_SES_DA (1<<5)
+#define SIE_SES_RF_MO (1<<6)
+#define SIE_SES_CND_ST (1<<7)
+
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete;
+static uint32_t endpointStallState;
+
+static void SIECommand(uint32_t command) {
+ // The command phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CCEMPTY;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
+ while (!(LPC_USB->USBDevIntSt & CCEMPTY));
+}
+
+static void SIEWriteData(uint8_t data) {
+ // The data write phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CCEMPTY;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_WRITE, data);
+ while (!(LPC_USB->USBDevIntSt & CCEMPTY));
+}
+
+static uint8_t SIEReadData(uint32_t command) {
+ // The data read phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CDFULL;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_READ, command);
+ while (!(LPC_USB->USBDevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->USBCmdData;
+}
+
+static void SIEsetDeviceStatus(uint8_t status) {
+ // Write SIE device status register
+ SIECommand(SIE_CMD_SET_DEVICE_STATUS);
+ SIEWriteData(status);
+}
+
+static uint8_t SIEgetDeviceStatus(void) {
+ // Read SIE device status register
+ SIECommand(SIE_CMD_GET_DEVICE_STATUS);
+ return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
+}
+
+void SIEsetAddress(uint8_t address) {
+ // Write SIE device address register
+ SIECommand(SIE_CMD_SET_ADDRESS);
+ SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
+}
+
+static uint8_t SIEselectEndpoint(uint8_t endpoint) {
+ // SIE select endpoint command
+ SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
+ return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
+}
+
+static uint8_t SIEclearBuffer(void) {
+ // SIE clear buffer command
+ SIECommand(SIE_CMD_CLEAR_BUFFER);
+ return SIEReadData(SIE_CMD_CLEAR_BUFFER);
+}
+
+static void SIEvalidateBuffer(void) {
+ // SIE validate buffer command
+ SIECommand(SIE_CMD_VALIDATE_BUFFER);
+}
+
+static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
+ // SIE set endpoint status command
+ SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
+ SIEWriteData(status);
+}
+
+static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
+static uint16_t SIEgetFrameNumber(void) {
+ // Read current frame number
+ uint16_t lowByte;
+ uint16_t highByte;
+
+ SIECommand(SIE_CMD_READ_FRAME_NUMBER);
+ lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+ highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+
+ return (highByte << 8) | lowByte;
+}
+
+static void SIEconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(SIE_CONF_DEVICE);
+}
+
+static void SIEunconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(0);
+}
+
+static void SIEconnect(void) {
+ // Connect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status | SIE_DS_CON);
+}
+
+
+static void SIEdisconnect(void) {
+ // Disconnect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_CON);
+}
+
+
+static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
+ // Implemented using using EP_INT_CLR.
+ LPC_USB->USBEpIntClr = EP(endpoint);
+ while (!(LPC_USB->USBDevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->USBCmdData;
+}
+
+
+static void enableEndpointEvent(uint8_t endpoint) {
+ // Enable an endpoint interrupt
+ LPC_USB->USBEpIntEn |= EP(endpoint);
+}
+
+static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
+static void disableEndpointEvent(uint8_t endpoint) {
+ // Disable an endpoint interrupt
+ LPC_USB->USBEpIntEn &= ~EP(endpoint);
+}
+
+static volatile uint32_t __attribute__((used)) dummyRead;
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ // Read from an OUT endpoint
+ uint32_t size;
+ uint32_t i;
+ uint32_t data = 0;
+ uint8_t offset;
+
+ LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | RD_EN;
+ while (!(LPC_USB->USBRxPLen & PKT_RDY));
+
+ size = LPC_USB->USBRxPLen & PKT_LNGTH_MASK;
+
+ offset = 0;
+
+ if (size > 0) {
+ for (i=0; i<size; i++) {
+ if (offset==0) {
+ // Fetch up to four bytes of data as a word
+ data = LPC_USB->USBRxData;
+ }
+
+ // extract a byte
+ *buffer = (data>>offset) & 0xff;
+ buffer++;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ }
+ } else {
+ dummyRead = LPC_USB->USBRxData;
+ }
+
+ LPC_USB->USBCtrl = 0;
+
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ SIEselectEndpoint(endpoint);
+ SIEclearBuffer();
+ }
+
+ return size;
+}
+
+static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
+ // Write to an IN endpoint
+ uint32_t temp, data;
+ uint8_t offset;
+
+ LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | WR_EN;
+
+ LPC_USB->USBTxPLen = size;
+ offset = 0;
+ data = 0;
+
+ if (size>0) {
+ do {
+ // Fetch next data byte into a word-sized temporary variable
+ temp = *buffer++;
+
+ // Add to current data word
+ temp = temp << offset;
+ data = data | temp;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ size--;
+
+ if ((offset==0) || (size==0)) {
+ // Write the word to the endpoint
+ LPC_USB->USBTxData = data;
+ data = 0;
+ }
+ } while (size>0);
+ } else {
+ LPC_USB->USBTxData = 0;
+ }
+
+ // Clear WR_EN to cover zero length packet case
+ LPC_USB->USBCtrl=0;
+
+ SIEselectEndpoint(endpoint);
+ SIEvalidateBuffer();
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ // Enable power to USB device controller
+ LPC_SC->PCONP |= PCUSB;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ // Configure pins P0.29 and P0.30 to be USB D+ and USB D-
+ LPC_PINCON->PINSEL1 &= 0xc3ffffff;
+ LPC_PINCON->PINSEL1 |= 0x14000000;
+
+ // Disconnect USB device
+ SIEdisconnect();
+
+ // Configure pin P2.9 to be Connect
+ LPC_PINCON->PINSEL4 &= 0xfffcffff;
+ LPC_PINCON->PINSEL4 |= 0x00040000;
+
+ // Connect must be low for at least 2.5uS
+ wait(0.3);
+
+ // Set the maximum packet size for the control endpoints
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->USBDevIntEn = EP_SLOW | DEV_STAT | FRAME;
+ enableEndpointEvent(EP0IN);
+ enableEndpointEvent(EP0OUT);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected
+ SIEdisconnect();
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQn);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQn);
+ // Connect USB device
+ SIEconnect();
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQn);
+ // Disconnect USB device
+ SIEdisconnect();
+}
+
+void USBHAL::configureDevice(void) {
+ SIEconfigureDevice();
+}
+
+void USBHAL::unconfigureDevice(void) {
+ SIEunconfigureDevice();
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ SIEsetAddress(address);
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0read(void) {
+ // Not required
+}
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ return endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWritecore(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ // This will stall both control endpoints
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ }
+
+ *bytesRead = endpointReadcore(endpoint, buffer);
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ if (getEndpointStallState(endpoint)) {
+ return EP_STALLED;
+ }
+
+ epComplete &= ~EP(endpoint);
+
+ endpointWritecore(endpoint, data, size);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ // Realise an endpoint
+ LPC_USB->USBDevIntClr = EP_RLZED;
+ LPC_USB->USBReEp |= EP(endpoint);
+ LPC_USB->USBEpInd = endpoint;
+ LPC_USB->USBMaxPSize = maxPacket;
+
+ while (!(LPC_USB->USBDevIntSt & EP_RLZED));
+ LPC_USB->USBDevIntClr = EP_RLZED;
+
+ // Clear stall state
+ endpointStallState &= ~EP(endpoint);
+
+ enableEndpointEvent(endpoint);
+ return true;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ // Stall an endpoint
+ if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
+ // Conditionally stall both control endpoints
+ SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
+ } else {
+ SIEsetEndpointStatus(endpoint, SIE_SES_ST);
+
+ // Update stall state
+ endpointStallState |= EP(endpoint);
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ // Unstall an endpoint. The endpoint will also be reinitialised
+ SIEsetEndpointStatus(endpoint, 0);
+
+ // Update stall state
+ endpointStallState &= ~EP(endpoint);
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ // Returns true if endpoint stalled
+ return endpointStallState & EP(endpoint);
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Remote wakeup
+ uint8_t status;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_SUS);
+}
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t devStat;
+
+ if (LPC_USB->USBDevIntSt & FRAME) {
+ // Start of frame event
+ SOF(SIEgetFrameNumber());
+ // Clear interrupt status flag
+ LPC_USB->USBDevIntClr = FRAME;
+ }
+
+ if (LPC_USB->USBDevIntSt & DEV_STAT) {
+ // Device Status interrupt
+ // Must clear the interrupt status flag before reading the device status from the SIE
+ LPC_USB->USBDevIntClr = DEV_STAT;
+
+ // Read device status from SIE
+ devStat = SIEgetDeviceStatus();
+ //printf("devStat: %d\r\n", devStat);
+
+ if (devStat & SIE_DS_SUS_CH) {
+ // Suspend status changed
+ if((devStat & SIE_DS_SUS) != 0) {
+ suspendStateChanged(0);
+ }
+ }
+
+ if (devStat & SIE_DS_RST) {
+ // Bus reset
+ if((devStat & SIE_DS_SUS) == 0) {
+ suspendStateChanged(1);
+ }
+ busReset();
+ }
+ }
+
+ if (LPC_USB->USBDevIntSt & EP_SLOW) {
+ // (Slow) Endpoint Interrupt
+
+ // Process each endpoint interrupt
+ if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
+ if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
+ // this is a setup packet
+ EP0setupCallback();
+ } else {
+ EP0out();
+ }
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ }
+
+ if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
+ selectEndpointClearInterrupt(EP0IN);
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 16*2; num++) {
+ if (LPC_USB->USBEpIntSt & EP(num)) {
+ selectEndpointClearInterrupt(num);
+ epComplete |= EP(num);
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp
new file mode 100644
index 000000000..a5d7b4440
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp
@@ -0,0 +1,628 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
+
+#include "USBHAL.h"
+
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Power Control for Peripherals register
+#define PCUSB (1UL<<31)
+
+// USB Clock Control register
+#define DEV_CLK_EN (1UL<<1)
+#define PORT_CLK_EN (1UL<<3)
+#define AHB_CLK_EN (1UL<<4)
+
+// USB Clock Status register
+#define DEV_CLK_ON (1UL<<1)
+#define AHB_CLK_ON (1UL<<4)
+
+// USB Device Interupt registers
+#define FRAME (1UL<<0)
+#define EP_FAST (1UL<<1)
+#define EP_SLOW (1UL<<2)
+#define DEV_STAT (1UL<<3)
+#define CCEMPTY (1UL<<4)
+#define CDFULL (1UL<<5)
+#define RxENDPKT (1UL<<6)
+#define TxENDPKT (1UL<<7)
+#define EP_RLZED (1UL<<8)
+#define ERR_INT (1UL<<9)
+
+// USB Control register
+#define RD_EN (1<<0)
+#define WR_EN (1<<1)
+#define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
+
+// USB Receive Packet Length register
+#define DV (1UL<<10)
+#define PKT_RDY (1UL<<11)
+#define PKT_LNGTH_MASK (0x3ff)
+
+// Serial Interface Engine (SIE)
+#define SIE_WRITE (0x01)
+#define SIE_READ (0x02)
+#define SIE_COMMAND (0x05)
+#define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
+
+// SIE Command codes
+#define SIE_CMD_SET_ADDRESS (0xD0)
+#define SIE_CMD_CONFIGURE_DEVICE (0xD8)
+#define SIE_CMD_SET_MODE (0xF3)
+#define SIE_CMD_READ_FRAME_NUMBER (0xF5)
+#define SIE_CMD_READ_TEST_REGISTER (0xFD)
+#define SIE_CMD_SET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_ERROR_CODE (0xFF)
+#define SIE_CMD_READ_ERROR_STATUS (0xFB)
+
+#define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
+#define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
+#define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
+
+#define SIE_CMD_CLEAR_BUFFER (0xF2)
+#define SIE_CMD_VALIDATE_BUFFER (0xFA)
+
+// SIE Device Status register
+#define SIE_DS_CON (1<<0)
+#define SIE_DS_CON_CH (1<<1)
+#define SIE_DS_SUS (1<<2)
+#define SIE_DS_SUS_CH (1<<3)
+#define SIE_DS_RST (1<<4)
+
+// SIE Device Set Address register
+#define SIE_DSA_DEV_EN (1<<7)
+
+// SIE Configue Device register
+#define SIE_CONF_DEVICE (1<<0)
+
+// Select Endpoint register
+#define SIE_SE_FE (1<<0)
+#define SIE_SE_ST (1<<1)
+#define SIE_SE_STP (1<<2)
+#define SIE_SE_PO (1<<3)
+#define SIE_SE_EPN (1<<4)
+#define SIE_SE_B_1_FULL (1<<5)
+#define SIE_SE_B_2_FULL (1<<6)
+
+// Set Endpoint Status command
+#define SIE_SES_ST (1<<0)
+#define SIE_SES_DA (1<<5)
+#define SIE_SES_RF_MO (1<<6)
+#define SIE_SES_CND_ST (1<<7)
+
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete;
+static uint32_t endpointStallState;
+
+static void SIECommand(uint32_t command) {
+ // The command phase of a SIE transaction
+ LPC_USB->DevIntClr = CCEMPTY;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
+ while (!(LPC_USB->DevIntSt & CCEMPTY));
+}
+
+static void SIEWriteData(uint8_t data) {
+ // The data write phase of a SIE transaction
+ LPC_USB->DevIntClr = CCEMPTY;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_WRITE, data);
+ while (!(LPC_USB->DevIntSt & CCEMPTY));
+}
+
+static uint8_t SIEReadData(uint32_t command) {
+ // The data read phase of a SIE transaction
+ LPC_USB->DevIntClr = CDFULL;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_READ, command);
+ while (!(LPC_USB->DevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->CmdData;
+}
+
+static void SIEsetDeviceStatus(uint8_t status) {
+ // Write SIE device status register
+ SIECommand(SIE_CMD_SET_DEVICE_STATUS);
+ SIEWriteData(status);
+}
+
+static uint8_t SIEgetDeviceStatus(void) {
+ // Read SIE device status register
+ SIECommand(SIE_CMD_GET_DEVICE_STATUS);
+ return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
+}
+
+void SIEsetAddress(uint8_t address) {
+ // Write SIE device address register
+ SIECommand(SIE_CMD_SET_ADDRESS);
+ SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
+}
+
+static uint8_t SIEselectEndpoint(uint8_t endpoint) {
+ // SIE select endpoint command
+ SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
+ return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
+}
+
+static uint8_t SIEclearBuffer(void) {
+ // SIE clear buffer command
+ SIECommand(SIE_CMD_CLEAR_BUFFER);
+ return SIEReadData(SIE_CMD_CLEAR_BUFFER);
+}
+
+static void SIEvalidateBuffer(void) {
+ // SIE validate buffer command
+ SIECommand(SIE_CMD_VALIDATE_BUFFER);
+}
+
+static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
+ // SIE set endpoint status command
+ SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
+ SIEWriteData(status);
+}
+
+static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
+static uint16_t SIEgetFrameNumber(void) {
+ // Read current frame number
+ uint16_t lowByte;
+ uint16_t highByte;
+
+ SIECommand(SIE_CMD_READ_FRAME_NUMBER);
+ lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+ highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+
+ return (highByte << 8) | lowByte;
+}
+
+static void SIEconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(SIE_CONF_DEVICE);
+}
+
+static void SIEunconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(0);
+}
+
+static void SIEconnect(void) {
+ // Connect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status | SIE_DS_CON);
+}
+
+
+static void SIEdisconnect(void) {
+ // Disconnect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_CON);
+}
+
+
+static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
+ // Implemented using using EP_INT_CLR.
+ LPC_USB->EpIntClr = EP(endpoint);
+ while (!(LPC_USB->DevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->CmdData;
+}
+
+
+static void enableEndpointEvent(uint8_t endpoint) {
+ // Enable an endpoint interrupt
+ LPC_USB->EpIntEn |= EP(endpoint);
+}
+
+static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
+static void disableEndpointEvent(uint8_t endpoint) {
+ // Disable an endpoint interrupt
+ LPC_USB->EpIntEn &= ~EP(endpoint);
+}
+
+static volatile uint32_t __attribute__((used)) dummyRead;
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ // Read from an OUT endpoint
+ uint32_t size;
+ uint32_t i;
+ uint32_t data = 0;
+ uint8_t offset;
+
+ LPC_USB->Ctrl = LOG_ENDPOINT(endpoint) | RD_EN;
+ while (!(LPC_USB->RxPLen & PKT_RDY));
+
+ size = LPC_USB->RxPLen & PKT_LNGTH_MASK;
+
+ offset = 0;
+
+ if (size > 0) {
+ for (i=0; i<size; i++) {
+ if (offset==0) {
+ // Fetch up to four bytes of data as a word
+ data = LPC_USB->RxData;
+ }
+
+ // extract a byte
+ *buffer = (data>>offset) & 0xff;
+ buffer++;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ }
+ } else {
+ dummyRead = LPC_USB->RxData;
+ }
+
+ LPC_USB->Ctrl = 0;
+
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ SIEselectEndpoint(endpoint);
+ SIEclearBuffer();
+ }
+
+ return size;
+}
+
+static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
+ // Write to an IN endpoint
+ uint32_t temp, data;
+ uint8_t offset;
+
+ LPC_USB->Ctrl = LOG_ENDPOINT(endpoint) | WR_EN;
+
+ LPC_USB->TxPLen = size;
+ offset = 0;
+ data = 0;
+
+ if (size>0) {
+ do {
+ // Fetch next data byte into a word-sized temporary variable
+ temp = *buffer++;
+
+ // Add to current data word
+ temp = temp << offset;
+ data = data | temp;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ size--;
+
+ if ((offset==0) || (size==0)) {
+ // Write the word to the endpoint
+ LPC_USB->TxData = data;
+ data = 0;
+ }
+ } while (size>0);
+ } else {
+ LPC_USB->TxData = 0;
+ }
+
+ // Clear WR_EN to cover zero length packet case
+ LPC_USB->Ctrl=0;
+
+ SIEselectEndpoint(endpoint);
+ SIEvalidateBuffer();
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ // Enable power to USB device controller
+ LPC_SC->PCONP |= PCUSB;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN | PORT_CLK_EN;
+ while ((LPC_USB->USBClkSt & (DEV_CLK_EN | AHB_CLK_EN | PORT_CLK_EN)) != (DEV_CLK_ON | AHB_CLK_ON | PORT_CLK_EN));
+
+ // Select port USB2
+ LPC_USB->StCtrl |= 3;
+
+
+ // Configure pin P0.31 to be USB2
+ LPC_IOCON->P0_31 &= ~0x07;
+ LPC_IOCON->P0_31 |= 0x01;
+
+ // Disconnect USB device
+ SIEdisconnect();
+
+ // Configure pin P0.14 to be Connect
+ LPC_IOCON->P0_14 &= ~0x07;
+ LPC_IOCON->P0_14 |= 0x03;
+
+ // Connect must be low for at least 2.5uS
+ wait(0.3);
+
+ // Set the maximum packet size for the control endpoints
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->DevIntEn = EP_SLOW | DEV_STAT | FRAME;
+ enableEndpointEvent(EP0IN);
+ enableEndpointEvent(EP0OUT);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected
+ SIEdisconnect();
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQn);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQn);
+ // Connect USB device
+ SIEconnect();
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQn);
+ // Disconnect USB device
+ SIEdisconnect();
+}
+
+void USBHAL::configureDevice(void) {
+ SIEconfigureDevice();
+}
+
+void USBHAL::unconfigureDevice(void) {
+ SIEunconfigureDevice();
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ SIEsetAddress(address);
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0read(void) {
+ // Not required
+}
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ return endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWritecore(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ // This will stall both control endpoints
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ }
+
+ *bytesRead = endpointReadcore(endpoint, buffer);
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ if (getEndpointStallState(endpoint)) {
+ return EP_STALLED;
+ }
+
+ epComplete &= ~EP(endpoint);
+
+ endpointWritecore(endpoint, data, size);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ // Realise an endpoint
+ LPC_USB->DevIntClr = EP_RLZED;
+ LPC_USB->ReEp |= EP(endpoint);
+ LPC_USB->EpInd = endpoint;
+ LPC_USB->MaxPSize = maxPacket;
+
+ while (!(LPC_USB->DevIntSt & EP_RLZED));
+ LPC_USB->DevIntClr = EP_RLZED;
+
+ // Clear stall state
+ endpointStallState &= ~EP(endpoint);
+
+ enableEndpointEvent(endpoint);
+ return true;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ // Stall an endpoint
+ if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
+ // Conditionally stall both control endpoints
+ SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
+ } else {
+ SIEsetEndpointStatus(endpoint, SIE_SES_ST);
+
+ // Update stall state
+ endpointStallState |= EP(endpoint);
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ // Unstall an endpoint. The endpoint will also be reinitialised
+ SIEsetEndpointStatus(endpoint, 0);
+
+ // Update stall state
+ endpointStallState &= ~EP(endpoint);
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ // Returns true if endpoint stalled
+ return endpointStallState & EP(endpoint);
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Remote wakeup
+ uint8_t status;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_SUS);
+}
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t devStat;
+
+ if (LPC_USB->DevIntSt & FRAME) {
+ // Start of frame event
+ SOF(SIEgetFrameNumber());
+ // Clear interrupt status flag
+ LPC_USB->DevIntClr = FRAME;
+ }
+
+ if (LPC_USB->DevIntSt & DEV_STAT) {
+ // Device Status interrupt
+ // Must clear the interrupt status flag before reading the device status from the SIE
+ LPC_USB->DevIntClr = DEV_STAT;
+
+ // Read device status from SIE
+ devStat = SIEgetDeviceStatus();
+ //printf("devStat: %d\r\n", devStat);
+
+ if (devStat & SIE_DS_SUS_CH) {
+ // Suspend status changed
+ if((devStat & SIE_DS_SUS) != 0) {
+ suspendStateChanged(0);
+ }
+ }
+
+ if (devStat & SIE_DS_RST) {
+ // Bus reset
+ if((devStat & SIE_DS_SUS) == 0) {
+ suspendStateChanged(1);
+ }
+ busReset();
+ }
+ }
+
+ if (LPC_USB->DevIntSt & EP_SLOW) {
+ // (Slow) Endpoint Interrupt
+
+ // Process each endpoint interrupt
+ if (LPC_USB->EpIntSt & EP(EP0OUT)) {
+ if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
+ // this is a setup packet
+ EP0setupCallback();
+ } else {
+ EP0out();
+ }
+ LPC_USB->DevIntClr = EP_SLOW;
+ }
+
+ if (LPC_USB->EpIntSt & EP(EP0IN)) {
+ selectEndpointClearInterrupt(EP0IN);
+ LPC_USB->DevIntClr = EP_SLOW;
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 16*2; num++) {
+ if (LPC_USB->EpIntSt & EP(num)) {
+ selectEndpointClearInterrupt(num);
+ epComplete |= EP(num);
+ LPC_USB->DevIntClr = EP_SLOW;
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp
new file mode 100644
index 000000000..13e193cd2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp
@@ -0,0 +1,473 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#if defined(TARGET_Maxim)
+
+#include "USBHAL.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+
+#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+USBHAL *USBHAL::instance;
+
+typedef struct {
+ volatile uint32_t buf0_desc;
+ volatile uint32_t buf0_address;
+ volatile uint32_t buf1_desc;
+ volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+ ep_buffer_t out_buffer;
+ ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+ ep0_buffer_t ep0;
+ ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+// Static storage for endpoint buffer descriptor table. Must be 512 byte alligned for DMA.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 512
+#else
+__attribute__ ((aligned (512)))
+#endif
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+// static storage for temporary data buffers. Must be 32 byte alligned.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 4
+#else
+__attribute__ ((aligned (4)))
+#endif
+static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET];
+
+// contorl packet state
+static enum {
+ CTRL_NONE = 0,
+ CTRL_SETUP,
+ CTRL_OUT,
+ CTRL_IN,
+} control_state;
+
+USBHAL::USBHAL(void)
+{
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // The PLL must be enabled for USB
+ MBED_ASSERT(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE);
+
+ // Enable the USB clock
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N;
+
+ // reset the device
+ MXC_USB->cn = 0;
+ MXC_USB->cn = 1;
+ MXC_USB->dev_inten = 0;
+ MXC_USB->dev_cn = 0;
+ MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+
+ // fill in callback arrays
+ epCallback[EP0OUT] = NULL;
+ epCallback[EP0IN] = NULL;
+ epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback;
+ epCallback[EP1IN ] = &USBHAL::EP1_IN_callback;
+ epCallback[EP2OUT] = &USBHAL::EP2_OUT_callback;
+ epCallback[EP2IN ] = &USBHAL::EP2_IN_callback;
+ epCallback[EP3OUT] = &USBHAL::EP3_OUT_callback;
+ epCallback[EP3IN ] = &USBHAL::EP3_IN_callback;
+ epCallback[EP4OUT] = &USBHAL::EP4_OUT_callback;
+ epCallback[EP4IN ] = &USBHAL::EP4_IN_callback;
+ epCallback[EP5OUT] = &USBHAL::EP5_OUT_callback;
+ epCallback[EP5IN ] = &USBHAL::EP5_IN_callback;
+ epCallback[EP6OUT] = &USBHAL::EP6_OUT_callback;
+ epCallback[EP6IN ] = &USBHAL::EP6_IN_callback;
+ epCallback[EP7OUT] = &USBHAL::EP7_OUT_callback;
+ epCallback[EP7IN ] = &USBHAL::EP7_IN_callback;
+
+ // clear driver state
+ control_state = CTRL_NONE;
+
+ // set the descriptor location
+ MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+ // attach IRQ handler and enable interrupts
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+ NVIC_EnableIRQ(USB_IRQn);
+}
+
+USBHAL::~USBHAL(void)
+{
+ MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+ MXC_USB->cn = 0;
+}
+
+void USBHAL::connect(void)
+{
+ // enable interrupts
+ MXC_USB->dev_inten |= CONNECT_INTS;
+
+ // allow interrupts on ep0
+ MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+
+ // pullup enable
+ MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+}
+
+void USBHAL::disconnect(void)
+{
+ // disable interrupts
+ MXC_USB->dev_inten &= ~CONNECT_INTS;
+
+ // disable pullup
+ MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+}
+
+void USBHAL::configureDevice(void)
+{
+ // do nothing
+}
+
+void USBHAL::unconfigureDevice(void)
+{
+ // reset endpoints
+ for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+ // Disable endpoint and clear the data toggle
+ MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+ MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+ }
+}
+
+void USBHAL::setAddress(uint8_t address)
+{
+ // do nothing
+}
+
+void USBHAL::remoteWakeup(void)
+{
+ // do nothing
+}
+
+static ep_buffer_t *get_desc(uint8_t endpoint)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+ ep_buffer_t *desc;
+
+ if (epnum == 0) {
+ if (IN_EP(endpoint)) {
+ desc = &ep_buffer_descriptor.ep0.in_buffer;
+ } else {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ }
+ } else {
+ desc = &ep_buffer_descriptor.ep[epnum - 1];
+ }
+
+ return desc;
+}
+
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+ memcpy(buffer, (void*)&MXC_USB->setup0, 8); // setup packet is fixed at 8 bytes
+}
+
+void USBHAL::EP0read(void)
+{
+ if (control_state == CTRL_IN) {
+ // This is the status stage. ACK.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+ control_state = CTRL_NONE;
+ return;
+ }
+
+ control_state = CTRL_OUT;
+
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void)
+{
+ // do nothing
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+ uint32_t size;
+
+ if (MXC_USB->out_owner & 1) {
+ return 0;
+ }
+
+ // get the packet length and contents
+ ep_buffer_t *desc = get_desc(EP0OUT);
+ size = desc->buf0_desc;
+ memcpy(buffer, aligned_buffer[0], size);
+
+ return size;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+ if ((size == 0) && (control_state != CTRL_IN)) {
+ // This is a status stage ACK. Handle in hardware.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+ control_state = CTRL_NONE;
+ return;
+ }
+
+ control_state = CTRL_IN;
+
+ endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0stall(void)
+{
+ stallEndpoint(0);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (maximumSize > MXC_USB_MAX_PACKET) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << epnum);
+ if (MXC_USB->out_owner & mask) {
+ return EP_INVALID;
+ }
+
+ ep_buffer_t *desc = get_desc(endpoint);
+ desc->buf0_desc = maximumSize;
+ desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+ MXC_USB->out_owner = mask;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead)
+{
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << EP_NUM(endpoint));
+ if (MXC_USB->out_owner & mask) {
+ return EP_PENDING;
+ }
+
+ // get the packet length and contents
+ ep_buffer_t *desc = get_desc(endpoint);
+ *bytesRead = desc->buf0_desc;
+ memcpy(data, aligned_buffer[EP_NUM(endpoint)], *bytesRead);
+
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (size > MXC_USB_MAX_PACKET) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << epnum);
+ if (MXC_USB->in_owner & mask) {
+ return EP_INVALID;
+ }
+
+ memcpy(aligned_buffer[epnum], data, size);
+
+ ep_buffer_t *desc = get_desc(endpoint);
+ desc->buf0_desc = size;
+ desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+ // start the DMA
+ MXC_USB->in_owner = mask;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+ uint32_t mask = (1 << EP_NUM(endpoint));
+ if (MXC_USB->in_owner & mask) {
+ return EP_PENDING;
+ }
+
+ return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if (epnum == 0) {
+ MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL;
+ }
+
+ MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+ MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+ uint32_t ep_ctrl;
+
+ if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) {
+ return false;
+ }
+
+ if (IN_EP(endpoint)) {
+ ep_ctrl = (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS);
+ } else {
+ ep_ctrl = (MXC_S_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS);
+ }
+
+ ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN);
+
+ MXC_USB->ep[epnum] = ep_ctrl;
+
+ return true;
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint)
+{
+ return !!(MXC_USB->ep[endpoint] & MXC_F_USB_EP_STALL);
+}
+
+void USBHAL::_usbisr(void)
+{
+ instance->usbisr();
+}
+
+void USBHAL::usbisr(void)
+{
+ // get and clear irqs
+ uint32_t irq_flags = MXC_USB->dev_intfl;
+ MXC_USB->dev_intfl = irq_flags;
+
+ // process only enabled interrupts
+ irq_flags &= MXC_USB->dev_inten;
+
+ // suspend
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+ suspendStateChanged(1);
+ }
+
+ // bus reset
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+
+ // reset endpoints
+ for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+ // Disable endpoint and clear the data toggle
+ MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+ MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+ }
+
+ // clear driver state
+ control_state = CTRL_NONE;
+
+ busReset();
+
+ // no need to process events after reset
+ return;
+ }
+
+ // Setup packet
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+ control_state = CTRL_SETUP;
+ EP0setupCallback();
+ }
+
+ // IN packets
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+ // get and clear IN irqs
+ uint32_t in_irqs = MXC_USB->in_int;
+ MXC_USB->in_int = in_irqs;
+
+ if (in_irqs & 1) {
+ EP0in();
+ }
+
+ for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+ uint32_t irq_mask = (1 << epnum);
+ if (in_irqs & irq_mask) {
+ uint8_t endpoint = (epnum << 1) | DIR_IN;
+ (instance->*(epCallback[endpoint]))();
+ }
+ }
+ }
+
+ // OUT packets
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+ // get and clear OUT irqs
+ uint32_t out_irqs = MXC_USB->out_int;
+ MXC_USB->out_int = out_irqs;
+
+ if (out_irqs & 1) {
+ EP0out();
+ }
+
+ for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+ uint32_t irq_mask = (1 << epnum);
+ if (out_irqs & irq_mask) {
+ uint8_t endpoint = (epnum << 1) | DIR_OUT;
+ (instance->*(epCallback[endpoint]))();
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp
new file mode 100644
index 000000000..5eee82a64
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp
@@ -0,0 +1,1497 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use,
+* copy, modify, merge, publish, distribute, sublicense, and/or
+* sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following
+* conditions:
+*
+* The above copyright notice and this permission notice shall be
+* included in all copies or substantial portions of the
+* Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
+* KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+* PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_RZ_A1H)
+
+/*
+ This class can use the pipe1, pipe3 and pipe6 only. You should
+ re-program this class if you wanted to use other pipe.
+ */
+
+/*************************************************************************/
+extern "C"
+{
+#include "r_typedefs.h"
+#include "iodefine.h"
+}
+#include "USBHAL.h"
+#include "devdrv_usb_function_api.h"
+#include "usb_iobitmask.h"
+#include "rza_io_regrw.h"
+#include "USBDevice_Types.h"
+#include "usb_function_setting.h"
+
+
+/*************************************************************************/
+/* constants */
+const struct PIPECFGREC {
+ uint16_t endpoint;
+ uint16_t pipesel;
+ uint16_t pipecfg;
+ uint16_t pipebuf;
+ uint16_t pipemaxp;
+ uint16_t pipeperi;
+} def_pipecfg[] = {
+ /*EP0OUT and EP0IN are configured by USB IP*/
+ {
+ EP1OUT, /*EP1: Host -> Func, INT*/
+ 6 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_INTERRUPT |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP1,
+ ( ( ( 64) / 64 - 1 ) << 10 ) | 0x04u,
+ MAX_PACKET_SIZE_EP1,
+ DEVDRV_USBF_OFF |
+ ( 3 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP1IN, /*EP1: Host <- Func, INT*/
+ 7 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_INTERRUPT |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP1,
+ ( ( ( 64) / 64 - 1 ) << 10 ) | 0x05u,
+ MAX_PACKET_SIZE_EP1,
+ DEVDRV_USBF_OFF |
+ ( 3 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP2OUT, /*EP2: Host -> Func, BULK*/
+ 3 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_BULK |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKON |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP2,
+ ( ( (2048) / 64 - 1 ) << 10 ) | 0x30u,
+ MAX_PACKET_SIZE_EP2,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP2IN, /*EP2: Host <- Func, BULK*/
+ 4 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_BULK |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP2,
+ ( ( (2048) / 64 - 1 ) << 10 ) | 0x50u,
+ MAX_PACKET_SIZE_EP2,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP3OUT, /*EP3: Host -> Func, ISO*/
+ 1 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_ISO |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKON |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP3,
+ ( ( ( 512) / 64 - 1 ) << 10 ) | 0x10u,
+ MAX_PACKET_SIZE_EP3,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP3IN, /*EP3: Host <- Func, ISO*/
+ 2 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_ISO |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP3,
+ ( ( ( 512) / 64 - 1 ) << 10 ) | 0x20u,
+ MAX_PACKET_SIZE_EP3,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ { /*terminator*/
+ 0, 0, 0, 0, 0,
+ },
+};
+
+
+/*************************************************************************/
+/* workareas */
+USBHAL * USBHAL::instance;
+
+static IRQn_Type int_id; /* interrupt ID */
+static uint16_t int_level; /* initerrupt level */
+static uint16_t clock_mode; /* input clock selector */
+static uint16_t mode; /* USB speed (HIGH/FULL) */
+
+//static DigitalOut *usbx_en;
+
+static uint16_t EP0_read_status;
+static uint16_t EPx_read_status;
+
+static uint16_t setup_buffer[MAX_PACKET_SIZE_EP0 / 2];
+
+/* 0: not used / other: a pipe number to use recv_buffer*/
+static uint8_t recv_buffer[MAX_PACKET_SIZE_EPBULK];
+volatile static uint16_t recv_error;
+
+
+/*************************************************************************/
+/* prototypes for C */
+extern "C" {
+ void usbx_function_BRDYInterruptPIPE0 (uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_BRDYInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+
+ void usbx_function_NRDYInterruptPIPE0(uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_NRDYInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+
+ void usbx_function_BEMPInterruptPIPE0(uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_BEMPInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+}
+
+
+/*************************************************************************/
+/* macros */
+
+/******************************************************************************
+ * Function Name: usbx_function_BRDYInterruptPIPE0
+ * Description : Executes BRDY interrupt for pipe0.
+ * Arguments : uint16_t status ; BRDYSTS Register Value
+ * : uint16_t intenb ; BRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BRDYInterruptPIPE0 (
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+ uint16_t read_status;
+
+ USB20X.BRDYSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+ RZA_IO_RegWrite_16(
+ &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0,
+ USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+
+ g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] =
+ g_usbx_function_data_count[USB_FUNCTION_PIPE0];
+
+ read_status = usbx_function_read_buffer_c(USB_FUNCTION_PIPE0);
+
+ g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] -=
+ g_usbx_function_data_count[USB_FUNCTION_PIPE0];
+
+ switch (read_status) {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ case USB_FUNCTION_READEND: /* End of data read */
+ /* PID = BUF */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* PID = BUF */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case USB_FUNCTION_READOVER: /* FIFO access error */
+ /* Buffer Clear */
+ USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR;
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* Req Error */
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ default:
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* Req Error */
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+ }
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_BRDYInterrupt
+ * Description : Executes BRDY interrupt uxclude pipe0.
+ * Arguments : uint16_t status ; BRDYSTS Register Value
+ * : uint16_t intenb ; BRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BRDYInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_brdy_int
+ * Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+ * : According to the pipe that interrupt is generated in,
+ * : reads/writes buffer allocated in the pipe.
+ * : This function is executed in the BRDY
+ * : interrupt handler. This function
+ * : clears BRDY interrupt status and BEMP
+ * : interrupt status.
+ * Arguments : uint16_t Status ; BRDYSTS Register Value
+ * : uint16_t Int_enbl ; BRDYENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+ uint16_t ep;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ pipebit = g_usbx_function_bit_set[pipe];
+
+ if ((status & pipebit) && (intenb & pipebit)) {
+ USB20X.BRDYSTS = (uint16_t)~pipebit;
+ USB20X.BEMPSTS = (uint16_t)~pipebit;
+
+ switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) {
+ case USB_FUNCTION_D0FIFO_DMA:
+ if (g_usbx_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) {
+ /*now, DMA is not supported*/
+ usbx_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) {
+ /*now, DMA is not supported*/
+ usbx_function_read_dma(pipe);
+ usbx_function_disable_brdy_int(pipe);
+ } else {
+ USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ if (g_usbx_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) {
+ /*now, DMA is not supported*/
+ usbx_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) {
+ /*now, DMA is not supported*/
+ usbx_function_read_dma(pipe);
+ usbx_function_disable_brdy_int(pipe);
+ } else {
+ USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ break;
+
+ default:
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ } else {
+ /* write */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2 + 1])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ usbx_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_NRDYInterruptPIPE0
+ * Description : Executes NRDY interrupt for pipe0.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t intenb ; NRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_NRDYInterruptPIPE0(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ USB20X.NRDYSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.NRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_NRDYInterrupt
+ * Description : Executes NRDY interrupt exclude pipe0.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t intenb ; NRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_NRDYInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_nrdy_int
+ * Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+ * : Checks NRDY interrupt cause by PID. When the cause if STALL,
+ * : regards the pipe state as STALL and ends the processing.
+ * : Then the cause is not STALL, increments the error count to
+ * : communicate again. When the error count is 3, determines
+ * : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+ * : This function is executed in the NRDY interrupt handler.
+ * : This function clears NRDY interrupt status.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t int_enb ; NRDYENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+#if 0
+ uint16_t usefifo;
+#endif
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+#if 0
+ uint16_t mbw;
+ uint32_t size;
+#endif
+ uint16_t ep;
+
+ bitcheck = (uint16_t)(status & intenb);
+
+ USB20X.NRDYSTS = (uint16_t)~status;
+
+
+ if (RZA_IO_RegRead_16(&USB20X.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) {
+ /* USB HOST */
+ /* not support */
+
+ } else {
+ /* USB Function */
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) {
+ continue;
+ }
+
+ if (g_usbx_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_WAIT) {
+ continue;
+ }
+
+#if 0
+ usbx_function_set_pid_nak(pipe);
+
+ size = (uint32_t)g_usbx_function_data_count[pipe];
+ mbw = usbx_function_get_mbw(
+ size, (uint32_t)g_usbx_function_data_pointer[pipe]);
+
+ usefifo = (uint16_t)(g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo) {
+
+ case USB_FUNCTION_D0FIFO_USE:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+ USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+
+ default:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+ }
+
+ usbx_function_aclrm(pipe);
+
+ usbx_function_enable_nrdy_int(pipe);
+ usbx_function_enable_brdy_int(pipe);
+
+ usbx_function_set_pid_buf(pipe);
+#endif
+
+ pid = usbx_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) {
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ } else {
+ usbx_function_set_pid_buf(pipe);
+ }
+
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ __NOP();
+ } else {
+ /* write */
+ __NOP();
+ }
+ }
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.NRDYSTS;
+ }
+}
+
+/******************************************************************************
+ * Function Name: usbx_function_BEMPInterruptPIPE0
+ * Description : Executes BEMP interrupt for pipe0.
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BEMPInterruptPIPE0(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ USB20X.BEMPSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+ RZA_IO_RegWrite_16(
+ &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0,
+ USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+
+ /*usbx_function_write_buffer_c(USB_FUNCTION_PIPE0);*/
+ (object->*EP0func)();
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BEMPSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_BEMPInterrupt
+ * Description : Executes BEMP interrupt exclude pipe0.
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BEMPInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_bemp_int
+ * Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+ uint16_t ep;
+
+ bitcheck = (uint16_t)(status & intenb);
+
+ USB20X.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) {
+ continue;
+ }
+
+ pid = usbx_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) ||
+ (pid == DEVDRV_USBF_PID_STALL2)) {
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+
+ } else {
+ inbuf = usbx_function_get_inbuf(pipe);
+
+ if (inbuf == 0) {
+ usbx_function_disable_bemp_int(pipe);
+ usbx_function_set_pid_nak(pipe);
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+
+ switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) {
+ case USB_FUNCTION_D0FIFO_DMA:
+ /*now, DMA is not supported*/
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ /*now, DMA is not supported*/
+ break;
+
+ default:
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ __NOP();
+ } else {
+ /* write */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2 + 1])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BEMPSTS;
+ }
+}
+
+/******************************************************************************
+ * Function Name: EP2PIPE
+ * Description : Converts from endpoint to pipe
+ * Arguments : number of endpoint
+ * Return Value : number of pipe
+ *****************************************************************************/
+/*EP2PIPE converter is for pipe1, pipe3 and pipe6 only.*/
+#define EP2PIPE(endpoint) ((uint32_t)usbx_function_EpToPipe(endpoint))
+
+
+/******************************************************************************
+ * Function Name: usbx_function_save_request
+ * Description : Retains the USB request information in variables.
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+#define usbx_function_save_request() \
+ { \
+ uint16_t *bufO = &setup_buffer[0]; \
+ \
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVALID; \
+ /*data[0] <= bmRequest, data[1] <= bmRequestType */ \
+ *bufO++ = USB20X.USBREQ; \
+ /*data[2] data[3] <= wValue*/ \
+ *bufO++ = USB20X.USBVAL; \
+ /*data[4] data[5] <= wIndex*/ \
+ *bufO++ = USB20X.USBINDX; \
+ /*data[6] data[6] <= wIndex*/ \
+ *bufO++ = USB20X.USBLENG; \
+ }
+
+
+/*************************************************************************/
+/*************************************************************************/
+/*************************************************************************/
+
+/*************************************************************************/
+/* constructor */
+USBHAL::USBHAL(void)
+{
+ /* ---- P4_1 : P4_1 (USB0_EN for GR-PEACH) ---- */
+ //usbx_en = new DigitalOut(P4_1, 1);
+
+ /* some constants */
+ int_id = USBIX_IRQn;
+ int_level = ( 2 << 3 );
+ clock_mode = USBFCLOCK_X1_48MHZ;
+#if (USB_FUNCTION_HISPEED == 0)
+ mode = USB_FUNCTION_FULL_SPEED;
+#else
+ mode = USB_FUNCTION_HIGH_SPEED;
+#endif
+ EP0_read_status = DEVDRV_USBF_WRITEEND;
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ(int_id);
+
+ /* Setup the end point */
+ epCallback[ 0] = &USBHAL::EP1_OUT_callback;
+ epCallback[ 1] = &USBHAL::EP1_IN_callback;
+ epCallback[ 2] = &USBHAL::EP2_OUT_callback;
+ epCallback[ 3] = &USBHAL::EP2_IN_callback;
+ epCallback[ 4] = &USBHAL::EP3_OUT_callback;
+ epCallback[ 5] = &USBHAL::EP3_IN_callback;
+ epCallback[ 6] = &USBHAL::EP4_OUT_callback;
+ epCallback[ 7] = &USBHAL::EP4_IN_callback;
+ epCallback[ 8] = &USBHAL::EP5_OUT_callback;
+ epCallback[ 9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ /* registers me */
+ instance = this;
+
+ /* Clear pipe table */
+ usbx_function_clear_pipe_tbl();
+
+/******************************************************************************
+ * Function Name: usbx_api_function_init
+ * Description : Initializes the USB module in the USB function mode.
+ *****************************************************************************/
+ /* The clock of USB0 modules is permitted */
+#if (USB_FUNCTION_CH == 0)
+ CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71);
+#else
+ CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71 | CPG_STBCR7_MSTP70);
+#endif
+ volatile uint8_t dummy8;
+ dummy8 = CPG.STBCR7;
+
+ {
+/******************************************************************************
+ * Function Name: usbx_function_setting_interrupt
+ * Description : Sets the USB module interrupt level.
+ *****************************************************************************/
+#if 0 /*DMA is not supported*/
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+#endif
+
+ InterruptHandlerRegister(int_id, &_usbisr);
+ GIC_SetPriority(int_id, int_level);
+ GIC_EnableIRQ(int_id);
+
+#if 0 /*DMA is not supported*/
+ d0fifo_dmaintid = Userdef_USB_usbx_function_d0fifo_dmaintid();
+ if (d0fifo_dmaintid != 0xFFFF) {
+ InterruptHandlerRegister(d0fifo_dmaintid, usbx_function_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, int_level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+#endif
+
+#if 0 /*DMA is not supported*/
+ d1fifo_dmaintid = Userdef_USB_usbx_function_d1fifo_dmaintid();
+ if (d1fifo_dmaintid != 0xFFFF) {
+ InterruptHandlerRegister(d1fifo_dmaintid, usbx_function_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, int_level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#endif
+/*****************************************************************************/
+ }
+
+ /* reset USB module with setting tranciever and HSE=1 */
+ usbx_function_reset_module(clock_mode);
+
+ /* clear variables */
+ usbx_function_init_status();
+
+ /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+ usbx_function_InitModule(mode);
+
+ {
+ uint16_t buf;
+ buf = USB20X.INTENB0;
+ buf |= USB_INTENB0_SOFE;
+ USB20X.INTENB0 = buf;
+ }
+}
+
+/*************************************************************************/
+USBHAL::~USBHAL(void)
+{
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ( int_id );
+ /* Unregisters interrupt function and priority */
+ InterruptHandlerRegister( int_id, (uint32_t)NULL );
+
+ //usbx_en = NULL;
+ instance = NULL;
+}
+
+/*************************************************************************/
+void USBHAL::connect(void)
+{
+ /* Activates USB0_EN */
+ //(*usbx_en) = 0;
+}
+
+
+/*************************************************************************/
+void USBHAL::disconnect(void)
+{
+ /* Deactivates USB0_EN */
+ //(*usbx_en) = 1;
+}
+
+
+/*************************************************************************/
+void USBHAL::configureDevice(void)
+{
+ /*The pipes set up in USBHAL::realiseEndpoint*/
+ /*usbx_function_clear_alt();*/ /* Alternate setting clear */
+ /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/
+}
+
+
+/*************************************************************************/
+void USBHAL::unconfigureDevice(void)
+{
+ /* The Interface would be managed by USBDevice */
+ /*usbx_function_clear_alt();*/ /* Alternate setting clear */
+ /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/
+}
+
+
+/*************************************************************************/
+void USBHAL::setAddress(uint8_t address)
+{
+ if (address <= 127) {
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); /* OK */
+ } else {
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); /* Not Spec */
+ }
+}
+
+
+/*************************************************************************/
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags)
+{
+ const struct PIPECFGREC *cfg;
+ uint16_t pipe;
+ uint16_t buf;
+
+ if ( (EP0OUT == endpoint) || (EP0IN == endpoint) ) {
+ return true;
+ }
+
+ for (cfg = &def_pipecfg[0]; cfg->pipesel != 0; cfg++) {
+ if (cfg->endpoint == endpoint) {
+ break;
+ }
+ }
+ if (cfg->pipesel == 0) {
+ return false;
+ }
+
+ pipe = ((cfg->pipesel & USB_PIPESEL_PIPESEL) >> USB_PIPESEL_PIPESEL_SHIFT);
+
+ g_usbx_function_PipeTbl[ pipe ] = (uint16_t)(endpoint | ((cfg->pipesel & USB_FUNCTION_FIFO_USE) << 0));
+
+ /* There are maintenance routine of SHTNAK and BFRE bits
+ * in original sample program. This sample is not
+ * programmed. Do maintenance the "def_pipecfg" array if
+ * you want it. */
+
+ /* Interrupt Disable */
+ buf = USB20X.BRDYENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.BRDYENB = buf;
+ buf = USB20X.NRDYENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.NRDYENB = buf;
+ buf = USB20X.BEMPENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.BEMPENB = buf;
+
+ usbx_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB20X.CFIFOSEL, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.CFIFOSEL, 0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB20X.D0FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.D0FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB20X.D1FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.D1FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB20X.PIPESEL = pipe;
+ USB20X.PIPECFG = cfg->pipecfg;
+ USB20X.PIPEBUF = cfg->pipebuf;
+ USB20X.PIPEMAXP = cfg->pipemaxp;
+ USB20X.PIPEPERI = cfg->pipeperi;
+
+ g_usbx_function_pipecfg[pipe] = cfg->pipecfg;
+ g_usbx_function_pipebuf[pipe] = cfg->pipebuf;
+ g_usbx_function_pipemaxp[pipe] = cfg->pipemaxp;
+ g_usbx_function_pipeperi[pipe] = cfg->pipeperi;
+
+ /* Buffer Clear */
+ usbx_function_set_sqclr(pipe);
+ usbx_function_aclrm(pipe);
+
+ /* init Global */
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usbx_function_PipeDataSize[pipe] = 0;
+
+ return true;
+}
+
+
+/*************************************************************************/
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+ memcpy(buffer, setup_buffer, MAX_PACKET_SIZE_EP0);
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0readStage(void)
+{
+ // No implements
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0read(void)
+{
+ uint8_t *buffer;
+ uint32_t size;
+
+ /* remain of last writing */
+ while (EP0_read_status != DEVDRV_USBF_WRITEEND) {
+ static uint8_t bbb[2] = { 255, 255 };
+ EP0write(&bbb[0], 0);
+ }
+
+ buffer = (uint8_t*)(&setup_buffer[4]);
+ size = (MAX_PACKET_SIZE_EP0 / 2) - 8;
+ usbx_api_function_CtrlWriteStart(size, buffer);
+}
+
+
+/*************************************************************************/
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+ memcpy(buffer, (uint8_t*)(&setup_buffer[4]), g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0]);
+
+ return g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0];
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+ /* zero byte writing */
+ if ( (size == 0) && (EP0_read_status == DEVDRV_USBF_WRITEEND) ) {
+ return;
+ }
+
+ if (EP0_read_status == DEVDRV_USBF_WRITEEND) {
+ /*1st block*/
+ EP0_read_status = usbx_api_function_CtrlReadStart(size, buffer);
+ } else {
+ /* waits the last transmission */
+ /*other blocks*/
+ g_usbx_function_data_count[ USB_FUNCTION_PIPE0 ] = size;
+ g_usbx_function_data_pointer [ USB_FUNCTION_PIPE0 ] = buffer;
+ EP0_read_status = usbx_function_write_buffer_c(USB_FUNCTION_PIPE0);
+ }
+ /*max size may be deblocking outside*/
+ if (size == MAX_PACKET_SIZE_EP0) {
+ EP0_read_status = DEVDRV_USBF_WRITING;
+ }
+}
+
+
+/*************************************************************************/
+#if 0 // No implements
+void USBHAL::EP0getWriteResult(void)
+{
+}
+#endif
+
+/*************************************************************************/
+void USBHAL::EP0stall(void)
+{
+ stallEndpoint( 0 );
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t max_size)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ EP_STATUS status = EP_COMPLETED;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ case DEVDRV_USBF_PIPE_WAIT:
+ usbx_api_function_set_pid_nak(pipe);
+ usbx_api_function_clear_pipe_status(pipe);
+
+ usbx_api_function_start_receive_transfer(pipe, max_size, recv_buffer);
+ break;
+
+ default:
+ status = EP_PENDING;
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytes_read )
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint16_t pipe_status;
+ uint16_t err;
+ EP_STATUS status = EP_PENDING;
+
+
+ if (EPx_read_status != DEVDRV_USBF_PIPE_WAIT) {
+ return status;
+ }
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read);
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ return EP_COMPLETED;
+
+ case DEVDRV_USBF_PIPE_DONE:
+ return EP_COMPLETED;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ break;
+
+ default:
+ return status;
+ }
+
+ /* sets the output buffer and size */
+ g_usbx_function_data_pointer[pipe] = buffer;
+
+ /* receives data from pipe */
+ err = usbx_function_read_buffer(pipe);
+ recv_error = err;
+ switch (err) {
+ case USB_FUNCTION_READEND:
+ case USB_FUNCTION_READSHRT:
+ case USB_FUNCTION_READOVER:
+ *bytes_read = g_usbx_function_PipeDataSize[pipe];
+ break;
+
+ case USB_FUNCTION_READING:
+ case DEVDRV_USBF_FIFOERROR:
+ break;
+ }
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read);
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_DONE:
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_IDLE:
+ case DEVDRV_USBF_PIPE_NORES:
+ case DEVDRV_USBF_PIPE_STALL:
+ case DEVDRV_USBF_FIFOERROR:
+ default:
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ uint16_t err;
+ uint16_t count;
+ EP_STATUS status = EP_PENDING;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ /* waits the last transmission */
+ count = 30000;
+ while ((pipe_status == DEVDRV_USBF_PIPE_WAIT) || (pipe_status == DEVDRV_USBF_PIPE_DONE)) {
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+ if( --count == 0 ) {
+ pipe_status = DEVDRV_USBF_PIPE_STALL;
+ break;
+ }
+ }
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ err = usbx_api_function_start_send_transfer(pipe, size, data);
+
+ switch (err) {
+ /* finish to write */
+ case DEVDRV_USBF_WRITEEND:
+ /* finish to write, but data is short */
+ case DEVDRV_USBF_WRITESHRT:
+ /* continue to write */
+ case DEVDRV_USBF_WRITING:
+ /* use DMA */
+ case DEVDRV_USBF_WRITEDMA:
+ /* error */
+ case DEVDRV_USBF_FIFOERROR:
+ status = EP_PENDING;
+ break;
+ }
+ break;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ case DEVDRV_USBF_PIPE_DONE:
+ status = EP_PENDING;
+ break;
+
+ case DEVDRV_USBF_PIPE_NORES:
+ case DEVDRV_USBF_PIPE_STALL:
+ default:
+ status = EP_STALLED;
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ EP_STATUS status = EP_PENDING;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ status = EP_PENDING;
+ break;
+
+ case DEVDRV_USBF_PIPE_DONE:
+ usbx_function_stop_transfer(pipe);
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_NORES:
+ status = EP_STALLED;
+ break;
+
+ case DEVDRV_USBF_PIPE_STALL:
+ status = EP_STALLED;
+ break;
+
+ default:
+ status = EP_PENDING;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+
+ usbx_function_clear_pid_stall(pipe);
+}
+
+
+/*************************************************************************/
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+
+ usbx_function_set_pid_stall( pipe );
+}
+
+
+/*************************************************************************/
+bool USBHAL::getEndpointStallState(uint8_t endpoint)
+{
+ // No implemens
+ return false;
+}
+
+
+/*************************************************************************/
+#if 0 // No implements
+void USBHAL::remoteWakeup(void)
+{
+}
+#endif
+
+/*************************************************************************/
+void USBHAL::_usbisr(void)
+{
+ instance->usbisr();
+}
+
+
+/*************************************************************************/
+void USBHAL::usbisr(void)
+{
+ uint16_t int_sts0;
+ uint16_t int_sts1;
+ uint16_t int_sts2;
+ uint16_t int_sts3;
+ uint16_t int_enb0;
+ uint16_t int_enb2;
+ uint16_t int_enb3;
+ uint16_t int_enb4;
+ volatile uint16_t dumy_sts;
+
+
+ int_sts0 = USB20X.INTSTS0;
+
+ if (!(int_sts0 & (
+ USB_FUNCTION_BITVBINT |
+ USB_FUNCTION_BITRESM |
+ USB_FUNCTION_BITSOFR |
+ USB_FUNCTION_BITDVST |
+ USB_FUNCTION_BITCTRT |
+ USB_FUNCTION_BITBEMP |
+ USB_FUNCTION_BITNRDY |
+ USB_FUNCTION_BITBRDY ))) {
+ return;
+ }
+
+ int_sts1 = USB20X.BRDYSTS;
+ int_sts2 = USB20X.NRDYSTS;
+ int_sts3 = USB20X.BEMPSTS;
+ int_enb0 = USB20X.INTENB0;
+ int_enb2 = USB20X.BRDYENB;
+ int_enb3 = USB20X.NRDYENB;
+ int_enb4 = USB20X.BEMPENB;
+
+ if ((int_sts0 & USB_FUNCTION_BITRESM) &&
+ (int_enb0 & USB_FUNCTION_BITRSME)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITRESM;
+ RZA_IO_RegWrite_16(&USB20X.INTENB0, 0, USB_INTENB0_RSME_SHIFT, USB_INTENB0_RSME);
+ /*usbx_function_USB_FUNCTION_Resume();*/
+ suspendStateChanged(1);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITVBINT) &&
+ (int_enb0 & USB_FUNCTION_BITVBSE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVBINT;
+
+ if (usbx_function_CheckVBUStaus() == DEVDRV_USBF_ON) {
+ usbx_function_USB_FUNCTION_Attach();
+ } else {
+ usbx_function_USB_FUNCTION_Detach();
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITSOFR) &&
+ (int_enb0 & USB_FUNCTION_BITSOFE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITSOFR;
+ SOF((USB20X.FRMNUM & USB_FRMNUM_FRNM) >> USB_FRMNUM_FRNM_SHIFT);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITDVST) &&
+ (int_enb0 & USB_FUNCTION_BITDVSE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITDVST;
+ switch (int_sts0 & USB_FUNCTION_BITDVSQ) {
+ case USB_FUNCTION_DS_POWR:
+ break;
+
+ case USB_FUNCTION_DS_DFLT:
+ /*****************************************************************************
+ * Function Name: usbx_function_USB_FUNCTION_BusReset
+ * Description : This function is executed when the USB device is transitioned
+ * : to POWERD_STATE. Sets the device descriptor according to the
+ * : connection speed determined by the USB reset hand shake.
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+ usbx_function_init_status(); /* memory clear */
+
+#if 0
+ /* You would program those steps in USBCallback_busReset
+ * if the system need the comment out steps.
+ */
+
+ if (usbx_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) {
+ /* Device Descriptor reset */
+ usbx_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED);
+ } else {
+ /* Device Descriptor reset */
+ usbx_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED);
+ }
+#endif
+ /* Default Control PIPE reset */
+ /*****************************************************************************
+ * Function Name: usbx_function_ResetDCP
+ * Description : Initializes the default control pipe(DCP).
+ * Outline : Reset default control pipe
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+ USB20X.DCPCFG = 0;
+ USB20X.DCPMAXP = 64; /*TODO: This value is copied from sample*/
+
+ USB20X.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB20X.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB20X.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+
+ busReset();
+ break;
+
+ case USB_FUNCTION_DS_ADDS:
+ break;
+
+ case USB_FUNCTION_DS_CNFG:
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR:
+ case USB_FUNCTION_DS_SPD_DFLT:
+ case USB_FUNCTION_DS_SPD_ADDR:
+ case USB_FUNCTION_DS_SPD_CNFG:
+ suspendStateChanged(0);
+ /*usbx_function_USB_FUNCTION_Suspend();*/
+ break;
+
+ default:
+ break;
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBEMP) &&
+ (int_enb0 & USB_FUNCTION_BITBEMP) &&
+ ((int_sts3 & int_enb4) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== BEMP PIPE0 ==== */
+ usbx_function_BEMPInterruptPIPE0(int_sts3, int_enb4, this, &USBHAL::EP0in);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBRDY) &&
+ (int_enb0 & USB_FUNCTION_BITBRDY) &&
+ ((int_sts1 & int_enb2) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== BRDY PIPE0 ==== */
+ usbx_function_BRDYInterruptPIPE0(int_sts1, int_enb2, this, &USBHAL::EP0out);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITNRDY) &&
+ (int_enb0 & USB_FUNCTION_BITNRDY) &&
+ ((int_sts2 & int_enb3) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== NRDY PIPE0 ==== */
+ usbx_function_NRDYInterruptPIPE0(int_sts2, int_enb3, this, NULL);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITCTRT) && (int_enb0 & USB_FUNCTION_BITCTRE)) {
+ int_sts0 = USB20X.INTSTS0;
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITCTRT;
+
+ if (((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND)) {
+
+ /* remake EP0 into buffer */
+ usbx_function_save_request();
+ if ((USB20X.INTSTS0 & USB_FUNCTION_BITVALID) && (
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND))) {
+ /* New SETUP token received */
+ /* Three dummy reads for cleearing interrupt requests */
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS0;
+ return;
+ }
+ }
+
+ switch (int_sts0 & USB_FUNCTION_BITCTSQ) {
+ case USB_FUNCTION_CS_IDST:
+ if (g_usbx_function_TestModeFlag == DEVDRV_USBF_YES) {
+ /* ==== Test Mode ==== */
+ usbx_function_USB_FUNCTION_TestMode();
+ }
+ /* Needs not procedure in this state */
+ break;
+
+ case USB_FUNCTION_CS_RDDS:
+ /* Reads a setup packet */
+ EP0setupCallback();
+ break;
+
+ case USB_FUNCTION_CS_WRDS:
+ /* Original code was the SetDescriptor was called */
+ EP0setupCallback();
+ break;
+
+ case USB_FUNCTION_CS_WRND:
+ EP0setupCallback();
+
+ /*The EP0setupCallback should finish in successful */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_RDSS:
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_WRSS:
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_SQER:
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+
+ default:
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBEMP) &&
+ (int_enb0 & USB_FUNCTION_BITBEMP) &&
+ (int_sts3 & int_enb4) ) {
+ /* ==== BEMP PIPEx ==== */
+ usbx_function_BEMPInterrupt(int_sts3, int_enb4, this, epCallback);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBRDY) &&
+ (int_enb0 & USB_FUNCTION_BITBRDY) &&
+ (int_sts1 & int_enb2) ) {
+ /* ==== BRDY PIPEx ==== */
+ usbx_function_BRDYInterrupt(int_sts1, int_enb2, this, epCallback);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITNRDY) &&
+ (int_enb0 & USB_FUNCTION_BITNRDY) &&
+ (int_sts2 & int_enb3)) {
+ /* ==== NRDY PIPEx ==== */
+ usbx_function_NRDYInterrupt(int_sts2, int_enb3, this, epCallback);
+ } else {
+ /* Do Nothing */
+ }
+
+ /* Three dummy reads for cleearing interrupt requests */
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS1;
+}
+
+/*************************************************************************/
+#endif
+/*************************************************************************/
+/*EOF*/
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp
new file mode 100644
index 000000000..8faac6170
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp
@@ -0,0 +1,410 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_STM32F4)
+
+#include "USBHAL.h"
+#include "USBRegs_STM32.h"
+#include "pinmap.h"
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete = 0;
+
+static uint32_t bufferEnd = 0;
+static const uint32_t rxFifoSize = 512;
+static uint32_t rxFifoCount = 0;
+
+static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
+
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ return 0;
+}
+
+USBHAL::USBHAL(void) {
+ NVIC_DisableIRQ(OTG_FS_IRQn);
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+
+ // Enable power and clocking
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
+
+#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE)
+ pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+ pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
+ pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
+ pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+ pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+#else
+ pin_function(PA_8, STM_PIN_DATA(2, 10));
+ pin_function(PA_9, STM_PIN_DATA(0, 0));
+ pin_function(PA_10, STM_PIN_DATA(2, 10));
+ pin_function(PA_11, STM_PIN_DATA(2, 10));
+ pin_function(PA_12, STM_PIN_DATA(2, 10));
+
+ // Set ID pin to open drain with pull-up resistor
+ pin_mode(PA_10, OpenDrain);
+ GPIOA->PUPDR &= ~(0x3 << 20);
+ GPIOA->PUPDR |= 1 << 20;
+
+ // Set VBUS pin to open drain
+ pin_mode(PA_9, OpenDrain);
+#endif
+
+ RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
+
+ // Enable interrupts
+ OTG_FS->GREGS.GAHBCFG |= (1 << 0);
+
+ // Turnaround time to maximum value - too small causes packet loss
+ OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
+
+ // Unmask global interrupts
+ OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
+ (1 << 4) | // RX FIFO not empty
+ (1 << 12); // USB reset
+
+ OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
+ (1 << 2); // Non-zero-length status OUT handshake
+
+ OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
+ (1 << 16); // Power Up
+
+ instance = this;
+ NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
+ NVIC_SetPriority(OTG_FS_IRQn, 1);
+}
+
+USBHAL::~USBHAL(void) {
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(OTG_FS_IRQn);
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(OTG_FS_IRQn);
+}
+
+void USBHAL::configureDevice(void) {
+ // Not needed
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // Not needed
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ OTG_FS->DREGS.DCFG |= (address << 4);
+ EP0write(0, 0);
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
+ uint32_t flags) {
+ uint32_t epIndex = endpoint >> 1;
+
+ uint32_t type;
+ switch (endpoint) {
+ case EP0IN:
+ case EP0OUT:
+ type = 0;
+ break;
+ case EPISO_IN:
+ case EPISO_OUT:
+ type = 1;
+ case EPBULK_IN:
+ case EPBULK_OUT:
+ type = 2;
+ break;
+ case EPINT_IN:
+ case EPINT_OUT:
+ type = 3;
+ break;
+ }
+
+ // Generic in or out EP controls
+ uint32_t control = (maxPacket << 0) | // Packet size
+ (1 << 15) | // Active endpoint
+ (type << 18); // Endpoint type
+
+ if (endpoint & 0x1) { // In Endpoint
+ // Set up the Tx FIFO
+ if (endpoint == EP0IN) {
+ OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
+ (bufferEnd << 0);
+ }
+ else {
+ OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
+ (bufferEnd << 0);
+ }
+ bufferEnd += maxPacket >> 2;
+
+ // Set the In EP specific control settings
+ if (endpoint != EP0IN) {
+ control |= (1 << 28); // SD0PID
+ }
+
+ control |= (epIndex << 22) | // TxFIFO index
+ (1 << 27); // SNAK
+ OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
+
+ // Unmask the interrupt
+ OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
+ }
+ else { // Out endpoint
+ // Set the out EP specific control settings
+ control |= (1 << 26); // CNAK
+ OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
+
+ // Unmask the interrupt
+ OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
+ }
+ return true;
+}
+
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer) {
+ memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void) {
+}
+
+void USBHAL::EP0read(void) {
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ uint32_t* buffer32 = (uint32_t *) buffer;
+ uint32_t length = rxFifoCount;
+ for (uint32_t i = 0; i < length; i += 4) {
+ buffer32[i >> 2] = OTG_FS->FIFO[0][0];
+ }
+
+ rxFifoCount = 0;
+ return length;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWrite(0, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+}
+
+void USBHAL::EP0stall(void) {
+ // If we stall the out endpoint here then we have problems transferring
+ // and setup requests after the (stalled) get device qualifier requests.
+ // TODO: Find out if this is correct behavior, or whether we are doing
+ // something else wrong
+ stallEndpoint(EP0IN);
+// stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ uint32_t epIndex = endpoint >> 1;
+ uint32_t size = (1 << 19) | // 1 packet
+ (maximumSize << 0); // Packet size
+// if (endpoint == EP0OUT) {
+ size |= (1 << 29); // 1 setup packet
+// }
+ OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
+ OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
+ (1 << 26); // Clear NAK
+
+ epComplete &= ~(1 << endpoint);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+ if (!(epComplete & (1 << endpoint))) {
+ return EP_PENDING;
+ }
+
+ uint32_t* buffer32 = (uint32_t *) buffer;
+ uint32_t length = rxFifoCount;
+ for (uint32_t i = 0; i < length; i += 4) {
+ buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
+ }
+ rxFifoCount = 0;
+ *bytesRead = length;
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t epIndex = endpoint >> 1;
+ OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
+ (size << 0); // Size of packet
+ OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
+ (1 << 26); // CNAK
+ OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
+
+ while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
+
+ for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
+ OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
+ }
+
+ epComplete &= ~(1 << endpoint);
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & (1 << endpoint)) {
+ epComplete &= ~(1 << endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ if (endpoint & 0x1) { // In EP
+ OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
+ (1 << 21); // Stall
+ }
+ else { // Out EP
+ OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
+ OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
+ (1 << 21); // Stall
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ return false;
+}
+
+void USBHAL::remoteWakeup(void) {
+}
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
+ // Set SNAK bits
+ OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
+
+ OTG_FS->DREGS.DIEPMSK = (1 << 0);
+
+ bufferEnd = 0;
+
+ // Set the receive FIFO size
+ OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
+ bufferEnd += rxFifoSize >> 2;
+
+ // Create the endpoints, and wait for setup packets on out EP0
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+
+ OTG_FS->GREGS.GINTSTS = (1 << 12);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
+ uint32_t status = OTG_FS->GREGS.GRXSTSP;
+
+ uint32_t endpoint = (status & 0xF) << 1;
+ uint32_t length = (status >> 4) & 0x7FF;
+ uint32_t type = (status >> 17) & 0xF;
+
+ rxFifoCount = length;
+
+ if (type == 0x6) {
+ // Setup packet
+ for (uint32_t i=0; i<length; i+=4) {
+ setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
+ }
+ rxFifoCount = 0;
+ }
+
+ if (type == 0x4) {
+ // Setup complete
+ EP0setupCallback();
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+ }
+
+ if (type == 0x2) {
+ // Out packet
+ if (endpoint == EP0OUT) {
+ EP0out();
+ }
+ else {
+ epComplete |= (1 << endpoint);
+ if ((instance->*(epCallback[endpoint - 2]))()) {
+ epComplete &= (1 << endpoint);
+ }
+ }
+ }
+
+ for (uint32_t i=0; i<rxFifoCount; i+=4) {
+ (void) OTG_FS->FIFO[0][0];
+ }
+ OTG_FS->GREGS.GINTSTS = (1 << 4);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
+ // Loop through the in endpoints
+ for (uint32_t i=0; i<4; i++) {
+ if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
+
+ if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
+ // If the Tx FIFO is empty on EP0 we need to send a further
+ // packet, so call EP0in()
+ if (i == 0) {
+ EP0in();
+ }
+ // Clear the interrupt
+ OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
+ // Stop firing Tx empty interrupts
+ // Will get turned on again if another write is called
+ OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
+ }
+
+ // If the transfer is complete
+ if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
+ epComplete |= (1 << (1 + (i << 1)));
+ OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
+ }
+ }
+ }
+ OTG_FS->GREGS.GINTSTS = (1 << 18);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
+ SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
+ OTG_FS->GREGS.GINTSTS = (1 << 3);
+ }
+}
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h
new file mode 100644
index 000000000..3e11a49c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h
@@ -0,0 +1,149 @@
+/**
+ ******************************************************************************
+ * @file usb_regs.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 19-March-2012
+ * @brief hardware registers
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+#ifndef __USB_OTG_REGS_H__
+#define __USB_OTG_REGS_H__
+
+typedef struct //000h
+{
+ __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GREGS;
+
+typedef struct // 800h
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+}
+USB_OTG_DREGS;
+
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ uint32_t Reserved14;
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEPREGS;
+
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ uint32_t Reserved14[3];
+}
+USB_OTG_OUTEPREGS;
+
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HREGS;
+
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ uint32_t Reserved[3];
+}
+USB_OTG_HC_REGS;
+
+typedef struct
+{
+ USB_OTG_GREGS GREGS;
+ uint32_t RESERVED0[188];
+ USB_OTG_HREGS HREGS;
+ uint32_t RESERVED1[9];
+ __IO uint32_t HPRT;
+ uint32_t RESERVED2[47];
+ USB_OTG_HC_REGS HC_REGS[8];
+ uint32_t RESERVED3[128];
+ USB_OTG_DREGS DREGS;
+ uint32_t RESERVED4[50];
+ USB_OTG_INEPREGS INEP_REGS[4];
+ uint32_t RESERVED5[96];
+ USB_OTG_OUTEPREGS OUTEP_REGS[4];
+ uint32_t RESERVED6[160];
+ __IO uint32_t PCGCCTL;
+ uint32_t RESERVED7[127];
+ __IO uint32_t FIFO[4][1024];
+}
+USB_OTG_CORE_REGS;
+
+
+#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
+#define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
+
+#endif //__USB_OTG_REGS_H__
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp
new file mode 100644
index 000000000..571421d82
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp
@@ -0,0 +1,276 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBHAL.h"
+#include "USBHID.h"
+
+
+USBHID::USBHID(uint8_t output_report_length, uint8_t input_report_length, uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect): USBDevice(vendor_id, product_id, product_release)
+{
+ output_length = output_report_length;
+ input_length = input_report_length;
+ if(connect) {
+ USBDevice::connect();
+ }
+}
+
+
+bool USBHID::send(HID_REPORT *report)
+{
+ return write(EPINT_IN, report->data, report->length, MAX_HID_REPORT_SIZE);
+}
+
+bool USBHID::sendNB(HID_REPORT *report)
+{
+ return writeNB(EPINT_IN, report->data, report->length, MAX_HID_REPORT_SIZE);
+}
+
+
+bool USBHID::read(HID_REPORT *report)
+{
+ uint32_t bytesRead = 0;
+ bool result;
+ result = USBDevice::readEP(EPINT_OUT, report->data, &bytesRead, MAX_HID_REPORT_SIZE);
+ if(!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ report->length = bytesRead;
+ return result;
+}
+
+
+bool USBHID::readNB(HID_REPORT *report)
+{
+ uint32_t bytesRead = 0;
+ bool result;
+ result = USBDevice::readEP_NB(EPINT_OUT, report->data, &bytesRead, MAX_HID_REPORT_SIZE);
+ // if readEP_NB did not succeed, does not issue a readStart
+ if (!result)
+ return false;
+ report->length = bytesRead;
+ if(!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return result;
+}
+
+
+uint16_t USBHID::reportDescLength() {
+ reportDesc();
+ return reportLength;
+}
+
+
+
+//
+// Route callbacks from lower layers to class(es)
+//
+
+
+// Called in ISR context
+// Called by USBDevice on Endpoint0 request
+// This is used to handle extensions to standard requests
+// and class specific requests
+// Return true if class handles this request
+bool USBHID::USBCallback_request() {
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ uint8_t *hidDescriptor;
+
+ // Process additional standard requests
+
+ if ((transfer->setup.bmRequestType.Type == STANDARD_TYPE))
+ {
+ switch (transfer->setup.bRequest)
+ {
+ case GET_DESCRIPTOR:
+ switch (DESCRIPTOR_TYPE(transfer->setup.wValue))
+ {
+ case REPORT_DESCRIPTOR:
+ if ((reportDesc() != NULL) \
+ && (reportDescLength() != 0))
+ {
+ transfer->remaining = reportDescLength();
+ transfer->ptr = reportDesc();
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ break;
+ case HID_DESCRIPTOR:
+ // Find the HID descriptor, after the configuration descriptor
+ hidDescriptor = findDescriptor(HID_DESCRIPTOR);
+ if (hidDescriptor != NULL)
+ {
+ transfer->remaining = HID_DESCRIPTOR_LENGTH;
+ transfer->ptr = hidDescriptor;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ break;
+
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Process class-specific requests
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE)
+ {
+ switch (transfer->setup.bRequest)
+ {
+ case SET_REPORT:
+ // First byte will be used for report ID
+ outputReport.data[0] = transfer->setup.wValue & 0xff;
+ outputReport.length = transfer->setup.wLength + 1;
+
+ transfer->remaining = sizeof(outputReport.data) - 1;
+ transfer->ptr = &outputReport.data[1];
+ transfer->direction = HOST_TO_DEVICE;
+ transfer->notify = true;
+ success = true;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+
+#define DEFAULT_CONFIGURATION (1)
+
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported
+bool USBHID::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPINT_IN, MAX_PACKET_SIZE_EPINT);
+ addEndpoint(EPINT_OUT, MAX_PACKET_SIZE_EPINT);
+
+ // We activate the endpoint to be able to recceive data
+ readStart(EPINT_OUT, MAX_PACKET_SIZE_EPINT);
+ return true;
+}
+
+
+uint8_t * USBHID::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'H',0,'I',0,'D',0, //bString iInterface - HID
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBHID::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'H',0,'I',0,'D',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 //bString iProduct - HID device
+ };
+ return stringIproductDescriptor;
+}
+
+
+
+uint8_t * USBHID::reportDesc() {
+ static uint8_t reportDescriptor[] = {
+ 0x06, LSB(0xFFAB), MSB(0xFFAB),
+ 0x0A, LSB(0x0200), MSB(0x0200),
+ 0xA1, 0x01, // Collection 0x01
+ 0x75, 0x08, // report size = 8 bits
+ 0x15, 0x00, // logical minimum = 0
+ 0x26, 0xFF, 0x00, // logical maximum = 255
+ 0x95, input_length, // report count
+ 0x09, 0x01, // usage
+ 0x81, 0x02, // Input (array)
+ 0x95, output_length,// report count
+ 0x09, 0x02, // usage
+ 0x91, 0x02, // Output (array)
+ 0xC0 // end collection
+
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+}
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBHID::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPower
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ HID_SUBCLASS_NONE, // bInterfaceSubClass
+ HID_PROTOCOL_NONE, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(this->reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(this->reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h
new file mode 100644
index 000000000..faa75cb94
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h
@@ -0,0 +1,172 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USB_HID_H
+#define USB_HID_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBHID_Types.h"
+#include "USBDevice.h"
+
+
+/**
+ * USBHID example
+ * @code
+ * #include "mbed.h"
+ * #include "USBHID.h"
+ *
+ * USBHID hid;
+ * HID_REPORT recv;
+ * BusOut leds(LED1,LED2,LED3,LED4);
+ *
+ * int main(void) {
+ * while (1) {
+ * hid.read(&recv);
+ * leds = recv.data[0];
+ * }
+ * }
+ * @endcode
+ */
+
+class USBHID: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param output_report_length Maximum length of a sent report (up to 64 bytes) (default: 64 bytes)
+ * @param input_report_length Maximum length of a received report (up to 64 bytes) (default: 64 bytes)
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ * @param connect Connect the device
+ */
+ USBHID(uint8_t output_report_length = 64, uint8_t input_report_length = 64, uint16_t vendor_id = 0x1234, uint16_t product_id = 0x0006, uint16_t product_release = 0x0001, bool connect = true);
+
+
+ /**
+ * Send a Report. warning: blocking
+ *
+ * @param report Report which will be sent (a report is defined by all data and the length)
+ * @returns true if successful
+ */
+ bool send(HID_REPORT *report);
+
+
+ /**
+ * Send a Report. warning: non blocking
+ *
+ * @param report Report which will be sent (a report is defined by all data and the length)
+ * @returns true if successful
+ */
+ bool sendNB(HID_REPORT *report);
+
+ /**
+ * Read a report: blocking
+ *
+ * @param report pointer to the report to fill
+ * @returns true if successful
+ */
+ bool read(HID_REPORT * report);
+
+ /**
+ * Read a report: non blocking
+ *
+ * @param report pointer to the report to fill
+ * @returns true if successful
+ */
+ bool readNB(HID_REPORT * report);
+
+protected:
+ uint16_t reportLength;
+
+ /*
+ * Get the Report descriptor
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Get the length of the report descriptor
+ *
+ * @returns the length of the report descriptor
+ */
+ virtual uint16_t reportDescLength();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+
+ /*
+ * HID Report received by SET_REPORT request. Warning: Called in ISR context
+ * First byte of data will be the report ID
+ *
+ * @param report Data and length received
+ */
+ virtual void HID_callbackSetReport(HID_REPORT *report){};
+
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request();
+
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+private:
+ HID_REPORT outputReport;
+ uint8_t output_length;
+ uint8_t input_length;
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h
new file mode 100644
index 000000000..b8b181bed
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h
@@ -0,0 +1,91 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBCLASS_HID_TYPES
+#define USBCLASS_HID_TYPES
+
+#include <stdint.h>
+
+/* */
+#define HID_VERSION_1_11 (0x0111)
+
+/* HID Class */
+#define HID_CLASS (3)
+#define HID_SUBCLASS_NONE (0)
+#define HID_PROTOCOL_NONE (0)
+
+/* Descriptors */
+#define HID_DESCRIPTOR (33)
+#define HID_DESCRIPTOR_LENGTH (0x09)
+#define REPORT_DESCRIPTOR (34)
+
+/* Class requests */
+#define GET_REPORT (0x1)
+#define GET_IDLE (0x2)
+#define SET_REPORT (0x9)
+#define SET_IDLE (0xa)
+
+/* HID Class Report Descriptor */
+/* Short items: size is 0, 1, 2 or 3 specifying 0, 1, 2 or 4 (four) bytes */
+/* of data as per HID Class standard */
+
+/* Main items */
+#define INPUT(size) (0x80 | size)
+#define OUTPUT(size) (0x90 | size)
+#define FEATURE(size) (0xb0 | size)
+#define COLLECTION(size) (0xa0 | size)
+#define END_COLLECTION(size) (0xc0 | size)
+
+/* Global items */
+#define USAGE_PAGE(size) (0x04 | size)
+#define LOGICAL_MINIMUM(size) (0x14 | size)
+#define LOGICAL_MAXIMUM(size) (0x24 | size)
+#define PHYSICAL_MINIMUM(size) (0x34 | size)
+#define PHYSICAL_MAXIMUM(size) (0x44 | size)
+#define UNIT_EXPONENT(size) (0x54 | size)
+#define UNIT(size) (0x64 | size)
+#define REPORT_SIZE(size) (0x74 | size)
+#define REPORT_ID(size) (0x84 | size)
+#define REPORT_COUNT(size) (0x94 | size)
+#define PUSH(size) (0xa4 | size)
+#define POP(size) (0xb4 | size)
+
+/* Local items */
+#define USAGE(size) (0x08 | size)
+#define USAGE_MINIMUM(size) (0x18 | size)
+#define USAGE_MAXIMUM(size) (0x28 | size)
+#define DESIGNATOR_INDEX(size) (0x38 | size)
+#define DESIGNATOR_MINIMUM(size) (0x48 | size)
+#define DESIGNATOR_MAXIMUM(size) (0x58 | size)
+#define STRING_INDEX(size) (0x78 | size)
+#define STRING_MINIMUM(size) (0x88 | size)
+#define STRING_MAXIMUM(size) (0x98 | size)
+#define DELIMITER(size) (0xa8 | size)
+
+/* HID Report */
+/* Where report IDs are used the first byte of 'data' will be the */
+/* report ID and 'length' will include this report ID byte. */
+
+#define MAX_HID_REPORT_SIZE (64)
+
+typedef struct {
+ uint32_t length;
+ uint8_t data[MAX_HID_REPORT_SIZE];
+} HID_REPORT;
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp
new file mode 100644
index 000000000..df4ca4798
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp
@@ -0,0 +1,553 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+
+#include "USBKeyboard.h"
+
+#define REPORT_ID_KEYBOARD 1
+#define REPORT_ID_VOLUME 3
+
+
+typedef struct {
+ unsigned char usage;
+ unsigned char modifier;
+} KEYMAP;
+
+#ifdef US_KEYBOARD
+/* US keyboard (as HID standard) */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x34, KEY_SHIFT}, /* " */
+ {0x20, KEY_SHIFT}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x1f, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x31, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x31, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x35, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+
+#else
+/* UK keyboard */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x1f, KEY_SHIFT}, /* " */
+ {0x32, 0}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x34, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x64, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x64, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x32, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+#endif
+
+uint8_t * USBKeyboard::reportDesc() {
+ static uint8_t reportDescriptor[] = {
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x06, // Keyboard
+ COLLECTION(1), 0x01, // Application
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+
+ USAGE_PAGE(1), 0x07, // Key Codes
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01, // Constant
+
+
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08, // LEDs
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01, // Constant
+
+
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x65,
+ USAGE_PAGE(1), 0x07, // Key Codes
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(1), 0x65,
+ INPUT(1), 0x00, // Data, Array
+ END_COLLECTION(0),
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+}
+
+
+bool USBKeyboard::EPINT_OUT_callback() {
+ uint32_t bytesRead = 0;
+ uint8_t led[65];
+ USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE);
+
+ // we take led[1] because led[0] is the report ID
+ lock_status = led[1] & 0x07;
+
+ // We activate the endpoint to be able to recceive data
+ if (!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+uint8_t USBKeyboard::lockStatus() {
+ return lock_status;
+}
+
+int USBKeyboard::_putc(int c) {
+ return keyCode(c, keymap[c].modifier);
+}
+
+bool USBKeyboard::keyCode(uint8_t key, uint8_t modifier) {
+ // Send a simulated keyboard keypress. Returns true if successful.
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_KEYBOARD;
+ report.data[1] = modifier;
+ report.data[2] = 0;
+ report.data[3] = keymap[key].usage;
+ report.data[4] = 0;
+ report.data[5] = 0;
+ report.data[6] = 0;
+ report.data[7] = 0;
+ report.data[8] = 0;
+
+ report.length = 9;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[1] = 0;
+ report.data[3] = 0;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ return true;
+
+}
+
+
+bool USBKeyboard::mediaControl(MEDIA_KEY key) {
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = (1 << key) & 0x7f;
+
+ report.length = 2;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = 0;
+
+ report.length = 2;
+
+ return send(&report);
+}
+
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBKeyboard::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPowerHello World from Mbed
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ 1, // bInterfaceSubClass
+ 1, // bInterfaceProtocol (keyboard)
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h
new file mode 100644
index 000000000..c58ae56f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h
@@ -0,0 +1,183 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBKEYBOARD_H
+#define USBKEYBOARD_H
+
+#include "USBHID.h"
+#include "Stream.h"
+
+/* Modifiers */
+enum MODIFIER_KEY {
+ KEY_CTRL = 1,
+ KEY_SHIFT = 2,
+ KEY_ALT = 4,
+};
+
+
+enum MEDIA_KEY {
+ KEY_NEXT_TRACK, /*!< next Track Button */
+ KEY_PREVIOUS_TRACK, /*!< Previous track Button */
+ KEY_STOP, /*!< Stop Button */
+ KEY_PLAY_PAUSE, /*!< Play/Pause Button */
+ KEY_MUTE, /*!< Mute Button */
+ KEY_VOLUME_UP, /*!< Volume Up Button */
+ KEY_VOLUME_DOWN, /*!< Volume Down Button */
+};
+
+enum FUNCTION_KEY {
+ KEY_F1 = 128, /* F1 key */
+ KEY_F2, /* F2 key */
+ KEY_F3, /* F3 key */
+ KEY_F4, /* F4 key */
+ KEY_F5, /* F5 key */
+ KEY_F6, /* F6 key */
+ KEY_F7, /* F7 key */
+ KEY_F8, /* F8 key */
+ KEY_F9, /* F9 key */
+ KEY_F10, /* F10 key */
+ KEY_F11, /* F11 key */
+ KEY_F12, /* F12 key */
+
+ KEY_PRINT_SCREEN, /* Print Screen key */
+ KEY_SCROLL_LOCK, /* Scroll lock */
+ KEY_CAPS_LOCK, /* caps lock */
+ KEY_NUM_LOCK, /* num lock */
+ KEY_INSERT, /* Insert key */
+ KEY_HOME, /* Home key */
+ KEY_PAGE_UP, /* Page Up key */
+ KEY_PAGE_DOWN, /* Page Down key */
+
+ RIGHT_ARROW, /* Right arrow */
+ LEFT_ARROW, /* Left arrow */
+ DOWN_ARROW, /* Down arrow */
+ UP_ARROW, /* Up arrow */
+};
+
+/**
+ * USBKeyboard example
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBKeyboard.h"
+ *
+ * USBKeyboard key;
+ *
+ * int main(void)
+ * {
+ * while (1)
+ * {
+ * key.printf("Hello World\r\n");
+ * wait(1);
+ * }
+ * }
+ *
+ * @endcode
+ */
+class USBKeyboard: public USBHID, public Stream {
+public:
+
+ /**
+ * Constructor
+ *
+ *
+ * @param leds Leds bus: first: NUM_LOCK, second: CAPS_LOCK, third: SCROLL_LOCK
+ * @param vendor_id Your vendor_id (default: 0x1235)
+ * @param product_id Your product_id (default: 0x0050)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBKeyboard(uint16_t vendor_id = 0x1235, uint16_t product_id = 0x0050, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false) {
+ lock_status = 0;
+ connect();
+ };
+
+ /**
+ * To send a character defined by a modifier(CTRL, SHIFT, ALT) and the key
+ *
+ * @code
+ * //To send CTRL + s (save)
+ * keyboard.keyCode('s', KEY_CTRL);
+ * @endcode
+ *
+ * @param modifier bit 0: KEY_CTRL, bit 1: KEY_SHIFT, bit 2: KEY_ALT (default: 0)
+ * @param key character to send
+ * @returns true if there is no error, false otherwise
+ */
+ bool keyCode(uint8_t key, uint8_t modifier = 0);
+
+ /**
+ * Send a character
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Control media keys
+ *
+ * @param key media key pressed (KEY_NEXT_TRACK, KEY_PREVIOUS_TRACK, KEY_STOP, KEY_PLAY_PAUSE, KEY_MUTE, KEY_VOLUME_UP, KEY_VOLUME_DOWN)
+ * @returns true if there is no error, false otherwise
+ */
+ bool mediaControl(MEDIA_KEY key);
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys
+ *
+ * @returns if handle by subclass, return true
+ */
+ virtual bool EPINT_OUT_callback();
+
+ /**
+ * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important:
+ * - First bit: NUM_LOCK
+ * - Second bit: CAPS_LOCK
+ * - Third bit: SCROLL_LOCK
+ *
+ * @returns status of lock keys
+ */
+ uint8_t lockStatus();
+
+protected:
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+private:
+ //dummy otherwise it doesn,t compile (we must define all methods of an abstract class)
+ virtual int _getc() {
+ return -1;
+ };
+
+ uint8_t lock_status;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp
new file mode 100644
index 000000000..980e67909
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp
@@ -0,0 +1,245 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMouse.h"
+
+bool USBMouse::update(int16_t x, int16_t y, uint8_t button, int8_t z) {
+ switch (mouse_type) {
+ case REL_MOUSE:
+ while (x > 127) {
+ if (!mouseSend(127, 0, button, z)) return false;
+ x = x - 127;
+ }
+ while (x < -128) {
+ if (!mouseSend(-128, 0, button, z)) return false;
+ x = x + 128;
+ }
+ while (y > 127) {
+ if (!mouseSend(0, 127, button, z)) return false;
+ y = y - 127;
+ }
+ while (y < -128) {
+ if (!mouseSend(0, -128, button, z)) return false;
+ y = y + 128;
+ }
+ return mouseSend(x, y, button, z);
+ case ABS_MOUSE:
+ HID_REPORT report;
+
+ report.data[0] = x & 0xff;
+ report.data[1] = (x >> 8) & 0xff;
+ report.data[2] = y & 0xff;
+ report.data[3] = (y >> 8) & 0xff;
+ report.data[4] = -z;
+ report.data[5] = button & 0x07;
+
+ report.length = 6;
+
+ return send(&report);
+ default:
+ return false;
+ }
+}
+
+bool USBMouse::mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z) {
+ HID_REPORT report;
+ report.data[0] = buttons & 0x07;
+ report.data[1] = x;
+ report.data[2] = y;
+ report.data[3] = -z; // >0 to scroll down, <0 to scroll up
+
+ report.length = 4;
+
+ return send(&report);
+}
+
+bool USBMouse::move(int16_t x, int16_t y) {
+ return update(x, y, button, 0);
+}
+
+bool USBMouse::scroll(int8_t z) {
+ return update(0, 0, button, z);
+}
+
+
+bool USBMouse::doubleClick() {
+ if (!click(MOUSE_LEFT))
+ return false;
+ wait(0.1);
+ return click(MOUSE_LEFT);
+}
+
+bool USBMouse::click(uint8_t button) {
+ if (!update(0, 0, button, 0))
+ return false;
+ wait(0.01);
+ return update(0, 0, 0, 0);
+}
+
+bool USBMouse::press(uint8_t button_) {
+ button = button_ & 0x07;
+ return update(0, 0, button, 0);
+}
+
+bool USBMouse::release(uint8_t button_) {
+ button = (button & (~button_)) & 0x07;
+ return update(0, 0, button, 0);
+}
+
+
+uint8_t * USBMouse::reportDesc() {
+
+ if (mouse_type == REL_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+ USAGE_PAGE(1), 0x01, // Genric Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x1,
+ USAGE_MAXIMUM(1), 0x3,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01,
+
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x08,
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81,
+ LOGICAL_MAXIMUM(1), 0x7f,
+ INPUT(1), 0x06, // Relative data
+
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ } else if (mouse_type == ABS_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(2), 0xff, 0x7f, // 32767
+ REPORT_SIZE(1), 0x10,
+ REPORT_COUNT(1), 0x02,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81, // -127
+ LOGICAL_MAXIMUM(1), 0x7f, // 127
+ REPORT_SIZE(1), 0x08,
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x06, // Data, Variable, Relative
+
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x03,
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(1), 0x01, // 1
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01, // Constant
+
+ END_COLLECTION(0),
+ END_COLLECTION(0)
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ }
+ return NULL;
+}
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBMouse::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPowerHello World from Mbed
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ 1, // bInterfaceSubClass
+ 2, // bInterfaceProtocol (mouse)
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h
new file mode 100644
index 000000000..7aa426334
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h
@@ -0,0 +1,209 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMOUSE_H
+#define USBMOUSE_H
+
+#include "USBHID.h"
+
+#define REPORT_ID_MOUSE 2
+
+/* Common usage */
+
+enum MOUSE_BUTTON
+{
+ MOUSE_LEFT = 1,
+ MOUSE_RIGHT = 2,
+ MOUSE_MIDDLE = 4,
+};
+
+/* X and Y limits */
+/* These values do not directly map to screen pixels */
+/* Zero may be interpreted as meaning 'no movement' */
+#define X_MIN_ABS (1) /*!< Minimum value on x-axis */
+#define Y_MIN_ABS (1) /*!< Minimum value on y-axis */
+#define X_MAX_ABS (0x7fff) /*!< Maximum value on x-axis */
+#define Y_MAX_ABS (0x7fff) /*!< Maximum value on y-axis */
+
+#define X_MIN_REL (-127) /*!< The maximum value that we can move to the left on the x-axis */
+#define Y_MIN_REL (-127) /*!< The maximum value that we can move up on the y-axis */
+#define X_MAX_REL (127) /*!< The maximum value that we can move to the right on the x-axis */
+#define Y_MAX_REL (127) /*!< The maximum value that we can move down on the y-axis */
+
+enum MOUSE_TYPE
+{
+ ABS_MOUSE,
+ REL_MOUSE,
+};
+
+/**
+ *
+ * USBMouse example
+ * @code
+ * #include "mbed.h"
+ * #include "USBMouse.h"
+ *
+ * USBMouse mouse;
+ *
+ * int main(void)
+ * {
+ * while (1)
+ * {
+ * mouse.move(20, 0);
+ * wait(0.5);
+ * }
+ * }
+ *
+ * @endcode
+ *
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "USBMouse.h"
+ * #include <math.h>
+ *
+ * USBMouse mouse(ABS_MOUSE);
+ *
+ * int main(void)
+ * {
+ * uint16_t x_center = (X_MAX_ABS - X_MIN_ABS)/2;
+ * uint16_t y_center = (Y_MAX_ABS - Y_MIN_ABS)/2;
+ * uint16_t x_screen = 0;
+ * uint16_t y_screen = 0;
+ *
+ * uint32_t x_origin = x_center;
+ * uint32_t y_origin = y_center;
+ * uint32_t radius = 5000;
+ * uint32_t angle = 0;
+ *
+ * while (1)
+ * {
+ * x_screen = x_origin + cos((double)angle*3.14/180.0)*radius;
+ * y_screen = y_origin + sin((double)angle*3.14/180.0)*radius;
+ *
+ * mouse.move(x_screen, y_screen);
+ * angle += 3;
+ * wait(0.01);
+ * }
+ * }
+ *
+ * @endcode
+ */
+class USBMouse: public USBHID
+{
+ public:
+
+ /**
+ * Constructor
+ *
+ * @param mouse_type Mouse type: ABS_MOUSE (absolute mouse) or REL_MOUSE (relative mouse) (default: REL_MOUSE)
+ * @param vendor_id Your vendor_id (default: 0x1234)
+ * @param product_id Your product_id (default: 0x0001)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBMouse(MOUSE_TYPE mouse_type = REL_MOUSE, uint16_t vendor_id = 0x1234, uint16_t product_id = 0x0001, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false)
+ {
+ button = 0;
+ this->mouse_type = mouse_type;
+ connect();
+ };
+
+ /**
+ * Write a state of the mouse
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @param buttons buttons state (first bit represents MOUSE_LEFT, second bit MOUSE_RIGHT and third bit MOUSE_MIDDLE)
+ * @param z wheel state (>0 to scroll down, <0 to scroll up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool update(int16_t x, int16_t y, uint8_t buttons, int8_t z);
+
+
+ /**
+ * Move the cursor to (x, y)
+ *
+ * @param x-axis position
+ * @param y-axis position
+ * @returns true if there is no error, false otherwise
+ */
+ bool move(int16_t x, int16_t y);
+
+ /**
+ * Press one or several buttons
+ *
+ * @param button button state (ex: press(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool press(uint8_t button);
+
+ /**
+ * Release one or several buttons
+ *
+ * @param button button state (ex: release(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool release(uint8_t button);
+
+ /**
+ * Double click (MOUSE_LEFT)
+ *
+ * @returns true if there is no error, false otherwise
+ */
+ bool doubleClick();
+
+ /**
+ * Click
+ *
+ * @param button state of the buttons ( ex: clic(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool click(uint8_t button);
+
+ /**
+ * Scrolling
+ *
+ * @param z value of the wheel (>0 to go down, <0 to go up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool scroll(int8_t z);
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ protected:
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ private:
+ MOUSE_TYPE mouse_type;
+ uint8_t button;
+ bool mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp
new file mode 100644
index 000000000..cd6809120
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp
@@ -0,0 +1,706 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMouseKeyboard.h"
+
+typedef struct {
+ unsigned char usage;
+ unsigned char modifier;
+} KEYMAP;
+
+#ifdef US_KEYBOARD
+/* US keyboard (as HID standard) */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x34, KEY_SHIFT}, /* " */
+ {0x20, KEY_SHIFT}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x1f, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x31, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x31, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x35, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+
+#else
+/* UK keyboard */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x1f, KEY_SHIFT}, /* " */
+ {0x32, 0}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x34, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x64, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x64, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x32, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+#endif
+
+
+uint8_t * USBMouseKeyboard::reportDesc() {
+ if (mouse_type == REL_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+ // Keyboard
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x06,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08,
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01,
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(2), 0xff, 0x00,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(2), 0xff, 0x00,
+ INPUT(1), 0x00,
+ END_COLLECTION(0),
+
+ // Mouse
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+ REPORT_ID(1), REPORT_ID_MOUSE,
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x1,
+ USAGE_MAXIMUM(1), 0x3,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x08,
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81,
+ LOGICAL_MAXIMUM(1), 0x7f,
+ INPUT(1), 0x06,
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ } else if (mouse_type == ABS_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+
+ // Keyboard
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x06,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08,
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01,
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(2), 0xff, 0x00,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(2), 0xff, 0x00,
+ INPUT(1), 0x00,
+ END_COLLECTION(0),
+
+ // Mouse
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+ REPORT_ID(1), REPORT_ID_MOUSE,
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(2), 0xff, 0x7f, // 32767
+ REPORT_SIZE(1), 0x10,
+ REPORT_COUNT(1), 0x02,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81, // -127
+ LOGICAL_MAXIMUM(1), 0x7f, // 127
+ REPORT_SIZE(1), 0x08,
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x06, // Data, Variable, Relative
+
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x03,
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(1), 0x01, // 1
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01, // Constant
+
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ }
+
+ return NULL;
+}
+
+bool USBMouseKeyboard::EPINT_OUT_callback() {
+ uint32_t bytesRead = 0;
+ uint8_t led[65];
+ USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE);
+
+ // we take led[1] because led[0] is the report ID
+ lock_status = led[1] & 0x07;
+
+ // We activate the endpoint to be able to recceive data
+ if (!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+uint8_t USBMouseKeyboard::lockStatus() {
+ return lock_status;
+}
+
+bool USBMouseKeyboard::update(int16_t x, int16_t y, uint8_t button, int8_t z) {
+ switch (mouse_type) {
+ case REL_MOUSE:
+ while (x > 127) {
+ if (!mouseSend(127, 0, button, z)) return false;
+ x = x - 127;
+ }
+ while (x < -128) {
+ if (!mouseSend(-128, 0, button, z)) return false;
+ x = x + 128;
+ }
+ while (y > 127) {
+ if (!mouseSend(0, 127, button, z)) return false;
+ y = y - 127;
+ }
+ while (y < -128) {
+ if (!mouseSend(0, -128, button, z)) return false;
+ y = y + 128;
+ }
+ return mouseSend(x, y, button, z);
+ case ABS_MOUSE:
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_MOUSE;
+ report.data[1] = x & 0xff;
+ report.data[2] = (x >> 8) & 0xff;
+ report.data[3] = y & 0xff;
+ report.data[4] = (y >> 8) & 0xff;
+ report.data[5] = -z;
+ report.data[6] = button & 0x07;
+
+ report.length = 7;
+
+ return send(&report);
+ default:
+ return false;
+ }
+}
+
+bool USBMouseKeyboard::mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z) {
+ HID_REPORT report;
+ report.data[0] = REPORT_ID_MOUSE;
+ report.data[1] = buttons & 0x07;
+ report.data[2] = x;
+ report.data[3] = y;
+ report.data[4] = -z; // >0 to scroll down, <0 to scroll up
+
+ report.length = 5;
+
+ return send(&report);
+}
+
+bool USBMouseKeyboard::move(int16_t x, int16_t y) {
+ return update(x, y, button, 0);
+}
+
+bool USBMouseKeyboard::scroll(int8_t z) {
+ return update(0, 0, button, z);
+}
+
+bool USBMouseKeyboard::doubleClick() {
+ if (!click(MOUSE_LEFT))
+ return false;
+ wait(0.1);
+ return click(MOUSE_LEFT);
+}
+
+bool USBMouseKeyboard::click(uint8_t button) {
+ if (!update(0, 0, button, 0))
+ return false;
+ wait(0.01);
+ return update(0, 0, 0, 0);
+}
+
+bool USBMouseKeyboard::press(uint8_t button_) {
+ button = button_ & 0x07;
+ return update(0, 0, button, 0);
+}
+
+bool USBMouseKeyboard::release(uint8_t button_) {
+ button = (button & (~button_)) & 0x07;
+ return update(0, 0, button, 0);
+}
+
+int USBMouseKeyboard::_putc(int c) {
+ return keyCode(c, keymap[c].modifier);
+}
+
+bool USBMouseKeyboard::keyCode(uint8_t key, uint8_t modifier) {
+ // Send a simulated keyboard keypress. Returns true if successful.
+
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_KEYBOARD;
+ report.data[1] = modifier;
+ report.data[2] = 0;
+ report.data[3] = keymap[key].usage;
+ report.data[4] = 0;
+ report.data[5] = 0;
+ report.data[6] = 0;
+ report.data[7] = 0;
+ report.data[8] = 0;
+
+ report.length = 9;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[1] = 0;
+ report.data[3] = 0;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ return true;
+
+}
+
+
+bool USBMouseKeyboard::mediaControl(MEDIA_KEY key) {
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = (1 << key) & 0x7f;
+
+ report.length = 2;
+
+ send(&report);
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = 0;
+
+ report.length = 2;
+
+ return send(&report);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h
new file mode 100644
index 000000000..1b19b10db
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h
@@ -0,0 +1,220 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMOUSEKEYBOARD_H
+#define USBMOUSEKEYBOARD_H
+
+#define REPORT_ID_KEYBOARD 1
+#define REPORT_ID_MOUSE 2
+#define REPORT_ID_VOLUME 3
+
+#include "USBMouse.h"
+#include "USBKeyboard.h"
+#include "Stream.h"
+#include "USBHID.h"
+
+/**
+ * USBMouseKeyboard example
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBMouseKeyboard.h"
+ *
+ * USBMouseKeyboard key_mouse;
+ *
+ * int main(void)
+ * {
+ * while(1)
+ * {
+ * key_mouse.move(20, 0);
+ * key_mouse.printf("Hello From MBED\r\n");
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ *
+ *
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBMouseKeyboard.h"
+ *
+ * USBMouseKeyboard key_mouse(ABS_MOUSE);
+ *
+ * int main(void)
+ * {
+ * while(1)
+ * {
+ * key_mouse.move(X_MAX_ABS/2, Y_MAX_ABS/2);
+ * key_mouse.printf("Hello from MBED\r\n");
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class USBMouseKeyboard: public USBHID, public Stream
+{
+ public:
+
+ /**
+ * Constructor
+ *
+ * @param mouse_type Mouse type: ABS_MOUSE (absolute mouse) or REL_MOUSE (relative mouse) (default: REL_MOUSE)
+ * @param leds Leds bus: first: NUM_LOCK, second: CAPS_LOCK, third: SCROLL_LOCK
+ * @param vendor_id Your vendor_id (default: 0x1234)
+ * @param product_id Your product_id (default: 0x0001)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBMouseKeyboard(MOUSE_TYPE mouse_type = REL_MOUSE, uint16_t vendor_id = 0x0021, uint16_t product_id = 0x0011, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false)
+ {
+ lock_status = 0;
+ button = 0;
+ this->mouse_type = mouse_type;
+ connect();
+ };
+
+ /**
+ * Write a state of the mouse
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @param buttons buttons state (first bit represents MOUSE_LEFT, second bit MOUSE_RIGHT and third bit MOUSE_MIDDLE)
+ * @param z wheel state (>0 to scroll down, <0 to scroll up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool update(int16_t x, int16_t y, uint8_t buttons, int8_t z);
+
+
+ /**
+ * Move the cursor to (x, y)
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @returns true if there is no error, false otherwise
+ */
+ bool move(int16_t x, int16_t y);
+
+ /**
+ * Press one or several buttons
+ *
+ * @param button button state (ex: press(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool press(uint8_t button);
+
+ /**
+ * Release one or several buttons
+ *
+ * @param button button state (ex: release(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool release(uint8_t button);
+
+ /**
+ * Double click (MOUSE_LEFT)
+ *
+ * @returns true if there is no error, false otherwise
+ */
+ bool doubleClick();
+
+ /**
+ * Click
+ *
+ * @param button state of the buttons ( ex: clic(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool click(uint8_t button);
+
+ /**
+ * Scrolling
+ *
+ * @param z value of the wheel (>0 to go down, <0 to go up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool scroll(int8_t z);
+
+ /**
+ * To send a character defined by a modifier(CTRL, SHIFT, ALT) and the key
+ *
+ * @code
+ * //To send CTRL + s (save)
+ * keyboard.keyCode('s', KEY_CTRL);
+ * @endcode
+ *
+ * @param modifier bit 0: KEY_CTRL, bit 1: KEY_SHIFT, bit 2: KEY_ALT (default: 0)
+ * @param key character to send
+ * @returns true if there is no error, false otherwise
+ */
+ bool keyCode(uint8_t key, uint8_t modifier = 0);
+
+ /**
+ * Send a character
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Control media keys
+ *
+ * @param key media key pressed (KEY_NEXT_TRACK, KEY_PREVIOUS_TRACK, KEY_STOP, KEY_PLAY_PAUSE, KEY_MUTE, KEY_VOLUME_UP, KEY_VOLUME_DOWN)
+ * @returns true if there is no error, false otherwise
+ */
+ bool mediaControl(MEDIA_KEY key);
+
+ /**
+ * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important:
+ * - First bit: NUM_LOCK
+ * - Second bit: CAPS_LOCK
+ * - Third bit: SCROLL_LOCK
+ *
+ * @returns status of lock keys
+ */
+ uint8_t lockStatus();
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys
+ *
+ * @returns if handle by subclass, return true
+ */
+ virtual bool EPINT_OUT_callback();
+
+
+ private:
+ bool mouseWrite(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+ MOUSE_TYPE mouse_type;
+ uint8_t button;
+ bool mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+
+ uint8_t lock_status;
+
+ //dummy otherwise it doesn't compile (we must define all methods of an abstract class)
+ virtual int _getc() { return -1;}
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h
new file mode 100644
index 000000000..9cfcf1363
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h
@@ -0,0 +1,276 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef MIDIMESSAGE_H
+#define MIDIMESSAGE_H
+
+#include "mbed.h"
+
+#define MAX_MIDI_MESSAGE_SIZE 256 // Max message size. SysEx can be up to 65536 but 256 should be fine for most usage
+
+// MIDI Message Format
+//
+// [ msg(4) | channel(4) ] [ 0 | n(7) ] [ 0 | m(7) ]
+//
+// MIDI Data Messages (Channel Specific)
+//
+// Message msg n m
+// ---------------------------------------------
+// Note Off 0x8 Key Velocity
+// Note On 0x9 Key Velocity
+// Polyphonic Aftertouch 0xA Key Pressure
+// Control Change 0xB Controller Value
+// Program Change 0xC Program -
+// Channel Aftertouch 0xD Pressure -
+// Pitch Wheel 0xE LSB MSB
+
+#define CABLE_NUM (0<<4)
+
+/** A MIDI message container */
+class MIDIMessage {
+public:
+ MIDIMessage() : length(4) {}
+
+ MIDIMessage(uint8_t *buf) : length(4) {
+ for (int i = 0; i < 4; i++)
+ data[i] = buf[i];
+ }
+
+ // New constructor, buf is a true MIDI message (not USBMidi message) and buf_len true message length.
+ MIDIMessage(uint8_t *buf, int buf_len) {
+ length=buf_len+1;
+ // first byte keeped for retro-compatibility
+ data[0]=0;
+
+ for (int i = 0; i < buf_len; i++)
+ data[i+1] = buf[i];
+ }
+
+ // create messages
+
+ /** Create a NoteOff message
+ * @param key Key ID
+ * @param velocity Key velocity (0-127, default = 127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage NoteOff(int key, int velocity = 127, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x08;
+ msg.data[1] = 0x80 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = velocity & 0x7F;
+ return msg;
+ }
+
+ /** Create a NoteOn message
+ * @param key Key ID
+ * @param velocity Key velocity (0-127, default = 127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage NoteOn(int key, int velocity = 127, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x09;
+ msg.data[1] = 0x90 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = velocity & 0x7F;
+ return msg;
+ }
+
+ /** Create a PolyPhonic Aftertouch message
+ * @param key Key ID
+ * @param pressure Aftertouch pressure (0-127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage PolyphonicAftertouch(int key, int pressure, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0A;
+ msg.data[1] = 0xA0 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = pressure & 0x7F;
+ return msg;
+ }
+
+ /** Create a Control Change message
+ * @param control Controller ID
+ * @param value Controller value (0-127)
+ * @param channel Controller channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ControlChange(int control, int value, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0B;
+ msg.data[1] = 0xB0 | (channel & 0x0F);
+ msg.data[2] = control & 0x7F;
+ msg.data[3] = value & 0x7F;
+ return msg;
+ }
+
+ /** Create a Program Change message
+ * @param program Program ID
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ProgramChange(int program, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0C;
+ msg.data[1] = 0xC0 | (channel & 0x0F);
+ msg.data[2] = program & 0x7F;
+ msg.data[3] = 0x00;
+ return msg;
+ }
+
+ /** Create a Channel Aftertouch message
+ * @param pressure Pressure
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ChannelAftertouch(int pressure, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0D;
+ msg.data[1] = 0xD0 | (channel & 0x0F);
+ msg.data[2] = pressure & 0x7F;
+ msg.data[3] = 0x00;
+ return msg;
+ }
+
+ /** Create a Pitch Wheel message
+ * @param pitch Pitch (-8192 - 8191, default = 0)
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage PitchWheel(int pitch = 0, int channel = 0) {
+ MIDIMessage msg;
+ int p = pitch + 8192; // 0 - 16383, 8192 is center
+ msg.data[0] = CABLE_NUM | 0x0E;
+ msg.data[1] = 0xE0 | (channel & 0x0F);
+ msg.data[2] = p & 0x7F;
+ msg.data[3] = (p >> 7) & 0x7F;
+ return msg;
+ }
+
+ /** Create an All Notes Off message
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage AllNotesOff(int channel = 0) {
+ return ControlChange(123, 0, channel);
+ }
+
+ /** Create a SysEx message
+ * @param data SysEx data (including 0xF0 .. 0xF7)
+ * @param len SysEx data length
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage SysEx(uint8_t *data, int len) {
+ MIDIMessage msg=MIDIMessage(data,len);
+ return msg;
+ }
+
+ // decode messages
+
+ /** MIDI Message Types */
+ enum MIDIMessageType {
+ ErrorType,
+ NoteOffType,
+ NoteOnType,
+ PolyphonicAftertouchType,
+ ControlChangeType,
+ ProgramChangeType,
+ ChannelAftertouchType,
+ PitchWheelType,
+ AllNotesOffType,
+ SysExType
+ };
+
+ /** Read the message type
+ * @returns MIDIMessageType
+ */
+ MIDIMessageType type() {
+ switch((data[1] >> 4) & 0xF) {
+ case 0x8: return NoteOffType;
+ case 0x9: return NoteOnType;
+ case 0xA: return PolyphonicAftertouchType;
+ case 0xB:
+ if(controller() < 120) { // standard controllers
+ return ControlChangeType;
+ } else if(controller() == 123) {
+ return AllNotesOffType;
+ } else {
+ return ErrorType; // unsupported atm
+ }
+ case 0xC: return ProgramChangeType;
+ case 0xD: return ChannelAftertouchType;
+ case 0xE: return PitchWheelType;
+ case 0xF: return SysExType;
+ default: return ErrorType;
+ }
+ }
+
+ /** Read the channel number */
+ int channel() {
+ return (data[1] & 0x0F);
+ }
+
+ /** Read the key ID */
+ int key() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the velocity */
+ int velocity() {
+ return (data[3] & 0x7F);
+ }
+
+ /** Read the controller value */
+ int value() {
+ return (data[3] & 0x7F);
+ }
+
+ /** Read the aftertouch pressure */
+ int pressure() {
+ if(type() == PolyphonicAftertouchType) {
+ return (data[3] & 0x7F);
+ } else {
+ return (data[2] & 0x7F);
+ }
+ }
+
+ /** Read the controller number */
+ int controller() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the program number */
+ int program() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the pitch value */
+ int pitch() {
+ int p = ((data[3] & 0x7F) << 7) | (data[2] & 0x7F);
+ return p - 8192; // 0 - 16383, 8192 is center
+ }
+
+ uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+ uint8_t length;
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp
new file mode 100644
index 000000000..084574a79
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp
@@ -0,0 +1,207 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMIDI.h"
+
+
+USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release)
+ : USBDevice(vendor_id, product_id, product_release), cur_data(0), data_end(true)
+{
+ midi_evt = NULL;
+ USBDevice::connect();
+}
+
+// write plain MIDIMessage that will be converted to USBMidi event packet
+void USBMIDI::write(MIDIMessage m) {
+ // first byte keeped for retro-compatibility
+ for(int p=1; p < m.length; p+=3) {
+ uint8_t buf[4];
+ // Midi message to USBMidi event packet
+ buf[0]=m.data[1] >> 4;
+ // SysEx
+ if(buf[0] == 0xF) {
+ if((m.length - p) > 3) {
+ // SysEx start or continue
+ buf[0]=0x4;
+ } else {
+ switch(m.length - p) {
+ case 1:
+ // SysEx end with one byte
+ buf[0]=0x5;
+ break;
+ case 2:
+ // SysEx end with two bytes
+ buf[0]=0x6;
+ break;
+ case 3:
+ // SysEx end with three bytes
+ buf[0]=0x7;
+ break;
+ }
+ }
+ }
+ buf[1]=m.data[p];
+
+ if(p+1 < m.length)
+ buf[2]=m.data[p+1];
+ else
+ buf[2]=0;
+
+ if(p+2 < m.length)
+ buf[3]=m.data[p+2];
+ else
+ buf[3]=0;
+
+ USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK);
+ }
+}
+
+
+void USBMIDI::attach(void (*fptr)(MIDIMessage)) {
+ midi_evt = fptr;
+}
+
+bool USBMIDI::EPBULK_OUT_callback() {
+ uint8_t buf[64];
+ uint32_t len;
+ readEP(EPBULK_OUT, buf, &len, 64);
+
+ if (midi_evt != NULL) {
+ for (uint32_t i=0; i<len; i+=4) {
+ uint8_t data_read;
+ data_end=true;
+ switch(buf[i]) {
+ case 0x2:
+ // Two-bytes System Common Message - undefined in USBMidi 1.0
+ data_read=2;
+ break;
+ case 0x4:
+ // SysEx start or continue
+ data_end=false;
+ data_read=3;
+ break;
+ case 0x5:
+ // Single-byte System Common Message or SysEx end with one byte
+ data_read=1;
+ break;
+ case 0x6:
+ // SysEx end with two bytes
+ data_read=2;
+ break;
+ case 0xC:
+ // Program change
+ data_read=2;
+ break;
+ case 0xD:
+ // Channel pressure
+ data_read=2;
+ break;
+ case 0xF:
+ // Single byte
+ data_read=1;
+ break;
+ default:
+ // Others three-bytes messages
+ data_read=3;
+ break;
+ }
+
+ for(uint8_t j=1;j<data_read+1;j++) {
+ data[cur_data]=buf[i+j];
+ cur_data++;
+ }
+
+ if(data_end) {
+ midi_evt(MIDIMessage(data,cur_data));
+ cur_data=0;
+ }
+ }
+ }
+
+ // We reactivate the endpoint to receive next characters
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBMIDI::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ // We activate the endpoint to be able to receive data
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+
+uint8_t * USBMIDI::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x0c, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBMIDI::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
+
+
+uint8_t * USBMIDI::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // configuration descriptor
+ 0x09, 0x02, 0x65, 0x00, 0x02, 0x01, 0x00, 0xc0, 0x50,
+
+ // The Audio Interface Collection
+ 0x09, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // Standard AC Interface Descriptor
+ 0x09, 0x24, 0x01, 0x00, 0x01, 0x09, 0x00, 0x01, 0x01, // Class-specific AC Interface Descriptor
+ 0x09, 0x04, 0x01, 0x00, 0x02, 0x01, 0x03, 0x00, 0x00, // MIDIStreaming Interface Descriptors
+ 0x07, 0x24, 0x01, 0x00, 0x01, 0x41, 0x00, // Class-Specific MS Interface Header Descriptor
+
+ // MIDI IN JACKS
+ 0x06, 0x24, 0x02, 0x01, 0x01, 0x00,
+ 0x06, 0x24, 0x02, 0x02, 0x02, 0x00,
+
+ // MIDI OUT JACKS
+ 0x09, 0x24, 0x03, 0x01, 0x03, 0x01, 0x02, 0x01, 0x00,
+ 0x09, 0x24, 0x03, 0x02, 0x06, 0x01, 0x01, 0x01, 0x00,
+
+ // OUT endpoint descriptor
+ 0x09, 0x05, 0x02, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x25, 0x01, 0x01, 0x01,
+
+ // IN endpoint descriptor
+ 0x09, 0x05, 0x82, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x25, 0x01, 0x01, 0x03,
+ };
+ return configDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h
new file mode 100644
index 000000000..cc5be5b7d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMIDI_H
+#define USBMIDI_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+#include "MIDIMessage.h"
+
+#define DEFAULT_CONFIGURATION (1)
+
+/**
+* USBMIDI example
+*
+* @code
+* #include "mbed.h"
+* #include "USBMIDI.h"
+*
+* USBMIDI midi;
+*
+* int main() {
+* while (1) {
+* for(int i=48; i<83; i++) { // send some messages!
+* midi.write(MIDIMessage::NoteOn(i));
+* wait(0.25);
+* midi.write(MIDIMessage::NoteOff(i));
+* wait(0.5);
+* }
+* }
+* }
+* @endcode
+*/
+class USBMIDI: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBMIDI(uint16_t vendor_id = 0x0700, uint16_t product_id = 0x0101, uint16_t product_release = 0x0001);
+
+ /**
+ * Send a MIDIMessage
+ *
+ * @param m The MIDIMessage to send
+ */
+ void write(MIDIMessage m);
+
+ /**
+ * Attach a callback for when a MIDIEvent is received
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(MIDIMessage));
+
+
+protected:
+ virtual bool EPBULK_OUT_callback();
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+private:
+ uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+ uint8_t cur_data;
+ bool data_end;
+
+ void (*midi_evt)(MIDIMessage);
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp
new file mode 100644
index 000000000..ee5ad2473
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp
@@ -0,0 +1,655 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMSD.h"
+
+#define DISK_OK 0x00
+#define NO_INIT 0x01
+#define NO_DISK 0x02
+#define WRITE_PROTECT 0x04
+
+#define CBW_Signature 0x43425355
+#define CSW_Signature 0x53425355
+
+// SCSI Commands
+#define TEST_UNIT_READY 0x00
+#define REQUEST_SENSE 0x03
+#define FORMAT_UNIT 0x04
+#define INQUIRY 0x12
+#define MODE_SELECT6 0x15
+#define MODE_SENSE6 0x1A
+#define START_STOP_UNIT 0x1B
+#define MEDIA_REMOVAL 0x1E
+#define READ_FORMAT_CAPACITIES 0x23
+#define READ_CAPACITY 0x25
+#define READ10 0x28
+#define WRITE10 0x2A
+#define VERIFY10 0x2F
+#define READ12 0xA8
+#define WRITE12 0xAA
+#define MODE_SELECT10 0x55
+#define MODE_SENSE10 0x5A
+
+// MSC class specific requests
+#define MSC_REQUEST_RESET 0xFF
+#define MSC_REQUEST_GET_MAX_LUN 0xFE
+
+#define DEFAULT_CONFIGURATION (1)
+
+// max packet size
+#define MAX_PACKET MAX_PACKET_SIZE_EPBULK
+
+// CSW Status
+enum Status {
+ CSW_PASSED,
+ CSW_FAILED,
+ CSW_ERROR,
+};
+
+
+USBMSD::USBMSD(uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) {
+ stage = READ_CBW;
+ memset((void *)&cbw, 0, sizeof(CBW));
+ memset((void *)&csw, 0, sizeof(CSW));
+ page = NULL;
+}
+
+USBMSD::~USBMSD() {
+ disconnect();
+}
+
+
+// Called in ISR context to process a class specific request
+bool USBMSD::USBCallback_request(void) {
+
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ static uint8_t maxLUN[1] = {0};
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ switch (transfer->setup.bRequest) {
+ case MSC_REQUEST_RESET:
+ reset();
+ success = true;
+ break;
+ case MSC_REQUEST_GET_MAX_LUN:
+ transfer->remaining = 1;
+ transfer->ptr = maxLUN;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+
+bool USBMSD::connect(bool blocking) {
+ //disk initialization
+ if (disk_status() & NO_INIT) {
+ if (disk_initialize()) {
+ return false;
+ }
+ }
+
+ // get number of blocks
+ BlockCount = disk_sectors();
+
+ // get memory size
+ MemorySize = disk_size();
+
+ if (BlockCount > 0) {
+ BlockSize = MemorySize / BlockCount;
+ if (BlockSize != 0) {
+ free(page);
+ page = (uint8_t *)malloc(BlockSize * sizeof(uint8_t));
+ if (page == NULL)
+ return false;
+ }
+ } else {
+ return false;
+ }
+
+ //connect the device
+ USBDevice::connect(blocking);
+ return true;
+}
+
+void USBMSD::disconnect() {
+ USBDevice::disconnect();
+ //De-allocate MSD page size:
+ free(page);
+ page = NULL;
+}
+
+void USBMSD::reset() {
+ stage = READ_CBW;
+}
+
+
+// Called in ISR context called when a data is received
+bool USBMSD::EPBULK_OUT_callback() {
+ uint32_t size = 0;
+ uint8_t buf[MAX_PACKET_SIZE_EPBULK];
+ readEP(EPBULK_OUT, buf, &size, MAX_PACKET_SIZE_EPBULK);
+ switch (stage) {
+ // the device has to decode the CBW received
+ case READ_CBW:
+ CBWDecode(buf, size);
+ break;
+
+ // the device has to receive data from the host
+ case PROCESS_CBW:
+ switch (cbw.CB[0]) {
+ case WRITE10:
+ case WRITE12:
+ memoryWrite(buf, size);
+ break;
+ case VERIFY10:
+ memoryVerify(buf, size);
+ break;
+ }
+ break;
+
+ // an error has occured: stall endpoint and send CSW
+ default:
+ stallEndpoint(EPBULK_OUT);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ break;
+ }
+
+ //reactivate readings on the OUT bulk endpoint
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+// Called in ISR context when a data has been transferred
+bool USBMSD::EPBULK_IN_callback() {
+ switch (stage) {
+
+ // the device has to send data to the host
+ case PROCESS_CBW:
+ switch (cbw.CB[0]) {
+ case READ10:
+ case READ12:
+ memoryRead();
+ break;
+ }
+ break;
+
+ //the device has to send a CSW
+ case SEND_CSW:
+ sendCSW();
+ break;
+
+ // the host has received the CSW -> we wait a CBW
+ case WAIT_CSW:
+ stage = READ_CBW;
+ break;
+
+ // an error has occured
+ default:
+ stallEndpoint(EPBULK_IN);
+ sendCSW();
+ break;
+ }
+ return true;
+}
+
+
+void USBMSD::memoryWrite (uint8_t * buf, uint16_t size) {
+
+ if ((addr + size) > MemorySize) {
+ size = MemorySize - addr;
+ stage = ERROR;
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ // we fill an array in RAM of 1 block before writing it in memory
+ for (int i = 0; i < size; i++)
+ page[addr%BlockSize + i] = buf[i];
+
+ // if the array is filled, write it in memory
+ if (!((addr + size)%BlockSize)) {
+ if (!(disk_status() & WRITE_PROTECT)) {
+ disk_write(page, addr/BlockSize, 1);
+ }
+ }
+
+ addr += size;
+ length -= size;
+ csw.DataResidue -= size;
+
+ if ((!length) || (stage != PROCESS_CBW)) {
+ csw.Status = (stage == ERROR) ? CSW_FAILED : CSW_PASSED;
+ sendCSW();
+ }
+}
+
+void USBMSD::memoryVerify (uint8_t * buf, uint16_t size) {
+ uint32_t n;
+
+ if ((addr + size) > MemorySize) {
+ size = MemorySize - addr;
+ stage = ERROR;
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ // beginning of a new block -> load a whole block in RAM
+ if (!(addr%BlockSize))
+ disk_read(page, addr/BlockSize, 1);
+
+ // info are in RAM -> no need to re-read memory
+ for (n = 0; n < size; n++) {
+ if (page[addr%BlockSize + n] != buf[n]) {
+ memOK = false;
+ break;
+ }
+ }
+
+ addr += size;
+ length -= size;
+ csw.DataResidue -= size;
+
+ if ( !length || (stage != PROCESS_CBW)) {
+ csw.Status = (memOK && (stage == PROCESS_CBW)) ? CSW_PASSED : CSW_FAILED;
+ sendCSW();
+ }
+}
+
+
+bool USBMSD::inquiryRequest (void) {
+ uint8_t inquiry[] = { 0x00, 0x80, 0x00, 0x01,
+ 36 - 4, 0x80, 0x00, 0x00,
+ 'M', 'B', 'E', 'D', '.', 'O', 'R', 'G',
+ 'M', 'B', 'E', 'D', ' ', 'U', 'S', 'B', ' ', 'D', 'I', 'S', 'K', ' ', ' ', ' ',
+ '1', '.', '0', ' ',
+ };
+ if (!write(inquiry, sizeof(inquiry))) {
+ return false;
+ }
+ return true;
+}
+
+
+bool USBMSD::readFormatCapacity() {
+ uint8_t capacity[] = { 0x00, 0x00, 0x00, 0x08,
+ (uint8_t)((BlockCount >> 24) & 0xff),
+ (uint8_t)((BlockCount >> 16) & 0xff),
+ (uint8_t)((BlockCount >> 8) & 0xff),
+ (uint8_t)((BlockCount >> 0) & 0xff),
+
+ 0x02,
+ (uint8_t)((BlockSize >> 16) & 0xff),
+ (uint8_t)((BlockSize >> 8) & 0xff),
+ (uint8_t)((BlockSize >> 0) & 0xff),
+ };
+ if (!write(capacity, sizeof(capacity))) {
+ return false;
+ }
+ return true;
+}
+
+
+bool USBMSD::readCapacity (void) {
+ uint8_t capacity[] = {
+ (uint8_t)(((BlockCount - 1) >> 24) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 16) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 8) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 0) & 0xff),
+
+ (uint8_t)((BlockSize >> 24) & 0xff),
+ (uint8_t)((BlockSize >> 16) & 0xff),
+ (uint8_t)((BlockSize >> 8) & 0xff),
+ (uint8_t)((BlockSize >> 0) & 0xff),
+ };
+ if (!write(capacity, sizeof(capacity))) {
+ return false;
+ }
+ return true;
+}
+
+bool USBMSD::write (uint8_t * buf, uint16_t size) {
+
+ if (size >= cbw.DataLength) {
+ size = cbw.DataLength;
+ }
+ stage = SEND_CSW;
+
+ if (!writeNB(EPBULK_IN, buf, size, MAX_PACKET_SIZE_EPBULK)) {
+ return false;
+ }
+
+ csw.DataResidue -= size;
+ csw.Status = CSW_PASSED;
+ return true;
+}
+
+
+bool USBMSD::modeSense6 (void) {
+ uint8_t sense6[] = { 0x03, 0x00, 0x00, 0x00 };
+ if (!write(sense6, sizeof(sense6))) {
+ return false;
+ }
+ return true;
+}
+
+void USBMSD::sendCSW() {
+ csw.Signature = CSW_Signature;
+ writeNB(EPBULK_IN, (uint8_t *)&csw, sizeof(CSW), MAX_PACKET_SIZE_EPBULK);
+ stage = WAIT_CSW;
+}
+
+bool USBMSD::requestSense (void) {
+ uint8_t request_sense[] = {
+ 0x70,
+ 0x00,
+ 0x05, // Sense Key: illegal request
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x0A,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x30,
+ 0x01,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ };
+
+ if (!write(request_sense, sizeof(request_sense))) {
+ return false;
+ }
+
+ return true;
+}
+
+void USBMSD::fail() {
+ csw.Status = CSW_FAILED;
+ sendCSW();
+}
+
+
+void USBMSD::CBWDecode(uint8_t * buf, uint16_t size) {
+ if (size == sizeof(cbw)) {
+ memcpy((uint8_t *)&cbw, buf, size);
+ if (cbw.Signature == CBW_Signature) {
+ csw.Tag = cbw.Tag;
+ csw.DataResidue = cbw.DataLength;
+ if ((cbw.CBLength < 1) || (cbw.CBLength > 16) ) {
+ fail();
+ } else {
+ switch (cbw.CB[0]) {
+ case TEST_UNIT_READY:
+ testUnitReady();
+ break;
+ case REQUEST_SENSE:
+ requestSense();
+ break;
+ case INQUIRY:
+ inquiryRequest();
+ break;
+ case MODE_SENSE6:
+ modeSense6();
+ break;
+ case READ_FORMAT_CAPACITIES:
+ readFormatCapacity();
+ break;
+ case READ_CAPACITY:
+ readCapacity();
+ break;
+ case READ10:
+ case READ12:
+ if (infoTransfer()) {
+ if ((cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ memoryRead();
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case WRITE10:
+ case WRITE12:
+ if (infoTransfer()) {
+ if (!(cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ } else {
+ stallEndpoint(EPBULK_IN);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case VERIFY10:
+ if (!(cbw.CB[1] & 0x02)) {
+ csw.Status = CSW_PASSED;
+ sendCSW();
+ break;
+ }
+ if (infoTransfer()) {
+ if (!(cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ memOK = true;
+ } else {
+ stallEndpoint(EPBULK_IN);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case MEDIA_REMOVAL:
+ csw.Status = CSW_PASSED;
+ sendCSW();
+ break;
+ default:
+ fail();
+ break;
+ }
+ }
+ }
+ }
+}
+
+void USBMSD::testUnitReady (void) {
+
+ if (cbw.DataLength != 0) {
+ if ((cbw.Flags & 0x80) != 0) {
+ stallEndpoint(EPBULK_IN);
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ }
+ }
+
+ csw.Status = CSW_PASSED;
+ sendCSW();
+}
+
+
+void USBMSD::memoryRead (void) {
+ uint32_t n;
+
+ n = (length > MAX_PACKET) ? MAX_PACKET : length;
+
+ if ((addr + n) > MemorySize) {
+ n = MemorySize - addr;
+ stage = ERROR;
+ }
+
+ // we read an entire block
+ if (!(addr%BlockSize))
+ disk_read(page, addr/BlockSize, 1);
+
+ // write data which are in RAM
+ writeNB(EPBULK_IN, &page[addr%BlockSize], n, MAX_PACKET_SIZE_EPBULK);
+
+ addr += n;
+ length -= n;
+
+ csw.DataResidue -= n;
+
+ if ( !length || (stage != PROCESS_CBW)) {
+ csw.Status = (stage == PROCESS_CBW) ? CSW_PASSED : CSW_FAILED;
+ stage = (stage == PROCESS_CBW) ? SEND_CSW : stage;
+ }
+}
+
+
+bool USBMSD::infoTransfer (void) {
+ uint32_t n;
+
+ // Logical Block Address of First Block
+ n = (cbw.CB[2] << 24) | (cbw.CB[3] << 16) | (cbw.CB[4] << 8) | (cbw.CB[5] << 0);
+
+ addr = n * BlockSize;
+
+ // Number of Blocks to transfer
+ switch (cbw.CB[0]) {
+ case READ10:
+ case WRITE10:
+ case VERIFY10:
+ n = (cbw.CB[7] << 8) | (cbw.CB[8] << 0);
+ break;
+
+ case READ12:
+ case WRITE12:
+ n = (cbw.CB[6] << 24) | (cbw.CB[7] << 16) | (cbw.CB[8] << 8) | (cbw.CB[9] << 0);
+ break;
+ }
+
+ length = n * BlockSize;
+
+ if (!cbw.DataLength) { // host requests no data
+ csw.Status = CSW_FAILED;
+ sendCSW();
+ return false;
+ }
+
+ if (cbw.DataLength != length) {
+ if ((cbw.Flags & 0x80) != 0) {
+ stallEndpoint(EPBULK_IN);
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ csw.Status = CSW_FAILED;
+ sendCSW();
+ return false;
+ }
+
+ return true;
+}
+
+
+
+
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBMSD::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ //activate readings
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+
+uint8_t * USBMSD::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'S',0,'D',0 //bString iInterface - MSD
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBMSD::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x12, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'M',0,'S',0,'D',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
+
+
+uint8_t * USBMSD::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+
+ // Configuration 1
+ 9, // bLength
+ 2, // bDescriptorType
+ LSB(9 + 9 + 7 + 7), // wTotalLength
+ MSB(9 + 9 + 7 + 7),
+ 0x01, // bNumInterfaces
+ 0x01, // bConfigurationValue: 0x01 is used to select this configuration
+ 0x00, // iConfiguration: no string to describe this configuration
+ 0xC0, // bmAttributes
+ 100, // bMaxPower, device power consumption is 100 mA
+
+ // Interface 0, Alternate Setting 0, MSC Class
+ 9, // bLength
+ 4, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ 0x08, // bInterfaceClass
+ 0x06, // bInterfaceSubClass
+ 0x50, // bInterfaceProtocol
+ 0x04, // iInterface
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ 7, // bLength
+ 5, // bDescriptorType
+ PHY_TO_DESC(EPBULK_IN), // bEndpointAddress
+ 0x02, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0, // bInterval
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ 7, // bLength
+ 5, // bDescriptorType
+ PHY_TO_DESC(EPBULK_OUT), // bEndpointAddress
+ 0x02, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0 // bInterval
+ };
+ return configDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h
new file mode 100644
index 000000000..ff750026c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h
@@ -0,0 +1,251 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#ifndef USBMSD_H
+#define USBMSD_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+/**
+ * USBMSD class: generic class in order to use all kinds of blocks storage chip
+ *
+ * Introduction
+ *
+ * The USBMSD implements the MSD protocol. It permits to access a memory chip (flash, sdcard,...)
+ * from a computer over USB. But this class doesn't work standalone, you need to subclass this class
+ * and define virtual functions which are called in USBMSD.
+ *
+ * How to use this class with your chip ?
+ *
+ * You have to inherit and define some pure virtual functions (mandatory step):
+ * - virtual int disk_read(char * data, int block): function to read a block
+ * - virtual int disk_write(const char * data, int block): function to write a block
+ * - virtual int disk_initialize(): function to initialize the memory
+ * - virtual int disk_sectors(): return the number of blocks
+ * - virtual int disk_size(): return the memory size
+ * - virtual int disk_status(): return the status of the storage chip (0: OK, 1: not initialized, 2: no medium in the drive, 4: write protection)
+ *
+ * All functions names are compatible with the fat filesystem library. So you can imagine using your own class with
+ * USBMSD and the fat filesystem library in the same program. Just be careful because there are two different parts which
+ * will access the sd card. You can do a master/slave system using the disk_status method.
+ *
+ * Once these functions defined, you can call connect() (at the end of the constructor of your class for instance)
+ * of USBMSD to connect your mass storage device. connect() will first call disk_status() to test the status of the disk.
+ * If disk_status() returns 1 (disk not initialized), then disk_initialize() is called. After this step, connect() will collect information
+ * such as the number of blocks and the memory size.
+ */
+class USBMSD: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBMSD(uint16_t vendor_id = 0x0703, uint16_t product_id = 0x0104, uint16_t product_release = 0x0001);
+
+ /**
+ * Connect the USB MSD device. Establish disk initialization before really connect the device.
+ *
+ * @param blocking if not configured
+ * @returns true if successful
+ */
+ bool connect(bool blocking = true);
+
+ /**
+ * Disconnect the USB MSD device.
+ */
+ void disconnect();
+
+ /**
+ * Destructor
+ */
+ ~USBMSD();
+
+protected:
+
+ /*
+ * read one or more blocks on a storage chip
+ *
+ * @param data pointer where will be stored read data
+ * @param block starting block number
+ * @param count number of blocks to read
+ * @returns 0 if successful
+ */
+ virtual int disk_read(uint8_t* data, uint64_t block, uint8_t count) = 0;
+
+ /*
+ * write one or more blocks on a storage chip
+ *
+ * @param data data to write
+ * @param block starting block number
+ * @param count number of blocks to write
+ * @returns 0 if successful
+ */
+ virtual int disk_write(const uint8_t* data, uint64_t block, uint8_t count) = 0;
+
+ /*
+ * Disk initilization
+ */
+ virtual int disk_initialize() = 0;
+
+ /*
+ * Return the number of blocks
+ *
+ * @returns number of blocks
+ */
+ virtual uint64_t disk_sectors() = 0;
+
+ /*
+ * Return memory size
+ *
+ * @returns memory size
+ */
+ virtual uint64_t disk_size() = 0;
+
+
+ /*
+ * To check the status of the storage chip
+ *
+ * @returns status: 0: OK, 1: disk not initialized, 2: no medium in the drive, 4: write protected
+ */
+ virtual int disk_status() = 0;
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Callback called when a packet is received
+ */
+ virtual bool EPBULK_OUT_callback();
+
+ /*
+ * Callback called when a packet has been sent
+ */
+ virtual bool EPBULK_IN_callback();
+
+ /*
+ * Set configuration of device. Add endpoints
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+ /*
+ * Callback called to process class specific requests
+ */
+ virtual bool USBCallback_request();
+
+
+private:
+
+ // MSC Bulk-only Stage
+ enum Stage {
+ READ_CBW, // wait a CBW
+ ERROR, // error
+ PROCESS_CBW, // process a CBW request
+ SEND_CSW, // send a CSW
+ WAIT_CSW, // wait that a CSW has been effectively sent
+ };
+
+ // Bulk-only CBW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataLength;
+ uint8_t Flags;
+ uint8_t LUN;
+ uint8_t CBLength;
+ uint8_t CB[16];
+ } PACKED CBW;
+
+ // Bulk-only CSW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataResidue;
+ uint8_t Status;
+ } PACKED CSW;
+
+ //state of the bulk-only state machine
+ Stage stage;
+
+ // current CBW
+ CBW cbw;
+
+ // CSW which will be sent
+ CSW csw;
+
+ // addr where will be read or written data
+ uint32_t addr;
+
+ // length of a reading or writing
+ uint32_t length;
+
+ // memory OK (after a memoryVerify)
+ bool memOK;
+
+ // cache in RAM before writing in memory. Useful also to read a block.
+ uint8_t * page;
+
+ int BlockSize;
+ uint64_t MemorySize;
+ uint64_t BlockCount;
+
+ void CBWDecode(uint8_t * buf, uint16_t size);
+ void sendCSW (void);
+ bool inquiryRequest (void);
+ bool write (uint8_t * buf, uint16_t size);
+ bool readFormatCapacity();
+ bool readCapacity (void);
+ bool infoTransfer (void);
+ void memoryRead (void);
+ bool modeSense6 (void);
+ void testUnitReady (void);
+ bool requestSense (void);
+ void memoryVerify (uint8_t * buf, uint16_t size);
+ void memoryWrite (uint8_t * buf, uint16_t size);
+ void reset();
+ void fail();
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h
new file mode 100644
index 000000000..ea46bdfe6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef CIRCBUFFER_H
+#define CIRCBUFFER_H
+
+template <class T, int Size>
+class CircBuffer {
+public:
+ CircBuffer():write(0), read(0){}
+ bool isFull() {
+ return ((write + 1) % size == read);
+ };
+
+ bool isEmpty() {
+ return (read == write);
+ };
+
+ void queue(T k) {
+ if (isFull()) {
+ read++;
+ read %= size;
+ }
+ buf[write++] = k;
+ write %= size;
+ }
+
+ uint16_t available() {
+ return (write >= read) ? write - read : size - read + write;
+ };
+
+ bool dequeue(T * c) {
+ bool empty = isEmpty();
+ if (!empty) {
+ *c = buf[read++];
+ read %= size;
+ }
+ return(!empty);
+ };
+
+private:
+ volatile uint16_t write;
+ volatile uint16_t read;
+ static const int size = Size+1; //a modern optimizer should be able to remove this so it uses no ram.
+ T buf[Size];
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp
new file mode 100644
index 000000000..aa55541f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp
@@ -0,0 +1,286 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBCDC.h"
+
+static uint8_t cdc_line_coding[7]= {0x80, 0x25, 0x00, 0x00, 0x00, 0x00, 0x08};
+
+#define DEFAULT_CONFIGURATION (1)
+
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+
+// Control Line State bits
+#define CLS_DTR (1 << 0)
+#define CLS_RTS (1 << 1)
+
+#define MAX_CDC_REPORT_SIZE MAX_PACKET_SIZE_EPBULK
+
+USBCDC::USBCDC(uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect_blocking): USBDevice(vendor_id, product_id, product_release) {
+ terminal_connected = false;
+ USBDevice::connect(connect_blocking);
+}
+
+bool USBCDC::USBCallback_request(void) {
+ /* Called in ISR context */
+
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ /* Process class-specific requests */
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ switch (transfer->setup.bRequest) {
+ case CDC_GET_LINE_CODING:
+ transfer->remaining = 7;
+ transfer->ptr = cdc_line_coding;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case CDC_SET_LINE_CODING:
+ transfer->remaining = 7;
+ transfer->notify = true;
+ success = true;
+ break;
+ case CDC_SET_CONTROL_LINE_STATE:
+ if (transfer->setup.wValue & CLS_DTR) {
+ terminal_connected = true;
+ } else {
+ terminal_connected = false;
+ }
+ success = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+void USBCDC::USBCallback_requestCompleted(uint8_t *buf, uint32_t length) {
+ // Request of setting line coding has 7 bytes
+ if (length != 7) {
+ return;
+ }
+
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ /* Process class-specific requests */
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ if (transfer->setup.bRequest == CDC_SET_LINE_CODING) {
+ if (memcmp(cdc_line_coding, buf, 7)) {
+ memcpy(cdc_line_coding, buf, 7);
+
+ int baud = buf[0] + (buf[1] << 8)
+ + (buf[2] << 16) + (buf[3] << 24);
+ int stop = buf[4];
+ int bits = buf[6];
+ int parity = buf[5];
+
+ lineCodingChanged(baud, bits, parity, stop);
+ }
+ }
+ }
+}
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBCDC::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPINT_IN, MAX_PACKET_SIZE_EPINT);
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ // We activate the endpoint to be able to recceive data
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+bool USBCDC::send(uint8_t * buffer, uint32_t size) {
+ return USBDevice::write(EPBULK_IN, buffer, size, MAX_CDC_REPORT_SIZE);
+}
+
+bool USBCDC::readEP(uint8_t * buffer, uint32_t * size) {
+ if (!USBDevice::readEP(EPBULK_OUT, buffer, size, MAX_CDC_REPORT_SIZE))
+ return false;
+ if (!readStart(EPBULK_OUT, MAX_CDC_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+bool USBCDC::readEP_NB(uint8_t * buffer, uint32_t * size) {
+ if (!USBDevice::readEP_NB(EPBULK_OUT, buffer, size, MAX_CDC_REPORT_SIZE))
+ return false;
+ if (!readStart(EPBULK_OUT, MAX_CDC_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+
+uint8_t * USBCDC::deviceDesc() {
+ static uint8_t deviceDescriptor[] = {
+ 18, // bLength
+ 1, // bDescriptorType
+ 0x10, 0x01, // bcdUSB
+ 2, // bDeviceClass
+ 0, // bDeviceSubClass
+ 0, // bDeviceProtocol
+ MAX_PACKET_SIZE_EP0, // bMaxPacketSize0
+ (uint8_t)(LSB(VENDOR_ID)), (uint8_t)(MSB(VENDOR_ID)), // idVendor
+ (uint8_t)(LSB(PRODUCT_ID)), (uint8_t)(MSB(PRODUCT_ID)),// idProduct
+ 0x00, 0x01, // bcdDevice
+ 1, // iManufacturer
+ 2, // iProduct
+ 3, // iSerialNumber
+ 1 // bNumConfigurations
+ };
+ return deviceDescriptor;
+}
+
+uint8_t * USBCDC::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08,
+ STRING_DESCRIPTOR,
+ 'C',0,'D',0,'C',0,
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBCDC::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16,
+ STRING_DESCRIPTOR,
+ 'C',0,'D',0,'C',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0
+ };
+ return stringIproductDescriptor;
+}
+
+
+#define CONFIG1_DESC_SIZE (9+8+9+5+5+4+5+7+9+7+7)
+
+uint8_t * USBCDC::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // configuration descriptor
+ 9, // bLength
+ 2, // bDescriptorType
+ LSB(CONFIG1_DESC_SIZE), // wTotalLength
+ MSB(CONFIG1_DESC_SIZE),
+ 2, // bNumInterfaces
+ 1, // bConfigurationValue
+ 0, // iConfiguration
+ 0x80, // bmAttributes
+ 50, // bMaxPower
+
+ // IAD to associate the two CDC interfaces
+ 0x08, // bLength
+ 0x0b, // bDescriptorType
+ 0x00, // bFirstInterface
+ 0x02, // bInterfaceCount
+ 0x02, // bFunctionClass
+ 0x02, // bFunctionSubClass
+ 0, // bFunctionProtocol
+ 0, // iFunction
+
+ // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+ 9, // bLength
+ 4, // bDescriptorType
+ 0, // bInterfaceNumber
+ 0, // bAlternateSetting
+ 1, // bNumEndpoints
+ 0x02, // bInterfaceClass
+ 0x02, // bInterfaceSubClass
+ 0x01, // bInterfaceProtocol
+ 0, // iInterface
+
+ // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x00, // bDescriptorSubtype
+ 0x10, 0x01, // bcdCDC
+
+ // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x01, // bDescriptorSubtype
+ 0x03, // bmCapabilities
+ 1, // bDataInterface
+
+ // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28
+ 4, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x02, // bDescriptorSubtype
+ 0x06, // bmCapabilities
+
+ // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x06, // bDescriptorSubtype
+ 0, // bMasterInterface
+ 1, // bSlaveInterface0
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes (0x03=intr)
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 16, // bInterval
+
+
+
+
+ // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+ 9, // bLength
+ 4, // bDescriptorType
+ 1, // bInterfaceNumber
+ 0, // bAlternateSetting
+ 2, // bNumEndpoints
+ 0x0A, // bInterfaceClass
+ 0x00, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0, // iInterface
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPBULK_IN), // bEndpointAddress
+ E_BULK, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0, // bInterval
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPBULK_OUT), // bEndpointAddress
+ E_BULK, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0 // bInterval
+ };
+ return configDescriptor;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h
new file mode 100644
index 000000000..33c6b0a02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h
@@ -0,0 +1,123 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBCDC_H
+#define USBCDC_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+class USBCDC: public USBDevice {
+public:
+
+ /*
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ * @param connect_blocking define if the connection must be blocked if USB not plugged in
+ */
+ USBCDC(uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect_blocking);
+
+protected:
+
+ /*
+ * Get device descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the device descriptor
+ */
+ virtual uint8_t * deviceDesc();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Send a buffer
+ *
+ * @param endpoint endpoint which will be sent the buffer
+ * @param buffer buffer to be sent
+ * @param size length of the buffer
+ * @returns true if successful
+ */
+ bool send(uint8_t * buffer, uint32_t size);
+
+ /*
+ * Read a buffer from a certain endpoint. Warning: blocking
+ *
+ * @param endpoint endpoint to read
+ * @param buffer buffer where will be stored bytes
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP(uint8_t * buffer, uint32_t * size);
+
+ /*
+ * Read a buffer from a certain endpoint. Warning: non blocking
+ *
+ * @param endpoint endpoint to read
+ * @param buffer buffer where will be stored bytes
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP_NB(uint8_t * buffer, uint32_t * size);
+
+ /*
+ * Called by USBCallback_requestCompleted when CDC line coding is changed
+ * Warning: Called in ISR
+ *
+ * @param baud The baud rate
+ * @param bits The number of bits in a word (5-8)
+ * @param parity The parity
+ * @param stop The number of stop bits (1 or 2)
+ */
+ virtual void lineCodingChanged(int baud, int bits, int parity, int stop) {};
+
+protected:
+ virtual bool USBCallback_request();
+ virtual void USBCallback_requestCompleted(uint8_t *buf, uint32_t length);
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+ volatile bool terminal_connected;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp
new file mode 100644
index 000000000..4dc28b9e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBSerial.h"
+
+int USBSerial::_putc(int c) {
+ if (!terminal_connected)
+ return 0;
+ send((uint8_t *)&c, 1);
+ return 1;
+}
+
+int USBSerial::_getc() {
+ uint8_t c = 0;
+ while (buf.isEmpty());
+ buf.dequeue(&c);
+ return c;
+}
+
+
+bool USBSerial::writeBlock(uint8_t * buf, uint16_t size) {
+ if(size > MAX_PACKET_SIZE_EPBULK) {
+ return false;
+ }
+ if(!send(buf, size)) {
+ return false;
+ }
+ return true;
+}
+
+
+
+bool USBSerial::EPBULK_OUT_callback() {
+ uint8_t c[65];
+ uint32_t size = 0;
+
+ //we read the packet received and put it on the circular buffer
+ readEP(c, &size);
+ for (uint32_t i = 0; i < size; i++) {
+ buf.queue(c[i]);
+ }
+
+ //call a potential handler
+ rx.call();
+
+ return true;
+}
+
+uint8_t USBSerial::available() {
+ return buf.available();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h
new file mode 100644
index 000000000..164cf9bc7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h
@@ -0,0 +1,161 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBSERIAL_H
+#define USBSERIAL_H
+
+#include "USBCDC.h"
+#include "Stream.h"
+#include "CircBuffer.h"
+
+
+/**
+* USBSerial example
+*
+* @code
+* #include "mbed.h"
+* #include "USBSerial.h"
+*
+* //Virtual serial port over USB
+* USBSerial serial;
+*
+* int main(void) {
+*
+* while(1)
+* {
+* serial.printf("I am a virtual serial port\n");
+* wait(1);
+* }
+* }
+* @endcode
+*/
+class USBSerial: public USBCDC, public Stream {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id (default: 0x1f00)
+ * @param product_id Your product_id (default: 0x2012)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ * @param connect_blocking define if the connection must be blocked if USB not plugged in
+ *
+ */
+ USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking){
+ settingsChangedCallback = 0;
+ };
+
+
+ /**
+ * Send a character. You can use puts, printf.
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Read a character: blocking
+ *
+ * @returns character read
+ */
+ virtual int _getc();
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ uint8_t available();
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable() { return available() ? 1 : 0; }
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable() { return 1; } // always return 1, for write operation is blocking
+
+ /**
+ * Write a block of data.
+ *
+ * For more efficiency, a block of size 64 (maximum size of a bulk endpoint) has to be written.
+ *
+ * @param buf pointer on data which will be written
+ * @param size size of the buffer. The maximum size of a block is limited by the size of the endpoint (64 bytes)
+ *
+ * @returns true if successfull
+ */
+ bool writeBlock(uint8_t * buf, uint16_t size);
+
+ /**
+ * Attach a member function to call when a packet is received.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ rx.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when a packet is received
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(void)) {
+ if(fptr != NULL) {
+ rx.attach(fptr);
+ }
+ }
+
+ /**
+ * Attach a callback to call when serial's settings are changed.
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(int baud, int bits, int parity, int stop)) {
+ settingsChangedCallback = fptr;
+ }
+
+protected:
+ virtual bool EPBULK_OUT_callback();
+ virtual void lineCodingChanged(int baud, int bits, int parity, int stop){
+ if (settingsChangedCallback) {
+ settingsChangedCallback(baud, bits, parity, stop);
+ }
+ }
+
+private:
+ FunctionPointer rx;
+ CircBuffer<uint8_t,128> buf;
+ void (*settingsChangedCallback)(int baud, int bits, int parity, int stop);
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h
new file mode 100644
index 000000000..06ea4301a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h
@@ -0,0 +1,36 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IUSBENUMERATOR_H_
+#define IUSBENUMERATOR_H_
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+
+/*
+Generic interface to implement for "smart" USB enumeration
+*/
+
+class IUSBEnumerator
+{
+public:
+ virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+};
+
+#endif /*IUSBENUMERATOR_H_*/
+
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h
new file mode 100644
index 000000000..fbbf066e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h
@@ -0,0 +1,329 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : devdrv_usb_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_API_H
+#define USB_HOST_API_H
+
+#include "r_typedefs.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_PORTNUM (2)
+
+#define USB_HOST_ELT_INTERRUPT_LEVEL (9)
+
+#define USBHCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */
+#define USBHCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */
+
+#define USB_HOST_MAX_DEVICE (10)
+
+#define USB_HOST_ON (1)
+#define USB_HOST_OFF (0)
+#define USB_HOST_YES (1)
+#define USB_HOST_NO (0)
+
+#define USB_HOST_NON_SPEED (0)
+#define USB_HOST_LOW_SPEED (1)
+#define USB_HOST_FULL_SPEED (2)
+#define USB_HOST_HIGH_SPEED (3)
+
+/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */
+#define DEVDRV_USBH_STALL (-2)
+#define DEVDRV_USBH_TIMEOUT (-3)
+#define DEVDRV_USBH_NAK_TIMEOUT (-4)
+#define DEVDRV_USBH_DETACH_ERR (-5)
+#define DEVDRV_USBH_SETUP_ERR (-6)
+#define DEVDRV_USBH_CTRL_COM_ERR (-7)
+#define DEVDRV_USBH_COM_ERR (-8)
+#define DEVDRV_USBH_DEV_ADDR_ERR (-9)
+
+#define USB_HOST_ATTACH (1)
+#define USB_HOST_DETACH (0)
+
+#define USB_HOST_MAX_PIPE_NO (9u)
+#define USB_HOST_PIPE0 (0)
+#define USB_HOST_PIPE1 (1)
+#define USB_HOST_PIPE2 (2)
+#define USB_HOST_PIPE3 (3)
+#define USB_HOST_PIPE4 (4)
+#define USB_HOST_PIPE5 (5)
+#define USB_HOST_PIPE6 (6)
+#define USB_HOST_PIPE7 (7)
+#define USB_HOST_PIPE8 (8)
+#define USB_HOST_PIPE9 (9)
+
+#define USB_HOST_ISO (0xc000u)
+#define USB_HOST_INTERRUPT (0x8000u)
+#define USB_HOST_BULK (0x4000u)
+
+#define USB_HOST_PIPE_IDLE (0x00)
+#define USB_HOST_PIPE_WAIT (0x01)
+#define USB_HOST_PIPE_DONE (0x02)
+#define USB_HOST_PIPE_NORES (0x03)
+#define USB_HOST_PIPE_STALL (0x04)
+#define USB_HOST_PIPE_ERROR (0x05)
+
+#define USB_HOST_NONE (0x0000u)
+#define USB_HOST_BFREFIELD (0x0400u)
+#define USB_HOST_BFREON (0x0400u)
+#define USB_HOST_BFREOFF (0x0000u)
+#define USB_HOST_DBLBFIELD (0x0200u)
+#define USB_HOST_DBLBON (0x0200u)
+#define USB_HOST_DBLBOFF (0x0000u)
+#define USB_HOST_CNTMDFIELD (0x0100u)
+#define USB_HOST_CNTMDON (0x0100u)
+#define USB_HOST_CNTMDOFF (0x0000u)
+#define USB_HOST_SHTNAKON (0x0080u)
+#define USB_HOST_SHTNAKOFF (0x0000u)
+#define USB_HOST_DIRFIELD (0x0010u)
+#define USB_HOST_DIR_H_OUT (0x0010u)
+#define USB_HOST_DIR_H_IN (0x0000u)
+#define USB_HOST_EPNUMFIELD (0x000fu)
+
+#define USB_HOST_CUSE (0)
+#define USB_HOST_D0USE (1)
+#define USB_HOST_D0DMA (2)
+#define USB_HOST_D1USE (3)
+#define USB_HOST_D1DMA (4)
+
+#define USB_HOST_CFIFO_USE (0x0000)
+#define USB_HOST_D0FIFO_USE (0x1000)
+#define USB_HOST_D1FIFO_USE (0x2000)
+#define USB_HOST_D0FIFO_DMA (0x5000)
+#define USB_HOST_D1FIFO_DMA (0x6000)
+
+#define USB_HOST_BUF2FIFO (0)
+#define USB_HOST_FIFO2BUF (1)
+
+#define USB_HOST_DRV_DETACHED (0x0000)
+#define USB_HOST_DRV_ATTACHED (0x0001)
+#define USB_HOST_DRV_GET_DEVICE_DESC_64 (0x0002)
+#define USB_HOST_DRV_POWERED (0x0003)
+#define USB_HOST_DRV_DEFAULT (0x0004)
+#define USB_HOST_DRV_SET_ADDRESS (0x0005)
+#define USB_HOST_DRV_ADDRESSED (0x0006)
+#define USB_HOST_DRV_GET_DEVICE_DESC_18 (0x0007)
+#define USB_HOST_DRV_GET_CONGIG_DESC_9 (0x0008)
+#define USB_HOST_DRV_GET_CONGIG_DESC (0x0009)
+#define USB_HOST_DRV_SET_CONFIG (0x000a)
+#define USB_HOST_DRV_CONFIGURED (0x000b)
+#define USB_HOST_DRV_SUSPEND (0x1000)
+#define USB_HOST_DRV_NORES (0x0100)
+#define USB_HOST_DRV_STALL (0x0200)
+
+#define USB_HOST_TESTMODE_FORCE (0x000du)
+#define USB_HOST_TESTMODE_TESTPACKET (0x000cu)
+#define USB_HOST_TESTMODE_SE0_NAK (0x000bu)
+#define USB_HOST_TESTMODE_K (0x000au)
+#define USB_HOST_TESTMODE_J (0x0009u)
+#define USB_HOST_TESTMODE_NORMAL (0x0000u)
+
+#define USB_HOST_DT_DEVICE (0x01)
+#define USB_HOST_DT_CONFIGURATION (0x02)
+#define USB_HOST_DT_STRING (0x03)
+#define USB_HOST_DT_INTERFACE (0x04)
+#define USB_HOST_DT_ENDPOINT (0x05)
+#define USB_HOST_DT_DEVICE_QUALIFIER (0x06)
+#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION (0x07)
+#define USB_HOST_DT_INTERFACE_POWER (0x08)
+
+#define USB_HOST_IF_CLS_NOT (0x00)
+#define USB_HOST_IF_CLS_AUDIO (0x01)
+#define USB_HOST_IF_CLS_CDC_CTRL (0x02)
+#define USB_HOST_IF_CLS_HID (0x03)
+#define USB_HOST_IF_CLS_PHYSICAL (0x05)
+#define USB_HOST_IF_CLS_IMAGE (0x06)
+#define USB_HOST_IF_CLS_PRINTER (0x07)
+#define USB_HOST_IF_CLS_MASS (0x08)
+#define USB_HOST_IF_CLS_HUB (0x09)
+#define USB_HOST_IF_CLS_CDC_DATA (0x0a)
+#define USB_HOST_IF_CLS_CRAD (0x0b)
+#define USB_HOST_IF_CLS_CONTENT (0x0d)
+#define USB_HOST_IF_CLS_VIDEO (0x0e)
+#define USB_HOST_IF_CLS_DIAG (0xdc)
+#define USB_HOST_IF_CLS_WIRELESS (0xe0)
+#define USB_HOST_IF_CLS_APL (0xfe)
+#define USB_HOST_IF_CLS_VENDOR (0xff)
+#define USB_HOST_IF_CLS_HELE (0xaa)
+
+#define USB_HOST_EP_DIR_MASK (0x80)
+#define USB_HOST_EP_OUT (0x00)
+#define USB_HOST_EP_IN (0x80)
+#define USB_HOST_EP_TYPE (0x03)
+#define USB_HOST_EP_CNTRL (0x00)
+#define USB_HOST_EP_ISO (0x01)
+#define USB_HOST_EP_BULK (0x02)
+#define USB_HOST_EP_INT (0x03)
+#define USB_HOST_EP_NUM_MASK (0x0f)
+
+#define USB_HOST_PIPE_IN (0)
+#define USB_HOST_PIPE_OUT (1)
+
+#define USB_END_POINT_ERROR (0xffff)
+
+#define USB_HOST_REQ_GET_STATUS (0x0000)
+#define USB_HOST_REQ_CLEAR_FEATURE (0x0100)
+#define USB_HOST_REQ_RESERVED2 (0x0200)
+#define USB_HOST_REQ_SET_FEATURE (0x0300)
+#define USB_HOST_REQ_RESERVED4 (0x0400)
+#define USB_HOST_REQ_SET_ADDRESS (0x0500)
+#define USB_HOST_REQ_GET_DESCRIPTOR (0x0600)
+#define USB_HOST_REQ_SET_DESCRIPTOR (0x0700)
+#define USB_HOST_REQ_GET_CONFIGURATION (0x0800)
+#define USB_HOST_REQ_SET_CONFIGURATION (0x0900)
+#define USB_HOST_REQ_GET_INTERFACE (0x0a00)
+#define USB_HOST_REQ_SET_INTERFACE (0x0b00)
+#define USB_HOST_REQ_SYNCH_FRAME (0x0c00)
+
+#define USB_HOST_REQTYPE_HOST_TO_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_DEVICE_TO_HOST (0x0080)
+#define USB_HOST_REQTYPE_STANDARD (0x0020)
+#define USB_HOST_REQTYPE_CLASS (0x0040)
+#define USB_HOST_REQTYPE_VENDOR (0x0060)
+#define USB_HOST_REQTYPE_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_INTERFACE (0x0001)
+#define USB_HOST_REQTYPE_ENDPOINT (0x0002)
+#define USB_HOST_REQTYPE_OTHER (0x0003)
+
+#define USB_HOST_DESCTYPE_DEVICE (0x0100)
+#define USB_HOST_DESCTYPE_CONFIGURATION (0x0200)
+#define USB_HOST_DESCTYPE_STRING (0x0300)
+#define USB_HOST_DESCTYPE_INTERFACE (0x0400)
+#define USB_HOST_DESCTYPE_ENDPOINT (0x0500)
+#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER (0x0600)
+#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700)
+#define USB_HOST_DESCTYPE_INTERFACE_POWER (0x0800)
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+typedef struct
+{
+ uint16_t pipe_number;
+ uint16_t pipe_cfg;
+ uint16_t pipe_buf;
+ uint16_t pipe_max_pktsize;
+ uint16_t pipe_cycle;
+ uint16_t fifo_port;
+} USB_HOST_CFG_PIPETBL_t;
+
+typedef struct
+{
+ uint32_t fifo;
+ uint32_t buffer;
+ uint32_t bytes;
+ uint32_t dir;
+ uint32_t size;
+} USB_HOST_DMA_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr);
+int32_t R_USB_api_host_detach(uint16_t root);
+int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes);
+int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+
+int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum);
+int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir);
+uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root);
+
+void R_USB_api_host_elt_clocksel(uint16_t clockmode);
+void R_USB_api_host_elt_4_4(uint16_t root);
+void R_USB_api_host_elt_4_5(uint16_t root);
+void R_USB_api_host_elt_4_6(uint16_t root);
+void R_USB_api_host_elt_4_7(uint16_t root);
+void R_USB_api_host_elt_4_8(uint16_t root);
+void R_USB_api_host_elt_4_9(uint16_t root);
+void R_USB_api_host_elt_get_desc(uint16_t root);
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host_api.h"
+#include "usb1_host_api.h"
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#ifdef USB0_HOST_API_H
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_host_attach(void);
+void Userdef_USB_usb0_host_detach(void);
+void Userdef_USB_usb0_host_delay_1ms(void);
+void Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_host_delay_500ns(void);
+void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+void Userdef_USB_usb0_host_notice(const char * format);
+void Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#ifdef USB1_HOST_API_H
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_host_attach(void);
+void Userdef_USB_usb1_host_detach(void);
+void Userdef_USB_usb1_host_delay_1ms(void);
+void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_host_delay_500ns(void);
+void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+void Userdef_USB_usb1_host_notice(const char * format);
+void Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#endif /* USB_HOST_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h
new file mode 100644
index 000000000..287e0860e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_H
+#define USB_HOST_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_DEVICE_0 (0u)
+#define USB_HOST_DEVICE_1 (1u)
+#define USB_HOST_DEVICE_2 (2u)
+#define USB_HOST_DEVICE_3 (3u)
+#define USB_HOST_DEVICE_4 (4u)
+#define USB_HOST_DEVICE_5 (5u)
+#define USB_HOST_DEVICE_6 (6u)
+#define USB_HOST_DEVICE_7 (7u)
+#define USB_HOST_DEVICE_8 (8u)
+#define USB_HOST_DEVICE_9 (9u)
+#define USB_HOST_DEVICE_10 (10u)
+
+#define USB_HOST_ENDPOINT_DESC (0x05)
+
+#define USB_HOST_BITUPLLE (0x0002u)
+#define USB_HOST_BITUCKSEL (0x0004u)
+#define USB_HOST_BITBWAIT (0x003fu)
+
+#define USB_HOST_BUSWAIT_02 (0x0000u)
+#define USB_HOST_BUSWAIT_03 (0x0001u)
+#define USB_HOST_BUSWAIT_04 (0x0002u)
+#define USB_HOST_BUSWAIT_05 (0x0003u)
+#define USB_HOST_BUSWAIT_06 (0x0004u)
+#define USB_HOST_BUSWAIT_07 (0x0005u)
+#define USB_HOST_BUSWAIT_08 (0x0006u)
+#define USB_HOST_BUSWAIT_09 (0x0007u)
+#define USB_HOST_BUSWAIT_10 (0x0008u)
+#define USB_HOST_BUSWAIT_11 (0x0009u)
+#define USB_HOST_BUSWAIT_12 (0x000au)
+#define USB_HOST_BUSWAIT_13 (0x000bu)
+#define USB_HOST_BUSWAIT_14 (0x000cu)
+#define USB_HOST_BUSWAIT_15 (0x000du)
+#define USB_HOST_BUSWAIT_16 (0x000eu)
+#define USB_HOST_BUSWAIT_17 (0x000fu)
+
+#define USB_HOST_FS_JSTS (0x0001u)
+#define USB_HOST_LS_JSTS (0x0002u)
+
+#define USB_HOST_BITRST (0x0040u)
+#define USB_HOST_BITRESUME (0x0020u)
+#define USB_HOST_BITUACT (0x0010u)
+#define USB_HOST_HSPROC (0x0004u)
+#define USB_HOST_HSMODE (0x0003u)
+#define USB_HOST_FSMODE (0x0002u)
+#define USB_HOST_LSMODE (0x0001u)
+#define USB_HOST_UNDECID (0x0000u)
+
+#define USB_HOST_BITRCNT (0x8000u)
+#define USB_HOST_BITDREQE (0x1000u)
+#define USB_HOST_BITMBW (0x0c00u)
+#define USB_HOST_BITMBW_8 (0x0000u)
+#define USB_HOST_BITMBW_16 (0x0400u)
+#define USB_HOST_BITMBW_32 (0x0800u)
+#define USB_HOST_BITBYTE_LITTLE (0x0000u)
+#define USB_HOST_BITBYTE_BIG (0x0100u)
+#define USB_HOST_BITISEL (0x0020u)
+#define USB_HOST_BITCURPIPE (0x000fu)
+
+#define USB_HOST_CFIFO_READ (0x0000u)
+#define USB_HOST_CFIFO_WRITE (0x0020u)
+
+#define USB_HOST_BITBVAL (0x8000u)
+#define USB_HOST_BITBCLR (0x4000u)
+#define USB_HOST_BITFRDY (0x2000u)
+#define USB_HOST_BITDTLN (0x0fffu)
+
+#define USB_HOST_BITBEMPE (0x0400u)
+#define USB_HOST_BITNRDYE (0x0200u)
+#define USB_HOST_BITBRDYE (0x0100u)
+#define USB_HOST_BITBEMP (0x0400u)
+#define USB_HOST_BITNRDY (0x0200u)
+#define USB_HOST_BITBRDY (0x0100u)
+
+#define USB_HOST_BITBCHGE (0x4000u)
+#define USB_HOST_BITDTCHE (0x1000u)
+#define USB_HOST_BITATTCHE (0x0800u)
+#define USB_HOST_BITEOFERRE (0x0040u)
+#define USB_HOST_BITBCHG (0x4000u)
+#define USB_HOST_BITDTCH (0x1000u)
+#define USB_HOST_BITATTCH (0x0800u)
+#define USB_HOST_BITEOFERR (0x0040u)
+
+#define USB_HOST_BITSIGNE (0x0020u)
+#define USB_HOST_BITSACKE (0x0010u)
+#define USB_HOST_BITSIGN (0x0020u)
+#define USB_HOST_BITSACK (0x0010u)
+
+#define USB_HOST_BITSUREQ (0x4000u)
+#define USB_HOST_BITSQSET (0x0080u)
+#define USB_HOST_PID_STALL2 (0x0003u)
+#define USB_HOST_PID_STALL (0x0002u)
+#define USB_HOST_PID_BUF (0x0001u)
+#define USB_HOST_PID_NAK (0x0000u)
+
+#define USB_HOST_PIPExBUF (64u)
+
+#define USB_HOST_D0FIFO (0)
+#define USB_HOST_D1FIFO (1)
+#define USB_HOST_DMA_READY (0)
+#define USB_HOST_DMA_BUSY (1)
+#define USB_HOST_DMA_BUSYEND (2)
+
+#define USB_HOST_FIFO_USE (0x7000)
+
+#define USB_HOST_FIFOERROR (0xffff)
+#define USB_HOST_WRITEEND (0)
+#define USB_HOST_WRITESHRT (1)
+#define USB_HOST_WRITING (2)
+#define USB_HOST_WRITEDMA (3)
+#define USB_HOST_READEND (0)
+#define USB_HOST_READSHRT (1)
+#define USB_HOST_READING (2)
+#define USB_HOST_READOVER (3)
+#define USB_HOST_READZERO (4)
+
+#define USB_HOST_CMD_IDLE (0x0000)
+#define USB_HOST_CMD_DOING (0x0001)
+#define USB_HOST_CMD_DONE (0x0002)
+#define USB_HOST_CMD_NORES (0x0003)
+#define USB_HOST_CMD_STALL (0x0004)
+#define USB_HOST_CMD_FIELD (0x000f)
+
+#if 0
+#define USB_HOST_CHG_CMDFIELD( r, v ) do { r &= ( ~USB_HOST_CMD_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_MODE_WRITE (0x0100)
+#define USB_HOST_MODE_READ (0x0200)
+#define USB_HOST_MODE_NO_DATA (0x0300)
+#define USB_HOST_MODE_FIELD (0x0f00)
+
+#define USB_HOST_STAGE_SETUP (0x0010)
+#define USB_HOST_STAGE_DATA (0x0020)
+#define USB_HOST_STAGE_STATUS (0x0030)
+#define USB_HOST_STAGE_FIELD (0x00f0)
+
+#if 0
+#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_DEVADD_MASK (0x7fc0)
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern uint16_t g_usb_host_elt_clockmode;
+
+#endif /* USB_HOST_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h
new file mode 100644
index 000000000..33b82ea6f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_host_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+
+#define USB_HOST_LOCAL_Rev "VER080_140709"
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c
new file mode 100644
index 000000000..0b1b7da65
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c
@@ -0,0 +1,1486 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <string.h>
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "ohci_wrapp_RZ_A1.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+#include "rza_io_regrw.h"
+#include "usb_host_setting.h"
+
+/* ------------------ HcControl Register --------------------- */
+#define OR_CONTROL_PLE (0x00000004)
+#define OR_CONTROL_IE (0x00000008)
+#define OR_CONTROL_CLE (0x00000010)
+#define OR_CONTROL_BLE (0x00000020)
+/* ----------------- HcCommandStatus Register ----------------- */
+#define OR_CMD_STATUS_HCR (0x00000001)
+#define OR_CMD_STATUS_CLF (0x00000002)
+#define OR_CMD_STATUS_BLF (0x00000004)
+#define OR_CMD_STATUS_OCR (0x00000008)
+/* --------------- HcInterruptStatus Register ----------------- */
+#define OR_INTR_STATUS_WDH (0x00000002)
+#define OR_INTR_STATUS_RHSC (0x00000040)
+/* --------------- HcInterruptEnable Register ----------------- */
+#define OR_INTR_ENABLE_WDH (0x00000002)
+#define OR_INTR_ENABLE_RHSC (0x00000040)
+/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define OR_RH_PORT_CSC (0x00010000)
+#define OR_RH_PORT_LSDA (0x00000200)
+#define OR_RH_PORT_PRS (0x00000010)
+#define OR_RH_PORT_POCI (0x00000008)
+#define OR_RH_PORT_CCS (0x00000001)
+
+#define ED_FORMAT (0x00008000) /* Format */
+#define ED_SKIP (0x00004000) /* Skip this ep in queue */
+#define ED_TOGLE_CARRY (0x00000002)
+#define ED_HALTED (0x00000001)
+
+#define TD_SETUP (0x00000000) /* Direction of Setup Packet */
+#define TD_OUT (0x00080000) /* Direction Out */
+#define TD_TOGGLE_0 (0x02000000) /* Toggle 0 */
+#define TD_TOGGLE_1 (0x03000000) /* Toggle 1 */
+
+/* -------------- USB Standard Requests -------------- */
+#define GET_STATUS (0x00)
+#define SET_FEATURE (0x03)
+#define SET_ADDRESS (0x05)
+
+#define TD_CTL_MSK_DP (0x00180000)
+#define TD_CTL_MSK_T (0x03000000)
+#define TD_CTL_MSK_CC (0xF0000000)
+#define TD_CTL_MSK_EC (0x0C000000)
+#define TD_CTL_SHFT_CC (28)
+#define TD_CTL_SHFT_EC (26)
+#define TD_CTL_SHFT_T (24)
+#define ED_SHFT_TOGLE_CARRY (1)
+#define SIG_GEN_LIST_REQ (1)
+#if (ISO_TRANS_MAX_NUM > 0)
+#define TD_PSW_MSK_CC (0xF000)
+#define TD_PSW_SHFT_CC (12)
+#define TD_CTL_MSK_FC (0x07000000)
+#define TD_CTL_SHFT_FC (24)
+#endif
+
+#define CTL_TRANS_TIMEOUT (1000)
+#define BLK_TRANS_TIMEOUT (5)
+#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM))
+
+#define PORT_LOW_SPEED (0x00000200)
+#define PORT_HIGH_SPEED (0x00000400)
+#define PORT_NUM (16 + 1) /* num + root(1) */
+
+typedef struct tag_hctd {
+ uint32_t control; /* Transfer descriptor control */
+ uint8_t *currBufPtr; /* Physical address of current buffer pointer */
+ struct tag_hctd *nextTD; /* Physical pointer to next Transfer Descriptor */
+ uint8_t *bufEnd; /* Physical address of end of buffer */
+} hctd_t;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+#define PSW_NUM (8)
+typedef struct tag_hcisotd {
+ uint32_t control; /* Transfer descriptor control */
+ uint8_t *bufferPage0; /* Buffer Page 0 */
+ struct tag_hcisotd *nextTD; /* Physical pointer to next Transfer Descriptor */
+ uint8_t *bufEnd; /* Physical address of end of buffer */
+ uint16_t offsetPSW[PSW_NUM]; /* Offset/PSW */
+} hcisotd_t;
+#endif
+
+typedef struct tag_hced {
+ uint32_t control; /* Endpoint descriptor control */
+ uint32_t tailTD; /* Physical address of tail in Transfer descriptor list */
+ uint32_t headTD; /* Physcial address of head in Transfer descriptor list */
+ struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */
+} hced_t;
+
+typedef struct tag_hcca {
+ uint32_t IntTable[32]; /* Interrupt Table */
+ uint32_t FrameNumber; /* Frame Number */
+ uint32_t DoneHead; /* Done Head */
+ volatile uint8_t Reserved[116]; /* Reserved for future use */
+ volatile uint8_t Unknown[4]; /* Unused */
+} hcca_t;
+
+typedef struct tag_usb_ohci_reg {
+ volatile uint32_t HcRevision;
+ volatile uint32_t HcControl;
+ volatile uint32_t HcCommandStatus;
+ volatile uint32_t HcInterruptStatus;
+ volatile uint32_t HcInterruptEnable;
+ volatile uint32_t HcInterruptDisable;
+ volatile uint32_t HcHCCA;
+ volatile uint32_t HcPeriodCurrentED;
+ volatile uint32_t HcControlHeadED;
+ volatile uint32_t HcControlCurrentED;
+ volatile uint32_t HcBulkHeadED;
+ volatile uint32_t HcBulkCurrentED;
+ volatile uint32_t HcDoneHead;
+ volatile uint32_t HcFmInterval;
+ volatile uint32_t HcFmRemaining;
+ volatile uint32_t HcFmNumber;
+ volatile uint32_t HcPeriodicStart;
+ volatile uint32_t HcLSThreshold;
+ volatile uint32_t HcRhDescriptorA;
+ volatile uint32_t HcRhDescriptorB;
+ volatile uint32_t HcRhStatus;
+ volatile uint32_t HcRhPortStatus1;
+} usb_ohci_reg_t;
+
+typedef struct tag_genelal_ed {
+ osThreadId tskid;
+ osSemaphoreId semid_wait;
+ osSemaphoreId semid_list;
+ void *p_curr_td; /* pointer of hctd_t or hcisotd_t */
+ hced_t *p_curr_ed;
+ uint32_t pipe_no;
+ uint32_t trans_wait;
+ uint32_t cycle_time;
+ uint8_t *p_start_buf;
+#if (ISO_TRANS_MAX_NUM > 0)
+ uint32_t psw_idx;
+#endif
+} genelal_ed_t;
+
+typedef struct tag_tdinfo {
+ uint32_t count;
+ uint32_t direction;
+ uint32_t msp;
+ uint16_t devadr;
+ uint16_t speed; /* 1:Speed = Low */
+ uint8_t endpoint_no;
+} tdinfo_t;
+
+typedef struct tag_split_trans {
+ uint16_t root_devadr;
+ uint16_t get_port;
+ uint16_t port_speed;
+ uint16_t reset_port;
+ uint32_t seq_cnt;
+ uint32_t port_sts_bits[PORT_NUM];
+} split_trans_t;
+
+static void callback_task(void const * argument);
+static void control_ed_task(void const * argument);
+static void bulk_ed_task(void const * argument);
+static void int_ed_task(void const * argument);
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed);
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
+static void set_split_trans_setting(void);
+static void control_trans(genelal_ed_t *p_g_ed);
+static void bulk_trans(genelal_ed_t *p_g_ed);
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t chk_cycle(hced_t *p_ed);
+static void int_trans(genelal_ed_t *p_g_ed);
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument);
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
+static void chk_iso_td_done(genelal_ed_t *p_g_ed);
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed);
+static void iso_trans(genelal_ed_t *p_g_ed);
+#endif
+static void connect_check(void);
+
+extern USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[];
+extern USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[];
+#if (ISO_TRANS_MAX_NUM > 0)
+extern USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[];
+#endif
+
+static usb_ohci_reg_t usb_reg;
+static usb_ohci_reg_t *p_usb_reg = &usb_reg;
+static usbisr_fnc_t *p_usbisr_cb = NULL;
+static osSemaphoreId semid_cb = NULL;
+static uint32_t connect_change = 0xFFFFFFFF;
+static uint32_t init_end = 0;
+static genelal_ed_t ctl_ed;
+static genelal_ed_t blk_ed;
+static genelal_ed_t int_ed[INT_TRANS_MAX_NUM];
+static split_trans_t split_ctl;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static genelal_ed_t iso_ed[ISO_TRANS_MAX_NUM];
+#endif
+
+osSemaphoreDef(ohciwrapp_sem_01);
+osSemaphoreDef(ohciwrapp_sem_02);
+osSemaphoreDef(ohciwrapp_sem_03);
+osSemaphoreDef(ohciwrapp_sem_04);
+osSemaphoreDef(ohciwrapp_sem_05);
+osSemaphoreDef(ohciwrapp_sem_06);
+osSemaphoreDef(ohciwrapp_sem_07);
+#if (INT_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_08);
+osSemaphoreDef(ohciwrapp_sem_09);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+osSemaphoreDef(ohciwrapp_sem_10);
+osSemaphoreDef(ohciwrapp_sem_11);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+osSemaphoreDef(ohciwrapp_sem_12);
+osSemaphoreDef(ohciwrapp_sem_13);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+osSemaphoreDef(ohciwrapp_sem_14);
+osSemaphoreDef(ohciwrapp_sem_15);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_16);
+osSemaphoreDef(ohciwrapp_sem_17);
+#endif
+
+osThreadDef(callback_task, osPriorityHigh, 512);
+osThreadDef(control_ed_task, osPriorityNormal, 512);
+osThreadDef(bulk_ed_task, osPriorityNormal, 512);
+static void int_ed_task_1(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_1, osPriorityNormal, 512);
+#if (INT_TRANS_MAX_NUM >= 2)
+static void int_ed_task_2(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_2, osPriorityNormal, 512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+static void int_ed_task_3(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_3, osPriorityNormal, 512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+static void int_ed_task_4(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_4, osPriorityNormal, 512);
+#endif
+
+#if (ISO_TRANS_MAX_NUM >= 1)
+static void iso_ed_task_1(void const * argument) {
+ iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_1, osPriorityNormal, 512);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+static void iso_ed_task_2(void const * argument) {
+ iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_2, osPriorityNormal, 512);
+#endif
+
+void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
+ static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
+ osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
+ , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
+ , osSemaphore(ohciwrapp_sem_07)
+#if (INT_TRANS_MAX_NUM >= 2)
+ , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+ , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+ , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+ , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+ , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17)
+#endif
+ };
+ static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = {
+ osThread(int_ed_task_1)
+#if (INT_TRANS_MAX_NUM >= 2)
+ , osThread(int_ed_task_2)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+ , osThread(int_ed_task_3)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+ , osThread(int_ed_task_4)
+#endif
+ };
+#if (ISO_TRANS_MAX_NUM > 0)
+ static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = {
+ osThread(iso_ed_task_1)
+#if (ISO_TRANS_MAX_NUM >= 2)
+ , osThread(iso_ed_task_2)
+#endif
+ };
+#endif
+
+ uint32_t cnt;
+ uint32_t index = 0;
+
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ(USBIXUSBIX);
+
+#if (USB_HOST_CH == 0)
+ /* P4_1(USB0_EN) */
+ GPIOP4 &= ~0x0002; /* Outputs low level */
+ GPIOPMC4 &= ~0x0002; /* Port mode */
+ GPIOPM4 &= ~0x0002; /* Output mode */
+#endif
+
+ p_usbisr_cb = p_usbisr_fnc;
+#if (USB_HOST_HISPEED == 0)
+ g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
+#else
+ g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+#endif
+ p_usb_reg->HcRevision = 0x00000010;
+ p_usb_reg->HcControl = 0x00000000;
+ p_usb_reg->HcCommandStatus = 0x00000000;
+ p_usb_reg->HcInterruptStatus = 0x00000000;
+ p_usb_reg->HcInterruptEnable = 0x00000000;
+ p_usb_reg->HcInterruptDisable = 0x00000000;
+ p_usb_reg->HcHCCA = 0x00000000;
+ p_usb_reg->HcPeriodCurrentED = 0x00000000;
+ p_usb_reg->HcControlHeadED = 0x00000000;
+ p_usb_reg->HcControlCurrentED = 0x00000000;
+ p_usb_reg->HcBulkHeadED = 0x00000000;
+ p_usb_reg->HcBulkCurrentED = 0x00000000;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcFmInterval = 0x00002EDF;
+ p_usb_reg->HcFmRemaining = 0x00002EDF;
+ p_usb_reg->HcFmNumber = 0x00000000;
+ p_usb_reg->HcPeriodicStart = 0x00000000;
+ p_usb_reg->HcLSThreshold = 0x00000628;
+ p_usb_reg->HcRhDescriptorA = 0xFF000901;
+ p_usb_reg->HcRhDescriptorB = 0x00020000;
+ p_usb_reg->HcRhStatus = 0x00000000;
+ p_usb_reg->HcRhPortStatus1 = 0x00000000;
+
+#if (USB_HOST_CH == 0)
+ GPIOP4 |= 0x0002; /* P4_1 Outputs high level */
+ osDelay(5);
+ GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */
+ osDelay(10);
+#else
+ osDelay(15);
+#endif
+
+ if (init_end == 0) {
+ (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
+ (void)memset(&blk_ed, 0, sizeof(blk_ed));
+ (void)memset(&int_ed[0], 0, sizeof(int_ed));
+#if (ISO_TRANS_MAX_NUM > 0)
+ (void)memset(&iso_ed[0], 0, sizeof(iso_ed));
+#endif
+
+ /* callback */
+ semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ (void)osThreadCreate(osThread(callback_task), 0);
+
+ /* control transfer */
+ ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
+
+ /* bulk transfer */
+ blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
+
+ /* interrupt transfer */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt);
+ }
+
+#if (ISO_TRANS_MAX_NUM > 0)
+ /* isochronous transfer */
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ iso_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ iso_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt);
+ }
+#endif
+ init_end = 1;
+ }
+}
+
+uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
+ if (init_end == 0) {
+ return 0;
+ }
+
+ return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
+}
+
+void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
+ uint32_t cnt;
+ uint32_t last_data;
+ hcca_t *p_hcca;
+
+ if (init_end == 0) {
+ return;
+ }
+
+ switch (reg_ofs) {
+ case OHCI_REG_CONTROL:
+ last_data = p_usb_reg->HcControl;
+ p_usb_reg->HcControl = (set_data & 0x000007FF);
+ if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
+ /* change CLE */
+ if ((set_data & OR_CONTROL_CLE) != 0) {
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ } else {
+ if (ctl_ed.trans_wait == 1) {
+ ctl_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(ctl_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ }
+ }
+ if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
+ /* change BLE */
+ if ((set_data & OR_CONTROL_BLE) != 0) {
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ } else {
+ if (blk_ed.trans_wait == 1) {
+ blk_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(blk_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ }
+ }
+#if (ISO_TRANS_MAX_NUM > 0)
+ if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) {
+ /* change IE */
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ if ((set_data & OR_CONTROL_IE) != 0) {
+ (void)osSemaphoreRelease(iso_ed[cnt].semid_list);
+ } else {
+ if (iso_ed[cnt].trans_wait == 1) {
+ iso_ed[cnt].trans_wait = 0;
+ (void)osSemaphoreRelease(iso_ed[cnt].semid_wait);
+ }
+ (void)osSemaphoreWait(iso_ed[cnt].semid_list, osWaitForever);
+ }
+ }
+ }
+#endif
+ if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
+ /* change PLE */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((set_data & OR_CONTROL_PLE) != 0) {
+ (void)osSemaphoreRelease(int_ed[cnt].semid_list);
+ } else {
+ if (int_ed[cnt].trans_wait == 1) {
+ int_ed[cnt].trans_wait = 0;
+ (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
+ }
+ (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever);
+ }
+ }
+ }
+ break;
+ case OHCI_REG_COMMANDSTATUS:
+ if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
+ if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
+ ohciwrapp_loc_Connect(1);
+ }
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
+ }
+ if ((set_data & OR_CMD_STATUS_CLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_BLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_OCR) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
+ } else {
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
+ }
+ break;
+ case OHCI_REG_INTERRUPTSTATUS:
+ if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
+ && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
+ if (p_usb_reg->HcDoneHead != 0x00000000) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ } else {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
+ }
+ }
+ if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
+ }
+ break;
+ case OHCI_REG_INTERRUPTENABLE:
+ case OHCI_REG_INTERRUPTDISABLE:
+ case OHCI_REG_HCCA:
+ case OHCI_REG_CONTROLHEADED:
+ case OHCI_REG_CONTROLCURRENTED:
+ case OHCI_REG_BULKHEADED:
+ case OHCI_REG_BULKCURRENTED:
+ case OHCI_REG_FMINTERVAL:
+ case OHCI_REG_FMREMAINING:
+ case OHCI_REG_PERIODICSTART:
+ case OHCI_REG_LSTHRESHOLD:
+ case OHCI_REG_RHDESCRIPTORA:
+ case OHCI_REG_RHDESCRIPTORB:
+ case OHCI_REG_RHSTATUS:
+ *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
+ break;
+ case OHCI_REG_RHPORTSTATUS1:
+ p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
+ if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */
+ p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
+ usbx_host_UsbBusReset();
+ p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
+ }
+ break;
+ case OHCI_REG_REVISION:
+ case OHCI_REG_PERIODCURRENTED:
+ case OHCI_REG_DONEHEADED:
+ case OHCI_REG_FMNUMBER:
+ default:
+ /* Do Nothing */
+ break;
+ }
+}
+
+static void callback_task(void const * argument) {
+ usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
+
+ if (p_wk_cb == NULL) {
+ return;
+ }
+
+ while (1) {
+ osSemaphoreWait(semid_cb, osWaitForever);
+ if (connect_change != 0xFFFFFFFF) {
+ connect_change = 0xFFFFFFFF;
+ connect_check();
+ }
+ p_wk_cb();
+ }
+}
+
+static void control_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
+ if ((p_usb_reg->HcControlCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
+ p_usb_reg->HcControlCurrentED = p_usb_reg->HcControlHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_CLF;
+ }
+ if (p_usb_reg->HcControlCurrentED != 0) {
+ ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
+ if (chk_genelal_ed(&ctl_ed) != 0) {
+ control_trans(&ctl_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ }
+ p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ }
+}
+
+static void bulk_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
+ if ((p_usb_reg->HcBulkCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
+ p_usb_reg->HcBulkCurrentED = p_usb_reg->HcBulkHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
+ }
+ if (p_usb_reg->HcBulkCurrentED != 0) {
+ blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
+ if (chk_genelal_ed(&blk_ed) != 0) {
+ bulk_trans(&blk_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ }
+ p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ }
+}
+
+static void int_ed_task(void const * argument) {
+ genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
+ uint32_t cnt;
+ uint32_t wait_cnt = 0;
+ hcca_t *p_hcca;
+ hced_t *p_ed;
+
+ while (1) {
+ (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever);
+ if (p_int_ed->p_curr_ed == NULL) {
+ for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL); cnt++) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL)) {
+ if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
+ p_int_ed->p_curr_ed = p_ed;
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans_setting(p_int_ed, (uint32_t)argument);
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ }
+ p_ed = p_ed->nextED;
+ }
+ }
+ }
+ if (p_int_ed->p_curr_ed != NULL) {
+ while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans(p_int_ed);
+ (void)osSemaphoreWait(p_int_ed->semid_wait, osWaitForever);
+ usbx_host_stop_transfer(p_int_ed->pipe_no);
+ wait_cnt = p_int_ed->cycle_time;
+ } else {
+ if (wait_cnt > 0) {
+ wait_cnt--;
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ break;
+ }
+ }
+ }
+ (void)osSemaphoreRelease(p_int_ed->semid_list);
+ if (p_int_ed->p_curr_ed == NULL) {
+ osDelay(10);
+ } else {
+ osDelay(1);
+ }
+ }
+}
+
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
+ uint32_t cnt;
+ int32_t ret = 0;
+
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
+ int32_t ret = 0;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ if (((p_ed->control & ED_SKIP) != 0)
+ || ((p_ed->control & ED_FORMAT) != 0)
+ || ((p_ed->headTD & ED_HALTED) != 0)
+ || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+ /* Do Nothing */
+ } else if ((p_ed->control & 0x0000007F) > 10) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+ if (p_g_ed->p_curr_td == NULL) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ p_g_ed->p_start_buf = p_td->currBufPtr;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed) {
+ hcca_t *p_hcca;
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+ p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0)
+ | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+ p_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
+ if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ }
+ }
+}
+
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
+ uint8_t *p_buf;
+ tdinfo_t td_info;
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ /* Hi-Speed mode only */
+ if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
+ return;
+ }
+
+ if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
+ return;
+ }
+
+ get_td_info(p_g_ed, &td_info);
+ p_buf = p_g_ed->p_start_buf;
+
+ if (td_info.direction == 0) {
+ uint8_t bRequest = p_buf[1];
+ uint16_t wValue = (p_buf[3] << 8) + p_buf[2];
+ uint16_t wIndx = (p_buf[5] << 8) + p_buf[4];
+ uint16_t devadd;
+
+ if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
+ /* SET_ADDRESS */
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ usbx_host_set_devadd(wValue, &devadd);
+ if (split_ctl.root_devadr == 0) {
+ split_ctl.root_devadr = wValue; /* New Address */
+ }
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
+ && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
+ /* SET_FEATURE PORT_RESET */
+ split_ctl.reset_port = (wIndx & 0x00FF);
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
+ /* GET_STATUS */
+ split_ctl.get_port = wIndx;
+ split_ctl.seq_cnt = 1;
+ } else {
+ /* Do Nothing */
+ }
+ } else if (td_info.direction == 2) {
+ if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
+ if (split_ctl.get_port < PORT_NUM) {
+ split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
+ }
+ split_ctl.seq_cnt = 0;
+ }
+ } else {
+ /* Do Nothing */
+ }
+}
+
+static void set_split_trans_setting(void) {
+ uint16_t port_speed;
+ uint16_t devadd;
+
+ if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
+ port_speed = USB_HOST_HIGH_SPEED;
+ } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
+ port_speed = USB_HOST_LOW_SPEED;
+ } else {
+ port_speed = USB_HOST_FULL_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ split_ctl.reset_port = 0;
+ }
+}
+
+static void control_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ if (td_info.devadr == 0) {
+ set_split_trans_setting();
+ }
+ } else {
+ /* When a non-Hi-Speed, the communication speed is determined from the TD. */
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ if (td_info.speed == 1) {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ } else {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ }
+ usbx_host_set_devadd(td_info.devadr, &devadd);
+ }
+
+ USB20X.DCPMAXP = (td_info.devadr << 12) + td_info.msp;
+ if (td_info.direction == 0) {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+ } else if (td_info.count != 0) {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
+ } else {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
+ }
+ g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ p_g_ed->pipe_no = USB_HOST_PIPE0;
+
+ p_g_ed->trans_wait = 1;
+
+ if (td_info.direction == 0) {
+ uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
+ uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
+ uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
+ uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
+
+ g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
+ usbx_host_SetupStage(Req, Val, Indx, Len);
+ } else if (td_info.direction == 1) {
+ usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
+ if (p_g_ed->trans_wait == 1) {
+ p_g_ed->trans_wait = 0;
+ RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+ }
+
+ g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
+ g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+}
+
+static void bulk_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0];
+ uint8_t wk_table[6];
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_BULK;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
+ usbx_host_stop_transfer(p_g_ed->pipe_no);
+}
+
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index];
+ uint8_t wk_table[6];
+ uint32_t cycle_time;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_INT;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ cycle_time = chk_cycle(p_ed);
+ p_g_ed->cycle_time = cycle_time;
+ user_table->pipe_cycle = 0;
+ while (cycle_time > 1) {
+ cycle_time >>= 1;
+ user_table->pipe_cycle++;
+ }
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ usbx_host_get_devadd(td_info.devadr, &devadd);
+ if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+ user_table->pipe_cycle += 3;
+ if (user_table->pipe_cycle > 7) {
+ user_table->pipe_cycle = 7;
+ }
+ }
+ }
+
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+}
+
+static uint32_t chk_cycle(hced_t *p_ed) {
+ uint32_t cnt;
+ uint32_t hit_cnt = 0;
+ uint32_t cycle_time = 1;
+ hcca_t *p_hcca;
+ hced_t *p_wk_ed;
+
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+
+ for (cnt = 0; cnt < 32; cnt++) {
+ p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while (p_wk_ed != NULL) {
+ if (p_wk_ed == p_ed) {
+ hit_cnt++;
+ break;
+ }
+ p_wk_ed = p_wk_ed->nextED;
+ }
+ }
+ if (hit_cnt < 2) {
+ cycle_time = 32;
+ } else if (hit_cnt < 4) {
+ cycle_time = 16;
+ } else if (hit_cnt < 8) {
+ cycle_time = 8;
+ } else if (hit_cnt < 16) {
+ cycle_time = 4;
+ } else if (hit_cnt < 32) {
+ cycle_time = 2;
+ } else{
+ cycle_time = 1;
+ }
+
+ return cycle_time;
+}
+
+static void int_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+
+ get_td_info(p_g_ed, &td_info);
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+}
+
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
+ p_td_info->msp = (p_ed->control >> 16) & 0x000007FF;
+ p_td_info->devadr = p_ed->control & 0x0000000F;
+ p_td_info->speed = (p_ed->control >> 13) & 0x00000001;
+ p_td_info->direction = (p_ed->control >> 11) & 0x00000003;
+
+ if ((p_ed->control & ED_FORMAT) == 0) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+ if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
+ p_td_info->direction = 0;
+ } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
+ p_td_info->direction = 1;
+ } else {
+ p_td_info->direction = 2;
+ }
+ }
+ if (p_td->currBufPtr != NULL) {
+ p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
+ } else {
+ p_td_info->count = 0;
+ }
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+ if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+ if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) {
+ p_td_info->direction = 0;
+ } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) {
+ p_td_info->direction = 1;
+ } else {
+ p_td_info->direction = 2;
+ }
+ }
+#endif
+ }
+}
+
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
+ if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
+ usbx_host_set_sqclr(pipe);
+ } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
+ usbx_host_set_sqset(pipe);
+ } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) {
+ usbx_host_set_sqclr(pipe);
+ } else {
+ usbx_host_set_sqset(pipe);
+ }
+}
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument) {
+ genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
+ uint32_t wait_cnt = 0;
+ uint32_t wait_time = 0;
+ hcca_t *p_hcca;
+ hced_t *p_ed;
+
+ while (1) {
+ (void)osSemaphoreWait(p_iso_ed->semid_list, osWaitForever);
+ if (p_iso_ed->p_curr_ed == NULL) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_ed = (hced_t *)p_hcca->IntTable[0];
+ while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0)
+ && (p_iso_ed->p_curr_ed == NULL)) {
+ if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) {
+ p_iso_ed->p_curr_ed = p_ed;
+ if (chk_iso_ed(p_iso_ed) != 0) {
+ iso_trans_setting(p_iso_ed, (uint32_t)argument);
+ } else {
+ p_iso_ed->p_curr_ed = NULL;
+ }
+ }
+ p_ed = p_ed->nextED;
+ }
+ p_iso_ed->psw_idx = 0;
+ }
+ if (p_iso_ed->p_curr_ed != NULL) {
+ while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
+ if (chk_iso_ed(p_iso_ed) != 0) {
+ wait_time = iso_chk_starting_frame(p_iso_ed);
+ if (wait_time != 0) {
+ osDelay(wait_time);
+ p_usb_reg->HcFmNumber += wait_time;
+ p_usb_reg->HcFmNumber &= 0x0000FFFF;
+ }
+ p_iso_ed->psw_idx = 0;
+ iso_trans(p_iso_ed);
+ (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever);
+ usbx_host_stop_transfer(p_iso_ed->pipe_no);
+ wait_cnt = 1;
+ } else {
+ if (wait_cnt > 0) {
+ wait_cnt--;
+ } else {
+ p_iso_ed->p_curr_ed = NULL;
+ }
+ break;
+ }
+ }
+ }
+ (void)osSemaphoreRelease(p_iso_ed->semid_list);
+ if (p_iso_ed->p_curr_ed == NULL) {
+ osDelay(10);
+ } else {
+ osDelay(1);
+ }
+ }
+}
+
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) {
+ uint32_t cnt;
+ int32_t ret = 0;
+
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void chk_iso_td_done(genelal_ed_t *p_g_ed) {
+ hcca_t *p_hcca;
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ uint32_t ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+ p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0)
+ | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+ p_isotd->nextTD = (hcisotd_t *)p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
+ if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ }
+ }
+}
+
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){
+ int32_t ret = 0;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ if (((p_ed->control & ED_SKIP) != 0)
+ || ((p_ed->control & ED_FORMAT) == 0)
+ || ((p_ed->headTD & ED_HALTED) != 0)
+ || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+ /* Do Nothing */
+ } else if ((p_ed->control & 0x0000007F) > 10) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+ if (p_g_ed->p_curr_td == NULL) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+ p_g_ed->p_start_buf = p_isotd->bufferPage0;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index];
+ uint8_t wk_table[6];
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_ISO;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ p_g_ed->cycle_time = 1;
+ user_table->pipe_cycle = 0;
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ usbx_host_get_devadd(td_info.devadr, &devadd);
+ if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+ user_table->pipe_cycle += 3;
+ }
+ }
+
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+}
+
+static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ uint32_t starting_frame = p_isotd->control & 0x0000FFFF;
+ uint32_t wait_time = 0;
+
+ if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) {
+ wait_time = starting_frame - p_usb_reg->HcFmNumber;
+ }
+
+ return wait_time;
+}
+
+static void iso_trans(genelal_ed_t *p_g_ed) {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+ uint32_t buff_addr;
+ uint32_t data_size;
+
+ if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) {
+ buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000;
+ } else {
+ buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000;
+ }
+ buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF;
+
+ if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+ data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx];
+ } else {
+ data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1;
+ }
+ p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size;
+
+ get_td_info(p_g_ed, &td_info);
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+ }
+}
+#endif
+
+static void connect_check(void) {
+ uint32_t type = 0;
+ uint16_t stat;
+ uint16_t devadd = 0;
+ uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
+
+ if (usbx_host_CheckAttach() == USB_HOST_ATTACH) {
+ type = 1;
+ }
+
+ if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
+ || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
+ return;
+ }
+
+ if (type == 0) {
+ usbx_host_UsbDetach();
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
+ } else {
+ usbx_host_UsbAttach();
+ stat = usbx_host_UsbBusReset();
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if (stat == USB_HOST_HSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+ } else if (stat == USB_HOST_FSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
+ } else {
+ wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usbx_host_init_pipe_status();
+ usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
+ }
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CSC;
+ p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
+ (void)memset(&split_ctl, 0, sizeof(split_ctl));
+}
+
+void ohciwrapp_loc_Connect(uint32_t type) {
+ uint32_t cnt;
+
+ connect_change = type;
+ if (type == 0) {
+ if (ctl_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ if (blk_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ }
+#if (ISO_TRANS_MAX_NUM > 0)
+ for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+ if (iso_ed[cnt].trans_wait == 1) {
+ hced_t *p_ed = iso_ed[cnt].p_curr_ed;
+
+ p_ed->headTD |= ED_HALTED;
+ ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ }
+#endif
+ }
+ (void)osSemaphoreRelease(semid_cb);
+}
+
+void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
+ uint32_t periodic = 0;
+ uint32_t cnt;
+ uint32_t sqmon;
+ hced_t *p_ed;
+ genelal_ed_t *p_wait_ed = NULL;
+
+ if (ctl_ed.pipe_no == pipe) {
+ p_wait_ed = &ctl_ed;
+ } else if (blk_ed.pipe_no == pipe) {
+ p_wait_ed = &blk_ed;
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ if (p_wait_ed == NULL) {
+ for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+ if (iso_ed[cnt].pipe_no == pipe) {
+ p_wait_ed = &iso_ed[cnt];
+ break;
+ }
+ }
+ }
+#endif
+ if (p_wait_ed == NULL) {
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].pipe_no == pipe) {
+ p_wait_ed = &int_ed[cnt];
+ periodic = 1;
+ break;
+ }
+ }
+ }
+ }
+
+ if (p_wait_ed == NULL) {
+ return;
+ }
+ p_ed = p_wait_ed->p_curr_ed;
+ if (p_ed == NULL) {
+ return;
+ }
+
+ if ((p_ed->control & ED_FORMAT) == 0) {
+ hctd_t *p_td = (hctd_t *)p_wait_ed->p_curr_td;
+
+ if (p_td != NULL) {
+ if (ConditionCode == TD_CC_NOERROR) {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+
+ /* CurrentBufferPointer */
+ p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe];
+ } else {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+ }
+
+ /* DataToggle */
+ sqmon = usbx_host_get_sqmon(pipe);
+ RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
+ if (sqmon == 0) {
+ p_ed->headTD &= ~ED_TOGLE_CARRY;
+ } else {
+ p_ed->headTD |= ED_TOGLE_CARRY;
+ }
+
+ /* ConditionCode */
+ RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if (p_wait_ed == &ctl_ed) {
+ chk_split_trans_setting(&ctl_ed);
+ }
+ chk_genelal_td_done(p_wait_ed);
+
+ if (periodic != 0) {
+ if (chk_genelal_ed(p_wait_ed) != 0) {
+ int_trans(p_wait_ed);
+ } else {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ } else {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ }
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td;
+ uint32_t next_trans = 0;
+
+ if (p_isotd != NULL) {
+ usbx_host_stop_transfer(pipe);
+ if (p_usb_reg->HcFmNumber < 0x0000FFFF) {
+ p_usb_reg->HcFmNumber++;
+ } else {
+ p_usb_reg->HcFmNumber = 0;
+ }
+
+ /* Size of packet */
+ p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
+
+ /* ConditionCode */
+ RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+ RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx],
+ (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC);
+
+ if (usbx_host_CheckAttach() != USB_HOST_ATTACH) {
+ p_ed->headTD |= ED_HALTED;
+ }
+ if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+ p_wait_ed->psw_idx = 0;
+ chk_iso_td_done(p_wait_ed);
+ } else {
+ p_wait_ed->psw_idx++;
+ }
+ if (chk_iso_ed(p_wait_ed) != 0) {
+ if (iso_chk_starting_frame(p_wait_ed) == 0) {
+ iso_trans(p_wait_ed);
+ next_trans = 1;
+ }
+ }
+ if (next_trans == 0) {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ }
+#endif
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h
new file mode 100644
index 000000000..0b1a9ef81
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_H
+#define OHCI_WRAPP_RZ_A1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OHCI_REG_REVISION (0x00) /* HcRevision */
+#define OHCI_REG_CONTROL (0x04) /* HcControl */
+#define OHCI_REG_COMMANDSTATUS (0x08) /* HcCommandStatus */
+#define OHCI_REG_INTERRUPTSTATUS (0x0C) /* HcInterruptStatus */
+#define OHCI_REG_INTERRUPTENABLE (0x10) /* HcInterruptEnable */
+#define OHCI_REG_INTERRUPTDISABLE (0x14) /* HcInterruptDisable */
+#define OHCI_REG_HCCA (0x18) /* HcHCCA */
+#define OHCI_REG_PERIODCURRENTED (0x1C) /* HcPeriodCurrentED */
+#define OHCI_REG_CONTROLHEADED (0x20) /* HcControlHeadED */
+#define OHCI_REG_CONTROLCURRENTED (0x24) /* HcControlCurrentED */
+#define OHCI_REG_BULKHEADED (0x28) /* HcBulkHeadED */
+#define OHCI_REG_BULKCURRENTED (0x2C) /* HcBulkCurrentED */
+#define OHCI_REG_DONEHEADED (0x30) /* HcDoneHead */
+#define OHCI_REG_FMINTERVAL (0x34) /* HcFmInterval */
+#define OHCI_REG_FMREMAINING (0x38) /* HcFmRemaining */
+#define OHCI_REG_FMNUMBER (0x3C) /* HcFmNumber */
+#define OHCI_REG_PERIODICSTART (0x40) /* HcPeriodicStart */
+#define OHCI_REG_LSTHRESHOLD (0x44) /* HcLSThreshold */
+#define OHCI_REG_RHDESCRIPTORA (0x48) /* HcRhDescriptorA */
+#define OHCI_REG_RHDESCRIPTORB (0x4C) /* HcRhDescriptorB */
+#define OHCI_REG_RHSTATUS (0x50) /* HcRhStatus */
+#define OHCI_REG_RHPORTSTATUS1 (0x54) /* HcRhPortStatus1 */
+
+typedef void (usbisr_fnc_t)(void);
+
+extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
+extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
+extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
+extern void ohciwrapp_interrupt(uint32_t int_sense);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_H */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h
new file mode 100644
index 000000000..250c45b66
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H
+#define OHCI_WRAPP_RZ_A1_LOCAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ConditionCode */
+#define TD_CC_NOERROR (0)
+#define TD_CC_CRC (1)
+#define TD_CC_BITSTUFFING (2)
+#define TD_CC_DATATOGGLEMISMATCH (3)
+#define TD_CC_STALL (4)
+#define TD_CC_DEVICENOTRESPONDING (5)
+#define TD_CC_PIDCHECKFAILURE (6)
+#define TD_CC_UNEXPECTEDPID (7)
+#define TD_CC_DATAOVERRUN (8)
+#define TD_CC_DATAUNDERRUN (9)
+#define TD_CC_BUFFEROVERRUN (12)
+#define TD_CC_BUFFERUNDERRUN (13)
+#define TD_CC_NOT_ACCESSED_1 (14)
+#define TD_CC_NOT_ACCESSED_2 (15)
+
+extern void ohciwrapp_loc_Connect(uint32_t type);
+extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_LOCAL_H */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c
new file mode 100644
index 000000000..2a6d126dd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/********************************************************************************************************/
+/* Endpoint Configuration Data Format */
+/********************************************************************************************************/
+/* LINE1: Pipe Window Select Register */
+/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */
+/* LINE2: Pipe Configuration Register */
+/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE3: Pipe Buffer Configuration Register */
+/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */
+/* [ ### SET ### ] */
+/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */
+/* LINE4: Pipe Maxpacket Size Register */
+/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE5: Pipe Cycle Configuration Register (0x6C) */
+/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE6: use FIFO port */
+/* : USB_HOST_CUSE [ ### SET ### ] */
+/* : USB_HOST_D0USE / USB_HOST_D1USE */
+/* : USB_HOST_D0DMA / USB_HOST_D0DMA */
+/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */
+/********************************************************************************************************/
+
+/* Device Address 1 */
+USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE3,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D0USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE6,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE7,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE8,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE9,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE1,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE2,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h
new file mode 100644
index 000000000..70e5c2115
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_H
+#define USB0_HOST_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb0_host_bit_set[];
+extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb0_host_PipeIgnore[];
+extern uint16_t g_usb0_host_PipeTbl[];
+extern uint16_t g_usb0_host_pipe_status[];
+extern uint32_t g_usb0_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t g_usb0_host_DmaInfo[];
+extern uint16_t g_usb0_host_DmaPipe[];
+extern uint16_t g_usb0_host_DmaBval[];
+extern uint16_t g_usb0_host_DmaStatus[];
+
+extern uint16_t g_usb0_host_driver_state;
+extern uint16_t g_usb0_host_ConfigNum;
+extern uint16_t g_usb0_host_CmdStage;
+extern uint16_t g_usb0_host_bchg_flag;
+extern uint16_t g_usb0_host_detach_flag;
+extern uint16_t g_usb0_host_attach_flag;
+
+extern uint16_t g_usb0_host_UsbAddress;
+extern uint16_t g_usb0_host_setUsbAddress;
+extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t g_usb0_host_UsbDeviceSpeed;
+extern uint16_t g_usb0_host_SupportUsbDeviceSpeed;
+
+extern uint16_t g_usb0_host_SavReq;
+extern uint16_t g_usb0_host_SavVal;
+extern uint16_t g_usb0_host_SavIndx;
+extern uint16_t g_usb0_host_SavLen;
+
+extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb0_host_is_hispeed(void);
+uint16_t usb0_host_is_hispeed_enable(void);
+uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_host_write_buffer(uint16_t pipe);
+uint16_t usb0_host_write_buffer_c(uint16_t pipe);
+uint16_t usb0_host_write_buffer_d0(uint16_t pipe);
+uint16_t usb0_host_write_buffer_d1(uint16_t pipe);
+void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_host_read_buffer(uint16_t pipe);
+uint16_t usb0_host_read_buffer_c(uint16_t pipe);
+uint16_t usb0_host_read_buffer_d0(uint16_t pipe);
+uint16_t usb0_host_read_buffer_d1(uint16_t pipe);
+uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb0_host_read_dma(uint16_t pipe);
+void usb0_host_stop_transfer(uint16_t pipe);
+void usb0_host_brdy_int(uint16_t status, uint16_t int_enb);
+void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb0_host_bemp_int(uint16_t status, uint16_t int_enb);
+void usb0_host_setting_interrupt(uint8_t level);
+void usb0_host_reset_module(uint16_t clockmode);
+uint16_t usb0_host_get_buf_size(uint16_t pipe);
+uint16_t usb0_host_get_mxps(uint16_t pipe);
+void usb0_host_enable_brdy_int(uint16_t pipe);
+void usb0_host_disable_brdy_int(uint16_t pipe);
+void usb0_host_clear_brdy_sts(uint16_t pipe);
+void usb0_host_enable_bemp_int(uint16_t pipe);
+void usb0_host_disable_bemp_int(uint16_t pipe);
+void usb0_host_clear_bemp_sts(uint16_t pipe);
+void usb0_host_enable_nrdy_int(uint16_t pipe);
+void usb0_host_disable_nrdy_int(uint16_t pipe);
+void usb0_host_clear_nrdy_sts(uint16_t pipe);
+void usb0_host_set_pid_buf(uint16_t pipe);
+void usb0_host_set_pid_nak(uint16_t pipe);
+void usb0_host_set_pid_stall(uint16_t pipe);
+void usb0_host_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_host_get_pid(uint16_t pipe);
+void usb0_host_set_sqclr(uint16_t pipe);
+void usb0_host_set_sqset(uint16_t pipe);
+void usb0_host_set_csclr(uint16_t pipe);
+void usb0_host_aclrm(uint16_t pipe);
+void usb0_host_set_aclrm(uint16_t pipe);
+void usb0_host_clr_aclrm(uint16_t pipe);
+uint16_t usb0_host_get_sqmon(uint16_t pipe);
+uint16_t usb0_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void usb0_host_init_pipe_status(void);
+int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void usb0_host_StatusStage(void);
+void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void usb0_host_InitModule(void);
+uint16_t usb0_host_CheckAttach(void);
+void usb0_host_UsbDetach(void);
+void usb0_host_UsbDetach2(void);
+void usb0_host_UsbAttach(void);
+uint16_t usb0_host_UsbBusReset(void);
+int32_t usb0_host_UsbResume(void);
+int32_t usb0_host_UsbSuspend(void);
+void usb0_host_Enable_DetachINT(void);
+void usb0_host_Disable_DetachINT(void);
+void usb0_host_UsbStateManager(void);
+
+
+#endif /* USB0_HOST_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h
new file mode 100644
index 000000000..dbdd64d6d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_API_H
+#define USB0_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_interrupt(uint32_t int_sense);
+void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t usb0_api_host_enumeration(uint16_t devadr);
+int32_t usb0_api_host_detach(void);
+int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t usb0_api_host_GetUsbDeviceState(void);
+
+void usb0_api_host_elt_4_4(void);
+void usb0_api_host_elt_4_5(void);
+void usb0_api_host_elt_4_6(void);
+void usb0_api_host_elt_4_7(void);
+void usb0_api_host_elt_4_8(void);
+void usb0_api_host_elt_4_9(void);
+void usb0_api_host_elt_get_desc(void);
+
+void usb0_host_EL_ModeInit(void);
+void usb0_host_EL_SetUACT(void);
+void usb0_host_EL_ClearUACT(void);
+void usb0_host_EL_SetTESTMODE(uint16_t mode);
+void usb0_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t usb0_host_EL_GetINTSTS1(void);
+void usb0_host_EL_UsbBusReset(void);
+void usb0_host_EL_UsbAttach(void);
+void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb0_host_EL_StatusStage(void);
+void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t usb0_host_EL_UsbSuspend(void);
+int32_t usb0_host_EL_UsbResume(void);
+
+#if 0 /* prototype in devdrv_usb_host_api.h */
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_host_attach(void);
+void Userdef_USB_usb0_host_detach(void);
+void Userdef_USB_usb0_host_delay_1ms(void);
+void Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_host_delay_500ns(void);
+void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+#endif
+
+#endif /* USB0_HOST_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h
new file mode 100644
index 000000000..3e5e40c3b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_DMACDRV_H
+#define USB0_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC1_Open(uint32_t req);
+void usb0_host_DMAC1_Close(uint32_t * remain);
+void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC2_Open(uint32_t req);
+void usb0_host_DMAC2_Close(uint32_t * remain);
+void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif /* USB0_HOST_DMACDRV_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c
new file mode 100644
index 000000000..bb7b68f2b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d1(uint16_t pipe);
+
+static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb0_host_clear_transaction_counter(uint16_t pipe);
+static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ case USB_HOST_D0FIFO_DMA:
+ usefifo = USB_HOST_D0USE;
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ case USB_HOST_D1FIFO_DMA:
+ usefifo = USB_HOST_D1USE;
+ break;
+
+ default:
+ usefifo = USB_HOST_CUSE;
+ break;
+ };
+
+ usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+ usb0_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ status = usb0_host_write_buffer(pipe);
+
+ if (status != USB_HOST_FIFOERROR)
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ status = usb0_host_write_buffer_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ status = usb0_host_write_buffer_d1(pipe);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ status = usb0_host_write_dma_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ status = usb0_host_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb0_host_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write */
+ case USB_HOST_WRITESHRT: /* End of data write */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+
+ /* for last transfer */
+ usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEDMA: /* DMA write */
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ }
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.CFIFOCTR,
+ USB_CFIFOCTR_BVAL_SHIFT,
+ USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ usb0_host_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ usb0_host_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb0_host_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d0(pipe);
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) !=0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ status = usb0_host_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READZERO: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb0_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOCTR;
+ break;
+
+ case USB_HOST_D0USE:
+ case USB_HOST_D0DMA:
+ buffer = USB200.D0FIFOCTR;
+ break;
+
+ case USB_HOST_D1USE:
+ case USB_HOST_D1DMA:
+ buffer = USB200.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.(DFACC)
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D0FIFO.UINT32;
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t Pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+ return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit
+* : : USB_HOST_BITMBW_16 16bit
+* : : USB_HOST_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb0_host_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_HOST_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_HOST_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_HOST_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+
+ usb0_host_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ default:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+ usb0_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d1
+* Description : Sets the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c
new file mode 100644
index 000000000..57e6e5a08
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+/* #include "usb0_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_host_dmaint(uint16_t fifo);
+static void usb0_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D0FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D1FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D0FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D1FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_HOST_D0FIFO
+* : ; USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb0_host_DmaPipe[fifo];
+
+ if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+ {
+ usb0_host_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb0_host_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint16_t useport;
+ uint32_t remain;
+
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb0_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c
new file mode 100644
index 000000000..0dbce8e91
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_brdy_int
+* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t status ; BRDYSTS Register Value
+* : uint16_t int_enb ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb0_host_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB200.BRDYSTS = (uint16_t)~pipebit;
+ USB200.BEMPSTS = (uint16_t)~pipebit;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb0_host_read_buffer(pipe);
+ }
+ else
+ {
+ usb0_host_write_buffer(pipe);
+ }
+ }
+#if(1) /* ohci_wrapp */
+ switch (g_usb0_host_pipe_status[pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+ break;
+ case USB_HOST_PIPE_NORES:
+ case USB_HOST_PIPE_STALL:
+ case USB_HOST_PIPE_ERROR:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+#endif
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_nrdy_int
+* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+ g_usb0_host_PipeIgnore[pipe]++;
+
+ if (g_usb0_host_PipeIgnore[pipe] == 3)
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ }
+ else
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+#endif
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_bemp_int
+* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ inbuf = usb0_host_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb0_host_disable_bemp_int(pipe);
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c
new file mode 100644
index 000000000..eb3359e28
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c
@@ -0,0 +1,1580 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "MBRZA1H.h" /* INTC Driver Header */
+#else
+#include "devdrv_intc.h" /* INTC Driver Header */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed
+* : USB_HOST_FULL_SPEED ; Full-Speed
+* : USB_HOST_LOW_SPEED ; Low-Speed
+* : USB_HOST_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_HSMODE)
+ {
+ speed = USB_HOST_HIGH_SPEED;
+ }
+ else if (rhst == USB_HOST_FSMODE)
+ {
+ speed = USB_HOST_FULL_SPEED;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ speed = USB_HOST_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_HOST_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+* : USB_HOST_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = USB_HOST_NO;
+
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE) == 1)
+ {
+ ret = USB_HOST_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_HOST_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+
+ Userdef_USB_usb0_host_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_pid_stall (uint16_t pipe)
+{
+ usb0_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_host_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_host_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_HOST_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_aclrm (uint16_t pipe)
+{
+ usb0_host_set_aclrm(pipe);
+ usb0_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_host_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb0_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+
+ InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt);
+ GIC_SetPriority(USBI0_IRQn, level);
+ GIC_EnableIRQ(USBI0_IRQn);
+
+ d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#else
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI0, level);
+ R_INTC_Enable(INTC_ID_USBI0);
+
+ d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_host_reset_module (uint16_t clockmode)
+{
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_host_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_host_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+
+ return size;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c
new file mode 100644
index 000000000..2f8ef12a3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlTransStart
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *Buf ; Data buffer
+* Return Value : DEVDRV_SUCCESS ; SUCCESS
+* : DEVDRV_ERROR ; ERROR
+*******************************************************************************/
+int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+ uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+ if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 1,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+ if (Len == 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
+ }
+ else
+ {
+ if ((Req & 0x0080) != 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
+ }
+ else
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
+ }
+ }
+
+ g_usb0_host_SavReq = Req; /* save request */
+ g_usb0_host_SavVal = Val;
+ g_usb0_host_SavIndx = Indx;
+ g_usb0_host_SavLen = Len;
+ }
+ else
+ {
+ if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val)
+ || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
+ {
+ return DEVDRV_ERROR;
+ }
+ }
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ /* --------------- SETUP STAGE --------------- */
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+ usb0_host_SetupStage(Req, Val, Indx, Len);
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_READ:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ default:
+ break;
+ }
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ }
+ break;
+
+ /* --------------- DATA STAGE --------------- */
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
+ break;
+
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlReadStart((uint32_t)Len, Buf);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ /* --------------- STATUS STAGE --------------- */
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+ usb0_host_StatusStage();
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
+ usb0_host_set_pid_nak(USB_HOST_PIPE0);
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ default:
+ break;
+ }
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_SetupStage
+* Description : Executes USB control transfer/set up stage.
+* Arguments : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
+ USB200.USBREQ = Req;
+ USB200.USBVAL = Val;
+ USB200.USBINDX = Indx;
+ USB200.USBLENG = Len;
+ USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_StatusStage
+* Description : Executes USB control transfer/status stage.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_StatusStage (void)
+{
+ uint8_t Buf1[16];
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlWriteStart
+* Description : Executes USB control transfer/data stage(write).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+* : USB_HOST_WRITEEND ; End of data write (not null)
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t EndFlag_K;
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 1,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0);
+ /* Host Control sequence */
+ switch (EndFlag_K)
+ {
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write (not null) */
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+ return (EndFlag_K); /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlReadStart
+* Description : Executes USB control transfer/data stage(read).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 0,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c
new file mode 100644
index 000000000..baa39adaa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_host_init
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint8_t int_level : USB Module interrupt level
+* : USBU16 mode : USB_HOST_HIGH_SPEED
+* : USB_HOST_FULL_SPEED
+* : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+* : USB_HOST_ATTACH
+* : USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ uint16_t connect;
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ g_usb0_host_SupportUsbDeviceSpeed = mode;
+
+ usb0_host_setting_interrupt(int_level);
+ usb0_host_reset_module(clockmode);
+
+ g_usb0_host_bchg_flag = USB_HOST_NO;
+ g_usb0_host_detach_flag = USB_HOST_NO;
+ g_usb0_host_attach_flag = USB_HOST_NO;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_InitModule();
+
+ connect = usb0_host_CheckAttach();
+
+ if (connect == USB_HOST_ATTACH)
+ {
+ g_usb0_host_attach_flag = USB_HOST_YES;
+ }
+ else
+ {
+ usb0_host_UsbDetach2();
+ }
+
+ return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_enumeration
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
+* : DEVDRV_SUCCESS : device enumeration success
+* : DEVDRV_ERROR : device enumeration error
+*******************************************************************************/
+int32_t usb0_api_host_enumeration (uint16_t devadr)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ g_usb0_host_setUsbAddress = devadr;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = DEVDRV_USBH_DETACH_ERR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = DEVDRV_SUCCESS;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_detach
+* Description : USB detach routine
+* Arguments : none
+* Return Value : USB_HOST_DETACH : USB detach
+* : USB_HOST_ATTACH : USB attach
+* : DEVDRV_ERROR : error
+*******************************************************************************/
+int32_t usb0_api_host_detach (void)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = USB_HOST_DETACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = USB_HOST_ATTACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_in
+* Description : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_receive_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_out
+* Description : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_send_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_control_transfer
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *buf ; Buffer
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_USBH_DETACH_ERR ; device detach
+* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+* : DEVDRV_USBH_STALL ; STALL
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+ uint16_t Len, uint8_t * Buf)
+{
+ int32_t ret;
+
+ do
+ {
+ ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+ if (ret == DEVDRV_SUCCESS)
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+ && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+ }
+ else
+ {
+ return DEVDRV_ERROR;
+ }
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[USB_HOST_PIPE0])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_CTRL_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_set_endpoint
+* Description : Sets end point on the information specified in the argument.
+* Arguments : uint16_t devadr ; device address
+* : uint8_t *configdescriptor ; device configration descriptor
+* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+ uint16_t ret;
+ uint32_t end_point;
+ uint32_t offset;
+ uint32_t totalLength;
+ USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+ /* End Point Search */
+ end_point = 0;
+ offset = configdescriptor[0];
+ totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+ do
+ {
+ if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+ {
+ pipe_table = &user_table[end_point];
+
+ if (pipe_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+ if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ ++end_point;
+ }
+
+ /* Next End Point Search */
+ offset += configdescriptor[offset];
+
+ } while (offset < totalLength);
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint_pipe
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : uint16_t pipe_sel : Pipe Number
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ if (user_table->pipe_number == pipe_sel)
+ {
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+ break;
+ }
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_host_SetEndpointTable
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : uint16_t devadr : device address
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* : uint8_t *Table : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
+* : USB_HOST_DIR_H_OUT ; OUT endpoint
+* : USB_END_POINT_ERROR ; error
+*******************************************************************************/
+uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+ uint16_t PipeCfg;
+ uint16_t PipeMaxp;
+ uint16_t pipe_number;
+ uint16_t ret;
+ uint16_t ret_flag = 0; // avoid warning.
+
+ pipe_number = user_table->pipe_number;
+
+ if (Table[1] != USB_HOST_ENDPOINT_DESC)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ switch (Table[3] & USB_HOST_EP_TYPE)
+ {
+ case USB_HOST_EP_CNTRL:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+
+ case USB_HOST_EP_ISO:
+ if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_ISO;
+ break;
+
+ case USB_HOST_EP_BULK:
+ if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_BULK;
+ break;
+
+ case USB_HOST_EP_INT:
+ if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_INTERRUPT;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Set pipe configuration table */
+ if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= USB_HOST_DIR_H_IN;
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ PipeCfg |= USB_HOST_BFREON;
+#endif
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ ret = USB_HOST_PIPE_IN;
+ }
+ else /* OUT(send) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ }
+ PipeCfg |= USB_HOST_DIR_H_OUT;
+ ret = USB_HOST_PIPE_OUT;
+ }
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+ break;
+
+ case USB_HOST_D0USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+ break;
+
+ case USB_HOST_D1USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+ break;
+
+ case USB_HOST_D0DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+ break;
+
+ case USB_HOST_D1DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Endpoint number set */
+ PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+ g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+ /* Max packet size set */
+ PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+ if (PipeMaxp == 0u)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ /* Set device address */
+ PipeMaxp |= (uint16_t)(devadr << 12);
+
+ user_table->pipe_cfg = PipeCfg;
+ user_table->pipe_max_pktsize = PipeMaxp;
+
+ usb0_host_resetEP(user_table);
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_resetEP
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+ uint16_t pipe;
+
+ /* Host pipe */
+ /* The pipe number of pipe definition table is obtained */
+ pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
+
+ /* FIFO port access pipe is set to initial value */
+ /* The connection with FIFO should be cut before setting the pipe */
+ if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+ /* Pipe to set is set to NAK */
+ usb0_host_set_pid_nak(pipe);
+
+ /* Pipe is set */
+ USB200.PIPESEL = pipe;
+
+ USB200.PIPECFG = tbl->pipe_cfg;
+ USB200.PIPEBUF = tbl->pipe_buf;
+ USB200.PIPEMAXP = tbl->pipe_max_pktsize;
+ USB200.PIPEPERI = tbl->pipe_cycle;
+
+ g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg;
+ g_usb0_host_pipebuf[pipe] = tbl->pipe_buf;
+ g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+ g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+ /* Sequence bit clear */
+ usb0_host_set_sqclr(pipe);
+
+ usb0_host_aclrm(pipe);
+ usb0_host_set_csclr(pipe);
+
+ /* Pipe window selection is set to unused */
+ USB200.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_data_count
+* Description : Get g_usb0_host_data_count[pipe]
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+ if (pipe > USB_HOST_MAX_PIPE_NO)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ *data_count = g_usb0_host_PipeDataSize[pipe];
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c
new file mode 100644
index 000000000..2d1d5f5fc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb0_host_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb0_host_DmaInfo[2];
+
+uint16_t g_usb0_host_DmaPipe[2];
+uint16_t g_usb0_host_DmaBval[2];
+uint16_t g_usb0_host_DmaStatus[2];
+
+uint16_t g_usb0_host_driver_state;
+uint16_t g_usb0_host_ConfigNum;
+uint16_t g_usb0_host_CmdStage;
+uint16_t g_usb0_host_bchg_flag;
+uint16_t g_usb0_host_detach_flag;
+uint16_t g_usb0_host_attach_flag;
+
+uint16_t g_usb0_host_UsbAddress;
+uint16_t g_usb0_host_setUsbAddress;
+uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t g_usb0_host_UsbDeviceSpeed;
+uint16_t g_usb0_host_SupportUsbDeviceSpeed;
+
+uint16_t g_usb0_host_SavReq;
+uint16_t g_usb0_host_SavVal;
+uint16_t g_usb0_host_SavIndx;
+uint16_t g_usb0_host_SavLen;
+
+uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_init_pipe_status
+* Description : Initialize pipe status.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_init_pipe_status (void)
+{
+ uint16_t loop;
+
+ g_usb0_host_ConfigNum = 0;
+
+ for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+ {
+ g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
+ g_usb0_host_PipeDataSize[loop] = 0;
+
+ /* pipe configuration in usb0_host_resetEP() */
+ g_usb0_host_pipecfg[loop] = 0;
+ g_usb0_host_pipebuf[loop] = 0;
+ g_usb0_host_pipemaxp[loop] = 0;
+ g_usb0_host_pipeperi[loop] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c
new file mode 100644
index 000000000..f4e5a27c7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c
@@ -0,0 +1,496 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_interrupt1(void);
+static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt
+* Description : Executes USB interrupt.
+* : Register this function in the USB interrupt handler.
+* : Set CFIF0 in the pipe set before the interrupt after executing
+* : this function.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt (uint32_t int_sense)
+{
+ uint16_t savepipe1;
+ uint16_t savepipe2;
+ uint16_t buffer;
+
+ savepipe1 = USB200.CFIFOSEL;
+ savepipe2 = USB200.PIPESEL;
+ usb0_host_interrupt1();
+
+ /* Control transmission changes ISEL within interruption processing. */
+ /* For this reason, write return of ISEL cannot be performed. */
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+ USB200.CFIFOSEL = buffer;
+ USB200.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt1
+* Description : Execue the USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt1 (void)
+{
+ uint16_t intsts0;
+ uint16_t intsts1;
+ uint16_t intenb0;
+ uint16_t intenb1;
+ uint16_t brdysts;
+ uint16_t nrdysts;
+ uint16_t bempsts;
+ uint16_t brdyenb;
+ uint16_t nrdyenb;
+ uint16_t bempenb;
+ volatile uint16_t dumy_sts;
+
+ intsts0 = USB200.INTSTS0;
+ intsts1 = USB200.INTSTS1;
+ intenb0 = USB200.INTENB0;
+ intenb1 = USB200.INTENB1;
+
+ if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ g_usb0_host_bchg_flag = USB_HOST_YES;
+ }
+ else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+ }
+ else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+ }
+ else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+ && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+ g_usb0_host_detach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_detach();
+
+ usb0_host_UsbDetach2();
+ }
+ else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+ && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+ g_usb0_host_attach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_attach();
+
+ usb0_host_UsbAttach();
+ }
+ else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+ {
+ brdysts = USB200.BRDYSTS;
+ nrdysts = USB200.NRDYSTS;
+ bempsts = USB200.BEMPSTS;
+ brdyenb = USB200.BRDYENB;
+ nrdyenb = USB200.NRDYENB;
+ bempenb = USB200.BEMPENB;
+
+ if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+ {
+ usb0_host_BRDYInterrupt(brdysts, brdyenb);
+ }
+ else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+ {
+ usb0_host_BEMPInterrupt(bempsts, bempenb);
+ }
+ else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+ {
+ usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* Three dummy read for clearing interrupt requests */
+ dumy_sts = USB200.INTSTS0;
+ dumy_sts = USB200.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BRDYInterrupt
+* Description : Executes USB BRDY interrupt.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ }
+ else
+ {
+ usb0_host_brdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_NRDYInterrupt
+* Description : Executes USB NRDY interrupt.
+* Arguments : uint16_t Status ; NRDYSTS Register Value
+* : uint16_t Int_enbl ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else if (pid == USB_HOST_PID_NAK)
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ usb0_host_nrdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BEMPInterrupt
+* Description : Executes USB BEMP interrupt.
+* Arguments : uint16_t Status ; BEMPSTS Register Value
+* : uint16_t Int_enbl ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#endif
+ }
+ }
+ else
+ {
+ usb0_host_bemp_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BEMPSTS;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c
new file mode 100644
index 000000000..4c5f810db
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_EnableINT_Module(void);
+static void usb0_host_Enable_AttachINT(void);
+static void usb0_host_Disable_AttachINT(void);
+static void usb0_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_InitModule
+* Description : Initializes the USB module in USB host module.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_InitModule (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ usb0_host_init_pipe_status();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* HOST mode */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DRPD_SHIFT,
+ USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CheckAttach
+* Description : Returns the USB device connection state.
+* Arguments : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+* : ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb0_host_CheckAttach (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+ uint16_t rhst;
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_UNDECID)
+ {
+ if (buf1 == USB_HOST_FS_JSTS)
+ {
+ if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ return USB_HOST_ATTACH;
+ }
+ else if (buf1 == USB_HOST_LS_JSTS)
+ {
+ /* Low Speed Device */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+ {
+ return USB_HOST_ATTACH;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbAttach
+* Description : Connects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbAttach (void)
+{
+ usb0_host_EnableINT_Module();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Disable_AttachINT();
+ usb0_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach (void)
+{
+ uint16_t pipe;
+ uint16_t devadr;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+
+ /* Terminate all the pipes in which communications on port */
+ /* are currently carried out */
+ for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+ {
+ if (pipe == USB_HOST_PIPE0)
+ {
+ devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_DEVSEL_SHIFT,
+ USB_DCPMAXP_DEVSEL);
+ }
+ else
+ {
+ devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+ }
+
+ if (devadr == g_usb0_host_UsbAddress)
+ {
+ usb0_host_stop_transfer(pipe);
+ }
+
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+ }
+ }
+
+ g_usb0_host_ConfigNum = 0;
+ g_usb0_host_UsbAddress = 0;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach2
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach2 (void)
+{
+ usb0_host_Disable_DetachINT();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbBusReset
+* Description : Issues the USB bus reset signal.
+* Arguments : none
+* Return Value : uint16_t ; RHST
+*******************************************************************************/
+uint16_t usb0_host_UsbBusReset (void)
+{
+ uint16_t buffer;
+ uint16_t loop;
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_USBRST_SHIFT,
+ USB_DVSTCTR0_USBRST);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(50);
+
+ buffer = USB200.DVSTCTR0;
+ buffer &= (uint16_t)(~(USB_HOST_BITRST));
+ buffer |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buffer;
+
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
+ {
+ buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (buffer == USB_HOST_HSPROC)
+ {
+ Userdef_USB_usb0_host_delay_xms(10);
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbResume
+* Description : Issues the USB resume signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS
+* : ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb0_host_UsbResume (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+ {
+ /* not SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_RESUME_SHIFT,
+ USB_DVSTCTR0_RESUME);
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ buf = USB200.DVSTCTR0;
+ buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+ buf |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buf;
+
+ g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbSuspend
+* Description : Issues the USB suspend signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
+* : ; DEVDRV_ERROR :SUSPEND
+*******************************************************************************/
+int32_t usb0_host_UsbSuspend (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+ {
+ /* SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(5);
+
+ buf = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+ {
+ usb0_host_UsbDetach();
+ }
+ else
+ {
+ g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_DetachINT
+* Description : Enables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_DetachINT
+* Description : Disables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_AttachINT
+* Description : Enables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_AttachINT
+* Description : Disables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_BchgINT
+* Description : Disables the USB bus change detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_BchgINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_devadd
+* Description : DEVADDn register is set by specified value
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : Set value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_devadd
+* Description : DEVADDn register is obtained
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *devadd = *ptr;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_EnableINT_Module
+* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+* : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_EnableINT_Module (void)
+{
+ uint16_t buf;
+
+ buf = USB200.INTENB0;
+ buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+ USB200.INTENB0 = buf;
+
+ buf = USB200.INTENB1;
+ buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+ USB200.INTENB1 = buf;
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0);
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c
new file mode 100644
index 000000000..8f081a618
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID, AM,LVL,REQD */
+ { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC1_CHCFG_n_DAD_SHIFT,
+ DMAC1_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC1_CHCFG_n_SAD_SHIFT,
+ DMAC1_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->dst_size,
+ DMAC1_CHCFG_n_DDS_SHIFT,
+ DMAC1_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->src_size,
+ DMAC1_CHCFG_n_SDS_SHIFT,
+ DMAC1_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DMS_SHIFT,
+ DMAC1_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSEL_SHIFT,
+ DMAC1_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_SBE_SHIFT,
+ DMAC1_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DEM_SHIFT,
+ DMAC1_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_TM_SHIFT,
+ DMAC1_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_SEL_SHIFT,
+ DMAC1_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_HIEN_SHIFT,
+ DMAC1_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_LOEN_SHIFT,
+ DMAC1_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC1_CHCFG_n_AM_SHIFT,
+ DMAC1_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC1_CHCFG_n_LVL_SHIFT,
+ DMAC1_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ req_direction,
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC01_DMARS_CH1_RID_SHIFT,
+ DMAC01_DMARS_CH1_RID);
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC01_DMARS_CH1_MID_SHIFT,
+ DMAC01_DMARS_CH1_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Open
+* Description : Enables DMAC channel 1 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC1_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SETEN_SHIFT,
+ DMAC1_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_STG_SHIFT,
+ DMAC1_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Close
+* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_CLREN_SHIFT,
+ DMAC1_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 1 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 1 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_SR_SHIFT,
+ DMAC1_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC2_CHCFG_n_DAD_SHIFT,
+ DMAC2_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC2_CHCFG_n_SAD_SHIFT,
+ DMAC2_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->dst_size,
+ DMAC2_CHCFG_n_DDS_SHIFT,
+ DMAC2_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->src_size,
+ DMAC2_CHCFG_n_SDS_SHIFT,
+ DMAC2_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DMS_SHIFT,
+ DMAC2_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSEL_SHIFT,
+ DMAC2_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_SBE_SHIFT,
+ DMAC2_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DEM_SHIFT,
+ DMAC2_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_TM_SHIFT,
+ DMAC2_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 2,
+ DMAC2_CHCFG_n_SEL_SHIFT,
+ DMAC2_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_HIEN_SHIFT,
+ DMAC2_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_LOEN_SHIFT,
+ DMAC2_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC2_CHCFG_n_AM_SHIFT,
+ DMAC2_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC2_CHCFG_n_LVL_SHIFT,
+ DMAC2_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ req_direction,
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH2_RID_SHIFT,
+ DMAC23_DMARS_CH2_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH2_MID_SHIFT,
+ DMAC23_DMARS_CH2_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Open
+* Description : Enables DMAC channel 2 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC2_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SETEN_SHIFT,
+ DMAC2_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_STG_SHIFT,
+ DMAC2_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Close
+* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_CLREN_SHIFT,
+ DMAC2_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 2 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 2 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_SR_SHIFT,
+ DMAC2_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c
new file mode 100644
index 000000000..db0b4cfd1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb0_host.h"
+#include "MBRZA1H.h" /* INTC Driver Header */
+#include "usb0_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_attach (void)
+{
+// printf("\n");
+// printf("channel 0 attach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_detach (void)
+{
+// printf("\n");
+// printf("channel 0 detach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_1ms (void)
+{
+ osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_xms (uint32_t msec)
+{
+ osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb0_host_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_host_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_HOST_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_HOST_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC1 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC2 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma0
+* Description : Disables DMA transfer.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+* Notice : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC1_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC2_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_notice
+* Description : Notice of USER
+* Arguments : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_notice (const char * format)
+{
+// printf(format);
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_user_rdy
+* Description : This function notify a user and wait for trigger
+* Arguments : const char *format
+* : uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data)
+{
+// printf(format, data);
+ getchar();
+
+ return;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h
new file mode 100644
index 000000000..1759e7038
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_H
+#define USB1_HOST_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb1_host_bit_set[];
+extern uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb1_host_PipeIgnore[];
+extern uint16_t g_usb1_host_PipeTbl[];
+extern uint16_t g_usb1_host_pipe_status[];
+extern uint32_t g_usb1_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t g_usb1_host_DmaInfo[];
+extern uint16_t g_usb1_host_DmaPipe[];
+extern uint16_t g_usb1_host_DmaBval[];
+extern uint16_t g_usb1_host_DmaStatus[];
+
+extern uint16_t g_usb1_host_driver_state;
+extern uint16_t g_usb1_host_ConfigNum;
+extern uint16_t g_usb1_host_CmdStage;
+extern uint16_t g_usb1_host_bchg_flag;
+extern uint16_t g_usb1_host_detach_flag;
+extern uint16_t g_usb1_host_attach_flag;
+
+extern uint16_t g_usb1_host_UsbAddress;
+extern uint16_t g_usb1_host_setUsbAddress;
+extern uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t g_usb1_host_UsbDeviceSpeed;
+extern uint16_t g_usb1_host_SupportUsbDeviceSpeed;
+
+extern uint16_t g_usb1_host_SavReq;
+extern uint16_t g_usb1_host_SavVal;
+extern uint16_t g_usb1_host_SavIndx;
+extern uint16_t g_usb1_host_SavLen;
+
+extern uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb1_host_is_hispeed(void);
+uint16_t usb1_host_is_hispeed_enable(void);
+uint16_t usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_host_write_buffer(uint16_t pipe);
+uint16_t usb1_host_write_buffer_c(uint16_t pipe);
+uint16_t usb1_host_write_buffer_d0(uint16_t pipe);
+uint16_t usb1_host_write_buffer_d1(uint16_t pipe);
+void usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_host_read_buffer(uint16_t pipe);
+uint16_t usb1_host_read_buffer_c(uint16_t pipe);
+uint16_t usb1_host_read_buffer_d0(uint16_t pipe);
+uint16_t usb1_host_read_buffer_d1(uint16_t pipe);
+uint16_t usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb1_host_read_dma(uint16_t pipe);
+void usb1_host_stop_transfer(uint16_t pipe);
+void usb1_host_brdy_int(uint16_t status, uint16_t int_enb);
+void usb1_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb1_host_bemp_int(uint16_t status, uint16_t int_enb);
+void usb1_host_setting_interrupt(uint8_t level);
+void usb1_host_reset_module(uint16_t clockmode);
+uint16_t usb1_host_get_buf_size(uint16_t pipe);
+uint16_t usb1_host_get_mxps(uint16_t pipe);
+void usb1_host_enable_brdy_int(uint16_t pipe);
+void usb1_host_disable_brdy_int(uint16_t pipe);
+void usb1_host_clear_brdy_sts(uint16_t pipe);
+void usb1_host_enable_bemp_int(uint16_t pipe);
+void usb1_host_disable_bemp_int(uint16_t pipe);
+void usb1_host_clear_bemp_sts(uint16_t pipe);
+void usb1_host_enable_nrdy_int(uint16_t pipe);
+void usb1_host_disable_nrdy_int(uint16_t pipe);
+void usb1_host_clear_nrdy_sts(uint16_t pipe);
+void usb1_host_set_pid_buf(uint16_t pipe);
+void usb1_host_set_pid_nak(uint16_t pipe);
+void usb1_host_set_pid_stall(uint16_t pipe);
+void usb1_host_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_host_get_pid(uint16_t pipe);
+void usb1_host_set_sqclr(uint16_t pipe);
+void usb1_host_set_sqset(uint16_t pipe);
+void usb1_host_set_csclr(uint16_t pipe);
+void usb1_host_aclrm(uint16_t pipe);
+void usb1_host_set_aclrm(uint16_t pipe);
+void usb1_host_clr_aclrm(uint16_t pipe);
+uint16_t usb1_host_get_sqmon(uint16_t pipe);
+uint16_t usb1_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void usb1_host_init_pipe_status(void);
+int32_t usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void usb1_host_StatusStage(void);
+void usb1_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void usb1_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void usb1_host_InitModule(void);
+uint16_t usb1_host_CheckAttach(void);
+void usb1_host_UsbDetach(void);
+void usb1_host_UsbDetach2(void);
+void usb1_host_UsbAttach(void);
+uint16_t usb1_host_UsbBusReset(void);
+int32_t usb1_host_UsbResume(void);
+int32_t usb1_host_UsbSuspend(void);
+void usb1_host_Enable_DetachINT(void);
+void usb1_host_Disable_DetachINT(void);
+void usb1_host_UsbStateManager(void);
+
+
+#endif /* USB1_HOST_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h
new file mode 100644
index 000000000..63ae6d650
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_API_H
+#define USB1_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_interrupt(uint32_t int_sense);
+void usb1_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb1_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t usb1_api_host_enumeration(uint16_t devadr);
+int32_t usb1_api_host_detach(void);
+int32_t usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table);
+int32_t usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t usb1_api_host_GetUsbDeviceState(void);
+
+void usb1_api_host_elt_4_4(void);
+void usb1_api_host_elt_4_5(void);
+void usb1_api_host_elt_4_6(void);
+void usb1_api_host_elt_4_7(void);
+void usb1_api_host_elt_4_8(void);
+void usb1_api_host_elt_4_9(void);
+void usb1_api_host_elt_get_desc(void);
+
+void usb1_host_EL_ModeInit(void);
+void usb1_host_EL_SetUACT(void);
+void usb1_host_EL_ClearUACT(void);
+void usb1_host_EL_SetTESTMODE(uint16_t mode);
+void usb1_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t usb1_host_EL_GetINTSTS1(void);
+void usb1_host_EL_UsbBusReset(void);
+void usb1_host_EL_UsbAttach(void);
+void usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb1_host_EL_StatusStage(void);
+void usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t usb1_host_EL_UsbSuspend(void);
+int32_t usb1_host_EL_UsbResume(void);
+
+#if 0 /* prototype in devdrv_usb_host_api.h */
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_host_attach(void);
+void Userdef_USB_usb1_host_detach(void);
+void Userdef_USB_usb1_host_delay_1ms(void);
+void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_host_delay_500ns(void);
+void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+#endif
+
+#endif /* USB1_HOST_API_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h
new file mode 100644
index 000000000..a4c3943d7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_DMACDRV_H
+#define USB1_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC3_Open(uint32_t req);
+void usb1_host_DMAC3_Close(uint32_t *remain);
+void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC4_Open(uint32_t req);
+void usb1_host_DMAC4_Close(uint32_t *remain);
+void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif /* USB1_HOST_DMACDRV_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c
new file mode 100644
index 000000000..aa76d6143
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void usb1_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d1(uint16_t pipe);
+
+static void usb1_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb1_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb1_host_clear_transaction_counter(uint16_t pipe);
+static void usb1_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ usb1_host_clear_bemp_sts(pipe);
+ usb1_host_clear_brdy_sts(pipe);
+ usb1_host_clear_nrdy_sts(pipe);
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ case USB_HOST_D0FIFO_DMA:
+ usefifo = USB_HOST_D0USE;
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ case USB_HOST_D1FIFO_DMA:
+ usefifo = USB_HOST_D1USE;
+ break;
+
+ default:
+ usefifo = USB_HOST_CUSE;
+ break;
+ };
+
+ usb1_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+ usb1_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ status = usb1_host_write_buffer(pipe);
+
+ if (status != USB_HOST_FIFOERROR)
+ {
+ usb1_host_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ status = usb1_host_write_buffer_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ status = usb1_host_write_buffer_d1(pipe);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ status = usb1_host_write_dma_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ status = usb1_host_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb1_host_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb1_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write */
+ case USB_HOST_WRITESHRT: /* End of data write */
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ usb1_host_clear_nrdy_sts(pipe);
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+
+ /* for last transfer */
+ usb1_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEDMA: /* DMA write */
+ usb1_host_clear_nrdy_sts(pipe);
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ }
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.CFIFOCTR,
+ USB_CFIFOCTR_BVAL_SHIFT,
+ USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;
+ }
+
+ dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb1_host_data_count[pipe] = 0;
+ g_usb1_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;
+ }
+
+ dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb1_host_data_count[pipe] = 0;
+ g_usb1_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb1_host_clear_bemp_sts(pipe);
+ usb1_host_clear_brdy_sts(pipe);
+ usb1_host_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb1_host_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb1_host_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ usb1_host_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ usb1_host_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb1_host_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = 0;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_host_read_dma(pipe);
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = 0;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_host_read_dma(pipe);
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ status = usb1_host_read_buffer_d0(pipe);
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ status = usb1_host_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb1_host_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) !=0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ status = usb1_host_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb1_host_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READZERO: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ }
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ }
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ g_usb1_host_data_pointer[pipe] += count;
+ g_usb1_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ g_usb1_host_data_pointer[pipe] += count;
+ g_usb1_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb1_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOCTR;
+ break;
+
+ case USB_HOST_D0USE:
+ case USB_HOST_D0DMA:
+ buffer = USB201.D0FIFOCTR;
+ break;
+
+ case USB_HOST_D1USE:
+ case USB_HOST_D1DMA:
+ buffer = USB201.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb1_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB201.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB201.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.(DFACC)
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb1_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB201.D0FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D0FIFO.UINT32;
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB201.D1FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.CFIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D0FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t Pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D1FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+ return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb1_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit
+* : : USB_HOST_BITMBW_16 16bit
+* : : USB_HOST_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb1_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb1_host_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_HOST_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_HOST_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_HOST_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+
+ usb1_host_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ default:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb1_host_disable_brdy_int(pipe);
+ usb1_host_disable_nrdy_int(pipe);
+ usb1_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+ usb1_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d1
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c
new file mode 100644
index 000000000..6c8a5f9d7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+/* #include "usb1_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_host_dmaint(uint16_t fifo);
+static void usb1_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB201.D0FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+ g_usb1_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB201.D1FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+ g_usb1_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb1_host_dmaint(USB_HOST_D0FIFO);
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb1_host_dmaint(USB_HOST_D1FIFO);
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_HOST_D0FIFO
+* : ; USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb1_host_DmaPipe[fifo];
+
+ if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+ {
+ usb1_host_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb1_host_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb1_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb1_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint16_t useport;
+ uint32_t remain;
+
+ useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+
+ if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+
+ if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb1_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c
new file mode 100644
index 000000000..503ec7a13
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_brdy_int
+* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t status ; BRDYSTS Register Value
+* : uint16_t int_enb ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb1_host_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB201.BRDYSTS = (uint16_t)~pipebit;
+ USB201.BEMPSTS = (uint16_t)~pipebit;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+ {
+ usb1_host_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_host_read_dma(pipe);
+ usb1_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+ {
+ usb1_host_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_host_read_dma(pipe);
+ usb1_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb1_host_read_buffer(pipe);
+ }
+ else
+ {
+ usb1_host_write_buffer(pipe);
+ }
+ }
+#if(1) /* ohci_wrapp */
+ switch (g_usb1_host_pipe_status[pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+ break;
+ case USB_HOST_PIPE_NORES:
+ case USB_HOST_PIPE_STALL:
+ case USB_HOST_PIPE_ERROR:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+#endif
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_nrdy_int
+* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+ {
+ pid = usb1_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+ g_usb1_host_PipeIgnore[pipe]++;
+
+ if (g_usb1_host_PipeIgnore[pipe] == 3)
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ }
+ else
+ {
+ usb1_host_set_pid_buf(pipe);
+ }
+#endif
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_bemp_int
+* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+ {
+ pid = usb1_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ inbuf = usb1_host_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb1_host_disable_bemp_int(pipe);
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c
new file mode 100644
index 000000000..b242794fa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c
@@ -0,0 +1,1598 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "MBRZA1H.h" /* INTC Driver Header */
+#else
+#include "devdrv_intc.h" /* INTC Driver Header */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB201.BRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB201.BRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB201.BRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB201.BEMPENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB201.BEMPENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB201.BEMPSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB201.NRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB201.NRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB201.NRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed
+* : USB_HOST_FULL_SPEED ; Full-Speed
+* : USB_HOST_LOW_SPEED ; Low-Speed
+* : USB_HOST_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_HSMODE)
+ {
+ speed = USB_HOST_HIGH_SPEED;
+ }
+ else if (rhst == USB_HOST_FSMODE)
+ {
+ speed = USB_HOST_FULL_SPEED;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ speed = USB_HOST_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_HOST_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+* : USB_HOST_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = USB_HOST_NO;
+
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE) == 1)
+ {
+ ret = USB_HOST_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb1_host_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb1_host_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_HOST_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+
+ Userdef_USB_usb1_host_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_pid_stall (uint16_t pipe)
+{
+ usb1_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_host_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_host_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_HOST_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_aclrm (uint16_t pipe)
+{
+ usb1_host_set_aclrm(pipe);
+ usb1_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_host_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb1_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+
+ InterruptHandlerRegister(USBI1_IRQn, usb1_host_interrupt);
+ GIC_SetPriority(USBI1_IRQn, level);
+ GIC_EnableIRQ(USBI1_IRQn);
+
+ d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#else
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_host_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI1, level);
+ R_INTC_Enable(INTC_ID_USBI1);
+
+ d0fifo_dmaintid = Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_host_reset_module (uint16_t clockmode)
+{
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB201.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_host_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb1_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_host_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+
+ return size;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c
new file mode 100644
index 000000000..913e5ad9c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlTransStart
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *Buf ; Data buffer
+* Return Value : DEVDRV_SUCCESS ; SUCCESS
+* : DEVDRV_ERROR ; ERROR
+*******************************************************************************/
+int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+ uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+ if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 1,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]);
+
+ if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+ if (Len == 0)
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
+ }
+ else
+ {
+ if ((Req & 0x0080) != 0)
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
+ }
+ else
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
+ }
+ }
+
+ g_usb1_host_SavReq = Req; /* save request */
+ g_usb1_host_SavVal = Val;
+ g_usb1_host_SavIndx = Indx;
+ g_usb1_host_SavLen = Len;
+ }
+ else
+ {
+ if ((g_usb1_host_SavReq != Req) || (g_usb1_host_SavVal != Val)
+ || (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len))
+ {
+ return DEVDRV_ERROR;
+ }
+ }
+
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ /* --------------- SETUP STAGE --------------- */
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+ usb1_host_SetupStage(Req, Val, Indx, Len);
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_READ:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ default:
+ break;
+ }
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ }
+ break;
+
+ /* --------------- DATA STAGE --------------- */
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ usb1_host_CtrlWriteStart((uint32_t)Len, Buf);
+ break;
+
+ case USB_HOST_MODE_READ:
+ usb1_host_CtrlReadStart((uint32_t)Len, Buf);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ /* --------------- STATUS STAGE --------------- */
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+ usb1_host_StatusStage();
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
+ usb1_host_set_pid_nak(USB_HOST_PIPE0);
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ default:
+ break;
+ }
+
+ if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_SetupStage
+* Description : Executes USB control transfer/set up stage.
+* Arguments : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
+ USB201.USBREQ = Req;
+ USB201.USBVAL = Val;
+ USB201.USBINDX = Indx;
+ USB201.USBLENG = Len;
+ USB201.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_StatusStage
+* Description : Executes USB control transfer/status stage.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_StatusStage (void)
+{
+ uint8_t Buf1[16];
+
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_READ:
+ usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ case USB_HOST_MODE_WRITE:
+ usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlWriteStart
+* Description : Executes USB control transfer/data stage(write).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+* : USB_HOST_WRITEEND ; End of data write (not null)
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t EndFlag_K;
+ uint16_t mbw;
+
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb1_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB201.DCPCFG,
+ 1,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0);
+ /* Host Control sequence */
+ switch (EndFlag_K)
+ {
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write (not null) */
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+ usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+ return (EndFlag_K); /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlReadStart
+* Description : Executes USB control transfer/data stage(read).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t mbw;
+
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb1_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB201.DCPCFG,
+ 0,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c
new file mode 100644
index 000000000..260328e04
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_host_init
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint8_t int_level : USB Module interrupt level
+* : USBU16 mode : USB_HOST_HIGH_SPEED
+* : USB_HOST_FULL_SPEED
+* : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+* : USB_HOST_ATTACH
+* : USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ uint16_t connect;
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ g_usb1_host_SupportUsbDeviceSpeed = mode;
+
+ usb1_host_setting_interrupt(int_level);
+ usb1_host_reset_module(clockmode);
+
+ g_usb1_host_bchg_flag = USB_HOST_NO;
+ g_usb1_host_detach_flag = USB_HOST_NO;
+ g_usb1_host_attach_flag = USB_HOST_NO;
+
+ g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+ g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb1_host_InitModule();
+
+ connect = usb1_host_CheckAttach();
+
+ if (connect == USB_HOST_ATTACH)
+ {
+ g_usb1_host_attach_flag = USB_HOST_YES;
+ }
+ else
+ {
+ usb1_host_UsbDetach2();
+ }
+
+ return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_enumeration
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
+* : DEVDRV_SUCCESS : device enumeration success
+* : DEVDRV_ERROR : device enumeration error
+*******************************************************************************/
+int32_t usb1_api_host_enumeration (uint16_t devadr)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ g_usb1_host_setUsbAddress = devadr;
+
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = DEVDRV_USBH_DETACH_ERR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = DEVDRV_SUCCESS;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_detach
+* Description : USB detach routine
+* Arguments : none
+* Return Value : USB_HOST_DETACH : USB detach
+* : USB_HOST_ATTACH : USB attach
+* : DEVDRV_ERROR : error
+*******************************************************************************/
+int32_t usb1_api_host_detach (void)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = USB_HOST_DETACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = USB_HOST_ATTACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_in
+* Description : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb1_host_start_receive_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb1_host_stop_transfer(Pipe);
+
+ g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_out
+* Description : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb1_host_start_send_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb1_host_stop_transfer(Pipe);
+
+ g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_control_transfer
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *buf ; Buffer
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_USBH_DETACH_ERR ; device detach
+* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+* : DEVDRV_USBH_STALL ; STALL
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+ uint16_t Len, uint8_t * Buf)
+{
+ int32_t ret;
+
+ do
+ {
+ ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+ if (ret == DEVDRV_SUCCESS)
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+ && (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+ }
+ else
+ {
+ return DEVDRV_ERROR;
+ }
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[USB_HOST_PIPE0])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_CTRL_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_set_endpoint
+* Description : Sets end point on the information specified in the argument.
+* Arguments : uint16_t devadr ; device address
+* : uint8_t *configdescriptor ; device configration descriptor
+* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+ uint16_t ret;
+ uint32_t end_point;
+ uint32_t offset;
+ uint32_t totalLength;
+ USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+ /* End Point Search */
+ end_point = 0;
+ offset = configdescriptor[0];
+ totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+ do
+ {
+ if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+ {
+ pipe_table = &user_table[end_point];
+
+ if (pipe_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+ if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ ++end_point;
+ }
+
+ /* Next End Point Search */
+ offset += configdescriptor[offset];
+
+ } while (offset < totalLength);
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : uint16_t pipe_sel : Pipe Number
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint_pipe
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ if (user_table->pipe_number == pipe_sel)
+ {
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+ break;
+ }
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_host_SetEndpointTable
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : uint16_t devadr : device address
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* : uint8_t *Table : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
+* : USB_HOST_DIR_H_OUT ; OUT endpoint
+* : USB_END_POINT_ERROR ; error
+*******************************************************************************/
+uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+ uint16_t PipeCfg;
+ uint16_t PipeMaxp;
+ uint16_t pipe_number;
+ uint16_t ret;
+ uint16_t ret_flag = 0; // avoid warning.
+
+ pipe_number = user_table->pipe_number;
+
+ if (Table[1] != USB_HOST_ENDPOINT_DESC)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ switch (Table[3] & USB_HOST_EP_TYPE)
+ {
+ case USB_HOST_EP_CNTRL:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+
+ case USB_HOST_EP_ISO:
+ if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_ISO;
+ break;
+
+ case USB_HOST_EP_BULK:
+ if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_BULK;
+ break;
+
+ case USB_HOST_EP_INT:
+ if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_INTERRUPT;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Set pipe configuration table */
+ if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= USB_HOST_DIR_H_IN;
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ PipeCfg |= USB_HOST_BFREON;
+#endif
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ ret = USB_HOST_PIPE_IN;
+ }
+ else /* OUT(send) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ }
+ PipeCfg |= USB_HOST_DIR_H_OUT;
+ ret = USB_HOST_PIPE_OUT;
+ }
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+ break;
+
+ case USB_HOST_D0USE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+ break;
+
+ case USB_HOST_D1USE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+ break;
+
+ case USB_HOST_D0DMA:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+ break;
+
+ case USB_HOST_D1DMA:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Endpoint number set */
+ PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+ g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+ /* Max packet size set */
+ PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+ if (PipeMaxp == 0u)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ /* Set device address */
+ PipeMaxp |= (uint16_t)(devadr << 12);
+
+ user_table->pipe_cfg = PipeCfg;
+ user_table->pipe_max_pktsize = PipeMaxp;
+
+ usb1_host_resetEP(user_table);
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_resetEP
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+ uint16_t pipe;
+
+ /* Host pipe */
+ /* The pipe number of pipe definition table is obtained */
+ pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
+
+ /* FIFO port access pipe is set to initial value */
+ /* The connection with FIFO should be cut before setting the pipe */
+ if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb1_host_disable_brdy_int(pipe);
+ usb1_host_disable_nrdy_int(pipe);
+ usb1_host_disable_bemp_int(pipe);
+
+ /* Pipe to set is set to NAK */
+ usb1_host_set_pid_nak(pipe);
+
+ /* Pipe is set */
+ USB201.PIPESEL = pipe;
+
+ USB201.PIPECFG = tbl->pipe_cfg;
+ USB201.PIPEBUF = tbl->pipe_buf;
+ USB201.PIPEMAXP = tbl->pipe_max_pktsize;
+ USB201.PIPEPERI = tbl->pipe_cycle;
+
+ g_usb1_host_pipecfg[pipe] = tbl->pipe_cfg;
+ g_usb1_host_pipebuf[pipe] = tbl->pipe_buf;
+ g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+ g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+ /* Sequence bit clear */
+ usb1_host_set_sqclr(pipe);
+
+ usb1_host_aclrm(pipe);
+ usb1_host_set_csclr(pipe);
+
+ /* Pipe window selection is set to unused */
+ USB201.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_data_count
+* Description : Get g_usb0_host_data_count[pipe]
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+ if (pipe > USB_HOST_MAX_PIPE_NO)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ *data_count = g_usb1_host_PipeDataSize[pipe];
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c
new file mode 100644
index 000000000..245da23af
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb1_host_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb1_host_DmaInfo[2];
+
+uint16_t g_usb1_host_DmaPipe[2];
+uint16_t g_usb1_host_DmaBval[2];
+uint16_t g_usb1_host_DmaStatus[2];
+
+uint16_t g_usb1_host_driver_state;
+uint16_t g_usb1_host_ConfigNum;
+uint16_t g_usb1_host_CmdStage;
+uint16_t g_usb1_host_bchg_flag;
+uint16_t g_usb1_host_detach_flag;
+uint16_t g_usb1_host_attach_flag;
+
+uint16_t g_usb1_host_UsbAddress;
+uint16_t g_usb1_host_setUsbAddress;
+uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t g_usb1_host_UsbDeviceSpeed;
+uint16_t g_usb1_host_SupportUsbDeviceSpeed;
+
+uint16_t g_usb1_host_SavReq;
+uint16_t g_usb1_host_SavVal;
+uint16_t g_usb1_host_SavIndx;
+uint16_t g_usb1_host_SavLen;
+
+uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_init_pipe_status
+* Description : Initialize pipe status.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_init_pipe_status (void)
+{
+ uint16_t loop;
+
+ g_usb1_host_ConfigNum = 0;
+
+ for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+ {
+ g_usb1_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
+ g_usb1_host_PipeDataSize[loop] = 0;
+
+ /* pipe configuration in usb1_host_resetEP() */
+ g_usb1_host_pipecfg[loop] = 0;
+ g_usb1_host_pipebuf[loop] = 0;
+ g_usb1_host_pipemaxp[loop] = 0;
+ g_usb1_host_pipeperi[loop] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c
new file mode 100644
index 000000000..d05b19d0e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c
@@ -0,0 +1,497 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_interrupt1(void);
+static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt
+* Description : Executes USB interrupt.
+* : Register this function in the USB interrupt handler.
+* : Set CFIF0 in the pipe set before the interrupt after executing
+* : this function.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt (uint32_t int_sense)
+{
+ uint16_t savepipe1;
+ uint16_t savepipe2;
+ uint16_t buffer;
+
+ savepipe1 = USB201.CFIFOSEL;
+ savepipe2 = USB201.PIPESEL;
+ usb1_host_interrupt1();
+
+ /* Control transmission changes ISEL within interruption processing. */
+ /* For this reason, write return of ISEL cannot be performed. */
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+ USB201.CFIFOSEL = buffer;
+ USB201.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt1
+* Description : Execue the USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt1 (void)
+{
+ uint16_t intsts0;
+ uint16_t intsts1;
+ uint16_t intenb0;
+ uint16_t intenb1;
+ uint16_t brdysts;
+ uint16_t nrdysts;
+ uint16_t bempsts;
+ uint16_t brdyenb;
+ uint16_t nrdyenb;
+ uint16_t bempenb;
+ volatile uint16_t dumy_sts;
+
+ intsts0 = USB201.INTSTS0;
+ intsts1 = USB201.INTSTS1;
+ intenb0 = USB201.INTENB0;
+ intenb1 = USB201.INTENB1;
+
+ if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ g_usb1_host_bchg_flag = USB_HOST_YES;
+ }
+ else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+ }
+ else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+ }
+ else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+ && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+ g_usb1_host_detach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb1_host_detach();
+
+ usb1_host_UsbDetach2();
+ }
+ else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+ && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+ g_usb1_host_attach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb1_host_attach();
+
+ usb1_host_UsbAttach();
+ }
+ else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+ {
+ brdysts = USB201.BRDYSTS;
+ nrdysts = USB201.NRDYSTS;
+ bempsts = USB201.BEMPSTS;
+ brdyenb = USB201.BRDYENB;
+ nrdyenb = USB201.NRDYENB;
+ bempenb = USB201.BEMPENB;
+
+ if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+ {
+ usb1_host_BRDYInterrupt(brdysts, brdyenb);
+ }
+ else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+ {
+ usb1_host_BEMPInterrupt(bempsts, bempenb);
+ }
+ else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+ {
+ usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* Three dummy read for clearing interrupt requests */
+ dumy_sts = USB201.INTSTS0;
+ dumy_sts = USB201.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BRDYInterrupt
+* Description : Executes USB BRDY interrupt.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#else
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ }
+ else
+ {
+ usb1_host_brdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_NRDYInterrupt
+* Description : Executes USB NRDY interrupt.
+* Arguments : uint16_t Status ; NRDYSTS Register Value
+* : uint16_t Int_enbl ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+ pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+
+ }
+ else if (pid == USB_HOST_PID_NAK)
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ usb1_host_nrdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BEMPInterrupt
+* Description : Executes USB BEMP interrupt.
+* Arguments : uint16_t Status ; BEMPSTS Register Value
+* : uint16_t Int_enbl ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+ pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#else
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#endif
+ }
+ }
+ else
+ {
+ usb1_host_bemp_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.BEMPSTS;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c
new file mode 100644
index 000000000..ea8abf876
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_EnableINT_Module(void);
+static void usb1_host_Enable_AttachINT(void);
+static void usb1_host_Disable_AttachINT(void);
+static void usb1_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_InitModule
+* Description : Initializes the USB module in USB host module.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_InitModule (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ usb1_host_init_pipe_status();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* HOST mode */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DRPD_SHIFT,
+ USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ USB201.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB201.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB201.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CheckAttach
+* Description : Returns the USB device connection state.
+* Arguments : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+* : ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb1_host_CheckAttach (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+ uint16_t rhst;
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_UNDECID)
+ {
+ if (buf1 == USB_HOST_FS_JSTS)
+ {
+ if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ return USB_HOST_ATTACH;
+ }
+ else if (buf1 == USB_HOST_LS_JSTS)
+ {
+ /* Low Speed Device */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+ {
+ return USB_HOST_ATTACH;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbAttach
+* Description : Connects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbAttach (void)
+{
+ usb1_host_EnableINT_Module();
+ usb1_host_Disable_BchgINT();
+ usb1_host_Disable_AttachINT();
+ usb1_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach (void)
+{
+ uint16_t pipe;
+ uint16_t devadr;
+
+ g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+
+ /* Terminate all the pipes in which communications on port */
+ /* are currently carried out */
+ for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+ {
+ if (pipe == USB_HOST_PIPE0)
+ {
+ devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_DEVSEL_SHIFT,
+ USB_DCPMAXP_DEVSEL);
+ }
+ else
+ {
+ devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+ }
+
+ if (devadr == g_usb1_host_UsbAddress)
+ {
+ usb1_host_stop_transfer(pipe);
+ }
+
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+ }
+ }
+
+ g_usb1_host_ConfigNum = 0;
+ g_usb1_host_UsbAddress = 0;
+ g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb1_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach2
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach2 (void)
+{
+ usb1_host_Disable_DetachINT();
+ usb1_host_Disable_BchgINT();
+ usb1_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbBusReset
+* Description : Issues the USB bus reset signal.
+* Arguments : none
+* Return Value : uint16_t ; RHST
+*******************************************************************************/
+uint16_t usb1_host_UsbBusReset (void)
+{
+ uint16_t buffer;
+ uint16_t loop;
+
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_USBRST_SHIFT,
+ USB_DVSTCTR0_USBRST);
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb1_host_delay_xms(50);
+
+ buffer = USB201.DVSTCTR0;
+ buffer &= (uint16_t)(~(USB_HOST_BITRST));
+ buffer |= USB_HOST_BITUACT;
+ USB201.DVSTCTR0 = buffer;
+
+ Userdef_USB_usb1_host_delay_xms(20);
+
+ for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
+ {
+ buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (buffer == USB_HOST_HSPROC)
+ {
+ Userdef_USB_usb1_host_delay_xms(10);
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbResume
+* Description : Issues the USB resume signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS
+* : ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb1_host_UsbResume (void)
+{
+ uint16_t buf;
+
+ if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+ {
+ /* not SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_RESUME_SHIFT,
+ USB_DVSTCTR0_RESUME);
+ Userdef_USB_usb1_host_delay_xms(20);
+
+ buf = USB201.DVSTCTR0;
+ buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+ buf |= USB_HOST_BITUACT;
+ USB201.DVSTCTR0 = buf;
+
+ g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbSuspend
+* Description : Issues the USB suspend signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
+* : ; DEVDRV_ERROR :SUSPEND
+*******************************************************************************/
+int32_t usb1_host_UsbSuspend (void)
+{
+ uint16_t buf;
+
+ if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+ {
+ /* SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb1_host_delay_xms(5);
+
+ buf = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+ {
+ usb1_host_UsbDetach();
+ }
+ else
+ {
+ g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_DetachINT
+* Description : Enables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_DetachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 1,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_DetachINT
+* Description : Disables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_DetachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_AttachINT
+* Description : Enables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_AttachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 1,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_AttachINT
+* Description : Disables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_AttachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_BchgINT
+* Description : Disables the USB bus change detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_BchgINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_devadd
+* Description : DEVADDn register is set by specified value
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : Set value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB201.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB201.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB201.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB201.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB201.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB201.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB201.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB201.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB201.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB201.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB201.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_devadd
+* Description : DEVADDn register is obtained
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB201.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB201.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB201.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB201.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB201.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB201.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB201.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB201.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB201.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB201.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB201.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *devadd = *ptr;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_EnableINT_Module
+* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+* : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_EnableINT_Module (void)
+{
+ uint16_t buf;
+
+ buf = USB201.INTENB0;
+ buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+ USB201.INTENB0 = buf;
+
+ buf = USB201.INTENB1;
+ buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+ USB201.INTENB1 = buf;
+
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0);
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c
new file mode 100644
index 000000000..b3cc2e6e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID, AM,LVL,REQD */
+ { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 3.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 3 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC3_CHCFG_n_DAD_SHIFT,
+ DMAC3_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC3_CHCFG_n_SAD_SHIFT,
+ DMAC3_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->dst_size,
+ DMAC3_CHCFG_n_DDS_SHIFT,
+ DMAC3_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->src_size,
+ DMAC3_CHCFG_n_SDS_SHIFT,
+ DMAC3_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DMS_SHIFT,
+ DMAC3_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSEL_SHIFT,
+ DMAC3_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_SBE_SHIFT,
+ DMAC3_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DEM_SHIFT,
+ DMAC3_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_TM_SHIFT,
+ DMAC3_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 3,
+ DMAC3_CHCFG_n_SEL_SHIFT,
+ DMAC3_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_HIEN_SHIFT,
+ DMAC3_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_LOEN_SHIFT,
+ DMAC3_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC3_CHCFG_n_AM_SHIFT,
+ DMAC3_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC3_CHCFG_n_LVL_SHIFT,
+ DMAC3_CHCFG_n_LVL);
+ if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ req_direction,
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH3_RID_SHIFT,
+ DMAC23_DMARS_CH3_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH3_MID_SHIFT,
+ DMAC23_DMARS_CH3_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Open
+* Description : Enables DMAC channel 3 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC3_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SETEN_SHIFT,
+ DMAC3_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_STG_SHIFT,
+ DMAC3_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Close
+* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_CLREN_SHIFT,
+ DMAC3_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 3 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 3 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_SR_SHIFT,
+ DMAC3_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 4.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 4 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC4_CHCFG_n_DAD_SHIFT,
+ DMAC4_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC4_CHCFG_n_SAD_SHIFT,
+ DMAC4_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->dst_size,
+ DMAC4_CHCFG_n_DDS_SHIFT,
+ DMAC4_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->src_size,
+ DMAC4_CHCFG_n_SDS_SHIFT,
+ DMAC4_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DMS_SHIFT,
+ DMAC4_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSEL_SHIFT,
+ DMAC4_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_SBE_SHIFT,
+ DMAC4_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DEM_SHIFT,
+ DMAC4_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_TM_SHIFT,
+ DMAC4_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 4,
+ DMAC4_CHCFG_n_SEL_SHIFT,
+ DMAC4_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_HIEN_SHIFT,
+ DMAC4_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_LOEN_SHIFT,
+ DMAC4_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC4_CHCFG_n_AM_SHIFT,
+ DMAC4_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC4_CHCFG_n_LVL_SHIFT,
+ DMAC4_CHCFG_n_LVL);
+ if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ req_direction,
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC45_DMARS_CH4_RID_SHIFT,
+ DMAC45_DMARS_CH4_RID);
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC45_DMARS_CH4_MID_SHIFT,
+ DMAC45_DMARS_CH4_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Open
+* Description : Enables DMAC channel 4 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC4_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SETEN_SHIFT,
+ DMAC4_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_STG_SHIFT,
+ DMAC4_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Close
+* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_CLREN_SHIFT,
+ DMAC4_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 4 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 4 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_SR_SHIFT,
+ DMAC4_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c
new file mode 100644
index 000000000..f002e54b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb1_host.h"
+#include "MBRZA1H.h" /* INTC Driver Header */
+#include "usb1_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_attach (void)
+{
+// printf("\n");
+// printf("channel 1 attach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_detach (void)
+{
+// printf("\n");
+// printf("channel 1 detach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_1ms (void)
+{
+ osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_xms (uint32_t msec)
+{
+ osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb1_host_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_host_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_HOST_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_HOST_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor = DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor = DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC3 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC4 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma0
+* Description : Disables DMA transfer.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+* Notice : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_host_DMAC3_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_host_DMAC4_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_notice
+* Description : Notice of USER
+* Arguments : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_notice (const char * format)
+{
+// printf(format);
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_user_rdy
+* Description : This function notify a user and wait for trigger
+* Arguments : const char *format
+* : uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data)
+{
+// printf(format, data);
+ getchar();
+
+ return;
+}
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h
new file mode 100644
index 000000000..b1c450cd1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_HOST_SETTING_H
+#define USB_HOST_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_HOST_CH 0
+#define USB_HOST_HISPEED 1
+
+#define INT_TRANS_MAX_NUM 4 /* min:1 max:4 */
+#define ISO_TRANS_MAX_NUM 0 /* min:0 max:2 */
+
+#if (USB_HOST_CH == 0)
+#include "usb0_host.h"
+#define USB20X USB200
+#define USBIXUSBIX USBI0_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed g_usb0_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed g_usb0_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage g_usb0_host_CmdStage
+#define g_usbx_host_pipe_status g_usb0_host_pipe_status
+#define g_usbx_host_data_pointer g_usb0_host_data_pointer
+#define g_usbx_host_data_count g_usb0_host_data_count
+#define usbx_api_host_init usb0_api_host_init
+#define usbx_host_UsbBusReset usb0_host_UsbBusReset
+#define usbx_host_get_devadd usb0_host_get_devadd
+#define usbx_host_set_devadd usb0_host_set_devadd
+#define usbx_host_SetupStage usb0_host_SetupStage
+#define usbx_host_CtrlWriteStart usb0_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart usb0_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable usb0_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer usb0_host_start_send_transfer
+#define usbx_host_start_receive_transfer usb0_host_start_receive_transfer
+#define usbx_host_stop_transfer usb0_host_stop_transfer
+#define usbx_host_set_sqclr usb0_host_set_sqclr
+#define usbx_host_set_sqset usb0_host_set_sqset
+#define usbx_host_CheckAttach usb0_host_CheckAttach
+#define usbx_host_UsbDetach usb0_host_UsbDetach
+#define usbx_host_UsbAttach usb0_host_UsbAttach
+#define usbx_host_init_pipe_status usb0_host_init_pipe_status
+#define usbx_host_get_sqmon usb0_host_get_sqmon
+#else
+#include "usb1_host.h"
+#define USB20X USB201
+#define USBIXUSBIX USBI1_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed g_usb1_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed g_usb1_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage g_usb1_host_CmdStage
+#define g_usbx_host_pipe_status g_usb1_host_pipe_status
+#define g_usbx_host_data_pointer g_usb1_host_data_pointer
+#define g_usbx_host_data_count g_usb1_host_data_count
+#define usbx_api_host_init usb1_api_host_init
+#define usbx_host_UsbBusReset usb1_host_UsbBusReset
+#define usbx_host_get_devadd usb1_host_get_devadd
+#define usbx_host_set_devadd usb1_host_set_devadd
+#define usbx_host_SetupStage usb1_host_SetupStage
+#define usbx_host_CtrlWriteStart usb1_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart usb1_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable usb1_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer usb1_host_start_send_transfer
+#define usbx_host_start_receive_transfer usb1_host_start_receive_transfer
+#define usbx_host_stop_transfer usb1_host_stop_transfer
+#define usbx_host_set_sqclr usb1_host_set_sqclr
+#define usbx_host_set_sqset usb1_host_set_sqset
+#define usbx_host_CheckAttach usb1_host_CheckAttach
+#define usbx_host_UsbDetach usb1_host_UsbDetach
+#define usbx_host_UsbAttach usb1_host_UsbAttach
+#define usbx_host_init_pipe_status usb1_host_init_pipe_status
+#define usbx_host_get_sqmon usb1_host_get_sqmon
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_HOST_SETTING_H */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp
new file mode 100644
index 000000000..8314b3ef4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp
@@ -0,0 +1,124 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBDeviceConnected.h"
+#include "dbg.h"
+
+USBDeviceConnected::USBDeviceConnected() {
+ init();
+}
+
+void USBDeviceConnected::init() {
+ hub_nb = 0;
+ port = 0;
+ vid = 0;
+ pid = 0;
+ nb_interf = 0;
+ enumerated = false;
+ activeAddr = false;
+ sizeControlEndpoint = 8;
+ device_class = 0;
+ device_subclass = 0;
+ proto = 0;
+ speed = false;
+ for (int i = 0; i < MAX_INTF; i++) {
+ memset((void *)&intf[i], 0, sizeof(INTERFACE));
+ intf[i].in_use = false;
+ for (int j = 0; j < MAX_ENDPOINT_PER_INTERFACE; j++) {
+ intf[i].ep[j] = NULL;
+ strcpy(intf[i].name, "Unknown");
+ }
+ }
+ hub_parent = NULL;
+ hub = NULL;
+ nb_interf = 0;
+}
+
+INTERFACE * USBDeviceConnected::getInterface(uint8_t index) {
+ if (index >= MAX_INTF)
+ return NULL;
+
+ if (intf[index].in_use)
+ return &intf[index];
+
+ return NULL;
+}
+
+bool USBDeviceConnected::addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) {
+ if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use)) {
+ return false;
+ }
+ intf[intf_nb].in_use = true;
+ intf[intf_nb].intf_class = intf_class;
+ intf[intf_nb].intf_subclass = intf_subclass;
+ intf[intf_nb].intf_protocol = intf_protocol;
+ intf[intf_nb].nb_endpoint = 0;
+ return true;
+}
+
+bool USBDeviceConnected::addEndpoint(uint8_t intf_nb, USBEndpoint * ept) {
+ if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use == false) || (intf[intf_nb].nb_endpoint >= MAX_ENDPOINT_PER_INTERFACE)) {
+ return false;
+ }
+ intf[intf_nb].nb_endpoint++;
+
+ for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+ if (intf[intf_nb].ep[i] == NULL) {
+ intf[intf_nb].ep[i] = ept;
+ return true;
+ }
+ }
+ return false;
+}
+
+void USBDeviceConnected::init(uint8_t hub_, uint8_t port_, bool lowSpeed_) {
+ USB_DBG("init dev: %p", this);
+ init();
+ hub_nb = hub_;
+ port = port_;
+ speed = lowSpeed_;
+}
+
+void USBDeviceConnected::disconnect() {
+ for(int i = 0; i < MAX_INTF; i++) {
+ intf[i].detach.call();
+ }
+ init();
+}
+
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index) {
+ if (intf_nb >= MAX_INTF) {
+ return NULL;
+ }
+ for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+ if ((intf[intf_nb].ep[i]->getType() == type) && (intf[intf_nb].ep[i]->getDir() == dir)) {
+ if(index) {
+ index--;
+ } else {
+ return intf[intf_nb].ep[i];
+ }
+ }
+ }
+ return NULL;
+}
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, uint8_t index) {
+ if ((intf_nb >= MAX_INTF) || (index >= MAX_ENDPOINT_PER_INTERFACE)) {
+ return NULL;
+ }
+ return intf[intf_nb].ep[index];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h
new file mode 100644
index 000000000..22a4c1d3e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h
@@ -0,0 +1,185 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBDEVICECONNECTED_H
+#define USBDEVICECONNECTED_H
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+
+class USBHostHub;
+
+typedef struct {
+ bool in_use;
+ uint8_t nb_endpoint;
+ uint8_t intf_class;
+ uint8_t intf_subclass;
+ uint8_t intf_protocol;
+ USBEndpoint * ep[MAX_ENDPOINT_PER_INTERFACE];
+ FunctionPointer detach;
+ char name[10];
+} INTERFACE;
+
+/**
+* USBDeviceConnected class
+*/
+class USBDeviceConnected
+{
+public:
+
+ /**
+ * Constructor
+ */
+ USBDeviceConnected();
+
+ /**
+ * Attach an USBEndpoint to this device
+ *
+ * @param intf_nb interface number
+ * @param ep pointeur on the USBEndpoint which will be attached
+ * @returns true if successful, false otherwise
+ */
+ bool addEndpoint(uint8_t intf_nb, USBEndpoint * ep);
+
+ /**
+ * Retrieve an USBEndpoint by its TYPE and DIRECTION
+ *
+ * @param intf_nb the interface on which to lookup the USBEndpoint
+ * @param type type of the USBEndpoint looked for
+ * @param dir direction of the USBEndpoint looked for
+ * @param index the index of the USBEndpoint whitin the interface
+ * @returns pointer on the USBEndpoint if found, NULL otherwise
+ */
+ USBEndpoint * getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index = 0);
+
+ /**
+ * Retrieve an USBEndpoint by its index
+ *
+ * @param intf_nb interface number
+ * @param index index of the USBEndpoint
+ * @returns pointer on the USBEndpoint if found, NULL otherwise
+ */
+ USBEndpoint * getEndpoint(uint8_t intf_nb, uint8_t index);
+
+ /**
+ * Add a new interface to this device
+ *
+ * @param intf_nb interface number
+ * @param intf_class interface class
+ * @param intf_subclass interface subclass
+ * @param intf_protocol interface protocol
+ * @returns true if successful, false otherwise
+ */
+ bool addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol);
+
+ /**
+ * Get a specific interface
+ *
+ * @param index index of the interface to be fetched
+ * @returns interface
+ */
+ INTERFACE * getInterface(uint8_t index);
+
+ /**
+ * Attach a member function to call when a the device has been disconnected
+ *
+ * @param intf_nb interface number
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ intf[intf_nb].detach.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when the device has been disconnected
+ *
+ * @param intf_nb interface number
+ * @param fn function pointer
+ */
+ inline void onDisconnect(uint8_t intf_nb, void (*fn)(void)) {
+ if (fn != NULL) {
+ intf[intf_nb].detach.attach(fn);
+ }
+ }
+
+ /**
+ * Disconnect the device by calling a callback function registered by a driver
+ */
+ void disconnect();
+
+ // setters
+ void init(uint8_t hub, uint8_t port, bool lowSpeed);
+ inline void setAddress(uint8_t addr_) { addr = addr_; };
+ inline void setVid(uint16_t vid_) { vid = vid_; };
+ inline void setPid(uint16_t pid_) { pid = pid_; };
+ inline void setClass(uint8_t device_class_) { device_class = device_class_; };
+ inline void setSubClass(uint8_t device_subclass_) { device_subclass = device_subclass_; };
+ inline void setProtocol(uint8_t pr) { proto = pr; };
+ inline void setSizeControlEndpoint(uint32_t size) { sizeControlEndpoint = size; };
+ inline void activeAddress(bool active) { activeAddr = active; };
+ inline void setEnumerated() { enumerated = true; };
+ inline void setNbIntf(uint8_t nb_intf) {nb_interf = nb_intf; };
+ inline void setHubParent(USBHostHub * hub) { hub_parent = hub; };
+ inline void setName(const char * name_, uint8_t intf_nb) { strcpy(intf[intf_nb].name, name_); };
+
+ //getters
+ inline uint8_t getPort() { return port; };
+ inline uint8_t getHub() { return hub_nb; };
+ inline uint8_t getAddress() { return addr; };
+ inline uint16_t getVid() { return vid; };
+ inline uint16_t getPid() { return pid; };
+ inline uint8_t getClass() { return device_class; };
+ inline uint8_t getSubClass() { return device_subclass; };
+ inline uint8_t getProtocol() { return proto; };
+ inline bool getSpeed() { return speed; };
+ inline uint32_t getSizeControlEndpoint() { return sizeControlEndpoint; };
+ inline bool isActiveAddress() { return activeAddr; };
+ inline bool isEnumerated() { return enumerated; };
+ inline USBHostHub * getHubParent() { return hub_parent; };
+ inline uint8_t getNbIntf() { return nb_interf; };
+ inline const char * getName(uint8_t intf_nb) { return intf[intf_nb].name; };
+
+ // in case this device is a hub
+ USBHostHub * hub;
+
+private:
+ USBHostHub * hub_parent;
+
+ INTERFACE intf[MAX_INTF];
+ uint32_t sizeControlEndpoint;
+ uint8_t hub_nb;
+ uint8_t port;
+ uint16_t vid;
+ uint16_t pid;
+ uint8_t addr;
+ uint8_t device_class;
+ uint8_t device_subclass;
+ uint8_t proto;
+ bool speed;
+ volatile bool activeAddr;
+ volatile bool enumerated;
+ uint8_t nb_interf;
+
+ void init();
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp
new file mode 100644
index 000000000..fc372232f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp
@@ -0,0 +1,162 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "dbg.h"
+#include "USBEndpoint.h"
+
+void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2])
+{
+ hced = hced_;
+ type = type_;
+ dir = dir_;
+ setup = (type == CONTROL_ENDPOINT) ? true : false;
+
+ //TDs have been allocated by the host
+ memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define
+ memset(td_list_[0], 0, sizeof(HCTD));
+ memset(td_list_[1], 0, sizeof(HCTD));
+
+ td_list[0]->ep = this;
+ td_list[1]->ep = this;
+
+ hced->control = 0;
+ //Empty queue
+ hced->tailTD = td_list[0];
+ hced->headTD = td_list[0];
+ hced->nextED = 0;
+
+ address = (ep_number & 0x7F) | ((dir - 1) << 7);
+
+ hced->control = ((ep_number & 0x7F) << 7) // Endpoint address
+ | (type != CONTROL_ENDPOINT ? ( dir << 11) : 0 ) // direction : Out = 1, 2 = In
+ | ((size & 0x3ff) << 16); // MaxPkt Size
+
+ transfer_len = 0;
+ transferred = 0;
+ buf_start = 0;
+ nextEp = NULL;
+
+ td_current = td_list[0];
+ td_next = td_list[1];
+
+ intf_nb = 0;
+
+ state = USB_TYPE_IDLE;
+}
+
+void USBEndpoint::setSize(uint32_t size)
+{
+ hced->control &= ~(0x3ff << 16);
+ hced->control |= (size << 16);
+}
+
+
+void USBEndpoint::setDeviceAddress(uint8_t addr)
+{
+ hced->control &= ~(0x7f);
+ hced->control |= (addr & 0x7F);
+}
+
+void USBEndpoint::setSpeed(uint8_t speed)
+{
+ hced->control &= ~(1 << 13);
+ hced->control |= (speed << 13);
+}
+
+//Only for control Eps
+void USBEndpoint::setNextToken(uint32_t token)
+{
+ switch (token) {
+ case TD_SETUP:
+ dir = OUT;
+ setup = true;
+ break;
+ case TD_IN:
+ dir = IN;
+ setup = false;
+ break;
+ case TD_OUT:
+ dir = OUT;
+ setup = false;
+ break;
+ }
+}
+
+struct {
+ USB_TYPE type;
+ const char * str;
+} static type_string[] = {
+/*0*/ {USB_TYPE_OK, "USB_TYPE_OK"},
+ {USB_TYPE_CRC_ERROR, "USB_TYPE_CRC_ERROR"},
+ {USB_TYPE_BIT_STUFFING_ERROR, "USB_TYPE_BIT_STUFFING_ERROR"},
+ {USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR, "USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR"},
+ {USB_TYPE_STALL_ERROR, "USB_TYPE_STALL_ERROR"},
+/*5*/ {USB_TYPE_DEVICE_NOT_RESPONDING_ERROR, "USB_TYPE_DEVICE_NOT_RESPONDING_ERROR"},
+ {USB_TYPE_PID_CHECK_FAILURE_ERROR, "USB_TYPE_PID_CHECK_FAILURE_ERROR"},
+ {USB_TYPE_UNEXPECTED_PID_ERROR, "USB_TYPE_UNEXPECTED_PID_ERROR"},
+ {USB_TYPE_DATA_OVERRUN_ERROR, "USB_TYPE_DATA_OVERRUN_ERROR"},
+ {USB_TYPE_DATA_UNDERRUN_ERROR, "USB_TYPE_DATA_UNDERRUN_ERROR"},
+/*10*/ {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+ {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+ {USB_TYPE_BUFFER_OVERRUN_ERROR, "USB_TYPE_BUFFER_OVERRUN_ERROR"},
+ {USB_TYPE_BUFFER_UNDERRUN_ERROR, "USB_TYPE_BUFFER_UNDERRUN_ERROR"},
+ {USB_TYPE_DISCONNECTED, "USB_TYPE_DISCONNECTED"},
+/*15*/ {USB_TYPE_FREE, "USB_TYPE_FREE"},
+ {USB_TYPE_IDLE, "USB_TYPE_IDLE"},
+ {USB_TYPE_PROCESSING, "USB_TYPE_PROCESSING"},
+ {USB_TYPE_ERROR, "USB_TYPE_ERROR"}
+};
+
+void USBEndpoint::setState(uint8_t st) {
+ if (st > 18)
+ return;
+ state = type_string[st].type;
+}
+
+
+const char * USBEndpoint::getStateString() {
+ return type_string[state].str;
+}
+
+void USBEndpoint::queueTransfer()
+{
+ transfer_len = (uint32_t)td_current->bufEnd - (uint32_t)td_current->currBufPtr + 1;
+ transferred = transfer_len;
+ buf_start = (uint8_t *)td_current->currBufPtr;
+
+ //Now add this free TD at this end of the queue
+ state = USB_TYPE_PROCESSING;
+ td_current->nextTD = td_next;
+ hced->tailTD = td_next;
+}
+
+void USBEndpoint::unqueueTransfer(volatile HCTD * td)
+{
+ td->control=0;
+ td->currBufPtr=0;
+ td->bufEnd=0;
+ td->nextTD=0;
+ hced->headTD = (HCTD *)((uint32_t)hced->tailTD | ((uint32_t)hced->headTD & 0x2)); //Carry bit
+ td_current = td_next;
+ td_next = td;
+}
+
+void USBEndpoint::queueEndpoint(USBEndpoint * ed)
+{
+ nextEp = ed;
+ hced->nextED = (ed == NULL) ? 0 : ed->getHCED();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h
new file mode 100644
index 000000000..2ec90d729
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h
@@ -0,0 +1,171 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBENDPOINT_H
+#define USBENDPOINT_H
+
+#include "FunctionPointer.h"
+#include "USBHostTypes.h"
+#include "rtos.h"
+
+class USBDeviceConnected;
+
+/**
+* USBEndpoint class
+*/
+class USBEndpoint
+{
+public:
+ /**
+ * Constructor
+ */
+ USBEndpoint() {
+ state = USB_TYPE_FREE;
+ nextEp = NULL;
+ };
+
+ /**
+ * Initialize an endpoint
+ *
+ * @param hced hced associated to the endpoint
+ * @param type endpoint type
+ * @param dir endpoint direction
+ * @param size endpoint size
+ * @param ep_number endpoint number
+ * @param td_list array of two allocated transfer descriptors
+ */
+ void init(HCED * hced, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t ep_number, HCTD* td_list[2]);
+
+ /**
+ * Set next token. Warning: only useful for the control endpoint
+ *
+ * @param token IN, OUT or SETUP token
+ */
+ void setNextToken(uint32_t token);
+
+ /**
+ * Queue an endpoint
+ *
+ * @param endpoint endpoint which will be queued in the linked list
+ */
+ void queueEndpoint(USBEndpoint * endpoint);
+
+
+ /**
+ * Queue a transfer on the endpoint
+ */
+ void queueTransfer();
+
+ /**
+ * Unqueue a transfer from the endpoint
+ *
+ * @param td hctd which will be unqueued
+ */
+ void unqueueTransfer(volatile HCTD * td);
+
+ /**
+ * Attach a member function to call when a transfer is finished
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void attach(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ rx.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when a transfer is finished
+ *
+ * @param fptr function pointer
+ */
+ inline void attach(void (*fptr)(void)) {
+ if(fptr != NULL) {
+ rx.attach(fptr);
+ }
+ }
+
+ /**
+ * Call the handler associted to the end of a transfer
+ */
+ inline void call() {
+ rx.call();
+ };
+
+
+ // setters
+ inline void setState(USB_TYPE st) { state = st; }
+ void setState(uint8_t st);
+ void setDeviceAddress(uint8_t addr);
+ inline void setLengthTransferred(int len) { transferred = len; };
+ void setSpeed(uint8_t speed);
+ void setSize(uint32_t size);
+ inline void setDir(ENDPOINT_DIRECTION d) { dir = d; }
+ inline void setIntfNb(uint8_t intf_nb_) { intf_nb = intf_nb_; };
+
+ // getters
+ const char * getStateString();
+ inline USB_TYPE getState() { return state; }
+ inline ENDPOINT_TYPE getType() { return type; };
+ inline uint8_t getDeviceAddress() { return hced->control & 0x7f; };
+ inline int getLengthTransferred() { return transferred; }
+ inline uint8_t * getBufStart() { return buf_start; }
+ inline uint8_t getAddress(){ return address; };
+ inline uint32_t getSize() { return (hced->control >> 16) & 0x3ff; };
+ inline volatile HCTD * getHeadTD() { return (volatile HCTD*) ((uint32_t)hced->headTD & ~0xF); };
+ inline volatile HCTD** getTDList() { return td_list; };
+ inline volatile HCED * getHCED() { return hced; };
+ inline ENDPOINT_DIRECTION getDir() { return dir; }
+ inline volatile HCTD * getProcessedTD() { return td_current; };
+ inline volatile HCTD* getNextTD() { return td_current; };
+ inline bool isSetup() { return setup; }
+ inline USBEndpoint * nextEndpoint() { return (USBEndpoint*)nextEp; };
+ inline uint8_t getIntfNb() { return intf_nb; };
+
+ USBDeviceConnected * dev;
+
+ Queue<uint8_t, 1> ep_queue;
+
+private:
+ ENDPOINT_TYPE type;
+ volatile USB_TYPE state;
+ ENDPOINT_DIRECTION dir;
+ bool setup;
+
+ uint8_t address;
+
+ int transfer_len;
+ int transferred;
+ uint8_t * buf_start;
+
+ FunctionPointer rx;
+
+ USBEndpoint* nextEp;
+
+ // USBEndpoint descriptor
+ volatile HCED * hced;
+
+ volatile HCTD * td_list[2];
+ volatile HCTD * td_current;
+ volatile HCTD * td_next;
+
+ uint8_t intf_nb;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h
new file mode 100644
index 000000000..e32969de3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h
@@ -0,0 +1,169 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHALHOST_H
+#define USBHALHOST_H
+
+#include "USBHostTypes.h"
+#include "USBHostConf.h"
+
+class USBHostHub;
+
+/**
+* USBHALHost class
+*/
+class USBHALHost {
+protected:
+
+ /**
+ * Constructor
+ * init variables and memory where will be stored HCCA, ED and TD
+ */
+ USBHALHost();
+
+ /**
+ * Initialize host controller. Enable USB interrupts. This part is not in the constructor because,
+ * this function calls a virtual method if a device is already connected
+ */
+ void init();
+
+ /**
+ * reset the root hub
+ */
+ void resetRootHub();
+
+ /**
+ * return the value contained in the control HEAD ED register
+ *
+ * @returns address of the control Head ED
+ */
+ uint32_t controlHeadED();
+
+ /**
+ * return the value contained in the bulk HEAD ED register
+ *
+ * @returns address of the bulk head ED
+ */
+ uint32_t bulkHeadED();
+
+ /**
+ * return the value of the head interrupt ED contained in the HCCA
+ *
+ * @returns address of the head interrupt ED contained in the HCCA
+ */
+ uint32_t interruptHeadED();
+
+ /**
+ * Update the head ED for control transfers
+ */
+ void updateControlHeadED(uint32_t addr);
+
+ /**
+ * Update the head ED for bulk transfers
+ */
+ void updateBulkHeadED(uint32_t addr);
+
+ /**
+ * Update the head ED for interrupt transfers
+ */
+ void updateInterruptHeadED(uint32_t addr);
+
+ /**
+ * Enable List for the specified endpoint type
+ *
+ * @param type enable the list of ENDPOINT_TYPE type
+ */
+ void enableList(ENDPOINT_TYPE type);
+
+ /**
+ * Disable List for the specified endpoint type
+ *
+ * @param type disable the list of ENDPOINT_TYPE type
+ */
+ bool disableList(ENDPOINT_TYPE type);
+
+ /**
+ * Virtual method called when a device has been connected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param lowSpeed 1 if low speed, 0 otherwise
+ * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+ */
+ virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL) = 0;
+
+ /**
+ * Virtual method called when a device has been disconnected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+ * @param addr list of the TDs which have been completed to dequeue freed TDs
+ */
+ virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = 0;
+
+ /**
+ * Virtual method called when a transfer has been completed
+ *
+ * @param addr list of the TDs which have been completed
+ */
+ virtual void transferCompleted(volatile uint32_t addr) = 0;
+
+ /**
+ * Find a memory section for a new ED
+ *
+ * @returns the address of the new ED
+ */
+ volatile uint8_t * getED();
+
+ /**
+ * Find a memory section for a new TD
+ *
+ * @returns the address of the new TD
+ */
+ volatile uint8_t * getTD();
+
+ /**
+ * Release a previous memory section reserved for an ED
+ *
+ * @param ed address of the ED
+ */
+ void freeED(volatile uint8_t * ed);
+
+ /**
+ * Release a previous memory section reserved for an TD
+ *
+ * @param td address of the TD
+ */
+ void freeTD(volatile uint8_t * td);
+
+private:
+ static void _usbisr(void);
+ void UsbIrqhandler();
+
+ void memInit();
+
+ HCCA volatile * usb_hcca; //256 bytes aligned
+ uint8_t volatile * usb_edBuf; //4 bytes aligned
+ uint8_t volatile * usb_tdBuf; //4 bytes aligned
+
+ static USBHALHost * instHost;
+
+ bool volatile edBufAlloc[MAX_ENDPOINT];
+ bool volatile tdBufAlloc[MAX_TD];
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp
new file mode 100644
index 000000000..c1eadf389
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp
@@ -0,0 +1,325 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_LPC1768)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN (1<<0)
+#define DEV_CLK_EN (1<<1)
+#define PORTSEL_CLK_EN (1<<3)
+#define AHB_CLK_EN (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON (1<<0)
+#define DEV_CLK_ON (1<<1)
+#define PORTSEL_CLK_ON (1<<3)
+#define AHB_CLK_ON (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ NVIC_DisableIRQ(USB_IRQn);
+
+ //Cut power
+ LPC_SC->PCONP &= ~(1UL<<31);
+ wait_ms(100);
+
+ // turn on power for USB
+ LPC_SC->PCONP |= (1UL<<31);
+
+ // Enable USB host clock, port selection and AHB clock
+ LPC_USB->USBClkCtrl |= CLOCK_MASK;
+
+ // Wait for clocks to become available
+ while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
+
+ // it seems the bits[0:1] mean the following
+ // 0: U1=device, U2=host
+ // 1: U1=host, U2=host
+ // 2: reserved
+ // 3: U1=host, U2=device
+ // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+ // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+ LPC_USB->OTGStCtrl |= 1;
+
+ // now that we've configured the ports, we can turn off the portsel clock
+ LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+
+ // configure USB D+/D- pins
+ // P0[29] = USB_D+, 01
+ // P0[30] = USB_D-, 01
+ LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
+ LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
+
+ LPC_USB->HcControl = 0; // HARDWARE RESET
+ LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
+ LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+
+ // Write Fm Interval and Largest Data Packet Counter
+ LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
+ LPC_USB->HcPeriodicStart = FI * 90 / 100;
+
+ // Put HC in operational state
+ LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+ // Set Global Power
+ LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
+
+ LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
+
+ // Clear Interrrupt Status
+ LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
+
+ LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+ // Enable the USB Interrupt
+ NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+
+ NVIC_EnableIRQ(USB_IRQn);
+
+ // Check for any connected devices
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return LPC_USB->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return LPC_USB->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ LPC_USB->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ LPC_USB->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
+ LPC_USB->HcControl |= OR_CONTROL_CLE;
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
+ LPC_USB->HcControl |= OR_CONTROL_BLE;
+ break;
+ case INTERRUPT_ENDPOINT:
+ LPC_USB->HcControl |= OR_CONTROL_PLE;
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_CLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_CLE;
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_BLE){
+ LPC_USB->HcControl &= ~OR_CONTROL_BLE;
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_PLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_PLE;
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ usb_hcca = (volatile HCCA *)usb_buf;
+ usb_edBuf = usb_buf + HCCA_SIZE;
+ usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
+
+ while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
+ {
+
+ uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
+
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+ if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ // wait 200ms to avoid bounce
+ wait_ms(200);
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+ }
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ }
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+ }
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp
new file mode 100644
index 000000000..38213c76a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp
@@ -0,0 +1,292 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A1H)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+#include "ohci_wrapp_RZ_A1.h"
+
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+#define ALIGNE_MSK (0x0000000F)
+
+static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ ohciwrapp_init(&_usbisr);
+
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
+
+ // Write Fm Interval and Largest Data Packet Counter
+ ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
+ ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100);
+
+ // Put HC in operational state
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
+ // Set Global Power
+ ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
+
+ ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
+
+ // Clear Interrrupt Status
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
+
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
+
+ // Enable the USB Interrupt
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+
+ // Check for any connected devices
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
+ deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case INTERRUPT_ENDPOINT:
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_CLE) {
+ wk_data &= ~OR_CONTROL_CLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_BLE) {
+ wk_data &= ~OR_CONTROL_BLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_PLE) {
+ wk_data &= ~OR_CONTROL_PLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
+
+ usb_hcca = (volatile HCCA *)p_wk_buf;
+ usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
+ usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
+
+ while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
+ uint32_t data;
+
+ if (int_status != 0) { //Is there something to actually process?
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
+ deviceConnected(0, 1, data);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+ }
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ }
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+ }
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp
new file mode 100644
index 000000000..d05486db9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp
@@ -0,0 +1,1160 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "USBHost.h"
+#include "USBHostHub.h"
+
+USBHost * USBHost::instHost = NULL;
+
+#define DEVICE_CONNECTED_EVENT (1 << 0)
+#define DEVICE_DISCONNECTED_EVENT (1 << 1)
+#define TD_PROCESSED_EVENT (1 << 2)
+
+#define MAX_TRY_ENUMERATE_HUB 3
+
+#define MIN(a, b) ((a > b) ? b : a)
+
+/**
+* How interrupts are processed:
+* - new device connected:
+* - a message is queued in queue_usb_event with the id DEVICE_CONNECTED_EVENT
+* - when the usb_thread receives the event, it:
+* - resets the device
+* - reads the device descriptor
+* - sets the address of the device
+* - if it is a hub, enumerates it
+* - device disconnected:
+* - a message is queued in queue_usb_event with the id DEVICE_DISCONNECTED_EVENT
+* - when the usb_thread receives the event, it:
+* - free the device and all its children (hub)
+* - td processed
+* - a message is queued in queue_usb_event with the id TD_PROCESSED_EVENT
+* - when the usb_thread receives the event, it:
+* - call the callback attached to the endpoint where the td is attached
+*/
+void USBHost::usb_process() {
+
+ bool controlListState;
+ bool bulkListState;
+ bool interruptListState;
+ USBEndpoint * ep;
+ uint8_t i, j, res, timeout_set_addr = 10;
+ uint8_t buf[8];
+ bool too_many_hub;
+ int idx;
+
+#if DEBUG_TRANSFER
+ uint8_t * buf_transfer;
+#endif
+
+#if MAX_HUB_NB
+ uint8_t k;
+#endif
+
+ while(1) {
+ osEvent evt = mail_usb_event.get();
+
+ if (evt.status == osEventMail) {
+
+ message_t * usb_msg = (message_t*)evt.value.p;
+
+ switch (usb_msg->event_id) {
+
+ // a new device has been connected
+ case DEVICE_CONNECTED_EVENT:
+ too_many_hub = false;
+ buf[4] = 0;
+
+ do
+ {
+ Lock lock(this);
+
+ for (i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (!deviceInUse[i]) {
+ USB_DBG_EVENT("new device connected: %p\r\n", &devices[i]);
+ devices[i].init(usb_msg->hub, usb_msg->port, usb_msg->lowSpeed);
+ deviceReset[i] = false;
+ deviceInited[i] = true;
+ break;
+ }
+ }
+
+ if (i == MAX_DEVICE_CONNECTED) {
+ USB_ERR("Too many device connected!!\r\n");
+ continue;
+ }
+
+ if (!controlEndpointAllocated) {
+ control = newEndpoint(CONTROL_ENDPOINT, OUT, 0x08, 0x00);
+ addEndpoint(NULL, 0, (USBEndpoint*)control);
+ controlEndpointAllocated = true;
+ }
+
+ #if MAX_HUB_NB
+ if (usb_msg->hub_parent)
+ devices[i].setHubParent((USBHostHub *)(usb_msg->hub_parent));
+ #endif
+
+ for (j = 0; j < timeout_set_addr; j++) {
+
+ resetDevice(&devices[i]);
+
+ // set size of control endpoint
+ devices[i].setSizeControlEndpoint(8);
+
+ devices[i].activeAddress(false);
+
+ // get first 8 bit of device descriptor
+ // and check if we deal with a hub
+ USB_DBG("usb_thread read device descriptor on dev: %p\r\n", &devices[i]);
+ res = getDeviceDescriptor(&devices[i], buf, 8);
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("usb_thread could not read dev descr");
+ continue;
+ }
+
+ // set size of control endpoint
+ devices[i].setSizeControlEndpoint(buf[7]);
+
+ // second step: set an address to the device
+ res = setAddress(&devices[i], devices[i].getAddress());
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("SET ADDR FAILED");
+ continue;
+ }
+ devices[i].activeAddress(true);
+ USB_DBG("Address of %p: %d", &devices[i], devices[i].getAddress());
+
+ // try to read again the device descriptor to check if the device
+ // answers to its new address
+ res = getDeviceDescriptor(&devices[i], buf, 8);
+
+ if (res == USB_TYPE_OK) {
+ break;
+ }
+
+ Thread::wait(100);
+ }
+
+ USB_INFO("New device connected: %p [hub: %d - port: %d]", &devices[i], usb_msg->hub, usb_msg->port);
+
+ #if MAX_HUB_NB
+ if (buf[4] == HUB_CLASS) {
+ for (k = 0; k < MAX_HUB_NB; k++) {
+ if (hub_in_use[k] == false) {
+ for (uint8_t j = 0; j < MAX_TRY_ENUMERATE_HUB; j++) {
+ if (hubs[k].connect(&devices[i])) {
+ devices[i].hub = &hubs[k];
+ hub_in_use[k] = true;
+ break;
+ }
+ }
+ if (hub_in_use[k] == true)
+ break;
+ }
+ }
+
+ if (k == MAX_HUB_NB) {
+ USB_ERR("Too many hubs connected!!\r\n");
+ too_many_hub = true;
+ }
+ }
+
+ if (usb_msg->hub_parent)
+ ((USBHostHub *)(usb_msg->hub_parent))->deviceConnected(&devices[i]);
+ #endif
+
+ if ((i < MAX_DEVICE_CONNECTED) && !too_many_hub) {
+ deviceInUse[i] = true;
+ }
+
+ } while(0);
+
+ break;
+
+ // a device has been disconnected
+ case DEVICE_DISCONNECTED_EVENT:
+
+ do
+ {
+ Lock lock(this);
+
+ controlListState = disableList(CONTROL_ENDPOINT);
+ bulkListState = disableList(BULK_ENDPOINT);
+ interruptListState = disableList(INTERRUPT_ENDPOINT);
+
+ idx = findDevice(usb_msg->hub, usb_msg->port, (USBHostHub *)(usb_msg->hub_parent));
+ if (idx != -1) {
+ freeDevice((USBDeviceConnected*)&devices[idx]);
+ }
+
+ if (controlListState) enableList(CONTROL_ENDPOINT);
+ if (bulkListState) enableList(BULK_ENDPOINT);
+ if (interruptListState) enableList(INTERRUPT_ENDPOINT);
+
+ } while(0);
+
+ break;
+
+ // a td has been processed
+ // call callback on the ed associated to the td
+ // we are not in ISR -> users can use printf in their callback method
+ case TD_PROCESSED_EVENT:
+ ep = (USBEndpoint *) ((HCTD *)usb_msg->td_addr)->ep;
+ if (usb_msg->td_state == USB_TYPE_IDLE) {
+ USB_DBG_EVENT("call callback on td %p [ep: %p state: %s - dev: %p - %s]", usb_msg->td_addr, ep, ep->getStateString(), ep->dev, ep->dev->getName(ep->getIntfNb()));
+
+#if DEBUG_TRANSFER
+ if (ep->getDir() == IN) {
+ buf_transfer = ep->getBufStart();
+ printf("READ SUCCESS [%d bytes transferred - td: 0x%08X] on ep: [%p - addr: %02X]: ", ep->getLengthTransferred(), usb_msg->td_addr, ep, ep->getAddress());
+ for (int i = 0; i < ep->getLengthTransferred(); i++)
+ printf("%02X ", buf_transfer[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+ ep->call();
+ } else {
+ idx = findDevice(ep->dev);
+ if (idx != -1) {
+ if (deviceInUse[idx]) {
+ USB_WARN("td %p processed but not in idle state: %s [ep: %p - dev: %p - %s]", usb_msg->td_addr, ep->getStateString(), ep, ep->dev, ep->dev->getName(ep->getIntfNb()));
+ ep->setState(USB_TYPE_IDLE);
+ }
+ }
+ }
+ break;
+ }
+
+ mail_usb_event.free(usb_msg);
+ }
+ }
+}
+
+/* static */void USBHost::usb_process_static(void const * arg) {
+ ((USBHost *)arg)->usb_process();
+}
+
+USBHost::USBHost() : usbThread(USBHost::usb_process_static, (void *)this, osPriorityNormal, USB_THREAD_STACK)
+{
+ headControlEndpoint = NULL;
+ headBulkEndpoint = NULL;
+ headInterruptEndpoint = NULL;
+ tailControlEndpoint = NULL;
+ tailBulkEndpoint = NULL;
+ tailInterruptEndpoint = NULL;
+
+ lenReportDescr = 0;
+
+ controlEndpointAllocated = false;
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ deviceInUse[i] = false;
+ devices[i].setAddress(i + 1);
+ deviceReset[i] = false;
+ deviceInited[i] = false;
+ for (uint8_t j = 0; j < MAX_INTF; j++)
+ deviceAttachedDriver[i][j] = false;
+ }
+
+#if MAX_HUB_NB
+ for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+ hubs[i].setHost(this);
+ hub_in_use[i] = false;
+ }
+#endif
+}
+
+USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost)
+{
+ m_pHost->usb_mutex.lock();
+}
+
+USBHost::Lock::~Lock()
+{
+ m_pHost->usb_mutex.unlock();
+}
+
+void USBHost::transferCompleted(volatile uint32_t addr)
+{
+ uint8_t state;
+
+ if(addr == 0)
+ return;
+
+ volatile HCTD* tdList = NULL;
+
+ //First we must reverse the list order and dequeue each TD
+ do {
+ volatile HCTD* td = (volatile HCTD*)addr;
+ addr = (uint32_t)td->nextTD; //Dequeue from physical list
+ td->nextTD = tdList; //Enqueue into reversed list
+ tdList = td;
+ } while(addr);
+
+ while(tdList != NULL) {
+ volatile HCTD* td = tdList;
+ tdList = (volatile HCTD*)td->nextTD; //Dequeue element now as it could be modified below
+ if (td->ep != NULL) {
+ USBEndpoint * ep = (USBEndpoint *)(td->ep);
+
+ if (((HCTD *)td)->control >> 28) {
+ state = ((HCTD *)td)->control >> 28;
+ } else {
+ if (td->currBufPtr)
+ ep->setLengthTransferred((uint32_t)td->currBufPtr - (uint32_t)ep->getBufStart());
+ state = 16 /*USB_TYPE_IDLE*/;
+ }
+
+ ep->unqueueTransfer(td);
+
+ if (ep->getType() != CONTROL_ENDPOINT) {
+ // callback on the processed td will be called from the usb_thread (not in ISR)
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = TD_PROCESSED_EVENT;
+ usb_msg->td_addr = (void *)td;
+ usb_msg->td_state = state;
+ mail_usb_event.put(usb_msg);
+ }
+ ep->setState(state);
+ ep->ep_queue.put((uint8_t*)1);
+ }
+ }
+}
+
+USBHost * USBHost::getHostInst()
+{
+ if (instHost == NULL) {
+ instHost = new USBHost();
+ instHost->init();
+ }
+ return instHost;
+}
+
+
+/*
+ * Called when a device has been connected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent)
+{
+ // be sure that the new device connected is not already connected...
+ int idx = findDevice(hub, port, hub_parent);
+ if (idx != -1) {
+ if (deviceInited[idx])
+ return;
+ }
+
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = DEVICE_CONNECTED_EVENT;
+ usb_msg->hub = hub;
+ usb_msg->port = port;
+ usb_msg->lowSpeed = lowSpeed;
+ usb_msg->hub_parent = hub_parent;
+ mail_usb_event.put(usb_msg);
+}
+
+/*
+ * Called when a device has been disconnected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)
+{
+ // be sure that the device disconnected is connected...
+ int idx = findDevice(hub, port, hub_parent);
+ if (idx != -1) {
+ if (!deviceInUse[idx])
+ return;
+ } else {
+ return;
+ }
+
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = DEVICE_DISCONNECTED_EVENT;
+ usb_msg->hub = hub;
+ usb_msg->port = port;
+ usb_msg->hub_parent = hub_parent;
+ mail_usb_event.put(usb_msg);
+}
+
+void USBHost::freeDevice(USBDeviceConnected * dev)
+{
+ USBEndpoint * ep = NULL;
+ HCED * ed = NULL;
+
+#if MAX_HUB_NB
+ if (dev->getClass() == HUB_CLASS) {
+ if (dev->hub == NULL) {
+ USB_ERR("HUB NULL!!!!!\r\n");
+ } else {
+ dev->hub->hubDisconnected();
+ for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+ if (dev->hub == &hubs[i]) {
+ hub_in_use[i] = false;
+ break;
+ }
+ }
+ }
+ }
+
+ // notify hub parent that this device has been disconnected
+ if (dev->getHubParent())
+ dev->getHubParent()->deviceDisconnected(dev);
+
+#endif
+
+ int idx = findDevice(dev);
+ if (idx != -1) {
+ deviceInUse[idx] = false;
+ deviceReset[idx] = false;
+
+ for (uint8_t j = 0; j < MAX_INTF; j++) {
+ deviceAttachedDriver[idx][j] = false;
+ if (dev->getInterface(j) != NULL) {
+ USB_DBG("FREE INTF %d on dev: %p, %p, nb_endpot: %d, %s", j, (void *)dev->getInterface(j), dev, dev->getInterface(j)->nb_endpoint, dev->getName(j));
+ for (int i = 0; i < dev->getInterface(j)->nb_endpoint; i++) {
+ if ((ep = dev->getEndpoint(j, i)) != NULL) {
+ ed = (HCED *)ep->getHCED();
+ ed->control |= (1 << 14); //sKip bit
+ unqueueEndpoint(ep);
+
+ freeTD((volatile uint8_t*)ep->getTDList()[0]);
+ freeTD((volatile uint8_t*)ep->getTDList()[1]);
+
+ freeED((uint8_t *)ep->getHCED());
+ }
+ printList(BULK_ENDPOINT);
+ printList(INTERRUPT_ENDPOINT);
+ }
+ USB_INFO("Device disconnected [%p - %s - hub: %d - port: %d]", dev, dev->getName(j), dev->getHub(), dev->getPort());
+ }
+ }
+ dev->disconnect();
+ }
+}
+
+
+void USBHost::unqueueEndpoint(USBEndpoint * ep)
+{
+ USBEndpoint * prec = NULL;
+ USBEndpoint * current = NULL;
+
+ for (int i = 0; i < 2; i++) {
+ current = (i == 0) ? (USBEndpoint*)headBulkEndpoint : (USBEndpoint*)headInterruptEndpoint;
+ prec = current;
+ while (current != NULL) {
+ if (current == ep) {
+ if (current->nextEndpoint() != NULL) {
+ prec->queueEndpoint(current->nextEndpoint());
+ if (current == headBulkEndpoint) {
+ updateBulkHeadED((uint32_t)current->nextEndpoint()->getHCED());
+ headBulkEndpoint = current->nextEndpoint();
+ } else if (current == headInterruptEndpoint) {
+ updateInterruptHeadED((uint32_t)current->nextEndpoint()->getHCED());
+ headInterruptEndpoint = current->nextEndpoint();
+ }
+ }
+ // here we are dequeuing the queue of ed
+ // we need to update the tail pointer
+ else {
+ prec->queueEndpoint(NULL);
+ if (current == headBulkEndpoint) {
+ updateBulkHeadED(0);
+ headBulkEndpoint = current->nextEndpoint();
+ } else if (current == headInterruptEndpoint) {
+ updateInterruptHeadED(0);
+ headInterruptEndpoint = current->nextEndpoint();
+ }
+
+ // modify tail
+ switch (current->getType()) {
+ case BULK_ENDPOINT:
+ tailBulkEndpoint = prec;
+ break;
+ case INTERRUPT_ENDPOINT:
+ tailInterruptEndpoint = prec;
+ break;
+ default:
+ break;
+ }
+ }
+ current->setState(USB_TYPE_FREE);
+ return;
+ }
+ prec = current;
+ current = current->nextEndpoint();
+ }
+ }
+}
+
+
+USBDeviceConnected * USBHost::getDevice(uint8_t index)
+{
+ if ((index >= MAX_DEVICE_CONNECTED) || (!deviceInUse[index])) {
+ return NULL;
+ }
+ return (USBDeviceConnected*)&devices[index];
+}
+
+// create an USBEndpoint descriptor. the USBEndpoint is not linked
+USBEndpoint * USBHost::newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr)
+{
+ int i = 0;
+ HCED * ed = (HCED *)getED();
+ HCTD* td_list[2] = { (HCTD*)getTD(), (HCTD*)getTD() };
+
+ memset((void *)td_list[0], 0x00, sizeof(HCTD));
+ memset((void *)td_list[1], 0x00, sizeof(HCTD));
+
+ // search a free USBEndpoint
+ for (i = 0; i < MAX_ENDPOINT; i++) {
+ if (endpoints[i].getState() == USB_TYPE_FREE) {
+ endpoints[i].init(ed, type, dir, size, addr, td_list);
+ USB_DBG("USBEndpoint created (%p): type: %d, dir: %d, size: %d, addr: %d, state: %s", &endpoints[i], type, dir, size, addr, endpoints[i].getStateString());
+ return &endpoints[i];
+ }
+ }
+ USB_ERR("could not allocate more endpoints!!!!");
+ return NULL;
+}
+
+
+USB_TYPE USBHost::resetDevice(USBDeviceConnected * dev)
+{
+ int index = findDevice(dev);
+ if (index != -1) {
+ USB_DBG("Resetting hub %d, port %d\n", dev->getHub(), dev->getPort());
+ Thread::wait(100);
+ if (dev->getHub() == 0) {
+ resetRootHub();
+ }
+#if MAX_HUB_NB
+ else {
+ dev->getHubParent()->portReset(dev->getPort());
+ }
+#endif
+ Thread::wait(100);
+ deviceReset[index] = true;
+ return USB_TYPE_OK;
+ }
+
+ return USB_TYPE_ERROR;
+}
+
+// link the USBEndpoint to the linked list and attach an USBEndpoint to a device
+bool USBHost::addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep)
+{
+
+ if (ep == NULL) {
+ return false;
+ }
+
+ HCED * prevEd;
+
+ // set device address in the USBEndpoint descriptor
+ if (dev == NULL) {
+ ep->setDeviceAddress(0);
+ } else {
+ ep->setDeviceAddress(dev->getAddress());
+ }
+
+ if ((dev != NULL) && dev->getSpeed()) {
+ ep->setSpeed(dev->getSpeed());
+ }
+
+ ep->setIntfNb(intf_nb);
+
+ // queue the new USBEndpoint on the ED list
+ switch (ep->getType()) {
+
+ case CONTROL_ENDPOINT:
+ prevEd = ( HCED*) controlHeadED();
+ if (!prevEd) {
+ updateControlHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First control USBEndpoint: %08X", (uint32_t) ep->getHCED());
+ headControlEndpoint = ep;
+ tailControlEndpoint = ep;
+ return true;
+ }
+ tailControlEndpoint->queueEndpoint(ep);
+ tailControlEndpoint = ep;
+ return true;
+
+ case BULK_ENDPOINT:
+ prevEd = ( HCED*) bulkHeadED();
+ if (!prevEd) {
+ updateBulkHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First bulk USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+ headBulkEndpoint = ep;
+ tailBulkEndpoint = ep;
+ break;
+ }
+ USB_DBG_TRANSFER("Queue BULK Ed %p after %p\r\n",ep->getHCED(), prevEd);
+ tailBulkEndpoint->queueEndpoint(ep);
+ tailBulkEndpoint = ep;
+ break;
+
+ case INTERRUPT_ENDPOINT:
+ prevEd = ( HCED*) interruptHeadED();
+ if (!prevEd) {
+ updateInterruptHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First interrupt USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+ headInterruptEndpoint = ep;
+ tailInterruptEndpoint = ep;
+ break;
+ }
+ USB_DBG_TRANSFER("Queue INTERRUPT Ed %p after %p\r\n",ep->getHCED(), prevEd);
+ tailInterruptEndpoint->queueEndpoint(ep);
+ tailInterruptEndpoint = ep;
+ break;
+ default:
+ return false;
+ }
+
+ ep->dev = dev;
+ dev->addEndpoint(intf_nb, ep);
+
+ return true;
+}
+
+
+int USBHost::findDevice(USBDeviceConnected * dev)
+{
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (dev == &devices[i]) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+int USBHost::findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent)
+{
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (devices[i].getHub() == hub && devices[i].getPort() == port) {
+ if (hub_parent != NULL) {
+ if (hub_parent == devices[i].getHubParent())
+ return i;
+ } else {
+ return i;
+ }
+ }
+ }
+ return -1;
+}
+
+void USBHost::printList(ENDPOINT_TYPE type)
+{
+#if DEBUG_EP_STATE
+ volatile HCED * hced;
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ hced = (HCED *)controlHeadED();
+ break;
+ case BULK_ENDPOINT:
+ hced = (HCED *)bulkHeadED();
+ break;
+ case INTERRUPT_ENDPOINT:
+ hced = (HCED *)interruptHeadED();
+ break;
+ }
+ volatile HCTD * hctd = NULL;
+ const char * type_str = (type == BULK_ENDPOINT) ? "BULK" :
+ ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" :
+ ((type == CONTROL_ENDPOINT) ? "CONTROL" : "ISOCHRONOUS"));
+ printf("State of %s:\r\n", type_str);
+ while (hced != NULL) {
+ uint8_t dir = ((hced->control & (3 << 11)) >> 11);
+ printf("hced: %p [ADDR: %d, DIR: %s, EP_NB: 0x%X]\r\n", hced,
+ hced->control & 0x7f,
+ (dir == 1) ? "OUT" : ((dir == 0) ? "FROM_TD":"IN"),
+ (hced->control & (0xf << 7)) >> 7);
+ hctd = (HCTD *)((uint32_t)(hced->headTD) & ~(0xf));
+ while (hctd != hced->tailTD) {
+ printf("\thctd: %p [DIR: %s]\r\n", hctd, ((hctd->control & (3 << 19)) >> 19) == 1 ? "OUT" : "IN");
+ hctd = hctd->nextTD;
+ }
+ printf("\thctd: %p\r\n", hctd);
+ hced = hced->nextED;
+ }
+ printf("\r\n\r\n");
+#endif
+}
+
+
+// add a transfer on the TD linked list
+USB_TYPE USBHost::addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len)
+{
+ td_mutex.lock();
+
+ // allocate a TD which will be freed in TDcompletion
+ volatile HCTD * td = ed->getNextTD();
+ if (td == NULL) {
+ return USB_TYPE_ERROR;
+ }
+
+ uint32_t token = (ed->isSetup() ? TD_SETUP : ( (ed->getDir() == IN) ? TD_IN : TD_OUT ));
+
+ uint32_t td_toggle;
+
+ if (ed->getType() == CONTROL_ENDPOINT) {
+ if (ed->isSetup()) {
+ td_toggle = TD_TOGGLE_0;
+ } else {
+ td_toggle = TD_TOGGLE_1;
+ }
+ } else {
+ td_toggle = 0;
+ }
+
+ td->control = (TD_ROUNDING | token | TD_DELAY_INT(0) | td_toggle | TD_CC);
+ td->currBufPtr = buf;
+ td->bufEnd = (buf + (len - 1));
+
+ ENDPOINT_TYPE type = ed->getType();
+
+ disableList(type);
+ ed->queueTransfer();
+ printList(type);
+ enableList(type);
+
+ td_mutex.unlock();
+
+ return USB_TYPE_PROCESSING;
+}
+
+
+
+USB_TYPE USBHost::getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr)
+{
+ USB_TYPE t = controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (DEVICE_DESCRIPTOR << 8) | (0),
+ 0, buf, MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf));
+ if (len_dev_descr)
+ *len_dev_descr = MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf);
+
+ return t;
+}
+
+USB_TYPE USBHost::getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr)
+{
+ USB_TYPE res;
+ uint16_t total_conf_descr_length = 0;
+
+ // fourth step: get the beginning of the configuration descriptor to have the total length of the conf descr
+ res = controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (CONFIGURATION_DESCRIPTOR << 8) | (0),
+ 0, buf, CONFIGURATION_DESCRIPTOR_LENGTH);
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("GET CONF 1 DESCR FAILED");
+ return res;
+ }
+ total_conf_descr_length = buf[2] | (buf[3] << 8);
+ total_conf_descr_length = MIN(max_len_buf, total_conf_descr_length);
+
+ if (len_conf_descr)
+ *len_conf_descr = total_conf_descr_length;
+
+ USB_DBG("TOTAL_LENGTH: %d \t NUM_INTERF: %d", total_conf_descr_length, buf[4]);
+
+ return controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (CONFIGURATION_DESCRIPTOR << 8) | (0),
+ 0, buf, total_conf_descr_length);
+}
+
+
+USB_TYPE USBHost::setAddress(USBDeviceConnected * dev, uint8_t address) {
+ return controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+ SET_ADDRESS,
+ address,
+ 0, NULL, 0);
+
+}
+
+USB_TYPE USBHost::setConfiguration(USBDeviceConnected * dev, uint8_t conf)
+{
+ return controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+ SET_CONFIGURATION,
+ conf,
+ 0, NULL, 0);
+}
+
+uint8_t USBHost::numberDriverAttached(USBDeviceConnected * dev) {
+ int index = findDevice(dev);
+ uint8_t cnt = 0;
+ if (index == -1)
+ return 0;
+ for (uint8_t i = 0; i < MAX_INTF; i++) {
+ if (deviceAttachedDriver[index][i])
+ cnt++;
+ }
+ return cnt;
+}
+
+// enumerate a device with the control USBEndpoint
+USB_TYPE USBHost::enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator)
+{
+ uint16_t total_conf_descr_length = 0;
+ USB_TYPE res;
+
+ do
+ {
+ Lock lock(this);
+
+ // don't enumerate a device which all interfaces are registered to a specific driver
+ int index = findDevice(dev);
+
+ if (index == -1) {
+ return USB_TYPE_ERROR;
+ }
+
+ uint8_t nb_intf_attached = numberDriverAttached(dev);
+ USB_DBG("dev: %p nb_intf: %d", dev, dev->getNbIntf());
+ USB_DBG("dev: %p nb_intf_attached: %d", dev, nb_intf_attached);
+ if ((nb_intf_attached != 0) && (dev->getNbIntf() == nb_intf_attached)) {
+ USB_DBG("Don't enumerate dev: %p because all intf are registered with a driver", dev);
+ return USB_TYPE_OK;
+ }
+
+ USB_DBG("Enumerate dev: %p", dev);
+
+ // third step: get the whole device descriptor to see vid, pid
+ res = getDeviceDescriptor(dev, data, DEVICE_DESCRIPTOR_LENGTH);
+
+ if (res != USB_TYPE_OK) {
+ USB_DBG("GET DEV DESCR FAILED");
+ return res;
+ }
+
+ dev->setClass(data[4]);
+ dev->setSubClass(data[5]);
+ dev->setProtocol(data[6]);
+ dev->setVid(data[8] | (data[9] << 8));
+ dev->setPid(data[10] | (data[11] << 8));
+ USB_DBG("CLASS: %02X \t VID: %04X \t PID: %04X", data[4], data[8] | (data[9] << 8), data[10] | (data[11] << 8));
+
+ pEnumerator->setVidPid( data[8] | (data[9] << 8), data[10] | (data[11] << 8) );
+
+ res = getConfigurationDescriptor(dev, data, sizeof(data), &total_conf_descr_length);
+ if (res != USB_TYPE_OK) {
+ return res;
+ }
+
+ #if (DEBUG > 3)
+ USB_DBG("CONFIGURATION DESCRIPTOR:\r\n");
+ for (int i = 0; i < total_conf_descr_length; i++)
+ printf("%02X ", data[i]);
+ printf("\r\n\r\n");
+ #endif
+
+ // Parse the configuration descriptor
+ parseConfDescr(dev, data, total_conf_descr_length, pEnumerator);
+
+ // only set configuration if not enumerated before
+ if (!dev->isEnumerated()) {
+
+ USB_DBG("Set configuration 1 on dev: %p", dev);
+ // sixth step: set configuration (only 1 supported)
+ res = setConfiguration(dev, 1);
+
+ if (res != USB_TYPE_OK) {
+ USB_DBG("SET CONF FAILED");
+ return res;
+ }
+ }
+
+ dev->setEnumerated();
+
+ // Now the device is enumerated!
+ USB_DBG("dev %p is enumerated\r\n", dev);
+
+ } while(0);
+
+ // Some devices may require this delay
+ Thread::wait(100);
+
+ return USB_TYPE_OK;
+}
+// this method fills the USBDeviceConnected object: class,.... . It also add endpoints found in the descriptor.
+void USBHost::parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator)
+{
+ uint32_t index = 0;
+ uint32_t len_desc = 0;
+ uint8_t id = 0;
+ int nb_endpoints_used = 0;
+ USBEndpoint * ep = NULL;
+ uint8_t intf_nb = 0;
+ bool parsing_intf = false;
+ uint8_t current_intf = 0;
+
+ while (index < len) {
+ len_desc = conf_descr[index];
+ id = conf_descr[index+1];
+ switch (id) {
+ case CONFIGURATION_DESCRIPTOR:
+ USB_DBG("dev: %p has %d intf", dev, conf_descr[4]);
+ dev->setNbIntf(conf_descr[4]);
+ break;
+ case INTERFACE_DESCRIPTOR:
+ if(pEnumerator->parseInterface(conf_descr[index + 2], conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7])) {
+ if (intf_nb++ <= MAX_INTF) {
+ current_intf = conf_descr[index + 2];
+ dev->addInterface(current_intf, conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7]);
+ nb_endpoints_used = 0;
+ USB_DBG("ADD INTF %d on device %p: class: %d, subclass: %d, proto: %d", current_intf, dev, conf_descr[index + 5],conf_descr[index + 6],conf_descr[index + 7]);
+ } else {
+ USB_DBG("Drop intf...");
+ }
+ parsing_intf = true;
+ } else {
+ parsing_intf = false;
+ }
+ break;
+ case ENDPOINT_DESCRIPTOR:
+ if (parsing_intf && (intf_nb <= MAX_INTF) ) {
+ if (nb_endpoints_used < MAX_ENDPOINT_PER_INTERFACE) {
+ if( pEnumerator->useEndpoint(current_intf, (ENDPOINT_TYPE)(conf_descr[index + 3] & 0x03), (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1)) ) {
+ // if the USBEndpoint is isochronous -> skip it (TODO: fix this)
+ if ((conf_descr[index + 3] & 0x03) != ISOCHRONOUS_ENDPOINT) {
+ ep = newEndpoint((ENDPOINT_TYPE)(conf_descr[index+3] & 0x03),
+ (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1),
+ conf_descr[index + 4] | (conf_descr[index + 5] << 8),
+ conf_descr[index + 2] & 0x0f);
+ USB_DBG("ADD USBEndpoint %p, on interf %d on device %p", ep, current_intf, dev);
+ if (ep != NULL && dev != NULL) {
+ addEndpoint(dev, current_intf, ep);
+ } else {
+ USB_DBG("EP NULL");
+ }
+ nb_endpoints_used++;
+ } else {
+ USB_DBG("ISO USBEndpoint NOT SUPPORTED");
+ }
+ }
+ }
+ }
+ break;
+ case HID_DESCRIPTOR:
+ lenReportDescr = conf_descr[index + 7] | (conf_descr[index + 8] << 8);
+ break;
+ default:
+ break;
+ }
+ index += len_desc;
+ }
+}
+
+
+USB_TYPE USBHost::bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::generalTransfer(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking, ENDPOINT_TYPE type, bool write) {
+
+#if DEBUG_TRANSFER
+ const char * type_str = (type == BULK_ENDPOINT) ? "BULK" : ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" : "ISOCHRONOUS");
+ USB_DBG_TRANSFER("----- %s %s [dev: %p - %s - hub: %d - port: %d - addr: %d - ep: %02X]------", type_str, (write) ? "WRITE" : "READ", dev, dev->getName(ep->getIntfNb()), dev->getHub(), dev->getPort(), dev->getAddress(), ep->getAddress());
+#endif
+
+ Lock lock(this);
+
+ USB_TYPE res;
+ ENDPOINT_DIRECTION dir = (write) ? OUT : IN;
+
+ if (dev == NULL) {
+ USB_ERR("dev NULL");
+ return USB_TYPE_ERROR;
+ }
+
+ if (ep == NULL) {
+ USB_ERR("ep NULL");
+ return USB_TYPE_ERROR;
+ }
+
+ if (ep->getState() != USB_TYPE_IDLE) {
+ USB_WARN("[ep: %p - dev: %p - %s] NOT IDLE: %s", ep, ep->dev, ep->dev->getName(ep->getIntfNb()), ep->getStateString());
+ return ep->getState();
+ }
+
+ if ((ep->getDir() != dir) || (ep->getType() != type)) {
+ USB_ERR("[ep: %p - dev: %p] wrong dir or bad USBEndpoint type", ep, ep->dev);
+ return USB_TYPE_ERROR;
+ }
+
+ if (dev->getAddress() != ep->getDeviceAddress()) {
+ USB_ERR("[ep: %p - dev: %p] USBEndpoint addr and device addr don't match", ep, ep->dev);
+ return USB_TYPE_ERROR;
+ }
+
+#if DEBUG_TRANSFER
+ if (write) {
+ USB_DBG_TRANSFER("%s WRITE buffer", type_str);
+ for (int i = 0; i < ep->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+ addTransfer(ep, buf, len);
+
+ if (blocking) {
+
+ ep->ep_queue.get();
+ res = ep->getState();
+
+ USB_DBG_TRANSFER("%s TRANSFER res: %s on ep: %p\r\n", type_str, ep->getStateString(), ep);
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+
+ return USB_TYPE_OK;
+ }
+
+ return USB_TYPE_PROCESSING;
+
+}
+
+
+USB_TYPE USBHost::controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+ return controlTransfer(dev, requestType, request, value, index, buf, len, false);
+}
+
+USB_TYPE USBHost::controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+ return controlTransfer(dev, requestType, request, value, index, buf, len, true);
+}
+
+USB_TYPE USBHost::controlTransfer(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len, bool write)
+{
+ Lock lock(this);
+ USB_DBG_TRANSFER("----- CONTROL %s [dev: %p - hub: %d - port: %d] ------", (write) ? "WRITE" : "READ", dev, dev->getHub(), dev->getPort());
+
+ int length_transfer = len;
+ USB_TYPE res;
+ uint32_t token;
+
+ control->setSpeed(dev->getSpeed());
+ control->setSize(dev->getSizeControlEndpoint());
+ if (dev->isActiveAddress()) {
+ control->setDeviceAddress(dev->getAddress());
+ } else {
+ control->setDeviceAddress(0);
+ }
+
+ USB_DBG_TRANSFER("Control transfer on device: %d\r\n", control->getDeviceAddress());
+ fillControlBuf(requestType, request, value, index, len);
+
+#if DEBUG_TRANSFER
+ USB_DBG_TRANSFER("SETUP PACKET: ");
+ for (int i = 0; i < 8; i++)
+ printf("%01X ", setupPacket[i]);
+ printf("\r\n");
+#endif
+
+ control->setNextToken(TD_SETUP);
+ addTransfer(control, (uint8_t*)setupPacket, 8);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+ USB_DBG_TRANSFER("CONTROL setup stage %s", control->getStateString());
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+
+ if (length_transfer) {
+ token = (write) ? TD_OUT : TD_IN;
+ control->setNextToken(token);
+ addTransfer(control, (uint8_t *)buf, length_transfer);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+#if DEBUG_TRANSFER
+ USB_DBG_TRANSFER("CONTROL %s stage %s", (write) ? "WRITE" : "READ", control->getStateString());
+ if (write) {
+ USB_DBG_TRANSFER("CONTROL WRITE buffer");
+ for (int i = 0; i < control->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ } else {
+ USB_DBG_TRANSFER("CONTROL READ SUCCESS [%d bytes transferred]", control->getLengthTransferred());
+ for (int i = 0; i < control->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+ }
+
+ token = (write) ? TD_IN : TD_OUT;
+ control->setNextToken(token);
+ addTransfer(control, NULL, 0);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+ USB_DBG_TRANSFER("CONTROL ack stage %s", control->getStateString());
+
+ if (res != USB_TYPE_IDLE)
+ return res;
+
+ return USB_TYPE_OK;
+}
+
+
+void USBHost::fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len)
+{
+ setupPacket[0] = requestType;
+ setupPacket[1] = request;
+ setupPacket[2] = (uint8_t) value;
+ setupPacket[3] = (uint8_t) (value >> 8);
+ setupPacket[4] = (uint8_t) index;
+ setupPacket[5] = (uint8_t) (index >> 8);
+ setupPacket[6] = (uint8_t) len;
+ setupPacket[7] = (uint8_t) (len >> 8);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h
new file mode 100644
index 000000000..802ae9931
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h
@@ -0,0 +1,395 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_H
+#define USBHOST_H
+
+#include "USBHALHost.h"
+#include "USBDeviceConnected.h"
+#include "IUSBEnumerator.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+#include "dbg.h"
+#include "USBHostHub.h"
+
+/**
+* USBHost class
+* This class is a singleton. All drivers have a reference on the static USBHost instance
+*/
+class USBHost : public USBHALHost {
+public:
+ /**
+ * Static method to create or retrieve the single USBHost instance
+ */
+ static USBHost * getHostInst();
+
+ /**
+ * Control read: setup stage, data stage and status stage
+ *
+ * @param dev the control read will be done for this device
+ * @param requestType request type
+ * @param request request
+ * @param value value
+ * @param index index
+ * @param buf pointer on a buffer where will be store the data received
+ * @param len length of the transfer
+ *
+ * @returns status of the control read
+ */
+ USB_TYPE controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+ /**
+ * Control write: setup stage, data stage and status stage
+ *
+ * @param dev the control write will be done for this device
+ * @param requestType request type
+ * @param request request
+ * @param value value
+ * @param index index
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ *
+ * @returns status of the control write
+ */
+ USB_TYPE controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+ /**
+ * Bulk read
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to read a packet
+ * @param buf pointer on a buffer where will be store the data received
+ * @param len length of the transfer
+ * @param blocking if true, the read is blocking (wait for completion)
+ *
+ * @returns status of the bulk read
+ */
+ USB_TYPE bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Bulk write
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the write is blocking (wait for completion)
+ *
+ * @returns status of the bulk write
+ */
+ USB_TYPE bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Interrupt read
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the read is blocking (wait for completion)
+ *
+ * @returns status of the interrupt read
+ */
+ USB_TYPE interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Interrupt write
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the write is blocking (wait for completion)
+ *
+ * @returns status of the interrupt write
+ */
+ USB_TYPE interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Enumerate a device.
+ *
+ * @param dev device which will be enumerated
+ *
+ * @returns status of the enumeration
+ */
+ USB_TYPE enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator);
+
+ /**
+ * reset a specific device
+ *
+ * @param dev device which will be resetted
+ */
+ USB_TYPE resetDevice(USBDeviceConnected * dev);
+
+ /**
+ * Get a device
+ *
+ * @param index index of the device which will be returned
+ *
+ * @returns pointer on the "index" device
+ */
+ USBDeviceConnected * getDevice(uint8_t index);
+
+ /*
+ * If there is a HID device connected, the host stores the length of the report descriptor.
+ * This avoid to the driver to re-ask the configuration descriptor to request the report descriptor
+ *
+ * @returns length of the report descriptor
+ */
+ inline uint16_t getLengthReportDescr() {
+ return lenReportDescr;
+ };
+
+ /**
+ * register a driver into the host associated with a callback function called when the device is disconnected
+ *
+ * @param dev device
+ * @param intf interface number
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, T* tptr, void (T::*mptr)(void)) {
+ int index = findDevice(dev);
+ if ((index != -1) && (mptr != NULL) && (tptr != NULL)) {
+ USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+ deviceAttachedDriver[index][intf] = true;
+ dev->onDisconnect(intf, tptr, mptr);
+ }
+ }
+
+ /**
+ * register a driver into the host associated with a callback function called when the device is disconnected
+ *
+ * @param dev device
+ * @param intf interface number
+ * @param fn callback called when the specified device has been disconnected
+ */
+ inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, void (*fn)(void)) {
+ int index = findDevice(dev);
+ if ((index != -1) && (fn != NULL)) {
+ USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+ deviceAttachedDriver[index][intf] = true;
+ dev->onDisconnect(intf, fn);
+ }
+ }
+
+ /**
+ * Instantiate to protect USB thread from accessing shared objects (USBConnectedDevices and Interfaces)
+ */
+ class Lock
+ {
+ public:
+ Lock(USBHost* pHost);
+ ~Lock();
+ private:
+ USBHost* m_pHost;
+ };
+
+ friend class USBHostHub;
+
+protected:
+
+ /**
+ * Virtual method called when a transfer has been completed
+ *
+ * @param addr list of the TDs which have been completed
+ */
+ virtual void transferCompleted(volatile uint32_t addr);
+
+ /**
+ * Virtual method called when a device has been connected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param lowSpeed 1 if low speed, 0 otherwise
+ * @param hub_parent reference on the parent hub
+ */
+ virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL);
+
+ /**
+ * Virtuel method called when a device has been disconnected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param addr list of the TDs which have been completed to dequeue freed TDs
+ */
+ virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
+
+
+private:
+ // singleton class -> constructor is private
+ USBHost();
+ static USBHost * instHost;
+ uint16_t lenReportDescr;
+
+ // endpoints
+ void unqueueEndpoint(USBEndpoint * ep) ;
+ USBEndpoint endpoints[MAX_ENDPOINT];
+ USBEndpoint* volatile control;
+
+ USBEndpoint* volatile headControlEndpoint;
+ USBEndpoint* volatile headBulkEndpoint;
+ USBEndpoint* volatile headInterruptEndpoint;
+
+ USBEndpoint* volatile tailControlEndpoint;
+ USBEndpoint* volatile tailBulkEndpoint;
+ USBEndpoint* volatile tailInterruptEndpoint;
+
+ bool controlEndpointAllocated;
+
+ // devices connected
+ USBDeviceConnected devices[MAX_DEVICE_CONNECTED];
+ bool deviceInUse[MAX_DEVICE_CONNECTED];
+ bool deviceAttachedDriver[MAX_DEVICE_CONNECTED][MAX_INTF];
+ bool deviceReset[MAX_DEVICE_CONNECTED];
+ bool deviceInited[MAX_DEVICE_CONNECTED];
+
+#if MAX_HUB_NB
+ USBHostHub hubs[MAX_HUB_NB];
+ bool hub_in_use[MAX_HUB_NB];
+#endif
+
+ // to store a setup packet
+ uint8_t setupPacket[8];
+
+ typedef struct {
+ uint8_t event_id;
+ void * td_addr;
+ uint8_t hub;
+ uint8_t port;
+ uint8_t lowSpeed;
+ uint8_t td_state;
+ void * hub_parent;
+ } message_t;
+
+ Thread usbThread;
+ void usb_process();
+ static void usb_process_static(void const * arg);
+ Mail<message_t, 10> mail_usb_event;
+ Mutex usb_mutex;
+ Mutex td_mutex;
+
+ // buffer for conf descriptor
+ uint8_t data[415];
+
+ /**
+ * Add a transfer on the TD linked list associated to an ED
+ *
+ * @param ed the transfer is associated to this ed
+ * @param buf pointer on a buffer where will be read/write data to send or receive
+ * @param len transfer length
+ *
+ * @return status of the transfer
+ */
+ USB_TYPE addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len) ;
+
+ /**
+ * Link the USBEndpoint to the linked list and attach an USBEndpoint this USBEndpoint to a device
+ *
+ * @param dev pointer on a USBDeviceConnected object
+ * @param ep pointer on the USBEndpoint which will be added
+ *
+ * return true if successful
+ */
+ bool addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep) ;
+
+ /**
+ * Create an USBEndpoint descriptor. Warning: the USBEndpoint is not linked.
+ *
+ * @param type USBEndpoint type (CONTROL_ENDPOINT, BULK_ENDPOINT, INTERRUPT_ENDPOINT)
+ * @param dir USBEndpoint direction (no meaning for CONTROL_ENDPOINT)
+ * @param size USBEndpoint max packet size
+ * @param addr USBEndpoint address
+ *
+ * @returns pointer on the USBEndpoint created
+ */
+ USBEndpoint * newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr) ;
+
+ /**
+ * Request the device descriptor
+ *
+ * @param dev request the device descriptor on this device
+ * @param buf buffer to store the device descriptor
+ * @param max_len_buf maximum size of buf
+ * @param len_dev_descr pointer to store the length of the packet transferred
+ */
+ USB_TYPE getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr = NULL);
+
+ /**
+ * Request the configuration descriptor
+ *
+ * @param dev request the configuration descriptor on this device
+ * @param buf buffer to store the configuration descriptor
+ * @param max_len_buf maximum size of buf
+ * @param len_conf_descr pointer to store the length of the packet transferred
+ */
+ USB_TYPE getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr = NULL);
+
+ /**
+ * Set the address of a specific device
+ *
+ * @param dev device to set the address
+ * @param address address
+ */
+ USB_TYPE setAddress(USBDeviceConnected * dev, uint8_t address);
+
+ /**
+ * Set the configuration of a device
+ *
+ * @param dev device on which the specified configuration will be activated
+ * @param conf configuration number to activate (usually 1)
+ */
+ USB_TYPE setConfiguration(USBDeviceConnected * dev, uint8_t conf);
+
+ /**
+ * Free a specific device
+ *
+ * @param dev device to be freed
+ */
+ void freeDevice(USBDeviceConnected * dev);
+
+ USB_TYPE controlTransfer( USBDeviceConnected * dev,
+ uint8_t requestType,
+ uint8_t request,
+ uint32_t value,
+ uint32_t index,
+ uint8_t * buf,
+ uint32_t len,
+ bool write);
+
+ USB_TYPE generalTransfer( USBDeviceConnected * dev,
+ USBEndpoint * ep,
+ uint8_t * buf,
+ uint32_t len,
+ bool blocking,
+ ENDPOINT_TYPE type,
+ bool write) ;
+
+ void fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len) ;
+ void parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator) ;
+ int findDevice(USBDeviceConnected * dev) ;
+ int findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent = NULL) ;
+ uint8_t numberDriverAttached(USBDeviceConnected * dev);
+
+ /////////////////////////
+ /// FOR DEBUG
+ /////////////////////////
+ void printList(ENDPOINT_TYPE type);
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h
new file mode 100644
index 000000000..3a93b30bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h
@@ -0,0 +1,91 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_CONF_H
+#define USBHOST_CONF_H
+
+/*
+* Maximum number of devices that can be connected
+* to the usb host
+*/
+#define MAX_DEVICE_CONNECTED 5
+
+/*
+* Maximum of Hub connected to the usb host
+*/
+#define MAX_HUB_NB 2
+
+/*
+* Maximum number of ports on a USB hub
+*/
+#define MAX_HUB_PORT 4
+
+/*
+* Enable USBHostMSD
+*/
+#define USBHOST_MSD 1
+
+/*
+* Enable USBHostKeyboard
+*/
+#define USBHOST_KEYBOARD 1
+
+/*
+* Enable USBHostMouse
+*/
+#define USBHOST_MOUSE 1
+
+/*
+* Enable USBHostSerial or USBHostMultiSerial (if set > 1)
+*/
+#define USBHOST_SERIAL 1
+
+/*
+* Enable USB3Gmodule
+*/
+#define USBHOST_3GMODULE 1
+
+/*
+* Enable USB MIDI
+*/
+#define USBHOST_MIDI 1
+
+/*
+* Maximum number of interfaces of a usb device
+*/
+#define MAX_INTF 4
+
+/*
+* Maximum number of endpoints on each interface
+*/
+#define MAX_ENDPOINT_PER_INTERFACE 3
+
+/*
+* Maximum number of endpoint descriptors that can be allocated
+*/
+#define MAX_ENDPOINT (MAX_DEVICE_CONNECTED * MAX_INTF * MAX_ENDPOINT_PER_INTERFACE)
+
+/*
+* Maximum number of transfer descriptors that can be allocated
+*/
+#define MAX_TD (MAX_ENDPOINT*2)
+
+/*
+* usb_thread stack size
+*/
+#define USB_THREAD_STACK (256*4 + MAX_HUB_NB*256*4)
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h
new file mode 100644
index 000000000..c4462aa05
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h
@@ -0,0 +1,226 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_INC_H
+#define USB_INC_H
+
+#include "mbed.h"
+#include "toolchain.h"
+
+enum USB_TYPE {
+ USB_TYPE_OK = 0,
+
+ // completion code
+ USB_TYPE_CRC_ERROR = 1,
+ USB_TYPE_BIT_STUFFING_ERROR = 2,
+ USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
+ USB_TYPE_STALL_ERROR = 4,
+ USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
+ USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
+ USB_TYPE_UNEXPECTED_PID_ERROR = 7,
+ USB_TYPE_DATA_OVERRUN_ERROR = 8,
+ USB_TYPE_DATA_UNDERRUN_ERROR = 9,
+ USB_TYPE_RESERVED = 9,
+ USB_TYPE_RESERVED_ = 10,
+ USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
+ USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
+
+ // general usb state
+ USB_TYPE_DISCONNECTED = 14,
+ USB_TYPE_FREE = 15,
+ USB_TYPE_IDLE = 16,
+ USB_TYPE_PROCESSING = 17,
+
+ USB_TYPE_ERROR = 18,
+};
+
+
+enum ENDPOINT_DIRECTION {
+ OUT = 1,
+ IN
+};
+
+enum ENDPOINT_TYPE {
+ CONTROL_ENDPOINT = 0,
+ ISOCHRONOUS_ENDPOINT,
+ BULK_ENDPOINT,
+ INTERRUPT_ENDPOINT
+};
+
+#define AUDIO_CLASS 0x01
+#define CDC_CLASS 0x02
+#define HID_CLASS 0x03
+#define MSD_CLASS 0x08
+#define HUB_CLASS 0x09
+#define SERIAL_CLASS 0x0A
+
+// ------------------ HcControl Register ---------------------
+#define OR_CONTROL_PLE 0x00000004
+#define OR_CONTROL_CLE 0x00000010
+#define OR_CONTROL_BLE 0x00000020
+#define OR_CONTROL_HCFS 0x000000C0
+#define OR_CONTROL_HC_OPER 0x00000080
+// ----------------- HcCommandStatus Register -----------------
+#define OR_CMD_STATUS_HCR 0x00000001
+#define OR_CMD_STATUS_CLF 0x00000002
+#define OR_CMD_STATUS_BLF 0x00000004
+// --------------- HcInterruptStatus Register -----------------
+#define OR_INTR_STATUS_WDH 0x00000002
+#define OR_INTR_STATUS_RHSC 0x00000040
+#define OR_INTR_STATUS_UE 0x00000010
+// --------------- HcInterruptEnable Register -----------------
+#define OR_INTR_ENABLE_WDH 0x00000002
+#define OR_INTR_ENABLE_RHSC 0x00000040
+#define OR_INTR_ENABLE_MIE 0x80000000
+// ---------------- HcRhDescriptorA Register ------------------
+#define OR_RH_STATUS_LPSC 0x00010000
+#define OR_RH_STATUS_DRWE 0x00008000
+// -------------- HcRhPortStatus[1:NDP] Register --------------
+#define OR_RH_PORT_CCS 0x00000001
+#define OR_RH_PORT_PRS 0x00000010
+#define OR_RH_PORT_CSC 0x00010000
+#define OR_RH_PORT_PRSC 0x00100000
+#define OR_RH_PORT_LSDA 0x00000200
+
+#define FI 0x2EDF // 12000 bits per frame (-1)
+#define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
+
+#define ED_SKIP (uint32_t) (0x00001000) // Skip this ep in queue
+
+#define TD_ROUNDING (uint32_t) (0x00040000) // Buffer Rounding
+#define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
+#define TD_IN (uint32_t)(0x00100000) // Direction In
+#define TD_OUT (uint32_t)(0x00080000) // Direction Out
+#define TD_DELAY_INT(x) (uint32_t)((x) << 21) // Delay Interrupt
+#define TD_TOGGLE_0 (uint32_t)(0x02000000) // Toggle 0
+#define TD_TOGGLE_1 (uint32_t)(0x03000000) // Toggle 1
+#define TD_CC (uint32_t)(0xF0000000) // Completion Code
+
+#define DEVICE_DESCRIPTOR (1)
+#define CONFIGURATION_DESCRIPTOR (2)
+#define INTERFACE_DESCRIPTOR (4)
+#define ENDPOINT_DESCRIPTOR (5)
+#define HID_DESCRIPTOR (33)
+
+// ----------- Control RequestType Fields -----------
+#define USB_DEVICE_TO_HOST 0x80
+#define USB_HOST_TO_DEVICE 0x00
+#define USB_REQUEST_TYPE_CLASS 0x20
+#define USB_REQUEST_TYPE_STANDARD 0x00
+#define USB_RECIPIENT_DEVICE 0x00
+#define USB_RECIPIENT_INTERFACE 0x01
+#define USB_RECIPIENT_ENDPOINT 0x02
+
+// -------------- USB Standard Requests --------------
+#define SET_ADDRESS 0x05
+#define GET_DESCRIPTOR 0x06
+#define SET_CONFIGURATION 0x09
+#define SET_INTERFACE 0x0b
+#define CLEAR_FEATURE 0x01
+
+// -------------- USB Descriptor Length --------------
+#define DEVICE_DESCRIPTOR_LENGTH 0x12
+#define CONFIGURATION_DESCRIPTOR_LENGTH 0x09
+
+// ------------ HostController Transfer Descriptor ------------
+typedef struct HCTD {
+ __IO uint32_t control; // Transfer descriptor control
+ __IO uint8_t * currBufPtr; // Physical address of current buffer pointer
+ __IO HCTD * nextTD; // Physical pointer to next Transfer Descriptor
+ __IO uint8_t * bufEnd; // Physical address of end of buffer
+ void * ep; // ep address where a td is linked in
+ uint32_t dummy[3]; // padding
+} PACKED HCTD;
+
+// ----------- HostController EndPoint Descriptor -------------
+typedef struct hcEd {
+ __IO uint32_t control; // Endpoint descriptor control
+ __IO HCTD * tailTD; // Physical address of tail in Transfer descriptor list
+ __IO HCTD * headTD; // Physcial address of head in Transfer descriptor list
+ __IO hcEd * nextED; // Physical address of next Endpoint descriptor
+} PACKED HCED;
+
+
+// ----------- Host Controller Communication Area ------------
+typedef struct hcca {
+ __IO uint32_t IntTable[32]; // Interrupt Table
+ __IO uint32_t FrameNumber; // Frame Number
+ __IO uint32_t DoneHead; // Done Head
+ volatile uint8_t Reserved[116]; // Reserved for future use
+ volatile uint8_t Unknown[4]; // Unused
+} PACKED HCCA;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize;
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} PACKED DeviceDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} PACKED ConfigurationDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} InterfaceDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint16_t wMaxPacketSize;
+ uint8_t bInterval;
+} EndpointDescriptor;
+
+typedef struct {
+ uint8_t bDescLength;
+ uint8_t bDescriptorType;
+ uint8_t bNbrPorts;
+ uint16_t wHubCharacteristics;
+ uint8_t bPwrOn2PwrGood;
+ uint8_t bHubContrCurrent;
+ uint8_t DeviceRemovable;
+ uint8_t PortPweCtrlMak;
+} HubDescriptor;
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h
new file mode 100644
index 000000000..33deb4843
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h
@@ -0,0 +1,66 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_DEBUG_H
+#define USB_DEBUG_H
+
+//Debug is disabled by default
+#define DEBUG 3 /*INFO,ERR,WARN*/
+#define DEBUG_TRANSFER 0
+#define DEBUG_EP_STATE 0
+#define DEBUG_EVENT 0
+
+#if (DEBUG > 3)
+#define USB_DBG(x, ...) std::printf("[USB_DBG: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG(x, ...)
+#endif
+
+#if (DEBUG > 2)
+#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_INFO(x, ...)
+#endif
+
+#if (DEBUG > 1)
+#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_WARN(x, ...)
+#endif
+
+#if (DEBUG > 0)
+#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_ERR(x, ...)
+#endif
+
+#if (DEBUG_TRANSFER)
+#define USB_DBG_TRANSFER(x, ...) std::printf("[USB_TRANSFER: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_TRANSFER(x, ...)
+#endif
+
+#if (DEBUG_EVENT)
+#define USB_DBG_EVENT(x, ...) std::printf("[USB_EVENT: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_EVENT(x, ...)
+#endif
+
+
+#endif
+
+
+
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h
new file mode 100644
index 000000000..5814fdd88
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h
@@ -0,0 +1,95 @@
+/* IUSBHostSerial.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef IUSBHOSTSERIAL_H_
+#define IUSBHOSTSERIAL_H_
+
+/**
+ * Generic interface to abstract 3G dongles' impl
+ */
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "IUSBHostSerialListener.h"
+
+// This is needed by some versions of GCC
+#undef putc
+#undef getc
+
+class IUSBHostSerial {
+public:
+
+ enum IrqType {
+ RxIrq,
+ TxIrq
+ };
+
+ /*
+ * Get a char from the dongle's serial interface
+ */
+ virtual int getc() = 0;
+
+ /*
+ * Put a char to the dongle's serial interface
+ */
+ virtual int putc(int c) = 0;
+
+ /*
+ * Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+ */
+ virtual int readPacket() = 0;
+
+ /*
+ * Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+ */
+ virtual int writePacket() = 0;
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int readable() = 0;
+
+ /**
+ * Check the free space in output.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int writeable() = 0;
+
+ /**
+ * Attach a handler to call when a packet is received / when a packet has been transmitted.
+ *
+ * @param pListener instance of the listener deriving from the IUSBHostSerialListener
+ */
+ virtual void attach(IUSBHostSerialListener* pListener) = 0;
+
+ /**
+ * Enable or disable readable/writeable callbacks
+ */
+ virtual void setupIrq(bool en, IrqType irq = RxIrq) = 0;
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIAL_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h
new file mode 100644
index 000000000..525b73463
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h
@@ -0,0 +1,37 @@
+/* IUSBHostSerialListener.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#ifndef IUSBHOSTSERIALLISTENER_H_
+#define IUSBHOSTSERIALLISTENER_H_
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+class IUSBHostSerialListener
+{
+public:
+ virtual void readable() = 0; //Called when new data is available
+ virtual void writeable() = 0; //Called when new space is available
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIALLISTENER_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp
new file mode 100644
index 000000000..49cafb7cc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp
@@ -0,0 +1,235 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongle.h"
+#include "WANDongleInitializer.h"
+
+WANDongle::WANDongle() : m_pInitializer(NULL), m_serialCount(0), m_totalInitializers(0)
+{
+ host = USBHost::getHostInst();
+ init();
+}
+
+
+bool WANDongle::connected() {
+ return dev_connected;
+}
+
+bool WANDongle::tryConnect()
+{
+ //FIXME should run on USB thread
+
+ USB_DBG("Trying to connect device");
+
+ if (dev_connected) {
+ USB_DBG("Device is already connected!");
+ return true;
+ }
+
+ m_pInitializer = NULL;
+
+ //Protect from concurrent access from USB thread
+ USBHost::Lock lock(host);
+
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ if ((dev = host->getDevice(i)) != NULL)
+ {
+ m_pInitializer = NULL; //Will be set in setVidPid callback
+
+ USB_DBG("Enumerate");
+ int ret = host->enumerate(dev, this);
+ if(ret)
+ {
+ return false;
+ }
+
+ USB_DBG("Device has VID:%04x PID:%04x", dev->getVid(), dev->getPid());
+
+ if(m_pInitializer) //If an initializer has been found
+ {
+ USB_DBG("m_pInitializer=%p", m_pInitializer);
+ USB_DBG("m_pInitializer->getSerialVid()=%04x", m_pInitializer->getSerialVid());
+ USB_DBG("m_pInitializer->getSerialPid()=%04x", m_pInitializer->getSerialPid());
+ if ((dev->getVid() == m_pInitializer->getSerialVid()) && (dev->getPid() == m_pInitializer->getSerialPid()))
+ {
+ USB_DBG("The dongle is in virtual serial mode");
+ host->registerDriver(dev, 0, this, &WANDongle::init);
+ m_serialCount = m_pInitializer->getSerialPortCount();
+ if( m_serialCount > WANDONGLE_MAX_SERIAL_PORTS )
+ {
+ m_serialCount = WANDONGLE_MAX_SERIAL_PORTS;
+ }
+ for(int j = 0; j < m_serialCount; j++)
+ {
+ USB_DBG("Connecting serial port #%d", j+1);
+ USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, false));
+ USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, true));
+ m_serial[j].connect( dev, m_pInitializer->getEp(dev, j, false), m_pInitializer->getEp(dev, j, true) );
+ }
+
+ USB_DBG("Device connected");
+
+ dev_connected = true;
+
+
+ return true;
+ }
+ else if ((dev->getVid() == m_pInitializer->getMSDVid()) && (dev->getPid() == m_pInitializer->getMSDPid()))
+ {
+ USB_DBG("Vodafone K3370 dongle detected in MSD mode");
+ //Try to switch
+ if( m_pInitializer->switchMode(dev) )
+ {
+ USB_DBG("Switched OK");
+ return false; //Will be connected on a next iteration
+ }
+ else
+ {
+ USB_ERR("Could not switch mode");
+ return false;
+ }
+ }
+ } //if()
+ } //if()
+ } //for()
+ return false;
+}
+
+bool WANDongle::disconnect()
+{
+ dev_connected = false;
+ for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+ {
+ m_serial[i].disconnect();
+ }
+ return true;
+}
+
+int WANDongle::getDongleType()
+{
+ if( m_pInitializer != NULL )
+ {
+ return m_pInitializer->getType();
+ }
+ else
+ {
+ return WAN_DONGLE_TYPE_UNKNOWN;
+ }
+}
+
+IUSBHostSerial& WANDongle::getSerial(int index)
+{
+ return m_serial[index];
+}
+
+int WANDongle::getSerialCount()
+{
+ return m_serialCount;
+}
+
+//Private methods
+void WANDongle::init()
+{
+ m_pInitializer = NULL;
+ dev_connected = false;
+ for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+ {
+ m_serial[i].init(host);
+ }
+}
+
+
+/*virtual*/ void WANDongle::setVidPid(uint16_t vid, uint16_t pid)
+{
+ WANDongleInitializer* initializer;
+
+ for(int i = 0; i < m_totalInitializers; i++)
+ {
+ initializer = m_Initializers[i];
+ USB_DBG("initializer=%p", initializer);
+ USB_DBG("initializer->getSerialVid()=%04x", initializer->getSerialVid());
+ USB_DBG("initializer->getSerialPid()=%04x", initializer->getSerialPid());
+ if ((dev->getVid() == initializer->getSerialVid()) && (dev->getPid() == initializer->getSerialPid()))
+ {
+ USB_DBG("The dongle is in virtual serial mode");
+ m_pInitializer = initializer;
+ break;
+ }
+ else if ((dev->getVid() == initializer->getMSDVid()) && (dev->getPid() == initializer->getMSDPid()))
+ {
+ USB_DBG("Dongle detected in MSD mode");
+ m_pInitializer = initializer;
+ break;
+ }
+ initializer++;
+ } //for
+ if(m_pInitializer)
+ {
+ m_pInitializer->setVidPid(vid, pid);
+ }
+}
+
+/*virtual*/ bool WANDongle::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if(m_pInitializer)
+ {
+ return m_pInitializer->parseInterface(intf_nb, intf_class, intf_subclass, intf_protocol);
+ }
+ else
+ {
+ return false;
+ }
+}
+
+/*virtual*/ bool WANDongle::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if(m_pInitializer)
+ {
+ return m_pInitializer->useEndpoint(intf_nb, type, dir);
+ }
+ else
+ {
+ return false;
+ }
+}
+
+
+bool WANDongle::addInitializer(WANDongleInitializer* pInitializer)
+{
+ if (m_totalInitializers >= WANDONGLE_MAX_INITIALIZERS)
+ return false;
+ m_Initializers[m_totalInitializers++] = pInitializer;
+ return true;
+}
+
+WANDongle::~WANDongle()
+{
+ for(int i = 0; i < m_totalInitializers; i++)
+ delete m_Initializers[i];
+}
+
+#endif /* USBHOST_3GMODULE */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h
new file mode 100644
index 000000000..960b8bcfb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h
@@ -0,0 +1,108 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLE_H
+#define WANDONGLE_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+#include "WANDongleInitializer.h"
+#include "IUSBEnumerator.h"
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongle : public IUSBEnumerator {
+public:
+ /*
+ * Constructor
+ *
+ * @param rootdir mount name
+ */
+ WANDongle();
+
+ /*
+ * Destructor
+ */
+ virtual ~WANDongle();
+
+ /*
+ * Check if a serial port device is connected
+ *
+ * @return true if a serial device is connected
+ */
+ bool connected();
+
+ /*
+ * Try to connect device
+ *
+ * * @return true if connection was successful
+ */
+ bool tryConnect();
+
+ /*
+ * Disconnect device
+ *
+ * * @return true if disconnection was successful
+ */
+ bool disconnect();
+
+ int getDongleType();
+
+ IUSBHostSerial& getSerial(int index);
+ int getSerialCount();
+ bool addInitializer(WANDongleInitializer* pInitializer);
+
+ //From IUSBEnumerator
+
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+protected:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+
+ WANDongleInitializer* m_pInitializer;
+
+ void init();
+
+ WANDongleSerialPort m_serial[WANDONGLE_MAX_SERIAL_PORTS];
+ int m_serialCount;
+
+ int m_totalInitializers;
+ WANDongleInitializer* m_Initializers[WANDONGLE_MAX_INITIALIZERS];
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h
new file mode 100644
index 000000000..2f0a4a37c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h
@@ -0,0 +1,73 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLEINITIALIZER_H
+#define WANDONGLEINITIALIZER_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include <stdint.h>
+
+#include "USBHost.h"
+#include "IUSBEnumerator.h"
+
+// [TODO] move these declarations to a proper place
+#define WANDONGLE_MAX_SERIAL_PORTS 2
+#define WANDONGLE_MAX_INITIALIZERS 6
+
+#define WAN_DONGLE_TYPE_UNKNOWN (-1)
+
+class WANDongleInitializer : public IUSBEnumerator
+{
+protected:
+ WANDongleInitializer(USBHost* pHost) { m_pHost = pHost; }
+ USBHost* m_pHost;
+ uint8_t m_serialIntfMap[WANDONGLE_MAX_SERIAL_PORTS];
+
+public:
+ virtual ~WANDongleInitializer() {}
+ virtual uint16_t getMSDVid() = 0;
+ virtual uint16_t getMSDPid() = 0;
+
+ virtual uint16_t getSerialVid() = 0;
+ virtual uint16_t getSerialPid() = 0;
+
+ virtual bool switchMode(USBDeviceConnected* pDev) = 0;
+
+ virtual USBEndpoint* getEp(USBDeviceConnected* pDev, int serialPortNumber, bool tx) {
+ return pDev->getEndpoint(m_serialIntfMap[serialPortNumber], BULK_ENDPOINT, tx ? OUT : IN, 0);
+ }
+
+ virtual int getSerialPortCount() = 0;
+
+ virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+
+ virtual int getType() = 0;
+
+ virtual uint8_t getSerialIntf(int index) { return m_serialIntfMap[index]; }
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp
new file mode 100644
index 000000000..96343f15c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp
@@ -0,0 +1,340 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#define __DEBUG__ 0
+#ifndef __MODULE__
+#define __MODULE__ "WANDongleSerialPort.cpp"
+#endif
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+
+WANDongleSerialPort::WANDongleSerialPort() : cb_tx_en(false), cb_rx_en(false), listener(NULL)
+{
+ reset();
+}
+
+void WANDongleSerialPort::init(USBHost* pHost)
+{
+ host = pHost;
+}
+
+void WANDongleSerialPort::reset()
+{
+ tx_mtx.lock();
+ rx_mtx.lock();
+
+ bulk_in = NULL;
+ bulk_out = NULL;
+
+ buf_out_len = 0;
+ max_out_size = 0;
+ lock_tx = false;
+ cb_tx_pending = false;
+
+ buf_in_len = 0;
+ buf_in_read_pos = 0;
+ lock_rx = false;
+ cb_rx_pending = false;
+
+ tx_mtx.unlock();
+ rx_mtx.unlock();
+}
+
+int WANDongleSerialPort::readPacket()
+{
+ USB_DBG("Read packet on %p", this);
+ rx_mtx.lock();
+ if(lock_rx)
+ {
+ USB_ERR("Fail");
+ rx_mtx.unlock();
+ return -1;
+ }
+
+ if( bulk_in == NULL )
+ {
+ USB_WARN("Port is disconnected");
+ rx_mtx.unlock();
+ return -1;
+ }
+
+ lock_rx = true; //Receiving
+ rx_mtx.unlock();
+// USB_DBG("readPacket");
+ //lock_rx.lock();
+ USB_TYPE res = host->bulkRead(dev, (USBEndpoint *)bulk_in, buf_in, ((USBEndpoint *)bulk_in)->getSize(), false); //Queue transfer
+ if(res != USB_TYPE_PROCESSING)
+ {
+ //lock_rx.unlock();
+ USB_ERR("host->bulkRead() returned %d", res);
+ Thread::wait(100);
+ return -1;
+ }
+ return 0;
+}
+
+int WANDongleSerialPort::writePacket()
+{
+ tx_mtx.lock();
+ if(lock_tx)
+ {
+ USB_ERR("Fail");
+ tx_mtx.unlock();
+ return -1;
+ }
+
+ if( bulk_out == NULL )
+ {
+ USB_WARN("Port is disconnected");
+ tx_mtx.unlock();
+ return -1;
+ }
+
+ lock_tx = true; //Transmitting
+ tx_mtx.unlock();
+// USB_DBG("writePacket");
+
+ //lock_tx.lock();
+ USB_TYPE res = host->bulkWrite(dev, (USBEndpoint *)bulk_out, buf_out, buf_out_len, false); //Queue transfer
+ if(res != USB_TYPE_PROCESSING)
+ {
+ //lock_tx.unlock();
+ USB_ERR("host->bulkWrite() returned %d", res);
+ Thread::wait(100);
+ return -1;
+ }
+ return 0;
+}
+
+int WANDongleSerialPort::putc(int c)
+{
+ tx_mtx.lock();
+ if(!lock_tx)
+ {
+ if(buf_out_len < max_out_size)
+ {
+ buf_out[buf_out_len] = (uint8_t)c;
+ buf_out_len++;
+ }
+ }
+ else
+ {
+ USB_ERR("CAN'T WRITE!");
+ }
+ tx_mtx.unlock();
+ return c;
+}
+
+int WANDongleSerialPort::getc()
+{
+ rx_mtx.lock();
+ int c = 0;
+ if(!lock_rx)
+ {
+ if(buf_in_read_pos < buf_in_len)
+ {
+ c = (int)buf_in[buf_in_read_pos];
+ buf_in_read_pos++;
+ }
+ }
+ else
+ {
+ USB_ERR("CAN'T READ!");
+ }
+ rx_mtx.unlock();
+ return c;
+}
+
+int WANDongleSerialPort::readable()
+{
+ rx_mtx.lock();
+ if (lock_rx)
+ {
+ rx_mtx.unlock();
+ return 0;
+ }
+
+ /* if( !lock_rx.trylock() )
+ {
+ return 0;
+ }*/
+ int res = buf_in_len - buf_in_read_pos;
+ //lock_rx.unlock();
+ rx_mtx.unlock();
+ return res;
+}
+
+int WANDongleSerialPort::writeable()
+{
+ tx_mtx.lock();
+ if (lock_tx)
+ {
+ tx_mtx.unlock();
+ return 0;
+ }
+
+ /*if( !lock_tx.trylock() )
+ {
+ return 0;
+ }*/
+ int res = max_out_size - buf_out_len;
+ tx_mtx.unlock();
+ //lock_tx.unlock();
+ return res;
+}
+
+void WANDongleSerialPort::attach(IUSBHostSerialListener* pListener)
+{
+ if(pListener == NULL)
+ {
+ setupIrq(false, RxIrq);
+ setupIrq(false, TxIrq);
+ }
+ listener = pListener;
+ if(pListener != NULL)
+ {
+ setupIrq(true, RxIrq);
+ setupIrq(true, TxIrq);
+ }
+}
+
+void WANDongleSerialPort::setupIrq(bool en, IrqType irq /*= RxIrq*/)
+{
+ switch(irq)
+ {
+ case RxIrq:
+ rx_mtx.lock();
+ cb_rx_en = en;
+ if(en && cb_rx_pending)
+ {
+ cb_rx_pending = false;
+ rx_mtx.unlock();
+ listener->readable(); //Process the interrupt that was raised
+ }
+ else
+ {
+ rx_mtx.unlock();
+ }
+ break;
+ case TxIrq:
+ tx_mtx.lock();
+ cb_tx_en = en;
+ if(en && cb_tx_pending)
+ {
+ cb_tx_pending = false;
+ tx_mtx.unlock();
+ listener->writeable(); //Process the interrupt that was raised
+ }
+ else
+ {
+ tx_mtx.unlock();
+ }
+ break;
+ }
+}
+
+
+void WANDongleSerialPort::connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp )
+{
+ dev = pDev;
+ bulk_in = pInEp;
+ bulk_out = pOutEp;
+ max_out_size = bulk_out->getSize();
+ if( max_out_size > WANDONGLE_MAX_OUTEP_SIZE )
+ {
+ max_out_size = WANDONGLE_MAX_OUTEP_SIZE;
+ }
+ bulk_in->attach(this, &WANDongleSerialPort::rxHandler);
+ bulk_out->attach(this, &WANDongleSerialPort::txHandler);
+ readPacket(); //Start receiving data
+}
+
+void WANDongleSerialPort::disconnect( )
+{
+ reset();
+}
+
+//Private methods
+
+
+void WANDongleSerialPort::rxHandler()
+{
+ if (((USBEndpoint *) bulk_in)->getState() == USB_TYPE_IDLE) //Success
+ {
+ buf_in_read_pos = 0;
+ buf_in_len = ((USBEndpoint *) bulk_in)->getLengthTransferred(); //Update length
+ //lock_rx.unlock();
+ rx_mtx.lock();
+ lock_rx = false; //Transmission complete
+ if(cb_rx_en)
+ {
+ rx_mtx.unlock();
+ listener->readable(); //Call handler from the IRQ context
+ //readPacket() should be called by the handler subsequently once the buffer has been emptied
+ }
+ else
+ {
+ cb_rx_pending = true; //Queue the callback
+ rx_mtx.unlock();
+ }
+
+ }
+ else //Error, try reading again
+ {
+ //lock_rx.unlock();
+ USB_DBG("Trying again");
+ readPacket();
+ }
+}
+
+void WANDongleSerialPort::txHandler()
+{
+ if (((USBEndpoint *) bulk_out)->getState() == USB_TYPE_IDLE) //Success
+ {
+ tx_mtx.lock();
+ buf_out_len = 0; //Reset length
+ lock_tx = false; //Transmission complete
+ //lock_tx.unlock();
+ if(cb_tx_en)
+ {
+ tx_mtx.unlock();
+ listener->writeable(); //Call handler from the IRQ context
+ //writePacket() should be called by the handler subsequently once the buffer has been filled
+ }
+ else
+ {
+ cb_tx_pending = true; //Queue the callback
+ tx_mtx.unlock();
+ }
+ }
+ else //Error, try reading again
+ {
+ //lock_tx.unlock();
+ writePacket();
+ }
+}
+
+#endif /* USBHOST_3GMODULE */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h
new file mode 100644
index 000000000..7c79d1734
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h
@@ -0,0 +1,133 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLESERIALPORT_H
+#define WANDONGLESERIALPORT_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongleSerialPort : public IUSBHostSerial {
+public:
+ /*
+ * Constructor
+ *
+ */
+ WANDongleSerialPort();
+
+ void init( USBHost* pHost );
+
+ void connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp );
+
+ void disconnect( );
+
+ /*
+ * Get a char from the dongle's serial interface
+ */
+ virtual int getc();
+
+ /*
+ * Put a char to the dongle's serial interface
+ */
+ virtual int putc(int c);
+
+ /*
+ * Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+ */
+ virtual int readPacket();
+
+ /*
+ * Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+ */
+ virtual int writePacket();
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int readable();
+
+ /**
+ * Check the free space in output.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int writeable();
+
+ /**
+ * Attach a handler to call when a packet is received / when a packet has been transmitted.
+ *
+ * @param pListener instance of the listener deriving from the IUSBHostSerialListener
+ */
+ virtual void attach(IUSBHostSerialListener* pListener);
+
+ /**
+ * Enable or disable readable/writeable callbacks
+ */
+ virtual void setupIrq(bool en, IrqType irq = RxIrq);
+
+
+protected:
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ USBHost * host;
+ USBDeviceConnected * dev;
+
+ uint8_t buf_out[WANDONGLE_MAX_OUTEP_SIZE];
+ volatile uint32_t buf_out_len;
+ uint32_t max_out_size;
+ volatile bool lock_tx;
+ volatile bool cb_tx_en;
+ volatile bool cb_tx_pending;
+ Mutex tx_mtx;
+
+ uint8_t buf_in[WANDONGLE_MAX_INEP_SIZE];
+ volatile uint32_t buf_in_len;
+ volatile uint32_t buf_in_read_pos;
+ volatile bool lock_rx;
+ volatile bool cb_rx_en;
+ volatile bool cb_rx_pending;
+ Mutex rx_mtx;
+
+ IUSBHostSerialListener* listener;
+
+ void reset();
+
+ void rxHandler();
+ void txHandler();
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp
new file mode 100644
index 000000000..dbb2cda53
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp
@@ -0,0 +1,184 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostKeyboard.h"
+
+#if USBHOST_KEYBOARD
+
+static uint8_t keymap[4][0x39] = {
+ { 0, 0, 0, 0, 'a', 'b' /*0x05*/,
+ 'c', 'd', 'e', 'f', 'g' /*0x0a*/,
+ 'h', 'i', 'j', 'k', 'l'/*0x0f*/,
+ 'm', 'n', 'o', 'p', 'q'/*0x14*/,
+ 'r', 's', 't', 'u', 'v'/*0x19*/,
+ 'w', 'x', 'y', 'z', '1'/*0x1E*/,
+ '2', '3', '4', '5', '6'/*0x23*/,
+ '7', '8', '9', '0', 0x0A /*enter*/, /*0x28*/
+ 0x1B /*escape*/, 0x08 /*backspace*/, 0x09/*tab*/, 0x20/*space*/, '-', /*0x2d*/
+ '=', '[', ']', '\\', '#', /*0x32*/
+ ';', '\'', 0, ',', '.', /*0x37*/
+ '/'},
+
+ /* CTRL MODIFIER */
+ { 0, 0, 0, 0, 0, 0 /*0x05*/,
+ 0, 0, 0, 0, 0 /*0x0a*/,
+ 0, 0, 0, 0, 0/*0x0f*/,
+ 0, 0, 0, 0, 0/*0x14*/,
+ 0, 0, 0, 0, 0/*0x19*/,
+ 0, 0, 0, 0, 0/*0x1E*/,
+ 0, 0, 0, 0, 0/*0x23*/,
+ 0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ 0, 0, 0, 0, 0, /*0x32*/
+ 0, 0, 0, 0, 0, /*0x37*/
+ 0},
+
+ /* SHIFT MODIFIER */
+ { 0, 0, 0, 0, 'A', 'B' /*0x05*/,
+ 'C', 'D', 'E', 'F', 'G' /*0x0a*/,
+ 'H', 'I', 'J', 'K', 'L'/*0x0f*/,
+ 'M', 'N', 'O', 'P', 'Q'/*0x14*/,
+ 'R', 'S', 'T', 'U', 'V'/*0x19*/,
+ 'W', 'X', 'Y', 'Z', '!'/*0x1E*/,
+ '@', '#', '$', '%', '^'/*0x23*/,
+ '&', '*', '(', ')', 0, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ '+', '{', '}', '|', '~', /*0x32*/
+ ':', '"', 0, '<', '>', /*0x37*/
+ '?'},
+
+ /* ALT MODIFIER */
+ { 0, 0, 0, 0, 0, 0 /*0x05*/,
+ 0, 0, 0, 0, 0 /*0x0a*/,
+ 0, 0, 0, 0, 0/*0x0f*/,
+ 0, 0, 0, 0, 0/*0x14*/,
+ 0, 0, 0, 0, 0/*0x19*/,
+ 0, 0, 0, 0, 0/*0x1E*/,
+ 0, 0, 0, 0, 0/*0x23*/,
+ 0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ 0, 0, 0, 0, 0, /*0x32*/
+ 0, 0, 0, 0, 0, /*0x37*/
+ 0}
+
+};
+
+
+USBHostKeyboard::USBHostKeyboard() {
+ host = USBHost::getHostInst();
+ init();
+}
+
+
+void USBHostKeyboard::init() {
+ dev = NULL;
+ int_in = NULL;
+ report_id = 0;
+ onKey = NULL;
+ onKeyCode = NULL;
+ dev_connected = false;
+ keyboard_intf = -1;
+ keyboard_device_found = false;
+}
+
+bool USBHostKeyboard::connected() {
+ return dev_connected;
+}
+
+
+bool USBHostKeyboard::connect() {
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ if (host->enumerate(dev, this))
+ break;
+
+ if (keyboard_device_found) {
+ int_in = dev->getEndpoint(keyboard_intf, INTERRUPT_ENDPOINT, IN);
+
+ if (!int_in)
+ break;
+
+ USB_INFO("New Keyboard device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, keyboard_intf);
+ dev->setName("Keyboard", keyboard_intf);
+ host->registerDriver(dev, keyboard_intf, this, &USBHostKeyboard::init);
+
+ int_in->attach(this, &USBHostKeyboard::rxHandler);
+ host->interruptRead(dev, int_in, report, int_in->getSize(), false);
+
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+ init();
+ return false;
+}
+
+void USBHostKeyboard::rxHandler() {
+ int len = int_in->getLengthTransferred();
+ int index = (len == 9) ? 1 : 0;
+ int len_listen = int_in->getSize();
+ uint8_t key = 0;
+ if (len == 8 || len == 9) {
+ uint8_t modifier = (report[index] == 4) ? 3 : report[index];
+ len_listen = len;
+ key = keymap[modifier][report[index + 2]];
+ if (key && onKey) {
+ (*onKey)(key);
+ }
+ if ((report[index + 2] || modifier) && onKeyCode) {
+ (*onKeyCode)(report[index + 2], modifier);
+ }
+ }
+ if (dev && int_in)
+ host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostKeyboard::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for keyboard driver
+}
+
+/*virtual*/ bool USBHostKeyboard::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((keyboard_intf == -1) &&
+ (intf_class == HID_CLASS) &&
+ (intf_subclass == 0x01) &&
+ (intf_protocol == 0x01)) {
+ keyboard_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostKeyboard::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == keyboard_intf) {
+ if (type == INTERRUPT_ENDPOINT && dir == IN) {
+ keyboard_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h
new file mode 100644
index 000000000..93730061c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h
@@ -0,0 +1,102 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTKEYBOARD_H
+#define USBHOSTKEYBOARD_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_KEYBOARD
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB keyboard
+ */
+class USBHostKeyboard : public IUSBEnumerator {
+public:
+
+ /**
+ * Constructor
+ */
+ USBHostKeyboard();
+
+ /**
+ * Try to connect a keyboard device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Check if a keyboard is connected
+ *
+ * @returns true if a keyboard is connected
+ */
+ bool connected();
+
+ /**
+ * Attach a callback called when a keyboard event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*ptr)(uint8_t key)) {
+ if (ptr != NULL) {
+ onKey = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when a keyboard event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*ptr)(uint8_t keyCode, uint8_t modifier)) {
+ if (ptr != NULL) {
+ onKeyCode = ptr;
+ }
+ }
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * int_in;
+ uint8_t report[9];
+ int keyboard_intf;
+ bool keyboard_device_found;
+
+ bool dev_connected;
+
+ void rxHandler();
+
+ void (*onKey)(uint8_t key);
+ void (*onKeyCode)(uint8_t key, uint8_t modifier);
+
+ int report_id;
+
+ void init();
+
+};
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp
new file mode 100644
index 000000000..52fcf8c5b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp
@@ -0,0 +1,153 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostMouse.h"
+
+#if USBHOST_MOUSE
+
+USBHostMouse::USBHostMouse() {
+ host = USBHost::getHostInst();
+ init();
+}
+
+void USBHostMouse::init() {
+ dev = NULL;
+ int_in = NULL;
+ onUpdate = NULL;
+ onButtonUpdate = NULL;
+ onXUpdate = NULL;
+ onYUpdate = NULL;
+ onZUpdate = NULL;
+ report_id = 0;
+ dev_connected = false;
+ mouse_device_found = false;
+ mouse_intf = -1;
+
+ buttons = 0;
+ x = 0;
+ y = 0;
+ z = 0;
+}
+
+bool USBHostMouse::connected() {
+ return dev_connected;
+}
+
+bool USBHostMouse::connect() {
+ int len_listen;
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ if(host->enumerate(dev, this))
+ break;
+
+ if (mouse_device_found) {
+
+ int_in = dev->getEndpoint(mouse_intf, INTERRUPT_ENDPOINT, IN);
+ if (!int_in)
+ break;
+
+ USB_INFO("New Mouse device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, mouse_intf);
+ dev->setName("Mouse", mouse_intf);
+ host->registerDriver(dev, mouse_intf, this, &USBHostMouse::init);
+
+ int_in->attach(this, &USBHostMouse::rxHandler);
+ len_listen = int_in->getSize();
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+ host->interruptRead(dev, int_in, report, len_listen, false);
+
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+ init();
+ return false;
+}
+
+void USBHostMouse::rxHandler() {
+ int len_listen = int_in->getSize();
+
+ if (onUpdate) {
+ (*onUpdate)(report[0] & 0x07, report[1], report[2], report[3]);
+ }
+
+ if (onButtonUpdate && (buttons != (report[0] & 0x07))) {
+ (*onButtonUpdate)(report[0] & 0x07);
+ }
+
+ if (onXUpdate && (x != report[1])) {
+ (*onXUpdate)(report[1]);
+ }
+
+ if (onYUpdate && (y != report[2])) {
+ (*onYUpdate)(report[2]);
+ }
+
+ if (onZUpdate && (z != report[3])) {
+ (*onZUpdate)(report[3]);
+ }
+
+ // update mouse state
+ buttons = report[0] & 0x07;
+ x = report[1];
+ y = report[2];
+ z = report[3];
+
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+
+ if (dev)
+ host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostMouse::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for mouse driver
+}
+
+/*virtual*/ bool USBHostMouse::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((mouse_intf == -1) &&
+ (intf_class == HID_CLASS) &&
+ (intf_subclass == 0x01) &&
+ (intf_protocol == 0x02)) {
+ mouse_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMouse::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == mouse_intf) {
+ if (type == INTERRUPT_ENDPOINT && dir == IN) {
+ mouse_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h
new file mode 100644
index 000000000..03e099448
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h
@@ -0,0 +1,139 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTMOUSE_H
+#define USBHOSTMOUSE_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MOUSE
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB mouse
+ */
+class USBHostMouse : public IUSBEnumerator {
+public:
+
+ /**
+ * Constructor
+ */
+ USBHostMouse();
+
+ /**
+ * Try to connect a mouse device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Check if a mouse is connected
+ *
+ * @returns true if a mouse is connected
+ */
+ bool connected();
+
+ /**
+ * Attach a callback called when a mouse event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attachEvent(void (*ptr)(uint8_t buttons, int8_t x, int8_t y, int8_t z)) {
+ if (ptr != NULL) {
+ onUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the button state changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachButtonEvent(void (*ptr)(uint8_t buttons)) {
+ if (ptr != NULL) {
+ onButtonUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the X axis value changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachXEvent(void (*ptr)(int8_t x)) {
+ if (ptr != NULL) {
+ onXUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the Y axis value changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachYEvent(void (*ptr)(int8_t y)) {
+ if (ptr != NULL) {
+ onYUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the Z axis value changes (scrolling)
+ *
+ * @param ptr function pointer
+ */
+ inline void attachZEvent(void (*ptr)(int8_t z)) {
+ if (ptr != NULL) {
+ onZUpdate = ptr;
+ }
+ }
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * int_in;
+ uint8_t report[4];
+
+ bool dev_connected;
+ bool mouse_device_found;
+ int mouse_intf;
+
+ uint8_t buttons;
+ int8_t x;
+ int8_t y;
+ int8_t z;
+
+ void rxHandler();
+ void (*onUpdate)(uint8_t buttons, int8_t x, int8_t y, int8_t z);
+ void (*onButtonUpdate)(uint8_t buttons);
+ void (*onXUpdate)(int8_t x);
+ void (*onYUpdate)(int8_t y);
+ void (*onZUpdate)(int8_t z);
+ int report_id;
+ void init();
+};
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp
new file mode 100644
index 000000000..75c57f3ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp
@@ -0,0 +1,274 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostHub.h"
+
+#if MAX_HUB_NB
+
+#include "USBHost.h"
+#include "dbg.h"
+
+#define GET_STATUS 0x00
+#define CLEAR_FEATURE 0x01
+#define GET_STATE 0x02
+#define SET_FEATURE 0x03
+#define GET_DESCRIPTOR 0x06
+
+#define PORT_CONNECTION_FEATURE (0x00)
+#define PORT_ENABLE_FEATURE (0x01)
+#define PORT_RESET_FEATURE (0x04)
+#define PORT_POWER_FEATURE (0x08)
+
+#define C_PORT_CONNECTION_FEATURE (16)
+#define C_PORT_ENABLE_FEATURE (17)
+#define C_PORT_RESET_FEATURE (20)
+
+#define PORT_CONNECTION (1 << 0)
+#define PORT_ENABLE (1 << 1)
+#define PORT_SUSPEND (1 << 2)
+#define PORT_OVER_CURRENT (1 << 3)
+#define PORT_RESET (1 << 4)
+#define PORT_POWER (1 << 8)
+#define PORT_LOW_SPEED (1 << 9)
+
+#define C_PORT_CONNECTION (1 << 16)
+#define C_PORT_ENABLE (1 << 17)
+#define C_PORT_SUSPEND (1 << 18)
+#define C_PORT_OVER_CURRENT (1 << 19)
+#define C_PORT_RESET (1 << 20)
+
+USBHostHub::USBHostHub() {
+ host = NULL;
+ init();
+}
+
+void USBHostHub::init() {
+ dev_connected = false;
+ dev = NULL;
+ int_in = NULL;
+ dev_connected = false;
+ hub_intf = -1;
+ hub_device_found = false;
+ nb_port = 0;
+ hub_characteristics = 0;
+
+ for (int i = 0; i < MAX_HUB_PORT; i++) {
+ device_children[i] = NULL;
+ }
+}
+
+void USBHostHub::setHost(USBHost * host_) {
+ host = host_;
+}
+
+bool USBHostHub::connected()
+{
+ return dev_connected;
+}
+
+bool USBHostHub::connect(USBDeviceConnected * dev)
+{
+ if (dev_connected) {
+ return true;
+ }
+
+ if(host->enumerate(dev, this)) {
+ init();
+ return false;
+ }
+
+ if (hub_device_found) {
+ this->dev = dev;
+
+ int_in = dev->getEndpoint(hub_intf, INTERRUPT_ENDPOINT, IN);
+
+ if (!int_in) {
+ init();
+ return false;
+ }
+
+ USB_INFO("New HUB: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, hub_intf);
+ dev->setName("Hub", hub_intf);
+ host->registerDriver(dev, hub_intf, this, &USBHostHub::disconnect);
+
+ int_in->attach(this, &USBHostHub::rxHandler);
+
+ // get HUB descriptor
+ host->controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS,
+ GET_DESCRIPTOR,
+ 0x29 << 8, 0, buf, sizeof(HubDescriptor));
+ nb_port = buf[2];
+ hub_characteristics = buf[3];
+
+ USB_DBG("Hub has %d port", nb_port);
+
+ for (uint8_t j = 1; j <= nb_port; j++) {
+ setPortFeature(PORT_POWER_FEATURE, j);
+ }
+ wait_ms(buf[5]*2);
+
+ host->interruptRead(dev, int_in, buf, 1, false);
+ dev_connected = true;
+ return true;
+ }
+
+ return false;
+}
+
+void USBHostHub::disconnect() {
+ init();
+}
+
+/*virtual*/ void USBHostHub::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostHub::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((hub_intf == -1) &&
+ (intf_class == HUB_CLASS) &&
+ (intf_subclass == 0) &&
+ (intf_protocol == 0)) {
+ hub_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostHub::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == hub_intf) {
+ if ((type == INTERRUPT_ENDPOINT) && (dir == IN)) {
+ hub_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+void USBHostHub::deviceConnected(USBDeviceConnected * dev) {
+ device_children[dev->getPort() - 1] = dev;
+}
+
+void USBHostHub::deviceDisconnected(USBDeviceConnected * dev) {
+ device_children[dev->getPort() - 1] = NULL;
+}
+
+void USBHostHub::hubDisconnected() {
+ for (uint8_t i = 0; i < MAX_HUB_PORT; i++) {
+ if (device_children[i] != NULL) {
+ host->freeDevice(device_children[i]);
+ }
+ }
+}
+
+void USBHostHub::rxHandler() {
+ uint32_t status;
+ if (int_in) {
+ if (int_in->getState() == USB_TYPE_IDLE) {
+ for (int port = 1; port <= nb_port; port++) {
+ status = getPortStatus(port);
+ USB_DBG("[hub handler hub: %d] status port %d [hub: %p]: 0x%X", dev->getHub(), port, dev, status);
+
+ // if connection status has changed
+ if (status & C_PORT_CONNECTION) {
+ if (status & PORT_CONNECTION) {
+ USB_DBG("[hub handler hub: %d - port: %d] new device connected", dev->getHub(), port);
+ host->deviceConnected(dev->getHub() + 1, port, status & PORT_LOW_SPEED, this);
+ } else {
+ USB_DBG("[hub handler hub: %d - port: %d] device disconnected", dev->getHub(), port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ }
+
+ clearPortFeature(C_PORT_CONNECTION_FEATURE, port);
+ }
+
+ if (status & C_PORT_RESET) {
+ clearPortFeature(C_PORT_RESET_FEATURE, port);
+ }
+
+ if (status & C_PORT_ENABLE) {
+ clearPortFeature(C_PORT_ENABLE_FEATURE, port);
+ }
+
+ if ((status & PORT_OVER_CURRENT)) {
+ USB_ERR("OVER CURRENT DETECTED\r\n");
+ clearPortFeature(PORT_OVER_CURRENT, port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ }
+ }
+ }
+ host->interruptRead(dev, int_in, buf, 1, false);
+ }
+}
+
+void USBHostHub::portReset(uint8_t port) {
+ // reset port
+ uint32_t status;
+ USB_DBG("reset port %d on hub: %p [this: %p]", port, dev, this)
+ setPortFeature(PORT_RESET_FEATURE, port);
+#if defined(TARGET_RZ_A1H)
+ Thread::wait(50); // Reset release waiting for Hi-Speed check.
+#endif
+ while(1) {
+ status = getPortStatus(port);
+ if (status & (PORT_ENABLE | PORT_RESET))
+ break;
+ if (status & PORT_OVER_CURRENT) {
+ USB_ERR("OVER CURRENT DETECTED\r\n");
+ clearPortFeature(PORT_OVER_CURRENT, port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ break;
+ }
+ Thread::wait(10);
+ }
+}
+
+void USBHostHub::setPortFeature(uint32_t feature, uint8_t port) {
+ host->controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ SET_FEATURE,
+ feature,
+ port,
+ NULL,
+ 0);
+}
+
+void USBHostHub::clearPortFeature(uint32_t feature, uint8_t port) {
+ host->controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ CLEAR_FEATURE,
+ feature,
+ port,
+ NULL,
+ 0);
+}
+
+uint32_t USBHostHub::getPortStatus(uint8_t port) {
+ uint32_t st;
+ host->controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ GET_STATUS,
+ 0,
+ port,
+ (uint8_t *)&st,
+ 4);
+ return st;
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h
new file mode 100644
index 000000000..e199c369e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h
@@ -0,0 +1,125 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTHUB_H
+#define USBHOSTHUB_H
+
+#include "USBHostConf.h"
+
+#if MAX_HUB_NB
+
+#include "USBHostTypes.h"
+#include "IUSBEnumerator.h"
+
+class USBHost;
+class USBDeviceConnected;
+class USBEndpoint;
+
+/**
+ * A class to use a USB Hub
+ */
+class USBHostHub : public IUSBEnumerator {
+public:
+ /**
+ * Constructor
+ */
+ USBHostHub();
+
+ /**
+ * Check if a USB Hub is connected
+ *
+ * @return true if a serial device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect device
+ *
+ * @param dev device to connect
+ * @return true if connection was successful
+ */
+ bool connect(USBDeviceConnected * dev);
+
+ /**
+ * Automatically called by USBHost when a device
+ * has been enumerated by usb_thread
+ *
+ * @param dev device connected
+ */
+ void deviceConnected(USBDeviceConnected * dev);
+
+ /**
+ * Automatically called by USBHost when a device
+ * has been disconnected from this hub
+ *
+ * @param dev device disconnected
+ */
+ void deviceDisconnected(USBDeviceConnected * dev);
+
+ /**
+ * Rest a specific port
+ *
+ * @param port port number
+ */
+ void portReset(uint8_t port);
+
+ /*
+ * Called by USBHost to set the instance of USBHost
+ *
+ * @param host host instance
+ */
+ void setHost(USBHost * host);
+
+ /**
+ * Called by USBhost when a hub has been disconnected
+ */
+ void hubDisconnected();
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+ USBEndpoint * int_in;
+ uint8_t nb_port;
+ uint8_t hub_characteristics;
+
+ void rxHandler();
+
+ uint8_t buf[sizeof(HubDescriptor)];
+
+ int hub_intf;
+ bool hub_device_found;
+
+ void setPortFeature(uint32_t feature, uint8_t port);
+ void clearPortFeature(uint32_t feature, uint8_t port);
+ uint32_t getPortStatus(uint8_t port);
+
+ USBDeviceConnected * device_children[MAX_HUB_PORT];
+
+ void init();
+ void disconnect();
+
+};
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp
new file mode 100644
index 000000000..3e98f88b5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp
@@ -0,0 +1,362 @@
+/* Copyright (c) 2014 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "USBHostMIDI.h"
+
+#if USBHOST_MIDI
+
+#include "dbg.h"
+
+#define SET_LINE_CODING 0x20
+
+USBHostMIDI::USBHostMIDI() {
+ host = USBHost::getHostInst();
+ size_bulk_in = 0;
+ size_bulk_out = 0;
+ init();
+}
+
+void USBHostMIDI::init() {
+ dev = NULL;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ dev_connected = false;
+ midi_intf = -1;
+ midi_device_found = false;
+ sysExBufferPos = 0;
+}
+
+bool USBHostMIDI::connected() {
+ return dev_connected;
+}
+
+bool USBHostMIDI::connect() {
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ USB_DBG("Trying to connect MIDI device\r\n");
+
+ if (host->enumerate(dev, this)) {
+ break;
+ }
+
+ if (midi_device_found) {
+ bulk_in = dev->getEndpoint(midi_intf, BULK_ENDPOINT, IN);
+ bulk_out = dev->getEndpoint(midi_intf, BULK_ENDPOINT, OUT);
+
+ if (!bulk_in || !bulk_out) {
+ break;
+ }
+
+ USB_INFO("New MIDI device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, midi_intf);
+ dev->setName("MIDI", midi_intf);
+ host->registerDriver(dev, midi_intf, this, &USBHostMIDI::init);
+
+ size_bulk_in = bulk_in->getSize();
+ size_bulk_out = bulk_out->getSize();
+
+ bulk_in->attach(this, &USBHostMIDI::rxHandler);
+
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+
+ init();
+ return false;
+}
+
+void USBHostMIDI::rxHandler() {
+ uint8_t *midi;
+ if (bulk_in) {
+ int length = bulk_in->getLengthTransferred();
+ if (bulk_in->getState() == USB_TYPE_IDLE || bulk_in->getState() == USB_TYPE_FREE) {
+ // MIDI event handling
+ for (int i = 0; i < length; i += 4) {
+ if (i + 4 > length) {
+ // length shortage, ignored.
+ break;
+ }
+
+ // read each four bytes
+ midi = &buf[i];
+ // process MIDI message
+ // switch by code index number
+ switch (midi[0] & 0xf) {
+ case 0: // miscellaneous function codes
+ miscellaneousFunctionCode(midi[1], midi[2], midi[3]);
+ break;
+ case 1: // cable events
+ cableEvent(midi[1], midi[2], midi[3]);
+ break;
+ case 2: // two bytes system common messages
+ systemCommonTwoBytes(midi[1], midi[2]);
+ break;
+ case 3: // three bytes system common messages
+ systemCommonThreeBytes(midi[1], midi[2], midi[3]);
+ break;
+ case 4: // SysEx starts or continues
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[3];
+ // SysEx continues. don't send
+ break;
+ case 5: // SysEx ends with single byte
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 6: // SysEx ends with two bytes
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 7: // SysEx ends with three bytes
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[3];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 8:
+ noteOff(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 9:
+ if (midi[3]) {
+ noteOn(midi[1] & 0xf, midi[2], midi[3]);
+ } else {
+ noteOff(midi[1] & 0xf, midi[2], midi[3]);
+ }
+ break;
+ case 10:
+ polyKeyPress(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 11:
+ controlChange(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 12:
+ programChange(midi[1] & 0xf, midi[2]);
+ break;
+ case 13:
+ channelPressure(midi[1] & 0xf, midi[2]);
+ break;
+ case 14:
+ pitchBend(midi[1] & 0xf, midi[2] | (midi[3] << 7));
+ break;
+ case 15:
+ singleByte(midi[1]);
+ break;
+ }
+ }
+
+ // read another message
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ }
+ }
+}
+
+bool USBHostMIDI::sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3) {
+ if (bulk_out) {
+ uint8_t midi[4];
+
+ midi[0] = data0;
+ midi[1] = data1;
+ midi[2] = data2;
+ midi[3] = data3;
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, 4) == USB_TYPE_OK) {
+ return true;
+ }
+ }
+ return false;
+}
+
+bool USBHostMIDI::sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(0, data1, data2, data3);
+}
+
+bool USBHostMIDI::sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(1, data1, data2, data3);
+}
+
+bool USBHostMIDI::sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2) {
+ return sendMidiBuffer(2, data1, data2, 0);
+}
+
+bool USBHostMIDI::sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(3, data1, data2, 0);
+}
+
+bool USBHostMIDI::sendSystemExclusive(uint8_t *buffer, int length) {
+ uint8_t midi[64];
+ int midiLength;
+ int midiPos;
+ if (bulk_out) {
+ for (int i = 0; i < length; i += 48) {
+ if (i + 48 >= length) {
+ // contains last data
+ midiLength = (((length - i) + 2) / 3) * 4;
+ for (int pos = i; pos < length; pos += 3) {
+ midiPos = (pos + 2) / 3 * 4;
+ if (pos + 3 >= length) {
+ // last data
+ switch (pos % 3) {
+ case 0:
+ midi[midiPos ] = 7;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ break;
+ case 1:
+ midi[midiPos ] = 5;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = 0;
+ midi[midiPos + 3] = 0;
+ break;
+ case 2:
+ midi[midiPos ] = 6;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = 0;
+ break;
+ }
+ } else {
+ // has more data
+ midi[midiPos ] = 4;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ }
+ }
+ } else {
+ // has more data
+ midiLength = 64;
+ for (int pos = i; pos < length; pos += 3) {
+ midiPos = (pos + 2) / 3 * 4;
+ midi[midiPos ] = 4;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ }
+ }
+
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, midiLength) != USB_TYPE_OK) {
+ return false;
+ }
+ }
+ return true;
+ }
+ return false;
+}
+
+bool USBHostMIDI::sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity) {
+ return sendMidiBuffer(8, channel & 0xf | 0x80, note & 0x7f, velocity & 0x7f);
+}
+
+bool USBHostMIDI::sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity) {
+ return sendMidiBuffer(9, channel & 0xf | 0x90, note & 0x7f, velocity & 0x7f);
+}
+
+bool USBHostMIDI::sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure) {
+ return sendMidiBuffer(10, channel & 0xf | 0xa0, note & 0x7f, pressure & 0x7f);
+}
+
+bool USBHostMIDI::sendControlChange(uint8_t channel, uint8_t key, uint8_t value) {
+ return sendMidiBuffer(11, channel & 0xf | 0xb0, key & 0x7f, value & 0x7f);
+}
+
+bool USBHostMIDI::sendProgramChange(uint8_t channel, uint8_t program) {
+ return sendMidiBuffer(12, channel & 0xf | 0xc0, program & 0x7f, 0);
+}
+
+bool USBHostMIDI::sendChannelPressure(uint8_t channel, uint8_t pressure) {
+ return sendMidiBuffer(13, channel & 0xf | 0xd0, pressure & 0x7f, 0);
+}
+
+bool USBHostMIDI::sendPitchBend(uint8_t channel, uint16_t value) {
+ return sendMidiBuffer(14, channel & 0xf | 0xe0, value & 0x7f, (value >> 7) & 0x7f);
+}
+
+bool USBHostMIDI::sendSingleByte(uint8_t data) {
+ return sendMidiBuffer(15, data, 0, 0);
+}
+
+/*virtual*/ void USBHostMIDI::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for this driver
+}
+
+/*virtual*/ bool USBHostMIDI::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ // USB MIDI class/subclass
+ if ((midi_intf == -1) &&
+ (intf_class == AUDIO_CLASS) &&
+ (intf_subclass == 0x03)) {
+ midi_intf = intf_nb;
+ return true;
+ }
+
+ // vendor specific device
+ if ((midi_intf == -1) &&
+ (intf_class == 0xff) &&
+ (intf_subclass == 0x03)) {
+ midi_intf = intf_nb;
+ return true;
+ }
+
+ return false;
+}
+
+/*virtual*/ bool USBHostMIDI::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == midi_intf) {
+ if (type == BULK_ENDPOINT) {
+ midi_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h
new file mode 100644
index 000000000..e124e9b7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h
@@ -0,0 +1,353 @@
+/* Copyright (c) 2014 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef USBHOSTMIDI_H
+#define USBHOSTMIDI_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MIDI
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB MIDI device
+ */
+class USBHostMIDI : public IUSBEnumerator {
+public:
+ /**
+ * Constructor
+ */
+ USBHostMIDI();
+
+ /**
+ * Check if a USB MIDI device is connected
+ *
+ * @returns true if a midi device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect a midi device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Attach a callback called when miscellaneous function code is received
+ *
+ * @param ptr function pointer
+ * prototype: void onMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachMiscellaneousFunctionCode(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ miscellaneousFunctionCode = fn;
+ }
+
+ /**
+ * Attach a callback called when cable event is received
+ *
+ * @param ptr function pointer
+ * prototype: void onCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachCableEvent(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ cableEvent = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemCommonTwoBytes(uint8_t data1, uint8_t data2);
+ */
+ inline void attachSystemCommonTwoBytes(void (*fn)(uint8_t, uint8_t)) {
+ systemCommonTwoBytes = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemCommonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachSystemCommonThreeBytes(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ systemCommonThreeBytes = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemExclusive(uint8_t *data, uint16_t length, bool hasNextData);
+ */
+ inline void attachSystemExclusive(void (*fn)(uint8_t *, uint16_t, bool)) {
+ systemExclusive = fn;
+ }
+
+ /**
+ * Attach a callback called when note on is received
+ *
+ * @param ptr function pointer
+ * prototype: void onNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
+ */
+ inline void attachNoteOn(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ noteOn = fn;
+ }
+
+ /**
+ * Attach a callback called when note off is received
+ *
+ * @param ptr function pointer
+ * prototype: void onNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
+ */
+ inline void attachNoteOff(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ noteOff = fn;
+ }
+
+ /**
+ * Attach a callback called when poly keypress is received
+ *
+ * @param ptr function pointer
+ * prototype: void onPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
+ */
+ inline void attachPolyKeyPress(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ polyKeyPress = fn;
+ }
+
+ /**
+ * Attach a callback called when control change is received
+ *
+ * @param ptr function pointer
+ * prototype: void onControlChange(uint8_t channel, uint8_t key, uint8_t value);
+ */
+ inline void attachControlChange(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ controlChange = fn;
+ }
+
+ /**
+ * Attach a callback called when program change is received
+ *
+ * @param ptr function pointer
+ * prototype: void onProgramChange(uint8_t channel, uint8_t program);
+ */
+ inline void attachProgramChange(void (*fn)(uint8_t, uint8_t)) {
+ programChange = fn;
+ }
+
+ /**
+ * Attach a callback called when channel pressure is received
+ *
+ * @param ptr function pointer
+ * prototype: void onChannelPressure(uint8_t channel, uint8_t pressure);
+ */
+ inline void attachChannelPressure(void (*fn)(uint8_t, uint8_t)) {
+ channelPressure = fn;
+ }
+
+ /**
+ * Attach a callback called when pitch bend is received
+ *
+ * @param ptr function pointer
+ * prototype: void onPitchBend(uint8_t channel, uint16_t value);
+ */
+ inline void attachPitchBend(void (*fn)(uint8_t, uint16_t)) {
+ pitchBend = fn;
+ }
+
+ /**
+ * Attach a callback called when single byte is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSingleByte(uint8_t value);
+ */
+ inline void attachSingleByte(void (*fn)(uint8_t)) {
+ singleByte = fn;
+ }
+
+ /**
+ * Send a cable event with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a cable event with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a system common message with 2 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2);
+
+ /**
+ * Send a system common message with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a system exclusive event
+ *
+ * @param buffer, starts with 0xF0, and end with 0xf7
+ * @param length
+ * @return true if message sent successfully
+ */
+ bool sendSystemExclusive(uint8_t *buffer, int length);
+
+ /**
+ * Send a note off event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param velocity 0-127
+ * @return true if message sent successfully
+ */
+ bool sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
+
+ /**
+ * Send a note on event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param velocity 0-127 (0 means note off)
+ * @return true if message sent successfully
+ */
+ bool sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
+
+ /**
+ * Send a poly keypress event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param pressure 0-127
+ * @return true if message sent successfully
+ */
+ bool sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
+
+ /**
+ * Send a control change event
+ *
+ * @param channel 0-15
+ * @param key 0-127
+ * @param value 0-127
+ * @return true if message sent successfully
+ */
+ bool sendControlChange(uint8_t channel, uint8_t key, uint8_t value);
+
+ /**
+ * Send a program change event
+ *
+ * @param channel 0-15
+ * @param program 0-127
+ * @return true if message sent successfully
+ */
+ bool sendProgramChange(uint8_t channel, uint8_t program);
+
+ /**
+ * Send a channel pressure event
+ *
+ * @param channel 0-15
+ * @param pressure 0-127
+ * @return true if message sent successfully
+ */
+ bool sendChannelPressure(uint8_t channel, uint8_t pressure);
+
+ /**
+ * Send a control change event
+ *
+ * @param channel 0-15
+ * @param key 0(lower)-8191(center)-16383(higher)
+ * @return true if message sent successfully
+ */
+ bool sendPitchBend(uint8_t channel, uint16_t value);
+
+ /**
+ * Send a single byte event
+ *
+ * @param data 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSingleByte(uint8_t data);
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint32_t size_bulk_in;
+ uint32_t size_bulk_out;
+
+ bool dev_connected;
+
+ void init();
+
+ uint8_t buf[64];
+
+ void rxHandler();
+
+ uint16_t sysExBufferPos;
+ uint8_t sysExBuffer[64];
+
+ void (*miscellaneousFunctionCode)(uint8_t, uint8_t, uint8_t);
+ void (*cableEvent)(uint8_t, uint8_t, uint8_t);
+ void (*systemCommonTwoBytes)(uint8_t, uint8_t);
+ void (*systemCommonThreeBytes)(uint8_t, uint8_t, uint8_t);
+ void (*systemExclusive)(uint8_t *, uint16_t, bool);
+ void (*noteOff)(uint8_t, uint8_t, uint8_t);
+ void (*noteOn)(uint8_t, uint8_t, uint8_t);
+ void (*polyKeyPress)(uint8_t, uint8_t, uint8_t);
+ void (*controlChange)(uint8_t, uint8_t, uint8_t);
+ void (*programChange)(uint8_t, uint8_t);
+ void (*channelPressure)(uint8_t, uint8_t);
+ void (*pitchBend)(uint8_t, uint16_t);
+ void (*singleByte)(uint8_t);
+
+ bool sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3);
+
+ int midi_intf;
+ bool midi_device_found;
+
+};
+
+#endif /* USBHOST_MIDI */
+
+#endif /* USBHOSTMIDI_H */
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp
new file mode 100644
index 000000000..1fcb54abf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp
@@ -0,0 +1,366 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostMSD.h"
+
+#if USBHOST_MSD
+
+#include "dbg.h"
+
+#define CBW_SIGNATURE 0x43425355
+#define CSW_SIGNATURE 0x53425355
+
+#define DEVICE_TO_HOST 0x80
+#define HOST_TO_DEVICE 0x00
+
+#define GET_MAX_LUN (0xFE)
+#define BO_MASS_STORAGE_RESET (0xFF)
+
+USBHostMSD::USBHostMSD(const char * rootdir) : FATFileSystem(rootdir)
+{
+ host = USBHost::getHostInst();
+ init();
+}
+
+void USBHostMSD::init() {
+ dev_connected = false;
+ dev = NULL;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ dev_connected = false;
+ blockSize = 0;
+ blockCount = 0;
+ msd_intf = -1;
+ msd_device_found = false;
+ disk_init = false;
+ dev_connected = false;
+ nb_ep = 0;
+}
+
+
+bool USBHostMSD::connected()
+{
+ return dev_connected;
+}
+
+bool USBHostMSD::connect()
+{
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ USB_DBG("Trying to connect MSD device\r\n");
+
+ if(host->enumerate(dev, this))
+ break;
+
+ if (msd_device_found) {
+ bulk_in = dev->getEndpoint(msd_intf, BULK_ENDPOINT, IN);
+ bulk_out = dev->getEndpoint(msd_intf, BULK_ENDPOINT, OUT);
+
+ if (!bulk_in || !bulk_out)
+ continue;
+
+ USB_INFO("New MSD device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, msd_intf);
+ dev->setName("MSD", msd_intf);
+ host->registerDriver(dev, msd_intf, this, &USBHostMSD::init);
+
+ dev_connected = true;
+ return true;
+ }
+ } //if()
+ } //for()
+ init();
+ return false;
+}
+
+/*virtual*/ void USBHostMSD::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostMSD::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((msd_intf == -1) &&
+ (intf_class == MSD_CLASS) &&
+ (intf_subclass == 0x06) &&
+ (intf_protocol == 0x50)) {
+ msd_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMSD::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == msd_intf) {
+ if (type == BULK_ENDPOINT) {
+ nb_ep++;
+ if (nb_ep == 2)
+ msd_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+
+int USBHostMSD::testUnitReady() {
+ USB_DBG("Test unit ready");
+ return SCSITransfer(NULL, 6, DEVICE_TO_HOST, 0, 0);
+}
+
+
+int USBHostMSD::readCapacity() {
+ USB_DBG("Read capacity");
+ uint8_t cmd[10] = {0x25,0,0,0,0,0,0,0,0,0};
+ uint8_t result[8];
+ int status = SCSITransfer(cmd, 10, DEVICE_TO_HOST, result, 8);
+ if (status == 0) {
+ blockCount = (result[0] << 24) | (result[1] << 16) | (result[2] << 8) | result[3];
+ blockSize = (result[4] << 24) | (result[5] << 16) | (result[6] << 8) | result[7];
+ USB_INFO("MSD [dev: %p] - blockCount: %lld, blockSize: %d, Capacity: %lld\r\n", dev, blockCount, blockSize, blockCount*blockSize);
+ }
+ return status;
+}
+
+
+int USBHostMSD::SCSIRequestSense() {
+ USB_DBG("Request sense");
+ uint8_t cmd[6] = {0x03,0,0,0,18,0};
+ uint8_t result[18];
+ int status = SCSITransfer(cmd, 6, DEVICE_TO_HOST, result, 18);
+ return status;
+}
+
+
+int USBHostMSD::inquiry(uint8_t lun, uint8_t page_code) {
+ USB_DBG("Inquiry");
+ uint8_t evpd = (page_code == 0) ? 0 : 1;
+ uint8_t cmd[6] = {0x12, uint8_t((lun << 5) | evpd), page_code, 0, 36, 0};
+ uint8_t result[36];
+ int status = SCSITransfer(cmd, 6, DEVICE_TO_HOST, result, 36);
+ if (status == 0) {
+ char vid_pid[17];
+ memcpy(vid_pid, &result[8], 8);
+ vid_pid[8] = 0;
+ USB_INFO("MSD [dev: %p] - Vendor ID: %s", dev, vid_pid);
+
+ memcpy(vid_pid, &result[16], 16);
+ vid_pid[16] = 0;
+ USB_INFO("MSD [dev: %p] - Product ID: %s", dev, vid_pid);
+
+ memcpy(vid_pid, &result[32], 4);
+ vid_pid[4] = 0;
+ USB_INFO("MSD [dev: %p] - Product rev: %s", dev, vid_pid);
+ }
+ return status;
+}
+
+int USBHostMSD::checkResult(uint8_t res, USBEndpoint * ep) {
+ // if ep stalled: send clear feature
+ if (res == USB_TYPE_STALL_ERROR) {
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, ep->getAddress(), NULL, 0);
+ // set state to IDLE if clear feature successful
+ if (res == USB_TYPE_OK) {
+ ep->setState(USB_TYPE_IDLE);
+ }
+ }
+
+ if (res != USB_TYPE_OK)
+ return -1;
+
+ return 0;
+}
+
+
+int USBHostMSD::SCSITransfer(uint8_t * cmd, uint8_t cmd_len, int flags, uint8_t * data, uint32_t transfer_len) {
+
+ int res = 0;
+
+ cbw.Signature = CBW_SIGNATURE;
+ cbw.Tag = 0;
+ cbw.DataLength = transfer_len;
+ cbw.Flags = flags;
+ cbw.LUN = 0;
+ cbw.CBLength = cmd_len;
+ memset(cbw.CB,0,sizeof(cbw.CB));
+ if (cmd) {
+ memcpy(cbw.CB,cmd,cmd_len);
+ }
+
+ // send the cbw
+ USB_DBG("Send CBW");
+ res = host->bulkWrite(dev, bulk_out,(uint8_t *)&cbw, 31);
+ if (checkResult(res, bulk_out))
+ return -1;
+
+ // data stage if needed
+ if (data) {
+ USB_DBG("data stage");
+ if (flags == HOST_TO_DEVICE) {
+
+ res = host->bulkWrite(dev, bulk_out, data, transfer_len);
+ if (checkResult(res, bulk_out))
+ return -1;
+
+ } else if (flags == DEVICE_TO_HOST) {
+
+ res = host->bulkRead(dev, bulk_in, data, transfer_len);
+ if (checkResult(res, bulk_in))
+ return -1;
+ }
+ }
+
+ // status stage
+ csw.Signature = 0;
+ USB_DBG("Read CSW");
+ res = host->bulkRead(dev, bulk_in,(uint8_t *)&csw, 13);
+ if (checkResult(res, bulk_in))
+ return -1;
+
+ if (csw.Signature != CSW_SIGNATURE) {
+ return -1;
+ }
+
+ USB_DBG("recv csw: status: %d", csw.Status);
+
+ // ModeSense?
+ if ((csw.Status == 1) && (cmd[0] != 0x03)) {
+ USB_DBG("request mode sense");
+ return SCSIRequestSense();
+ }
+
+ // perform reset recovery
+ if ((csw.Status == 2) && (cmd[0] != 0x03)) {
+
+ // send Bulk-Only Mass Storage Reset request
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_INTERFACE | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS,
+ BO_MASS_STORAGE_RESET,
+ 0, msd_intf, NULL, 0);
+
+ // unstall both endpoints
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, bulk_in->getAddress(), NULL, 0);
+
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, bulk_out->getAddress(), NULL, 0);
+
+ }
+
+ return csw.Status;
+}
+
+
+int USBHostMSD::dataTransfer(uint8_t * buf, uint32_t block, uint8_t nbBlock, int direction) {
+ uint8_t cmd[10];
+ memset(cmd,0,10);
+ cmd[0] = (direction == DEVICE_TO_HOST) ? 0x28 : 0x2A;
+
+ cmd[2] = (block >> 24) & 0xff;
+ cmd[3] = (block >> 16) & 0xff;
+ cmd[4] = (block >> 8) & 0xff;
+ cmd[5] = block & 0xff;
+
+ cmd[7] = (nbBlock >> 8) & 0xff;
+ cmd[8] = nbBlock & 0xff;
+
+ return SCSITransfer(cmd, 10, direction, buf, blockSize*nbBlock);
+}
+
+int USBHostMSD::getMaxLun() {
+ uint8_t buf[1], res;
+ res = host->controlRead( dev, USB_RECIPIENT_INTERFACE | USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS,
+ 0xfe, 0, msd_intf, buf, 1);
+ USB_DBG("max lun: %d", buf[0]);
+ return res;
+}
+
+int USBHostMSD::disk_initialize() {
+ USB_DBG("FILESYSTEM: init");
+ uint16_t i, timeout = 10;
+
+ getMaxLun();
+
+ for (i = 0; i < timeout; i++) {
+ Thread::wait(100);
+ if (!testUnitReady())
+ break;
+ }
+
+ if (i == timeout) {
+ disk_init = false;
+ return -1;
+ }
+
+ inquiry(0, 0);
+ disk_init = 1;
+ return readCapacity();
+}
+
+int USBHostMSD::disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ USB_DBG("FILESYSTEM: write block: %lld, count: %d", block_number, count);
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return -1;
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ if (dataTransfer((uint8_t*)buffer, b, 1, HOST_TO_DEVICE))
+ return -1;
+ buffer += 512;
+ }
+ return 0;
+}
+
+int USBHostMSD::disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ USB_DBG("FILESYSTEM: read block: %lld, count: %d", block_number, count);
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return -1;
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ if (dataTransfer((uint8_t*)buffer, b, 1, DEVICE_TO_HOST))
+ return -1;
+ buffer += 512;
+ }
+ return 0;
+}
+
+uint64_t USBHostMSD::disk_sectors() {
+ USB_DBG("FILESYSTEM: sectors");
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return 0;
+ return blockCount;
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h
new file mode 100644
index 000000000..10c602585
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h
@@ -0,0 +1,119 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTMSD_H
+#define USBHOSTMSD_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MSD
+
+#include "USBHost.h"
+#include "FATFileSystem.h"
+
+/**
+ * A class to communicate a USB flash disk
+ */
+class USBHostMSD : public IUSBEnumerator, public FATFileSystem {
+public:
+ /**
+ * Constructor
+ *
+ * @param rootdir mount name
+ */
+ USBHostMSD(const char * rootdir);
+
+ /**
+ * Check if a MSD device is connected
+ *
+ * @return true if a MSD device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect to a MSD device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+ // From FATFileSystem
+ virtual int disk_initialize();
+ virtual int disk_status() {return 0;};
+ virtual int disk_read(uint8_t* buffer, uint64_t sector, uint8_t count);
+ virtual int disk_write(const uint8_t* buffer, uint64_t sector, uint8_t count);
+ virtual int disk_sync() {return 0;};
+ virtual uint64_t disk_sectors();
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint8_t nb_ep;
+
+ // Bulk-only CBW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataLength;
+ uint8_t Flags;
+ uint8_t LUN;
+ uint8_t CBLength;
+ uint8_t CB[16];
+ } PACKED CBW;
+
+ // Bulk-only CSW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataResidue;
+ uint8_t Status;
+ } PACKED CSW;
+
+ CBW cbw;
+ CSW csw;
+
+ int SCSITransfer(uint8_t * cmd, uint8_t cmd_len, int flags, uint8_t * data, uint32_t transfer_len);
+ int testUnitReady();
+ int readCapacity();
+ int inquiry(uint8_t lun, uint8_t page_code);
+ int SCSIRequestSense();
+ int dataTransfer(uint8_t * buf, uint32_t block, uint8_t nbBlock, int direction);
+ int checkResult(uint8_t res, USBEndpoint * ep);
+ int getMaxLun();
+
+ int blockSize;
+ uint64_t blockCount;
+
+ int msd_intf;
+ bool msd_device_found;
+ bool disk_init;
+
+ void init();
+
+};
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h
new file mode 100644
index 000000000..ff79affad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h
@@ -0,0 +1,89 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MTXCIRCBUFFER_H
+#define MTXCIRCBUFFER_H
+
+#include "stdint.h"
+#include "rtos.h"
+
+//Mutex protected circular buffer
+template<typename T, int size>
+class MtxCircBuffer {
+public:
+
+ MtxCircBuffer() {
+ write = 0;
+ read = 0;
+ }
+
+ bool isFull() {
+ mtx.lock();
+ bool r = (((write + 1) % size) == read);
+ mtx.unlock();
+ return r;
+ }
+
+ bool isEmpty() {
+ mtx.lock();
+ bool r = (read == write);
+ mtx.unlock();
+ return r;
+ }
+
+ void flush() {
+ write = 0;
+ read = 0;
+ }
+
+ void queue(T k) {
+ mtx.lock();
+ while (((write + 1) % size) == read) {
+ mtx.unlock();
+ Thread::wait(10);
+ mtx.lock();
+ }
+ buf[write++] = k;
+ write %= size;
+ mtx.unlock();
+ }
+
+ uint16_t available() {
+ mtx.lock();
+ uint16_t a = (write >= read) ? (write - read) : (size - read + write);
+ mtx.unlock();
+ return a;
+ }
+
+ bool dequeue(T * c) {
+ mtx.lock();
+ bool empty = (read == write);
+ if (!empty) {
+ *c = buf[read++];
+ read %= size;
+ }
+ mtx.unlock();
+ return (!empty);
+ }
+
+private:
+ volatile uint16_t write;
+ volatile uint16_t read;
+ volatile T buf[size];
+ Mutex mtx;
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp
new file mode 100644
index 000000000..428026ff5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp
@@ -0,0 +1,345 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostSerial.h"
+
+#if USBHOST_SERIAL
+
+#include "dbg.h"
+
+#define CHECK_INTERFACE(cls,subcls,proto) \
+ (((cls == 0xFF) && (subcls == 0xFF) && (proto == 0xFF)) /* QUALCOM CDC */ || \
+ ((cls == SERIAL_CLASS) && (subcls == 0x00) && (proto == 0x00)) /* STANDARD CDC */ )
+
+#if (USBHOST_SERIAL <= 1)
+
+USBHostSerial::USBHostSerial()
+{
+ host = USBHost::getHostInst();
+ ports_found = 0;
+ dev_connected = false;
+}
+
+bool USBHostSerial::connected()
+{
+ return dev_connected;
+}
+
+void USBHostSerial::disconnect(void)
+{
+ ports_found = 0;
+ dev = NULL;
+}
+
+bool USBHostSerial::connect() {
+
+ if (dev)
+ {
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (dev == d)
+ return true;
+ }
+ disconnect();
+ }
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (d != NULL) {
+
+ USB_DBG("Trying to connect serial device \r\n");
+ if(host->enumerate(d, this))
+ break;
+
+ USBEndpoint* bulk_in = d->getEndpoint(port_intf, BULK_ENDPOINT, IN);
+ USBEndpoint* bulk_out = d->getEndpoint(port_intf, BULK_ENDPOINT, OUT);
+ if (bulk_in && bulk_out)
+ {
+ USBHostSerialPort::connect(host,d,port_intf,bulk_in, bulk_out);
+ dev = d;
+ dev_connected = true;
+ }
+ }
+ }
+ return dev != NULL;
+}
+
+/*virtual*/ void USBHostSerial::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if (!ports_found &&
+ CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
+ port_intf = intf_nb;
+ ports_found = true;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (ports_found && (intf_nb == port_intf)) {
+ if (type == BULK_ENDPOINT)
+ return true;
+ }
+ return false;
+}
+
+#else // (USBHOST_SERIAL > 1)
+
+//------------------------------------------------------------------------------
+
+USBHostMultiSerial::USBHostMultiSerial()
+{
+ host = USBHost::getHostInst();
+ dev = NULL;
+ memset(ports, NULL, sizeof(ports));
+ ports_found = 0;
+ dev_connected = false;
+}
+
+USBHostMultiSerial::~USBHostMultiSerial()
+{
+ disconnect();
+}
+
+bool USBHostMultiSerial::connected()
+{
+ return dev_connected;
+}
+
+void USBHostMultiSerial::disconnect(void)
+{
+ for (int port = 0; port < USBHOST_SERIAL; port ++)
+ {
+ if (ports[port])
+ {
+ delete ports[port];
+ ports[port] = NULL;
+ }
+ }
+ ports_found = 0;
+ dev = NULL;
+}
+
+bool USBHostMultiSerial::connect() {
+
+ if (dev)
+ {
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (dev == d)
+ return true;
+ }
+ disconnect();
+ }
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (d != NULL) {
+
+ USB_DBG("Trying to connect serial device \r\n");
+ if(host->enumerate(d, this))
+ break;
+
+ for (int port = 0; port < ports_found; port ++)
+ {
+ USBEndpoint* bulk_in = d->getEndpoint(port_intf[port], BULK_ENDPOINT, IN);
+ USBEndpoint* bulk_out = d->getEndpoint(port_intf[port], BULK_ENDPOINT, OUT);
+ if (bulk_in && bulk_out)
+ {
+ ports[port] = new USBHostSerialPort();
+ if (ports[port])
+ {
+ ports[port]->connect(host,d,port_intf[port],bulk_in, bulk_out);
+ dev = d;
+ dev_connected = true;
+ }
+ }
+ }
+ }
+ }
+ return dev != NULL;
+}
+
+/*virtual*/ void USBHostMultiSerial::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostMultiSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((ports_found < USBHOST_SERIAL) &&
+ CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
+ port_intf[ports_found++] = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMultiSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if ((ports_found > 0) && (intf_nb == port_intf[ports_found-1])) {
+ if (type == BULK_ENDPOINT)
+ return true;
+ }
+ return false;
+}
+
+#endif
+
+//------------------------------------------------------------------------------
+
+#define SET_LINE_CODING 0x20
+
+USBHostSerialPort::USBHostSerialPort(): circ_buf()
+{
+ init();
+}
+
+void USBHostSerialPort::init(void)
+{
+ host = NULL;
+ dev = NULL;
+ serial_intf = NULL;
+ size_bulk_in = 0;
+ size_bulk_out = 0;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ line_coding.baudrate = 9600;
+ line_coding.data_bits = 8;
+ line_coding.parity = None;
+ line_coding.stop_bits = 1;
+ circ_buf.flush();
+}
+
+void USBHostSerialPort::connect(USBHost* _host, USBDeviceConnected * _dev,
+ uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out)
+{
+ host = _host;
+ dev = _dev;
+ serial_intf = _serial_intf;
+ bulk_in = _bulk_in;
+ bulk_out = _bulk_out;
+
+ USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf);
+ dev->setName("Serial", serial_intf);
+ host->registerDriver(dev, serial_intf, this, &USBHostSerialPort::init);
+ baud(9600);
+ size_bulk_in = bulk_in->getSize();
+ size_bulk_out = bulk_out->getSize();
+ bulk_in->attach(this, &USBHostSerialPort::rxHandler);
+ bulk_out->attach(this, &USBHostSerialPort::txHandler);
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+}
+
+void USBHostSerialPort::rxHandler() {
+ if (bulk_in) {
+ int len = bulk_in->getLengthTransferred();
+ if (bulk_in->getState() == USB_TYPE_IDLE) {
+ for (int i = 0; i < len; i++) {
+ circ_buf.queue(buf[i]);
+ }
+ rx.call();
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ }
+ }
+}
+
+void USBHostSerialPort::txHandler() {
+ if (bulk_out) {
+ if (bulk_out->getState() == USB_TYPE_IDLE) {
+ tx.call();
+ }
+ }
+}
+
+int USBHostSerialPort::_putc(int c) {
+ if (bulk_out) {
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)&c, 1) == USB_TYPE_OK) {
+ return 1;
+ }
+ }
+ return -1;
+}
+
+void USBHostSerialPort::baud(int baudrate) {
+ line_coding.baudrate = baudrate;
+ format(line_coding.data_bits, (Parity)line_coding.parity, line_coding.stop_bits);
+}
+
+void USBHostSerialPort::format(int bits, Parity parity, int stop_bits) {
+ line_coding.data_bits = bits;
+ line_coding.parity = parity;
+ line_coding.stop_bits = (stop_bits == 1) ? 0 : 2;
+
+ // set line coding
+ host->controlWrite( dev,
+ USB_RECIPIENT_INTERFACE | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS,
+ SET_LINE_CODING,
+ 0, serial_intf, (uint8_t *)&line_coding, 7);
+}
+
+int USBHostSerialPort::_getc() {
+ uint8_t c = 0;
+ if (bulk_in == NULL) {
+ init();
+ return -1;
+ }
+ while (circ_buf.isEmpty());
+ circ_buf.dequeue(&c);
+ return c;
+}
+
+int USBHostSerialPort::writeBuf(const char* b, int s)
+{
+ int c = 0;
+ if (bulk_out)
+ {
+ while (c < s)
+ {
+ int i = (s < size_bulk_out) ? s : size_bulk_out;
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)(b+c), i) == USB_TYPE_OK)
+ c += i;
+ }
+ }
+ return s;
+}
+
+int USBHostSerialPort::readBuf(char* b, int s)
+{
+ int i = 0;
+ if (bulk_in)
+ {
+ for (i = 0; i < s; )
+ b[i++] = getc();
+ }
+ return i;
+}
+
+uint8_t USBHostSerialPort::available() {
+ return circ_buf.available();
+}
+
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h
new file mode 100644
index 000000000..94fc8ad7c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h
@@ -0,0 +1,231 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTSERIAL_H
+#define USBHOSTSERIAL_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_SERIAL
+
+#include "USBHost.h"
+#include "Stream.h"
+#include "MtxCircBuffer.h"
+
+/**
+ * A class to communicate a USB virtual serial port
+ */
+class USBHostSerialPort : public Stream {
+public:
+ /**
+ * Constructor
+ */
+ USBHostSerialPort();
+
+ enum IrqType {
+ RxIrq,
+ TxIrq
+ };
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Mark,
+ Space
+ };
+
+ void connect(USBHost* _host, USBDeviceConnected * _dev,
+ uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out);
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ uint8_t available();
+
+ /**
+ * Attach a member function to call when a packet is received.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param irq irq type
+ */
+ template<typename T>
+ inline void attach(T* tptr, void (T::*mptr)(void), IrqType irq = RxIrq) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ if (irq == RxIrq) {
+ rx.attach(tptr, mptr);
+ } else {
+ tx.attach(tptr, mptr);
+ }
+ }
+ }
+
+ /**
+ * Attach a callback called when a packet is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*fn)(void), IrqType irq = RxIrq) {
+ if (fn != NULL) {
+ if (irq == RxIrq) {
+ rx.attach(fn);
+ } else {
+ tx.attach(fn);
+ }
+ }
+ }
+
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate = 9600);
+
+ /** Set the transmission format used by the Serial port
+ *
+ * @param bits The number of bits in a word (default = 8)
+ * @param parity The parity used (USBHostSerialPort::None, USBHostSerialPort::Odd, USBHostSerialPort::Even, USBHostSerialPort::Mark, USBHostSerialPort::Space; default = USBHostSerialPort::None)
+ * @param stop The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits = 8, Parity parity = USBHostSerialPort::None, int stop_bits = 1);
+ virtual int writeBuf(const char* b, int s);
+ virtual int readBuf(char* b, int s);
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint32_t size_bulk_in;
+ uint32_t size_bulk_out;
+
+ void init();
+
+ MtxCircBuffer<uint8_t, 128> circ_buf;
+
+ uint8_t buf[64];
+
+ typedef struct {
+ uint32_t baudrate;
+ uint8_t stop_bits;
+ uint8_t parity;
+ uint8_t data_bits;
+ } PACKED LINE_CODING;
+
+ LINE_CODING line_coding;
+
+ void rxHandler();
+ void txHandler();
+ FunctionPointer rx;
+ FunctionPointer tx;
+
+ uint8_t serial_intf;
+};
+
+#if (USBHOST_SERIAL <= 1)
+
+class USBHostSerial : public IUSBEnumerator, public USBHostSerialPort
+{
+public:
+ USBHostSerial();
+
+ /**
+ * Try to connect a serial device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ void disconnect();
+
+ /**
+ * Check if a any serial port is connected
+ *
+ * @returns true if a serial device is connected
+ */
+ bool connected();
+
+protected:
+ USBHost* host;
+ USBDeviceConnected* dev;
+ uint8_t port_intf;
+ int ports_found;
+
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ bool dev_connected;
+};
+
+#else // (USBHOST_SERIAL > 1)
+
+class USBHostMultiSerial : public IUSBEnumerator {
+public:
+ USBHostMultiSerial();
+ virtual ~USBHostMultiSerial();
+
+ USBHostSerialPort* getPort(int port)
+ {
+ return port < USBHOST_SERIAL ? ports[port] : NULL;
+ }
+
+ /**
+ * Try to connect a serial device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ void disconnect();
+
+ /**
+ * Check if a any serial port is connected
+ *
+ * @returns true if a serial device is connected
+ */
+ bool connected();
+
+protected:
+ USBHost* host;
+ USBDeviceConnected* dev;
+ USBHostSerialPort* ports[USBHOST_SERIAL];
+ uint8_t port_intf[USBHOST_SERIAL];
+ int ports_found;
+
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ bool dev_connected;
+};
+#endif // (USBHOST_SERIAL <= 1)
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/doc/mbed.dia b/tool/mbed/mbed-sdk/libraries/doc/mbed.dia
new file mode 100644
index 000000000..af850e842
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/mbed.dia
Binary files differ
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt b/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt
new file mode 100644
index 000000000..270c64c06
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt
@@ -0,0 +1,35 @@
+lwip/api/tcpip.c: tcpip_init -> tcpip_thread
+
+lwip/core/netif.c: netif_add
+lwip/arch/lpc17_emac.c: lpc_enetif_init -> packet_rx, packet_tx
+
+=== tcpip_thread ===
+ while (true):
+ sys_timeouts_mbox_fetch(&mbox, (void **)&msg)
+ ...
+
+Feeding the tcpip_thread mbox:
+ tcpip_input
+ tcpip_callback_with_block
+ tcpip_timeout
+ tcpip_untimeout
+ tcpip_apimsg
+ tcpip_netifapi
+
+
+=== packet_rx ===
+ while (true):
+ sys_arch_sem_wait(&lpc_enetif->RxSem, osWaitForever)
+ ...
+
+Feeding the RX semaphore:
+ ENET_IRQHandler
+
+
+=== packet_tx ===
+ while (true):
+ sys_arch_sem_wait(&lpc_enetif->TxCleanSem, osWaitForever)
+ ...
+
+Feeding the TX semaphore:
+ ENET_IRQHandler
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia b/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia
new file mode 100644
index 000000000..ff427c818
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia
Binary files differ
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/source.txt b/tool/mbed/mbed-sdk/libraries/doc/net/source.txt
new file mode 100644
index 000000000..9300ad3a6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/source.txt
@@ -0,0 +1,32 @@
+lwip-1.4.0:
+ http://download.savannah.gnu.org/releases/lwip/lwip-1.4.0.zip
+
+NXP lwIP port:
+ http://sw.lpcware.com/index.php?p=lwip_lpc.git&a=snapshot&h=7b84446afe97af955acad1d720696a0de73ab7cf&fmt=zip
+
+NXP Driver Library (needed for Ethernet defines)
+ http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
+
+# lwip library
+ lwip-1.4.0\src
+ api
+ core
+ include
+ netif
+
+# lwip-eth library
+ lwip_lpc\nxpcommon\
+ examples/lpc177x_8x/ea1788/ea1788_tcpecho_freertos/source/configs/flash/lpc_emac_config.h
+ lpc_phy_dp83848.c
+ lpc_phy.h
+ arch\lpc177x_8x\lpc17_emac.c
+ arch\lpc177x_8x\lpc17_emac.h
+ lpc17xx.cmsis.driver.library\Drivers\include
+ lpc17xx_emac.h
+
+# lwip-sys library
+ lwip_lpc\nxpcommon\arch
+ cc.h
+ perf.h
+ touch sys_arch.c
+ touch sys_arch.h
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt b/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt
new file mode 100644
index 000000000..38377b665
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt
@@ -0,0 +1,216 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip. The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more.
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+ Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+ Creates and returns a new semaphore. The "count" argument specifies
+ the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+ Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+ Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+ Blocks the thread while waiting for the semaphore to be
+ signaled. If the "timeout" argument is non-zero, the thread should
+ only be blocked for the specified time (measured in
+ milliseconds). If the "timeout" argument is zero, the thread should be
+ blocked until the semaphore is signalled.
+
+ If the timeout argument is non-zero, the return value is the number of
+ milliseconds spent waiting for the semaphore to be signaled. If the
+ semaphore wasn't signaled within the specified time, the return value is
+ SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ (i.e., it was already signaled), the function may return zero.
+
+ Notice that lwIP implements a function with a similar name,
+ sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(int size)
+
+ Creates an empty mailbox for maximum "size" elements. Elements stored
+ in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+ in your lwipopts.h, or ignore this parameter in your implementation
+ and use a default size.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+ Deallocates a mailbox. If there are messages still present in the
+ mailbox when the mailbox is deallocated, it is an indication of a
+ programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+ Posts the "msg" to the mailbox. This function have to block until
+ the "msg" is really posted.
+
+- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+
+ Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+ is full, else, ERR_OK if the "msg" is posted.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+ Blocks the thread until a message arrives in the mailbox, but does
+ not block the thread longer than "timeout" milliseconds (similar to
+ the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+ be blocked until a message arrives. The "msg" argument is a result
+ parameter that is set by the function (i.e., by doing "*msg =
+ ptr"). The "msg" parameter maybe NULL to indicate that the message
+ should be dropped.
+
+ The return values are the same as for the sys_arch_sem_wait() function:
+ Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+ timeout.
+
+ Note that a function with a similar name, sys_mbox_fetch(), is
+ implemented by lwIP.
+
+- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+
+ This is similar to sys_arch_mbox_fetch, however if a message is not
+ present in the mailbox, it immediately returns with the code
+ SYS_MBOX_EMPTY. On success 0 is returned.
+
+ To allow for efficient implementations, this can be defined as a
+ function-like macro in sys_arch.h instead of a normal function. For
+ example, a naive implementation could be:
+ #define sys_arch_mbox_tryfetch(mbox,msg) \
+ sys_arch_mbox_fetch(mbox,msg,1)
+ although this would introduce unnecessary delays.
+
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+
+ Starts a new thread named "name" with priority "prio" that will begin its
+ execution in the function "thread()". The "arg" argument will be passed as an
+ argument to the thread() function. The stack size to used for this thread is
+ the "stacksize" parameter. The id of the new thread is returned. Both the id
+ and the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+ This optional function does a "fast" critical region protection and returns
+ the previous protection level. This function is only called during very short
+ critical regions. An embedded system which supports ISR-based drivers might
+ want to implement this function by disabling interrupts. Task-based systems
+ might want to implement this by using a mutex or disabling tasking. This
+ function should support recursive calls from the same task or interrupt. In
+ other words, sys_arch_protect() could be called while already protected. In
+ that case the return value indicates that it is already protected.
+
+ sys_arch_protect() is only required if your port is supporting an operating
+ system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+ This optional function does a "fast" set of critical region protection to the
+ value specified by pval. See the documentation for sys_arch_protect() for
+ more information. This function is only required if your port is supporting
+ an operating system.
+
+Note:
+
+Be carefull with using mem_malloc() in sys_arch. When malloc() refers to
+mem_malloc() you can run into a circular function call problem. In mem.c
+mem_init() tries to allcate a semaphore using mem_malloc, which of course
+can't be performed when sys_arch uses mem_malloc.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h - Architecture environment, some compiler specific, some
+ environment specific (probably should move env stuff
+ to sys_arch.h.)
+
+ Typedefs for the types used by lwip -
+ u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+ Compiler hints for packing lwip's structures -
+ PACK_STRUCT_FIELD(x)
+ PACK_STRUCT_STRUCT
+ PACK_STRUCT_BEGIN
+ PACK_STRUCT_END
+
+ Platform specific diagnostic output -
+ LWIP_PLATFORM_DIAG(x) - non-fatal, print a message.
+ LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution.
+ Portability defines for printf formatters:
+ U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
+
+ "lightweight" synchronization mechanisms -
+ SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+ SYS_ARCH_PROTECT(x) - enter protection mode.
+ SYS_ARCH_UNPROTECT(x) - leave protection mode.
+
+ If the compiler does not provide memset() this file must include a
+ definition of it, or include a file which defines it.
+
+ This file must either include a system-local <errno.h> which defines
+ the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+ to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h - Architecture specific performance measurement.
+ Measurement calls made throughout lwip, these can be defined to nothing.
+ PERF_START - start measuring something.
+ PERF_STOP(x) - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+ Arch dependent types for the following objects:
+ sys_sem_t, sys_mbox_t, sys_thread_t,
+ And, optionally:
+ sys_prot_t
+
+ Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+ SYS_MBOX_NULL NULL
+ SYS_SEM_NULL NULL
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia b/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia
new file mode 100644
index 000000000..7c79fabff
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia
Binary files differ
diff --git a/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia b/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia
new file mode 100644
index 000000000..cbffd7c93
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia
Binary files differ
diff --git a/tool/mbed/mbed-sdk/libraries/doc/rtos.txt b/tool/mbed/mbed-sdk/libraries/doc/rtos.txt
new file mode 100644
index 000000000..2afdc6a51
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/rtos.txt
@@ -0,0 +1,37 @@
+=== Tasks ===
+
+^ os_tsk.new->task_id ^ Tasks ^ Stack Size ^
+| 0x01 | Main | 4*OS_MAINSTKSIZE |
+| 0x02 | Timer | 4*OS_TIMERSTKSZ |
+| 0xFF | Idle | 4*OS_STKSIZE |
+
+----------
+ |
+ V os_tsk.run->tsk_stack
+
+
+MAGIC_WORD os_tsk.run->stack[0]
+----------
+
+The current task structure is always pointed by:
+ struct OS_TSK os_tsk;
+
+=== Init Sequence ===
+OS:
+ * osKernelInitialize
+ * rt_sys_init
+ * rt_init_context
+ * rt_init_stack
+ * rt_set_PSP
+ * rt_init_robin
+ * rt_svc_init
+
+ * set_main_stack
+
+ * osThreadCreate(os_thread_def_main)
+ * rt_tsk_create
+ * rt_init_context
+ * rt_init_stack
+ * rt_dispatch
+
+ * osKernelStart
diff --git a/tool/mbed/mbed-sdk/libraries/doc/style.xml b/tool/mbed/mbed-sdk/libraries/doc/style.xml
new file mode 100644
index 000000000..c991069fc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/doc/style.xml
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<profiles version="1">
+<profile kind="CodeFormatterProfile" name="mbed K&amp;R" version="1">
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.lineSplit" value="80"/>
+<setting id="org.eclipse.cdt.core.formatter.alignment_for_member_access" value="2"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line" value="false"/>
+<setting id="org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch" value="true"/>
+<setting id="org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list" value="2"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression" value="do not insert"/>
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+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier" value="true"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block" value="insert"/>
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+<setting id="org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations" value="false"/>
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+<setting id="org.eclipse.cdt.core.formatter.alignment_for_declarator_list" value="16"/>
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diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c
new file mode 100644
index 000000000..90613e712
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_f32.c
+*
+* Description: Vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include <math.h>
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAbs Vector Absolute Value
+ *
+ * Computes the absolute value of a vector on an element-by-element basis.
+ *
+ * <pre>
+ * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ /* read sample from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+
+ /* find absolute value */
+ in1 = fabsf(in1);
+
+ /* read sample from source */
+ in4 = *(pSrc + 3);
+
+ /* find absolute value */
+ in2 = fabsf(in2);
+
+ /* read sample from source */
+ *pDst = in1;
+
+ /* find absolute value */
+ in3 = fabsf(in3);
+
+ /* find absolute value */
+ in4 = fabsf(in4);
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Update destination pointer to process next sampels */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
index 000000000..c7822da51
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q15.c
+*
+* Description: Q15 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *simd;
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1; /* Input value1 */
+ q15_t in2; /* Input value2 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ simd = __SIMD32_CONST(pDst);
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read two inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+ /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ pDst = (q15_t *)simd;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in1 = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary input variable */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
index 000000000..f375bf182
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q31.c
+*
+* Description: Q31 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
+ *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
+ *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
+ *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
index 000000000..125374c0c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q7.c
+*
+* Description: Q7 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in; /* Input value1 */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read inputs */
+ in1 = (q31_t) * pSrc;
+ in2 = (q31_t) * (pSrc + 1);
+ in3 = (q31_t) * (pSrc + 2);
+
+ /* find absolute value */
+ out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
+
+ /* read input */
+ in4 = (q31_t) * (pSrc + 3);
+
+ /* find absolute value */
+ out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
+
+ /* store result to destination */
+ *pDst = (q7_t) out1;
+
+ /* find absolute value */
+ out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
+
+ /* find absolute value */
+ out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
+
+ /* store result to destination */
+ *(pDst + 1) = (q7_t) out2;
+
+ /* store result to destination */
+ *(pDst + 2) = (q7_t) out3;
+
+ /* store result to destination */
+ *(pDst + 3) = (q7_t) out4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif // #define ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Store the Absolute result in the destination buffer */
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c
new file mode 100644
index 000000000..7ae25d833
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_f32.c
+*
+* Description: Floating-point vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAdd Vector Addition
+ *
+ * Element-by-element addition of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+
+ /* read four inputs from sourceA and four inputs from sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* C = A + B */
+ /* add and store result to destination */
+ *pDst = inA1 + inB1;
+ *(pDst + 1) = inA2 + inB2;
+ *(pDst + 2) = inA3 + inB3;
+ *(pDst + 3) = inA4 + inB4;
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c
new file mode 100644
index 000000000..7af88664e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q15.c
+*
+* Description: Q15 vector addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c
new file mode 100644
index 000000000..c5b9ac262
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q31.c
+*
+* Description: Q31 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QADD(inA1, inB1);
+ *pDst++ = __QADD(inA2, inB2);
+ *pDst++ = __QADD(inA3, inB3);
+ *pDst++ = __QADD(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c
new file mode 100644
index 000000000..a5bb07fc0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q7.c
+*
+* Description: Q7 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
index 000000000..870672ba3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_f32.c
+*
+* Description: Floating-point dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup dot_prod Vector Dot Product
+ *
+ * Computes the dot product of two vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * <pre>
+ * sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+
+void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer */
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ /* Store the result back in the destination buffer */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
index 000000000..3eb0a10ef
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q15.c
+*
+* Description: Q15 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
+ * results are added to a 64-bit accumulator in 34.30 format.
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
+ * there is no risk of overflow.
+ * The return result is in 34.30 format.
+ */
+
+void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the result in the destination buffer in 34.30 format */
+ *result = sum;
+
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
index 000000000..3712a0a90
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q31.c
+*
+* Description: Q31 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
+ * are truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
+ * the length of the vectors is less than 2^16 elements.
+ * The return result is in 16.48 format.
+ */
+
+void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ sum += ((q63_t) inA1 * inB1) >> 14u;
+ sum += ((q63_t) inA2 * inB2) >> 14u;
+ sum += ((q63_t) inA3 * inB3) >> 14u;
+ sum += ((q63_t) inA4 * inB4) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in the destination buffer in 16.48 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
index 000000000..bbf4dd61a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q7.c
+*
+* Description: Q7 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
+ * results are added to an accumulator in 18.14 format.
+ * Nonsaturating additions are used and there is no danger of wrap around as long as
+ * the vectors are less than 2^18 elements long.
+ * The return result is in 18.14 format.
+ */
+
+void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t blkCnt; /* loop counter */
+
+ q31_t sum = 0; /* Temporary variables to store output */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1, input2; /* Temporary variables to store input */
+ q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
+
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read 4 samples at a time from sourceA */
+ input1 = *__SIMD32(pSrcA)++;
+ /* read 4 samples at a time from sourceB */
+ input2 = *__SIMD32(pSrcB)++;
+
+ /* extract two q7_t samples to q15_t samples */
+ inA1 = __SXTB16(__ROR(input1, 8));
+ /* extract reminaing two samples */
+ inA2 = __SXTB16(input1);
+ /* extract two q7_t samples to q15_t samples */
+ inB1 = __SXTB16(__ROR(input2, 8));
+ /* extract reminaing two samples */
+ inB2 = __SXTB16(input2);
+
+ /* multiply and accumulate two samples at a time */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /* Store the result in the destination buffer in 18.14 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
index 000000000..32532e15c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_f32.c
+*
+* Description: Floating-point vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicMult Vector Multiplication
+ *
+ * Element-by-element multiplication of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ float32_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ /* read sample from sourceA */
+ inA1 = *pSrcA;
+ /* read sample from sourceB */
+ inB1 = *pSrcB;
+ /* read sample from sourceA */
+ inA2 = *(pSrcA + 1);
+ /* read sample from sourceB */
+ inB2 = *(pSrcB + 1);
+
+ /* out = sourceA * sourceB */
+ out1 = inA1 * inB1;
+
+ /* read sample from sourceA */
+ inA3 = *(pSrcA + 2);
+ /* read sample from sourceB */
+ inB3 = *(pSrcB + 2);
+
+ /* out = sourceA * sourceB */
+ out2 = inA2 * inB2;
+
+ /* read sample from sourceA */
+ inA4 = *(pSrcA + 3);
+
+ /* store result to destination buffer */
+ *pDst = out1;
+
+ /* read sample from sourceB */
+ inB4 = *(pSrcB + 3);
+
+ /* out = sourceA * sourceB */
+ out3 = inA3 * inB3;
+
+ /* store result to destination buffer */
+ *(pDst + 1) = out2;
+
+ /* out = sourceA * sourceB */
+ out4 = inA4 * inB4;
+ /* store result to destination buffer */
+ *(pDst + 2) = out3;
+ /* store result to destination buffer */
+ *(pDst + 3) = out4;
+
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c
new file mode 100644
index 000000000..ac4266ca6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q15.c
+*
+* Description: Q15 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
+ q15_t out1, out2, out3, out4; /* temporary output variables */
+ q31_t mul1, mul2, mul3, mul4; /* temporary variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read two samples at a time from sourceA */
+ inA1 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB1 = *__SIMD32(pSrcB)++;
+ /* read two samples at a time from sourceA */
+ inA2 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB2 = *__SIMD32(pSrcB)++;
+
+ /* multiply mul = sourceA * sourceB */
+ mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+ mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+ /* saturate result to 16 bit */
+ out1 = (q15_t) __SSAT(mul1 >> 15, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15, 16);
+
+ /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c
new file mode 100644
index 000000000..9210c337e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q31.c
+*
+* Description: Q31 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ q31_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB2) >> 32;
+ out3 = ((q63_t) inA3 * inB3) >> 32;
+ out4 = ((q63_t) inA4 * inB4) >> 32;
+
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ *pDst++ = out1 << 1u;
+ *pDst++ = out2 << 1u;
+ *pDst++ = out3 << 1u;
+ *pDst++ = out4 << 1u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ *pDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
index 000000000..b8cb2002a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q7.c
+*
+* Description: Q7 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q7 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in temporary variables */
+ out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
index 000000000..d887b8cdc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_f32.c
+*
+* Description: Negates floating-point vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup negate Vector Negate
+ *
+ * Negates the elements of a vector.
+ *
+ * <pre>
+ * pDst[n] = -pSrc[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* negate the input */
+ in1 = -in1;
+ in2 = -in2;
+ in3 = -in3;
+ in4 = -in4;
+
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
index 000000000..b55e0cd60
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q15.c
+*
+* Description: Negates Q15 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q15_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read two inputs at a time */
+ in1 = _SIMD32_OFFSET(pSrc);
+ in2 = _SIMD32_OFFSET(pSrc + 2);
+
+ /* negate two samples at a time */
+ in1 = __QSUB16(0, in1);
+
+ /* negate two samples at a time */
+ in2 = __QSUB16(0, in2);
+
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst) = in1;
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst + 2) = in2;
+
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
index 000000000..b0332e0cf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q31.c
+*
+* Description: Negates Q31 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t in; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QSUB(0, in1);
+ *pDst++ = __QSUB(0, in2);
+ *pDst++ = __QSUB(0, in3);
+ *pDst++ = __QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
index 000000000..9786c20d0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q7.c
+*
+* Description: Negates Q7 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t input; /* Input values1-4 */
+ q31_t zero = 0x00000000;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read four inputs */
+ input = *__SIMD32(pSrc)++;
+
+ /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+ *__SIMD32(pDst)++ = __QSUB8(zero, input);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */ \
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
index 000000000..5efb45290
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_f32.c
+*
+* Description: Floating-point vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup offset Vector Offset
+ *
+ * Adds a constant offset to each element of a vector.
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ /* read samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* add offset to input */
+ in1 = in1 + offset;
+
+ /* read samples from source */
+ in3 = *(pSrc + 2);
+
+ /* add offset to input */
+ in2 = in2 + offset;
+
+ /* read samples from source */
+ in4 = *(pSrc + 3);
+
+ /* add offset to input */
+ in3 = in3 + offset;
+
+ /* store result to destination */
+ *pDst = in1;
+
+ /* add offset to input */
+ in4 = in4 + offset;
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
index 000000000..d64ae4962
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q15.c
+*
+* Description: Q15 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PKHBT(offset, offset, 16);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
index 000000000..996241969
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q31.c
+*
+* Description: Q31 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QADD(in1, offset);
+ *pDst++ = __QADD(in2, offset);
+ *pDst++ = __QADD(in3, offset);
+ *pDst++ = __QADD(in4, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = __QADD(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
index 000000000..1e68841d5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q7.c
+*
+* Description: Q7 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PACKq7(offset, offset, offset, offset);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
index 000000000..3e61ce563
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_f32.c
+*
+* Description: Multiplies a floating-point vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup scale Vector Scale
+ *
+ * Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
+ * </pre>
+ *
+ * In the fixed-point Q7, Q15, and Q31 functions, <code>scale</code> is represented by
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The algorithm used with fixed-point data is:
+ *
+ * <pre>
+ * pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The overall scale factor applied to the fixed-point data is
+ * <pre>
+ * scale = scaleFract * 2^shift.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variabels */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the results in the destination buffer. */
+ /* read input samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* multiply with scaling factor */
+ in1 = in1 * scale;
+
+ /* read input sample from source */
+ in3 = *(pSrc + 2);
+
+ /* multiply with scaling factor */
+ in2 = in2 * scale;
+
+ /* read input sample from source */
+ in4 = *(pSrc + 3);
+
+ /* multiply with scaling factor */
+ in3 = in3 * scale;
+ in4 = in4 * scale;
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
index 000000000..9b60a02c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q15.c
+*
+* Description: Multiplies a Q15 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+
+void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 15 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t in1, in2, in3, in4;
+ q31_t inA1, inA2; /* Temporary variables */
+ q31_t out1, out2, out3, out4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 2 inputs from memory */
+ inA1 = *__SIMD32(pSrc)++;
+ inA2 = *__SIMD32(pSrc)++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ /* apply shifting */
+ out1 = out1 >> kShift;
+ out2 = out2 >> kShift;
+ out3 = out3 >> kShift;
+ out4 = out4 >> kShift;
+
+ /* saturate the output */
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ /* store the result to destination */
+ *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
index 000000000..dec26f337
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q31.c
+*
+* Description: Multiplies a Q31 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+ uint32_t blkCnt; /* loop counter */
+ q31_t in, out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variabels */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << kShift;
+ out2 = in2 << kShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> kShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> kShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << kShift;
+ out4 = in4 << kShift;
+
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ if(in3 != (out3 >> kShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> kShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ /* Store result destination */
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 >> -kShift;
+ out2 = in2 >> -kShift;
+
+ out3 = in3 >> -kShift;
+ out4 = in4 >> -kShift;
+
+ /* Store result destination */
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ if(sign == 0)
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in << kShift;
+
+ if(in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in >> -kShift;
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
index 000000000..04e61b2e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q7.c
+*
+* Description: Multiplies a Q7 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.7 format.
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
+ */
+
+void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 7 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 4 inputs from memory */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the results in the temporary variables. */
+ out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+ out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+ out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+ out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+ /* Packing the individual outputs into 32bit and storing in
+ * destination buffer in single write */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c
new file mode 100644
index 000000000..d04d79d59
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q15.c
+*
+* Description: Shifts the elements of a Q15 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ /* C = A << shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c
new file mode 100644
index 000000000..bf7d6006e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q31.c
+*
+* Description: Shifts the elements of a Q31 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+/**
+ * @defgroup shift Vector Shift
+ *
+ * Shifts the elements of a fixed-point vector by a specified number of bits.
+ * There are separate functions for Q7, Q15, and Q31 data types.
+ * The underlying algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
+ * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+ q31_t out1, out2, out3, out4; /* Temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ out1 = in1 << shiftBits;
+ in3 = *(pSrc + 2);
+ out2 = in2 << shiftBits;
+ in4 = *(pSrc + 3);
+ if(in1 != (out1 >> shiftBits))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> shiftBits))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pDst = out1;
+ out3 = in3 << shiftBits;
+ *(pDst + 1) = out2;
+ out4 = in4 << shiftBits;
+
+ if(in3 != (out3 >> shiftBits))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> shiftBits))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update destination pointer to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ *pDst = (in1 >> -shiftBits);
+ *(pDst + 1) = (in2 >> -shiftBits);
+ *(pDst + 2) = (in3 >> -shiftBits);
+ *(pDst + 3) = (in4 >> -shiftBits);
+
+
+ pSrc += 4u;
+ pDst += 4u;
+
+ blkCnt--;
+ }
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A (>> or <<) shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+ (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
index 000000000..3d7752afa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q7.c
+*
+* Description: Processing function for the Q7 Shifting
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
+ */
+
+void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1; /* Input value1 */
+ q7_t in2; /* Input value2 */
+ q7_t in3; /* Input value3 */
+ q7_t in4; /* Input value4 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+ __SSAT((in2 << shiftBits), 8),
+ __SSAT((in3 << shiftBits), 8),
+ __SSAT((in4 << shiftBits), 8));
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ shiftBits = -shiftBits;
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
+ (in3 >> shiftBits), (in4 >> shiftBits));
+
+
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ in1 = *pSrc++;
+ *pDst++ = (in1 >> shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
index 000000000..b981f4e48
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_f32.c
+*
+* Description: Floating-point vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicSub Vector Subtraction
+ *
+ * Element-by-element subtraction of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read 4 input samples from sourceA and sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* dst = srcA - srcB */
+ /* subtract and store the result */
+ *pDst = inA1 - inB1;
+ *(pDst + 1) = inA2 - inB2;
+ *(pDst + 2) = inA3 - inB3;
+ *(pDst + 3) = inA4 - inB4;
+
+
+ /* Update pointers to process next sampels */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
index 000000000..76f418368
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q15.c
+*
+* Description: Q15 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer two samples at a time. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
index 000000000..62e1d4f9b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q31.c
+*
+* Description: Q31 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QSUB(inA1, inB1);
+ *pDst++ = __QSUB(inA2, inB2);
+ *pDst++ = __QSUB(inA3, inB3);
+ *pDst++ = __QSUB(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
index 000000000..c24fd8691
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q7.c
+*
+* Description: Q7 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c
new file mode 100644
index 000000000..a4e784d18
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c
@@ -0,0 +1,16065 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.c
+*
+* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup CFFT_CIFFT Complex FFT Tables
+ * @{
+ */
+
+/**
+* \par
+* Pseudo code for Generation of Bit reversal Table is
+* \par
+* <pre>for(l=1;l <= N/4;l++)
+* {
+* for(i=0;i<logN2;i++)
+* {
+* a[i]=l&(1<<i);
+* }
+* for(j=0; j<logN2; j++)
+* {
+* if (a[j]!=0)
+* y[l]+=(1<<((logN2-1)-j));
+* }
+* y[l] = y[l] >> 1;
+* } </pre>
+* \par
+* where N = 4096 logN2 = 12
+* \par
+* N is the maximum FFT Size supported
+*/
+
+/*
+* @brief Table for bit reversal process
+*/
+const uint16_t armBitRevTable[1024] = {
+ 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700,
+ 0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380,
+ 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540,
+ 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0,
+ 0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620,
+ 0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0,
+ 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460,
+ 0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0,
+ 0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0,
+ 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,
+ 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590,
+ 0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150,
+ 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0,
+ 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230,
+ 0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0,
+ 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70,
+ 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770,
+ 0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0,
+ 0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508,
+ 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,
+ 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648,
+ 0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8,
+ 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428,
+ 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8,
+ 0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8,
+ 0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368,
+ 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8,
+ 0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118,
+ 0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698,
+ 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,
+ 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8,
+ 0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38,
+ 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738,
+ 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8,
+ 0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578,
+ 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8,
+ 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604,
+ 0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284,
+ 0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444,
+ 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,
+ 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4,
+ 0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324,
+ 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4,
+ 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164,
+ 0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4,
+ 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214,
+ 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494,
+ 0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54,
+ 0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754,
+ 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,
+ 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534,
+ 0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4,
+ 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674,
+ 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4,
+ 0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c,
+ 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c,
+ 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c,
+ 0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c,
+ 0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc,
+ 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,
+ 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac,
+ 0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c,
+ 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec,
+ 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c,
+ 0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c,
+ 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c,
+ 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c,
+ 0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc,
+ 0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c,
+ 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,
+ 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c,
+ 0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc,
+ 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc,
+ 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302,
+ 0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582,
+ 0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142,
+ 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2,
+ 0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222,
+ 0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2,
+ 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,
+ 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762,
+ 0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2,
+ 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512,
+ 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192,
+ 0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652,
+ 0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2,
+ 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432,
+ 0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2,
+ 0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2,
+ 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,
+ 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2,
+ 0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a,
+ 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a,
+ 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a,
+ 0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca,
+ 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a,
+ 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a,
+ 0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa,
+ 0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a,
+ 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,
+ 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a,
+ 0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a,
+ 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a,
+ 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda,
+ 0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da,
+ 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a,
+ 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba,
+ 0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a,
+ 0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa,
+ 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,
+ 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486,
+ 0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46,
+ 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746,
+ 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6,
+ 0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526,
+ 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6,
+ 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666,
+ 0x166, 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6,
+ 0x6e6, 0x1e6, 0x5e6, 0x3e6, 0x7e6, 0x16, 0x416,
+ 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,
+ 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796,
+ 0x56, 0x456, 0x256, 0x656, 0x156, 0x556, 0x356,
+ 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 0x5d6,
+ 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136,
+ 0x536, 0x336, 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6,
+ 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 0x476, 0x276,
+ 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6,
+ 0x2f6, 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe,
+ 0x40e, 0x20e, 0x60e, 0x10e, 0x50e, 0x30e, 0x70e,
+ 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,
+ 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e,
+ 0x34e, 0x74e, 0xce, 0x4ce, 0x2ce, 0x6ce, 0x1ce,
+ 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 0x62e,
+ 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae,
+ 0x6ae, 0x1ae, 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e,
+ 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 0x76e, 0xee,
+ 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee,
+ 0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e,
+ 0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e,
+ 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,
+ 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de,
+ 0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e,
+ 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be,
+ 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e,
+ 0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e,
+ 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe,
+ 0x7fe, 0x1
+};
+
+
+/*
+* @brief Floating-point Twiddle factors Table Generation
+*/
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_16[32] = {
+ 1.000000000f, 0.000000000f,
+ 0.923879533f, 0.382683432f,
+ 0.707106781f, 0.707106781f,
+ 0.382683432f, 0.923879533f,
+ 0.000000000f, 1.000000000f,
+ -0.382683432f, 0.923879533f,
+ -0.707106781f, 0.707106781f,
+ -0.923879533f, 0.382683432f,
+ -1.000000000f, 0.000000000f,
+ -0.923879533f, -0.382683432f,
+ -0.707106781f, -0.707106781f,
+ -0.382683432f, -0.923879533f,
+ -0.000000000f, -1.000000000f,
+ 0.382683432f, -0.923879533f,
+ 0.707106781f, -0.707106781f,
+ 0.923879533f, -0.382683432f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_32[64] = {
+ 1.000000000f, 0.000000000f,
+ 0.980785280f, 0.195090322f,
+ 0.923879533f, 0.382683432f,
+ 0.831469612f, 0.555570233f,
+ 0.707106781f, 0.707106781f,
+ 0.555570233f, 0.831469612f,
+ 0.382683432f, 0.923879533f,
+ 0.195090322f, 0.980785280f,
+ 0.000000000f, 1.000000000f,
+ -0.195090322f, 0.980785280f,
+ -0.382683432f, 0.923879533f,
+ -0.555570233f, 0.831469612f,
+ -0.707106781f, 0.707106781f,
+ -0.831469612f, 0.555570233f,
+ -0.923879533f, 0.382683432f,
+ -0.980785280f, 0.195090322f,
+ -1.000000000f, 0.000000000f,
+ -0.980785280f, -0.195090322f,
+ -0.923879533f, -0.382683432f,
+ -0.831469612f, -0.555570233f,
+ -0.707106781f, -0.707106781f,
+ -0.555570233f, -0.831469612f,
+ -0.382683432f, -0.923879533f,
+ -0.195090322f, -0.980785280f,
+ -0.000000000f, -1.000000000f,
+ 0.195090322f, -0.980785280f,
+ 0.382683432f, -0.923879533f,
+ 0.555570233f, -0.831469612f,
+ 0.707106781f, -0.707106781f,
+ 0.831469612f, -0.555570233f,
+ 0.923879533f, -0.382683432f,
+ 0.980785280f, -0.195090322f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_64[128] = {
+ 1.000000000f, 0.000000000f,
+ 0.995184727f, 0.098017140f,
+ 0.980785280f, 0.195090322f,
+ 0.956940336f, 0.290284677f,
+ 0.923879533f, 0.382683432f,
+ 0.881921264f, 0.471396737f,
+ 0.831469612f, 0.555570233f,
+ 0.773010453f, 0.634393284f,
+ 0.707106781f, 0.707106781f,
+ 0.634393284f, 0.773010453f,
+ 0.555570233f, 0.831469612f,
+ 0.471396737f, 0.881921264f,
+ 0.382683432f, 0.923879533f,
+ 0.290284677f, 0.956940336f,
+ 0.195090322f, 0.980785280f,
+ 0.098017140f, 0.995184727f,
+ 0.000000000f, 1.000000000f,
+ -0.098017140f, 0.995184727f,
+ -0.195090322f, 0.980785280f,
+ -0.290284677f, 0.956940336f,
+ -0.382683432f, 0.923879533f,
+ -0.471396737f, 0.881921264f,
+ -0.555570233f, 0.831469612f,
+ -0.634393284f, 0.773010453f,
+ -0.707106781f, 0.707106781f,
+ -0.773010453f, 0.634393284f,
+ -0.831469612f, 0.555570233f,
+ -0.881921264f, 0.471396737f,
+ -0.923879533f, 0.382683432f,
+ -0.956940336f, 0.290284677f,
+ -0.980785280f, 0.195090322f,
+ -0.995184727f, 0.098017140f,
+ -1.000000000f, 0.000000000f,
+ -0.995184727f, -0.098017140f,
+ -0.980785280f, -0.195090322f,
+ -0.956940336f, -0.290284677f,
+ -0.923879533f, -0.382683432f,
+ -0.881921264f, -0.471396737f,
+ -0.831469612f, -0.555570233f,
+ -0.773010453f, -0.634393284f,
+ -0.707106781f, -0.707106781f,
+ -0.634393284f, -0.773010453f,
+ -0.555570233f, -0.831469612f,
+ -0.471396737f, -0.881921264f,
+ -0.382683432f, -0.923879533f,
+ -0.290284677f, -0.956940336f,
+ -0.195090322f, -0.980785280f,
+ -0.098017140f, -0.995184727f,
+ -0.000000000f, -1.000000000f,
+ 0.098017140f, -0.995184727f,
+ 0.195090322f, -0.980785280f,
+ 0.290284677f, -0.956940336f,
+ 0.382683432f, -0.923879533f,
+ 0.471396737f, -0.881921264f,
+ 0.555570233f, -0.831469612f,
+ 0.634393284f, -0.773010453f,
+ 0.707106781f, -0.707106781f,
+ 0.773010453f, -0.634393284f,
+ 0.831469612f, -0.555570233f,
+ 0.881921264f, -0.471396737f,
+ 0.923879533f, -0.382683432f,
+ 0.956940336f, -0.290284677f,
+ 0.980785280f, -0.195090322f,
+ 0.995184727f, -0.098017140f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+
+const float32_t twiddleCoef_128[256] = {
+1.000000000f , 0.000000000f ,
+0.998795456f , 0.049067674f ,
+0.995184727f , 0.098017140f ,
+0.989176510f , 0.146730474f ,
+0.980785280f , 0.195090322f ,
+0.970031253f , 0.242980180f ,
+0.956940336f , 0.290284677f ,
+0.941544065f , 0.336889853f ,
+0.923879533f , 0.382683432f ,
+0.903989293f , 0.427555093f ,
+0.881921264f , 0.471396737f ,
+0.857728610f , 0.514102744f ,
+0.831469612f , 0.555570233f ,
+0.803207531f , 0.595699304f ,
+0.773010453f , 0.634393284f ,
+0.740951125f , 0.671558955f ,
+0.707106781f , 0.707106781f ,
+0.671558955f , 0.740951125f ,
+0.634393284f , 0.773010453f ,
+0.595699304f , 0.803207531f ,
+0.555570233f , 0.831469612f ,
+0.514102744f , 0.857728610f ,
+0.471396737f , 0.881921264f ,
+0.427555093f , 0.903989293f ,
+0.382683432f , 0.923879533f ,
+0.336889853f , 0.941544065f ,
+0.290284677f , 0.956940336f ,
+0.242980180f , 0.970031253f ,
+0.195090322f , 0.980785280f ,
+0.146730474f , 0.989176510f ,
+0.098017140f , 0.995184727f ,
+0.049067674f , 0.998795456f ,
+0.000000000f , 1.000000000f ,
+-0.049067674f , 0.998795456f ,
+-0.098017140f , 0.995184727f ,
+-0.146730474f , 0.989176510f ,
+-0.195090322f , 0.980785280f ,
+-0.242980180f , 0.970031253f ,
+-0.290284677f , 0.956940336f ,
+-0.336889853f , 0.941544065f ,
+-0.382683432f , 0.923879533f ,
+-0.427555093f , 0.903989293f ,
+-0.471396737f , 0.881921264f ,
+-0.514102744f , 0.857728610f ,
+-0.555570233f , 0.831469612f ,
+-0.595699304f , 0.803207531f ,
+-0.634393284f , 0.773010453f ,
+-0.671558955f , 0.740951125f ,
+-0.707106781f , 0.707106781f ,
+-0.740951125f , 0.671558955f ,
+-0.773010453f , 0.634393284f ,
+-0.803207531f , 0.595699304f ,
+-0.831469612f , 0.555570233f ,
+-0.857728610f , 0.514102744f ,
+-0.881921264f , 0.471396737f ,
+-0.903989293f , 0.427555093f ,
+-0.923879533f , 0.382683432f ,
+-0.941544065f , 0.336889853f ,
+-0.956940336f , 0.290284677f ,
+-0.970031253f , 0.242980180f ,
+-0.980785280f , 0.195090322f ,
+-0.989176510f , 0.146730474f ,
+-0.995184727f , 0.098017140f ,
+-0.998795456f , 0.049067674f ,
+-1.000000000f , 0.000000000f ,
+-0.998795456f , -0.049067674f ,
+-0.995184727f , -0.098017140f ,
+-0.989176510f , -0.146730474f ,
+-0.980785280f , -0.195090322f ,
+-0.970031253f , -0.242980180f ,
+-0.956940336f , -0.290284677f ,
+-0.941544065f , -0.336889853f ,
+-0.923879533f , -0.382683432f ,
+-0.903989293f , -0.427555093f ,
+-0.881921264f , -0.471396737f ,
+-0.857728610f , -0.514102744f ,
+-0.831469612f , -0.555570233f ,
+-0.803207531f , -0.595699304f ,
+-0.773010453f , -0.634393284f ,
+-0.740951125f , -0.671558955f ,
+-0.707106781f , -0.707106781f ,
+-0.671558955f , -0.740951125f ,
+-0.634393284f , -0.773010453f ,
+-0.595699304f , -0.803207531f ,
+-0.555570233f , -0.831469612f ,
+-0.514102744f , -0.857728610f ,
+-0.471396737f , -0.881921264f ,
+-0.427555093f , -0.903989293f ,
+-0.382683432f , -0.923879533f ,
+-0.336889853f , -0.941544065f ,
+-0.290284677f , -0.956940336f ,
+-0.242980180f , -0.970031253f ,
+-0.195090322f , -0.980785280f ,
+-0.146730474f , -0.989176510f ,
+-0.098017140f , -0.995184727f ,
+-0.049067674f , -0.998795456f ,
+-0.000000000f , -1.000000000f ,
+0.049067674f , -0.998795456f ,
+0.098017140f , -0.995184727f ,
+0.146730474f , -0.989176510f ,
+0.195090322f , -0.980785280f ,
+0.242980180f , -0.970031253f ,
+0.290284677f , -0.956940336f ,
+0.336889853f , -0.941544065f ,
+0.382683432f , -0.923879533f ,
+0.427555093f , -0.903989293f ,
+0.471396737f , -0.881921264f ,
+0.514102744f , -0.857728610f ,
+0.555570233f , -0.831469612f ,
+0.595699304f , -0.803207531f ,
+0.634393284f , -0.773010453f ,
+0.671558955f , -0.740951125f ,
+0.707106781f , -0.707106781f ,
+0.740951125f , -0.671558955f ,
+0.773010453f , -0.634393284f ,
+0.803207531f , -0.595699304f ,
+0.831469612f , -0.555570233f ,
+0.857728610f , -0.514102744f ,
+0.881921264f , -0.471396737f ,
+0.903989293f , -0.427555093f ,
+0.923879533f , -0.382683432f ,
+0.941544065f , -0.336889853f ,
+0.956940336f , -0.290284677f ,
+0.970031253f , -0.242980180f ,
+0.980785280f , -0.195090322f ,
+0.989176510f , -0.146730474f ,
+0.995184727f , -0.098017140f ,
+0.998795456f , -0.049067674f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_256[512] = {
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, 0.024541229f,
+ 0.998795456f, 0.049067674f,
+ 0.997290457f, 0.073564564f,
+ 0.995184727f, 0.098017140f,
+ 0.992479535f, 0.122410675f,
+ 0.989176510f, 0.146730474f,
+ 0.985277642f, 0.170961889f,
+ 0.980785280f, 0.195090322f,
+ 0.975702130f, 0.219101240f,
+ 0.970031253f, 0.242980180f,
+ 0.963776066f, 0.266712757f,
+ 0.956940336f, 0.290284677f,
+ 0.949528181f, 0.313681740f,
+ 0.941544065f, 0.336889853f,
+ 0.932992799f, 0.359895037f,
+ 0.923879533f, 0.382683432f,
+ 0.914209756f, 0.405241314f,
+ 0.903989293f, 0.427555093f,
+ 0.893224301f, 0.449611330f,
+ 0.881921264f, 0.471396737f,
+ 0.870086991f, 0.492898192f,
+ 0.857728610f, 0.514102744f,
+ 0.844853565f, 0.534997620f,
+ 0.831469612f, 0.555570233f,
+ 0.817584813f, 0.575808191f,
+ 0.803207531f, 0.595699304f,
+ 0.788346428f, 0.615231591f,
+ 0.773010453f, 0.634393284f,
+ 0.757208847f, 0.653172843f,
+ 0.740951125f, 0.671558955f,
+ 0.724247083f, 0.689540545f,
+ 0.707106781f, 0.707106781f,
+ 0.689540545f, 0.724247083f,
+ 0.671558955f, 0.740951125f,
+ 0.653172843f, 0.757208847f,
+ 0.634393284f, 0.773010453f,
+ 0.615231591f, 0.788346428f,
+ 0.595699304f, 0.803207531f,
+ 0.575808191f, 0.817584813f,
+ 0.555570233f, 0.831469612f,
+ 0.534997620f, 0.844853565f,
+ 0.514102744f, 0.857728610f,
+ 0.492898192f, 0.870086991f,
+ 0.471396737f, 0.881921264f,
+ 0.449611330f, 0.893224301f,
+ 0.427555093f, 0.903989293f,
+ 0.405241314f, 0.914209756f,
+ 0.382683432f, 0.923879533f,
+ 0.359895037f, 0.932992799f,
+ 0.336889853f, 0.941544065f,
+ 0.313681740f, 0.949528181f,
+ 0.290284677f, 0.956940336f,
+ 0.266712757f, 0.963776066f,
+ 0.242980180f, 0.970031253f,
+ 0.219101240f, 0.975702130f,
+ 0.195090322f, 0.980785280f,
+ 0.170961889f, 0.985277642f,
+ 0.146730474f, 0.989176510f,
+ 0.122410675f, 0.992479535f,
+ 0.098017140f, 0.995184727f,
+ 0.073564564f, 0.997290457f,
+ 0.049067674f, 0.998795456f,
+ 0.024541229f, 0.999698819f,
+ 0.000000000f, 1.000000000f,
+ -0.024541229f, 0.999698819f,
+ -0.049067674f, 0.998795456f,
+ -0.073564564f, 0.997290457f,
+ -0.098017140f, 0.995184727f,
+ -0.122410675f, 0.992479535f,
+ -0.146730474f, 0.989176510f,
+ -0.170961889f, 0.985277642f,
+ -0.195090322f, 0.980785280f,
+ -0.219101240f, 0.975702130f,
+ -0.242980180f, 0.970031253f,
+ -0.266712757f, 0.963776066f,
+ -0.290284677f, 0.956940336f,
+ -0.313681740f, 0.949528181f,
+ -0.336889853f, 0.941544065f,
+ -0.359895037f, 0.932992799f,
+ -0.382683432f, 0.923879533f,
+ -0.405241314f, 0.914209756f,
+ -0.427555093f, 0.903989293f,
+ -0.449611330f, 0.893224301f,
+ -0.471396737f, 0.881921264f,
+ -0.492898192f, 0.870086991f,
+ -0.514102744f, 0.857728610f,
+ -0.534997620f, 0.844853565f,
+ -0.555570233f, 0.831469612f,
+ -0.575808191f, 0.817584813f,
+ -0.595699304f, 0.803207531f,
+ -0.615231591f, 0.788346428f,
+ -0.634393284f, 0.773010453f,
+ -0.653172843f, 0.757208847f,
+ -0.671558955f, 0.740951125f,
+ -0.689540545f, 0.724247083f,
+ -0.707106781f, 0.707106781f,
+ -0.724247083f, 0.689540545f,
+ -0.740951125f, 0.671558955f,
+ -0.757208847f, 0.653172843f,
+ -0.773010453f, 0.634393284f,
+ -0.788346428f, 0.615231591f,
+ -0.803207531f, 0.595699304f,
+ -0.817584813f, 0.575808191f,
+ -0.831469612f, 0.555570233f,
+ -0.844853565f, 0.534997620f,
+ -0.857728610f, 0.514102744f,
+ -0.870086991f, 0.492898192f,
+ -0.881921264f, 0.471396737f,
+ -0.893224301f, 0.449611330f,
+ -0.903989293f, 0.427555093f,
+ -0.914209756f, 0.405241314f,
+ -0.923879533f, 0.382683432f,
+ -0.932992799f, 0.359895037f,
+ -0.941544065f, 0.336889853f,
+ -0.949528181f, 0.313681740f,
+ -0.956940336f, 0.290284677f,
+ -0.963776066f, 0.266712757f,
+ -0.970031253f, 0.242980180f,
+ -0.975702130f, 0.219101240f,
+ -0.980785280f, 0.195090322f,
+ -0.985277642f, 0.170961889f,
+ -0.989176510f, 0.146730474f,
+ -0.992479535f, 0.122410675f,
+ -0.995184727f, 0.098017140f,
+ -0.997290457f, 0.073564564f,
+ -0.998795456f, 0.049067674f,
+ -0.999698819f, 0.024541229f,
+ -1.000000000f, 0.000000000f,
+ -0.999698819f, -0.024541229f,
+ -0.998795456f, -0.049067674f,
+ -0.997290457f, -0.073564564f,
+ -0.995184727f, -0.098017140f,
+ -0.992479535f, -0.122410675f,
+ -0.989176510f, -0.146730474f,
+ -0.985277642f, -0.170961889f,
+ -0.980785280f, -0.195090322f,
+ -0.975702130f, -0.219101240f,
+ -0.970031253f, -0.242980180f,
+ -0.963776066f, -0.266712757f,
+ -0.956940336f, -0.290284677f,
+ -0.949528181f, -0.313681740f,
+ -0.941544065f, -0.336889853f,
+ -0.932992799f, -0.359895037f,
+ -0.923879533f, -0.382683432f,
+ -0.914209756f, -0.405241314f,
+ -0.903989293f, -0.427555093f,
+ -0.893224301f, -0.449611330f,
+ -0.881921264f, -0.471396737f,
+ -0.870086991f, -0.492898192f,
+ -0.857728610f, -0.514102744f,
+ -0.844853565f, -0.534997620f,
+ -0.831469612f, -0.555570233f,
+ -0.817584813f, -0.575808191f,
+ -0.803207531f, -0.595699304f,
+ -0.788346428f, -0.615231591f,
+ -0.773010453f, -0.634393284f,
+ -0.757208847f, -0.653172843f,
+ -0.740951125f, -0.671558955f,
+ -0.724247083f, -0.689540545f,
+ -0.707106781f, -0.707106781f,
+ -0.689540545f, -0.724247083f,
+ -0.671558955f, -0.740951125f,
+ -0.653172843f, -0.757208847f,
+ -0.634393284f, -0.773010453f,
+ -0.615231591f, -0.788346428f,
+ -0.595699304f, -0.803207531f,
+ -0.575808191f, -0.817584813f,
+ -0.555570233f, -0.831469612f,
+ -0.534997620f, -0.844853565f,
+ -0.514102744f, -0.857728610f,
+ -0.492898192f, -0.870086991f,
+ -0.471396737f, -0.881921264f,
+ -0.449611330f, -0.893224301f,
+ -0.427555093f, -0.903989293f,
+ -0.405241314f, -0.914209756f,
+ -0.382683432f, -0.923879533f,
+ -0.359895037f, -0.932992799f,
+ -0.336889853f, -0.941544065f,
+ -0.313681740f, -0.949528181f,
+ -0.290284677f, -0.956940336f,
+ -0.266712757f, -0.963776066f,
+ -0.242980180f, -0.970031253f,
+ -0.219101240f, -0.975702130f,
+ -0.195090322f, -0.980785280f,
+ -0.170961889f, -0.985277642f,
+ -0.146730474f, -0.989176510f,
+ -0.122410675f, -0.992479535f,
+ -0.098017140f, -0.995184727f,
+ -0.073564564f, -0.997290457f,
+ -0.049067674f, -0.998795456f,
+ -0.024541229f, -0.999698819f,
+ -0.000000000f, -1.000000000f,
+ 0.024541229f, -0.999698819f,
+ 0.049067674f, -0.998795456f,
+ 0.073564564f, -0.997290457f,
+ 0.098017140f, -0.995184727f,
+ 0.122410675f, -0.992479535f,
+ 0.146730474f, -0.989176510f,
+ 0.170961889f, -0.985277642f,
+ 0.195090322f, -0.980785280f,
+ 0.219101240f, -0.975702130f,
+ 0.242980180f, -0.970031253f,
+ 0.266712757f, -0.963776066f,
+ 0.290284677f, -0.956940336f,
+ 0.313681740f, -0.949528181f,
+ 0.336889853f, -0.941544065f,
+ 0.359895037f, -0.932992799f,
+ 0.382683432f, -0.923879533f,
+ 0.405241314f, -0.914209756f,
+ 0.427555093f, -0.903989293f,
+ 0.449611330f, -0.893224301f,
+ 0.471396737f, -0.881921264f,
+ 0.492898192f, -0.870086991f,
+ 0.514102744f, -0.857728610f,
+ 0.534997620f, -0.844853565f,
+ 0.555570233f, -0.831469612f,
+ 0.575808191f, -0.817584813f,
+ 0.595699304f, -0.803207531f,
+ 0.615231591f, -0.788346428f,
+ 0.634393284f, -0.773010453f,
+ 0.653172843f, -0.757208847f,
+ 0.671558955f, -0.740951125f,
+ 0.689540545f, -0.724247083f,
+ 0.707106781f, -0.707106781f,
+ 0.724247083f, -0.689540545f,
+ 0.740951125f, -0.671558955f,
+ 0.757208847f, -0.653172843f,
+ 0.773010453f, -0.634393284f,
+ 0.788346428f, -0.615231591f,
+ 0.803207531f, -0.595699304f,
+ 0.817584813f, -0.575808191f,
+ 0.831469612f, -0.555570233f,
+ 0.844853565f, -0.534997620f,
+ 0.857728610f, -0.514102744f,
+ 0.870086991f, -0.492898192f,
+ 0.881921264f, -0.471396737f,
+ 0.893224301f, -0.449611330f,
+ 0.903989293f, -0.427555093f,
+ 0.914209756f, -0.405241314f,
+ 0.923879533f, -0.382683432f,
+ 0.932992799f, -0.359895037f,
+ 0.941544065f, -0.336889853f,
+ 0.949528181f, -0.313681740f,
+ 0.956940336f, -0.290284677f,
+ 0.963776066f, -0.266712757f,
+ 0.970031253f, -0.242980180f,
+ 0.975702130f, -0.219101240f,
+ 0.980785280f, -0.195090322f,
+ 0.985277642f, -0.170961889f,
+ 0.989176510f, -0.146730474f,
+ 0.992479535f, -0.122410675f,
+ 0.995184727f, -0.098017140f,
+ 0.997290457f, -0.073564564f,
+ 0.998795456f, -0.049067674f,
+ 0.999698819f, -0.024541229f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_512[1024] = {
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, 0.012271538f,
+ 0.999698819f, 0.024541229f,
+ 0.999322385f, 0.036807223f,
+ 0.998795456f, 0.049067674f,
+ 0.998118113f, 0.061320736f,
+ 0.997290457f, 0.073564564f,
+ 0.996312612f, 0.085797312f,
+ 0.995184727f, 0.098017140f,
+ 0.993906970f, 0.110222207f,
+ 0.992479535f, 0.122410675f,
+ 0.990902635f, 0.134580709f,
+ 0.989176510f, 0.146730474f,
+ 0.987301418f, 0.158858143f,
+ 0.985277642f, 0.170961889f,
+ 0.983105487f, 0.183039888f,
+ 0.980785280f, 0.195090322f,
+ 0.978317371f, 0.207111376f,
+ 0.975702130f, 0.219101240f,
+ 0.972939952f, 0.231058108f,
+ 0.970031253f, 0.242980180f,
+ 0.966976471f, 0.254865660f,
+ 0.963776066f, 0.266712757f,
+ 0.960430519f, 0.278519689f,
+ 0.956940336f, 0.290284677f,
+ 0.953306040f, 0.302005949f,
+ 0.949528181f, 0.313681740f,
+ 0.945607325f, 0.325310292f,
+ 0.941544065f, 0.336889853f,
+ 0.937339012f, 0.348418680f,
+ 0.932992799f, 0.359895037f,
+ 0.928506080f, 0.371317194f,
+ 0.923879533f, 0.382683432f,
+ 0.919113852f, 0.393992040f,
+ 0.914209756f, 0.405241314f,
+ 0.909167983f, 0.416429560f,
+ 0.903989293f, 0.427555093f,
+ 0.898674466f, 0.438616239f,
+ 0.893224301f, 0.449611330f,
+ 0.887639620f, 0.460538711f,
+ 0.881921264f, 0.471396737f,
+ 0.876070094f, 0.482183772f,
+ 0.870086991f, 0.492898192f,
+ 0.863972856f, 0.503538384f,
+ 0.857728610f, 0.514102744f,
+ 0.851355193f, 0.524589683f,
+ 0.844853565f, 0.534997620f,
+ 0.838224706f, 0.545324988f,
+ 0.831469612f, 0.555570233f,
+ 0.824589303f, 0.565731811f,
+ 0.817584813f, 0.575808191f,
+ 0.810457198f, 0.585797857f,
+ 0.803207531f, 0.595699304f,
+ 0.795836905f, 0.605511041f,
+ 0.788346428f, 0.615231591f,
+ 0.780737229f, 0.624859488f,
+ 0.773010453f, 0.634393284f,
+ 0.765167266f, 0.643831543f,
+ 0.757208847f, 0.653172843f,
+ 0.749136395f, 0.662415778f,
+ 0.740951125f, 0.671558955f,
+ 0.732654272f, 0.680600998f,
+ 0.724247083f, 0.689540545f,
+ 0.715730825f, 0.698376249f,
+ 0.707106781f, 0.707106781f,
+ 0.698376249f, 0.715730825f,
+ 0.689540545f, 0.724247083f,
+ 0.680600998f, 0.732654272f,
+ 0.671558955f, 0.740951125f,
+ 0.662415778f, 0.749136395f,
+ 0.653172843f, 0.757208847f,
+ 0.643831543f, 0.765167266f,
+ 0.634393284f, 0.773010453f,
+ 0.624859488f, 0.780737229f,
+ 0.615231591f, 0.788346428f,
+ 0.605511041f, 0.795836905f,
+ 0.595699304f, 0.803207531f,
+ 0.585797857f, 0.810457198f,
+ 0.575808191f, 0.817584813f,
+ 0.565731811f, 0.824589303f,
+ 0.555570233f, 0.831469612f,
+ 0.545324988f, 0.838224706f,
+ 0.534997620f, 0.844853565f,
+ 0.524589683f, 0.851355193f,
+ 0.514102744f, 0.857728610f,
+ 0.503538384f, 0.863972856f,
+ 0.492898192f, 0.870086991f,
+ 0.482183772f, 0.876070094f,
+ 0.471396737f, 0.881921264f,
+ 0.460538711f, 0.887639620f,
+ 0.449611330f, 0.893224301f,
+ 0.438616239f, 0.898674466f,
+ 0.427555093f, 0.903989293f,
+ 0.416429560f, 0.909167983f,
+ 0.405241314f, 0.914209756f,
+ 0.393992040f, 0.919113852f,
+ 0.382683432f, 0.923879533f,
+ 0.371317194f, 0.928506080f,
+ 0.359895037f, 0.932992799f,
+ 0.348418680f, 0.937339012f,
+ 0.336889853f, 0.941544065f,
+ 0.325310292f, 0.945607325f,
+ 0.313681740f, 0.949528181f,
+ 0.302005949f, 0.953306040f,
+ 0.290284677f, 0.956940336f,
+ 0.278519689f, 0.960430519f,
+ 0.266712757f, 0.963776066f,
+ 0.254865660f, 0.966976471f,
+ 0.242980180f, 0.970031253f,
+ 0.231058108f, 0.972939952f,
+ 0.219101240f, 0.975702130f,
+ 0.207111376f, 0.978317371f,
+ 0.195090322f, 0.980785280f,
+ 0.183039888f, 0.983105487f,
+ 0.170961889f, 0.985277642f,
+ 0.158858143f, 0.987301418f,
+ 0.146730474f, 0.989176510f,
+ 0.134580709f, 0.990902635f,
+ 0.122410675f, 0.992479535f,
+ 0.110222207f, 0.993906970f,
+ 0.098017140f, 0.995184727f,
+ 0.085797312f, 0.996312612f,
+ 0.073564564f, 0.997290457f,
+ 0.061320736f, 0.998118113f,
+ 0.049067674f, 0.998795456f,
+ 0.036807223f, 0.999322385f,
+ 0.024541229f, 0.999698819f,
+ 0.012271538f, 0.999924702f,
+ 0.000000000f, 1.000000000f,
+ -0.012271538f, 0.999924702f,
+ -0.024541229f, 0.999698819f,
+ -0.036807223f, 0.999322385f,
+ -0.049067674f, 0.998795456f,
+ -0.061320736f, 0.998118113f,
+ -0.073564564f, 0.997290457f,
+ -0.085797312f, 0.996312612f,
+ -0.098017140f, 0.995184727f,
+ -0.110222207f, 0.993906970f,
+ -0.122410675f, 0.992479535f,
+ -0.134580709f, 0.990902635f,
+ -0.146730474f, 0.989176510f,
+ -0.158858143f, 0.987301418f,
+ -0.170961889f, 0.985277642f,
+ -0.183039888f, 0.983105487f,
+ -0.195090322f, 0.980785280f,
+ -0.207111376f, 0.978317371f,
+ -0.219101240f, 0.975702130f,
+ -0.231058108f, 0.972939952f,
+ -0.242980180f, 0.970031253f,
+ -0.254865660f, 0.966976471f,
+ -0.266712757f, 0.963776066f,
+ -0.278519689f, 0.960430519f,
+ -0.290284677f, 0.956940336f,
+ -0.302005949f, 0.953306040f,
+ -0.313681740f, 0.949528181f,
+ -0.325310292f, 0.945607325f,
+ -0.336889853f, 0.941544065f,
+ -0.348418680f, 0.937339012f,
+ -0.359895037f, 0.932992799f,
+ -0.371317194f, 0.928506080f,
+ -0.382683432f, 0.923879533f,
+ -0.393992040f, 0.919113852f,
+ -0.405241314f, 0.914209756f,
+ -0.416429560f, 0.909167983f,
+ -0.427555093f, 0.903989293f,
+ -0.438616239f, 0.898674466f,
+ -0.449611330f, 0.893224301f,
+ -0.460538711f, 0.887639620f,
+ -0.471396737f, 0.881921264f,
+ -0.482183772f, 0.876070094f,
+ -0.492898192f, 0.870086991f,
+ -0.503538384f, 0.863972856f,
+ -0.514102744f, 0.857728610f,
+ -0.524589683f, 0.851355193f,
+ -0.534997620f, 0.844853565f,
+ -0.545324988f, 0.838224706f,
+ -0.555570233f, 0.831469612f,
+ -0.565731811f, 0.824589303f,
+ -0.575808191f, 0.817584813f,
+ -0.585797857f, 0.810457198f,
+ -0.595699304f, 0.803207531f,
+ -0.605511041f, 0.795836905f,
+ -0.615231591f, 0.788346428f,
+ -0.624859488f, 0.780737229f,
+ -0.634393284f, 0.773010453f,
+ -0.643831543f, 0.765167266f,
+ -0.653172843f, 0.757208847f,
+ -0.662415778f, 0.749136395f,
+ -0.671558955f, 0.740951125f,
+ -0.680600998f, 0.732654272f,
+ -0.689540545f, 0.724247083f,
+ -0.698376249f, 0.715730825f,
+ -0.707106781f, 0.707106781f,
+ -0.715730825f, 0.698376249f,
+ -0.724247083f, 0.689540545f,
+ -0.732654272f, 0.680600998f,
+ -0.740951125f, 0.671558955f,
+ -0.749136395f, 0.662415778f,
+ -0.757208847f, 0.653172843f,
+ -0.765167266f, 0.643831543f,
+ -0.773010453f, 0.634393284f,
+ -0.780737229f, 0.624859488f,
+ -0.788346428f, 0.615231591f,
+ -0.795836905f, 0.605511041f,
+ -0.803207531f, 0.595699304f,
+ -0.810457198f, 0.585797857f,
+ -0.817584813f, 0.575808191f,
+ -0.824589303f, 0.565731811f,
+ -0.831469612f, 0.555570233f,
+ -0.838224706f, 0.545324988f,
+ -0.844853565f, 0.534997620f,
+ -0.851355193f, 0.524589683f,
+ -0.857728610f, 0.514102744f,
+ -0.863972856f, 0.503538384f,
+ -0.870086991f, 0.492898192f,
+ -0.876070094f, 0.482183772f,
+ -0.881921264f, 0.471396737f,
+ -0.887639620f, 0.460538711f,
+ -0.893224301f, 0.449611330f,
+ -0.898674466f, 0.438616239f,
+ -0.903989293f, 0.427555093f,
+ -0.909167983f, 0.416429560f,
+ -0.914209756f, 0.405241314f,
+ -0.919113852f, 0.393992040f,
+ -0.923879533f, 0.382683432f,
+ -0.928506080f, 0.371317194f,
+ -0.932992799f, 0.359895037f,
+ -0.937339012f, 0.348418680f,
+ -0.941544065f, 0.336889853f,
+ -0.945607325f, 0.325310292f,
+ -0.949528181f, 0.313681740f,
+ -0.953306040f, 0.302005949f,
+ -0.956940336f, 0.290284677f,
+ -0.960430519f, 0.278519689f,
+ -0.963776066f, 0.266712757f,
+ -0.966976471f, 0.254865660f,
+ -0.970031253f, 0.242980180f,
+ -0.972939952f, 0.231058108f,
+ -0.975702130f, 0.219101240f,
+ -0.978317371f, 0.207111376f,
+ -0.980785280f, 0.195090322f,
+ -0.983105487f, 0.183039888f,
+ -0.985277642f, 0.170961889f,
+ -0.987301418f, 0.158858143f,
+ -0.989176510f, 0.146730474f,
+ -0.990902635f, 0.134580709f,
+ -0.992479535f, 0.122410675f,
+ -0.993906970f, 0.110222207f,
+ -0.995184727f, 0.098017140f,
+ -0.996312612f, 0.085797312f,
+ -0.997290457f, 0.073564564f,
+ -0.998118113f, 0.061320736f,
+ -0.998795456f, 0.049067674f,
+ -0.999322385f, 0.036807223f,
+ -0.999698819f, 0.024541229f,
+ -0.999924702f, 0.012271538f,
+ -1.000000000f, 0.000000000f,
+ -0.999924702f, -0.012271538f,
+ -0.999698819f, -0.024541229f,
+ -0.999322385f, -0.036807223f,
+ -0.998795456f, -0.049067674f,
+ -0.998118113f, -0.061320736f,
+ -0.997290457f, -0.073564564f,
+ -0.996312612f, -0.085797312f,
+ -0.995184727f, -0.098017140f,
+ -0.993906970f, -0.110222207f,
+ -0.992479535f, -0.122410675f,
+ -0.990902635f, -0.134580709f,
+ -0.989176510f, -0.146730474f,
+ -0.987301418f, -0.158858143f,
+ -0.985277642f, -0.170961889f,
+ -0.983105487f, -0.183039888f,
+ -0.980785280f, -0.195090322f,
+ -0.978317371f, -0.207111376f,
+ -0.975702130f, -0.219101240f,
+ -0.972939952f, -0.231058108f,
+ -0.970031253f, -0.242980180f,
+ -0.966976471f, -0.254865660f,
+ -0.963776066f, -0.266712757f,
+ -0.960430519f, -0.278519689f,
+ -0.956940336f, -0.290284677f,
+ -0.953306040f, -0.302005949f,
+ -0.949528181f, -0.313681740f,
+ -0.945607325f, -0.325310292f,
+ -0.941544065f, -0.336889853f,
+ -0.937339012f, -0.348418680f,
+ -0.932992799f, -0.359895037f,
+ -0.928506080f, -0.371317194f,
+ -0.923879533f, -0.382683432f,
+ -0.919113852f, -0.393992040f,
+ -0.914209756f, -0.405241314f,
+ -0.909167983f, -0.416429560f,
+ -0.903989293f, -0.427555093f,
+ -0.898674466f, -0.438616239f,
+ -0.893224301f, -0.449611330f,
+ -0.887639620f, -0.460538711f,
+ -0.881921264f, -0.471396737f,
+ -0.876070094f, -0.482183772f,
+ -0.870086991f, -0.492898192f,
+ -0.863972856f, -0.503538384f,
+ -0.857728610f, -0.514102744f,
+ -0.851355193f, -0.524589683f,
+ -0.844853565f, -0.534997620f,
+ -0.838224706f, -0.545324988f,
+ -0.831469612f, -0.555570233f,
+ -0.824589303f, -0.565731811f,
+ -0.817584813f, -0.575808191f,
+ -0.810457198f, -0.585797857f,
+ -0.803207531f, -0.595699304f,
+ -0.795836905f, -0.605511041f,
+ -0.788346428f, -0.615231591f,
+ -0.780737229f, -0.624859488f,
+ -0.773010453f, -0.634393284f,
+ -0.765167266f, -0.643831543f,
+ -0.757208847f, -0.653172843f,
+ -0.749136395f, -0.662415778f,
+ -0.740951125f, -0.671558955f,
+ -0.732654272f, -0.680600998f,
+ -0.724247083f, -0.689540545f,
+ -0.715730825f, -0.698376249f,
+ -0.707106781f, -0.707106781f,
+ -0.698376249f, -0.715730825f,
+ -0.689540545f, -0.724247083f,
+ -0.680600998f, -0.732654272f,
+ -0.671558955f, -0.740951125f,
+ -0.662415778f, -0.749136395f,
+ -0.653172843f, -0.757208847f,
+ -0.643831543f, -0.765167266f,
+ -0.634393284f, -0.773010453f,
+ -0.624859488f, -0.780737229f,
+ -0.615231591f, -0.788346428f,
+ -0.605511041f, -0.795836905f,
+ -0.595699304f, -0.803207531f,
+ -0.585797857f, -0.810457198f,
+ -0.575808191f, -0.817584813f,
+ -0.565731811f, -0.824589303f,
+ -0.555570233f, -0.831469612f,
+ -0.545324988f, -0.838224706f,
+ -0.534997620f, -0.844853565f,
+ -0.524589683f, -0.851355193f,
+ -0.514102744f, -0.857728610f,
+ -0.503538384f, -0.863972856f,
+ -0.492898192f, -0.870086991f,
+ -0.482183772f, -0.876070094f,
+ -0.471396737f, -0.881921264f,
+ -0.460538711f, -0.887639620f,
+ -0.449611330f, -0.893224301f,
+ -0.438616239f, -0.898674466f,
+ -0.427555093f, -0.903989293f,
+ -0.416429560f, -0.909167983f,
+ -0.405241314f, -0.914209756f,
+ -0.393992040f, -0.919113852f,
+ -0.382683432f, -0.923879533f,
+ -0.371317194f, -0.928506080f,
+ -0.359895037f, -0.932992799f,
+ -0.348418680f, -0.937339012f,
+ -0.336889853f, -0.941544065f,
+ -0.325310292f, -0.945607325f,
+ -0.313681740f, -0.949528181f,
+ -0.302005949f, -0.953306040f,
+ -0.290284677f, -0.956940336f,
+ -0.278519689f, -0.960430519f,
+ -0.266712757f, -0.963776066f,
+ -0.254865660f, -0.966976471f,
+ -0.242980180f, -0.970031253f,
+ -0.231058108f, -0.972939952f,
+ -0.219101240f, -0.975702130f,
+ -0.207111376f, -0.978317371f,
+ -0.195090322f, -0.980785280f,
+ -0.183039888f, -0.983105487f,
+ -0.170961889f, -0.985277642f,
+ -0.158858143f, -0.987301418f,
+ -0.146730474f, -0.989176510f,
+ -0.134580709f, -0.990902635f,
+ -0.122410675f, -0.992479535f,
+ -0.110222207f, -0.993906970f,
+ -0.098017140f, -0.995184727f,
+ -0.085797312f, -0.996312612f,
+ -0.073564564f, -0.997290457f,
+ -0.061320736f, -0.998118113f,
+ -0.049067674f, -0.998795456f,
+ -0.036807223f, -0.999322385f,
+ -0.024541229f, -0.999698819f,
+ -0.012271538f, -0.999924702f,
+ -0.000000000f, -1.000000000f,
+ 0.012271538f, -0.999924702f,
+ 0.024541229f, -0.999698819f,
+ 0.036807223f, -0.999322385f,
+ 0.049067674f, -0.998795456f,
+ 0.061320736f, -0.998118113f,
+ 0.073564564f, -0.997290457f,
+ 0.085797312f, -0.996312612f,
+ 0.098017140f, -0.995184727f,
+ 0.110222207f, -0.993906970f,
+ 0.122410675f, -0.992479535f,
+ 0.134580709f, -0.990902635f,
+ 0.146730474f, -0.989176510f,
+ 0.158858143f, -0.987301418f,
+ 0.170961889f, -0.985277642f,
+ 0.183039888f, -0.983105487f,
+ 0.195090322f, -0.980785280f,
+ 0.207111376f, -0.978317371f,
+ 0.219101240f, -0.975702130f,
+ 0.231058108f, -0.972939952f,
+ 0.242980180f, -0.970031253f,
+ 0.254865660f, -0.966976471f,
+ 0.266712757f, -0.963776066f,
+ 0.278519689f, -0.960430519f,
+ 0.290284677f, -0.956940336f,
+ 0.302005949f, -0.953306040f,
+ 0.313681740f, -0.949528181f,
+ 0.325310292f, -0.945607325f,
+ 0.336889853f, -0.941544065f,
+ 0.348418680f, -0.937339012f,
+ 0.359895037f, -0.932992799f,
+ 0.371317194f, -0.928506080f,
+ 0.382683432f, -0.923879533f,
+ 0.393992040f, -0.919113852f,
+ 0.405241314f, -0.914209756f,
+ 0.416429560f, -0.909167983f,
+ 0.427555093f, -0.903989293f,
+ 0.438616239f, -0.898674466f,
+ 0.449611330f, -0.893224301f,
+ 0.460538711f, -0.887639620f,
+ 0.471396737f, -0.881921264f,
+ 0.482183772f, -0.876070094f,
+ 0.492898192f, -0.870086991f,
+ 0.503538384f, -0.863972856f,
+ 0.514102744f, -0.857728610f,
+ 0.524589683f, -0.851355193f,
+ 0.534997620f, -0.844853565f,
+ 0.545324988f, -0.838224706f,
+ 0.555570233f, -0.831469612f,
+ 0.565731811f, -0.824589303f,
+ 0.575808191f, -0.817584813f,
+ 0.585797857f, -0.810457198f,
+ 0.595699304f, -0.803207531f,
+ 0.605511041f, -0.795836905f,
+ 0.615231591f, -0.788346428f,
+ 0.624859488f, -0.780737229f,
+ 0.634393284f, -0.773010453f,
+ 0.643831543f, -0.765167266f,
+ 0.653172843f, -0.757208847f,
+ 0.662415778f, -0.749136395f,
+ 0.671558955f, -0.740951125f,
+ 0.680600998f, -0.732654272f,
+ 0.689540545f, -0.724247083f,
+ 0.698376249f, -0.715730825f,
+ 0.707106781f, -0.707106781f,
+ 0.715730825f, -0.698376249f,
+ 0.724247083f, -0.689540545f,
+ 0.732654272f, -0.680600998f,
+ 0.740951125f, -0.671558955f,
+ 0.749136395f, -0.662415778f,
+ 0.757208847f, -0.653172843f,
+ 0.765167266f, -0.643831543f,
+ 0.773010453f, -0.634393284f,
+ 0.780737229f, -0.624859488f,
+ 0.788346428f, -0.615231591f,
+ 0.795836905f, -0.605511041f,
+ 0.803207531f, -0.595699304f,
+ 0.810457198f, -0.585797857f,
+ 0.817584813f, -0.575808191f,
+ 0.824589303f, -0.565731811f,
+ 0.831469612f, -0.555570233f,
+ 0.838224706f, -0.545324988f,
+ 0.844853565f, -0.534997620f,
+ 0.851355193f, -0.524589683f,
+ 0.857728610f, -0.514102744f,
+ 0.863972856f, -0.503538384f,
+ 0.870086991f, -0.492898192f,
+ 0.876070094f, -0.482183772f,
+ 0.881921264f, -0.471396737f,
+ 0.887639620f, -0.460538711f,
+ 0.893224301f, -0.449611330f,
+ 0.898674466f, -0.438616239f,
+ 0.903989293f, -0.427555093f,
+ 0.909167983f, -0.416429560f,
+ 0.914209756f, -0.405241314f,
+ 0.919113852f, -0.393992040f,
+ 0.923879533f, -0.382683432f,
+ 0.928506080f, -0.371317194f,
+ 0.932992799f, -0.359895037f,
+ 0.937339012f, -0.348418680f,
+ 0.941544065f, -0.336889853f,
+ 0.945607325f, -0.325310292f,
+ 0.949528181f, -0.313681740f,
+ 0.953306040f, -0.302005949f,
+ 0.956940336f, -0.290284677f,
+ 0.960430519f, -0.278519689f,
+ 0.963776066f, -0.266712757f,
+ 0.966976471f, -0.254865660f,
+ 0.970031253f, -0.242980180f,
+ 0.972939952f, -0.231058108f,
+ 0.975702130f, -0.219101240f,
+ 0.978317371f, -0.207111376f,
+ 0.980785280f, -0.195090322f,
+ 0.983105487f, -0.183039888f,
+ 0.985277642f, -0.170961889f,
+ 0.987301418f, -0.158858143f,
+ 0.989176510f, -0.146730474f,
+ 0.990902635f, -0.134580709f,
+ 0.992479535f, -0.122410675f,
+ 0.993906970f, -0.110222207f,
+ 0.995184727f, -0.098017140f,
+ 0.996312612f, -0.085797312f,
+ 0.997290457f, -0.073564564f,
+ 0.998118113f, -0.061320736f,
+ 0.998795456f, -0.049067674f,
+ 0.999322385f, -0.036807223f,
+ 0.999698819f, -0.024541229f,
+ 0.999924702f, -0.012271538f
+};
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_1024[2048] = {
+1.000000000f , 0.000000000f ,
+0.999981175f , 0.006135885f ,
+0.999924702f , 0.012271538f ,
+0.999830582f , 0.018406730f ,
+0.999698819f , 0.024541229f ,
+0.999529418f , 0.030674803f ,
+0.999322385f , 0.036807223f ,
+0.999077728f , 0.042938257f ,
+0.998795456f , 0.049067674f ,
+0.998475581f , 0.055195244f ,
+0.998118113f , 0.061320736f ,
+0.997723067f , 0.067443920f ,
+0.997290457f , 0.073564564f ,
+0.996820299f , 0.079682438f ,
+0.996312612f , 0.085797312f ,
+0.995767414f , 0.091908956f ,
+0.995184727f , 0.098017140f ,
+0.994564571f , 0.104121634f ,
+0.993906970f , 0.110222207f ,
+0.993211949f , 0.116318631f ,
+0.992479535f , 0.122410675f ,
+0.991709754f , 0.128498111f ,
+0.990902635f , 0.134580709f ,
+0.990058210f , 0.140658239f ,
+0.989176510f , 0.146730474f ,
+0.988257568f , 0.152797185f ,
+0.987301418f , 0.158858143f ,
+0.986308097f , 0.164913120f ,
+0.985277642f , 0.170961889f ,
+0.984210092f , 0.177004220f ,
+0.983105487f , 0.183039888f ,
+0.981963869f , 0.189068664f ,
+0.980785280f , 0.195090322f ,
+0.979569766f , 0.201104635f ,
+0.978317371f , 0.207111376f ,
+0.977028143f , 0.213110320f ,
+0.975702130f , 0.219101240f ,
+0.974339383f , 0.225083911f ,
+0.972939952f , 0.231058108f ,
+0.971503891f , 0.237023606f ,
+0.970031253f , 0.242980180f ,
+0.968522094f , 0.248927606f ,
+0.966976471f , 0.254865660f ,
+0.965394442f , 0.260794118f ,
+0.963776066f , 0.266712757f ,
+0.962121404f , 0.272621355f ,
+0.960430519f , 0.278519689f ,
+0.958703475f , 0.284407537f ,
+0.956940336f , 0.290284677f ,
+0.955141168f , 0.296150888f ,
+0.953306040f , 0.302005949f ,
+0.951435021f , 0.307849640f ,
+0.949528181f , 0.313681740f ,
+0.947585591f , 0.319502031f ,
+0.945607325f , 0.325310292f ,
+0.943593458f , 0.331106306f ,
+0.941544065f , 0.336889853f ,
+0.939459224f , 0.342660717f ,
+0.937339012f , 0.348418680f ,
+0.935183510f , 0.354163525f ,
+0.932992799f , 0.359895037f ,
+0.930766961f , 0.365612998f ,
+0.928506080f , 0.371317194f ,
+0.926210242f , 0.377007410f ,
+0.923879533f , 0.382683432f ,
+0.921514039f , 0.388345047f ,
+0.919113852f , 0.393992040f ,
+0.916679060f , 0.399624200f ,
+0.914209756f , 0.405241314f ,
+0.911706032f , 0.410843171f ,
+0.909167983f , 0.416429560f ,
+0.906595705f , 0.422000271f ,
+0.903989293f , 0.427555093f ,
+0.901348847f , 0.433093819f ,
+0.898674466f , 0.438616239f ,
+0.895966250f , 0.444122145f ,
+0.893224301f , 0.449611330f ,
+0.890448723f , 0.455083587f ,
+0.887639620f , 0.460538711f ,
+0.884797098f , 0.465976496f ,
+0.881921264f , 0.471396737f ,
+0.879012226f , 0.476799230f ,
+0.876070094f , 0.482183772f ,
+0.873094978f , 0.487550160f ,
+0.870086991f , 0.492898192f ,
+0.867046246f , 0.498227667f ,
+0.863972856f , 0.503538384f ,
+0.860866939f , 0.508830143f ,
+0.857728610f , 0.514102744f ,
+0.854557988f , 0.519355990f ,
+0.851355193f , 0.524589683f ,
+0.848120345f , 0.529803625f ,
+0.844853565f , 0.534997620f ,
+0.841554977f , 0.540171473f ,
+0.838224706f , 0.545324988f ,
+0.834862875f , 0.550457973f ,
+0.831469612f , 0.555570233f ,
+0.828045045f , 0.560661576f ,
+0.824589303f , 0.565731811f ,
+0.821102515f , 0.570780746f ,
+0.817584813f , 0.575808191f ,
+0.814036330f , 0.580813958f ,
+0.810457198f , 0.585797857f ,
+0.806847554f , 0.590759702f ,
+0.803207531f , 0.595699304f ,
+0.799537269f , 0.600616479f ,
+0.795836905f , 0.605511041f ,
+0.792106577f , 0.610382806f ,
+0.788346428f , 0.615231591f ,
+0.784556597f , 0.620057212f ,
+0.780737229f , 0.624859488f ,
+0.776888466f , 0.629638239f ,
+0.773010453f , 0.634393284f ,
+0.769103338f , 0.639124445f ,
+0.765167266f , 0.643831543f ,
+0.761202385f , 0.648514401f ,
+0.757208847f , 0.653172843f ,
+0.753186799f , 0.657806693f ,
+0.749136395f , 0.662415778f ,
+0.745057785f , 0.666999922f ,
+0.740951125f , 0.671558955f ,
+0.736816569f , 0.676092704f ,
+0.732654272f , 0.680600998f ,
+0.728464390f , 0.685083668f ,
+0.724247083f , 0.689540545f ,
+0.720002508f , 0.693971461f ,
+0.715730825f , 0.698376249f ,
+0.711432196f , 0.702754744f ,
+0.707106781f , 0.707106781f ,
+0.702754744f , 0.711432196f ,
+0.698376249f , 0.715730825f ,
+0.693971461f , 0.720002508f ,
+0.689540545f , 0.724247083f ,
+0.685083668f , 0.728464390f ,
+0.680600998f , 0.732654272f ,
+0.676092704f , 0.736816569f ,
+0.671558955f , 0.740951125f ,
+0.666999922f , 0.745057785f ,
+0.662415778f , 0.749136395f ,
+0.657806693f , 0.753186799f ,
+0.653172843f , 0.757208847f ,
+0.648514401f , 0.761202385f ,
+0.643831543f , 0.765167266f ,
+0.639124445f , 0.769103338f ,
+0.634393284f , 0.773010453f ,
+0.629638239f , 0.776888466f ,
+0.624859488f , 0.780737229f ,
+0.620057212f , 0.784556597f ,
+0.615231591f , 0.788346428f ,
+0.610382806f , 0.792106577f ,
+0.605511041f , 0.795836905f ,
+0.600616479f , 0.799537269f ,
+0.595699304f , 0.803207531f ,
+0.590759702f , 0.806847554f ,
+0.585797857f , 0.810457198f ,
+0.580813958f , 0.814036330f ,
+0.575808191f , 0.817584813f ,
+0.570780746f , 0.821102515f ,
+0.565731811f , 0.824589303f ,
+0.560661576f , 0.828045045f ,
+0.555570233f , 0.831469612f ,
+0.550457973f , 0.834862875f ,
+0.545324988f , 0.838224706f ,
+0.540171473f , 0.841554977f ,
+0.534997620f , 0.844853565f ,
+0.529803625f , 0.848120345f ,
+0.524589683f , 0.851355193f ,
+0.519355990f , 0.854557988f ,
+0.514102744f , 0.857728610f ,
+0.508830143f , 0.860866939f ,
+0.503538384f , 0.863972856f ,
+0.498227667f , 0.867046246f ,
+0.492898192f , 0.870086991f ,
+0.487550160f , 0.873094978f ,
+0.482183772f , 0.876070094f ,
+0.476799230f , 0.879012226f ,
+0.471396737f , 0.881921264f ,
+0.465976496f , 0.884797098f ,
+0.460538711f , 0.887639620f ,
+0.455083587f , 0.890448723f ,
+0.449611330f , 0.893224301f ,
+0.444122145f , 0.895966250f ,
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+0.999698819f , -0.024541229f ,
+0.999830582f , -0.018406730f ,
+0.999924702f , -0.012271538f ,
+0.999981175f , -0.006135885f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_2048[4096] = {
+ 1.000000000f, 0.000000000f,
+ 0.999995294f, 0.003067957f,
+ 0.999981175f, 0.006135885f,
+ 0.999957645f, 0.009203755f,
+ 0.999924702f, 0.012271538f,
+ 0.999882347f, 0.015339206f,
+ 0.999830582f, 0.018406730f,
+ 0.999769405f, 0.021474080f,
+ 0.999698819f, 0.024541229f,
+ 0.999618822f, 0.027608146f,
+ 0.999529418f, 0.030674803f,
+ 0.999430605f, 0.033741172f,
+ 0.999322385f, 0.036807223f,
+ 0.999204759f, 0.039872928f,
+ 0.999077728f, 0.042938257f,
+ 0.998941293f, 0.046003182f,
+ 0.998795456f, 0.049067674f,
+ 0.998640218f, 0.052131705f,
+ 0.998475581f, 0.055195244f,
+ 0.998301545f, 0.058258265f,
+ 0.998118113f, 0.061320736f,
+ 0.997925286f, 0.064382631f,
+ 0.997723067f, 0.067443920f,
+ 0.997511456f, 0.070504573f,
+ 0.997290457f, 0.073564564f,
+ 0.997060070f, 0.076623861f,
+ 0.996820299f, 0.079682438f,
+ 0.996571146f, 0.082740265f,
+ 0.996312612f, 0.085797312f,
+ 0.996044701f, 0.088853553f,
+ 0.995767414f, 0.091908956f,
+ 0.995480755f, 0.094963495f,
+ 0.995184727f, 0.098017140f,
+ 0.994879331f, 0.101069863f,
+ 0.994564571f, 0.104121634f,
+ 0.994240449f, 0.107172425f,
+ 0.993906970f, 0.110222207f,
+ 0.993564136f, 0.113270952f,
+ 0.993211949f, 0.116318631f,
+ 0.992850414f, 0.119365215f,
+ 0.992479535f, 0.122410675f,
+ 0.992099313f, 0.125454983f,
+ 0.991709754f, 0.128498111f,
+ 0.991310860f, 0.131540029f,
+ 0.990902635f, 0.134580709f,
+ 0.990485084f, 0.137620122f,
+ 0.990058210f, 0.140658239f,
+ 0.989622017f, 0.143695033f,
+ 0.989176510f, 0.146730474f,
+ 0.988721692f, 0.149764535f,
+ 0.988257568f, 0.152797185f,
+ 0.987784142f, 0.155828398f,
+ 0.987301418f, 0.158858143f,
+ 0.986809402f, 0.161886394f,
+ 0.986308097f, 0.164913120f,
+ 0.985797509f, 0.167938295f,
+ 0.985277642f, 0.170961889f,
+ 0.984748502f, 0.173983873f,
+ 0.984210092f, 0.177004220f,
+ 0.983662419f, 0.180022901f,
+ 0.983105487f, 0.183039888f,
+ 0.982539302f, 0.186055152f,
+ 0.981963869f, 0.189068664f,
+ 0.981379193f, 0.192080397f,
+ 0.980785280f, 0.195090322f,
+ 0.980182136f, 0.198098411f,
+ 0.979569766f, 0.201104635f,
+ 0.978948175f, 0.204108966f,
+ 0.978317371f, 0.207111376f,
+ 0.977677358f, 0.210111837f,
+ 0.977028143f, 0.213110320f,
+ 0.976369731f, 0.216106797f,
+ 0.975702130f, 0.219101240f,
+ 0.975025345f, 0.222093621f,
+ 0.974339383f, 0.225083911f,
+ 0.973644250f, 0.228072083f,
+ 0.972939952f, 0.231058108f,
+ 0.972226497f, 0.234041959f,
+ 0.971503891f, 0.237023606f,
+ 0.970772141f, 0.240003022f,
+ 0.970031253f, 0.242980180f,
+ 0.969281235f, 0.245955050f,
+ 0.968522094f, 0.248927606f,
+ 0.967753837f, 0.251897818f,
+ 0.966976471f, 0.254865660f,
+ 0.966190003f, 0.257831102f,
+ 0.965394442f, 0.260794118f,
+ 0.964589793f, 0.263754679f,
+ 0.963776066f, 0.266712757f,
+ 0.962953267f, 0.269668326f,
+ 0.962121404f, 0.272621355f,
+ 0.961280486f, 0.275571819f,
+ 0.960430519f, 0.278519689f,
+ 0.959571513f, 0.281464938f,
+ 0.958703475f, 0.284407537f,
+ 0.957826413f, 0.287347460f,
+ 0.956940336f, 0.290284677f,
+ 0.956045251f, 0.293219163f,
+ 0.955141168f, 0.296150888f,
+ 0.954228095f, 0.299079826f,
+ 0.953306040f, 0.302005949f,
+ 0.952375013f, 0.304929230f,
+ 0.951435021f, 0.307849640f,
+ 0.950486074f, 0.310767153f,
+ 0.949528181f, 0.313681740f,
+ 0.948561350f, 0.316593376f,
+ 0.947585591f, 0.319502031f,
+ 0.946600913f, 0.322407679f,
+ 0.945607325f, 0.325310292f,
+ 0.944604837f, 0.328209844f,
+ 0.943593458f, 0.331106306f,
+ 0.942573198f, 0.333999651f,
+ 0.941544065f, 0.336889853f,
+ 0.940506071f, 0.339776884f,
+ 0.939459224f, 0.342660717f,
+ 0.938403534f, 0.345541325f,
+ 0.937339012f, 0.348418680f,
+ 0.936265667f, 0.351292756f,
+ 0.935183510f, 0.354163525f,
+ 0.934092550f, 0.357030961f,
+ 0.932992799f, 0.359895037f,
+ 0.931884266f, 0.362755724f,
+ 0.930766961f, 0.365612998f,
+ 0.929640896f, 0.368466830f,
+ 0.928506080f, 0.371317194f,
+ 0.927362526f, 0.374164063f,
+ 0.926210242f, 0.377007410f,
+ 0.925049241f, 0.379847209f,
+ 0.923879533f, 0.382683432f,
+ 0.922701128f, 0.385516054f,
+ 0.921514039f, 0.388345047f,
+ 0.920318277f, 0.391170384f,
+ 0.919113852f, 0.393992040f,
+ 0.917900776f, 0.396809987f,
+ 0.916679060f, 0.399624200f,
+ 0.915448716f, 0.402434651f,
+ 0.914209756f, 0.405241314f,
+ 0.912962190f, 0.408044163f,
+ 0.911706032f, 0.410843171f,
+ 0.910441292f, 0.413638312f,
+ 0.909167983f, 0.416429560f,
+ 0.907886116f, 0.419216888f,
+ 0.906595705f, 0.422000271f,
+ 0.905296759f, 0.424779681f,
+ 0.903989293f, 0.427555093f,
+ 0.902673318f, 0.430326481f,
+ 0.901348847f, 0.433093819f,
+ 0.900015892f, 0.435857080f,
+ 0.898674466f, 0.438616239f,
+ 0.897324581f, 0.441371269f,
+ 0.895966250f, 0.444122145f,
+ 0.894599486f, 0.446868840f,
+ 0.893224301f, 0.449611330f,
+ 0.891840709f, 0.452349587f,
+ 0.890448723f, 0.455083587f,
+ 0.889048356f, 0.457813304f,
+ 0.887639620f, 0.460538711f,
+ 0.886222530f, 0.463259784f,
+ 0.884797098f, 0.465976496f,
+ 0.883363339f, 0.468688822f,
+ 0.881921264f, 0.471396737f,
+ 0.880470889f, 0.474100215f,
+ 0.879012226f, 0.476799230f,
+ 0.877545290f, 0.479493758f,
+ 0.876070094f, 0.482183772f,
+ 0.874586652f, 0.484869248f,
+ 0.873094978f, 0.487550160f,
+ 0.871595087f, 0.490226483f,
+ 0.870086991f, 0.492898192f,
+ 0.868570706f, 0.495565262f,
+ 0.867046246f, 0.498227667f,
+ 0.865513624f, 0.500885383f,
+ 0.863972856f, 0.503538384f,
+ 0.862423956f, 0.506186645f,
+ 0.860866939f, 0.508830143f,
+ 0.859301818f, 0.511468850f,
+ 0.857728610f, 0.514102744f,
+ 0.856147328f, 0.516731799f,
+ 0.854557988f, 0.519355990f,
+ 0.852960605f, 0.521975293f,
+ 0.851355193f, 0.524589683f,
+ 0.849741768f, 0.527199135f,
+ 0.848120345f, 0.529803625f,
+ 0.846490939f, 0.532403128f,
+ 0.844853565f, 0.534997620f,
+ 0.843208240f, 0.537587076f,
+ 0.841554977f, 0.540171473f,
+ 0.839893794f, 0.542750785f,
+ 0.838224706f, 0.545324988f,
+ 0.836547727f, 0.547894059f,
+ 0.834862875f, 0.550457973f,
+ 0.833170165f, 0.553016706f,
+ 0.831469612f, 0.555570233f,
+ 0.829761234f, 0.558118531f,
+ 0.828045045f, 0.560661576f,
+ 0.826321063f, 0.563199344f,
+ 0.824589303f, 0.565731811f,
+ 0.822849781f, 0.568258953f,
+ 0.821102515f, 0.570780746f,
+ 0.819347520f, 0.573297167f,
+ 0.817584813f, 0.575808191f,
+ 0.815814411f, 0.578313796f,
+ 0.814036330f, 0.580813958f,
+ 0.812250587f, 0.583308653f,
+ 0.810457198f, 0.585797857f,
+ 0.808656182f, 0.588281548f,
+ 0.806847554f, 0.590759702f,
+ 0.805031331f, 0.593232295f,
+ 0.803207531f, 0.595699304f,
+ 0.801376172f, 0.598160707f,
+ 0.799537269f, 0.600616479f,
+ 0.797690841f, 0.603066599f,
+ 0.795836905f, 0.605511041f,
+ 0.793975478f, 0.607949785f,
+ 0.792106577f, 0.610382806f,
+ 0.790230221f, 0.612810082f,
+ 0.788346428f, 0.615231591f,
+ 0.786455214f, 0.617647308f,
+ 0.784556597f, 0.620057212f,
+ 0.782650596f, 0.622461279f,
+ 0.780737229f, 0.624859488f,
+ 0.778816512f, 0.627251815f,
+ 0.776888466f, 0.629638239f,
+ 0.774953107f, 0.632018736f,
+ 0.773010453f, 0.634393284f,
+ 0.771060524f, 0.636761861f,
+ 0.769103338f, 0.639124445f,
+ 0.767138912f, 0.641481013f,
+ 0.765167266f, 0.643831543f,
+ 0.763188417f, 0.646176013f,
+ 0.761202385f, 0.648514401f,
+ 0.759209189f, 0.650846685f,
+ 0.757208847f, 0.653172843f,
+ 0.755201377f, 0.655492853f,
+ 0.753186799f, 0.657806693f,
+ 0.751165132f, 0.660114342f,
+ 0.749136395f, 0.662415778f,
+ 0.747100606f, 0.664710978f,
+ 0.745057785f, 0.666999922f,
+ 0.743007952f, 0.669282588f,
+ 0.740951125f, 0.671558955f,
+ 0.738887324f, 0.673829000f,
+ 0.736816569f, 0.676092704f,
+ 0.734738878f, 0.678350043f,
+ 0.732654272f, 0.680600998f,
+ 0.730562769f, 0.682845546f,
+ 0.728464390f, 0.685083668f,
+ 0.726359155f, 0.687315341f,
+ 0.724247083f, 0.689540545f,
+ 0.722128194f, 0.691759258f,
+ 0.720002508f, 0.693971461f,
+ 0.717870045f, 0.696177131f,
+ 0.715730825f, 0.698376249f,
+ 0.713584869f, 0.700568794f,
+ 0.711432196f, 0.702754744f,
+ 0.709272826f, 0.704934080f,
+ 0.707106781f, 0.707106781f,
+ 0.704934080f, 0.709272826f,
+ 0.702754744f, 0.711432196f,
+ 0.700568794f, 0.713584869f,
+ 0.698376249f, 0.715730825f,
+ 0.696177131f, 0.717870045f,
+ 0.693971461f, 0.720002508f,
+ 0.691759258f, 0.722128194f,
+ 0.689540545f, 0.724247083f,
+ 0.687315341f, 0.726359155f,
+ 0.685083668f, 0.728464390f,
+ 0.682845546f, 0.730562769f,
+ 0.680600998f, 0.732654272f,
+ 0.678350043f, 0.734738878f,
+ 0.676092704f, 0.736816569f,
+ 0.673829000f, 0.738887324f,
+ 0.671558955f, 0.740951125f,
+ 0.669282588f, 0.743007952f,
+ 0.666999922f, 0.745057785f,
+ 0.664710978f, 0.747100606f,
+ 0.662415778f, 0.749136395f,
+ 0.660114342f, 0.751165132f,
+ 0.657806693f, 0.753186799f,
+ 0.655492853f, 0.755201377f,
+ 0.653172843f, 0.757208847f,
+ 0.650846685f, 0.759209189f,
+ 0.648514401f, 0.761202385f,
+ 0.646176013f, 0.763188417f,
+ 0.643831543f, 0.765167266f,
+ 0.641481013f, 0.767138912f,
+ 0.639124445f, 0.769103338f,
+ 0.636761861f, 0.771060524f,
+ 0.634393284f, 0.773010453f,
+ 0.632018736f, 0.774953107f,
+ 0.629638239f, 0.776888466f,
+ 0.627251815f, 0.778816512f,
+ 0.624859488f, 0.780737229f,
+ 0.622461279f, 0.782650596f,
+ 0.620057212f, 0.784556597f,
+ 0.617647308f, 0.786455214f,
+ 0.615231591f, 0.788346428f,
+ 0.612810082f, 0.790230221f,
+ 0.610382806f, 0.792106577f,
+ 0.607949785f, 0.793975478f,
+ 0.605511041f, 0.795836905f,
+ 0.603066599f, 0.797690841f,
+ 0.600616479f, 0.799537269f,
+ 0.598160707f, 0.801376172f,
+ 0.595699304f, 0.803207531f,
+ 0.593232295f, 0.805031331f,
+ 0.590759702f, 0.806847554f,
+ 0.588281548f, 0.808656182f,
+ 0.585797857f, 0.810457198f,
+ 0.583308653f, 0.812250587f,
+ 0.580813958f, 0.814036330f,
+ 0.578313796f, 0.815814411f,
+ 0.575808191f, 0.817584813f,
+ 0.573297167f, 0.819347520f,
+ 0.570780746f, 0.821102515f,
+ 0.568258953f, 0.822849781f,
+ 0.565731811f, 0.824589303f,
+ 0.563199344f, 0.826321063f,
+ 0.560661576f, 0.828045045f,
+ 0.558118531f, 0.829761234f,
+ 0.555570233f, 0.831469612f,
+ 0.553016706f, 0.833170165f,
+ 0.550457973f, 0.834862875f,
+ 0.547894059f, 0.836547727f,
+ 0.545324988f, 0.838224706f,
+ 0.542750785f, 0.839893794f,
+ 0.540171473f, 0.841554977f,
+ 0.537587076f, 0.843208240f,
+ 0.534997620f, 0.844853565f,
+ 0.532403128f, 0.846490939f,
+ 0.529803625f, 0.848120345f,
+ 0.527199135f, 0.849741768f,
+ 0.524589683f, 0.851355193f,
+ 0.521975293f, 0.852960605f,
+ 0.519355990f, 0.854557988f,
+ 0.516731799f, 0.856147328f,
+ 0.514102744f, 0.857728610f,
+ 0.511468850f, 0.859301818f,
+ 0.508830143f, 0.860866939f,
+ 0.506186645f, 0.862423956f,
+ 0.503538384f, 0.863972856f,
+ 0.500885383f, 0.865513624f,
+ 0.498227667f, 0.867046246f,
+ 0.495565262f, 0.868570706f,
+ 0.492898192f, 0.870086991f,
+ 0.490226483f, 0.871595087f,
+ 0.487550160f, 0.873094978f,
+ 0.484869248f, 0.874586652f,
+ 0.482183772f, 0.876070094f,
+ 0.479493758f, 0.877545290f,
+ 0.476799230f, 0.879012226f,
+ 0.474100215f, 0.880470889f,
+ 0.471396737f, 0.881921264f,
+ 0.468688822f, 0.883363339f,
+ 0.465976496f, 0.884797098f,
+ 0.463259784f, 0.886222530f,
+ 0.460538711f, 0.887639620f,
+ 0.457813304f, 0.889048356f,
+ 0.455083587f, 0.890448723f,
+ 0.452349587f, 0.891840709f,
+ 0.449611330f, 0.893224301f,
+ 0.446868840f, 0.894599486f,
+ 0.444122145f, 0.895966250f,
+ 0.441371269f, 0.897324581f,
+ 0.438616239f, 0.898674466f,
+ 0.435857080f, 0.900015892f,
+ 0.433093819f, 0.901348847f,
+ 0.430326481f, 0.902673318f,
+ 0.427555093f, 0.903989293f,
+ 0.424779681f, 0.905296759f,
+ 0.422000271f, 0.906595705f,
+ 0.419216888f, 0.907886116f,
+ 0.416429560f, 0.909167983f,
+ 0.413638312f, 0.910441292f,
+ 0.410843171f, 0.911706032f,
+ 0.408044163f, 0.912962190f,
+ 0.405241314f, 0.914209756f,
+ 0.402434651f, 0.915448716f,
+ 0.399624200f, 0.916679060f,
+ 0.396809987f, 0.917900776f,
+ 0.393992040f, 0.919113852f,
+ 0.391170384f, 0.920318277f,
+ 0.388345047f, 0.921514039f,
+ 0.385516054f, 0.922701128f,
+ 0.382683432f, 0.923879533f,
+ 0.379847209f, 0.925049241f,
+ 0.377007410f, 0.926210242f,
+ 0.374164063f, 0.927362526f,
+ 0.371317194f, 0.928506080f,
+ 0.368466830f, 0.929640896f,
+ 0.365612998f, 0.930766961f,
+ 0.362755724f, 0.931884266f,
+ 0.359895037f, 0.932992799f,
+ 0.357030961f, 0.934092550f,
+ 0.354163525f, 0.935183510f,
+ 0.351292756f, 0.936265667f,
+ 0.348418680f, 0.937339012f,
+ 0.345541325f, 0.938403534f,
+ 0.342660717f, 0.939459224f,
+ 0.339776884f, 0.940506071f,
+ 0.336889853f, 0.941544065f,
+ 0.333999651f, 0.942573198f,
+ 0.331106306f, 0.943593458f,
+ 0.328209844f, 0.944604837f,
+ 0.325310292f, 0.945607325f,
+ 0.322407679f, 0.946600913f,
+ 0.319502031f, 0.947585591f,
+ 0.316593376f, 0.948561350f,
+ 0.313681740f, 0.949528181f,
+ 0.310767153f, 0.950486074f,
+ 0.307849640f, 0.951435021f,
+ 0.304929230f, 0.952375013f,
+ 0.302005949f, 0.953306040f,
+ 0.299079826f, 0.954228095f,
+ 0.296150888f, 0.955141168f,
+ 0.293219163f, 0.956045251f,
+ 0.290284677f, 0.956940336f,
+ 0.287347460f, 0.957826413f,
+ 0.284407537f, 0.958703475f,
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+ 0.999981175f, -0.006135885f,
+ 0.999995294f, -0.003067957f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_4096[8192] = {
+ 1.000000000f, 0.000000000f,
+ 0.999998823f, 0.001533980f,
+ 0.999995294f, 0.003067957f,
+ 0.999989411f, 0.004601926f,
+ 0.999981175f, 0.006135885f,
+ 0.999970586f, 0.007669829f,
+ 0.999957645f, 0.009203755f,
+ 0.999942350f, 0.010737659f,
+ 0.999924702f, 0.012271538f,
+ 0.999904701f, 0.013805389f,
+ 0.999882347f, 0.015339206f,
+ 0.999857641f, 0.016872988f,
+ 0.999830582f, 0.018406730f,
+ 0.999801170f, 0.019940429f,
+ 0.999769405f, 0.021474080f,
+ 0.999735288f, 0.023007681f,
+ 0.999698819f, 0.024541229f,
+ 0.999659997f, 0.026074718f,
+ 0.999618822f, 0.027608146f,
+ 0.999575296f, 0.029141509f,
+ 0.999529418f, 0.030674803f,
+ 0.999481187f, 0.032208025f,
+ 0.999430605f, 0.033741172f,
+ 0.999377670f, 0.035274239f,
+ 0.999322385f, 0.036807223f,
+ 0.999264747f, 0.038340120f,
+ 0.999204759f, 0.039872928f,
+ 0.999142419f, 0.041405641f,
+ 0.999077728f, 0.042938257f,
+ 0.999010686f, 0.044470772f,
+ 0.998941293f, 0.046003182f,
+ 0.998869550f, 0.047535484f,
+ 0.998795456f, 0.049067674f,
+ 0.998719012f, 0.050599749f,
+ 0.998640218f, 0.052131705f,
+ 0.998559074f, 0.053663538f,
+ 0.998475581f, 0.055195244f,
+ 0.998389737f, 0.056726821f,
+ 0.998301545f, 0.058258265f,
+ 0.998211003f, 0.059789571f,
+ 0.998118113f, 0.061320736f,
+ 0.998022874f, 0.062851758f,
+ 0.997925286f, 0.064382631f,
+ 0.997825350f, 0.065913353f,
+ 0.997723067f, 0.067443920f,
+ 0.997618435f, 0.068974328f,
+ 0.997511456f, 0.070504573f,
+ 0.997402130f, 0.072034653f,
+ 0.997290457f, 0.073564564f,
+ 0.997176437f, 0.075094301f,
+ 0.997060070f, 0.076623861f,
+ 0.996941358f, 0.078153242f,
+ 0.996820299f, 0.079682438f,
+ 0.996696895f, 0.081211447f,
+ 0.996571146f, 0.082740265f,
+ 0.996443051f, 0.084268888f,
+ 0.996312612f, 0.085797312f,
+ 0.996179829f, 0.087325535f,
+ 0.996044701f, 0.088853553f,
+ 0.995907229f, 0.090381361f,
+ 0.995767414f, 0.091908956f,
+ 0.995625256f, 0.093436336f,
+ 0.995480755f, 0.094963495f,
+ 0.995333912f, 0.096490431f,
+ 0.995184727f, 0.098017140f,
+ 0.995033199f, 0.099543619f,
+ 0.994879331f, 0.101069863f,
+ 0.994723121f, 0.102595869f,
+ 0.994564571f, 0.104121634f,
+ 0.994403680f, 0.105647154f,
+ 0.994240449f, 0.107172425f,
+ 0.994074879f, 0.108697444f,
+ 0.993906970f, 0.110222207f,
+ 0.993736722f, 0.111746711f,
+ 0.993564136f, 0.113270952f,
+ 0.993389211f, 0.114794927f,
+ 0.993211949f, 0.116318631f,
+ 0.993032350f, 0.117842062f,
+ 0.992850414f, 0.119365215f,
+ 0.992666142f, 0.120888087f,
+ 0.992479535f, 0.122410675f,
+ 0.992290591f, 0.123932975f,
+ 0.992099313f, 0.125454983f,
+ 0.991905700f, 0.126976696f,
+ 0.991709754f, 0.128498111f,
+ 0.991511473f, 0.130019223f,
+ 0.991310860f, 0.131540029f,
+ 0.991107914f, 0.133060525f,
+ 0.990902635f, 0.134580709f,
+ 0.990695025f, 0.136100575f,
+ 0.990485084f, 0.137620122f,
+ 0.990272812f, 0.139139344f,
+ 0.990058210f, 0.140658239f,
+ 0.989841278f, 0.142176804f,
+ 0.989622017f, 0.143695033f,
+ 0.989400428f, 0.145212925f,
+ 0.989176510f, 0.146730474f,
+ 0.988950265f, 0.148247679f,
+ 0.988721692f, 0.149764535f,
+ 0.988490793f, 0.151281038f,
+ 0.988257568f, 0.152797185f,
+ 0.988022017f, 0.154312973f,
+ 0.987784142f, 0.155828398f,
+ 0.987543942f, 0.157343456f,
+ 0.987301418f, 0.158858143f,
+ 0.987056571f, 0.160372457f,
+ 0.986809402f, 0.161886394f,
+ 0.986559910f, 0.163399949f,
+ 0.986308097f, 0.164913120f,
+ 0.986053963f, 0.166425904f,
+ 0.985797509f, 0.167938295f,
+ 0.985538735f, 0.169450291f,
+ 0.985277642f, 0.170961889f,
+ 0.985014231f, 0.172473084f,
+ 0.984748502f, 0.173983873f,
+ 0.984480455f, 0.175494253f,
+ 0.984210092f, 0.177004220f,
+ 0.983937413f, 0.178513771f,
+ 0.983662419f, 0.180022901f,
+ 0.983385110f, 0.181531608f,
+ 0.983105487f, 0.183039888f,
+ 0.982823551f, 0.184547737f,
+ 0.982539302f, 0.186055152f,
+ 0.982252741f, 0.187562129f,
+ 0.981963869f, 0.189068664f,
+ 0.981672686f, 0.190574755f,
+ 0.981379193f, 0.192080397f,
+ 0.981083391f, 0.193585587f,
+ 0.980785280f, 0.195090322f,
+ 0.980484862f, 0.196594598f,
+ 0.980182136f, 0.198098411f,
+ 0.979877104f, 0.199601758f,
+ 0.979569766f, 0.201104635f,
+ 0.979260123f, 0.202607039f,
+ 0.978948175f, 0.204108966f,
+ 0.978633924f, 0.205610413f,
+ 0.978317371f, 0.207111376f,
+ 0.977998515f, 0.208611852f,
+ 0.977677358f, 0.210111837f,
+ 0.977353900f, 0.211611327f,
+ 0.977028143f, 0.213110320f,
+ 0.976700086f, 0.214608811f,
+ 0.976369731f, 0.216106797f,
+ 0.976037079f, 0.217604275f,
+ 0.975702130f, 0.219101240f,
+ 0.975364885f, 0.220597690f,
+ 0.975025345f, 0.222093621f,
+ 0.974683511f, 0.223589029f,
+ 0.974339383f, 0.225083911f,
+ 0.973992962f, 0.226578264f,
+ 0.973644250f, 0.228072083f,
+ 0.973293246f, 0.229565366f,
+ 0.972939952f, 0.231058108f,
+ 0.972584369f, 0.232550307f,
+ 0.972226497f, 0.234041959f,
+ 0.971866337f, 0.235533059f,
+ 0.971503891f, 0.237023606f,
+ 0.971139158f, 0.238513595f,
+ 0.970772141f, 0.240003022f,
+ 0.970402839f, 0.241491885f,
+ 0.970031253f, 0.242980180f,
+ 0.969657385f, 0.244467903f,
+ 0.969281235f, 0.245955050f,
+ 0.968902805f, 0.247441619f,
+ 0.968522094f, 0.248927606f,
+ 0.968139105f, 0.250413007f,
+ 0.967753837f, 0.251897818f,
+ 0.967366292f, 0.253382037f,
+ 0.966976471f, 0.254865660f,
+ 0.966584374f, 0.256348682f,
+ 0.966190003f, 0.257831102f,
+ 0.965793359f, 0.259312915f,
+ 0.965394442f, 0.260794118f,
+ 0.964993253f, 0.262274707f,
+ 0.964589793f, 0.263754679f,
+ 0.964184064f, 0.265234030f,
+ 0.963776066f, 0.266712757f,
+ 0.963365800f, 0.268190857f,
+ 0.962953267f, 0.269668326f,
+ 0.962538468f, 0.271145160f,
+ 0.962121404f, 0.272621355f,
+ 0.961702077f, 0.274096910f,
+ 0.961280486f, 0.275571819f,
+ 0.960856633f, 0.277046080f,
+ 0.960430519f, 0.278519689f,
+ 0.960002146f, 0.279992643f,
+ 0.959571513f, 0.281464938f,
+ 0.959138622f, 0.282936570f,
+ 0.958703475f, 0.284407537f,
+ 0.958266071f, 0.285877835f,
+ 0.957826413f, 0.287347460f,
+ 0.957384501f, 0.288816408f,
+ 0.956940336f, 0.290284677f,
+ 0.956493919f, 0.291752263f,
+ 0.956045251f, 0.293219163f,
+ 0.955594334f, 0.294685372f,
+ 0.955141168f, 0.296150888f,
+ 0.954685755f, 0.297615707f,
+ 0.954228095f, 0.299079826f,
+ 0.953768190f, 0.300543241f,
+ 0.953306040f, 0.302005949f,
+ 0.952841648f, 0.303467947f,
+ 0.952375013f, 0.304929230f,
+ 0.951906137f, 0.306389795f,
+ 0.951435021f, 0.307849640f,
+ 0.950961666f, 0.309308760f,
+ 0.950486074f, 0.310767153f,
+ 0.950008245f, 0.312224814f,
+ 0.949528181f, 0.313681740f,
+ 0.949045882f, 0.315137929f,
+ 0.948561350f, 0.316593376f,
+ 0.948074586f, 0.318048077f,
+ 0.947585591f, 0.319502031f,
+ 0.947094366f, 0.320955232f,
+ 0.946600913f, 0.322407679f,
+ 0.946105232f, 0.323859367f,
+ 0.945607325f, 0.325310292f,
+ 0.945107193f, 0.326760452f,
+ 0.944604837f, 0.328209844f,
+ 0.944100258f, 0.329658463f,
+ 0.943593458f, 0.331106306f,
+ 0.943084437f, 0.332553370f,
+ 0.942573198f, 0.333999651f,
+ 0.942059740f, 0.335445147f,
+ 0.941544065f, 0.336889853f,
+ 0.941026175f, 0.338333767f,
+ 0.940506071f, 0.339776884f,
+ 0.939983753f, 0.341219202f,
+ 0.939459224f, 0.342660717f,
+ 0.938932484f, 0.344101426f,
+ 0.938403534f, 0.345541325f,
+ 0.937872376f, 0.346980411f,
+ 0.937339012f, 0.348418680f,
+ 0.936803442f, 0.349856130f,
+ 0.936265667f, 0.351292756f,
+ 0.935725689f, 0.352728556f,
+ 0.935183510f, 0.354163525f,
+ 0.934639130f, 0.355597662f,
+ 0.934092550f, 0.357030961f,
+ 0.933543773f, 0.358463421f,
+ 0.932992799f, 0.359895037f,
+ 0.932439629f, 0.361325806f,
+ 0.931884266f, 0.362755724f,
+ 0.931326709f, 0.364184790f,
+ 0.930766961f, 0.365612998f,
+ 0.930205023f, 0.367040346f,
+ 0.929640896f, 0.368466830f,
+ 0.929074581f, 0.369892447f,
+ 0.928506080f, 0.371317194f,
+ 0.927935395f, 0.372741067f,
+ 0.927362526f, 0.374164063f,
+ 0.926787474f, 0.375586178f,
+ 0.926210242f, 0.377007410f,
+ 0.925630831f, 0.378427755f,
+ 0.925049241f, 0.379847209f,
+ 0.924465474f, 0.381265769f,
+ 0.923879533f, 0.382683432f,
+ 0.923291417f, 0.384100195f,
+ 0.922701128f, 0.385516054f,
+ 0.922108669f, 0.386931006f,
+ 0.921514039f, 0.388345047f,
+ 0.920917242f, 0.389758174f,
+ 0.920318277f, 0.391170384f,
+ 0.919717146f, 0.392581674f,
+ 0.919113852f, 0.393992040f,
+ 0.918508394f, 0.395401479f,
+ 0.917900776f, 0.396809987f,
+ 0.917290997f, 0.398217562f,
+ 0.916679060f, 0.399624200f,
+ 0.916064966f, 0.401029897f,
+ 0.915448716f, 0.402434651f,
+ 0.914830312f, 0.403838458f,
+ 0.914209756f, 0.405241314f,
+ 0.913587048f, 0.406643217f,
+ 0.912962190f, 0.408044163f,
+ 0.912335185f, 0.409444149f,
+ 0.911706032f, 0.410843171f,
+ 0.911074734f, 0.412241227f,
+ 0.910441292f, 0.413638312f,
+ 0.909805708f, 0.415034424f,
+ 0.909167983f, 0.416429560f,
+ 0.908528119f, 0.417823716f,
+ 0.907886116f, 0.419216888f,
+ 0.907241978f, 0.420609074f,
+ 0.906595705f, 0.422000271f,
+ 0.905947298f, 0.423390474f,
+ 0.905296759f, 0.424779681f,
+ 0.904644091f, 0.426167889f,
+ 0.903989293f, 0.427555093f,
+ 0.903332368f, 0.428941292f,
+ 0.902673318f, 0.430326481f,
+ 0.902012144f, 0.431710658f,
+ 0.901348847f, 0.433093819f,
+ 0.900683429f, 0.434475961f,
+ 0.900015892f, 0.435857080f,
+ 0.899346237f, 0.437237174f,
+ 0.898674466f, 0.438616239f,
+ 0.898000580f, 0.439994271f,
+ 0.897324581f, 0.441371269f,
+ 0.896646470f, 0.442747228f,
+ 0.895966250f, 0.444122145f,
+ 0.895283921f, 0.445496017f,
+ 0.894599486f, 0.446868840f,
+ 0.893912945f, 0.448240612f,
+ 0.893224301f, 0.449611330f,
+ 0.892533555f, 0.450980989f,
+ 0.891840709f, 0.452349587f,
+ 0.891145765f, 0.453717121f,
+ 0.890448723f, 0.455083587f,
+ 0.889749586f, 0.456448982f,
+ 0.889048356f, 0.457813304f,
+ 0.888345033f, 0.459176548f,
+ 0.887639620f, 0.460538711f,
+ 0.886932119f, 0.461899791f,
+ 0.886222530f, 0.463259784f,
+ 0.885510856f, 0.464618686f,
+ 0.884797098f, 0.465976496f,
+ 0.884081259f, 0.467333209f,
+ 0.883363339f, 0.468688822f,
+ 0.882643340f, 0.470043332f,
+ 0.881921264f, 0.471396737f,
+ 0.881197113f, 0.472749032f,
+ 0.880470889f, 0.474100215f,
+ 0.879742593f, 0.475450282f,
+ 0.879012226f, 0.476799230f,
+ 0.878279792f, 0.478147056f,
+ 0.877545290f, 0.479493758f,
+ 0.876808724f, 0.480839331f,
+ 0.876070094f, 0.482183772f,
+ 0.875329403f, 0.483527079f,
+ 0.874586652f, 0.484869248f,
+ 0.873841843f, 0.486210276f,
+ 0.873094978f, 0.487550160f,
+ 0.872346059f, 0.488888897f,
+ 0.871595087f, 0.490226483f,
+ 0.870842063f, 0.491562916f,
+ 0.870086991f, 0.492898192f,
+ 0.869329871f, 0.494232309f,
+ 0.868570706f, 0.495565262f,
+ 0.867809497f, 0.496897049f,
+ 0.867046246f, 0.498227667f,
+ 0.866280954f, 0.499557113f,
+ 0.865513624f, 0.500885383f,
+ 0.864744258f, 0.502212474f,
+ 0.863972856f, 0.503538384f,
+ 0.863199422f, 0.504863109f,
+ 0.862423956f, 0.506186645f,
+ 0.861646461f, 0.507508991f,
+ 0.860866939f, 0.508830143f,
+ 0.860085390f, 0.510150097f,
+ 0.859301818f, 0.511468850f,
+ 0.858516224f, 0.512786401f,
+ 0.857728610f, 0.514102744f,
+ 0.856938977f, 0.515417878f,
+ 0.856147328f, 0.516731799f,
+ 0.855353665f, 0.518044504f,
+ 0.854557988f, 0.519355990f,
+ 0.853760301f, 0.520666254f,
+ 0.852960605f, 0.521975293f,
+ 0.852158902f, 0.523283103f,
+ 0.851355193f, 0.524589683f,
+ 0.850549481f, 0.525895027f,
+ 0.849741768f, 0.527199135f,
+ 0.848932055f, 0.528502002f,
+ 0.848120345f, 0.529803625f,
+ 0.847306639f, 0.531104001f,
+ 0.846490939f, 0.532403128f,
+ 0.845673247f, 0.533701002f,
+ 0.844853565f, 0.534997620f,
+ 0.844031895f, 0.536292979f,
+ 0.843208240f, 0.537587076f,
+ 0.842382600f, 0.538879909f,
+ 0.841554977f, 0.540171473f,
+ 0.840725375f, 0.541461766f,
+ 0.839893794f, 0.542750785f,
+ 0.839060237f, 0.544038527f,
+ 0.838224706f, 0.545324988f,
+ 0.837387202f, 0.546610167f,
+ 0.836547727f, 0.547894059f,
+ 0.835706284f, 0.549176662f,
+ 0.834862875f, 0.550457973f,
+ 0.834017501f, 0.551737988f,
+ 0.833170165f, 0.553016706f,
+ 0.832320868f, 0.554294121f,
+ 0.831469612f, 0.555570233f,
+ 0.830616400f, 0.556845037f,
+ 0.829761234f, 0.558118531f,
+ 0.828904115f, 0.559390712f,
+ 0.828045045f, 0.560661576f,
+ 0.827184027f, 0.561931121f,
+ 0.826321063f, 0.563199344f,
+ 0.825456154f, 0.564466242f,
+ 0.824589303f, 0.565731811f,
+ 0.823720511f, 0.566996049f,
+ 0.822849781f, 0.568258953f,
+ 0.821977115f, 0.569520519f,
+ 0.821102515f, 0.570780746f,
+ 0.820225983f, 0.572039629f,
+ 0.819347520f, 0.573297167f,
+ 0.818467130f, 0.574553355f,
+ 0.817584813f, 0.575808191f,
+ 0.816700573f, 0.577061673f,
+ 0.815814411f, 0.578313796f,
+ 0.814926329f, 0.579564559f,
+ 0.814036330f, 0.580813958f,
+ 0.813144415f, 0.582061990f,
+ 0.812250587f, 0.583308653f,
+ 0.811354847f, 0.584553943f,
+ 0.810457198f, 0.585797857f,
+ 0.809557642f, 0.587040394f,
+ 0.808656182f, 0.588281548f,
+ 0.807752818f, 0.589521319f,
+ 0.806847554f, 0.590759702f,
+ 0.805940391f, 0.591996695f,
+ 0.805031331f, 0.593232295f,
+ 0.804120377f, 0.594466499f,
+ 0.803207531f, 0.595699304f,
+ 0.802292796f, 0.596930708f,
+ 0.801376172f, 0.598160707f,
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+ 0.999995294f, -0.003067957f,
+ 0.999998823f, -0.001533980f
+};
+
+/*
+* @brief Q31 Twiddle factors Table
+*/
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+
+const q31_t twiddleCoefQ31[6144] = {
+ 0x7fffffff, 0x0, 0x7ffff621, 0x3243f5, 0x7fffd886, 0x6487e3, 0x7fffa72c,
+ 0x96cbc1,
+ 0x7fff6216, 0xc90f88, 0x7fff0943, 0xfb5330, 0x7ffe9cb2, 0x12d96b1,
+ 0x7ffe1c65, 0x15fda03,
+ 0x7ffd885a, 0x1921d20, 0x7ffce093, 0x1c45ffe, 0x7ffc250f, 0x1f6a297,
+ 0x7ffb55ce, 0x228e4e2,
+ 0x7ffa72d1, 0x25b26d7, 0x7ff97c18, 0x28d6870, 0x7ff871a2, 0x2bfa9a4,
+ 0x7ff75370, 0x2f1ea6c,
+ 0x7ff62182, 0x3242abf, 0x7ff4dbd9, 0x3566a96, 0x7ff38274, 0x388a9ea,
+ 0x7ff21553, 0x3bae8b2,
+ 0x7ff09478, 0x3ed26e6, 0x7feeffe1, 0x41f6480, 0x7fed5791, 0x451a177,
+ 0x7feb9b85, 0x483ddc3,
+ 0x7fe9cbc0, 0x4b6195d, 0x7fe7e841, 0x4e8543e, 0x7fe5f108, 0x51a8e5c,
+ 0x7fe3e616, 0x54cc7b1,
+ 0x7fe1c76b, 0x57f0035, 0x7fdf9508, 0x5b137df, 0x7fdd4eec, 0x5e36ea9,
+ 0x7fdaf519, 0x615a48b,
+ 0x7fd8878e, 0x647d97c, 0x7fd6064c, 0x67a0d76, 0x7fd37153, 0x6ac406f,
+ 0x7fd0c8a3, 0x6de7262,
+ 0x7fce0c3e, 0x710a345, 0x7fcb3c23, 0x742d311, 0x7fc85854, 0x77501be,
+ 0x7fc560cf, 0x7a72f45,
+ 0x7fc25596, 0x7d95b9e, 0x7fbf36aa, 0x80b86c2, 0x7fbc040a, 0x83db0a7,
+ 0x7fb8bdb8, 0x86fd947,
+ 0x7fb563b3, 0x8a2009a, 0x7fb1f5fc, 0x8d42699, 0x7fae7495, 0x9064b3a,
+ 0x7faadf7c, 0x9386e78,
+ 0x7fa736b4, 0x96a9049, 0x7fa37a3c, 0x99cb0a7, 0x7f9faa15, 0x9cecf89,
+ 0x7f9bc640, 0xa00ece8,
+ 0x7f97cebd, 0xa3308bd, 0x7f93c38c, 0xa6522fe, 0x7f8fa4b0, 0xa973ba5,
+ 0x7f8b7227, 0xac952aa,
+ 0x7f872bf3, 0xafb6805, 0x7f82d214, 0xb2d7baf, 0x7f7e648c, 0xb5f8d9f,
+ 0x7f79e35a, 0xb919dcf,
+ 0x7f754e80, 0xbc3ac35, 0x7f70a5fe, 0xbf5b8cb, 0x7f6be9d4, 0xc27c389,
+ 0x7f671a05, 0xc59cc68,
+ 0x7f62368f, 0xc8bd35e, 0x7f5d3f75, 0xcbdd865, 0x7f5834b7, 0xcefdb76,
+ 0x7f531655, 0xd21dc87,
+ 0x7f4de451, 0xd53db92, 0x7f489eaa, 0xd85d88f, 0x7f434563, 0xdb7d376,
+ 0x7f3dd87c, 0xde9cc40,
+ 0x7f3857f6, 0xe1bc2e4, 0x7f32c3d1, 0xe4db75b, 0x7f2d1c0e, 0xe7fa99e,
+ 0x7f2760af, 0xeb199a4,
+ 0x7f2191b4, 0xee38766, 0x7f1baf1e, 0xf1572dc, 0x7f15b8ee, 0xf475bff,
+ 0x7f0faf25, 0xf7942c7,
+ 0x7f0991c4, 0xfab272b, 0x7f0360cb, 0xfdd0926, 0x7efd1c3c, 0x100ee8ad,
+ 0x7ef6c418, 0x1040c5bb,
+ 0x7ef05860, 0x1072a048, 0x7ee9d914, 0x10a4784b, 0x7ee34636, 0x10d64dbd,
+ 0x7edc9fc6, 0x11082096,
+ 0x7ed5e5c6, 0x1139f0cf, 0x7ecf1837, 0x116bbe60, 0x7ec8371a, 0x119d8941,
+ 0x7ec14270, 0x11cf516a,
+ 0x7eba3a39, 0x120116d5, 0x7eb31e78, 0x1232d979, 0x7eabef2c, 0x1264994e,
+ 0x7ea4ac58, 0x1296564d,
+ 0x7e9d55fc, 0x12c8106f, 0x7e95ec1a, 0x12f9c7aa, 0x7e8e6eb2, 0x132b7bf9,
+ 0x7e86ddc6, 0x135d2d53,
+ 0x7e7f3957, 0x138edbb1, 0x7e778166, 0x13c0870a, 0x7e6fb5f4, 0x13f22f58,
+ 0x7e67d703, 0x1423d492,
+ 0x7e5fe493, 0x145576b1, 0x7e57dea7, 0x148715ae, 0x7e4fc53e, 0x14b8b17f,
+ 0x7e47985b, 0x14ea4a1f,
+ 0x7e3f57ff, 0x151bdf86, 0x7e37042a, 0x154d71aa, 0x7e2e9cdf, 0x157f0086,
+ 0x7e26221f, 0x15b08c12,
+ 0x7e1d93ea, 0x15e21445, 0x7e14f242, 0x16139918, 0x7e0c3d29, 0x16451a83,
+ 0x7e0374a0, 0x1676987f,
+ 0x7dfa98a8, 0x16a81305, 0x7df1a942, 0x16d98a0c, 0x7de8a670, 0x170afd8d,
+ 0x7ddf9034, 0x173c6d80,
+ 0x7dd6668f, 0x176dd9de, 0x7dcd2981, 0x179f429f, 0x7dc3d90d, 0x17d0a7bc,
+ 0x7dba7534, 0x1802092c,
+ 0x7db0fdf8, 0x183366e9, 0x7da77359, 0x1864c0ea, 0x7d9dd55a, 0x18961728,
+ 0x7d9423fc, 0x18c7699b,
+ 0x7d8a5f40, 0x18f8b83c, 0x7d808728, 0x192a0304, 0x7d769bb5, 0x195b49ea,
+ 0x7d6c9ce9, 0x198c8ce7,
+ 0x7d628ac6, 0x19bdcbf3, 0x7d58654d, 0x19ef0707, 0x7d4e2c7f, 0x1a203e1b,
+ 0x7d43e05e, 0x1a517128,
+ 0x7d3980ec, 0x1a82a026, 0x7d2f0e2b, 0x1ab3cb0d, 0x7d24881b, 0x1ae4f1d6,
+ 0x7d19eebf, 0x1b161479,
+ 0x7d0f4218, 0x1b4732ef, 0x7d048228, 0x1b784d30, 0x7cf9aef0, 0x1ba96335,
+ 0x7ceec873, 0x1bda74f6,
+ 0x7ce3ceb2, 0x1c0b826a, 0x7cd8c1ae, 0x1c3c8b8c, 0x7ccda169, 0x1c6d9053,
+ 0x7cc26de5, 0x1c9e90b8,
+ 0x7cb72724, 0x1ccf8cb3, 0x7cabcd28, 0x1d00843d, 0x7ca05ff1, 0x1d31774d,
+ 0x7c94df83, 0x1d6265dd,
+ 0x7c894bde, 0x1d934fe5, 0x7c7da505, 0x1dc4355e, 0x7c71eaf9, 0x1df5163f,
+ 0x7c661dbc, 0x1e25f282,
+ 0x7c5a3d50, 0x1e56ca1e, 0x7c4e49b7, 0x1e879d0d, 0x7c4242f2, 0x1eb86b46,
+ 0x7c362904, 0x1ee934c3,
+ 0x7c29fbee, 0x1f19f97b, 0x7c1dbbb3, 0x1f4ab968, 0x7c116853, 0x1f7b7481,
+ 0x7c0501d2, 0x1fac2abf,
+ 0x7bf88830, 0x1fdcdc1b, 0x7bebfb70, 0x200d888d, 0x7bdf5b94, 0x203e300d,
+ 0x7bd2a89e, 0x206ed295,
+ 0x7bc5e290, 0x209f701c, 0x7bb9096b, 0x20d0089c, 0x7bac1d31, 0x21009c0c,
+ 0x7b9f1de6, 0x21312a65,
+ 0x7b920b89, 0x2161b3a0, 0x7b84e61f, 0x219237b5, 0x7b77ada8, 0x21c2b69c,
+ 0x7b6a6227, 0x21f3304f,
+ 0x7b5d039e, 0x2223a4c5, 0x7b4f920e, 0x225413f8, 0x7b420d7a, 0x22847de0,
+ 0x7b3475e5, 0x22b4e274,
+ 0x7b26cb4f, 0x22e541af, 0x7b190dbc, 0x23159b88, 0x7b0b3d2c, 0x2345eff8,
+ 0x7afd59a4, 0x23763ef7,
+ 0x7aef6323, 0x23a6887f, 0x7ae159ae, 0x23d6cc87, 0x7ad33d45, 0x24070b08,
+ 0x7ac50dec, 0x243743fa,
+ 0x7ab6cba4, 0x24677758, 0x7aa8766f, 0x2497a517, 0x7a9a0e50, 0x24c7cd33,
+ 0x7a8b9348, 0x24f7efa2,
+ 0x7a7d055b, 0x25280c5e, 0x7a6e648a, 0x2558235f, 0x7a5fb0d8, 0x2588349d,
+ 0x7a50ea47, 0x25b84012,
+ 0x7a4210d8, 0x25e845b6, 0x7a332490, 0x26184581, 0x7a24256f, 0x26483f6c,
+ 0x7a151378, 0x26783370,
+ 0x7a05eead, 0x26a82186, 0x79f6b711, 0x26d809a5, 0x79e76ca7, 0x2707ebc7,
+ 0x79d80f6f, 0x2737c7e3,
+ 0x79c89f6e, 0x27679df4, 0x79b91ca4, 0x27976df1, 0x79a98715, 0x27c737d3,
+ 0x7999dec4, 0x27f6fb92,
+ 0x798a23b1, 0x2826b928, 0x797a55e0, 0x2856708d, 0x796a7554, 0x288621b9,
+ 0x795a820e, 0x28b5cca5,
+ 0x794a7c12, 0x28e5714b, 0x793a6361, 0x29150fa1, 0x792a37fe, 0x2944a7a2,
+ 0x7919f9ec, 0x29743946,
+ 0x7909a92d, 0x29a3c485, 0x78f945c3, 0x29d34958, 0x78e8cfb2, 0x2a02c7b8,
+ 0x78d846fb, 0x2a323f9e,
+ 0x78c7aba2, 0x2a61b101, 0x78b6fda8, 0x2a911bdc, 0x78a63d11, 0x2ac08026,
+ 0x789569df, 0x2aefddd8,
+ 0x78848414, 0x2b1f34eb, 0x78738bb3, 0x2b4e8558, 0x786280bf, 0x2b7dcf17,
+ 0x7851633b, 0x2bad1221,
+ 0x78403329, 0x2bdc4e6f, 0x782ef08b, 0x2c0b83fa, 0x781d9b65, 0x2c3ab2b9,
+ 0x780c33b8, 0x2c69daa6,
+ 0x77fab989, 0x2c98fbba, 0x77e92cd9, 0x2cc815ee, 0x77d78daa, 0x2cf72939,
+ 0x77c5dc01, 0x2d263596,
+ 0x77b417df, 0x2d553afc, 0x77a24148, 0x2d843964, 0x7790583e, 0x2db330c7,
+ 0x777e5cc3, 0x2de2211e,
+ 0x776c4edb, 0x2e110a62, 0x775a2e89, 0x2e3fec8b, 0x7747fbce, 0x2e6ec792,
+ 0x7735b6af, 0x2e9d9b70,
+ 0x77235f2d, 0x2ecc681e, 0x7710f54c, 0x2efb2d95, 0x76fe790e, 0x2f29ebcc,
+ 0x76ebea77, 0x2f58a2be,
+ 0x76d94989, 0x2f875262, 0x76c69647, 0x2fb5fab2, 0x76b3d0b4, 0x2fe49ba7,
+ 0x76a0f8d2, 0x30133539,
+ 0x768e0ea6, 0x3041c761, 0x767b1231, 0x30705217, 0x76680376, 0x309ed556,
+ 0x7654e279, 0x30cd5115,
+ 0x7641af3d, 0x30fbc54d, 0x762e69c4, 0x312a31f8, 0x761b1211, 0x3158970e,
+ 0x7607a828, 0x3186f487,
+ 0x75f42c0b, 0x31b54a5e, 0x75e09dbd, 0x31e39889, 0x75ccfd42, 0x3211df04,
+ 0x75b94a9c, 0x32401dc6,
+ 0x75a585cf, 0x326e54c7, 0x7591aedd, 0x329c8402, 0x757dc5ca, 0x32caab6f,
+ 0x7569ca99, 0x32f8cb07,
+ 0x7555bd4c, 0x3326e2c3, 0x75419de7, 0x3354f29b, 0x752d6c6c, 0x3382fa88,
+ 0x751928e0, 0x33b0fa84,
+ 0x7504d345, 0x33def287, 0x74f06b9e, 0x340ce28b, 0x74dbf1ef, 0x343aca87,
+ 0x74c7663a, 0x3468aa76,
+ 0x74b2c884, 0x34968250, 0x749e18cd, 0x34c4520d, 0x7489571c, 0x34f219a8,
+ 0x74748371, 0x351fd918,
+ 0x745f9dd1, 0x354d9057, 0x744aa63f, 0x357b3f5d, 0x74359cbd, 0x35a8e625,
+ 0x74208150, 0x35d684a6,
+ 0x740b53fb, 0x36041ad9, 0x73f614c0, 0x3631a8b8, 0x73e0c3a3, 0x365f2e3b,
+ 0x73cb60a8, 0x368cab5c,
+ 0x73b5ebd1, 0x36ba2014, 0x73a06522, 0x36e78c5b, 0x738acc9e, 0x3714f02a,
+ 0x73752249, 0x37424b7b,
+ 0x735f6626, 0x376f9e46, 0x73499838, 0x379ce885, 0x7333b883, 0x37ca2a30,
+ 0x731dc70a, 0x37f76341,
+ 0x7307c3d0, 0x382493b0, 0x72f1aed9, 0x3851bb77, 0x72db8828, 0x387eda8e,
+ 0x72c54fc1, 0x38abf0ef,
+ 0x72af05a7, 0x38d8fe93, 0x7298a9dd, 0x39060373, 0x72823c67, 0x3932ff87,
+ 0x726bbd48, 0x395ff2c9,
+ 0x72552c85, 0x398cdd32, 0x723e8a20, 0x39b9bebc, 0x7227d61c, 0x39e6975e,
+ 0x7211107e, 0x3a136712,
+ 0x71fa3949, 0x3a402dd2, 0x71e35080, 0x3a6ceb96, 0x71cc5626, 0x3a99a057,
+ 0x71b54a41, 0x3ac64c0f,
+ 0x719e2cd2, 0x3af2eeb7, 0x7186fdde, 0x3b1f8848, 0x716fbd68, 0x3b4c18ba,
+ 0x71586b74, 0x3b78a007,
+ 0x71410805, 0x3ba51e29, 0x7129931f, 0x3bd19318, 0x71120cc5, 0x3bfdfecd,
+ 0x70fa74fc, 0x3c2a6142,
+ 0x70e2cbc6, 0x3c56ba70, 0x70cb1128, 0x3c830a50, 0x70b34525, 0x3caf50da,
+ 0x709b67c0, 0x3cdb8e09,
+ 0x708378ff, 0x3d07c1d6, 0x706b78e3, 0x3d33ec39, 0x70536771, 0x3d600d2c,
+ 0x703b44ad, 0x3d8c24a8,
+ 0x7023109a, 0x3db832a6, 0x700acb3c, 0x3de4371f, 0x6ff27497, 0x3e10320d,
+ 0x6fda0cae, 0x3e3c2369,
+ 0x6fc19385, 0x3e680b2c, 0x6fa90921, 0x3e93e950, 0x6f906d84, 0x3ebfbdcd,
+ 0x6f77c0b3, 0x3eeb889c,
+ 0x6f5f02b2, 0x3f1749b8, 0x6f463383, 0x3f430119, 0x6f2d532c, 0x3f6eaeb8,
+ 0x6f1461b0, 0x3f9a5290,
+ 0x6efb5f12, 0x3fc5ec98, 0x6ee24b57, 0x3ff17cca, 0x6ec92683, 0x401d0321,
+ 0x6eaff099, 0x40487f94,
+ 0x6e96a99d, 0x4073f21d, 0x6e7d5193, 0x409f5ab6, 0x6e63e87f, 0x40cab958,
+ 0x6e4a6e66, 0x40f60dfb,
+ 0x6e30e34a, 0x4121589b, 0x6e174730, 0x414c992f, 0x6dfd9a1c, 0x4177cfb1,
+ 0x6de3dc11, 0x41a2fc1a,
+ 0x6dca0d14, 0x41ce1e65, 0x6db02d29, 0x41f93689, 0x6d963c54, 0x42244481,
+ 0x6d7c3a98, 0x424f4845,
+ 0x6d6227fa, 0x427a41d0, 0x6d48047e, 0x42a5311b, 0x6d2dd027, 0x42d0161e,
+ 0x6d138afb, 0x42faf0d4,
+ 0x6cf934fc, 0x4325c135, 0x6cdece2f, 0x4350873c, 0x6cc45698, 0x437b42e1,
+ 0x6ca9ce3b, 0x43a5f41e,
+ 0x6c8f351c, 0x43d09aed, 0x6c748b3f, 0x43fb3746, 0x6c59d0a9, 0x4425c923,
+ 0x6c3f055d, 0x4450507e,
+ 0x6c242960, 0x447acd50, 0x6c093cb6, 0x44a53f93, 0x6bee3f62, 0x44cfa740,
+ 0x6bd3316a, 0x44fa0450,
+ 0x6bb812d1, 0x452456bd, 0x6b9ce39b, 0x454e9e80, 0x6b81a3cd, 0x4578db93,
+ 0x6b66536b, 0x45a30df0,
+ 0x6b4af279, 0x45cd358f, 0x6b2f80fb, 0x45f7526b, 0x6b13fef5, 0x4621647d,
+ 0x6af86c6c, 0x464b6bbe,
+ 0x6adcc964, 0x46756828, 0x6ac115e2, 0x469f59b4, 0x6aa551e9, 0x46c9405c,
+ 0x6a897d7d, 0x46f31c1a,
+ 0x6a6d98a4, 0x471cece7, 0x6a51a361, 0x4746b2bc, 0x6a359db9, 0x47706d93,
+ 0x6a1987b0, 0x479a1d67,
+ 0x69fd614a, 0x47c3c22f, 0x69e12a8c, 0x47ed5be6, 0x69c4e37a, 0x4816ea86,
+ 0x69a88c19, 0x48406e08,
+ 0x698c246c, 0x4869e665, 0x696fac78, 0x48935397, 0x69532442, 0x48bcb599,
+ 0x69368bce, 0x48e60c62,
+ 0x6919e320, 0x490f57ee, 0x68fd2a3d, 0x49389836, 0x68e06129, 0x4961cd33,
+ 0x68c387e9, 0x498af6df,
+ 0x68a69e81, 0x49b41533, 0x6889a4f6, 0x49dd282a, 0x686c9b4b, 0x4a062fbd,
+ 0x684f8186, 0x4a2f2be6,
+ 0x683257ab, 0x4a581c9e, 0x68151dbe, 0x4a8101de, 0x67f7d3c5, 0x4aa9dba2,
+ 0x67da79c3, 0x4ad2a9e2,
+ 0x67bd0fbd, 0x4afb6c98, 0x679f95b7, 0x4b2423be, 0x67820bb7, 0x4b4ccf4d,
+ 0x676471c0, 0x4b756f40,
+ 0x6746c7d8, 0x4b9e0390, 0x67290e02, 0x4bc68c36, 0x670b4444, 0x4bef092d,
+ 0x66ed6aa1, 0x4c177a6e,
+ 0x66cf8120, 0x4c3fdff4, 0x66b187c3, 0x4c6839b7, 0x66937e91, 0x4c9087b1,
+ 0x6675658c, 0x4cb8c9dd,
+ 0x66573cbb, 0x4ce10034, 0x66390422, 0x4d092ab0, 0x661abbc5, 0x4d31494b,
+ 0x65fc63a9, 0x4d595bfe,
+ 0x65ddfbd3, 0x4d8162c4, 0x65bf8447, 0x4da95d96, 0x65a0fd0b, 0x4dd14c6e,
+ 0x65826622, 0x4df92f46,
+ 0x6563bf92, 0x4e210617, 0x6545095f, 0x4e48d0dd, 0x6526438f, 0x4e708f8f,
+ 0x65076e25, 0x4e984229,
+ 0x64e88926, 0x4ebfe8a5, 0x64c99498, 0x4ee782fb, 0x64aa907f, 0x4f0f1126,
+ 0x648b7ce0, 0x4f369320,
+ 0x646c59bf, 0x4f5e08e3, 0x644d2722, 0x4f857269, 0x642de50d, 0x4faccfab,
+ 0x640e9386, 0x4fd420a4,
+ 0x63ef3290, 0x4ffb654d, 0x63cfc231, 0x50229da1, 0x63b0426d, 0x5049c999,
+ 0x6390b34a, 0x5070e92f,
+ 0x637114cc, 0x5097fc5e, 0x635166f9, 0x50bf031f, 0x6331a9d4, 0x50e5fd6d,
+ 0x6311dd64, 0x510ceb40,
+ 0x62f201ac, 0x5133cc94, 0x62d216b3, 0x515aa162, 0x62b21c7b, 0x518169a5,
+ 0x6292130c, 0x51a82555,
+ 0x6271fa69, 0x51ced46e, 0x6251d298, 0x51f576ea, 0x62319b9d, 0x521c0cc2,
+ 0x6211557e, 0x524295f0,
+ 0x61f1003f, 0x5269126e, 0x61d09be5, 0x528f8238, 0x61b02876, 0x52b5e546,
+ 0x618fa5f7, 0x52dc3b92,
+ 0x616f146c, 0x53028518, 0x614e73da, 0x5328c1d0, 0x612dc447, 0x534ef1b5,
+ 0x610d05b7, 0x537514c2,
+ 0x60ec3830, 0x539b2af0, 0x60cb5bb7, 0x53c13439, 0x60aa7050, 0x53e73097,
+ 0x60897601, 0x540d2005,
+ 0x60686ccf, 0x5433027d, 0x604754bf, 0x5458d7f9, 0x60262dd6, 0x547ea073,
+ 0x6004f819, 0x54a45be6,
+ 0x5fe3b38d, 0x54ca0a4b, 0x5fc26038, 0x54efab9c, 0x5fa0fe1f, 0x55153fd4,
+ 0x5f7f8d46, 0x553ac6ee,
+ 0x5f5e0db3, 0x556040e2, 0x5f3c7f6b, 0x5585adad, 0x5f1ae274, 0x55ab0d46,
+ 0x5ef936d1, 0x55d05faa,
+ 0x5ed77c8a, 0x55f5a4d2, 0x5eb5b3a2, 0x561adcb9, 0x5e93dc1f, 0x56400758,
+ 0x5e71f606, 0x566524aa,
+ 0x5e50015d, 0x568a34a9, 0x5e2dfe29, 0x56af3750, 0x5e0bec6e, 0x56d42c99,
+ 0x5de9cc33, 0x56f9147e,
+ 0x5dc79d7c, 0x571deefa, 0x5da5604f, 0x5742bc06, 0x5d8314b1, 0x57677b9d,
+ 0x5d60baa7, 0x578c2dba,
+ 0x5d3e5237, 0x57b0d256, 0x5d1bdb65, 0x57d5696d, 0x5cf95638, 0x57f9f2f8,
+ 0x5cd6c2b5, 0x581e6ef1,
+ 0x5cb420e0, 0x5842dd54, 0x5c9170bf, 0x58673e1b, 0x5c6eb258, 0x588b9140,
+ 0x5c4be5b0, 0x58afd6bd,
+ 0x5c290acc, 0x58d40e8c, 0x5c0621b2, 0x58f838a9, 0x5be32a67, 0x591c550e,
+ 0x5bc024f0, 0x594063b5,
+ 0x5b9d1154, 0x59646498, 0x5b79ef96, 0x598857b2, 0x5b56bfbd, 0x59ac3cfd,
+ 0x5b3381ce, 0x59d01475,
+ 0x5b1035cf, 0x59f3de12, 0x5aecdbc5, 0x5a1799d1, 0x5ac973b5, 0x5a3b47ab,
+ 0x5aa5fda5, 0x5a5ee79a,
+ 0x5a82799a, 0x5a82799a, 0x5a5ee79a, 0x5aa5fda5, 0x5a3b47ab, 0x5ac973b5,
+ 0x5a1799d1, 0x5aecdbc5,
+ 0x59f3de12, 0x5b1035cf, 0x59d01475, 0x5b3381ce, 0x59ac3cfd, 0x5b56bfbd,
+ 0x598857b2, 0x5b79ef96,
+ 0x59646498, 0x5b9d1154, 0x594063b5, 0x5bc024f0, 0x591c550e, 0x5be32a67,
+ 0x58f838a9, 0x5c0621b2,
+ 0x58d40e8c, 0x5c290acc, 0x58afd6bd, 0x5c4be5b0, 0x588b9140, 0x5c6eb258,
+ 0x58673e1b, 0x5c9170bf,
+ 0x5842dd54, 0x5cb420e0, 0x581e6ef1, 0x5cd6c2b5, 0x57f9f2f8, 0x5cf95638,
+ 0x57d5696d, 0x5d1bdb65,
+ 0x57b0d256, 0x5d3e5237, 0x578c2dba, 0x5d60baa7, 0x57677b9d, 0x5d8314b1,
+ 0x5742bc06, 0x5da5604f,
+ 0x571deefa, 0x5dc79d7c, 0x56f9147e, 0x5de9cc33, 0x56d42c99, 0x5e0bec6e,
+ 0x56af3750, 0x5e2dfe29,
+ 0x568a34a9, 0x5e50015d, 0x566524aa, 0x5e71f606, 0x56400758, 0x5e93dc1f,
+ 0x561adcb9, 0x5eb5b3a2,
+ 0x55f5a4d2, 0x5ed77c8a, 0x55d05faa, 0x5ef936d1, 0x55ab0d46, 0x5f1ae274,
+ 0x5585adad, 0x5f3c7f6b,
+ 0x556040e2, 0x5f5e0db3, 0x553ac6ee, 0x5f7f8d46, 0x55153fd4, 0x5fa0fe1f,
+ 0x54efab9c, 0x5fc26038,
+ 0x54ca0a4b, 0x5fe3b38d, 0x54a45be6, 0x6004f819, 0x547ea073, 0x60262dd6,
+ 0x5458d7f9, 0x604754bf,
+ 0x5433027d, 0x60686ccf, 0x540d2005, 0x60897601, 0x53e73097, 0x60aa7050,
+ 0x53c13439, 0x60cb5bb7,
+ 0x539b2af0, 0x60ec3830, 0x537514c2, 0x610d05b7, 0x534ef1b5, 0x612dc447,
+ 0x5328c1d0, 0x614e73da,
+ 0x53028518, 0x616f146c, 0x52dc3b92, 0x618fa5f7, 0x52b5e546, 0x61b02876,
+ 0x528f8238, 0x61d09be5,
+ 0x5269126e, 0x61f1003f, 0x524295f0, 0x6211557e, 0x521c0cc2, 0x62319b9d,
+ 0x51f576ea, 0x6251d298,
+ 0x51ced46e, 0x6271fa69, 0x51a82555, 0x6292130c, 0x518169a5, 0x62b21c7b,
+ 0x515aa162, 0x62d216b3,
+ 0x5133cc94, 0x62f201ac, 0x510ceb40, 0x6311dd64, 0x50e5fd6d, 0x6331a9d4,
+ 0x50bf031f, 0x635166f9,
+ 0x5097fc5e, 0x637114cc, 0x5070e92f, 0x6390b34a, 0x5049c999, 0x63b0426d,
+ 0x50229da1, 0x63cfc231,
+ 0x4ffb654d, 0x63ef3290, 0x4fd420a4, 0x640e9386, 0x4faccfab, 0x642de50d,
+ 0x4f857269, 0x644d2722,
+ 0x4f5e08e3, 0x646c59bf, 0x4f369320, 0x648b7ce0, 0x4f0f1126, 0x64aa907f,
+ 0x4ee782fb, 0x64c99498,
+ 0x4ebfe8a5, 0x64e88926, 0x4e984229, 0x65076e25, 0x4e708f8f, 0x6526438f,
+ 0x4e48d0dd, 0x6545095f,
+ 0x4e210617, 0x6563bf92, 0x4df92f46, 0x65826622, 0x4dd14c6e, 0x65a0fd0b,
+ 0x4da95d96, 0x65bf8447,
+ 0x4d8162c4, 0x65ddfbd3, 0x4d595bfe, 0x65fc63a9, 0x4d31494b, 0x661abbc5,
+ 0x4d092ab0, 0x66390422,
+ 0x4ce10034, 0x66573cbb, 0x4cb8c9dd, 0x6675658c, 0x4c9087b1, 0x66937e91,
+ 0x4c6839b7, 0x66b187c3,
+ 0x4c3fdff4, 0x66cf8120, 0x4c177a6e, 0x66ed6aa1, 0x4bef092d, 0x670b4444,
+ 0x4bc68c36, 0x67290e02,
+ 0x4b9e0390, 0x6746c7d8, 0x4b756f40, 0x676471c0, 0x4b4ccf4d, 0x67820bb7,
+ 0x4b2423be, 0x679f95b7,
+ 0x4afb6c98, 0x67bd0fbd, 0x4ad2a9e2, 0x67da79c3, 0x4aa9dba2, 0x67f7d3c5,
+ 0x4a8101de, 0x68151dbe,
+ 0x4a581c9e, 0x683257ab, 0x4a2f2be6, 0x684f8186, 0x4a062fbd, 0x686c9b4b,
+ 0x49dd282a, 0x6889a4f6,
+ 0x49b41533, 0x68a69e81, 0x498af6df, 0x68c387e9, 0x4961cd33, 0x68e06129,
+ 0x49389836, 0x68fd2a3d,
+ 0x490f57ee, 0x6919e320, 0x48e60c62, 0x69368bce, 0x48bcb599, 0x69532442,
+ 0x48935397, 0x696fac78,
+ 0x4869e665, 0x698c246c, 0x48406e08, 0x69a88c19, 0x4816ea86, 0x69c4e37a,
+ 0x47ed5be6, 0x69e12a8c,
+ 0x47c3c22f, 0x69fd614a, 0x479a1d67, 0x6a1987b0, 0x47706d93, 0x6a359db9,
+ 0x4746b2bc, 0x6a51a361,
+ 0x471cece7, 0x6a6d98a4, 0x46f31c1a, 0x6a897d7d, 0x46c9405c, 0x6aa551e9,
+ 0x469f59b4, 0x6ac115e2,
+ 0x46756828, 0x6adcc964, 0x464b6bbe, 0x6af86c6c, 0x4621647d, 0x6b13fef5,
+ 0x45f7526b, 0x6b2f80fb,
+ 0x45cd358f, 0x6b4af279, 0x45a30df0, 0x6b66536b, 0x4578db93, 0x6b81a3cd,
+ 0x454e9e80, 0x6b9ce39b,
+ 0x452456bd, 0x6bb812d1, 0x44fa0450, 0x6bd3316a, 0x44cfa740, 0x6bee3f62,
+ 0x44a53f93, 0x6c093cb6,
+ 0x447acd50, 0x6c242960, 0x4450507e, 0x6c3f055d, 0x4425c923, 0x6c59d0a9,
+ 0x43fb3746, 0x6c748b3f,
+ 0x43d09aed, 0x6c8f351c, 0x43a5f41e, 0x6ca9ce3b, 0x437b42e1, 0x6cc45698,
+ 0x4350873c, 0x6cdece2f,
+ 0x4325c135, 0x6cf934fc, 0x42faf0d4, 0x6d138afb, 0x42d0161e, 0x6d2dd027,
+ 0x42a5311b, 0x6d48047e,
+ 0x427a41d0, 0x6d6227fa, 0x424f4845, 0x6d7c3a98, 0x42244481, 0x6d963c54,
+ 0x41f93689, 0x6db02d29,
+ 0x41ce1e65, 0x6dca0d14, 0x41a2fc1a, 0x6de3dc11, 0x4177cfb1, 0x6dfd9a1c,
+ 0x414c992f, 0x6e174730,
+ 0x4121589b, 0x6e30e34a, 0x40f60dfb, 0x6e4a6e66, 0x40cab958, 0x6e63e87f,
+ 0x409f5ab6, 0x6e7d5193,
+ 0x4073f21d, 0x6e96a99d, 0x40487f94, 0x6eaff099, 0x401d0321, 0x6ec92683,
+ 0x3ff17cca, 0x6ee24b57,
+ 0x3fc5ec98, 0x6efb5f12, 0x3f9a5290, 0x6f1461b0, 0x3f6eaeb8, 0x6f2d532c,
+ 0x3f430119, 0x6f463383,
+ 0x3f1749b8, 0x6f5f02b2, 0x3eeb889c, 0x6f77c0b3, 0x3ebfbdcd, 0x6f906d84,
+ 0x3e93e950, 0x6fa90921,
+ 0x3e680b2c, 0x6fc19385, 0x3e3c2369, 0x6fda0cae, 0x3e10320d, 0x6ff27497,
+ 0x3de4371f, 0x700acb3c,
+ 0x3db832a6, 0x7023109a, 0x3d8c24a8, 0x703b44ad, 0x3d600d2c, 0x70536771,
+ 0x3d33ec39, 0x706b78e3,
+ 0x3d07c1d6, 0x708378ff, 0x3cdb8e09, 0x709b67c0, 0x3caf50da, 0x70b34525,
+ 0x3c830a50, 0x70cb1128,
+ 0x3c56ba70, 0x70e2cbc6, 0x3c2a6142, 0x70fa74fc, 0x3bfdfecd, 0x71120cc5,
+ 0x3bd19318, 0x7129931f,
+ 0x3ba51e29, 0x71410805, 0x3b78a007, 0x71586b74, 0x3b4c18ba, 0x716fbd68,
+ 0x3b1f8848, 0x7186fdde,
+ 0x3af2eeb7, 0x719e2cd2, 0x3ac64c0f, 0x71b54a41, 0x3a99a057, 0x71cc5626,
+ 0x3a6ceb96, 0x71e35080,
+ 0x3a402dd2, 0x71fa3949, 0x3a136712, 0x7211107e, 0x39e6975e, 0x7227d61c,
+ 0x39b9bebc, 0x723e8a20,
+ 0x398cdd32, 0x72552c85, 0x395ff2c9, 0x726bbd48, 0x3932ff87, 0x72823c67,
+ 0x39060373, 0x7298a9dd,
+ 0x38d8fe93, 0x72af05a7, 0x38abf0ef, 0x72c54fc1, 0x387eda8e, 0x72db8828,
+ 0x3851bb77, 0x72f1aed9,
+ 0x382493b0, 0x7307c3d0, 0x37f76341, 0x731dc70a, 0x37ca2a30, 0x7333b883,
+ 0x379ce885, 0x73499838,
+ 0x376f9e46, 0x735f6626, 0x37424b7b, 0x73752249, 0x3714f02a, 0x738acc9e,
+ 0x36e78c5b, 0x73a06522,
+ 0x36ba2014, 0x73b5ebd1, 0x368cab5c, 0x73cb60a8, 0x365f2e3b, 0x73e0c3a3,
+ 0x3631a8b8, 0x73f614c0,
+ 0x36041ad9, 0x740b53fb, 0x35d684a6, 0x74208150, 0x35a8e625, 0x74359cbd,
+ 0x357b3f5d, 0x744aa63f,
+ 0x354d9057, 0x745f9dd1, 0x351fd918, 0x74748371, 0x34f219a8, 0x7489571c,
+ 0x34c4520d, 0x749e18cd,
+ 0x34968250, 0x74b2c884, 0x3468aa76, 0x74c7663a, 0x343aca87, 0x74dbf1ef,
+ 0x340ce28b, 0x74f06b9e,
+ 0x33def287, 0x7504d345, 0x33b0fa84, 0x751928e0, 0x3382fa88, 0x752d6c6c,
+ 0x3354f29b, 0x75419de7,
+ 0x3326e2c3, 0x7555bd4c, 0x32f8cb07, 0x7569ca99, 0x32caab6f, 0x757dc5ca,
+ 0x329c8402, 0x7591aedd,
+ 0x326e54c7, 0x75a585cf, 0x32401dc6, 0x75b94a9c, 0x3211df04, 0x75ccfd42,
+ 0x31e39889, 0x75e09dbd,
+ 0x31b54a5e, 0x75f42c0b, 0x3186f487, 0x7607a828, 0x3158970e, 0x761b1211,
+ 0x312a31f8, 0x762e69c4,
+ 0x30fbc54d, 0x7641af3d, 0x30cd5115, 0x7654e279, 0x309ed556, 0x76680376,
+ 0x30705217, 0x767b1231,
+ 0x3041c761, 0x768e0ea6, 0x30133539, 0x76a0f8d2, 0x2fe49ba7, 0x76b3d0b4,
+ 0x2fb5fab2, 0x76c69647,
+ 0x2f875262, 0x76d94989, 0x2f58a2be, 0x76ebea77, 0x2f29ebcc, 0x76fe790e,
+ 0x2efb2d95, 0x7710f54c,
+ 0x2ecc681e, 0x77235f2d, 0x2e9d9b70, 0x7735b6af, 0x2e6ec792, 0x7747fbce,
+ 0x2e3fec8b, 0x775a2e89,
+ 0x2e110a62, 0x776c4edb, 0x2de2211e, 0x777e5cc3, 0x2db330c7, 0x7790583e,
+ 0x2d843964, 0x77a24148,
+ 0x2d553afc, 0x77b417df, 0x2d263596, 0x77c5dc01, 0x2cf72939, 0x77d78daa,
+ 0x2cc815ee, 0x77e92cd9,
+ 0x2c98fbba, 0x77fab989, 0x2c69daa6, 0x780c33b8, 0x2c3ab2b9, 0x781d9b65,
+ 0x2c0b83fa, 0x782ef08b,
+ 0x2bdc4e6f, 0x78403329, 0x2bad1221, 0x7851633b, 0x2b7dcf17, 0x786280bf,
+ 0x2b4e8558, 0x78738bb3,
+ 0x2b1f34eb, 0x78848414, 0x2aefddd8, 0x789569df, 0x2ac08026, 0x78a63d11,
+ 0x2a911bdc, 0x78b6fda8,
+ 0x2a61b101, 0x78c7aba2, 0x2a323f9e, 0x78d846fb, 0x2a02c7b8, 0x78e8cfb2,
+ 0x29d34958, 0x78f945c3,
+ 0x29a3c485, 0x7909a92d, 0x29743946, 0x7919f9ec, 0x2944a7a2, 0x792a37fe,
+ 0x29150fa1, 0x793a6361,
+ 0x28e5714b, 0x794a7c12, 0x28b5cca5, 0x795a820e, 0x288621b9, 0x796a7554,
+ 0x2856708d, 0x797a55e0,
+ 0x2826b928, 0x798a23b1, 0x27f6fb92, 0x7999dec4, 0x27c737d3, 0x79a98715,
+ 0x27976df1, 0x79b91ca4,
+ 0x27679df4, 0x79c89f6e, 0x2737c7e3, 0x79d80f6f, 0x2707ebc7, 0x79e76ca7,
+ 0x26d809a5, 0x79f6b711,
+ 0x26a82186, 0x7a05eead, 0x26783370, 0x7a151378, 0x26483f6c, 0x7a24256f,
+ 0x26184581, 0x7a332490,
+ 0x25e845b6, 0x7a4210d8, 0x25b84012, 0x7a50ea47, 0x2588349d, 0x7a5fb0d8,
+ 0x2558235f, 0x7a6e648a,
+ 0x25280c5e, 0x7a7d055b, 0x24f7efa2, 0x7a8b9348, 0x24c7cd33, 0x7a9a0e50,
+ 0x2497a517, 0x7aa8766f,
+ 0x24677758, 0x7ab6cba4, 0x243743fa, 0x7ac50dec, 0x24070b08, 0x7ad33d45,
+ 0x23d6cc87, 0x7ae159ae,
+ 0x23a6887f, 0x7aef6323, 0x23763ef7, 0x7afd59a4, 0x2345eff8, 0x7b0b3d2c,
+ 0x23159b88, 0x7b190dbc,
+ 0x22e541af, 0x7b26cb4f, 0x22b4e274, 0x7b3475e5, 0x22847de0, 0x7b420d7a,
+ 0x225413f8, 0x7b4f920e,
+ 0x2223a4c5, 0x7b5d039e, 0x21f3304f, 0x7b6a6227, 0x21c2b69c, 0x7b77ada8,
+ 0x219237b5, 0x7b84e61f,
+ 0x2161b3a0, 0x7b920b89, 0x21312a65, 0x7b9f1de6, 0x21009c0c, 0x7bac1d31,
+ 0x20d0089c, 0x7bb9096b,
+ 0x209f701c, 0x7bc5e290, 0x206ed295, 0x7bd2a89e, 0x203e300d, 0x7bdf5b94,
+ 0x200d888d, 0x7bebfb70,
+ 0x1fdcdc1b, 0x7bf88830, 0x1fac2abf, 0x7c0501d2, 0x1f7b7481, 0x7c116853,
+ 0x1f4ab968, 0x7c1dbbb3,
+ 0x1f19f97b, 0x7c29fbee, 0x1ee934c3, 0x7c362904, 0x1eb86b46, 0x7c4242f2,
+ 0x1e879d0d, 0x7c4e49b7,
+ 0x1e56ca1e, 0x7c5a3d50, 0x1e25f282, 0x7c661dbc, 0x1df5163f, 0x7c71eaf9,
+ 0x1dc4355e, 0x7c7da505,
+ 0x1d934fe5, 0x7c894bde, 0x1d6265dd, 0x7c94df83, 0x1d31774d, 0x7ca05ff1,
+ 0x1d00843d, 0x7cabcd28,
+ 0x1ccf8cb3, 0x7cb72724, 0x1c9e90b8, 0x7cc26de5, 0x1c6d9053, 0x7ccda169,
+ 0x1c3c8b8c, 0x7cd8c1ae,
+ 0x1c0b826a, 0x7ce3ceb2, 0x1bda74f6, 0x7ceec873, 0x1ba96335, 0x7cf9aef0,
+ 0x1b784d30, 0x7d048228,
+ 0x1b4732ef, 0x7d0f4218, 0x1b161479, 0x7d19eebf, 0x1ae4f1d6, 0x7d24881b,
+ 0x1ab3cb0d, 0x7d2f0e2b,
+ 0x1a82a026, 0x7d3980ec, 0x1a517128, 0x7d43e05e, 0x1a203e1b, 0x7d4e2c7f,
+ 0x19ef0707, 0x7d58654d,
+ 0x19bdcbf3, 0x7d628ac6, 0x198c8ce7, 0x7d6c9ce9, 0x195b49ea, 0x7d769bb5,
+ 0x192a0304, 0x7d808728,
+ 0x18f8b83c, 0x7d8a5f40, 0x18c7699b, 0x7d9423fc, 0x18961728, 0x7d9dd55a,
+ 0x1864c0ea, 0x7da77359,
+ 0x183366e9, 0x7db0fdf8, 0x1802092c, 0x7dba7534, 0x17d0a7bc, 0x7dc3d90d,
+ 0x179f429f, 0x7dcd2981,
+ 0x176dd9de, 0x7dd6668f, 0x173c6d80, 0x7ddf9034, 0x170afd8d, 0x7de8a670,
+ 0x16d98a0c, 0x7df1a942,
+ 0x16a81305, 0x7dfa98a8, 0x1676987f, 0x7e0374a0, 0x16451a83, 0x7e0c3d29,
+ 0x16139918, 0x7e14f242,
+ 0x15e21445, 0x7e1d93ea, 0x15b08c12, 0x7e26221f, 0x157f0086, 0x7e2e9cdf,
+ 0x154d71aa, 0x7e37042a,
+ 0x151bdf86, 0x7e3f57ff, 0x14ea4a1f, 0x7e47985b, 0x14b8b17f, 0x7e4fc53e,
+ 0x148715ae, 0x7e57dea7,
+ 0x145576b1, 0x7e5fe493, 0x1423d492, 0x7e67d703, 0x13f22f58, 0x7e6fb5f4,
+ 0x13c0870a, 0x7e778166,
+ 0x138edbb1, 0x7e7f3957, 0x135d2d53, 0x7e86ddc6, 0x132b7bf9, 0x7e8e6eb2,
+ 0x12f9c7aa, 0x7e95ec1a,
+ 0x12c8106f, 0x7e9d55fc, 0x1296564d, 0x7ea4ac58, 0x1264994e, 0x7eabef2c,
+ 0x1232d979, 0x7eb31e78,
+ 0x120116d5, 0x7eba3a39, 0x11cf516a, 0x7ec14270, 0x119d8941, 0x7ec8371a,
+ 0x116bbe60, 0x7ecf1837,
+ 0x1139f0cf, 0x7ed5e5c6, 0x11082096, 0x7edc9fc6, 0x10d64dbd, 0x7ee34636,
+ 0x10a4784b, 0x7ee9d914,
+ 0x1072a048, 0x7ef05860, 0x1040c5bb, 0x7ef6c418, 0x100ee8ad, 0x7efd1c3c,
+ 0xfdd0926, 0x7f0360cb,
+ 0xfab272b, 0x7f0991c4, 0xf7942c7, 0x7f0faf25, 0xf475bff, 0x7f15b8ee,
+ 0xf1572dc, 0x7f1baf1e,
+ 0xee38766, 0x7f2191b4, 0xeb199a4, 0x7f2760af, 0xe7fa99e, 0x7f2d1c0e,
+ 0xe4db75b, 0x7f32c3d1,
+ 0xe1bc2e4, 0x7f3857f6, 0xde9cc40, 0x7f3dd87c, 0xdb7d376, 0x7f434563,
+ 0xd85d88f, 0x7f489eaa,
+ 0xd53db92, 0x7f4de451, 0xd21dc87, 0x7f531655, 0xcefdb76, 0x7f5834b7,
+ 0xcbdd865, 0x7f5d3f75,
+ 0xc8bd35e, 0x7f62368f, 0xc59cc68, 0x7f671a05, 0xc27c389, 0x7f6be9d4,
+ 0xbf5b8cb, 0x7f70a5fe,
+ 0xbc3ac35, 0x7f754e80, 0xb919dcf, 0x7f79e35a, 0xb5f8d9f, 0x7f7e648c,
+ 0xb2d7baf, 0x7f82d214,
+ 0xafb6805, 0x7f872bf3, 0xac952aa, 0x7f8b7227, 0xa973ba5, 0x7f8fa4b0,
+ 0xa6522fe, 0x7f93c38c,
+ 0xa3308bd, 0x7f97cebd, 0xa00ece8, 0x7f9bc640, 0x9cecf89, 0x7f9faa15,
+ 0x99cb0a7, 0x7fa37a3c,
+ 0x96a9049, 0x7fa736b4, 0x9386e78, 0x7faadf7c, 0x9064b3a, 0x7fae7495,
+ 0x8d42699, 0x7fb1f5fc,
+ 0x8a2009a, 0x7fb563b3, 0x86fd947, 0x7fb8bdb8, 0x83db0a7, 0x7fbc040a,
+ 0x80b86c2, 0x7fbf36aa,
+ 0x7d95b9e, 0x7fc25596, 0x7a72f45, 0x7fc560cf, 0x77501be, 0x7fc85854,
+ 0x742d311, 0x7fcb3c23,
+ 0x710a345, 0x7fce0c3e, 0x6de7262, 0x7fd0c8a3, 0x6ac406f, 0x7fd37153,
+ 0x67a0d76, 0x7fd6064c,
+ 0x647d97c, 0x7fd8878e, 0x615a48b, 0x7fdaf519, 0x5e36ea9, 0x7fdd4eec,
+ 0x5b137df, 0x7fdf9508,
+ 0x57f0035, 0x7fe1c76b, 0x54cc7b1, 0x7fe3e616, 0x51a8e5c, 0x7fe5f108,
+ 0x4e8543e, 0x7fe7e841,
+ 0x4b6195d, 0x7fe9cbc0, 0x483ddc3, 0x7feb9b85, 0x451a177, 0x7fed5791,
+ 0x41f6480, 0x7feeffe1,
+ 0x3ed26e6, 0x7ff09478, 0x3bae8b2, 0x7ff21553, 0x388a9ea, 0x7ff38274,
+ 0x3566a96, 0x7ff4dbd9,
+ 0x3242abf, 0x7ff62182, 0x2f1ea6c, 0x7ff75370, 0x2bfa9a4, 0x7ff871a2,
+ 0x28d6870, 0x7ff97c18,
+ 0x25b26d7, 0x7ffa72d1, 0x228e4e2, 0x7ffb55ce, 0x1f6a297, 0x7ffc250f,
+ 0x1c45ffe, 0x7ffce093,
+ 0x1921d20, 0x7ffd885a, 0x15fda03, 0x7ffe1c65, 0x12d96b1, 0x7ffe9cb2,
+ 0xfb5330, 0x7fff0943,
+ 0xc90f88, 0x7fff6216, 0x96cbc1, 0x7fffa72c, 0x6487e3, 0x7fffd886, 0x3243f5,
+ 0x7ffff621,
+ 0x0, 0x7fffffff, 0xffcdbc0b, 0x7ffff621, 0xff9b781d, 0x7fffd886, 0xff69343f,
+ 0x7fffa72c,
+ 0xff36f078, 0x7fff6216, 0xff04acd0, 0x7fff0943, 0xfed2694f, 0x7ffe9cb2,
+ 0xfea025fd, 0x7ffe1c65,
+ 0xfe6de2e0, 0x7ffd885a, 0xfe3ba002, 0x7ffce093, 0xfe095d69, 0x7ffc250f,
+ 0xfdd71b1e, 0x7ffb55ce,
+ 0xfda4d929, 0x7ffa72d1, 0xfd729790, 0x7ff97c18, 0xfd40565c, 0x7ff871a2,
+ 0xfd0e1594, 0x7ff75370,
+ 0xfcdbd541, 0x7ff62182, 0xfca9956a, 0x7ff4dbd9, 0xfc775616, 0x7ff38274,
+ 0xfc45174e, 0x7ff21553,
+ 0xfc12d91a, 0x7ff09478, 0xfbe09b80, 0x7feeffe1, 0xfbae5e89, 0x7fed5791,
+ 0xfb7c223d, 0x7feb9b85,
+ 0xfb49e6a3, 0x7fe9cbc0, 0xfb17abc2, 0x7fe7e841, 0xfae571a4, 0x7fe5f108,
+ 0xfab3384f, 0x7fe3e616,
+ 0xfa80ffcb, 0x7fe1c76b, 0xfa4ec821, 0x7fdf9508, 0xfa1c9157, 0x7fdd4eec,
+ 0xf9ea5b75, 0x7fdaf519,
+ 0xf9b82684, 0x7fd8878e, 0xf985f28a, 0x7fd6064c, 0xf953bf91, 0x7fd37153,
+ 0xf9218d9e, 0x7fd0c8a3,
+ 0xf8ef5cbb, 0x7fce0c3e, 0xf8bd2cef, 0x7fcb3c23, 0xf88afe42, 0x7fc85854,
+ 0xf858d0bb, 0x7fc560cf,
+ 0xf826a462, 0x7fc25596, 0xf7f4793e, 0x7fbf36aa, 0xf7c24f59, 0x7fbc040a,
+ 0xf79026b9, 0x7fb8bdb8,
+ 0xf75dff66, 0x7fb563b3, 0xf72bd967, 0x7fb1f5fc, 0xf6f9b4c6, 0x7fae7495,
+ 0xf6c79188, 0x7faadf7c,
+ 0xf6956fb7, 0x7fa736b4, 0xf6634f59, 0x7fa37a3c, 0xf6313077, 0x7f9faa15,
+ 0xf5ff1318, 0x7f9bc640,
+ 0xf5ccf743, 0x7f97cebd, 0xf59add02, 0x7f93c38c, 0xf568c45b, 0x7f8fa4b0,
+ 0xf536ad56, 0x7f8b7227,
+ 0xf50497fb, 0x7f872bf3, 0xf4d28451, 0x7f82d214, 0xf4a07261, 0x7f7e648c,
+ 0xf46e6231, 0x7f79e35a,
+ 0xf43c53cb, 0x7f754e80, 0xf40a4735, 0x7f70a5fe, 0xf3d83c77, 0x7f6be9d4,
+ 0xf3a63398, 0x7f671a05,
+ 0xf3742ca2, 0x7f62368f, 0xf342279b, 0x7f5d3f75, 0xf310248a, 0x7f5834b7,
+ 0xf2de2379, 0x7f531655,
+ 0xf2ac246e, 0x7f4de451, 0xf27a2771, 0x7f489eaa, 0xf2482c8a, 0x7f434563,
+ 0xf21633c0, 0x7f3dd87c,
+ 0xf1e43d1c, 0x7f3857f6, 0xf1b248a5, 0x7f32c3d1, 0xf1805662, 0x7f2d1c0e,
+ 0xf14e665c, 0x7f2760af,
+ 0xf11c789a, 0x7f2191b4, 0xf0ea8d24, 0x7f1baf1e, 0xf0b8a401, 0x7f15b8ee,
+ 0xf086bd39, 0x7f0faf25,
+ 0xf054d8d5, 0x7f0991c4, 0xf022f6da, 0x7f0360cb, 0xeff11753, 0x7efd1c3c,
+ 0xefbf3a45, 0x7ef6c418,
+ 0xef8d5fb8, 0x7ef05860, 0xef5b87b5, 0x7ee9d914, 0xef29b243, 0x7ee34636,
+ 0xeef7df6a, 0x7edc9fc6,
+ 0xeec60f31, 0x7ed5e5c6, 0xee9441a0, 0x7ecf1837, 0xee6276bf, 0x7ec8371a,
+ 0xee30ae96, 0x7ec14270,
+ 0xedfee92b, 0x7eba3a39, 0xedcd2687, 0x7eb31e78, 0xed9b66b2, 0x7eabef2c,
+ 0xed69a9b3, 0x7ea4ac58,
+ 0xed37ef91, 0x7e9d55fc, 0xed063856, 0x7e95ec1a, 0xecd48407, 0x7e8e6eb2,
+ 0xeca2d2ad, 0x7e86ddc6,
+ 0xec71244f, 0x7e7f3957, 0xec3f78f6, 0x7e778166, 0xec0dd0a8, 0x7e6fb5f4,
+ 0xebdc2b6e, 0x7e67d703,
+ 0xebaa894f, 0x7e5fe493, 0xeb78ea52, 0x7e57dea7, 0xeb474e81, 0x7e4fc53e,
+ 0xeb15b5e1, 0x7e47985b,
+ 0xeae4207a, 0x7e3f57ff, 0xeab28e56, 0x7e37042a, 0xea80ff7a, 0x7e2e9cdf,
+ 0xea4f73ee, 0x7e26221f,
+ 0xea1debbb, 0x7e1d93ea, 0xe9ec66e8, 0x7e14f242, 0xe9bae57d, 0x7e0c3d29,
+ 0xe9896781, 0x7e0374a0,
+ 0xe957ecfb, 0x7dfa98a8, 0xe92675f4, 0x7df1a942, 0xe8f50273, 0x7de8a670,
+ 0xe8c39280, 0x7ddf9034,
+ 0xe8922622, 0x7dd6668f, 0xe860bd61, 0x7dcd2981, 0xe82f5844, 0x7dc3d90d,
+ 0xe7fdf6d4, 0x7dba7534,
+ 0xe7cc9917, 0x7db0fdf8, 0xe79b3f16, 0x7da77359, 0xe769e8d8, 0x7d9dd55a,
+ 0xe7389665, 0x7d9423fc,
+ 0xe70747c4, 0x7d8a5f40, 0xe6d5fcfc, 0x7d808728, 0xe6a4b616, 0x7d769bb5,
+ 0xe6737319, 0x7d6c9ce9,
+ 0xe642340d, 0x7d628ac6, 0xe610f8f9, 0x7d58654d, 0xe5dfc1e5, 0x7d4e2c7f,
+ 0xe5ae8ed8, 0x7d43e05e,
+ 0xe57d5fda, 0x7d3980ec, 0xe54c34f3, 0x7d2f0e2b, 0xe51b0e2a, 0x7d24881b,
+ 0xe4e9eb87, 0x7d19eebf,
+ 0xe4b8cd11, 0x7d0f4218, 0xe487b2d0, 0x7d048228, 0xe4569ccb, 0x7cf9aef0,
+ 0xe4258b0a, 0x7ceec873,
+ 0xe3f47d96, 0x7ce3ceb2, 0xe3c37474, 0x7cd8c1ae, 0xe3926fad, 0x7ccda169,
+ 0xe3616f48, 0x7cc26de5,
+ 0xe330734d, 0x7cb72724, 0xe2ff7bc3, 0x7cabcd28, 0xe2ce88b3, 0x7ca05ff1,
+ 0xe29d9a23, 0x7c94df83,
+ 0xe26cb01b, 0x7c894bde, 0xe23bcaa2, 0x7c7da505, 0xe20ae9c1, 0x7c71eaf9,
+ 0xe1da0d7e, 0x7c661dbc,
+ 0xe1a935e2, 0x7c5a3d50, 0xe17862f3, 0x7c4e49b7, 0xe14794ba, 0x7c4242f2,
+ 0xe116cb3d, 0x7c362904,
+ 0xe0e60685, 0x7c29fbee, 0xe0b54698, 0x7c1dbbb3, 0xe0848b7f, 0x7c116853,
+ 0xe053d541, 0x7c0501d2,
+ 0xe02323e5, 0x7bf88830, 0xdff27773, 0x7bebfb70, 0xdfc1cff3, 0x7bdf5b94,
+ 0xdf912d6b, 0x7bd2a89e,
+ 0xdf608fe4, 0x7bc5e290, 0xdf2ff764, 0x7bb9096b, 0xdeff63f4, 0x7bac1d31,
+ 0xdeced59b, 0x7b9f1de6,
+ 0xde9e4c60, 0x7b920b89, 0xde6dc84b, 0x7b84e61f, 0xde3d4964, 0x7b77ada8,
+ 0xde0ccfb1, 0x7b6a6227,
+ 0xdddc5b3b, 0x7b5d039e, 0xddabec08, 0x7b4f920e, 0xdd7b8220, 0x7b420d7a,
+ 0xdd4b1d8c, 0x7b3475e5,
+ 0xdd1abe51, 0x7b26cb4f, 0xdcea6478, 0x7b190dbc, 0xdcba1008, 0x7b0b3d2c,
+ 0xdc89c109, 0x7afd59a4,
+ 0xdc597781, 0x7aef6323, 0xdc293379, 0x7ae159ae, 0xdbf8f4f8, 0x7ad33d45,
+ 0xdbc8bc06, 0x7ac50dec,
+ 0xdb9888a8, 0x7ab6cba4, 0xdb685ae9, 0x7aa8766f, 0xdb3832cd, 0x7a9a0e50,
+ 0xdb08105e, 0x7a8b9348,
+ 0xdad7f3a2, 0x7a7d055b, 0xdaa7dca1, 0x7a6e648a, 0xda77cb63, 0x7a5fb0d8,
+ 0xda47bfee, 0x7a50ea47,
+ 0xda17ba4a, 0x7a4210d8, 0xd9e7ba7f, 0x7a332490, 0xd9b7c094, 0x7a24256f,
+ 0xd987cc90, 0x7a151378,
+ 0xd957de7a, 0x7a05eead, 0xd927f65b, 0x79f6b711, 0xd8f81439, 0x79e76ca7,
+ 0xd8c8381d, 0x79d80f6f,
+ 0xd898620c, 0x79c89f6e, 0xd868920f, 0x79b91ca4, 0xd838c82d, 0x79a98715,
+ 0xd809046e, 0x7999dec4,
+ 0xd7d946d8, 0x798a23b1, 0xd7a98f73, 0x797a55e0, 0xd779de47, 0x796a7554,
+ 0xd74a335b, 0x795a820e,
+ 0xd71a8eb5, 0x794a7c12, 0xd6eaf05f, 0x793a6361, 0xd6bb585e, 0x792a37fe,
+ 0xd68bc6ba, 0x7919f9ec,
+ 0xd65c3b7b, 0x7909a92d, 0xd62cb6a8, 0x78f945c3, 0xd5fd3848, 0x78e8cfb2,
+ 0xd5cdc062, 0x78d846fb,
+ 0xd59e4eff, 0x78c7aba2, 0xd56ee424, 0x78b6fda8, 0xd53f7fda, 0x78a63d11,
+ 0xd5102228, 0x789569df,
+ 0xd4e0cb15, 0x78848414, 0xd4b17aa8, 0x78738bb3, 0xd48230e9, 0x786280bf,
+ 0xd452eddf, 0x7851633b,
+ 0xd423b191, 0x78403329, 0xd3f47c06, 0x782ef08b, 0xd3c54d47, 0x781d9b65,
+ 0xd396255a, 0x780c33b8,
+ 0xd3670446, 0x77fab989, 0xd337ea12, 0x77e92cd9, 0xd308d6c7, 0x77d78daa,
+ 0xd2d9ca6a, 0x77c5dc01,
+ 0xd2aac504, 0x77b417df, 0xd27bc69c, 0x77a24148, 0xd24ccf39, 0x7790583e,
+ 0xd21ddee2, 0x777e5cc3,
+ 0xd1eef59e, 0x776c4edb, 0xd1c01375, 0x775a2e89, 0xd191386e, 0x7747fbce,
+ 0xd1626490, 0x7735b6af,
+ 0xd13397e2, 0x77235f2d, 0xd104d26b, 0x7710f54c, 0xd0d61434, 0x76fe790e,
+ 0xd0a75d42, 0x76ebea77,
+ 0xd078ad9e, 0x76d94989, 0xd04a054e, 0x76c69647, 0xd01b6459, 0x76b3d0b4,
+ 0xcfeccac7, 0x76a0f8d2,
+ 0xcfbe389f, 0x768e0ea6, 0xcf8fade9, 0x767b1231, 0xcf612aaa, 0x76680376,
+ 0xcf32aeeb, 0x7654e279,
+ 0xcf043ab3, 0x7641af3d, 0xced5ce08, 0x762e69c4, 0xcea768f2, 0x761b1211,
+ 0xce790b79, 0x7607a828,
+ 0xce4ab5a2, 0x75f42c0b, 0xce1c6777, 0x75e09dbd, 0xcdee20fc, 0x75ccfd42,
+ 0xcdbfe23a, 0x75b94a9c,
+ 0xcd91ab39, 0x75a585cf, 0xcd637bfe, 0x7591aedd, 0xcd355491, 0x757dc5ca,
+ 0xcd0734f9, 0x7569ca99,
+ 0xccd91d3d, 0x7555bd4c, 0xccab0d65, 0x75419de7, 0xcc7d0578, 0x752d6c6c,
+ 0xcc4f057c, 0x751928e0,
+ 0xcc210d79, 0x7504d345, 0xcbf31d75, 0x74f06b9e, 0xcbc53579, 0x74dbf1ef,
+ 0xcb97558a, 0x74c7663a,
+ 0xcb697db0, 0x74b2c884, 0xcb3badf3, 0x749e18cd, 0xcb0de658, 0x7489571c,
+ 0xcae026e8, 0x74748371,
+ 0xcab26fa9, 0x745f9dd1, 0xca84c0a3, 0x744aa63f, 0xca5719db, 0x74359cbd,
+ 0xca297b5a, 0x74208150,
+ 0xc9fbe527, 0x740b53fb, 0xc9ce5748, 0x73f614c0, 0xc9a0d1c5, 0x73e0c3a3,
+ 0xc97354a4, 0x73cb60a8,
+ 0xc945dfec, 0x73b5ebd1, 0xc91873a5, 0x73a06522, 0xc8eb0fd6, 0x738acc9e,
+ 0xc8bdb485, 0x73752249,
+ 0xc89061ba, 0x735f6626, 0xc863177b, 0x73499838, 0xc835d5d0, 0x7333b883,
+ 0xc8089cbf, 0x731dc70a,
+ 0xc7db6c50, 0x7307c3d0, 0xc7ae4489, 0x72f1aed9, 0xc7812572, 0x72db8828,
+ 0xc7540f11, 0x72c54fc1,
+ 0xc727016d, 0x72af05a7, 0xc6f9fc8d, 0x7298a9dd, 0xc6cd0079, 0x72823c67,
+ 0xc6a00d37, 0x726bbd48,
+ 0xc67322ce, 0x72552c85, 0xc6464144, 0x723e8a20, 0xc61968a2, 0x7227d61c,
+ 0xc5ec98ee, 0x7211107e,
+ 0xc5bfd22e, 0x71fa3949, 0xc593146a, 0x71e35080, 0xc5665fa9, 0x71cc5626,
+ 0xc539b3f1, 0x71b54a41,
+ 0xc50d1149, 0x719e2cd2, 0xc4e077b8, 0x7186fdde, 0xc4b3e746, 0x716fbd68,
+ 0xc4875ff9, 0x71586b74,
+ 0xc45ae1d7, 0x71410805, 0xc42e6ce8, 0x7129931f, 0xc4020133, 0x71120cc5,
+ 0xc3d59ebe, 0x70fa74fc,
+ 0xc3a94590, 0x70e2cbc6, 0xc37cf5b0, 0x70cb1128, 0xc350af26, 0x70b34525,
+ 0xc32471f7, 0x709b67c0,
+ 0xc2f83e2a, 0x708378ff, 0xc2cc13c7, 0x706b78e3, 0xc29ff2d4, 0x70536771,
+ 0xc273db58, 0x703b44ad,
+ 0xc247cd5a, 0x7023109a, 0xc21bc8e1, 0x700acb3c, 0xc1efcdf3, 0x6ff27497,
+ 0xc1c3dc97, 0x6fda0cae,
+ 0xc197f4d4, 0x6fc19385, 0xc16c16b0, 0x6fa90921, 0xc1404233, 0x6f906d84,
+ 0xc1147764, 0x6f77c0b3,
+ 0xc0e8b648, 0x6f5f02b2, 0xc0bcfee7, 0x6f463383, 0xc0915148, 0x6f2d532c,
+ 0xc065ad70, 0x6f1461b0,
+ 0xc03a1368, 0x6efb5f12, 0xc00e8336, 0x6ee24b57, 0xbfe2fcdf, 0x6ec92683,
+ 0xbfb7806c, 0x6eaff099,
+ 0xbf8c0de3, 0x6e96a99d, 0xbf60a54a, 0x6e7d5193, 0xbf3546a8, 0x6e63e87f,
+ 0xbf09f205, 0x6e4a6e66,
+ 0xbedea765, 0x6e30e34a, 0xbeb366d1, 0x6e174730, 0xbe88304f, 0x6dfd9a1c,
+ 0xbe5d03e6, 0x6de3dc11,
+ 0xbe31e19b, 0x6dca0d14, 0xbe06c977, 0x6db02d29, 0xbddbbb7f, 0x6d963c54,
+ 0xbdb0b7bb, 0x6d7c3a98,
+ 0xbd85be30, 0x6d6227fa, 0xbd5acee5, 0x6d48047e, 0xbd2fe9e2, 0x6d2dd027,
+ 0xbd050f2c, 0x6d138afb,
+ 0xbcda3ecb, 0x6cf934fc, 0xbcaf78c4, 0x6cdece2f, 0xbc84bd1f, 0x6cc45698,
+ 0xbc5a0be2, 0x6ca9ce3b,
+ 0xbc2f6513, 0x6c8f351c, 0xbc04c8ba, 0x6c748b3f, 0xbbda36dd, 0x6c59d0a9,
+ 0xbbafaf82, 0x6c3f055d,
+ 0xbb8532b0, 0x6c242960, 0xbb5ac06d, 0x6c093cb6, 0xbb3058c0, 0x6bee3f62,
+ 0xbb05fbb0, 0x6bd3316a,
+ 0xbadba943, 0x6bb812d1, 0xbab16180, 0x6b9ce39b, 0xba87246d, 0x6b81a3cd,
+ 0xba5cf210, 0x6b66536b,
+ 0xba32ca71, 0x6b4af279, 0xba08ad95, 0x6b2f80fb, 0xb9de9b83, 0x6b13fef5,
+ 0xb9b49442, 0x6af86c6c,
+ 0xb98a97d8, 0x6adcc964, 0xb960a64c, 0x6ac115e2, 0xb936bfa4, 0x6aa551e9,
+ 0xb90ce3e6, 0x6a897d7d,
+ 0xb8e31319, 0x6a6d98a4, 0xb8b94d44, 0x6a51a361, 0xb88f926d, 0x6a359db9,
+ 0xb865e299, 0x6a1987b0,
+ 0xb83c3dd1, 0x69fd614a, 0xb812a41a, 0x69e12a8c, 0xb7e9157a, 0x69c4e37a,
+ 0xb7bf91f8, 0x69a88c19,
+ 0xb796199b, 0x698c246c, 0xb76cac69, 0x696fac78, 0xb7434a67, 0x69532442,
+ 0xb719f39e, 0x69368bce,
+ 0xb6f0a812, 0x6919e320, 0xb6c767ca, 0x68fd2a3d, 0xb69e32cd, 0x68e06129,
+ 0xb6750921, 0x68c387e9,
+ 0xb64beacd, 0x68a69e81, 0xb622d7d6, 0x6889a4f6, 0xb5f9d043, 0x686c9b4b,
+ 0xb5d0d41a, 0x684f8186,
+ 0xb5a7e362, 0x683257ab, 0xb57efe22, 0x68151dbe, 0xb556245e, 0x67f7d3c5,
+ 0xb52d561e, 0x67da79c3,
+ 0xb5049368, 0x67bd0fbd, 0xb4dbdc42, 0x679f95b7, 0xb4b330b3, 0x67820bb7,
+ 0xb48a90c0, 0x676471c0,
+ 0xb461fc70, 0x6746c7d8, 0xb43973ca, 0x67290e02, 0xb410f6d3, 0x670b4444,
+ 0xb3e88592, 0x66ed6aa1,
+ 0xb3c0200c, 0x66cf8120, 0xb397c649, 0x66b187c3, 0xb36f784f, 0x66937e91,
+ 0xb3473623, 0x6675658c,
+ 0xb31effcc, 0x66573cbb, 0xb2f6d550, 0x66390422, 0xb2ceb6b5, 0x661abbc5,
+ 0xb2a6a402, 0x65fc63a9,
+ 0xb27e9d3c, 0x65ddfbd3, 0xb256a26a, 0x65bf8447, 0xb22eb392, 0x65a0fd0b,
+ 0xb206d0ba, 0x65826622,
+ 0xb1def9e9, 0x6563bf92, 0xb1b72f23, 0x6545095f, 0xb18f7071, 0x6526438f,
+ 0xb167bdd7, 0x65076e25,
+ 0xb140175b, 0x64e88926, 0xb1187d05, 0x64c99498, 0xb0f0eeda, 0x64aa907f,
+ 0xb0c96ce0, 0x648b7ce0,
+ 0xb0a1f71d, 0x646c59bf, 0xb07a8d97, 0x644d2722, 0xb0533055, 0x642de50d,
+ 0xb02bdf5c, 0x640e9386,
+ 0xb0049ab3, 0x63ef3290, 0xafdd625f, 0x63cfc231, 0xafb63667, 0x63b0426d,
+ 0xaf8f16d1, 0x6390b34a,
+ 0xaf6803a2, 0x637114cc, 0xaf40fce1, 0x635166f9, 0xaf1a0293, 0x6331a9d4,
+ 0xaef314c0, 0x6311dd64,
+ 0xaecc336c, 0x62f201ac, 0xaea55e9e, 0x62d216b3, 0xae7e965b, 0x62b21c7b,
+ 0xae57daab, 0x6292130c,
+ 0xae312b92, 0x6271fa69, 0xae0a8916, 0x6251d298, 0xade3f33e, 0x62319b9d,
+ 0xadbd6a10, 0x6211557e,
+ 0xad96ed92, 0x61f1003f, 0xad707dc8, 0x61d09be5, 0xad4a1aba, 0x61b02876,
+ 0xad23c46e, 0x618fa5f7,
+ 0xacfd7ae8, 0x616f146c, 0xacd73e30, 0x614e73da, 0xacb10e4b, 0x612dc447,
+ 0xac8aeb3e, 0x610d05b7,
+ 0xac64d510, 0x60ec3830, 0xac3ecbc7, 0x60cb5bb7, 0xac18cf69, 0x60aa7050,
+ 0xabf2dffb, 0x60897601,
+ 0xabccfd83, 0x60686ccf, 0xaba72807, 0x604754bf, 0xab815f8d, 0x60262dd6,
+ 0xab5ba41a, 0x6004f819,
+ 0xab35f5b5, 0x5fe3b38d, 0xab105464, 0x5fc26038, 0xaaeac02c, 0x5fa0fe1f,
+ 0xaac53912, 0x5f7f8d46,
+ 0xaa9fbf1e, 0x5f5e0db3, 0xaa7a5253, 0x5f3c7f6b, 0xaa54f2ba, 0x5f1ae274,
+ 0xaa2fa056, 0x5ef936d1,
+ 0xaa0a5b2e, 0x5ed77c8a, 0xa9e52347, 0x5eb5b3a2, 0xa9bff8a8, 0x5e93dc1f,
+ 0xa99adb56, 0x5e71f606,
+ 0xa975cb57, 0x5e50015d, 0xa950c8b0, 0x5e2dfe29, 0xa92bd367, 0x5e0bec6e,
+ 0xa906eb82, 0x5de9cc33,
+ 0xa8e21106, 0x5dc79d7c, 0xa8bd43fa, 0x5da5604f, 0xa8988463, 0x5d8314b1,
+ 0xa873d246, 0x5d60baa7,
+ 0xa84f2daa, 0x5d3e5237, 0xa82a9693, 0x5d1bdb65, 0xa8060d08, 0x5cf95638,
+ 0xa7e1910f, 0x5cd6c2b5,
+ 0xa7bd22ac, 0x5cb420e0, 0xa798c1e5, 0x5c9170bf, 0xa7746ec0, 0x5c6eb258,
+ 0xa7502943, 0x5c4be5b0,
+ 0xa72bf174, 0x5c290acc, 0xa707c757, 0x5c0621b2, 0xa6e3aaf2, 0x5be32a67,
+ 0xa6bf9c4b, 0x5bc024f0,
+ 0xa69b9b68, 0x5b9d1154, 0xa677a84e, 0x5b79ef96, 0xa653c303, 0x5b56bfbd,
+ 0xa62feb8b, 0x5b3381ce,
+ 0xa60c21ee, 0x5b1035cf, 0xa5e8662f, 0x5aecdbc5, 0xa5c4b855, 0x5ac973b5,
+ 0xa5a11866, 0x5aa5fda5,
+ 0xa57d8666, 0x5a82799a, 0xa55a025b, 0x5a5ee79a, 0xa5368c4b, 0x5a3b47ab,
+ 0xa513243b, 0x5a1799d1,
+ 0xa4efca31, 0x59f3de12, 0xa4cc7e32, 0x59d01475, 0xa4a94043, 0x59ac3cfd,
+ 0xa486106a, 0x598857b2,
+ 0xa462eeac, 0x59646498, 0xa43fdb10, 0x594063b5, 0xa41cd599, 0x591c550e,
+ 0xa3f9de4e, 0x58f838a9,
+ 0xa3d6f534, 0x58d40e8c, 0xa3b41a50, 0x58afd6bd, 0xa3914da8, 0x588b9140,
+ 0xa36e8f41, 0x58673e1b,
+ 0xa34bdf20, 0x5842dd54, 0xa3293d4b, 0x581e6ef1, 0xa306a9c8, 0x57f9f2f8,
+ 0xa2e4249b, 0x57d5696d,
+ 0xa2c1adc9, 0x57b0d256, 0xa29f4559, 0x578c2dba, 0xa27ceb4f, 0x57677b9d,
+ 0xa25a9fb1, 0x5742bc06,
+ 0xa2386284, 0x571deefa, 0xa21633cd, 0x56f9147e, 0xa1f41392, 0x56d42c99,
+ 0xa1d201d7, 0x56af3750,
+ 0xa1affea3, 0x568a34a9, 0xa18e09fa, 0x566524aa, 0xa16c23e1, 0x56400758,
+ 0xa14a4c5e, 0x561adcb9,
+ 0xa1288376, 0x55f5a4d2, 0xa106c92f, 0x55d05faa, 0xa0e51d8c, 0x55ab0d46,
+ 0xa0c38095, 0x5585adad,
+ 0xa0a1f24d, 0x556040e2, 0xa08072ba, 0x553ac6ee, 0xa05f01e1, 0x55153fd4,
+ 0xa03d9fc8, 0x54efab9c,
+ 0xa01c4c73, 0x54ca0a4b, 0x9ffb07e7, 0x54a45be6, 0x9fd9d22a, 0x547ea073,
+ 0x9fb8ab41, 0x5458d7f9,
+ 0x9f979331, 0x5433027d, 0x9f7689ff, 0x540d2005, 0x9f558fb0, 0x53e73097,
+ 0x9f34a449, 0x53c13439,
+ 0x9f13c7d0, 0x539b2af0, 0x9ef2fa49, 0x537514c2, 0x9ed23bb9, 0x534ef1b5,
+ 0x9eb18c26, 0x5328c1d0,
+ 0x9e90eb94, 0x53028518, 0x9e705a09, 0x52dc3b92, 0x9e4fd78a, 0x52b5e546,
+ 0x9e2f641b, 0x528f8238,
+ 0x9e0effc1, 0x5269126e, 0x9deeaa82, 0x524295f0, 0x9dce6463, 0x521c0cc2,
+ 0x9dae2d68, 0x51f576ea,
+ 0x9d8e0597, 0x51ced46e, 0x9d6decf4, 0x51a82555, 0x9d4de385, 0x518169a5,
+ 0x9d2de94d, 0x515aa162,
+ 0x9d0dfe54, 0x5133cc94, 0x9cee229c, 0x510ceb40, 0x9cce562c, 0x50e5fd6d,
+ 0x9cae9907, 0x50bf031f,
+ 0x9c8eeb34, 0x5097fc5e, 0x9c6f4cb6, 0x5070e92f, 0x9c4fbd93, 0x5049c999,
+ 0x9c303dcf, 0x50229da1,
+ 0x9c10cd70, 0x4ffb654d, 0x9bf16c7a, 0x4fd420a4, 0x9bd21af3, 0x4faccfab,
+ 0x9bb2d8de, 0x4f857269,
+ 0x9b93a641, 0x4f5e08e3, 0x9b748320, 0x4f369320, 0x9b556f81, 0x4f0f1126,
+ 0x9b366b68, 0x4ee782fb,
+ 0x9b1776da, 0x4ebfe8a5, 0x9af891db, 0x4e984229, 0x9ad9bc71, 0x4e708f8f,
+ 0x9abaf6a1, 0x4e48d0dd,
+ 0x9a9c406e, 0x4e210617, 0x9a7d99de, 0x4df92f46, 0x9a5f02f5, 0x4dd14c6e,
+ 0x9a407bb9, 0x4da95d96,
+ 0x9a22042d, 0x4d8162c4, 0x9a039c57, 0x4d595bfe, 0x99e5443b, 0x4d31494b,
+ 0x99c6fbde, 0x4d092ab0,
+ 0x99a8c345, 0x4ce10034, 0x998a9a74, 0x4cb8c9dd, 0x996c816f, 0x4c9087b1,
+ 0x994e783d, 0x4c6839b7,
+ 0x99307ee0, 0x4c3fdff4, 0x9912955f, 0x4c177a6e, 0x98f4bbbc, 0x4bef092d,
+ 0x98d6f1fe, 0x4bc68c36,
+ 0x98b93828, 0x4b9e0390, 0x989b8e40, 0x4b756f40, 0x987df449, 0x4b4ccf4d,
+ 0x98606a49, 0x4b2423be,
+ 0x9842f043, 0x4afb6c98, 0x9825863d, 0x4ad2a9e2, 0x98082c3b, 0x4aa9dba2,
+ 0x97eae242, 0x4a8101de,
+ 0x97cda855, 0x4a581c9e, 0x97b07e7a, 0x4a2f2be6, 0x979364b5, 0x4a062fbd,
+ 0x97765b0a, 0x49dd282a,
+ 0x9759617f, 0x49b41533, 0x973c7817, 0x498af6df, 0x971f9ed7, 0x4961cd33,
+ 0x9702d5c3, 0x49389836,
+ 0x96e61ce0, 0x490f57ee, 0x96c97432, 0x48e60c62, 0x96acdbbe, 0x48bcb599,
+ 0x96905388, 0x48935397,
+ 0x9673db94, 0x4869e665, 0x965773e7, 0x48406e08, 0x963b1c86, 0x4816ea86,
+ 0x961ed574, 0x47ed5be6,
+ 0x96029eb6, 0x47c3c22f, 0x95e67850, 0x479a1d67, 0x95ca6247, 0x47706d93,
+ 0x95ae5c9f, 0x4746b2bc,
+ 0x9592675c, 0x471cece7, 0x95768283, 0x46f31c1a, 0x955aae17, 0x46c9405c,
+ 0x953eea1e, 0x469f59b4,
+ 0x9523369c, 0x46756828, 0x95079394, 0x464b6bbe, 0x94ec010b, 0x4621647d,
+ 0x94d07f05, 0x45f7526b,
+ 0x94b50d87, 0x45cd358f, 0x9499ac95, 0x45a30df0, 0x947e5c33, 0x4578db93,
+ 0x94631c65, 0x454e9e80,
+ 0x9447ed2f, 0x452456bd, 0x942cce96, 0x44fa0450, 0x9411c09e, 0x44cfa740,
+ 0x93f6c34a, 0x44a53f93,
+ 0x93dbd6a0, 0x447acd50, 0x93c0faa3, 0x4450507e, 0x93a62f57, 0x4425c923,
+ 0x938b74c1, 0x43fb3746,
+ 0x9370cae4, 0x43d09aed, 0x935631c5, 0x43a5f41e, 0x933ba968, 0x437b42e1,
+ 0x932131d1, 0x4350873c,
+ 0x9306cb04, 0x4325c135, 0x92ec7505, 0x42faf0d4, 0x92d22fd9, 0x42d0161e,
+ 0x92b7fb82, 0x42a5311b,
+ 0x929dd806, 0x427a41d0, 0x9283c568, 0x424f4845, 0x9269c3ac, 0x42244481,
+ 0x924fd2d7, 0x41f93689,
+ 0x9235f2ec, 0x41ce1e65, 0x921c23ef, 0x41a2fc1a, 0x920265e4, 0x4177cfb1,
+ 0x91e8b8d0, 0x414c992f,
+ 0x91cf1cb6, 0x4121589b, 0x91b5919a, 0x40f60dfb, 0x919c1781, 0x40cab958,
+ 0x9182ae6d, 0x409f5ab6,
+ 0x91695663, 0x4073f21d, 0x91500f67, 0x40487f94, 0x9136d97d, 0x401d0321,
+ 0x911db4a9, 0x3ff17cca,
+ 0x9104a0ee, 0x3fc5ec98, 0x90eb9e50, 0x3f9a5290, 0x90d2acd4, 0x3f6eaeb8,
+ 0x90b9cc7d, 0x3f430119,
+ 0x90a0fd4e, 0x3f1749b8, 0x90883f4d, 0x3eeb889c, 0x906f927c, 0x3ebfbdcd,
+ 0x9056f6df, 0x3e93e950,
+ 0x903e6c7b, 0x3e680b2c, 0x9025f352, 0x3e3c2369, 0x900d8b69, 0x3e10320d,
+ 0x8ff534c4, 0x3de4371f,
+ 0x8fdcef66, 0x3db832a6, 0x8fc4bb53, 0x3d8c24a8, 0x8fac988f, 0x3d600d2c,
+ 0x8f94871d, 0x3d33ec39,
+ 0x8f7c8701, 0x3d07c1d6, 0x8f649840, 0x3cdb8e09, 0x8f4cbadb, 0x3caf50da,
+ 0x8f34eed8, 0x3c830a50,
+ 0x8f1d343a, 0x3c56ba70, 0x8f058b04, 0x3c2a6142, 0x8eedf33b, 0x3bfdfecd,
+ 0x8ed66ce1, 0x3bd19318,
+ 0x8ebef7fb, 0x3ba51e29, 0x8ea7948c, 0x3b78a007, 0x8e904298, 0x3b4c18ba,
+ 0x8e790222, 0x3b1f8848,
+ 0x8e61d32e, 0x3af2eeb7, 0x8e4ab5bf, 0x3ac64c0f, 0x8e33a9da, 0x3a99a057,
+ 0x8e1caf80, 0x3a6ceb96,
+ 0x8e05c6b7, 0x3a402dd2, 0x8deeef82, 0x3a136712, 0x8dd829e4, 0x39e6975e,
+ 0x8dc175e0, 0x39b9bebc,
+ 0x8daad37b, 0x398cdd32, 0x8d9442b8, 0x395ff2c9, 0x8d7dc399, 0x3932ff87,
+ 0x8d675623, 0x39060373,
+ 0x8d50fa59, 0x38d8fe93, 0x8d3ab03f, 0x38abf0ef, 0x8d2477d8, 0x387eda8e,
+ 0x8d0e5127, 0x3851bb77,
+ 0x8cf83c30, 0x382493b0, 0x8ce238f6, 0x37f76341, 0x8ccc477d, 0x37ca2a30,
+ 0x8cb667c8, 0x379ce885,
+ 0x8ca099da, 0x376f9e46, 0x8c8addb7, 0x37424b7b, 0x8c753362, 0x3714f02a,
+ 0x8c5f9ade, 0x36e78c5b,
+ 0x8c4a142f, 0x36ba2014, 0x8c349f58, 0x368cab5c, 0x8c1f3c5d, 0x365f2e3b,
+ 0x8c09eb40, 0x3631a8b8,
+ 0x8bf4ac05, 0x36041ad9, 0x8bdf7eb0, 0x35d684a6, 0x8bca6343, 0x35a8e625,
+ 0x8bb559c1, 0x357b3f5d,
+ 0x8ba0622f, 0x354d9057, 0x8b8b7c8f, 0x351fd918, 0x8b76a8e4, 0x34f219a8,
+ 0x8b61e733, 0x34c4520d,
+ 0x8b4d377c, 0x34968250, 0x8b3899c6, 0x3468aa76, 0x8b240e11, 0x343aca87,
+ 0x8b0f9462, 0x340ce28b,
+ 0x8afb2cbb, 0x33def287, 0x8ae6d720, 0x33b0fa84, 0x8ad29394, 0x3382fa88,
+ 0x8abe6219, 0x3354f29b,
+ 0x8aaa42b4, 0x3326e2c3, 0x8a963567, 0x32f8cb07, 0x8a823a36, 0x32caab6f,
+ 0x8a6e5123, 0x329c8402,
+ 0x8a5a7a31, 0x326e54c7, 0x8a46b564, 0x32401dc6, 0x8a3302be, 0x3211df04,
+ 0x8a1f6243, 0x31e39889,
+ 0x8a0bd3f5, 0x31b54a5e, 0x89f857d8, 0x3186f487, 0x89e4edef, 0x3158970e,
+ 0x89d1963c, 0x312a31f8,
+ 0x89be50c3, 0x30fbc54d, 0x89ab1d87, 0x30cd5115, 0x8997fc8a, 0x309ed556,
+ 0x8984edcf, 0x30705217,
+ 0x8971f15a, 0x3041c761, 0x895f072e, 0x30133539, 0x894c2f4c, 0x2fe49ba7,
+ 0x893969b9, 0x2fb5fab2,
+ 0x8926b677, 0x2f875262, 0x89141589, 0x2f58a2be, 0x890186f2, 0x2f29ebcc,
+ 0x88ef0ab4, 0x2efb2d95,
+ 0x88dca0d3, 0x2ecc681e, 0x88ca4951, 0x2e9d9b70, 0x88b80432, 0x2e6ec792,
+ 0x88a5d177, 0x2e3fec8b,
+ 0x8893b125, 0x2e110a62, 0x8881a33d, 0x2de2211e, 0x886fa7c2, 0x2db330c7,
+ 0x885dbeb8, 0x2d843964,
+ 0x884be821, 0x2d553afc, 0x883a23ff, 0x2d263596, 0x88287256, 0x2cf72939,
+ 0x8816d327, 0x2cc815ee,
+ 0x88054677, 0x2c98fbba, 0x87f3cc48, 0x2c69daa6, 0x87e2649b, 0x2c3ab2b9,
+ 0x87d10f75, 0x2c0b83fa,
+ 0x87bfccd7, 0x2bdc4e6f, 0x87ae9cc5, 0x2bad1221, 0x879d7f41, 0x2b7dcf17,
+ 0x878c744d, 0x2b4e8558,
+ 0x877b7bec, 0x2b1f34eb, 0x876a9621, 0x2aefddd8, 0x8759c2ef, 0x2ac08026,
+ 0x87490258, 0x2a911bdc,
+ 0x8738545e, 0x2a61b101, 0x8727b905, 0x2a323f9e, 0x8717304e, 0x2a02c7b8,
+ 0x8706ba3d, 0x29d34958,
+ 0x86f656d3, 0x29a3c485, 0x86e60614, 0x29743946, 0x86d5c802, 0x2944a7a2,
+ 0x86c59c9f, 0x29150fa1,
+ 0x86b583ee, 0x28e5714b, 0x86a57df2, 0x28b5cca5, 0x86958aac, 0x288621b9,
+ 0x8685aa20, 0x2856708d,
+ 0x8675dc4f, 0x2826b928, 0x8666213c, 0x27f6fb92, 0x865678eb, 0x27c737d3,
+ 0x8646e35c, 0x27976df1,
+ 0x86376092, 0x27679df4, 0x8627f091, 0x2737c7e3, 0x86189359, 0x2707ebc7,
+ 0x860948ef, 0x26d809a5,
+ 0x85fa1153, 0x26a82186, 0x85eaec88, 0x26783370, 0x85dbda91, 0x26483f6c,
+ 0x85ccdb70, 0x26184581,
+ 0x85bdef28, 0x25e845b6, 0x85af15b9, 0x25b84012, 0x85a04f28, 0x2588349d,
+ 0x85919b76, 0x2558235f,
+ 0x8582faa5, 0x25280c5e, 0x85746cb8, 0x24f7efa2, 0x8565f1b0, 0x24c7cd33,
+ 0x85578991, 0x2497a517,
+ 0x8549345c, 0x24677758, 0x853af214, 0x243743fa, 0x852cc2bb, 0x24070b08,
+ 0x851ea652, 0x23d6cc87,
+ 0x85109cdd, 0x23a6887f, 0x8502a65c, 0x23763ef7, 0x84f4c2d4, 0x2345eff8,
+ 0x84e6f244, 0x23159b88,
+ 0x84d934b1, 0x22e541af, 0x84cb8a1b, 0x22b4e274, 0x84bdf286, 0x22847de0,
+ 0x84b06df2, 0x225413f8,
+ 0x84a2fc62, 0x2223a4c5, 0x84959dd9, 0x21f3304f, 0x84885258, 0x21c2b69c,
+ 0x847b19e1, 0x219237b5,
+ 0x846df477, 0x2161b3a0, 0x8460e21a, 0x21312a65, 0x8453e2cf, 0x21009c0c,
+ 0x8446f695, 0x20d0089c,
+ 0x843a1d70, 0x209f701c, 0x842d5762, 0x206ed295, 0x8420a46c, 0x203e300d,
+ 0x84140490, 0x200d888d,
+ 0x840777d0, 0x1fdcdc1b, 0x83fafe2e, 0x1fac2abf, 0x83ee97ad, 0x1f7b7481,
+ 0x83e2444d, 0x1f4ab968,
+ 0x83d60412, 0x1f19f97b, 0x83c9d6fc, 0x1ee934c3, 0x83bdbd0e, 0x1eb86b46,
+ 0x83b1b649, 0x1e879d0d,
+ 0x83a5c2b0, 0x1e56ca1e, 0x8399e244, 0x1e25f282, 0x838e1507, 0x1df5163f,
+ 0x83825afb, 0x1dc4355e,
+ 0x8376b422, 0x1d934fe5, 0x836b207d, 0x1d6265dd, 0x835fa00f, 0x1d31774d,
+ 0x835432d8, 0x1d00843d,
+ 0x8348d8dc, 0x1ccf8cb3, 0x833d921b, 0x1c9e90b8, 0x83325e97, 0x1c6d9053,
+ 0x83273e52, 0x1c3c8b8c,
+ 0x831c314e, 0x1c0b826a, 0x8311378d, 0x1bda74f6, 0x83065110, 0x1ba96335,
+ 0x82fb7dd8, 0x1b784d30,
+ 0x82f0bde8, 0x1b4732ef, 0x82e61141, 0x1b161479, 0x82db77e5, 0x1ae4f1d6,
+ 0x82d0f1d5, 0x1ab3cb0d,
+ 0x82c67f14, 0x1a82a026, 0x82bc1fa2, 0x1a517128, 0x82b1d381, 0x1a203e1b,
+ 0x82a79ab3, 0x19ef0707,
+ 0x829d753a, 0x19bdcbf3, 0x82936317, 0x198c8ce7, 0x8289644b, 0x195b49ea,
+ 0x827f78d8, 0x192a0304,
+ 0x8275a0c0, 0x18f8b83c, 0x826bdc04, 0x18c7699b, 0x82622aa6, 0x18961728,
+ 0x82588ca7, 0x1864c0ea,
+ 0x824f0208, 0x183366e9, 0x82458acc, 0x1802092c, 0x823c26f3, 0x17d0a7bc,
+ 0x8232d67f, 0x179f429f,
+ 0x82299971, 0x176dd9de, 0x82206fcc, 0x173c6d80, 0x82175990, 0x170afd8d,
+ 0x820e56be, 0x16d98a0c,
+ 0x82056758, 0x16a81305, 0x81fc8b60, 0x1676987f, 0x81f3c2d7, 0x16451a83,
+ 0x81eb0dbe, 0x16139918,
+ 0x81e26c16, 0x15e21445, 0x81d9dde1, 0x15b08c12, 0x81d16321, 0x157f0086,
+ 0x81c8fbd6, 0x154d71aa,
+ 0x81c0a801, 0x151bdf86, 0x81b867a5, 0x14ea4a1f, 0x81b03ac2, 0x14b8b17f,
+ 0x81a82159, 0x148715ae,
+ 0x81a01b6d, 0x145576b1, 0x819828fd, 0x1423d492, 0x81904a0c, 0x13f22f58,
+ 0x81887e9a, 0x13c0870a,
+ 0x8180c6a9, 0x138edbb1, 0x8179223a, 0x135d2d53, 0x8171914e, 0x132b7bf9,
+ 0x816a13e6, 0x12f9c7aa,
+ 0x8162aa04, 0x12c8106f, 0x815b53a8, 0x1296564d, 0x815410d4, 0x1264994e,
+ 0x814ce188, 0x1232d979,
+ 0x8145c5c7, 0x120116d5, 0x813ebd90, 0x11cf516a, 0x8137c8e6, 0x119d8941,
+ 0x8130e7c9, 0x116bbe60,
+ 0x812a1a3a, 0x1139f0cf, 0x8123603a, 0x11082096, 0x811cb9ca, 0x10d64dbd,
+ 0x811626ec, 0x10a4784b,
+ 0x810fa7a0, 0x1072a048, 0x81093be8, 0x1040c5bb, 0x8102e3c4, 0x100ee8ad,
+ 0x80fc9f35, 0xfdd0926,
+ 0x80f66e3c, 0xfab272b, 0x80f050db, 0xf7942c7, 0x80ea4712, 0xf475bff,
+ 0x80e450e2, 0xf1572dc,
+ 0x80de6e4c, 0xee38766, 0x80d89f51, 0xeb199a4, 0x80d2e3f2, 0xe7fa99e,
+ 0x80cd3c2f, 0xe4db75b,
+ 0x80c7a80a, 0xe1bc2e4, 0x80c22784, 0xde9cc40, 0x80bcba9d, 0xdb7d376,
+ 0x80b76156, 0xd85d88f,
+ 0x80b21baf, 0xd53db92, 0x80ace9ab, 0xd21dc87, 0x80a7cb49, 0xcefdb76,
+ 0x80a2c08b, 0xcbdd865,
+ 0x809dc971, 0xc8bd35e, 0x8098e5fb, 0xc59cc68, 0x8094162c, 0xc27c389,
+ 0x808f5a02, 0xbf5b8cb,
+ 0x808ab180, 0xbc3ac35, 0x80861ca6, 0xb919dcf, 0x80819b74, 0xb5f8d9f,
+ 0x807d2dec, 0xb2d7baf,
+ 0x8078d40d, 0xafb6805, 0x80748dd9, 0xac952aa, 0x80705b50, 0xa973ba5,
+ 0x806c3c74, 0xa6522fe,
+ 0x80683143, 0xa3308bd, 0x806439c0, 0xa00ece8, 0x806055eb, 0x9cecf89,
+ 0x805c85c4, 0x99cb0a7,
+ 0x8058c94c, 0x96a9049, 0x80552084, 0x9386e78, 0x80518b6b, 0x9064b3a,
+ 0x804e0a04, 0x8d42699,
+ 0x804a9c4d, 0x8a2009a, 0x80474248, 0x86fd947, 0x8043fbf6, 0x83db0a7,
+ 0x8040c956, 0x80b86c2,
+ 0x803daa6a, 0x7d95b9e, 0x803a9f31, 0x7a72f45, 0x8037a7ac, 0x77501be,
+ 0x8034c3dd, 0x742d311,
+ 0x8031f3c2, 0x710a345, 0x802f375d, 0x6de7262, 0x802c8ead, 0x6ac406f,
+ 0x8029f9b4, 0x67a0d76,
+ 0x80277872, 0x647d97c, 0x80250ae7, 0x615a48b, 0x8022b114, 0x5e36ea9,
+ 0x80206af8, 0x5b137df,
+ 0x801e3895, 0x57f0035, 0x801c19ea, 0x54cc7b1, 0x801a0ef8, 0x51a8e5c,
+ 0x801817bf, 0x4e8543e,
+ 0x80163440, 0x4b6195d, 0x8014647b, 0x483ddc3, 0x8012a86f, 0x451a177,
+ 0x8011001f, 0x41f6480,
+ 0x800f6b88, 0x3ed26e6, 0x800deaad, 0x3bae8b2, 0x800c7d8c, 0x388a9ea,
+ 0x800b2427, 0x3566a96,
+ 0x8009de7e, 0x3242abf, 0x8008ac90, 0x2f1ea6c, 0x80078e5e, 0x2bfa9a4,
+ 0x800683e8, 0x28d6870,
+ 0x80058d2f, 0x25b26d7, 0x8004aa32, 0x228e4e2, 0x8003daf1, 0x1f6a297,
+ 0x80031f6d, 0x1c45ffe,
+ 0x800277a6, 0x1921d20, 0x8001e39b, 0x15fda03, 0x8001634e, 0x12d96b1,
+ 0x8000f6bd, 0xfb5330,
+ 0x80009dea, 0xc90f88, 0x800058d4, 0x96cbc1, 0x8000277a, 0x6487e3,
+ 0x800009df, 0x3243f5,
+ 0x80000000, 0x0, 0x800009df, 0xffcdbc0b, 0x8000277a, 0xff9b781d, 0x800058d4,
+ 0xff69343f,
+ 0x80009dea, 0xff36f078, 0x8000f6bd, 0xff04acd0, 0x8001634e, 0xfed2694f,
+ 0x8001e39b, 0xfea025fd,
+ 0x800277a6, 0xfe6de2e0, 0x80031f6d, 0xfe3ba002, 0x8003daf1, 0xfe095d69,
+ 0x8004aa32, 0xfdd71b1e,
+ 0x80058d2f, 0xfda4d929, 0x800683e8, 0xfd729790, 0x80078e5e, 0xfd40565c,
+ 0x8008ac90, 0xfd0e1594,
+ 0x8009de7e, 0xfcdbd541, 0x800b2427, 0xfca9956a, 0x800c7d8c, 0xfc775616,
+ 0x800deaad, 0xfc45174e,
+ 0x800f6b88, 0xfc12d91a, 0x8011001f, 0xfbe09b80, 0x8012a86f, 0xfbae5e89,
+ 0x8014647b, 0xfb7c223d,
+ 0x80163440, 0xfb49e6a3, 0x801817bf, 0xfb17abc2, 0x801a0ef8, 0xfae571a4,
+ 0x801c19ea, 0xfab3384f,
+ 0x801e3895, 0xfa80ffcb, 0x80206af8, 0xfa4ec821, 0x8022b114, 0xfa1c9157,
+ 0x80250ae7, 0xf9ea5b75,
+ 0x80277872, 0xf9b82684, 0x8029f9b4, 0xf985f28a, 0x802c8ead, 0xf953bf91,
+ 0x802f375d, 0xf9218d9e,
+ 0x8031f3c2, 0xf8ef5cbb, 0x8034c3dd, 0xf8bd2cef, 0x8037a7ac, 0xf88afe42,
+ 0x803a9f31, 0xf858d0bb,
+ 0x803daa6a, 0xf826a462, 0x8040c956, 0xf7f4793e, 0x8043fbf6, 0xf7c24f59,
+ 0x80474248, 0xf79026b9,
+ 0x804a9c4d, 0xf75dff66, 0x804e0a04, 0xf72bd967, 0x80518b6b, 0xf6f9b4c6,
+ 0x80552084, 0xf6c79188,
+ 0x8058c94c, 0xf6956fb7, 0x805c85c4, 0xf6634f59, 0x806055eb, 0xf6313077,
+ 0x806439c0, 0xf5ff1318,
+ 0x80683143, 0xf5ccf743, 0x806c3c74, 0xf59add02, 0x80705b50, 0xf568c45b,
+ 0x80748dd9, 0xf536ad56,
+ 0x8078d40d, 0xf50497fb, 0x807d2dec, 0xf4d28451, 0x80819b74, 0xf4a07261,
+ 0x80861ca6, 0xf46e6231,
+ 0x808ab180, 0xf43c53cb, 0x808f5a02, 0xf40a4735, 0x8094162c, 0xf3d83c77,
+ 0x8098e5fb, 0xf3a63398,
+ 0x809dc971, 0xf3742ca2, 0x80a2c08b, 0xf342279b, 0x80a7cb49, 0xf310248a,
+ 0x80ace9ab, 0xf2de2379,
+ 0x80b21baf, 0xf2ac246e, 0x80b76156, 0xf27a2771, 0x80bcba9d, 0xf2482c8a,
+ 0x80c22784, 0xf21633c0,
+ 0x80c7a80a, 0xf1e43d1c, 0x80cd3c2f, 0xf1b248a5, 0x80d2e3f2, 0xf1805662,
+ 0x80d89f51, 0xf14e665c,
+ 0x80de6e4c, 0xf11c789a, 0x80e450e2, 0xf0ea8d24, 0x80ea4712, 0xf0b8a401,
+ 0x80f050db, 0xf086bd39,
+ 0x80f66e3c, 0xf054d8d5, 0x80fc9f35, 0xf022f6da, 0x8102e3c4, 0xeff11753,
+ 0x81093be8, 0xefbf3a45,
+ 0x810fa7a0, 0xef8d5fb8, 0x811626ec, 0xef5b87b5, 0x811cb9ca, 0xef29b243,
+ 0x8123603a, 0xeef7df6a,
+ 0x812a1a3a, 0xeec60f31, 0x8130e7c9, 0xee9441a0, 0x8137c8e6, 0xee6276bf,
+ 0x813ebd90, 0xee30ae96,
+ 0x8145c5c7, 0xedfee92b, 0x814ce188, 0xedcd2687, 0x815410d4, 0xed9b66b2,
+ 0x815b53a8, 0xed69a9b3,
+ 0x8162aa04, 0xed37ef91, 0x816a13e6, 0xed063856, 0x8171914e, 0xecd48407,
+ 0x8179223a, 0xeca2d2ad,
+ 0x8180c6a9, 0xec71244f, 0x81887e9a, 0xec3f78f6, 0x81904a0c, 0xec0dd0a8,
+ 0x819828fd, 0xebdc2b6e,
+ 0x81a01b6d, 0xebaa894f, 0x81a82159, 0xeb78ea52, 0x81b03ac2, 0xeb474e81,
+ 0x81b867a5, 0xeb15b5e1,
+ 0x81c0a801, 0xeae4207a, 0x81c8fbd6, 0xeab28e56, 0x81d16321, 0xea80ff7a,
+ 0x81d9dde1, 0xea4f73ee,
+ 0x81e26c16, 0xea1debbb, 0x81eb0dbe, 0xe9ec66e8, 0x81f3c2d7, 0xe9bae57d,
+ 0x81fc8b60, 0xe9896781,
+ 0x82056758, 0xe957ecfb, 0x820e56be, 0xe92675f4, 0x82175990, 0xe8f50273,
+ 0x82206fcc, 0xe8c39280,
+ 0x82299971, 0xe8922622, 0x8232d67f, 0xe860bd61, 0x823c26f3, 0xe82f5844,
+ 0x82458acc, 0xe7fdf6d4,
+ 0x824f0208, 0xe7cc9917, 0x82588ca7, 0xe79b3f16, 0x82622aa6, 0xe769e8d8,
+ 0x826bdc04, 0xe7389665,
+ 0x8275a0c0, 0xe70747c4, 0x827f78d8, 0xe6d5fcfc, 0x8289644b, 0xe6a4b616,
+ 0x82936317, 0xe6737319,
+ 0x829d753a, 0xe642340d, 0x82a79ab3, 0xe610f8f9, 0x82b1d381, 0xe5dfc1e5,
+ 0x82bc1fa2, 0xe5ae8ed8,
+ 0x82c67f14, 0xe57d5fda, 0x82d0f1d5, 0xe54c34f3, 0x82db77e5, 0xe51b0e2a,
+ 0x82e61141, 0xe4e9eb87,
+ 0x82f0bde8, 0xe4b8cd11, 0x82fb7dd8, 0xe487b2d0, 0x83065110, 0xe4569ccb,
+ 0x8311378d, 0xe4258b0a,
+ 0x831c314e, 0xe3f47d96, 0x83273e52, 0xe3c37474, 0x83325e97, 0xe3926fad,
+ 0x833d921b, 0xe3616f48,
+ 0x8348d8dc, 0xe330734d, 0x835432d8, 0xe2ff7bc3, 0x835fa00f, 0xe2ce88b3,
+ 0x836b207d, 0xe29d9a23,
+ 0x8376b422, 0xe26cb01b, 0x83825afb, 0xe23bcaa2, 0x838e1507, 0xe20ae9c1,
+ 0x8399e244, 0xe1da0d7e,
+ 0x83a5c2b0, 0xe1a935e2, 0x83b1b649, 0xe17862f3, 0x83bdbd0e, 0xe14794ba,
+ 0x83c9d6fc, 0xe116cb3d,
+ 0x83d60412, 0xe0e60685, 0x83e2444d, 0xe0b54698, 0x83ee97ad, 0xe0848b7f,
+ 0x83fafe2e, 0xe053d541,
+ 0x840777d0, 0xe02323e5, 0x84140490, 0xdff27773, 0x8420a46c, 0xdfc1cff3,
+ 0x842d5762, 0xdf912d6b,
+ 0x843a1d70, 0xdf608fe4, 0x8446f695, 0xdf2ff764, 0x8453e2cf, 0xdeff63f4,
+ 0x8460e21a, 0xdeced59b,
+ 0x846df477, 0xde9e4c60, 0x847b19e1, 0xde6dc84b, 0x84885258, 0xde3d4964,
+ 0x84959dd9, 0xde0ccfb1,
+ 0x84a2fc62, 0xdddc5b3b, 0x84b06df2, 0xddabec08, 0x84bdf286, 0xdd7b8220,
+ 0x84cb8a1b, 0xdd4b1d8c,
+ 0x84d934b1, 0xdd1abe51, 0x84e6f244, 0xdcea6478, 0x84f4c2d4, 0xdcba1008,
+ 0x8502a65c, 0xdc89c109,
+ 0x85109cdd, 0xdc597781, 0x851ea652, 0xdc293379, 0x852cc2bb, 0xdbf8f4f8,
+ 0x853af214, 0xdbc8bc06,
+ 0x8549345c, 0xdb9888a8, 0x85578991, 0xdb685ae9, 0x8565f1b0, 0xdb3832cd,
+ 0x85746cb8, 0xdb08105e,
+ 0x8582faa5, 0xdad7f3a2, 0x85919b76, 0xdaa7dca1, 0x85a04f28, 0xda77cb63,
+ 0x85af15b9, 0xda47bfee,
+ 0x85bdef28, 0xda17ba4a, 0x85ccdb70, 0xd9e7ba7f, 0x85dbda91, 0xd9b7c094,
+ 0x85eaec88, 0xd987cc90,
+ 0x85fa1153, 0xd957de7a, 0x860948ef, 0xd927f65b, 0x86189359, 0xd8f81439,
+ 0x8627f091, 0xd8c8381d,
+ 0x86376092, 0xd898620c, 0x8646e35c, 0xd868920f, 0x865678eb, 0xd838c82d,
+ 0x8666213c, 0xd809046e,
+ 0x8675dc4f, 0xd7d946d8, 0x8685aa20, 0xd7a98f73, 0x86958aac, 0xd779de47,
+ 0x86a57df2, 0xd74a335b,
+ 0x86b583ee, 0xd71a8eb5, 0x86c59c9f, 0xd6eaf05f, 0x86d5c802, 0xd6bb585e,
+ 0x86e60614, 0xd68bc6ba,
+ 0x86f656d3, 0xd65c3b7b, 0x8706ba3d, 0xd62cb6a8, 0x8717304e, 0xd5fd3848,
+ 0x8727b905, 0xd5cdc062,
+ 0x8738545e, 0xd59e4eff, 0x87490258, 0xd56ee424, 0x8759c2ef, 0xd53f7fda,
+ 0x876a9621, 0xd5102228,
+ 0x877b7bec, 0xd4e0cb15, 0x878c744d, 0xd4b17aa8, 0x879d7f41, 0xd48230e9,
+ 0x87ae9cc5, 0xd452eddf,
+ 0x87bfccd7, 0xd423b191, 0x87d10f75, 0xd3f47c06, 0x87e2649b, 0xd3c54d47,
+ 0x87f3cc48, 0xd396255a,
+ 0x88054677, 0xd3670446, 0x8816d327, 0xd337ea12, 0x88287256, 0xd308d6c7,
+ 0x883a23ff, 0xd2d9ca6a,
+ 0x884be821, 0xd2aac504, 0x885dbeb8, 0xd27bc69c, 0x886fa7c2, 0xd24ccf39,
+ 0x8881a33d, 0xd21ddee2,
+ 0x8893b125, 0xd1eef59e, 0x88a5d177, 0xd1c01375, 0x88b80432, 0xd191386e,
+ 0x88ca4951, 0xd1626490,
+ 0x88dca0d3, 0xd13397e2, 0x88ef0ab4, 0xd104d26b, 0x890186f2, 0xd0d61434,
+ 0x89141589, 0xd0a75d42,
+ 0x8926b677, 0xd078ad9e, 0x893969b9, 0xd04a054e, 0x894c2f4c, 0xd01b6459,
+ 0x895f072e, 0xcfeccac7,
+ 0x8971f15a, 0xcfbe389f, 0x8984edcf, 0xcf8fade9, 0x8997fc8a, 0xcf612aaa,
+ 0x89ab1d87, 0xcf32aeeb,
+ 0x89be50c3, 0xcf043ab3, 0x89d1963c, 0xced5ce08, 0x89e4edef, 0xcea768f2,
+ 0x89f857d8, 0xce790b79,
+ 0x8a0bd3f5, 0xce4ab5a2, 0x8a1f6243, 0xce1c6777, 0x8a3302be, 0xcdee20fc,
+ 0x8a46b564, 0xcdbfe23a,
+ 0x8a5a7a31, 0xcd91ab39, 0x8a6e5123, 0xcd637bfe, 0x8a823a36, 0xcd355491,
+ 0x8a963567, 0xcd0734f9,
+ 0x8aaa42b4, 0xccd91d3d, 0x8abe6219, 0xccab0d65, 0x8ad29394, 0xcc7d0578,
+ 0x8ae6d720, 0xcc4f057c,
+ 0x8afb2cbb, 0xcc210d79, 0x8b0f9462, 0xcbf31d75, 0x8b240e11, 0xcbc53579,
+ 0x8b3899c6, 0xcb97558a,
+ 0x8b4d377c, 0xcb697db0, 0x8b61e733, 0xcb3badf3, 0x8b76a8e4, 0xcb0de658,
+ 0x8b8b7c8f, 0xcae026e8,
+ 0x8ba0622f, 0xcab26fa9, 0x8bb559c1, 0xca84c0a3, 0x8bca6343, 0xca5719db,
+ 0x8bdf7eb0, 0xca297b5a,
+ 0x8bf4ac05, 0xc9fbe527, 0x8c09eb40, 0xc9ce5748, 0x8c1f3c5d, 0xc9a0d1c5,
+ 0x8c349f58, 0xc97354a4,
+ 0x8c4a142f, 0xc945dfec, 0x8c5f9ade, 0xc91873a5, 0x8c753362, 0xc8eb0fd6,
+ 0x8c8addb7, 0xc8bdb485,
+ 0x8ca099da, 0xc89061ba, 0x8cb667c8, 0xc863177b, 0x8ccc477d, 0xc835d5d0,
+ 0x8ce238f6, 0xc8089cbf,
+ 0x8cf83c30, 0xc7db6c50, 0x8d0e5127, 0xc7ae4489, 0x8d2477d8, 0xc7812572,
+ 0x8d3ab03f, 0xc7540f11,
+ 0x8d50fa59, 0xc727016d, 0x8d675623, 0xc6f9fc8d, 0x8d7dc399, 0xc6cd0079,
+ 0x8d9442b8, 0xc6a00d37,
+ 0x8daad37b, 0xc67322ce, 0x8dc175e0, 0xc6464144, 0x8dd829e4, 0xc61968a2,
+ 0x8deeef82, 0xc5ec98ee,
+ 0x8e05c6b7, 0xc5bfd22e, 0x8e1caf80, 0xc593146a, 0x8e33a9da, 0xc5665fa9,
+ 0x8e4ab5bf, 0xc539b3f1,
+ 0x8e61d32e, 0xc50d1149, 0x8e790222, 0xc4e077b8, 0x8e904298, 0xc4b3e746,
+ 0x8ea7948c, 0xc4875ff9,
+ 0x8ebef7fb, 0xc45ae1d7, 0x8ed66ce1, 0xc42e6ce8, 0x8eedf33b, 0xc4020133,
+ 0x8f058b04, 0xc3d59ebe,
+ 0x8f1d343a, 0xc3a94590, 0x8f34eed8, 0xc37cf5b0, 0x8f4cbadb, 0xc350af26,
+ 0x8f649840, 0xc32471f7,
+ 0x8f7c8701, 0xc2f83e2a, 0x8f94871d, 0xc2cc13c7, 0x8fac988f, 0xc29ff2d4,
+ 0x8fc4bb53, 0xc273db58,
+ 0x8fdcef66, 0xc247cd5a, 0x8ff534c4, 0xc21bc8e1, 0x900d8b69, 0xc1efcdf3,
+ 0x9025f352, 0xc1c3dc97,
+ 0x903e6c7b, 0xc197f4d4, 0x9056f6df, 0xc16c16b0, 0x906f927c, 0xc1404233,
+ 0x90883f4d, 0xc1147764,
+ 0x90a0fd4e, 0xc0e8b648, 0x90b9cc7d, 0xc0bcfee7, 0x90d2acd4, 0xc0915148,
+ 0x90eb9e50, 0xc065ad70,
+ 0x9104a0ee, 0xc03a1368, 0x911db4a9, 0xc00e8336, 0x9136d97d, 0xbfe2fcdf,
+ 0x91500f67, 0xbfb7806c,
+ 0x91695663, 0xbf8c0de3, 0x9182ae6d, 0xbf60a54a, 0x919c1781, 0xbf3546a8,
+ 0x91b5919a, 0xbf09f205,
+ 0x91cf1cb6, 0xbedea765, 0x91e8b8d0, 0xbeb366d1, 0x920265e4, 0xbe88304f,
+ 0x921c23ef, 0xbe5d03e6,
+ 0x9235f2ec, 0xbe31e19b, 0x924fd2d7, 0xbe06c977, 0x9269c3ac, 0xbddbbb7f,
+ 0x9283c568, 0xbdb0b7bb,
+ 0x929dd806, 0xbd85be30, 0x92b7fb82, 0xbd5acee5, 0x92d22fd9, 0xbd2fe9e2,
+ 0x92ec7505, 0xbd050f2c,
+ 0x9306cb04, 0xbcda3ecb, 0x932131d1, 0xbcaf78c4, 0x933ba968, 0xbc84bd1f,
+ 0x935631c5, 0xbc5a0be2,
+ 0x9370cae4, 0xbc2f6513, 0x938b74c1, 0xbc04c8ba, 0x93a62f57, 0xbbda36dd,
+ 0x93c0faa3, 0xbbafaf82,
+ 0x93dbd6a0, 0xbb8532b0, 0x93f6c34a, 0xbb5ac06d, 0x9411c09e, 0xbb3058c0,
+ 0x942cce96, 0xbb05fbb0,
+ 0x9447ed2f, 0xbadba943, 0x94631c65, 0xbab16180, 0x947e5c33, 0xba87246d,
+ 0x9499ac95, 0xba5cf210,
+ 0x94b50d87, 0xba32ca71, 0x94d07f05, 0xba08ad95, 0x94ec010b, 0xb9de9b83,
+ 0x95079394, 0xb9b49442,
+ 0x9523369c, 0xb98a97d8, 0x953eea1e, 0xb960a64c, 0x955aae17, 0xb936bfa4,
+ 0x95768283, 0xb90ce3e6,
+ 0x9592675c, 0xb8e31319, 0x95ae5c9f, 0xb8b94d44, 0x95ca6247, 0xb88f926d,
+ 0x95e67850, 0xb865e299,
+ 0x96029eb6, 0xb83c3dd1, 0x961ed574, 0xb812a41a, 0x963b1c86, 0xb7e9157a,
+ 0x965773e7, 0xb7bf91f8,
+ 0x9673db94, 0xb796199b, 0x96905388, 0xb76cac69, 0x96acdbbe, 0xb7434a67,
+ 0x96c97432, 0xb719f39e,
+ 0x96e61ce0, 0xb6f0a812, 0x9702d5c3, 0xb6c767ca, 0x971f9ed7, 0xb69e32cd,
+ 0x973c7817, 0xb6750921,
+ 0x9759617f, 0xb64beacd, 0x97765b0a, 0xb622d7d6, 0x979364b5, 0xb5f9d043,
+ 0x97b07e7a, 0xb5d0d41a,
+ 0x97cda855, 0xb5a7e362, 0x97eae242, 0xb57efe22, 0x98082c3b, 0xb556245e,
+ 0x9825863d, 0xb52d561e,
+ 0x9842f043, 0xb5049368, 0x98606a49, 0xb4dbdc42, 0x987df449, 0xb4b330b3,
+ 0x989b8e40, 0xb48a90c0,
+ 0x98b93828, 0xb461fc70, 0x98d6f1fe, 0xb43973ca, 0x98f4bbbc, 0xb410f6d3,
+ 0x9912955f, 0xb3e88592,
+ 0x99307ee0, 0xb3c0200c, 0x994e783d, 0xb397c649, 0x996c816f, 0xb36f784f,
+ 0x998a9a74, 0xb3473623,
+ 0x99a8c345, 0xb31effcc, 0x99c6fbde, 0xb2f6d550, 0x99e5443b, 0xb2ceb6b5,
+ 0x9a039c57, 0xb2a6a402,
+ 0x9a22042d, 0xb27e9d3c, 0x9a407bb9, 0xb256a26a, 0x9a5f02f5, 0xb22eb392,
+ 0x9a7d99de, 0xb206d0ba,
+ 0x9a9c406e, 0xb1def9e9, 0x9abaf6a1, 0xb1b72f23, 0x9ad9bc71, 0xb18f7071,
+ 0x9af891db, 0xb167bdd7,
+ 0x9b1776da, 0xb140175b, 0x9b366b68, 0xb1187d05, 0x9b556f81, 0xb0f0eeda,
+ 0x9b748320, 0xb0c96ce0,
+ 0x9b93a641, 0xb0a1f71d, 0x9bb2d8de, 0xb07a8d97, 0x9bd21af3, 0xb0533055,
+ 0x9bf16c7a, 0xb02bdf5c,
+ 0x9c10cd70, 0xb0049ab3, 0x9c303dcf, 0xafdd625f, 0x9c4fbd93, 0xafb63667,
+ 0x9c6f4cb6, 0xaf8f16d1,
+ 0x9c8eeb34, 0xaf6803a2, 0x9cae9907, 0xaf40fce1, 0x9cce562c, 0xaf1a0293,
+ 0x9cee229c, 0xaef314c0,
+ 0x9d0dfe54, 0xaecc336c, 0x9d2de94d, 0xaea55e9e, 0x9d4de385, 0xae7e965b,
+ 0x9d6decf4, 0xae57daab,
+ 0x9d8e0597, 0xae312b92, 0x9dae2d68, 0xae0a8916, 0x9dce6463, 0xade3f33e,
+ 0x9deeaa82, 0xadbd6a10,
+ 0x9e0effc1, 0xad96ed92, 0x9e2f641b, 0xad707dc8, 0x9e4fd78a, 0xad4a1aba,
+ 0x9e705a09, 0xad23c46e,
+ 0x9e90eb94, 0xacfd7ae8, 0x9eb18c26, 0xacd73e30, 0x9ed23bb9, 0xacb10e4b,
+ 0x9ef2fa49, 0xac8aeb3e,
+ 0x9f13c7d0, 0xac64d510, 0x9f34a449, 0xac3ecbc7, 0x9f558fb0, 0xac18cf69,
+ 0x9f7689ff, 0xabf2dffb,
+ 0x9f979331, 0xabccfd83, 0x9fb8ab41, 0xaba72807, 0x9fd9d22a, 0xab815f8d,
+ 0x9ffb07e7, 0xab5ba41a,
+ 0xa01c4c73, 0xab35f5b5, 0xa03d9fc8, 0xab105464, 0xa05f01e1, 0xaaeac02c,
+ 0xa08072ba, 0xaac53912,
+ 0xa0a1f24d, 0xaa9fbf1e, 0xa0c38095, 0xaa7a5253, 0xa0e51d8c, 0xaa54f2ba,
+ 0xa106c92f, 0xaa2fa056,
+ 0xa1288376, 0xaa0a5b2e, 0xa14a4c5e, 0xa9e52347, 0xa16c23e1, 0xa9bff8a8,
+ 0xa18e09fa, 0xa99adb56,
+ 0xa1affea3, 0xa975cb57, 0xa1d201d7, 0xa950c8b0, 0xa1f41392, 0xa92bd367,
+ 0xa21633cd, 0xa906eb82,
+ 0xa2386284, 0xa8e21106, 0xa25a9fb1, 0xa8bd43fa, 0xa27ceb4f, 0xa8988463,
+ 0xa29f4559, 0xa873d246,
+ 0xa2c1adc9, 0xa84f2daa, 0xa2e4249b, 0xa82a9693, 0xa306a9c8, 0xa8060d08,
+ 0xa3293d4b, 0xa7e1910f,
+ 0xa34bdf20, 0xa7bd22ac, 0xa36e8f41, 0xa798c1e5, 0xa3914da8, 0xa7746ec0,
+ 0xa3b41a50, 0xa7502943,
+ 0xa3d6f534, 0xa72bf174, 0xa3f9de4e, 0xa707c757, 0xa41cd599, 0xa6e3aaf2,
+ 0xa43fdb10, 0xa6bf9c4b,
+ 0xa462eeac, 0xa69b9b68, 0xa486106a, 0xa677a84e, 0xa4a94043, 0xa653c303,
+ 0xa4cc7e32, 0xa62feb8b,
+ 0xa4efca31, 0xa60c21ee, 0xa513243b, 0xa5e8662f, 0xa5368c4b, 0xa5c4b855,
+ 0xa55a025b, 0xa5a11866,
+ 0xa57d8666, 0xa57d8666, 0xa5a11866, 0xa55a025b, 0xa5c4b855, 0xa5368c4b,
+ 0xa5e8662f, 0xa513243b,
+ 0xa60c21ee, 0xa4efca31, 0xa62feb8b, 0xa4cc7e32, 0xa653c303, 0xa4a94043,
+ 0xa677a84e, 0xa486106a,
+ 0xa69b9b68, 0xa462eeac, 0xa6bf9c4b, 0xa43fdb10, 0xa6e3aaf2, 0xa41cd599,
+ 0xa707c757, 0xa3f9de4e,
+ 0xa72bf174, 0xa3d6f534, 0xa7502943, 0xa3b41a50, 0xa7746ec0, 0xa3914da8,
+ 0xa798c1e5, 0xa36e8f41,
+ 0xa7bd22ac, 0xa34bdf20, 0xa7e1910f, 0xa3293d4b, 0xa8060d08, 0xa306a9c8,
+ 0xa82a9693, 0xa2e4249b,
+ 0xa84f2daa, 0xa2c1adc9, 0xa873d246, 0xa29f4559, 0xa8988463, 0xa27ceb4f,
+ 0xa8bd43fa, 0xa25a9fb1,
+ 0xa8e21106, 0xa2386284, 0xa906eb82, 0xa21633cd, 0xa92bd367, 0xa1f41392,
+ 0xa950c8b0, 0xa1d201d7,
+ 0xa975cb57, 0xa1affea3, 0xa99adb56, 0xa18e09fa, 0xa9bff8a8, 0xa16c23e1,
+ 0xa9e52347, 0xa14a4c5e,
+ 0xaa0a5b2e, 0xa1288376, 0xaa2fa056, 0xa106c92f, 0xaa54f2ba, 0xa0e51d8c,
+ 0xaa7a5253, 0xa0c38095,
+ 0xaa9fbf1e, 0xa0a1f24d, 0xaac53912, 0xa08072ba, 0xaaeac02c, 0xa05f01e1,
+ 0xab105464, 0xa03d9fc8,
+ 0xab35f5b5, 0xa01c4c73, 0xab5ba41a, 0x9ffb07e7, 0xab815f8d, 0x9fd9d22a,
+ 0xaba72807, 0x9fb8ab41,
+ 0xabccfd83, 0x9f979331, 0xabf2dffb, 0x9f7689ff, 0xac18cf69, 0x9f558fb0,
+ 0xac3ecbc7, 0x9f34a449,
+ 0xac64d510, 0x9f13c7d0, 0xac8aeb3e, 0x9ef2fa49, 0xacb10e4b, 0x9ed23bb9,
+ 0xacd73e30, 0x9eb18c26,
+ 0xacfd7ae8, 0x9e90eb94, 0xad23c46e, 0x9e705a09, 0xad4a1aba, 0x9e4fd78a,
+ 0xad707dc8, 0x9e2f641b,
+ 0xad96ed92, 0x9e0effc1, 0xadbd6a10, 0x9deeaa82, 0xade3f33e, 0x9dce6463,
+ 0xae0a8916, 0x9dae2d68,
+ 0xae312b92, 0x9d8e0597, 0xae57daab, 0x9d6decf4, 0xae7e965b, 0x9d4de385,
+ 0xaea55e9e, 0x9d2de94d,
+ 0xaecc336c, 0x9d0dfe54, 0xaef314c0, 0x9cee229c, 0xaf1a0293, 0x9cce562c,
+ 0xaf40fce1, 0x9cae9907,
+ 0xaf6803a2, 0x9c8eeb34, 0xaf8f16d1, 0x9c6f4cb6, 0xafb63667, 0x9c4fbd93,
+ 0xafdd625f, 0x9c303dcf,
+ 0xb0049ab3, 0x9c10cd70, 0xb02bdf5c, 0x9bf16c7a, 0xb0533055, 0x9bd21af3,
+ 0xb07a8d97, 0x9bb2d8de,
+ 0xb0a1f71d, 0x9b93a641, 0xb0c96ce0, 0x9b748320, 0xb0f0eeda, 0x9b556f81,
+ 0xb1187d05, 0x9b366b68,
+ 0xb140175b, 0x9b1776da, 0xb167bdd7, 0x9af891db, 0xb18f7071, 0x9ad9bc71,
+ 0xb1b72f23, 0x9abaf6a1,
+ 0xb1def9e9, 0x9a9c406e, 0xb206d0ba, 0x9a7d99de, 0xb22eb392, 0x9a5f02f5,
+ 0xb256a26a, 0x9a407bb9,
+ 0xb27e9d3c, 0x9a22042d, 0xb2a6a402, 0x9a039c57, 0xb2ceb6b5, 0x99e5443b,
+ 0xb2f6d550, 0x99c6fbde,
+ 0xb31effcc, 0x99a8c345, 0xb3473623, 0x998a9a74, 0xb36f784f, 0x996c816f,
+ 0xb397c649, 0x994e783d,
+ 0xb3c0200c, 0x99307ee0, 0xb3e88592, 0x9912955f, 0xb410f6d3, 0x98f4bbbc,
+ 0xb43973ca, 0x98d6f1fe,
+ 0xb461fc70, 0x98b93828, 0xb48a90c0, 0x989b8e40, 0xb4b330b3, 0x987df449,
+ 0xb4dbdc42, 0x98606a49,
+ 0xb5049368, 0x9842f043, 0xb52d561e, 0x9825863d, 0xb556245e, 0x98082c3b,
+ 0xb57efe22, 0x97eae242,
+ 0xb5a7e362, 0x97cda855, 0xb5d0d41a, 0x97b07e7a, 0xb5f9d043, 0x979364b5,
+ 0xb622d7d6, 0x97765b0a,
+ 0xb64beacd, 0x9759617f, 0xb6750921, 0x973c7817, 0xb69e32cd, 0x971f9ed7,
+ 0xb6c767ca, 0x9702d5c3,
+ 0xb6f0a812, 0x96e61ce0, 0xb719f39e, 0x96c97432, 0xb7434a67, 0x96acdbbe,
+ 0xb76cac69, 0x96905388,
+ 0xb796199b, 0x9673db94, 0xb7bf91f8, 0x965773e7, 0xb7e9157a, 0x963b1c86,
+ 0xb812a41a, 0x961ed574,
+ 0xb83c3dd1, 0x96029eb6, 0xb865e299, 0x95e67850, 0xb88f926d, 0x95ca6247,
+ 0xb8b94d44, 0x95ae5c9f,
+ 0xb8e31319, 0x9592675c, 0xb90ce3e6, 0x95768283, 0xb936bfa4, 0x955aae17,
+ 0xb960a64c, 0x953eea1e,
+ 0xb98a97d8, 0x9523369c, 0xb9b49442, 0x95079394, 0xb9de9b83, 0x94ec010b,
+ 0xba08ad95, 0x94d07f05,
+ 0xba32ca71, 0x94b50d87, 0xba5cf210, 0x9499ac95, 0xba87246d, 0x947e5c33,
+ 0xbab16180, 0x94631c65,
+ 0xbadba943, 0x9447ed2f, 0xbb05fbb0, 0x942cce96, 0xbb3058c0, 0x9411c09e,
+ 0xbb5ac06d, 0x93f6c34a,
+ 0xbb8532b0, 0x93dbd6a0, 0xbbafaf82, 0x93c0faa3, 0xbbda36dd, 0x93a62f57,
+ 0xbc04c8ba, 0x938b74c1,
+ 0xbc2f6513, 0x9370cae4, 0xbc5a0be2, 0x935631c5, 0xbc84bd1f, 0x933ba968,
+ 0xbcaf78c4, 0x932131d1,
+ 0xbcda3ecb, 0x9306cb04, 0xbd050f2c, 0x92ec7505, 0xbd2fe9e2, 0x92d22fd9,
+ 0xbd5acee5, 0x92b7fb82,
+ 0xbd85be30, 0x929dd806, 0xbdb0b7bb, 0x9283c568, 0xbddbbb7f, 0x9269c3ac,
+ 0xbe06c977, 0x924fd2d7,
+ 0xbe31e19b, 0x9235f2ec, 0xbe5d03e6, 0x921c23ef, 0xbe88304f, 0x920265e4,
+ 0xbeb366d1, 0x91e8b8d0,
+ 0xbedea765, 0x91cf1cb6, 0xbf09f205, 0x91b5919a, 0xbf3546a8, 0x919c1781,
+ 0xbf60a54a, 0x9182ae6d,
+ 0xbf8c0de3, 0x91695663, 0xbfb7806c, 0x91500f67, 0xbfe2fcdf, 0x9136d97d,
+ 0xc00e8336, 0x911db4a9,
+ 0xc03a1368, 0x9104a0ee, 0xc065ad70, 0x90eb9e50, 0xc0915148, 0x90d2acd4,
+ 0xc0bcfee7, 0x90b9cc7d,
+ 0xc0e8b648, 0x90a0fd4e, 0xc1147764, 0x90883f4d, 0xc1404233, 0x906f927c,
+ 0xc16c16b0, 0x9056f6df,
+ 0xc197f4d4, 0x903e6c7b, 0xc1c3dc97, 0x9025f352, 0xc1efcdf3, 0x900d8b69,
+ 0xc21bc8e1, 0x8ff534c4,
+ 0xc247cd5a, 0x8fdcef66, 0xc273db58, 0x8fc4bb53, 0xc29ff2d4, 0x8fac988f,
+ 0xc2cc13c7, 0x8f94871d,
+ 0xc2f83e2a, 0x8f7c8701, 0xc32471f7, 0x8f649840, 0xc350af26, 0x8f4cbadb,
+ 0xc37cf5b0, 0x8f34eed8,
+ 0xc3a94590, 0x8f1d343a, 0xc3d59ebe, 0x8f058b04, 0xc4020133, 0x8eedf33b,
+ 0xc42e6ce8, 0x8ed66ce1,
+ 0xc45ae1d7, 0x8ebef7fb, 0xc4875ff9, 0x8ea7948c, 0xc4b3e746, 0x8e904298,
+ 0xc4e077b8, 0x8e790222,
+ 0xc50d1149, 0x8e61d32e, 0xc539b3f1, 0x8e4ab5bf, 0xc5665fa9, 0x8e33a9da,
+ 0xc593146a, 0x8e1caf80,
+ 0xc5bfd22e, 0x8e05c6b7, 0xc5ec98ee, 0x8deeef82, 0xc61968a2, 0x8dd829e4,
+ 0xc6464144, 0x8dc175e0,
+ 0xc67322ce, 0x8daad37b, 0xc6a00d37, 0x8d9442b8, 0xc6cd0079, 0x8d7dc399,
+ 0xc6f9fc8d, 0x8d675623,
+ 0xc727016d, 0x8d50fa59, 0xc7540f11, 0x8d3ab03f, 0xc7812572, 0x8d2477d8,
+ 0xc7ae4489, 0x8d0e5127,
+ 0xc7db6c50, 0x8cf83c30, 0xc8089cbf, 0x8ce238f6, 0xc835d5d0, 0x8ccc477d,
+ 0xc863177b, 0x8cb667c8,
+ 0xc89061ba, 0x8ca099da, 0xc8bdb485, 0x8c8addb7, 0xc8eb0fd6, 0x8c753362,
+ 0xc91873a5, 0x8c5f9ade,
+ 0xc945dfec, 0x8c4a142f, 0xc97354a4, 0x8c349f58, 0xc9a0d1c5, 0x8c1f3c5d,
+ 0xc9ce5748, 0x8c09eb40,
+ 0xc9fbe527, 0x8bf4ac05, 0xca297b5a, 0x8bdf7eb0, 0xca5719db, 0x8bca6343,
+ 0xca84c0a3, 0x8bb559c1,
+ 0xcab26fa9, 0x8ba0622f, 0xcae026e8, 0x8b8b7c8f, 0xcb0de658, 0x8b76a8e4,
+ 0xcb3badf3, 0x8b61e733,
+ 0xcb697db0, 0x8b4d377c, 0xcb97558a, 0x8b3899c6, 0xcbc53579, 0x8b240e11,
+ 0xcbf31d75, 0x8b0f9462,
+ 0xcc210d79, 0x8afb2cbb, 0xcc4f057c, 0x8ae6d720, 0xcc7d0578, 0x8ad29394,
+ 0xccab0d65, 0x8abe6219,
+ 0xccd91d3d, 0x8aaa42b4, 0xcd0734f9, 0x8a963567, 0xcd355491, 0x8a823a36,
+ 0xcd637bfe, 0x8a6e5123,
+ 0xcd91ab39, 0x8a5a7a31, 0xcdbfe23a, 0x8a46b564, 0xcdee20fc, 0x8a3302be,
+ 0xce1c6777, 0x8a1f6243,
+ 0xce4ab5a2, 0x8a0bd3f5, 0xce790b79, 0x89f857d8, 0xcea768f2, 0x89e4edef,
+ 0xced5ce08, 0x89d1963c,
+ 0xcf043ab3, 0x89be50c3, 0xcf32aeeb, 0x89ab1d87, 0xcf612aaa, 0x8997fc8a,
+ 0xcf8fade9, 0x8984edcf,
+ 0xcfbe389f, 0x8971f15a, 0xcfeccac7, 0x895f072e, 0xd01b6459, 0x894c2f4c,
+ 0xd04a054e, 0x893969b9,
+ 0xd078ad9e, 0x8926b677, 0xd0a75d42, 0x89141589, 0xd0d61434, 0x890186f2,
+ 0xd104d26b, 0x88ef0ab4,
+ 0xd13397e2, 0x88dca0d3, 0xd1626490, 0x88ca4951, 0xd191386e, 0x88b80432,
+ 0xd1c01375, 0x88a5d177,
+ 0xd1eef59e, 0x8893b125, 0xd21ddee2, 0x8881a33d, 0xd24ccf39, 0x886fa7c2,
+ 0xd27bc69c, 0x885dbeb8,
+ 0xd2aac504, 0x884be821, 0xd2d9ca6a, 0x883a23ff, 0xd308d6c7, 0x88287256,
+ 0xd337ea12, 0x8816d327,
+ 0xd3670446, 0x88054677, 0xd396255a, 0x87f3cc48, 0xd3c54d47, 0x87e2649b,
+ 0xd3f47c06, 0x87d10f75,
+ 0xd423b191, 0x87bfccd7, 0xd452eddf, 0x87ae9cc5, 0xd48230e9, 0x879d7f41,
+ 0xd4b17aa8, 0x878c744d,
+ 0xd4e0cb15, 0x877b7bec, 0xd5102228, 0x876a9621, 0xd53f7fda, 0x8759c2ef,
+ 0xd56ee424, 0x87490258,
+ 0xd59e4eff, 0x8738545e, 0xd5cdc062, 0x8727b905, 0xd5fd3848, 0x8717304e,
+ 0xd62cb6a8, 0x8706ba3d,
+ 0xd65c3b7b, 0x86f656d3, 0xd68bc6ba, 0x86e60614, 0xd6bb585e, 0x86d5c802,
+ 0xd6eaf05f, 0x86c59c9f,
+ 0xd71a8eb5, 0x86b583ee, 0xd74a335b, 0x86a57df2, 0xd779de47, 0x86958aac,
+ 0xd7a98f73, 0x8685aa20,
+ 0xd7d946d8, 0x8675dc4f, 0xd809046e, 0x8666213c, 0xd838c82d, 0x865678eb,
+ 0xd868920f, 0x8646e35c,
+ 0xd898620c, 0x86376092, 0xd8c8381d, 0x8627f091, 0xd8f81439, 0x86189359,
+ 0xd927f65b, 0x860948ef,
+ 0xd957de7a, 0x85fa1153, 0xd987cc90, 0x85eaec88, 0xd9b7c094, 0x85dbda91,
+ 0xd9e7ba7f, 0x85ccdb70,
+ 0xda17ba4a, 0x85bdef28, 0xda47bfee, 0x85af15b9, 0xda77cb63, 0x85a04f28,
+ 0xdaa7dca1, 0x85919b76,
+ 0xdad7f3a2, 0x8582faa5, 0xdb08105e, 0x85746cb8, 0xdb3832cd, 0x8565f1b0,
+ 0xdb685ae9, 0x85578991,
+ 0xdb9888a8, 0x8549345c, 0xdbc8bc06, 0x853af214, 0xdbf8f4f8, 0x852cc2bb,
+ 0xdc293379, 0x851ea652,
+ 0xdc597781, 0x85109cdd, 0xdc89c109, 0x8502a65c, 0xdcba1008, 0x84f4c2d4,
+ 0xdcea6478, 0x84e6f244,
+ 0xdd1abe51, 0x84d934b1, 0xdd4b1d8c, 0x84cb8a1b, 0xdd7b8220, 0x84bdf286,
+ 0xddabec08, 0x84b06df2,
+ 0xdddc5b3b, 0x84a2fc62, 0xde0ccfb1, 0x84959dd9, 0xde3d4964, 0x84885258,
+ 0xde6dc84b, 0x847b19e1,
+ 0xde9e4c60, 0x846df477, 0xdeced59b, 0x8460e21a, 0xdeff63f4, 0x8453e2cf,
+ 0xdf2ff764, 0x8446f695,
+ 0xdf608fe4, 0x843a1d70, 0xdf912d6b, 0x842d5762, 0xdfc1cff3, 0x8420a46c,
+ 0xdff27773, 0x84140490,
+ 0xe02323e5, 0x840777d0, 0xe053d541, 0x83fafe2e, 0xe0848b7f, 0x83ee97ad,
+ 0xe0b54698, 0x83e2444d,
+ 0xe0e60685, 0x83d60412, 0xe116cb3d, 0x83c9d6fc, 0xe14794ba, 0x83bdbd0e,
+ 0xe17862f3, 0x83b1b649,
+ 0xe1a935e2, 0x83a5c2b0, 0xe1da0d7e, 0x8399e244, 0xe20ae9c1, 0x838e1507,
+ 0xe23bcaa2, 0x83825afb,
+ 0xe26cb01b, 0x8376b422, 0xe29d9a23, 0x836b207d, 0xe2ce88b3, 0x835fa00f,
+ 0xe2ff7bc3, 0x835432d8,
+ 0xe330734d, 0x8348d8dc, 0xe3616f48, 0x833d921b, 0xe3926fad, 0x83325e97,
+ 0xe3c37474, 0x83273e52,
+ 0xe3f47d96, 0x831c314e, 0xe4258b0a, 0x8311378d, 0xe4569ccb, 0x83065110,
+ 0xe487b2d0, 0x82fb7dd8,
+ 0xe4b8cd11, 0x82f0bde8, 0xe4e9eb87, 0x82e61141, 0xe51b0e2a, 0x82db77e5,
+ 0xe54c34f3, 0x82d0f1d5,
+ 0xe57d5fda, 0x82c67f14, 0xe5ae8ed8, 0x82bc1fa2, 0xe5dfc1e5, 0x82b1d381,
+ 0xe610f8f9, 0x82a79ab3,
+ 0xe642340d, 0x829d753a, 0xe6737319, 0x82936317, 0xe6a4b616, 0x8289644b,
+ 0xe6d5fcfc, 0x827f78d8,
+ 0xe70747c4, 0x8275a0c0, 0xe7389665, 0x826bdc04, 0xe769e8d8, 0x82622aa6,
+ 0xe79b3f16, 0x82588ca7,
+ 0xe7cc9917, 0x824f0208, 0xe7fdf6d4, 0x82458acc, 0xe82f5844, 0x823c26f3,
+ 0xe860bd61, 0x8232d67f,
+ 0xe8922622, 0x82299971, 0xe8c39280, 0x82206fcc, 0xe8f50273, 0x82175990,
+ 0xe92675f4, 0x820e56be,
+ 0xe957ecfb, 0x82056758, 0xe9896781, 0x81fc8b60, 0xe9bae57d, 0x81f3c2d7,
+ 0xe9ec66e8, 0x81eb0dbe,
+ 0xea1debbb, 0x81e26c16, 0xea4f73ee, 0x81d9dde1, 0xea80ff7a, 0x81d16321,
+ 0xeab28e56, 0x81c8fbd6,
+ 0xeae4207a, 0x81c0a801, 0xeb15b5e1, 0x81b867a5, 0xeb474e81, 0x81b03ac2,
+ 0xeb78ea52, 0x81a82159,
+ 0xebaa894f, 0x81a01b6d, 0xebdc2b6e, 0x819828fd, 0xec0dd0a8, 0x81904a0c,
+ 0xec3f78f6, 0x81887e9a,
+ 0xec71244f, 0x8180c6a9, 0xeca2d2ad, 0x8179223a, 0xecd48407, 0x8171914e,
+ 0xed063856, 0x816a13e6,
+ 0xed37ef91, 0x8162aa04, 0xed69a9b3, 0x815b53a8, 0xed9b66b2, 0x815410d4,
+ 0xedcd2687, 0x814ce188,
+ 0xedfee92b, 0x8145c5c7, 0xee30ae96, 0x813ebd90, 0xee6276bf, 0x8137c8e6,
+ 0xee9441a0, 0x8130e7c9,
+ 0xeec60f31, 0x812a1a3a, 0xeef7df6a, 0x8123603a, 0xef29b243, 0x811cb9ca,
+ 0xef5b87b5, 0x811626ec,
+ 0xef8d5fb8, 0x810fa7a0, 0xefbf3a45, 0x81093be8, 0xeff11753, 0x8102e3c4,
+ 0xf022f6da, 0x80fc9f35,
+ 0xf054d8d5, 0x80f66e3c, 0xf086bd39, 0x80f050db, 0xf0b8a401, 0x80ea4712,
+ 0xf0ea8d24, 0x80e450e2,
+ 0xf11c789a, 0x80de6e4c, 0xf14e665c, 0x80d89f51, 0xf1805662, 0x80d2e3f2,
+ 0xf1b248a5, 0x80cd3c2f,
+ 0xf1e43d1c, 0x80c7a80a, 0xf21633c0, 0x80c22784, 0xf2482c8a, 0x80bcba9d,
+ 0xf27a2771, 0x80b76156,
+ 0xf2ac246e, 0x80b21baf, 0xf2de2379, 0x80ace9ab, 0xf310248a, 0x80a7cb49,
+ 0xf342279b, 0x80a2c08b,
+ 0xf3742ca2, 0x809dc971, 0xf3a63398, 0x8098e5fb, 0xf3d83c77, 0x8094162c,
+ 0xf40a4735, 0x808f5a02,
+ 0xf43c53cb, 0x808ab180, 0xf46e6231, 0x80861ca6, 0xf4a07261, 0x80819b74,
+ 0xf4d28451, 0x807d2dec,
+ 0xf50497fb, 0x8078d40d, 0xf536ad56, 0x80748dd9, 0xf568c45b, 0x80705b50,
+ 0xf59add02, 0x806c3c74,
+ 0xf5ccf743, 0x80683143, 0xf5ff1318, 0x806439c0, 0xf6313077, 0x806055eb,
+ 0xf6634f59, 0x805c85c4,
+ 0xf6956fb7, 0x8058c94c, 0xf6c79188, 0x80552084, 0xf6f9b4c6, 0x80518b6b,
+ 0xf72bd967, 0x804e0a04,
+ 0xf75dff66, 0x804a9c4d, 0xf79026b9, 0x80474248, 0xf7c24f59, 0x8043fbf6,
+ 0xf7f4793e, 0x8040c956,
+ 0xf826a462, 0x803daa6a, 0xf858d0bb, 0x803a9f31, 0xf88afe42, 0x8037a7ac,
+ 0xf8bd2cef, 0x8034c3dd,
+ 0xf8ef5cbb, 0x8031f3c2, 0xf9218d9e, 0x802f375d, 0xf953bf91, 0x802c8ead,
+ 0xf985f28a, 0x8029f9b4,
+ 0xf9b82684, 0x80277872, 0xf9ea5b75, 0x80250ae7, 0xfa1c9157, 0x8022b114,
+ 0xfa4ec821, 0x80206af8,
+ 0xfa80ffcb, 0x801e3895, 0xfab3384f, 0x801c19ea, 0xfae571a4, 0x801a0ef8,
+ 0xfb17abc2, 0x801817bf,
+ 0xfb49e6a3, 0x80163440, 0xfb7c223d, 0x8014647b, 0xfbae5e89, 0x8012a86f,
+ 0xfbe09b80, 0x8011001f,
+ 0xfc12d91a, 0x800f6b88, 0xfc45174e, 0x800deaad, 0xfc775616, 0x800c7d8c,
+ 0xfca9956a, 0x800b2427,
+ 0xfcdbd541, 0x8009de7e, 0xfd0e1594, 0x8008ac90, 0xfd40565c, 0x80078e5e,
+ 0xfd729790, 0x800683e8,
+ 0xfda4d929, 0x80058d2f, 0xfdd71b1e, 0x8004aa32, 0xfe095d69, 0x8003daf1,
+ 0xfe3ba002, 0x80031f6d,
+ 0xfe6de2e0, 0x800277a6, 0xfea025fd, 0x8001e39b, 0xfed2694f, 0x8001634e,
+ 0xff04acd0, 0x8000f6bd,
+ 0xff36f078, 0x80009dea, 0xff69343f, 0x800058d4, 0xff9b781d, 0x8000277a,
+ 0xffcdbc0b, 0x800009df,
+
+};
+
+
+/*
+* @brief Q15 Twiddle factors Table
+*/
+
+/**
+* \par
+* Example code for Q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q15(Fixed point 1.15):
+* round(twiddleCoefQ15(i) * pow(2, 15))
+*
+*/
+
+const q15_t ALIGN4 twiddleCoefQ15[6144] = {
+
+ 0x7fff, 0x0, 0x7fff, 0x32, 0x7fff, 0x65, 0x7fff, 0x97,
+ 0x7fff, 0xc9, 0x7fff, 0xfb, 0x7fff, 0x12e, 0x7ffe, 0x160,
+ 0x7ffe, 0x192, 0x7ffd, 0x1c4, 0x7ffc, 0x1f7, 0x7ffb, 0x229,
+ 0x7ffa, 0x25b, 0x7ff9, 0x28d, 0x7ff8, 0x2c0, 0x7ff7, 0x2f2,
+ 0x7ff6, 0x324, 0x7ff5, 0x356, 0x7ff4, 0x389, 0x7ff2, 0x3bb,
+ 0x7ff1, 0x3ed, 0x7fef, 0x41f, 0x7fed, 0x452, 0x7fec, 0x484,
+ 0x7fea, 0x4b6, 0x7fe8, 0x4e8, 0x7fe6, 0x51b, 0x7fe4, 0x54d,
+ 0x7fe2, 0x57f, 0x7fe0, 0x5b1, 0x7fdd, 0x5e3, 0x7fdb, 0x616,
+ 0x7fd9, 0x648, 0x7fd6, 0x67a, 0x7fd3, 0x6ac, 0x7fd1, 0x6de,
+ 0x7fce, 0x711, 0x7fcb, 0x743, 0x7fc8, 0x775, 0x7fc5, 0x7a7,
+ 0x7fc2, 0x7d9, 0x7fbf, 0x80c, 0x7fbc, 0x83e, 0x7fb9, 0x870,
+ 0x7fb5, 0x8a2, 0x7fb2, 0x8d4, 0x7fae, 0x906, 0x7fab, 0x938,
+ 0x7fa7, 0x96b, 0x7fa3, 0x99d, 0x7fa0, 0x9cf, 0x7f9c, 0xa01,
+ 0x7f98, 0xa33, 0x7f94, 0xa65, 0x7f90, 0xa97, 0x7f8b, 0xac9,
+ 0x7f87, 0xafb, 0x7f83, 0xb2d, 0x7f7e, 0xb60, 0x7f7a, 0xb92,
+ 0x7f75, 0xbc4, 0x7f71, 0xbf6, 0x7f6c, 0xc28, 0x7f67, 0xc5a,
+ 0x7f62, 0xc8c, 0x7f5d, 0xcbe, 0x7f58, 0xcf0, 0x7f53, 0xd22,
+ 0x7f4e, 0xd54, 0x7f49, 0xd86, 0x7f43, 0xdb8, 0x7f3e, 0xdea,
+ 0x7f38, 0xe1c, 0x7f33, 0xe4e, 0x7f2d, 0xe80, 0x7f27, 0xeb2,
+ 0x7f22, 0xee4, 0x7f1c, 0xf15, 0x7f16, 0xf47, 0x7f10, 0xf79,
+ 0x7f0a, 0xfab, 0x7f03, 0xfdd, 0x7efd, 0x100f, 0x7ef7, 0x1041,
+ 0x7ef0, 0x1073, 0x7eea, 0x10a4, 0x7ee3, 0x10d6, 0x7edd, 0x1108,
+ 0x7ed6, 0x113a, 0x7ecf, 0x116c, 0x7ec8, 0x119e, 0x7ec1, 0x11cf,
+ 0x7eba, 0x1201, 0x7eb3, 0x1233, 0x7eac, 0x1265, 0x7ea5, 0x1296,
+ 0x7e9d, 0x12c8, 0x7e96, 0x12fa, 0x7e8e, 0x132b, 0x7e87, 0x135d,
+ 0x7e7f, 0x138f, 0x7e78, 0x13c1, 0x7e70, 0x13f2, 0x7e68, 0x1424,
+ 0x7e60, 0x1455, 0x7e58, 0x1487, 0x7e50, 0x14b9, 0x7e48, 0x14ea,
+ 0x7e3f, 0x151c, 0x7e37, 0x154d, 0x7e2f, 0x157f, 0x7e26, 0x15b1,
+ 0x7e1e, 0x15e2, 0x7e15, 0x1614, 0x7e0c, 0x1645, 0x7e03, 0x1677,
+ 0x7dfb, 0x16a8, 0x7df2, 0x16da, 0x7de9, 0x170b, 0x7de0, 0x173c,
+ 0x7dd6, 0x176e, 0x7dcd, 0x179f, 0x7dc4, 0x17d1, 0x7dba, 0x1802,
+ 0x7db1, 0x1833, 0x7da7, 0x1865, 0x7d9e, 0x1896, 0x7d94, 0x18c7,
+ 0x7d8a, 0x18f9, 0x7d81, 0x192a, 0x7d77, 0x195b, 0x7d6d, 0x198d,
+ 0x7d63, 0x19be, 0x7d58, 0x19ef, 0x7d4e, 0x1a20, 0x7d44, 0x1a51,
+ 0x7d3a, 0x1a83, 0x7d2f, 0x1ab4, 0x7d25, 0x1ae5, 0x7d1a, 0x1b16,
+ 0x7d0f, 0x1b47, 0x7d05, 0x1b78, 0x7cfa, 0x1ba9, 0x7cef, 0x1bda,
+ 0x7ce4, 0x1c0c, 0x7cd9, 0x1c3d, 0x7cce, 0x1c6e, 0x7cc2, 0x1c9f,
+ 0x7cb7, 0x1cd0, 0x7cac, 0x1d01, 0x7ca0, 0x1d31, 0x7c95, 0x1d62,
+ 0x7c89, 0x1d93, 0x7c7e, 0x1dc4, 0x7c72, 0x1df5, 0x7c66, 0x1e26,
+ 0x7c5a, 0x1e57, 0x7c4e, 0x1e88, 0x7c42, 0x1eb8, 0x7c36, 0x1ee9,
+ 0x7c2a, 0x1f1a, 0x7c1e, 0x1f4b, 0x7c11, 0x1f7b, 0x7c05, 0x1fac,
+ 0x7bf9, 0x1fdd, 0x7bec, 0x200e, 0x7bdf, 0x203e, 0x7bd3, 0x206f,
+ 0x7bc6, 0x209f, 0x7bb9, 0x20d0, 0x7bac, 0x2101, 0x7b9f, 0x2131,
+ 0x7b92, 0x2162, 0x7b85, 0x2192, 0x7b78, 0x21c3, 0x7b6a, 0x21f3,
+ 0x7b5d, 0x2224, 0x7b50, 0x2254, 0x7b42, 0x2284, 0x7b34, 0x22b5,
+ 0x7b27, 0x22e5, 0x7b19, 0x2316, 0x7b0b, 0x2346, 0x7afd, 0x2376,
+ 0x7aef, 0x23a7, 0x7ae1, 0x23d7, 0x7ad3, 0x2407, 0x7ac5, 0x2437,
+ 0x7ab7, 0x2467, 0x7aa8, 0x2498, 0x7a9a, 0x24c8, 0x7a8c, 0x24f8,
+ 0x7a7d, 0x2528, 0x7a6e, 0x2558, 0x7a60, 0x2588, 0x7a51, 0x25b8,
+ 0x7a42, 0x25e8, 0x7a33, 0x2618, 0x7a24, 0x2648, 0x7a15, 0x2678,
+ 0x7a06, 0x26a8, 0x79f7, 0x26d8, 0x79e7, 0x2708, 0x79d8, 0x2738,
+ 0x79c9, 0x2768, 0x79b9, 0x2797, 0x79aa, 0x27c7, 0x799a, 0x27f7,
+ 0x798a, 0x2827, 0x797a, 0x2856, 0x796a, 0x2886, 0x795b, 0x28b6,
+ 0x794a, 0x28e5, 0x793a, 0x2915, 0x792a, 0x2945, 0x791a, 0x2974,
+ 0x790a, 0x29a4, 0x78f9, 0x29d3, 0x78e9, 0x2a03, 0x78d8, 0x2a32,
+ 0x78c8, 0x2a62, 0x78b7, 0x2a91, 0x78a6, 0x2ac1, 0x7895, 0x2af0,
+ 0x7885, 0x2b1f, 0x7874, 0x2b4f, 0x7863, 0x2b7e, 0x7851, 0x2bad,
+ 0x7840, 0x2bdc, 0x782f, 0x2c0c, 0x781e, 0x2c3b, 0x780c, 0x2c6a,
+ 0x77fb, 0x2c99, 0x77e9, 0x2cc8, 0x77d8, 0x2cf7, 0x77c6, 0x2d26,
+ 0x77b4, 0x2d55, 0x77a2, 0x2d84, 0x7790, 0x2db3, 0x777e, 0x2de2,
+ 0x776c, 0x2e11, 0x775a, 0x2e40, 0x7748, 0x2e6f, 0x7736, 0x2e9e,
+ 0x7723, 0x2ecc, 0x7711, 0x2efb, 0x76fe, 0x2f2a, 0x76ec, 0x2f59,
+ 0x76d9, 0x2f87, 0x76c7, 0x2fb6, 0x76b4, 0x2fe5, 0x76a1, 0x3013,
+ 0x768e, 0x3042, 0x767b, 0x3070, 0x7668, 0x309f, 0x7655, 0x30cd,
+ 0x7642, 0x30fc, 0x762e, 0x312a, 0x761b, 0x3159, 0x7608, 0x3187,
+ 0x75f4, 0x31b5, 0x75e1, 0x31e4, 0x75cd, 0x3212, 0x75b9, 0x3240,
+ 0x75a6, 0x326e, 0x7592, 0x329d, 0x757e, 0x32cb, 0x756a, 0x32f9,
+ 0x7556, 0x3327, 0x7542, 0x3355, 0x752d, 0x3383, 0x7519, 0x33b1,
+ 0x7505, 0x33df, 0x74f0, 0x340d, 0x74dc, 0x343b, 0x74c7, 0x3469,
+ 0x74b3, 0x3497, 0x749e, 0x34c4, 0x7489, 0x34f2, 0x7475, 0x3520,
+ 0x7460, 0x354e, 0x744b, 0x357b, 0x7436, 0x35a9, 0x7421, 0x35d7,
+ 0x740b, 0x3604, 0x73f6, 0x3632, 0x73e1, 0x365f, 0x73cb, 0x368d,
+ 0x73b6, 0x36ba, 0x73a0, 0x36e8, 0x738b, 0x3715, 0x7375, 0x3742,
+ 0x735f, 0x3770, 0x734a, 0x379d, 0x7334, 0x37ca, 0x731e, 0x37f7,
+ 0x7308, 0x3825, 0x72f2, 0x3852, 0x72dc, 0x387f, 0x72c5, 0x38ac,
+ 0x72af, 0x38d9, 0x7299, 0x3906, 0x7282, 0x3933, 0x726c, 0x3960,
+ 0x7255, 0x398d, 0x723f, 0x39ba, 0x7228, 0x39e7, 0x7211, 0x3a13,
+ 0x71fa, 0x3a40, 0x71e3, 0x3a6d, 0x71cc, 0x3a9a, 0x71b5, 0x3ac6,
+ 0x719e, 0x3af3, 0x7187, 0x3b20, 0x7170, 0x3b4c, 0x7158, 0x3b79,
+ 0x7141, 0x3ba5, 0x712a, 0x3bd2, 0x7112, 0x3bfe, 0x70fa, 0x3c2a,
+ 0x70e3, 0x3c57, 0x70cb, 0x3c83, 0x70b3, 0x3caf, 0x709b, 0x3cdc,
+ 0x7083, 0x3d08, 0x706b, 0x3d34, 0x7053, 0x3d60, 0x703b, 0x3d8c,
+ 0x7023, 0x3db8, 0x700b, 0x3de4, 0x6ff2, 0x3e10, 0x6fda, 0x3e3c,
+ 0x6fc2, 0x3e68, 0x6fa9, 0x3e94, 0x6f90, 0x3ec0, 0x6f78, 0x3eec,
+ 0x6f5f, 0x3f17, 0x6f46, 0x3f43, 0x6f2d, 0x3f6f, 0x6f14, 0x3f9a,
+ 0x6efb, 0x3fc6, 0x6ee2, 0x3ff1, 0x6ec9, 0x401d, 0x6eb0, 0x4048,
+ 0x6e97, 0x4074, 0x6e7d, 0x409f, 0x6e64, 0x40cb, 0x6e4a, 0x40f6,
+ 0x6e31, 0x4121, 0x6e17, 0x414d, 0x6dfe, 0x4178, 0x6de4, 0x41a3,
+ 0x6dca, 0x41ce, 0x6db0, 0x41f9, 0x6d96, 0x4224, 0x6d7c, 0x424f,
+ 0x6d62, 0x427a, 0x6d48, 0x42a5, 0x6d2e, 0x42d0, 0x6d14, 0x42fb,
+ 0x6cf9, 0x4326, 0x6cdf, 0x4351, 0x6cc4, 0x437b, 0x6caa, 0x43a6,
+ 0x6c8f, 0x43d1, 0x6c75, 0x43fb, 0x6c5a, 0x4426, 0x6c3f, 0x4450,
+ 0x6c24, 0x447b, 0x6c09, 0x44a5, 0x6bee, 0x44d0, 0x6bd3, 0x44fa,
+ 0x6bb8, 0x4524, 0x6b9d, 0x454f, 0x6b82, 0x4579, 0x6b66, 0x45a3,
+ 0x6b4b, 0x45cd, 0x6b30, 0x45f7, 0x6b14, 0x4621, 0x6af8, 0x464b,
+ 0x6add, 0x4675, 0x6ac1, 0x469f, 0x6aa5, 0x46c9, 0x6a89, 0x46f3,
+ 0x6a6e, 0x471d, 0x6a52, 0x4747, 0x6a36, 0x4770, 0x6a1a, 0x479a,
+ 0x69fd, 0x47c4, 0x69e1, 0x47ed, 0x69c5, 0x4817, 0x69a9, 0x4840,
+ 0x698c, 0x486a, 0x6970, 0x4893, 0x6953, 0x48bd, 0x6937, 0x48e6,
+ 0x691a, 0x490f, 0x68fd, 0x4939, 0x68e0, 0x4962, 0x68c4, 0x498b,
+ 0x68a7, 0x49b4, 0x688a, 0x49dd, 0x686d, 0x4a06, 0x6850, 0x4a2f,
+ 0x6832, 0x4a58, 0x6815, 0x4a81, 0x67f8, 0x4aaa, 0x67da, 0x4ad3,
+ 0x67bd, 0x4afb, 0x67a0, 0x4b24, 0x6782, 0x4b4d, 0x6764, 0x4b75,
+ 0x6747, 0x4b9e, 0x6729, 0x4bc7, 0x670b, 0x4bef, 0x66ed, 0x4c17,
+ 0x66d0, 0x4c40, 0x66b2, 0x4c68, 0x6693, 0x4c91, 0x6675, 0x4cb9,
+ 0x6657, 0x4ce1, 0x6639, 0x4d09, 0x661b, 0x4d31, 0x65fc, 0x4d59,
+ 0x65de, 0x4d81, 0x65c0, 0x4da9, 0x65a1, 0x4dd1, 0x6582, 0x4df9,
+ 0x6564, 0x4e21, 0x6545, 0x4e49, 0x6526, 0x4e71, 0x6507, 0x4e98,
+ 0x64e9, 0x4ec0, 0x64ca, 0x4ee8, 0x64ab, 0x4f0f, 0x648b, 0x4f37,
+ 0x646c, 0x4f5e, 0x644d, 0x4f85, 0x642e, 0x4fad, 0x640f, 0x4fd4,
+ 0x63ef, 0x4ffb, 0x63d0, 0x5023, 0x63b0, 0x504a, 0x6391, 0x5071,
+ 0x6371, 0x5098, 0x6351, 0x50bf, 0x6332, 0x50e6, 0x6312, 0x510d,
+ 0x62f2, 0x5134, 0x62d2, 0x515b, 0x62b2, 0x5181, 0x6292, 0x51a8,
+ 0x6272, 0x51cf, 0x6252, 0x51f5, 0x6232, 0x521c, 0x6211, 0x5243,
+ 0x61f1, 0x5269, 0x61d1, 0x5290, 0x61b0, 0x52b6, 0x6190, 0x52dc,
+ 0x616f, 0x5303, 0x614e, 0x5329, 0x612e, 0x534f, 0x610d, 0x5375,
+ 0x60ec, 0x539b, 0x60cb, 0x53c1, 0x60aa, 0x53e7, 0x6089, 0x540d,
+ 0x6068, 0x5433, 0x6047, 0x5459, 0x6026, 0x547f, 0x6005, 0x54a4,
+ 0x5fe4, 0x54ca, 0x5fc2, 0x54f0, 0x5fa1, 0x5515, 0x5f80, 0x553b,
+ 0x5f5e, 0x5560, 0x5f3c, 0x5586, 0x5f1b, 0x55ab, 0x5ef9, 0x55d0,
+ 0x5ed7, 0x55f6, 0x5eb6, 0x561b, 0x5e94, 0x5640, 0x5e72, 0x5665,
+ 0x5e50, 0x568a, 0x5e2e, 0x56af, 0x5e0c, 0x56d4, 0x5dea, 0x56f9,
+ 0x5dc8, 0x571e, 0x5da5, 0x5743, 0x5d83, 0x5767, 0x5d61, 0x578c,
+ 0x5d3e, 0x57b1, 0x5d1c, 0x57d5, 0x5cf9, 0x57fa, 0x5cd7, 0x581e,
+ 0x5cb4, 0x5843, 0x5c91, 0x5867, 0x5c6f, 0x588c, 0x5c4c, 0x58b0,
+ 0x5c29, 0x58d4, 0x5c06, 0x58f8, 0x5be3, 0x591c, 0x5bc0, 0x5940,
+ 0x5b9d, 0x5964, 0x5b7a, 0x5988, 0x5b57, 0x59ac, 0x5b34, 0x59d0,
+ 0x5b10, 0x59f4, 0x5aed, 0x5a18, 0x5ac9, 0x5a3b, 0x5aa6, 0x5a5f,
+ 0x5a82, 0x5a82, 0x5a5f, 0x5aa6, 0x5a3b, 0x5ac9, 0x5a18, 0x5aed,
+ 0x59f4, 0x5b10, 0x59d0, 0x5b34, 0x59ac, 0x5b57, 0x5988, 0x5b7a,
+ 0x5964, 0x5b9d, 0x5940, 0x5bc0, 0x591c, 0x5be3, 0x58f8, 0x5c06,
+ 0x58d4, 0x5c29, 0x58b0, 0x5c4c, 0x588c, 0x5c6f, 0x5867, 0x5c91,
+ 0x5843, 0x5cb4, 0x581e, 0x5cd7, 0x57fa, 0x5cf9, 0x57d5, 0x5d1c,
+ 0x57b1, 0x5d3e, 0x578c, 0x5d61, 0x5767, 0x5d83, 0x5743, 0x5da5,
+ 0x571e, 0x5dc8, 0x56f9, 0x5dea, 0x56d4, 0x5e0c, 0x56af, 0x5e2e,
+ 0x568a, 0x5e50, 0x5665, 0x5e72, 0x5640, 0x5e94, 0x561b, 0x5eb6,
+ 0x55f6, 0x5ed7, 0x55d0, 0x5ef9, 0x55ab, 0x5f1b, 0x5586, 0x5f3c,
+ 0x5560, 0x5f5e, 0x553b, 0x5f80, 0x5515, 0x5fa1, 0x54f0, 0x5fc2,
+ 0x54ca, 0x5fe4, 0x54a4, 0x6005, 0x547f, 0x6026, 0x5459, 0x6047,
+ 0x5433, 0x6068, 0x540d, 0x6089, 0x53e7, 0x60aa, 0x53c1, 0x60cb,
+ 0x539b, 0x60ec, 0x5375, 0x610d, 0x534f, 0x612e, 0x5329, 0x614e,
+ 0x5303, 0x616f, 0x52dc, 0x6190, 0x52b6, 0x61b0, 0x5290, 0x61d1,
+ 0x5269, 0x61f1, 0x5243, 0x6211, 0x521c, 0x6232, 0x51f5, 0x6252,
+ 0x51cf, 0x6272, 0x51a8, 0x6292, 0x5181, 0x62b2, 0x515b, 0x62d2,
+ 0x5134, 0x62f2, 0x510d, 0x6312, 0x50e6, 0x6332, 0x50bf, 0x6351,
+ 0x5098, 0x6371, 0x5071, 0x6391, 0x504a, 0x63b0, 0x5023, 0x63d0,
+ 0x4ffb, 0x63ef, 0x4fd4, 0x640f, 0x4fad, 0x642e, 0x4f85, 0x644d,
+ 0x4f5e, 0x646c, 0x4f37, 0x648b, 0x4f0f, 0x64ab, 0x4ee8, 0x64ca,
+ 0x4ec0, 0x64e9, 0x4e98, 0x6507, 0x4e71, 0x6526, 0x4e49, 0x6545,
+ 0x4e21, 0x6564, 0x4df9, 0x6582, 0x4dd1, 0x65a1, 0x4da9, 0x65c0,
+ 0x4d81, 0x65de, 0x4d59, 0x65fc, 0x4d31, 0x661b, 0x4d09, 0x6639,
+ 0x4ce1, 0x6657, 0x4cb9, 0x6675, 0x4c91, 0x6693, 0x4c68, 0x66b2,
+ 0x4c40, 0x66d0, 0x4c17, 0x66ed, 0x4bef, 0x670b, 0x4bc7, 0x6729,
+ 0x4b9e, 0x6747, 0x4b75, 0x6764, 0x4b4d, 0x6782, 0x4b24, 0x67a0,
+ 0x4afb, 0x67bd, 0x4ad3, 0x67da, 0x4aaa, 0x67f8, 0x4a81, 0x6815,
+ 0x4a58, 0x6832, 0x4a2f, 0x6850, 0x4a06, 0x686d, 0x49dd, 0x688a,
+ 0x49b4, 0x68a7, 0x498b, 0x68c4, 0x4962, 0x68e0, 0x4939, 0x68fd,
+ 0x490f, 0x691a, 0x48e6, 0x6937, 0x48bd, 0x6953, 0x4893, 0x6970,
+ 0x486a, 0x698c, 0x4840, 0x69a9, 0x4817, 0x69c5, 0x47ed, 0x69e1,
+ 0x47c4, 0x69fd, 0x479a, 0x6a1a, 0x4770, 0x6a36, 0x4747, 0x6a52,
+ 0x471d, 0x6a6e, 0x46f3, 0x6a89, 0x46c9, 0x6aa5, 0x469f, 0x6ac1,
+ 0x4675, 0x6add, 0x464b, 0x6af8, 0x4621, 0x6b14, 0x45f7, 0x6b30,
+ 0x45cd, 0x6b4b, 0x45a3, 0x6b66, 0x4579, 0x6b82, 0x454f, 0x6b9d,
+ 0x4524, 0x6bb8, 0x44fa, 0x6bd3, 0x44d0, 0x6bee, 0x44a5, 0x6c09,
+ 0x447b, 0x6c24, 0x4450, 0x6c3f, 0x4426, 0x6c5a, 0x43fb, 0x6c75,
+ 0x43d1, 0x6c8f, 0x43a6, 0x6caa, 0x437b, 0x6cc4, 0x4351, 0x6cdf,
+ 0x4326, 0x6cf9, 0x42fb, 0x6d14, 0x42d0, 0x6d2e, 0x42a5, 0x6d48,
+ 0x427a, 0x6d62, 0x424f, 0x6d7c, 0x4224, 0x6d96, 0x41f9, 0x6db0,
+ 0x41ce, 0x6dca, 0x41a3, 0x6de4, 0x4178, 0x6dfe, 0x414d, 0x6e17,
+ 0x4121, 0x6e31, 0x40f6, 0x6e4a, 0x40cb, 0x6e64, 0x409f, 0x6e7d,
+ 0x4074, 0x6e97, 0x4048, 0x6eb0, 0x401d, 0x6ec9, 0x3ff1, 0x6ee2,
+ 0x3fc6, 0x6efb, 0x3f9a, 0x6f14, 0x3f6f, 0x6f2d, 0x3f43, 0x6f46,
+ 0x3f17, 0x6f5f, 0x3eec, 0x6f78, 0x3ec0, 0x6f90, 0x3e94, 0x6fa9,
+ 0x3e68, 0x6fc2, 0x3e3c, 0x6fda, 0x3e10, 0x6ff2, 0x3de4, 0x700b,
+ 0x3db8, 0x7023, 0x3d8c, 0x703b, 0x3d60, 0x7053, 0x3d34, 0x706b,
+ 0x3d08, 0x7083, 0x3cdc, 0x709b, 0x3caf, 0x70b3, 0x3c83, 0x70cb,
+ 0x3c57, 0x70e3, 0x3c2a, 0x70fa, 0x3bfe, 0x7112, 0x3bd2, 0x712a,
+ 0x3ba5, 0x7141, 0x3b79, 0x7158, 0x3b4c, 0x7170, 0x3b20, 0x7187,
+ 0x3af3, 0x719e, 0x3ac6, 0x71b5, 0x3a9a, 0x71cc, 0x3a6d, 0x71e3,
+ 0x3a40, 0x71fa, 0x3a13, 0x7211, 0x39e7, 0x7228, 0x39ba, 0x723f,
+ 0x398d, 0x7255, 0x3960, 0x726c, 0x3933, 0x7282, 0x3906, 0x7299,
+ 0x38d9, 0x72af, 0x38ac, 0x72c5, 0x387f, 0x72dc, 0x3852, 0x72f2,
+ 0x3825, 0x7308, 0x37f7, 0x731e, 0x37ca, 0x7334, 0x379d, 0x734a,
+ 0x3770, 0x735f, 0x3742, 0x7375, 0x3715, 0x738b, 0x36e8, 0x73a0,
+ 0x36ba, 0x73b6, 0x368d, 0x73cb, 0x365f, 0x73e1, 0x3632, 0x73f6,
+ 0x3604, 0x740b, 0x35d7, 0x7421, 0x35a9, 0x7436, 0x357b, 0x744b,
+ 0x354e, 0x7460, 0x3520, 0x7475, 0x34f2, 0x7489, 0x34c4, 0x749e,
+ 0x3497, 0x74b3, 0x3469, 0x74c7, 0x343b, 0x74dc, 0x340d, 0x74f0,
+ 0x33df, 0x7505, 0x33b1, 0x7519, 0x3383, 0x752d, 0x3355, 0x7542,
+ 0x3327, 0x7556, 0x32f9, 0x756a, 0x32cb, 0x757e, 0x329d, 0x7592,
+ 0x326e, 0x75a6, 0x3240, 0x75b9, 0x3212, 0x75cd, 0x31e4, 0x75e1,
+ 0x31b5, 0x75f4, 0x3187, 0x7608, 0x3159, 0x761b, 0x312a, 0x762e,
+ 0x30fc, 0x7642, 0x30cd, 0x7655, 0x309f, 0x7668, 0x3070, 0x767b,
+ 0x3042, 0x768e, 0x3013, 0x76a1, 0x2fe5, 0x76b4, 0x2fb6, 0x76c7,
+ 0x2f87, 0x76d9, 0x2f59, 0x76ec, 0x2f2a, 0x76fe, 0x2efb, 0x7711,
+ 0x2ecc, 0x7723, 0x2e9e, 0x7736, 0x2e6f, 0x7748, 0x2e40, 0x775a,
+ 0x2e11, 0x776c, 0x2de2, 0x777e, 0x2db3, 0x7790, 0x2d84, 0x77a2,
+ 0x2d55, 0x77b4, 0x2d26, 0x77c6, 0x2cf7, 0x77d8, 0x2cc8, 0x77e9,
+ 0x2c99, 0x77fb, 0x2c6a, 0x780c, 0x2c3b, 0x781e, 0x2c0c, 0x782f,
+ 0x2bdc, 0x7840, 0x2bad, 0x7851, 0x2b7e, 0x7863, 0x2b4f, 0x7874,
+ 0x2b1f, 0x7885, 0x2af0, 0x7895, 0x2ac1, 0x78a6, 0x2a91, 0x78b7,
+ 0x2a62, 0x78c8, 0x2a32, 0x78d8, 0x2a03, 0x78e9, 0x29d3, 0x78f9,
+ 0x29a4, 0x790a, 0x2974, 0x791a, 0x2945, 0x792a, 0x2915, 0x793a,
+ 0x28e5, 0x794a, 0x28b6, 0x795b, 0x2886, 0x796a, 0x2856, 0x797a,
+ 0x2827, 0x798a, 0x27f7, 0x799a, 0x27c7, 0x79aa, 0x2797, 0x79b9,
+ 0x2768, 0x79c9, 0x2738, 0x79d8, 0x2708, 0x79e7, 0x26d8, 0x79f7,
+ 0x26a8, 0x7a06, 0x2678, 0x7a15, 0x2648, 0x7a24, 0x2618, 0x7a33,
+ 0x25e8, 0x7a42, 0x25b8, 0x7a51, 0x2588, 0x7a60, 0x2558, 0x7a6e,
+ 0x2528, 0x7a7d, 0x24f8, 0x7a8c, 0x24c8, 0x7a9a, 0x2498, 0x7aa8,
+ 0x2467, 0x7ab7, 0x2437, 0x7ac5, 0x2407, 0x7ad3, 0x23d7, 0x7ae1,
+ 0x23a7, 0x7aef, 0x2376, 0x7afd, 0x2346, 0x7b0b, 0x2316, 0x7b19,
+ 0x22e5, 0x7b27, 0x22b5, 0x7b34, 0x2284, 0x7b42, 0x2254, 0x7b50,
+ 0x2224, 0x7b5d, 0x21f3, 0x7b6a, 0x21c3, 0x7b78, 0x2192, 0x7b85,
+ 0x2162, 0x7b92, 0x2131, 0x7b9f, 0x2101, 0x7bac, 0x20d0, 0x7bb9,
+ 0x209f, 0x7bc6, 0x206f, 0x7bd3, 0x203e, 0x7bdf, 0x200e, 0x7bec,
+ 0x1fdd, 0x7bf9, 0x1fac, 0x7c05, 0x1f7b, 0x7c11, 0x1f4b, 0x7c1e,
+ 0x1f1a, 0x7c2a, 0x1ee9, 0x7c36, 0x1eb8, 0x7c42, 0x1e88, 0x7c4e,
+ 0x1e57, 0x7c5a, 0x1e26, 0x7c66, 0x1df5, 0x7c72, 0x1dc4, 0x7c7e,
+ 0x1d93, 0x7c89, 0x1d62, 0x7c95, 0x1d31, 0x7ca0, 0x1d01, 0x7cac,
+ 0x1cd0, 0x7cb7, 0x1c9f, 0x7cc2, 0x1c6e, 0x7cce, 0x1c3d, 0x7cd9,
+ 0x1c0c, 0x7ce4, 0x1bda, 0x7cef, 0x1ba9, 0x7cfa, 0x1b78, 0x7d05,
+ 0x1b47, 0x7d0f, 0x1b16, 0x7d1a, 0x1ae5, 0x7d25, 0x1ab4, 0x7d2f,
+ 0x1a83, 0x7d3a, 0x1a51, 0x7d44, 0x1a20, 0x7d4e, 0x19ef, 0x7d58,
+ 0x19be, 0x7d63, 0x198d, 0x7d6d, 0x195b, 0x7d77, 0x192a, 0x7d81,
+ 0x18f9, 0x7d8a, 0x18c7, 0x7d94, 0x1896, 0x7d9e, 0x1865, 0x7da7,
+ 0x1833, 0x7db1, 0x1802, 0x7dba, 0x17d1, 0x7dc4, 0x179f, 0x7dcd,
+ 0x176e, 0x7dd6, 0x173c, 0x7de0, 0x170b, 0x7de9, 0x16da, 0x7df2,
+ 0x16a8, 0x7dfb, 0x1677, 0x7e03, 0x1645, 0x7e0c, 0x1614, 0x7e15,
+ 0x15e2, 0x7e1e, 0x15b1, 0x7e26, 0x157f, 0x7e2f, 0x154d, 0x7e37,
+ 0x151c, 0x7e3f, 0x14ea, 0x7e48, 0x14b9, 0x7e50, 0x1487, 0x7e58,
+ 0x1455, 0x7e60, 0x1424, 0x7e68, 0x13f2, 0x7e70, 0x13c1, 0x7e78,
+ 0x138f, 0x7e7f, 0x135d, 0x7e87, 0x132b, 0x7e8e, 0x12fa, 0x7e96,
+ 0x12c8, 0x7e9d, 0x1296, 0x7ea5, 0x1265, 0x7eac, 0x1233, 0x7eb3,
+ 0x1201, 0x7eba, 0x11cf, 0x7ec1, 0x119e, 0x7ec8, 0x116c, 0x7ecf,
+ 0x113a, 0x7ed6, 0x1108, 0x7edd, 0x10d6, 0x7ee3, 0x10a4, 0x7eea,
+ 0x1073, 0x7ef0, 0x1041, 0x7ef7, 0x100f, 0x7efd, 0xfdd, 0x7f03,
+ 0xfab, 0x7f0a, 0xf79, 0x7f10, 0xf47, 0x7f16, 0xf15, 0x7f1c,
+ 0xee4, 0x7f22, 0xeb2, 0x7f27, 0xe80, 0x7f2d, 0xe4e, 0x7f33,
+ 0xe1c, 0x7f38, 0xdea, 0x7f3e, 0xdb8, 0x7f43, 0xd86, 0x7f49,
+ 0xd54, 0x7f4e, 0xd22, 0x7f53, 0xcf0, 0x7f58, 0xcbe, 0x7f5d,
+ 0xc8c, 0x7f62, 0xc5a, 0x7f67, 0xc28, 0x7f6c, 0xbf6, 0x7f71,
+ 0xbc4, 0x7f75, 0xb92, 0x7f7a, 0xb60, 0x7f7e, 0xb2d, 0x7f83,
+ 0xafb, 0x7f87, 0xac9, 0x7f8b, 0xa97, 0x7f90, 0xa65, 0x7f94,
+ 0xa33, 0x7f98, 0xa01, 0x7f9c, 0x9cf, 0x7fa0, 0x99d, 0x7fa3,
+ 0x96b, 0x7fa7, 0x938, 0x7fab, 0x906, 0x7fae, 0x8d4, 0x7fb2,
+ 0x8a2, 0x7fb5, 0x870, 0x7fb9, 0x83e, 0x7fbc, 0x80c, 0x7fbf,
+ 0x7d9, 0x7fc2, 0x7a7, 0x7fc5, 0x775, 0x7fc8, 0x743, 0x7fcb,
+ 0x711, 0x7fce, 0x6de, 0x7fd1, 0x6ac, 0x7fd3, 0x67a, 0x7fd6,
+ 0x648, 0x7fd9, 0x616, 0x7fdb, 0x5e3, 0x7fdd, 0x5b1, 0x7fe0,
+ 0x57f, 0x7fe2, 0x54d, 0x7fe4, 0x51b, 0x7fe6, 0x4e8, 0x7fe8,
+ 0x4b6, 0x7fea, 0x484, 0x7fec, 0x452, 0x7fed, 0x41f, 0x7fef,
+ 0x3ed, 0x7ff1, 0x3bb, 0x7ff2, 0x389, 0x7ff4, 0x356, 0x7ff5,
+ 0x324, 0x7ff6, 0x2f2, 0x7ff7, 0x2c0, 0x7ff8, 0x28d, 0x7ff9,
+ 0x25b, 0x7ffa, 0x229, 0x7ffb, 0x1f7, 0x7ffc, 0x1c4, 0x7ffd,
+ 0x192, 0x7ffe, 0x160, 0x7ffe, 0x12e, 0x7fff, 0xfb, 0x7fff,
+ 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32, 0x7fff,
+ 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69, 0x7fff,
+ 0xff37, 0x7fff, 0xff05, 0x7fff, 0xfed2, 0x7fff, 0xfea0, 0x7ffe,
+ 0xfe6e, 0x7ffe, 0xfe3c, 0x7ffd, 0xfe09, 0x7ffc, 0xfdd7, 0x7ffb,
+ 0xfda5, 0x7ffa, 0xfd73, 0x7ff9, 0xfd40, 0x7ff8, 0xfd0e, 0x7ff7,
+ 0xfcdc, 0x7ff6, 0xfcaa, 0x7ff5, 0xfc77, 0x7ff4, 0xfc45, 0x7ff2,
+ 0xfc13, 0x7ff1, 0xfbe1, 0x7fef, 0xfbae, 0x7fed, 0xfb7c, 0x7fec,
+ 0xfb4a, 0x7fea, 0xfb18, 0x7fe8, 0xfae5, 0x7fe6, 0xfab3, 0x7fe4,
+ 0xfa81, 0x7fe2, 0xfa4f, 0x7fe0, 0xfa1d, 0x7fdd, 0xf9ea, 0x7fdb,
+ 0xf9b8, 0x7fd9, 0xf986, 0x7fd6, 0xf954, 0x7fd3, 0xf922, 0x7fd1,
+ 0xf8ef, 0x7fce, 0xf8bd, 0x7fcb, 0xf88b, 0x7fc8, 0xf859, 0x7fc5,
+ 0xf827, 0x7fc2, 0xf7f4, 0x7fbf, 0xf7c2, 0x7fbc, 0xf790, 0x7fb9,
+ 0xf75e, 0x7fb5, 0xf72c, 0x7fb2, 0xf6fa, 0x7fae, 0xf6c8, 0x7fab,
+ 0xf695, 0x7fa7, 0xf663, 0x7fa3, 0xf631, 0x7fa0, 0xf5ff, 0x7f9c,
+ 0xf5cd, 0x7f98, 0xf59b, 0x7f94, 0xf569, 0x7f90, 0xf537, 0x7f8b,
+ 0xf505, 0x7f87, 0xf4d3, 0x7f83, 0xf4a0, 0x7f7e, 0xf46e, 0x7f7a,
+ 0xf43c, 0x7f75, 0xf40a, 0x7f71, 0xf3d8, 0x7f6c, 0xf3a6, 0x7f67,
+ 0xf374, 0x7f62, 0xf342, 0x7f5d, 0xf310, 0x7f58, 0xf2de, 0x7f53,
+ 0xf2ac, 0x7f4e, 0xf27a, 0x7f49, 0xf248, 0x7f43, 0xf216, 0x7f3e,
+ 0xf1e4, 0x7f38, 0xf1b2, 0x7f33, 0xf180, 0x7f2d, 0xf14e, 0x7f27,
+ 0xf11c, 0x7f22, 0xf0eb, 0x7f1c, 0xf0b9, 0x7f16, 0xf087, 0x7f10,
+ 0xf055, 0x7f0a, 0xf023, 0x7f03, 0xeff1, 0x7efd, 0xefbf, 0x7ef7,
+ 0xef8d, 0x7ef0, 0xef5c, 0x7eea, 0xef2a, 0x7ee3, 0xeef8, 0x7edd,
+ 0xeec6, 0x7ed6, 0xee94, 0x7ecf, 0xee62, 0x7ec8, 0xee31, 0x7ec1,
+ 0xedff, 0x7eba, 0xedcd, 0x7eb3, 0xed9b, 0x7eac, 0xed6a, 0x7ea5,
+ 0xed38, 0x7e9d, 0xed06, 0x7e96, 0xecd5, 0x7e8e, 0xeca3, 0x7e87,
+ 0xec71, 0x7e7f, 0xec3f, 0x7e78, 0xec0e, 0x7e70, 0xebdc, 0x7e68,
+ 0xebab, 0x7e60, 0xeb79, 0x7e58, 0xeb47, 0x7e50, 0xeb16, 0x7e48,
+ 0xeae4, 0x7e3f, 0xeab3, 0x7e37, 0xea81, 0x7e2f, 0xea4f, 0x7e26,
+ 0xea1e, 0x7e1e, 0xe9ec, 0x7e15, 0xe9bb, 0x7e0c, 0xe989, 0x7e03,
+ 0xe958, 0x7dfb, 0xe926, 0x7df2, 0xe8f5, 0x7de9, 0xe8c4, 0x7de0,
+ 0xe892, 0x7dd6, 0xe861, 0x7dcd, 0xe82f, 0x7dc4, 0xe7fe, 0x7dba,
+ 0xe7cd, 0x7db1, 0xe79b, 0x7da7, 0xe76a, 0x7d9e, 0xe739, 0x7d94,
+ 0xe707, 0x7d8a, 0xe6d6, 0x7d81, 0xe6a5, 0x7d77, 0xe673, 0x7d6d,
+ 0xe642, 0x7d63, 0xe611, 0x7d58, 0xe5e0, 0x7d4e, 0xe5af, 0x7d44,
+ 0xe57d, 0x7d3a, 0xe54c, 0x7d2f, 0xe51b, 0x7d25, 0xe4ea, 0x7d1a,
+ 0xe4b9, 0x7d0f, 0xe488, 0x7d05, 0xe457, 0x7cfa, 0xe426, 0x7cef,
+ 0xe3f4, 0x7ce4, 0xe3c3, 0x7cd9, 0xe392, 0x7cce, 0xe361, 0x7cc2,
+ 0xe330, 0x7cb7, 0xe2ff, 0x7cac, 0xe2cf, 0x7ca0, 0xe29e, 0x7c95,
+ 0xe26d, 0x7c89, 0xe23c, 0x7c7e, 0xe20b, 0x7c72, 0xe1da, 0x7c66,
+ 0xe1a9, 0x7c5a, 0xe178, 0x7c4e, 0xe148, 0x7c42, 0xe117, 0x7c36,
+ 0xe0e6, 0x7c2a, 0xe0b5, 0x7c1e, 0xe085, 0x7c11, 0xe054, 0x7c05,
+ 0xe023, 0x7bf9, 0xdff2, 0x7bec, 0xdfc2, 0x7bdf, 0xdf91, 0x7bd3,
+ 0xdf61, 0x7bc6, 0xdf30, 0x7bb9, 0xdeff, 0x7bac, 0xdecf, 0x7b9f,
+ 0xde9e, 0x7b92, 0xde6e, 0x7b85, 0xde3d, 0x7b78, 0xde0d, 0x7b6a,
+ 0xdddc, 0x7b5d, 0xddac, 0x7b50, 0xdd7c, 0x7b42, 0xdd4b, 0x7b34,
+ 0xdd1b, 0x7b27, 0xdcea, 0x7b19, 0xdcba, 0x7b0b, 0xdc8a, 0x7afd,
+ 0xdc59, 0x7aef, 0xdc29, 0x7ae1, 0xdbf9, 0x7ad3, 0xdbc9, 0x7ac5,
+ 0xdb99, 0x7ab7, 0xdb68, 0x7aa8, 0xdb38, 0x7a9a, 0xdb08, 0x7a8c,
+ 0xdad8, 0x7a7d, 0xdaa8, 0x7a6e, 0xda78, 0x7a60, 0xda48, 0x7a51,
+ 0xda18, 0x7a42, 0xd9e8, 0x7a33, 0xd9b8, 0x7a24, 0xd988, 0x7a15,
+ 0xd958, 0x7a06, 0xd928, 0x79f7, 0xd8f8, 0x79e7, 0xd8c8, 0x79d8,
+ 0xd898, 0x79c9, 0xd869, 0x79b9, 0xd839, 0x79aa, 0xd809, 0x799a,
+ 0xd7d9, 0x798a, 0xd7aa, 0x797a, 0xd77a, 0x796a, 0xd74a, 0x795b,
+ 0xd71b, 0x794a, 0xd6eb, 0x793a, 0xd6bb, 0x792a, 0xd68c, 0x791a,
+ 0xd65c, 0x790a, 0xd62d, 0x78f9, 0xd5fd, 0x78e9, 0xd5ce, 0x78d8,
+ 0xd59e, 0x78c8, 0xd56f, 0x78b7, 0xd53f, 0x78a6, 0xd510, 0x7895,
+ 0xd4e1, 0x7885, 0xd4b1, 0x7874, 0xd482, 0x7863, 0xd453, 0x7851,
+ 0xd424, 0x7840, 0xd3f4, 0x782f, 0xd3c5, 0x781e, 0xd396, 0x780c,
+ 0xd367, 0x77fb, 0xd338, 0x77e9, 0xd309, 0x77d8, 0xd2da, 0x77c6,
+ 0xd2ab, 0x77b4, 0xd27c, 0x77a2, 0xd24d, 0x7790, 0xd21e, 0x777e,
+ 0xd1ef, 0x776c, 0xd1c0, 0x775a, 0xd191, 0x7748, 0xd162, 0x7736,
+ 0xd134, 0x7723, 0xd105, 0x7711, 0xd0d6, 0x76fe, 0xd0a7, 0x76ec,
+ 0xd079, 0x76d9, 0xd04a, 0x76c7, 0xd01b, 0x76b4, 0xcfed, 0x76a1,
+ 0xcfbe, 0x768e, 0xcf90, 0x767b, 0xcf61, 0x7668, 0xcf33, 0x7655,
+ 0xcf04, 0x7642, 0xced6, 0x762e, 0xcea7, 0x761b, 0xce79, 0x7608,
+ 0xce4b, 0x75f4, 0xce1c, 0x75e1, 0xcdee, 0x75cd, 0xcdc0, 0x75b9,
+ 0xcd92, 0x75a6, 0xcd63, 0x7592, 0xcd35, 0x757e, 0xcd07, 0x756a,
+ 0xccd9, 0x7556, 0xccab, 0x7542, 0xcc7d, 0x752d, 0xcc4f, 0x7519,
+ 0xcc21, 0x7505, 0xcbf3, 0x74f0, 0xcbc5, 0x74dc, 0xcb97, 0x74c7,
+ 0xcb69, 0x74b3, 0xcb3c, 0x749e, 0xcb0e, 0x7489, 0xcae0, 0x7475,
+ 0xcab2, 0x7460, 0xca85, 0x744b, 0xca57, 0x7436, 0xca29, 0x7421,
+ 0xc9fc, 0x740b, 0xc9ce, 0x73f6, 0xc9a1, 0x73e1, 0xc973, 0x73cb,
+ 0xc946, 0x73b6, 0xc918, 0x73a0, 0xc8eb, 0x738b, 0xc8be, 0x7375,
+ 0xc890, 0x735f, 0xc863, 0x734a, 0xc836, 0x7334, 0xc809, 0x731e,
+ 0xc7db, 0x7308, 0xc7ae, 0x72f2, 0xc781, 0x72dc, 0xc754, 0x72c5,
+ 0xc727, 0x72af, 0xc6fa, 0x7299, 0xc6cd, 0x7282, 0xc6a0, 0x726c,
+ 0xc673, 0x7255, 0xc646, 0x723f, 0xc619, 0x7228, 0xc5ed, 0x7211,
+ 0xc5c0, 0x71fa, 0xc593, 0x71e3, 0xc566, 0x71cc, 0xc53a, 0x71b5,
+ 0xc50d, 0x719e, 0xc4e0, 0x7187, 0xc4b4, 0x7170, 0xc487, 0x7158,
+ 0xc45b, 0x7141, 0xc42e, 0x712a, 0xc402, 0x7112, 0xc3d6, 0x70fa,
+ 0xc3a9, 0x70e3, 0xc37d, 0x70cb, 0xc351, 0x70b3, 0xc324, 0x709b,
+ 0xc2f8, 0x7083, 0xc2cc, 0x706b, 0xc2a0, 0x7053, 0xc274, 0x703b,
+ 0xc248, 0x7023, 0xc21c, 0x700b, 0xc1f0, 0x6ff2, 0xc1c4, 0x6fda,
+ 0xc198, 0x6fc2, 0xc16c, 0x6fa9, 0xc140, 0x6f90, 0xc114, 0x6f78,
+ 0xc0e9, 0x6f5f, 0xc0bd, 0x6f46, 0xc091, 0x6f2d, 0xc066, 0x6f14,
+ 0xc03a, 0x6efb, 0xc00f, 0x6ee2, 0xbfe3, 0x6ec9, 0xbfb8, 0x6eb0,
+ 0xbf8c, 0x6e97, 0xbf61, 0x6e7d, 0xbf35, 0x6e64, 0xbf0a, 0x6e4a,
+ 0xbedf, 0x6e31, 0xbeb3, 0x6e17, 0xbe88, 0x6dfe, 0xbe5d, 0x6de4,
+ 0xbe32, 0x6dca, 0xbe07, 0x6db0, 0xbddc, 0x6d96, 0xbdb1, 0x6d7c,
+ 0xbd86, 0x6d62, 0xbd5b, 0x6d48, 0xbd30, 0x6d2e, 0xbd05, 0x6d14,
+ 0xbcda, 0x6cf9, 0xbcaf, 0x6cdf, 0xbc85, 0x6cc4, 0xbc5a, 0x6caa,
+ 0xbc2f, 0x6c8f, 0xbc05, 0x6c75, 0xbbda, 0x6c5a, 0xbbb0, 0x6c3f,
+ 0xbb85, 0x6c24, 0xbb5b, 0x6c09, 0xbb30, 0x6bee, 0xbb06, 0x6bd3,
+ 0xbadc, 0x6bb8, 0xbab1, 0x6b9d, 0xba87, 0x6b82, 0xba5d, 0x6b66,
+ 0xba33, 0x6b4b, 0xba09, 0x6b30, 0xb9df, 0x6b14, 0xb9b5, 0x6af8,
+ 0xb98b, 0x6add, 0xb961, 0x6ac1, 0xb937, 0x6aa5, 0xb90d, 0x6a89,
+ 0xb8e3, 0x6a6e, 0xb8b9, 0x6a52, 0xb890, 0x6a36, 0xb866, 0x6a1a,
+ 0xb83c, 0x69fd, 0xb813, 0x69e1, 0xb7e9, 0x69c5, 0xb7c0, 0x69a9,
+ 0xb796, 0x698c, 0xb76d, 0x6970, 0xb743, 0x6953, 0xb71a, 0x6937,
+ 0xb6f1, 0x691a, 0xb6c7, 0x68fd, 0xb69e, 0x68e0, 0xb675, 0x68c4,
+ 0xb64c, 0x68a7, 0xb623, 0x688a, 0xb5fa, 0x686d, 0xb5d1, 0x6850,
+ 0xb5a8, 0x6832, 0xb57f, 0x6815, 0xb556, 0x67f8, 0xb52d, 0x67da,
+ 0xb505, 0x67bd, 0xb4dc, 0x67a0, 0xb4b3, 0x6782, 0xb48b, 0x6764,
+ 0xb462, 0x6747, 0xb439, 0x6729, 0xb411, 0x670b, 0xb3e9, 0x66ed,
+ 0xb3c0, 0x66d0, 0xb398, 0x66b2, 0xb36f, 0x6693, 0xb347, 0x6675,
+ 0xb31f, 0x6657, 0xb2f7, 0x6639, 0xb2cf, 0x661b, 0xb2a7, 0x65fc,
+ 0xb27f, 0x65de, 0xb257, 0x65c0, 0xb22f, 0x65a1, 0xb207, 0x6582,
+ 0xb1df, 0x6564, 0xb1b7, 0x6545, 0xb18f, 0x6526, 0xb168, 0x6507,
+ 0xb140, 0x64e9, 0xb118, 0x64ca, 0xb0f1, 0x64ab, 0xb0c9, 0x648b,
+ 0xb0a2, 0x646c, 0xb07b, 0x644d, 0xb053, 0x642e, 0xb02c, 0x640f,
+ 0xb005, 0x63ef, 0xafdd, 0x63d0, 0xafb6, 0x63b0, 0xaf8f, 0x6391,
+ 0xaf68, 0x6371, 0xaf41, 0x6351, 0xaf1a, 0x6332, 0xaef3, 0x6312,
+ 0xaecc, 0x62f2, 0xaea5, 0x62d2, 0xae7f, 0x62b2, 0xae58, 0x6292,
+ 0xae31, 0x6272, 0xae0b, 0x6252, 0xade4, 0x6232, 0xadbd, 0x6211,
+ 0xad97, 0x61f1, 0xad70, 0x61d1, 0xad4a, 0x61b0, 0xad24, 0x6190,
+ 0xacfd, 0x616f, 0xacd7, 0x614e, 0xacb1, 0x612e, 0xac8b, 0x610d,
+ 0xac65, 0x60ec, 0xac3f, 0x60cb, 0xac19, 0x60aa, 0xabf3, 0x6089,
+ 0xabcd, 0x6068, 0xaba7, 0x6047, 0xab81, 0x6026, 0xab5c, 0x6005,
+ 0xab36, 0x5fe4, 0xab10, 0x5fc2, 0xaaeb, 0x5fa1, 0xaac5, 0x5f80,
+ 0xaaa0, 0x5f5e, 0xaa7a, 0x5f3c, 0xaa55, 0x5f1b, 0xaa30, 0x5ef9,
+ 0xaa0a, 0x5ed7, 0xa9e5, 0x5eb6, 0xa9c0, 0x5e94, 0xa99b, 0x5e72,
+ 0xa976, 0x5e50, 0xa951, 0x5e2e, 0xa92c, 0x5e0c, 0xa907, 0x5dea,
+ 0xa8e2, 0x5dc8, 0xa8bd, 0x5da5, 0xa899, 0x5d83, 0xa874, 0x5d61,
+ 0xa84f, 0x5d3e, 0xa82b, 0x5d1c, 0xa806, 0x5cf9, 0xa7e2, 0x5cd7,
+ 0xa7bd, 0x5cb4, 0xa799, 0x5c91, 0xa774, 0x5c6f, 0xa750, 0x5c4c,
+ 0xa72c, 0x5c29, 0xa708, 0x5c06, 0xa6e4, 0x5be3, 0xa6c0, 0x5bc0,
+ 0xa69c, 0x5b9d, 0xa678, 0x5b7a, 0xa654, 0x5b57, 0xa630, 0x5b34,
+ 0xa60c, 0x5b10, 0xa5e8, 0x5aed, 0xa5c5, 0x5ac9, 0xa5a1, 0x5aa6,
+ 0xa57e, 0x5a82, 0xa55a, 0x5a5f, 0xa537, 0x5a3b, 0xa513, 0x5a18,
+ 0xa4f0, 0x59f4, 0xa4cc, 0x59d0, 0xa4a9, 0x59ac, 0xa486, 0x5988,
+ 0xa463, 0x5964, 0xa440, 0x5940, 0xa41d, 0x591c, 0xa3fa, 0x58f8,
+ 0xa3d7, 0x58d4, 0xa3b4, 0x58b0, 0xa391, 0x588c, 0xa36f, 0x5867,
+ 0xa34c, 0x5843, 0xa329, 0x581e, 0xa307, 0x57fa, 0xa2e4, 0x57d5,
+ 0xa2c2, 0x57b1, 0xa29f, 0x578c, 0xa27d, 0x5767, 0xa25b, 0x5743,
+ 0xa238, 0x571e, 0xa216, 0x56f9, 0xa1f4, 0x56d4, 0xa1d2, 0x56af,
+ 0xa1b0, 0x568a, 0xa18e, 0x5665, 0xa16c, 0x5640, 0xa14a, 0x561b,
+ 0xa129, 0x55f6, 0xa107, 0x55d0, 0xa0e5, 0x55ab, 0xa0c4, 0x5586,
+ 0xa0a2, 0x5560, 0xa080, 0x553b, 0xa05f, 0x5515, 0xa03e, 0x54f0,
+ 0xa01c, 0x54ca, 0x9ffb, 0x54a4, 0x9fda, 0x547f, 0x9fb9, 0x5459,
+ 0x9f98, 0x5433, 0x9f77, 0x540d, 0x9f56, 0x53e7, 0x9f35, 0x53c1,
+ 0x9f14, 0x539b, 0x9ef3, 0x5375, 0x9ed2, 0x534f, 0x9eb2, 0x5329,
+ 0x9e91, 0x5303, 0x9e70, 0x52dc, 0x9e50, 0x52b6, 0x9e2f, 0x5290,
+ 0x9e0f, 0x5269, 0x9def, 0x5243, 0x9dce, 0x521c, 0x9dae, 0x51f5,
+ 0x9d8e, 0x51cf, 0x9d6e, 0x51a8, 0x9d4e, 0x5181, 0x9d2e, 0x515b,
+ 0x9d0e, 0x5134, 0x9cee, 0x510d, 0x9cce, 0x50e6, 0x9caf, 0x50bf,
+ 0x9c8f, 0x5098, 0x9c6f, 0x5071, 0x9c50, 0x504a, 0x9c30, 0x5023,
+ 0x9c11, 0x4ffb, 0x9bf1, 0x4fd4, 0x9bd2, 0x4fad, 0x9bb3, 0x4f85,
+ 0x9b94, 0x4f5e, 0x9b75, 0x4f37, 0x9b55, 0x4f0f, 0x9b36, 0x4ee8,
+ 0x9b17, 0x4ec0, 0x9af9, 0x4e98, 0x9ada, 0x4e71, 0x9abb, 0x4e49,
+ 0x9a9c, 0x4e21, 0x9a7e, 0x4df9, 0x9a5f, 0x4dd1, 0x9a40, 0x4da9,
+ 0x9a22, 0x4d81, 0x9a04, 0x4d59, 0x99e5, 0x4d31, 0x99c7, 0x4d09,
+ 0x99a9, 0x4ce1, 0x998b, 0x4cb9, 0x996d, 0x4c91, 0x994e, 0x4c68,
+ 0x9930, 0x4c40, 0x9913, 0x4c17, 0x98f5, 0x4bef, 0x98d7, 0x4bc7,
+ 0x98b9, 0x4b9e, 0x989c, 0x4b75, 0x987e, 0x4b4d, 0x9860, 0x4b24,
+ 0x9843, 0x4afb, 0x9826, 0x4ad3, 0x9808, 0x4aaa, 0x97eb, 0x4a81,
+ 0x97ce, 0x4a58, 0x97b0, 0x4a2f, 0x9793, 0x4a06, 0x9776, 0x49dd,
+ 0x9759, 0x49b4, 0x973c, 0x498b, 0x9720, 0x4962, 0x9703, 0x4939,
+ 0x96e6, 0x490f, 0x96c9, 0x48e6, 0x96ad, 0x48bd, 0x9690, 0x4893,
+ 0x9674, 0x486a, 0x9657, 0x4840, 0x963b, 0x4817, 0x961f, 0x47ed,
+ 0x9603, 0x47c4, 0x95e6, 0x479a, 0x95ca, 0x4770, 0x95ae, 0x4747,
+ 0x9592, 0x471d, 0x9577, 0x46f3, 0x955b, 0x46c9, 0x953f, 0x469f,
+ 0x9523, 0x4675, 0x9508, 0x464b, 0x94ec, 0x4621, 0x94d0, 0x45f7,
+ 0x94b5, 0x45cd, 0x949a, 0x45a3, 0x947e, 0x4579, 0x9463, 0x454f,
+ 0x9448, 0x4524, 0x942d, 0x44fa, 0x9412, 0x44d0, 0x93f7, 0x44a5,
+ 0x93dc, 0x447b, 0x93c1, 0x4450, 0x93a6, 0x4426, 0x938b, 0x43fb,
+ 0x9371, 0x43d1, 0x9356, 0x43a6, 0x933c, 0x437b, 0x9321, 0x4351,
+ 0x9307, 0x4326, 0x92ec, 0x42fb, 0x92d2, 0x42d0, 0x92b8, 0x42a5,
+ 0x929e, 0x427a, 0x9284, 0x424f, 0x926a, 0x4224, 0x9250, 0x41f9,
+ 0x9236, 0x41ce, 0x921c, 0x41a3, 0x9202, 0x4178, 0x91e9, 0x414d,
+ 0x91cf, 0x4121, 0x91b6, 0x40f6, 0x919c, 0x40cb, 0x9183, 0x409f,
+ 0x9169, 0x4074, 0x9150, 0x4048, 0x9137, 0x401d, 0x911e, 0x3ff1,
+ 0x9105, 0x3fc6, 0x90ec, 0x3f9a, 0x90d3, 0x3f6f, 0x90ba, 0x3f43,
+ 0x90a1, 0x3f17, 0x9088, 0x3eec, 0x9070, 0x3ec0, 0x9057, 0x3e94,
+ 0x903e, 0x3e68, 0x9026, 0x3e3c, 0x900e, 0x3e10, 0x8ff5, 0x3de4,
+ 0x8fdd, 0x3db8, 0x8fc5, 0x3d8c, 0x8fad, 0x3d60, 0x8f95, 0x3d34,
+ 0x8f7d, 0x3d08, 0x8f65, 0x3cdc, 0x8f4d, 0x3caf, 0x8f35, 0x3c83,
+ 0x8f1d, 0x3c57, 0x8f06, 0x3c2a, 0x8eee, 0x3bfe, 0x8ed6, 0x3bd2,
+ 0x8ebf, 0x3ba5, 0x8ea8, 0x3b79, 0x8e90, 0x3b4c, 0x8e79, 0x3b20,
+ 0x8e62, 0x3af3, 0x8e4b, 0x3ac6, 0x8e34, 0x3a9a, 0x8e1d, 0x3a6d,
+ 0x8e06, 0x3a40, 0x8def, 0x3a13, 0x8dd8, 0x39e7, 0x8dc1, 0x39ba,
+ 0x8dab, 0x398d, 0x8d94, 0x3960, 0x8d7e, 0x3933, 0x8d67, 0x3906,
+ 0x8d51, 0x38d9, 0x8d3b, 0x38ac, 0x8d24, 0x387f, 0x8d0e, 0x3852,
+ 0x8cf8, 0x3825, 0x8ce2, 0x37f7, 0x8ccc, 0x37ca, 0x8cb6, 0x379d,
+ 0x8ca1, 0x3770, 0x8c8b, 0x3742, 0x8c75, 0x3715, 0x8c60, 0x36e8,
+ 0x8c4a, 0x36ba, 0x8c35, 0x368d, 0x8c1f, 0x365f, 0x8c0a, 0x3632,
+ 0x8bf5, 0x3604, 0x8bdf, 0x35d7, 0x8bca, 0x35a9, 0x8bb5, 0x357b,
+ 0x8ba0, 0x354e, 0x8b8b, 0x3520, 0x8b77, 0x34f2, 0x8b62, 0x34c4,
+ 0x8b4d, 0x3497, 0x8b39, 0x3469, 0x8b24, 0x343b, 0x8b10, 0x340d,
+ 0x8afb, 0x33df, 0x8ae7, 0x33b1, 0x8ad3, 0x3383, 0x8abe, 0x3355,
+ 0x8aaa, 0x3327, 0x8a96, 0x32f9, 0x8a82, 0x32cb, 0x8a6e, 0x329d,
+ 0x8a5a, 0x326e, 0x8a47, 0x3240, 0x8a33, 0x3212, 0x8a1f, 0x31e4,
+ 0x8a0c, 0x31b5, 0x89f8, 0x3187, 0x89e5, 0x3159, 0x89d2, 0x312a,
+ 0x89be, 0x30fc, 0x89ab, 0x30cd, 0x8998, 0x309f, 0x8985, 0x3070,
+ 0x8972, 0x3042, 0x895f, 0x3013, 0x894c, 0x2fe5, 0x8939, 0x2fb6,
+ 0x8927, 0x2f87, 0x8914, 0x2f59, 0x8902, 0x2f2a, 0x88ef, 0x2efb,
+ 0x88dd, 0x2ecc, 0x88ca, 0x2e9e, 0x88b8, 0x2e6f, 0x88a6, 0x2e40,
+ 0x8894, 0x2e11, 0x8882, 0x2de2, 0x8870, 0x2db3, 0x885e, 0x2d84,
+ 0x884c, 0x2d55, 0x883a, 0x2d26, 0x8828, 0x2cf7, 0x8817, 0x2cc8,
+ 0x8805, 0x2c99, 0x87f4, 0x2c6a, 0x87e2, 0x2c3b, 0x87d1, 0x2c0c,
+ 0x87c0, 0x2bdc, 0x87af, 0x2bad, 0x879d, 0x2b7e, 0x878c, 0x2b4f,
+ 0x877b, 0x2b1f, 0x876b, 0x2af0, 0x875a, 0x2ac1, 0x8749, 0x2a91,
+ 0x8738, 0x2a62, 0x8728, 0x2a32, 0x8717, 0x2a03, 0x8707, 0x29d3,
+ 0x86f6, 0x29a4, 0x86e6, 0x2974, 0x86d6, 0x2945, 0x86c6, 0x2915,
+ 0x86b6, 0x28e5, 0x86a5, 0x28b6, 0x8696, 0x2886, 0x8686, 0x2856,
+ 0x8676, 0x2827, 0x8666, 0x27f7, 0x8656, 0x27c7, 0x8647, 0x2797,
+ 0x8637, 0x2768, 0x8628, 0x2738, 0x8619, 0x2708, 0x8609, 0x26d8,
+ 0x85fa, 0x26a8, 0x85eb, 0x2678, 0x85dc, 0x2648, 0x85cd, 0x2618,
+ 0x85be, 0x25e8, 0x85af, 0x25b8, 0x85a0, 0x2588, 0x8592, 0x2558,
+ 0x8583, 0x2528, 0x8574, 0x24f8, 0x8566, 0x24c8, 0x8558, 0x2498,
+ 0x8549, 0x2467, 0x853b, 0x2437, 0x852d, 0x2407, 0x851f, 0x23d7,
+ 0x8511, 0x23a7, 0x8503, 0x2376, 0x84f5, 0x2346, 0x84e7, 0x2316,
+ 0x84d9, 0x22e5, 0x84cc, 0x22b5, 0x84be, 0x2284, 0x84b0, 0x2254,
+ 0x84a3, 0x2224, 0x8496, 0x21f3, 0x8488, 0x21c3, 0x847b, 0x2192,
+ 0x846e, 0x2162, 0x8461, 0x2131, 0x8454, 0x2101, 0x8447, 0x20d0,
+ 0x843a, 0x209f, 0x842d, 0x206f, 0x8421, 0x203e, 0x8414, 0x200e,
+ 0x8407, 0x1fdd, 0x83fb, 0x1fac, 0x83ef, 0x1f7b, 0x83e2, 0x1f4b,
+ 0x83d6, 0x1f1a, 0x83ca, 0x1ee9, 0x83be, 0x1eb8, 0x83b2, 0x1e88,
+ 0x83a6, 0x1e57, 0x839a, 0x1e26, 0x838e, 0x1df5, 0x8382, 0x1dc4,
+ 0x8377, 0x1d93, 0x836b, 0x1d62, 0x8360, 0x1d31, 0x8354, 0x1d01,
+ 0x8349, 0x1cd0, 0x833e, 0x1c9f, 0x8332, 0x1c6e, 0x8327, 0x1c3d,
+ 0x831c, 0x1c0c, 0x8311, 0x1bda, 0x8306, 0x1ba9, 0x82fb, 0x1b78,
+ 0x82f1, 0x1b47, 0x82e6, 0x1b16, 0x82db, 0x1ae5, 0x82d1, 0x1ab4,
+ 0x82c6, 0x1a83, 0x82bc, 0x1a51, 0x82b2, 0x1a20, 0x82a8, 0x19ef,
+ 0x829d, 0x19be, 0x8293, 0x198d, 0x8289, 0x195b, 0x827f, 0x192a,
+ 0x8276, 0x18f9, 0x826c, 0x18c7, 0x8262, 0x1896, 0x8259, 0x1865,
+ 0x824f, 0x1833, 0x8246, 0x1802, 0x823c, 0x17d1, 0x8233, 0x179f,
+ 0x822a, 0x176e, 0x8220, 0x173c, 0x8217, 0x170b, 0x820e, 0x16da,
+ 0x8205, 0x16a8, 0x81fd, 0x1677, 0x81f4, 0x1645, 0x81eb, 0x1614,
+ 0x81e2, 0x15e2, 0x81da, 0x15b1, 0x81d1, 0x157f, 0x81c9, 0x154d,
+ 0x81c1, 0x151c, 0x81b8, 0x14ea, 0x81b0, 0x14b9, 0x81a8, 0x1487,
+ 0x81a0, 0x1455, 0x8198, 0x1424, 0x8190, 0x13f2, 0x8188, 0x13c1,
+ 0x8181, 0x138f, 0x8179, 0x135d, 0x8172, 0x132b, 0x816a, 0x12fa,
+ 0x8163, 0x12c8, 0x815b, 0x1296, 0x8154, 0x1265, 0x814d, 0x1233,
+ 0x8146, 0x1201, 0x813f, 0x11cf, 0x8138, 0x119e, 0x8131, 0x116c,
+ 0x812a, 0x113a, 0x8123, 0x1108, 0x811d, 0x10d6, 0x8116, 0x10a4,
+ 0x8110, 0x1073, 0x8109, 0x1041, 0x8103, 0x100f, 0x80fd, 0xfdd,
+ 0x80f6, 0xfab, 0x80f0, 0xf79, 0x80ea, 0xf47, 0x80e4, 0xf15,
+ 0x80de, 0xee4, 0x80d9, 0xeb2, 0x80d3, 0xe80, 0x80cd, 0xe4e,
+ 0x80c8, 0xe1c, 0x80c2, 0xdea, 0x80bd, 0xdb8, 0x80b7, 0xd86,
+ 0x80b2, 0xd54, 0x80ad, 0xd22, 0x80a8, 0xcf0, 0x80a3, 0xcbe,
+ 0x809e, 0xc8c, 0x8099, 0xc5a, 0x8094, 0xc28, 0x808f, 0xbf6,
+ 0x808b, 0xbc4, 0x8086, 0xb92, 0x8082, 0xb60, 0x807d, 0xb2d,
+ 0x8079, 0xafb, 0x8075, 0xac9, 0x8070, 0xa97, 0x806c, 0xa65,
+ 0x8068, 0xa33, 0x8064, 0xa01, 0x8060, 0x9cf, 0x805d, 0x99d,
+ 0x8059, 0x96b, 0x8055, 0x938, 0x8052, 0x906, 0x804e, 0x8d4,
+ 0x804b, 0x8a2, 0x8047, 0x870, 0x8044, 0x83e, 0x8041, 0x80c,
+ 0x803e, 0x7d9, 0x803b, 0x7a7, 0x8038, 0x775, 0x8035, 0x743,
+ 0x8032, 0x711, 0x802f, 0x6de, 0x802d, 0x6ac, 0x802a, 0x67a,
+ 0x8027, 0x648, 0x8025, 0x616, 0x8023, 0x5e3, 0x8020, 0x5b1,
+ 0x801e, 0x57f, 0x801c, 0x54d, 0x801a, 0x51b, 0x8018, 0x4e8,
+ 0x8016, 0x4b6, 0x8014, 0x484, 0x8013, 0x452, 0x8011, 0x41f,
+ 0x800f, 0x3ed, 0x800e, 0x3bb, 0x800c, 0x389, 0x800b, 0x356,
+ 0x800a, 0x324, 0x8009, 0x2f2, 0x8008, 0x2c0, 0x8007, 0x28d,
+ 0x8006, 0x25b, 0x8005, 0x229, 0x8004, 0x1f7, 0x8003, 0x1c4,
+ 0x8002, 0x192, 0x8002, 0x160, 0x8001, 0x12e, 0x8001, 0xfb,
+ 0x8001, 0xc9, 0x8000, 0x97, 0x8000, 0x65, 0x8000, 0x32,
+ 0x8000, 0x0, 0x8000, 0xffce, 0x8000, 0xff9b, 0x8000, 0xff69,
+ 0x8001, 0xff37, 0x8001, 0xff05, 0x8001, 0xfed2, 0x8002, 0xfea0,
+ 0x8002, 0xfe6e, 0x8003, 0xfe3c, 0x8004, 0xfe09, 0x8005, 0xfdd7,
+ 0x8006, 0xfda5, 0x8007, 0xfd73, 0x8008, 0xfd40, 0x8009, 0xfd0e,
+ 0x800a, 0xfcdc, 0x800b, 0xfcaa, 0x800c, 0xfc77, 0x800e, 0xfc45,
+ 0x800f, 0xfc13, 0x8011, 0xfbe1, 0x8013, 0xfbae, 0x8014, 0xfb7c,
+ 0x8016, 0xfb4a, 0x8018, 0xfb18, 0x801a, 0xfae5, 0x801c, 0xfab3,
+ 0x801e, 0xfa81, 0x8020, 0xfa4f, 0x8023, 0xfa1d, 0x8025, 0xf9ea,
+ 0x8027, 0xf9b8, 0x802a, 0xf986, 0x802d, 0xf954, 0x802f, 0xf922,
+ 0x8032, 0xf8ef, 0x8035, 0xf8bd, 0x8038, 0xf88b, 0x803b, 0xf859,
+ 0x803e, 0xf827, 0x8041, 0xf7f4, 0x8044, 0xf7c2, 0x8047, 0xf790,
+ 0x804b, 0xf75e, 0x804e, 0xf72c, 0x8052, 0xf6fa, 0x8055, 0xf6c8,
+ 0x8059, 0xf695, 0x805d, 0xf663, 0x8060, 0xf631, 0x8064, 0xf5ff,
+ 0x8068, 0xf5cd, 0x806c, 0xf59b, 0x8070, 0xf569, 0x8075, 0xf537,
+ 0x8079, 0xf505, 0x807d, 0xf4d3, 0x8082, 0xf4a0, 0x8086, 0xf46e,
+ 0x808b, 0xf43c, 0x808f, 0xf40a, 0x8094, 0xf3d8, 0x8099, 0xf3a6,
+ 0x809e, 0xf374, 0x80a3, 0xf342, 0x80a8, 0xf310, 0x80ad, 0xf2de,
+ 0x80b2, 0xf2ac, 0x80b7, 0xf27a, 0x80bd, 0xf248, 0x80c2, 0xf216,
+ 0x80c8, 0xf1e4, 0x80cd, 0xf1b2, 0x80d3, 0xf180, 0x80d9, 0xf14e,
+ 0x80de, 0xf11c, 0x80e4, 0xf0eb, 0x80ea, 0xf0b9, 0x80f0, 0xf087,
+ 0x80f6, 0xf055, 0x80fd, 0xf023, 0x8103, 0xeff1, 0x8109, 0xefbf,
+ 0x8110, 0xef8d, 0x8116, 0xef5c, 0x811d, 0xef2a, 0x8123, 0xeef8,
+ 0x812a, 0xeec6, 0x8131, 0xee94, 0x8138, 0xee62, 0x813f, 0xee31,
+ 0x8146, 0xedff, 0x814d, 0xedcd, 0x8154, 0xed9b, 0x815b, 0xed6a,
+ 0x8163, 0xed38, 0x816a, 0xed06, 0x8172, 0xecd5, 0x8179, 0xeca3,
+ 0x8181, 0xec71, 0x8188, 0xec3f, 0x8190, 0xec0e, 0x8198, 0xebdc,
+ 0x81a0, 0xebab, 0x81a8, 0xeb79, 0x81b0, 0xeb47, 0x81b8, 0xeb16,
+ 0x81c1, 0xeae4, 0x81c9, 0xeab3, 0x81d1, 0xea81, 0x81da, 0xea4f,
+ 0x81e2, 0xea1e, 0x81eb, 0xe9ec, 0x81f4, 0xe9bb, 0x81fd, 0xe989,
+ 0x8205, 0xe958, 0x820e, 0xe926, 0x8217, 0xe8f5, 0x8220, 0xe8c4,
+ 0x822a, 0xe892, 0x8233, 0xe861, 0x823c, 0xe82f, 0x8246, 0xe7fe,
+ 0x824f, 0xe7cd, 0x8259, 0xe79b, 0x8262, 0xe76a, 0x826c, 0xe739,
+ 0x8276, 0xe707, 0x827f, 0xe6d6, 0x8289, 0xe6a5, 0x8293, 0xe673,
+ 0x829d, 0xe642, 0x82a8, 0xe611, 0x82b2, 0xe5e0, 0x82bc, 0xe5af,
+ 0x82c6, 0xe57d, 0x82d1, 0xe54c, 0x82db, 0xe51b, 0x82e6, 0xe4ea,
+ 0x82f1, 0xe4b9, 0x82fb, 0xe488, 0x8306, 0xe457, 0x8311, 0xe426,
+ 0x831c, 0xe3f4, 0x8327, 0xe3c3, 0x8332, 0xe392, 0x833e, 0xe361,
+ 0x8349, 0xe330, 0x8354, 0xe2ff, 0x8360, 0xe2cf, 0x836b, 0xe29e,
+ 0x8377, 0xe26d, 0x8382, 0xe23c, 0x838e, 0xe20b, 0x839a, 0xe1da,
+ 0x83a6, 0xe1a9, 0x83b2, 0xe178, 0x83be, 0xe148, 0x83ca, 0xe117,
+ 0x83d6, 0xe0e6, 0x83e2, 0xe0b5, 0x83ef, 0xe085, 0x83fb, 0xe054,
+ 0x8407, 0xe023, 0x8414, 0xdff2, 0x8421, 0xdfc2, 0x842d, 0xdf91,
+ 0x843a, 0xdf61, 0x8447, 0xdf30, 0x8454, 0xdeff, 0x8461, 0xdecf,
+ 0x846e, 0xde9e, 0x847b, 0xde6e, 0x8488, 0xde3d, 0x8496, 0xde0d,
+ 0x84a3, 0xdddc, 0x84b0, 0xddac, 0x84be, 0xdd7c, 0x84cc, 0xdd4b,
+ 0x84d9, 0xdd1b, 0x84e7, 0xdcea, 0x84f5, 0xdcba, 0x8503, 0xdc8a,
+ 0x8511, 0xdc59, 0x851f, 0xdc29, 0x852d, 0xdbf9, 0x853b, 0xdbc9,
+ 0x8549, 0xdb99, 0x8558, 0xdb68, 0x8566, 0xdb38, 0x8574, 0xdb08,
+ 0x8583, 0xdad8, 0x8592, 0xdaa8, 0x85a0, 0xda78, 0x85af, 0xda48,
+ 0x85be, 0xda18, 0x85cd, 0xd9e8, 0x85dc, 0xd9b8, 0x85eb, 0xd988,
+ 0x85fa, 0xd958, 0x8609, 0xd928, 0x8619, 0xd8f8, 0x8628, 0xd8c8,
+ 0x8637, 0xd898, 0x8647, 0xd869, 0x8656, 0xd839, 0x8666, 0xd809,
+ 0x8676, 0xd7d9, 0x8686, 0xd7aa, 0x8696, 0xd77a, 0x86a5, 0xd74a,
+ 0x86b6, 0xd71b, 0x86c6, 0xd6eb, 0x86d6, 0xd6bb, 0x86e6, 0xd68c,
+ 0x86f6, 0xd65c, 0x8707, 0xd62d, 0x8717, 0xd5fd, 0x8728, 0xd5ce,
+ 0x8738, 0xd59e, 0x8749, 0xd56f, 0x875a, 0xd53f, 0x876b, 0xd510,
+ 0x877b, 0xd4e1, 0x878c, 0xd4b1, 0x879d, 0xd482, 0x87af, 0xd453,
+ 0x87c0, 0xd424, 0x87d1, 0xd3f4, 0x87e2, 0xd3c5, 0x87f4, 0xd396,
+ 0x8805, 0xd367, 0x8817, 0xd338, 0x8828, 0xd309, 0x883a, 0xd2da,
+ 0x884c, 0xd2ab, 0x885e, 0xd27c, 0x8870, 0xd24d, 0x8882, 0xd21e,
+ 0x8894, 0xd1ef, 0x88a6, 0xd1c0, 0x88b8, 0xd191, 0x88ca, 0xd162,
+ 0x88dd, 0xd134, 0x88ef, 0xd105, 0x8902, 0xd0d6, 0x8914, 0xd0a7,
+ 0x8927, 0xd079, 0x8939, 0xd04a, 0x894c, 0xd01b, 0x895f, 0xcfed,
+ 0x8972, 0xcfbe, 0x8985, 0xcf90, 0x8998, 0xcf61, 0x89ab, 0xcf33,
+ 0x89be, 0xcf04, 0x89d2, 0xced6, 0x89e5, 0xcea7, 0x89f8, 0xce79,
+ 0x8a0c, 0xce4b, 0x8a1f, 0xce1c, 0x8a33, 0xcdee, 0x8a47, 0xcdc0,
+ 0x8a5a, 0xcd92, 0x8a6e, 0xcd63, 0x8a82, 0xcd35, 0x8a96, 0xcd07,
+ 0x8aaa, 0xccd9, 0x8abe, 0xccab, 0x8ad3, 0xcc7d, 0x8ae7, 0xcc4f,
+ 0x8afb, 0xcc21, 0x8b10, 0xcbf3, 0x8b24, 0xcbc5, 0x8b39, 0xcb97,
+ 0x8b4d, 0xcb69, 0x8b62, 0xcb3c, 0x8b77, 0xcb0e, 0x8b8b, 0xcae0,
+ 0x8ba0, 0xcab2, 0x8bb5, 0xca85, 0x8bca, 0xca57, 0x8bdf, 0xca29,
+ 0x8bf5, 0xc9fc, 0x8c0a, 0xc9ce, 0x8c1f, 0xc9a1, 0x8c35, 0xc973,
+ 0x8c4a, 0xc946, 0x8c60, 0xc918, 0x8c75, 0xc8eb, 0x8c8b, 0xc8be,
+ 0x8ca1, 0xc890, 0x8cb6, 0xc863, 0x8ccc, 0xc836, 0x8ce2, 0xc809,
+ 0x8cf8, 0xc7db, 0x8d0e, 0xc7ae, 0x8d24, 0xc781, 0x8d3b, 0xc754,
+ 0x8d51, 0xc727, 0x8d67, 0xc6fa, 0x8d7e, 0xc6cd, 0x8d94, 0xc6a0,
+ 0x8dab, 0xc673, 0x8dc1, 0xc646, 0x8dd8, 0xc619, 0x8def, 0xc5ed,
+ 0x8e06, 0xc5c0, 0x8e1d, 0xc593, 0x8e34, 0xc566, 0x8e4b, 0xc53a,
+ 0x8e62, 0xc50d, 0x8e79, 0xc4e0, 0x8e90, 0xc4b4, 0x8ea8, 0xc487,
+ 0x8ebf, 0xc45b, 0x8ed6, 0xc42e, 0x8eee, 0xc402, 0x8f06, 0xc3d6,
+ 0x8f1d, 0xc3a9, 0x8f35, 0xc37d, 0x8f4d, 0xc351, 0x8f65, 0xc324,
+ 0x8f7d, 0xc2f8, 0x8f95, 0xc2cc, 0x8fad, 0xc2a0, 0x8fc5, 0xc274,
+ 0x8fdd, 0xc248, 0x8ff5, 0xc21c, 0x900e, 0xc1f0, 0x9026, 0xc1c4,
+ 0x903e, 0xc198, 0x9057, 0xc16c, 0x9070, 0xc140, 0x9088, 0xc114,
+ 0x90a1, 0xc0e9, 0x90ba, 0xc0bd, 0x90d3, 0xc091, 0x90ec, 0xc066,
+ 0x9105, 0xc03a, 0x911e, 0xc00f, 0x9137, 0xbfe3, 0x9150, 0xbfb8,
+ 0x9169, 0xbf8c, 0x9183, 0xbf61, 0x919c, 0xbf35, 0x91b6, 0xbf0a,
+ 0x91cf, 0xbedf, 0x91e9, 0xbeb3, 0x9202, 0xbe88, 0x921c, 0xbe5d,
+ 0x9236, 0xbe32, 0x9250, 0xbe07, 0x926a, 0xbddc, 0x9284, 0xbdb1,
+ 0x929e, 0xbd86, 0x92b8, 0xbd5b, 0x92d2, 0xbd30, 0x92ec, 0xbd05,
+ 0x9307, 0xbcda, 0x9321, 0xbcaf, 0x933c, 0xbc85, 0x9356, 0xbc5a,
+ 0x9371, 0xbc2f, 0x938b, 0xbc05, 0x93a6, 0xbbda, 0x93c1, 0xbbb0,
+ 0x93dc, 0xbb85, 0x93f7, 0xbb5b, 0x9412, 0xbb30, 0x942d, 0xbb06,
+ 0x9448, 0xbadc, 0x9463, 0xbab1, 0x947e, 0xba87, 0x949a, 0xba5d,
+ 0x94b5, 0xba33, 0x94d0, 0xba09, 0x94ec, 0xb9df, 0x9508, 0xb9b5,
+ 0x9523, 0xb98b, 0x953f, 0xb961, 0x955b, 0xb937, 0x9577, 0xb90d,
+ 0x9592, 0xb8e3, 0x95ae, 0xb8b9, 0x95ca, 0xb890, 0x95e6, 0xb866,
+ 0x9603, 0xb83c, 0x961f, 0xb813, 0x963b, 0xb7e9, 0x9657, 0xb7c0,
+ 0x9674, 0xb796, 0x9690, 0xb76d, 0x96ad, 0xb743, 0x96c9, 0xb71a,
+ 0x96e6, 0xb6f1, 0x9703, 0xb6c7, 0x9720, 0xb69e, 0x973c, 0xb675,
+ 0x9759, 0xb64c, 0x9776, 0xb623, 0x9793, 0xb5fa, 0x97b0, 0xb5d1,
+ 0x97ce, 0xb5a8, 0x97eb, 0xb57f, 0x9808, 0xb556, 0x9826, 0xb52d,
+ 0x9843, 0xb505, 0x9860, 0xb4dc, 0x987e, 0xb4b3, 0x989c, 0xb48b,
+ 0x98b9, 0xb462, 0x98d7, 0xb439, 0x98f5, 0xb411, 0x9913, 0xb3e9,
+ 0x9930, 0xb3c0, 0x994e, 0xb398, 0x996d, 0xb36f, 0x998b, 0xb347,
+ 0x99a9, 0xb31f, 0x99c7, 0xb2f7, 0x99e5, 0xb2cf, 0x9a04, 0xb2a7,
+ 0x9a22, 0xb27f, 0x9a40, 0xb257, 0x9a5f, 0xb22f, 0x9a7e, 0xb207,
+ 0x9a9c, 0xb1df, 0x9abb, 0xb1b7, 0x9ada, 0xb18f, 0x9af9, 0xb168,
+ 0x9b17, 0xb140, 0x9b36, 0xb118, 0x9b55, 0xb0f1, 0x9b75, 0xb0c9,
+ 0x9b94, 0xb0a2, 0x9bb3, 0xb07b, 0x9bd2, 0xb053, 0x9bf1, 0xb02c,
+ 0x9c11, 0xb005, 0x9c30, 0xafdd, 0x9c50, 0xafb6, 0x9c6f, 0xaf8f,
+ 0x9c8f, 0xaf68, 0x9caf, 0xaf41, 0x9cce, 0xaf1a, 0x9cee, 0xaef3,
+ 0x9d0e, 0xaecc, 0x9d2e, 0xaea5, 0x9d4e, 0xae7f, 0x9d6e, 0xae58,
+ 0x9d8e, 0xae31, 0x9dae, 0xae0b, 0x9dce, 0xade4, 0x9def, 0xadbd,
+ 0x9e0f, 0xad97, 0x9e2f, 0xad70, 0x9e50, 0xad4a, 0x9e70, 0xad24,
+ 0x9e91, 0xacfd, 0x9eb2, 0xacd7, 0x9ed2, 0xacb1, 0x9ef3, 0xac8b,
+ 0x9f14, 0xac65, 0x9f35, 0xac3f, 0x9f56, 0xac19, 0x9f77, 0xabf3,
+ 0x9f98, 0xabcd, 0x9fb9, 0xaba7, 0x9fda, 0xab81, 0x9ffb, 0xab5c,
+ 0xa01c, 0xab36, 0xa03e, 0xab10, 0xa05f, 0xaaeb, 0xa080, 0xaac5,
+ 0xa0a2, 0xaaa0, 0xa0c4, 0xaa7a, 0xa0e5, 0xaa55, 0xa107, 0xaa30,
+ 0xa129, 0xaa0a, 0xa14a, 0xa9e5, 0xa16c, 0xa9c0, 0xa18e, 0xa99b,
+ 0xa1b0, 0xa976, 0xa1d2, 0xa951, 0xa1f4, 0xa92c, 0xa216, 0xa907,
+ 0xa238, 0xa8e2, 0xa25b, 0xa8bd, 0xa27d, 0xa899, 0xa29f, 0xa874,
+ 0xa2c2, 0xa84f, 0xa2e4, 0xa82b, 0xa307, 0xa806, 0xa329, 0xa7e2,
+ 0xa34c, 0xa7bd, 0xa36f, 0xa799, 0xa391, 0xa774, 0xa3b4, 0xa750,
+ 0xa3d7, 0xa72c, 0xa3fa, 0xa708, 0xa41d, 0xa6e4, 0xa440, 0xa6c0,
+ 0xa463, 0xa69c, 0xa486, 0xa678, 0xa4a9, 0xa654, 0xa4cc, 0xa630,
+ 0xa4f0, 0xa60c, 0xa513, 0xa5e8, 0xa537, 0xa5c5, 0xa55a, 0xa5a1,
+ 0xa57e, 0xa57e, 0xa5a1, 0xa55a, 0xa5c5, 0xa537, 0xa5e8, 0xa513,
+ 0xa60c, 0xa4f0, 0xa630, 0xa4cc, 0xa654, 0xa4a9, 0xa678, 0xa486,
+ 0xa69c, 0xa463, 0xa6c0, 0xa440, 0xa6e4, 0xa41d, 0xa708, 0xa3fa,
+ 0xa72c, 0xa3d7, 0xa750, 0xa3b4, 0xa774, 0xa391, 0xa799, 0xa36f,
+ 0xa7bd, 0xa34c, 0xa7e2, 0xa329, 0xa806, 0xa307, 0xa82b, 0xa2e4,
+ 0xa84f, 0xa2c2, 0xa874, 0xa29f, 0xa899, 0xa27d, 0xa8bd, 0xa25b,
+ 0xa8e2, 0xa238, 0xa907, 0xa216, 0xa92c, 0xa1f4, 0xa951, 0xa1d2,
+ 0xa976, 0xa1b0, 0xa99b, 0xa18e, 0xa9c0, 0xa16c, 0xa9e5, 0xa14a,
+ 0xaa0a, 0xa129, 0xaa30, 0xa107, 0xaa55, 0xa0e5, 0xaa7a, 0xa0c4,
+ 0xaaa0, 0xa0a2, 0xaac5, 0xa080, 0xaaeb, 0xa05f, 0xab10, 0xa03e,
+ 0xab36, 0xa01c, 0xab5c, 0x9ffb, 0xab81, 0x9fda, 0xaba7, 0x9fb9,
+ 0xabcd, 0x9f98, 0xabf3, 0x9f77, 0xac19, 0x9f56, 0xac3f, 0x9f35,
+ 0xac65, 0x9f14, 0xac8b, 0x9ef3, 0xacb1, 0x9ed2, 0xacd7, 0x9eb2,
+ 0xacfd, 0x9e91, 0xad24, 0x9e70, 0xad4a, 0x9e50, 0xad70, 0x9e2f,
+ 0xad97, 0x9e0f, 0xadbd, 0x9def, 0xade4, 0x9dce, 0xae0b, 0x9dae,
+ 0xae31, 0x9d8e, 0xae58, 0x9d6e, 0xae7f, 0x9d4e, 0xaea5, 0x9d2e,
+ 0xaecc, 0x9d0e, 0xaef3, 0x9cee, 0xaf1a, 0x9cce, 0xaf41, 0x9caf,
+ 0xaf68, 0x9c8f, 0xaf8f, 0x9c6f, 0xafb6, 0x9c50, 0xafdd, 0x9c30,
+ 0xb005, 0x9c11, 0xb02c, 0x9bf1, 0xb053, 0x9bd2, 0xb07b, 0x9bb3,
+ 0xb0a2, 0x9b94, 0xb0c9, 0x9b75, 0xb0f1, 0x9b55, 0xb118, 0x9b36,
+ 0xb140, 0x9b17, 0xb168, 0x9af9, 0xb18f, 0x9ada, 0xb1b7, 0x9abb,
+ 0xb1df, 0x9a9c, 0xb207, 0x9a7e, 0xb22f, 0x9a5f, 0xb257, 0x9a40,
+ 0xb27f, 0x9a22, 0xb2a7, 0x9a04, 0xb2cf, 0x99e5, 0xb2f7, 0x99c7,
+ 0xb31f, 0x99a9, 0xb347, 0x998b, 0xb36f, 0x996d, 0xb398, 0x994e,
+ 0xb3c0, 0x9930, 0xb3e9, 0x9913, 0xb411, 0x98f5, 0xb439, 0x98d7,
+ 0xb462, 0x98b9, 0xb48b, 0x989c, 0xb4b3, 0x987e, 0xb4dc, 0x9860,
+ 0xb505, 0x9843, 0xb52d, 0x9826, 0xb556, 0x9808, 0xb57f, 0x97eb,
+ 0xb5a8, 0x97ce, 0xb5d1, 0x97b0, 0xb5fa, 0x9793, 0xb623, 0x9776,
+ 0xb64c, 0x9759, 0xb675, 0x973c, 0xb69e, 0x9720, 0xb6c7, 0x9703,
+ 0xb6f1, 0x96e6, 0xb71a, 0x96c9, 0xb743, 0x96ad, 0xb76d, 0x9690,
+ 0xb796, 0x9674, 0xb7c0, 0x9657, 0xb7e9, 0x963b, 0xb813, 0x961f,
+ 0xb83c, 0x9603, 0xb866, 0x95e6, 0xb890, 0x95ca, 0xb8b9, 0x95ae,
+ 0xb8e3, 0x9592, 0xb90d, 0x9577, 0xb937, 0x955b, 0xb961, 0x953f,
+ 0xb98b, 0x9523, 0xb9b5, 0x9508, 0xb9df, 0x94ec, 0xba09, 0x94d0,
+ 0xba33, 0x94b5, 0xba5d, 0x949a, 0xba87, 0x947e, 0xbab1, 0x9463,
+ 0xbadc, 0x9448, 0xbb06, 0x942d, 0xbb30, 0x9412, 0xbb5b, 0x93f7,
+ 0xbb85, 0x93dc, 0xbbb0, 0x93c1, 0xbbda, 0x93a6, 0xbc05, 0x938b,
+ 0xbc2f, 0x9371, 0xbc5a, 0x9356, 0xbc85, 0x933c, 0xbcaf, 0x9321,
+ 0xbcda, 0x9307, 0xbd05, 0x92ec, 0xbd30, 0x92d2, 0xbd5b, 0x92b8,
+ 0xbd86, 0x929e, 0xbdb1, 0x9284, 0xbddc, 0x926a, 0xbe07, 0x9250,
+ 0xbe32, 0x9236, 0xbe5d, 0x921c, 0xbe88, 0x9202, 0xbeb3, 0x91e9,
+ 0xbedf, 0x91cf, 0xbf0a, 0x91b6, 0xbf35, 0x919c, 0xbf61, 0x9183,
+ 0xbf8c, 0x9169, 0xbfb8, 0x9150, 0xbfe3, 0x9137, 0xc00f, 0x911e,
+ 0xc03a, 0x9105, 0xc066, 0x90ec, 0xc091, 0x90d3, 0xc0bd, 0x90ba,
+ 0xc0e9, 0x90a1, 0xc114, 0x9088, 0xc140, 0x9070, 0xc16c, 0x9057,
+ 0xc198, 0x903e, 0xc1c4, 0x9026, 0xc1f0, 0x900e, 0xc21c, 0x8ff5,
+ 0xc248, 0x8fdd, 0xc274, 0x8fc5, 0xc2a0, 0x8fad, 0xc2cc, 0x8f95,
+ 0xc2f8, 0x8f7d, 0xc324, 0x8f65, 0xc351, 0x8f4d, 0xc37d, 0x8f35,
+ 0xc3a9, 0x8f1d, 0xc3d6, 0x8f06, 0xc402, 0x8eee, 0xc42e, 0x8ed6,
+ 0xc45b, 0x8ebf, 0xc487, 0x8ea8, 0xc4b4, 0x8e90, 0xc4e0, 0x8e79,
+ 0xc50d, 0x8e62, 0xc53a, 0x8e4b, 0xc566, 0x8e34, 0xc593, 0x8e1d,
+ 0xc5c0, 0x8e06, 0xc5ed, 0x8def, 0xc619, 0x8dd8, 0xc646, 0x8dc1,
+ 0xc673, 0x8dab, 0xc6a0, 0x8d94, 0xc6cd, 0x8d7e, 0xc6fa, 0x8d67,
+ 0xc727, 0x8d51, 0xc754, 0x8d3b, 0xc781, 0x8d24, 0xc7ae, 0x8d0e,
+ 0xc7db, 0x8cf8, 0xc809, 0x8ce2, 0xc836, 0x8ccc, 0xc863, 0x8cb6,
+ 0xc890, 0x8ca1, 0xc8be, 0x8c8b, 0xc8eb, 0x8c75, 0xc918, 0x8c60,
+ 0xc946, 0x8c4a, 0xc973, 0x8c35, 0xc9a1, 0x8c1f, 0xc9ce, 0x8c0a,
+ 0xc9fc, 0x8bf5, 0xca29, 0x8bdf, 0xca57, 0x8bca, 0xca85, 0x8bb5,
+ 0xcab2, 0x8ba0, 0xcae0, 0x8b8b, 0xcb0e, 0x8b77, 0xcb3c, 0x8b62,
+ 0xcb69, 0x8b4d, 0xcb97, 0x8b39, 0xcbc5, 0x8b24, 0xcbf3, 0x8b10,
+ 0xcc21, 0x8afb, 0xcc4f, 0x8ae7, 0xcc7d, 0x8ad3, 0xccab, 0x8abe,
+ 0xccd9, 0x8aaa, 0xcd07, 0x8a96, 0xcd35, 0x8a82, 0xcd63, 0x8a6e,
+ 0xcd92, 0x8a5a, 0xcdc0, 0x8a47, 0xcdee, 0x8a33, 0xce1c, 0x8a1f,
+ 0xce4b, 0x8a0c, 0xce79, 0x89f8, 0xcea7, 0x89e5, 0xced6, 0x89d2,
+ 0xcf04, 0x89be, 0xcf33, 0x89ab, 0xcf61, 0x8998, 0xcf90, 0x8985,
+ 0xcfbe, 0x8972, 0xcfed, 0x895f, 0xd01b, 0x894c, 0xd04a, 0x8939,
+ 0xd079, 0x8927, 0xd0a7, 0x8914, 0xd0d6, 0x8902, 0xd105, 0x88ef,
+ 0xd134, 0x88dd, 0xd162, 0x88ca, 0xd191, 0x88b8, 0xd1c0, 0x88a6,
+ 0xd1ef, 0x8894, 0xd21e, 0x8882, 0xd24d, 0x8870, 0xd27c, 0x885e,
+ 0xd2ab, 0x884c, 0xd2da, 0x883a, 0xd309, 0x8828, 0xd338, 0x8817,
+ 0xd367, 0x8805, 0xd396, 0x87f4, 0xd3c5, 0x87e2, 0xd3f4, 0x87d1,
+ 0xd424, 0x87c0, 0xd453, 0x87af, 0xd482, 0x879d, 0xd4b1, 0x878c,
+ 0xd4e1, 0x877b, 0xd510, 0x876b, 0xd53f, 0x875a, 0xd56f, 0x8749,
+ 0xd59e, 0x8738, 0xd5ce, 0x8728, 0xd5fd, 0x8717, 0xd62d, 0x8707,
+ 0xd65c, 0x86f6, 0xd68c, 0x86e6, 0xd6bb, 0x86d6, 0xd6eb, 0x86c6,
+ 0xd71b, 0x86b6, 0xd74a, 0x86a5, 0xd77a, 0x8696, 0xd7aa, 0x8686,
+ 0xd7d9, 0x8676, 0xd809, 0x8666, 0xd839, 0x8656, 0xd869, 0x8647,
+ 0xd898, 0x8637, 0xd8c8, 0x8628, 0xd8f8, 0x8619, 0xd928, 0x8609,
+ 0xd958, 0x85fa, 0xd988, 0x85eb, 0xd9b8, 0x85dc, 0xd9e8, 0x85cd,
+ 0xda18, 0x85be, 0xda48, 0x85af, 0xda78, 0x85a0, 0xdaa8, 0x8592,
+ 0xdad8, 0x8583, 0xdb08, 0x8574, 0xdb38, 0x8566, 0xdb68, 0x8558,
+ 0xdb99, 0x8549, 0xdbc9, 0x853b, 0xdbf9, 0x852d, 0xdc29, 0x851f,
+ 0xdc59, 0x8511, 0xdc8a, 0x8503, 0xdcba, 0x84f5, 0xdcea, 0x84e7,
+ 0xdd1b, 0x84d9, 0xdd4b, 0x84cc, 0xdd7c, 0x84be, 0xddac, 0x84b0,
+ 0xdddc, 0x84a3, 0xde0d, 0x8496, 0xde3d, 0x8488, 0xde6e, 0x847b,
+ 0xde9e, 0x846e, 0xdecf, 0x8461, 0xdeff, 0x8454, 0xdf30, 0x8447,
+ 0xdf61, 0x843a, 0xdf91, 0x842d, 0xdfc2, 0x8421, 0xdff2, 0x8414,
+ 0xe023, 0x8407, 0xe054, 0x83fb, 0xe085, 0x83ef, 0xe0b5, 0x83e2,
+ 0xe0e6, 0x83d6, 0xe117, 0x83ca, 0xe148, 0x83be, 0xe178, 0x83b2,
+ 0xe1a9, 0x83a6, 0xe1da, 0x839a, 0xe20b, 0x838e, 0xe23c, 0x8382,
+ 0xe26d, 0x8377, 0xe29e, 0x836b, 0xe2cf, 0x8360, 0xe2ff, 0x8354,
+ 0xe330, 0x8349, 0xe361, 0x833e, 0xe392, 0x8332, 0xe3c3, 0x8327,
+ 0xe3f4, 0x831c, 0xe426, 0x8311, 0xe457, 0x8306, 0xe488, 0x82fb,
+ 0xe4b9, 0x82f1, 0xe4ea, 0x82e6, 0xe51b, 0x82db, 0xe54c, 0x82d1,
+ 0xe57d, 0x82c6, 0xe5af, 0x82bc, 0xe5e0, 0x82b2, 0xe611, 0x82a8,
+ 0xe642, 0x829d, 0xe673, 0x8293, 0xe6a5, 0x8289, 0xe6d6, 0x827f,
+ 0xe707, 0x8276, 0xe739, 0x826c, 0xe76a, 0x8262, 0xe79b, 0x8259,
+ 0xe7cd, 0x824f, 0xe7fe, 0x8246, 0xe82f, 0x823c, 0xe861, 0x8233,
+ 0xe892, 0x822a, 0xe8c4, 0x8220, 0xe8f5, 0x8217, 0xe926, 0x820e,
+ 0xe958, 0x8205, 0xe989, 0x81fd, 0xe9bb, 0x81f4, 0xe9ec, 0x81eb,
+ 0xea1e, 0x81e2, 0xea4f, 0x81da, 0xea81, 0x81d1, 0xeab3, 0x81c9,
+ 0xeae4, 0x81c1, 0xeb16, 0x81b8, 0xeb47, 0x81b0, 0xeb79, 0x81a8,
+ 0xebab, 0x81a0, 0xebdc, 0x8198, 0xec0e, 0x8190, 0xec3f, 0x8188,
+ 0xec71, 0x8181, 0xeca3, 0x8179, 0xecd5, 0x8172, 0xed06, 0x816a,
+ 0xed38, 0x8163, 0xed6a, 0x815b, 0xed9b, 0x8154, 0xedcd, 0x814d,
+ 0xedff, 0x8146, 0xee31, 0x813f, 0xee62, 0x8138, 0xee94, 0x8131,
+ 0xeec6, 0x812a, 0xeef8, 0x8123, 0xef2a, 0x811d, 0xef5c, 0x8116,
+ 0xef8d, 0x8110, 0xefbf, 0x8109, 0xeff1, 0x8103, 0xf023, 0x80fd,
+ 0xf055, 0x80f6, 0xf087, 0x80f0, 0xf0b9, 0x80ea, 0xf0eb, 0x80e4,
+ 0xf11c, 0x80de, 0xf14e, 0x80d9, 0xf180, 0x80d3, 0xf1b2, 0x80cd,
+ 0xf1e4, 0x80c8, 0xf216, 0x80c2, 0xf248, 0x80bd, 0xf27a, 0x80b7,
+ 0xf2ac, 0x80b2, 0xf2de, 0x80ad, 0xf310, 0x80a8, 0xf342, 0x80a3,
+ 0xf374, 0x809e, 0xf3a6, 0x8099, 0xf3d8, 0x8094, 0xf40a, 0x808f,
+ 0xf43c, 0x808b, 0xf46e, 0x8086, 0xf4a0, 0x8082, 0xf4d3, 0x807d,
+ 0xf505, 0x8079, 0xf537, 0x8075, 0xf569, 0x8070, 0xf59b, 0x806c,
+ 0xf5cd, 0x8068, 0xf5ff, 0x8064, 0xf631, 0x8060, 0xf663, 0x805d,
+ 0xf695, 0x8059, 0xf6c8, 0x8055, 0xf6fa, 0x8052, 0xf72c, 0x804e,
+ 0xf75e, 0x804b, 0xf790, 0x8047, 0xf7c2, 0x8044, 0xf7f4, 0x8041,
+ 0xf827, 0x803e, 0xf859, 0x803b, 0xf88b, 0x8038, 0xf8bd, 0x8035,
+ 0xf8ef, 0x8032, 0xf922, 0x802f, 0xf954, 0x802d, 0xf986, 0x802a,
+ 0xf9b8, 0x8027, 0xf9ea, 0x8025, 0xfa1d, 0x8023, 0xfa4f, 0x8020,
+ 0xfa81, 0x801e, 0xfab3, 0x801c, 0xfae5, 0x801a, 0xfb18, 0x8018,
+ 0xfb4a, 0x8016, 0xfb7c, 0x8014, 0xfbae, 0x8013, 0xfbe1, 0x8011,
+ 0xfc13, 0x800f, 0xfc45, 0x800e, 0xfc77, 0x800c, 0xfcaa, 0x800b,
+ 0xfcdc, 0x800a, 0xfd0e, 0x8009, 0xfd40, 0x8008, 0xfd73, 0x8007,
+ 0xfda5, 0x8006, 0xfdd7, 0x8005, 0xfe09, 0x8004, 0xfe3c, 0x8003,
+ 0xfe6e, 0x8002, 0xfea0, 0x8002, 0xfed2, 0x8001, 0xff05, 0x8001,
+ 0xff37, 0x8001, 0xff69, 0x8000, 0xff9b, 0x8000, 0xffce, 0x8000,
+};
+
+/**
+* @} end of CFFT_CIFFT group
+*/
+
+/*
+* @brief Q15 table for reciprocal
+*/
+const q15_t ALIGN4 armRecipTableQ15[64] = {
+ 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+ 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+ 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+ 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+ 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+ 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+ 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+ 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+ 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+ 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+ 0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*
+* @brief Q31 table for reciprocal
+*/
+const q31_t armRecipTableQ31[64] = {
+ 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+ 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+ 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+ 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+ 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+ 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+ 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+ 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+ 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+ 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+ 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
+
+const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] =
+{
+ //8x2, size 20
+ 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
+};
+
+const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] =
+{
+ //8x4, size 48
+ 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
+ 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
+ 152,224, 176,208, 184,232, 216,240, 200,224, 232,240
+};
+
+const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] =
+{
+ //radix 8, size 56
+ 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200,
+ 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400,
+ 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480,
+ 368,424, 376,488, 440,496
+};
+
+const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] =
+{
+ //8x2, size 208
+ 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768,
+ 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520,
+ 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776,
+ 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320,
+ 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400,
+ 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584,
+ 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600,
+ 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608,
+ 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864,
+ 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808,
+ 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832,
+ 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008,
+ 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
+};
+
+const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] =
+{
+ //8x4, size 440
+ 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640,
+ 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768,
+ 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384,
+ 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984,
+ 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608,
+ 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736,
+ 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864,
+ 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992,
+ 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104,
+ 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720,
+ 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160,
+ 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936,
+ 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048,
+ 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808,
+ 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544,
+ 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880,
+ 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496,
+ 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120,
+ 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552,
+ 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824,
+ 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672,
+ 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016,
+ 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640,
+ 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432,
+ 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936,
+ 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960,
+ 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648,
+ 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936,
+ 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928,
+ 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840,
+ 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888,
+ 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
+ 1960,1968, 2008,2032, 1992,2016, 2024,2032
+};
+
+const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] =
+{
+ //radix 8, size 448
+ 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576,
+ 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152,
+ 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216,
+ 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280,
+ 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344,
+ 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408,
+ 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472,
+ 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544,
+ 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120,
+ 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696,
+ 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272,
+ 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848,
+ 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416,
+ 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992,
+ 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576,
+ 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152,
+ 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728,
+ 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808,
+ 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384,
+ 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960,
+ 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536,
+ 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136,
+ 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224,
+ 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328,
+ 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416,
+ 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520,
+ 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616,
+ 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744,
+ 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872,
+ 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000,
+ 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176,
+ 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368,
+ 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560,
+ 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888,
+ 3448,3952, 3512,4016, 3576,4080
+};
+
+const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] =
+{
+ //8x2, size 1800
+ 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048,
+ 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048,
+ 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696,
+ 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648,
+ 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248,
+ 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200,
+ 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800,
+ 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752,
+ 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352,
+ 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304,
+ 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936,
+ 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856,
+ 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488,
+ 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408,
+ 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040,
+ 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960,
+ 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592,
+ 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096,
+ 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544,
+ 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080,
+ 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400,
+ 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120,
+ 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656,
+ 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168,
+ 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696,
+ 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208,
+ 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736,
+ 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272,
+ 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480,
+ 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312,
+ 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848,
+ 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280,
+ 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888,
+ 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288,
+ 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928,
+ 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464,
+ 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592,
+ 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504,
+ 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040,
+ 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136,
+ 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088,
+ 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816,
+ 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576,
+ 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664,
+ 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264,
+ 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800,
+ 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304,
+ 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840,
+ 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376,
+ 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392,
+ 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344,
+ 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944,
+ 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480,
+ 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016,
+ 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032,
+ 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984,
+ 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584,
+ 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632,
+ 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632,
+ 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168,
+ 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704,
+ 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208,
+ 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744,
+ 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248,
+ 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784,
+ 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320,
+ 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824,
+ 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360,
+ 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896,
+ 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400,
+ 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936,
+ 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440,
+ 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976,
+ 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512,
+ 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016,
+ 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552,
+ 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088,
+ 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592,
+ 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128,
+ 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160,
+ 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176,
+ 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712,
+ 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216,
+ 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752,
+ 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416,
+ 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304,
+ 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624,
+ 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296,
+ 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680,
+ 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208,
+ 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400,
+ 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808,
+ 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688,
+ 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976,
+ 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160,
+ 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344,
+ 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728,
+ 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736,
+ 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928,
+ 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872,
+ 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672,
+ 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208,
+ 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456,
+ 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248,
+ 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784,
+ 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448,
+ 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824,
+ 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240,
+ 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504,
+ 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168,
+ 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264,
+ 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456,
+ 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552,
+ 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312,
+ 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576,
+ 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248,
+ 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504,
+ 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360,
+ 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624,
+ 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384,
+ 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264,
+ 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664,
+ 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520,
+ 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280,
+ 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536,
+ 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048,
+ 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752,
+ 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992,
+ 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280,
+ 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856,
+ 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024,
+ 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624,
+ 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104,
+ 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664,
+ 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280,
+ 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688,
+ 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952,
+ 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456,
+ 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864,
+ 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784,
+ 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048,
+ 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728,
+ 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096,
+ 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112,
+ 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984,
+ 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160,
+ 8112,8136, 8120,8168, 8136,8160, 8152,8176
+};
+
+const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] =
+{
+ //8x2, size 3808
+ 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024,
+ 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824,
+ 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752,
+ 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680,
+ 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576,
+ 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376,
+ 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304,
+ 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232,
+ 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048,
+ 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928,
+ 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856,
+ 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784,
+ 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712,
+ 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480,
+ 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408,
+ 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336,
+ 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264,
+ 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064,
+ 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960,
+ 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792,
+ 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496,
+ 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328,
+ 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032,
+ 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928,
+ 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856,
+ 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560,
+ 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392,
+ 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096,
+ 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240,
+ 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600,
+ 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432,
+ 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136,
+ 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968,
+ 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640,
+ 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392,
+ 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176,
+ 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008,
+ 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712,
+ 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096,
+ 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712,
+ 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480,
+ 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248,
+ 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080,
+ 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784,
+ 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248,
+ 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288,
+ 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128,
+ 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824,
+ 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656,
+ 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328,
+ 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400,
+ 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864,
+ 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280,
+ 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400,
+ 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168,
+ 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904,
+ 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552,
+ 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440,
+ 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272,
+ 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976,
+ 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288,
+ 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480,
+ 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168,
+ 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016,
+ 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848,
+ 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520,
+ 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440,
+ 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056,
+ 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320,
+ 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592,
+ 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208,
+ 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096,
+ 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592,
+ 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632,
+ 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472,
+ 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168,
+ 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360,
+ 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672,
+ 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240,
+ 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208,
+ 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624,
+ 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208,
+ 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448,
+ 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744,
+ 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328,
+ 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280,
+ 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216,
+ 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784,
+ 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600,
+ 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320,
+ 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480,
+ 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856,
+ 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368,
+ 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360,
+ 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248,
+ 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896,
+ 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632,
+ 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400,
+ 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520,
+ 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936,
+ 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400,
+ 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472,
+ 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256,
+ 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976,
+ 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640,
+ 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512,
+ 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520,
+ 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048,
+ 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408,
+ 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552,
+ 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288,
+ 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088,
+ 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672,
+ 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592,
+ 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560,
+ 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128,
+ 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440,
+ 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664,
+ 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328,
+ 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168,
+ 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712,
+ 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704,
+ 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592,
+ 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240,
+ 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416,
+ 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240,
+ 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296,
+ 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776,
+ 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680,
+ 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280,
+ 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568,
+ 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816,
+ 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448,
+ 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352,
+ 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336,
+ 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856,
+ 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720,
+ 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392,
+ 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600,
+ 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928,
+ 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488,
+ 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432,
+ 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368,
+ 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968,
+ 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752,
+ 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472,
+ 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608,
+ 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008,
+ 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488,
+ 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544,
+ 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376,
+ 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048,
+ 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760,
+ 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584,
+ 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640,
+ 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120,
+ 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528,
+ 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624,
+ 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408,
+ 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160,
+ 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792,
+ 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664,
+ 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680,
+ 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200,
+ 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560,
+ 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736,
+ 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320,
+ 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448,
+ 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760,
+ 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464,
+ 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392,
+ 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576,
+ 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896,
+ 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688,
+ 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432,
+ 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736,
+ 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968,
+ 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376,
+ 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472,
+ 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424,
+ 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008,
+ 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536,
+ 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512,
+ 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736,
+ 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048,
+ 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728,
+ 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584,
+ 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248,
+ 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408,
+ 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112,
+ 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040,
+ 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616,
+ 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640,
+ 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664,
+ 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688,
+ 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616,
+ 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312,
+ 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336,
+ 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392,
+ 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656,
+ 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408,
+ 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192,
+ 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584,
+ 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760,
+ 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208,
+ 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816,
+ 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664,
+ 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816,
+ 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328,
+ 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296,
+ 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400,
+ 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480,
+ 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304,
+ 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912,
+ 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296,
+ 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360,
+ 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464,
+ 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440,
+ 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344,
+ 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800,
+ 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464,
+ 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968,
+ 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368,
+ 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440,
+ 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488,
+ 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528,
+ 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400,
+ 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440,
+ 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552,
+ 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056,
+ 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424,
+ 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760,
+ 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008,
+ 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408,
+ 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648,
+ 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120,
+ 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440,
+ 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656,
+ 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552,
+ 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160,
+ 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720,
+ 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760,
+ 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672,
+ 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624,
+ 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728,
+ 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736,
+ 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608,
+ 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512,
+ 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760,
+ 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296,
+ 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664,
+ 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712,
+ 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816,
+ 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824,
+ 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696,
+ 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832,
+ 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544,
+ 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584,
+ 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496,
+ 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688,
+ 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920,
+ 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344,
+ 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576,
+ 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400,
+ 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448,
+ 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696,
+ 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816,
+ 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344,
+ 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976,
+ 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416,
+ 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496,
+ 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488,
+ 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536,
+ 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592,
+ 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736,
+ 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664,
+ 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064,
+ 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464,
+ 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816,
+ 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768,
+ 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576,
+ 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592,
+ 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536,
+ 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664,
+ 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616,
+ 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704,
+ 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728,
+ 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488,
+ 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384,
+ 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560,
+ 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392,
+ 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528,
+ 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464,
+ 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304,
+ 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632,
+ 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808,
+ 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704,
+ 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832,
+ 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712,
+ 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848,
+ 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600,
+ 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640,
+ 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728,
+ 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,
+ 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384,
+ 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616,
+ 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656,
+ 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504,
+ 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528,
+ 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776,
+ 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880,
+ 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024,
+ 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232,
+ 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024,
+ 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544,
+ 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872,
+ 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016,
+ 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160,
+ 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304,
+ 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008,
+ 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152,
+ 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296,
+ 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632,
+ 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768,
+ 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760,
+ 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184,
+ 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856,
+ 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000,
+ 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160,
+ 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264,
+ 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048,
+ 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184,
+ 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264,
+ 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208,
+ 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352,
+ 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
+ 16328,16352, 16360,16368
+};
+
+const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] =
+{
+ //radix 8, size 4032
+ 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512,
+ 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184,
+ 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600,
+ 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016,
+ 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432,
+ 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848,
+ 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264,
+ 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680,
+ 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160,
+ 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672,
+ 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088,
+ 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760,
+ 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176,
+ 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592,
+ 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008,
+ 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424,
+ 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840,
+ 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224,
+ 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800,
+ 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216,
+ 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632,
+ 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952,
+ 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272,
+ 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848,
+ 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168,
+ 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488,
+ 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808,
+ 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384,
+ 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768,
+ 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184,
+ 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600,
+ 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016,
+ 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336,
+ 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912,
+ 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232,
+ 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552,
+ 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872,
+ 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448,
+ 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832,
+ 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248,
+ 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664,
+ 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080,
+ 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496,
+ 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816,
+ 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392,
+ 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712,
+ 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032,
+ 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416,
+ 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992,
+ 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408,
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+ 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696,
+ 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304,
+ 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040,
+ 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648,
+ 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256,
+ 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152,
+ 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856,
+ 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592,
+ 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200,
+ 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808,
+ 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416,
+ 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312,
+ 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240,
+ 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848,
+ 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456,
+ 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192,
+ 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864,
+ 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792,
+ 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496,
+ 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328,
+ 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936,
+ 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544,
+ 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440,
+ 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368,
+ 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072,
+ 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904,
+ 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512,
+ 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408,
+ 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112,
+ 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040,
+ 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968,
+ 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576,
+ 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472,
+ 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176,
+ 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104,
+ 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032,
+ 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736,
+ 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224,
+ 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152,
+ 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080,
+ 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784,
+ 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776,
+ 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800,
+ 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728,
+ 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656,
+ 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360,
+ 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768,
+ 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696,
+ 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400,
+ 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328,
+ 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416,
+ 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760,
+ 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464,
+ 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392,
+ 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480,
+ 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920,
+ 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848,
+ 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552,
+ 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960,
+ 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080,
+ 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104,
+ 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096,
+ 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536,
+ 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656,
+ 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680,
+ 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088,
+ 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208,
+ 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648,
+ 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648,
+ 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768,
+ 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208,
+ 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808,
+ 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248,
+ 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368,
+ 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384,
+ 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824,
+ 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424,
+ 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376,
+ 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496,
+ 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024,
+ 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464,
+ 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576,
+ 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528,
+ 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640,
+ 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688,
+ 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216,
+ 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752,
+ 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312,
+ 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864,
+ 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928,
+ 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504,
+ 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632,
+ 32248,32696
+};
+
+
+/**
+* \par
+* Example code for Floating-point RFFT Twiddle factors Generation:
+* \par
+* <pre>TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' </pre>
+* \par
+* Real and Imag values are in interleaved fashion
+*/
+const float32_t twiddleCoef_rfft_32[32] = {
+0.0f , 1.0f ,
+0.195090322f , 0.98078528f ,
+0.382683432f , 0.923879533f ,
+0.555570233f , 0.831469612f ,
+0.707106781f , 0.707106781f ,
+0.831469612f , 0.555570233f ,
+0.923879533f , 0.382683432f ,
+0.98078528f , 0.195090322f ,
+1.0f , 0.0f ,
+0.98078528f , -0.195090322f ,
+0.923879533f , -0.382683432f ,
+0.831469612f , -0.555570233f ,
+0.707106781f , -0.707106781f ,
+0.555570233f , -0.831469612f ,
+0.382683432f , -0.923879533f ,
+0.195090322f , -0.98078528f
+};
+
+const float32_t twiddleCoef_rfft_64[64] = {
+0.0f, 1.0f,
+0.098017140329561f, 0.995184726672197f,
+0.195090322016128f, 0.98078528040323f,
+0.290284677254462f, 0.956940335732209f,
+0.38268343236509f, 0.923879532511287f,
+0.471396736825998f, 0.881921264348355f,
+0.555570233019602f, 0.831469612302545f,
+0.634393284163645f, 0.773010453362737f,
+0.707106781186547f, 0.707106781186548f,
+0.773010453362737f, 0.634393284163645f,
+0.831469612302545f, 0.555570233019602f,
+0.881921264348355f, 0.471396736825998f,
+0.923879532511287f, 0.38268343236509f,
+0.956940335732209f, 0.290284677254462f,
+0.98078528040323f, 0.195090322016128f,
+0.995184726672197f, 0.098017140329561f,
+1.0f, 0.0f,
+0.995184726672197f, -0.098017140329561f,
+0.98078528040323f, -0.195090322016128f,
+0.956940335732209f, -0.290284677254462f,
+0.923879532511287f, -0.38268343236509f,
+0.881921264348355f, -0.471396736825998f,
+0.831469612302545f, -0.555570233019602f,
+0.773010453362737f, -0.634393284163645f,
+0.707106781186548f, -0.707106781186547f,
+0.634393284163645f, -0.773010453362737f,
+0.555570233019602f, -0.831469612302545f,
+0.471396736825998f, -0.881921264348355f,
+0.38268343236509f, -0.923879532511287f,
+0.290284677254462f, -0.956940335732209f,
+0.195090322016129f, -0.98078528040323f,
+0.098017140329561f, -0.995184726672197f
+};
+
+const float32_t twiddleCoef_rfft_128[128] = {
+ 0.000000000f, 1.000000000f,
+ 0.049067674f, 0.998795456f,
+ 0.098017140f, 0.995184727f,
+ 0.146730474f, 0.989176510f,
+ 0.195090322f, 0.980785280f,
+ 0.242980180f, 0.970031253f,
+ 0.290284677f, 0.956940336f,
+ 0.336889853f, 0.941544065f,
+ 0.382683432f, 0.923879533f,
+ 0.427555093f, 0.903989293f,
+ 0.471396737f, 0.881921264f,
+ 0.514102744f, 0.857728610f,
+ 0.555570233f, 0.831469612f,
+ 0.595699304f, 0.803207531f,
+ 0.634393284f, 0.773010453f,
+ 0.671558955f, 0.740951125f,
+ 0.707106781f, 0.707106781f,
+ 0.740951125f, 0.671558955f,
+ 0.773010453f, 0.634393284f,
+ 0.803207531f, 0.595699304f,
+ 0.831469612f, 0.555570233f,
+ 0.857728610f, 0.514102744f,
+ 0.881921264f, 0.471396737f,
+ 0.903989293f, 0.427555093f,
+ 0.923879533f, 0.382683432f,
+ 0.941544065f, 0.336889853f,
+ 0.956940336f, 0.290284677f,
+ 0.970031253f, 0.242980180f,
+ 0.980785280f, 0.195090322f,
+ 0.989176510f, 0.146730474f,
+ 0.995184727f, 0.098017140f,
+ 0.998795456f, 0.049067674f,
+ 1.000000000f, 0.000000000f,
+ 0.998795456f, -0.049067674f,
+ 0.995184727f, -0.098017140f,
+ 0.989176510f, -0.146730474f,
+ 0.980785280f, -0.195090322f,
+ 0.970031253f, -0.242980180f,
+ 0.956940336f, -0.290284677f,
+ 0.941544065f, -0.336889853f,
+ 0.923879533f, -0.382683432f,
+ 0.903989293f, -0.427555093f,
+ 0.881921264f, -0.471396737f,
+ 0.857728610f, -0.514102744f,
+ 0.831469612f, -0.555570233f,
+ 0.803207531f, -0.595699304f,
+ 0.773010453f, -0.634393284f,
+ 0.740951125f, -0.671558955f,
+ 0.707106781f, -0.707106781f,
+ 0.671558955f, -0.740951125f,
+ 0.634393284f, -0.773010453f,
+ 0.595699304f, -0.803207531f,
+ 0.555570233f, -0.831469612f,
+ 0.514102744f, -0.857728610f,
+ 0.471396737f, -0.881921264f,
+ 0.427555093f, -0.903989293f,
+ 0.382683432f, -0.923879533f,
+ 0.336889853f, -0.941544065f,
+ 0.290284677f, -0.956940336f,
+ 0.242980180f, -0.970031253f,
+ 0.195090322f, -0.980785280f,
+ 0.146730474f, -0.989176510f,
+ 0.098017140f, -0.995184727f,
+ 0.049067674f, -0.998795456f
+};
+
+const float32_t twiddleCoef_rfft_256[256] = {
+ 0.000000000f, 1.000000000f,
+ 0.024541229f, 0.999698819f,
+ 0.049067674f, 0.998795456f,
+ 0.073564564f, 0.997290457f,
+ 0.098017140f, 0.995184727f,
+ 0.122410675f, 0.992479535f,
+ 0.146730474f, 0.989176510f,
+ 0.170961889f, 0.985277642f,
+ 0.195090322f, 0.980785280f,
+ 0.219101240f, 0.975702130f,
+ 0.242980180f, 0.970031253f,
+ 0.266712757f, 0.963776066f,
+ 0.290284677f, 0.956940336f,
+ 0.313681740f, 0.949528181f,
+ 0.336889853f, 0.941544065f,
+ 0.359895037f, 0.932992799f,
+ 0.382683432f, 0.923879533f,
+ 0.405241314f, 0.914209756f,
+ 0.427555093f, 0.903989293f,
+ 0.449611330f, 0.893224301f,
+ 0.471396737f, 0.881921264f,
+ 0.492898192f, 0.870086991f,
+ 0.514102744f, 0.857728610f,
+ 0.534997620f, 0.844853565f,
+ 0.555570233f, 0.831469612f,
+ 0.575808191f, 0.817584813f,
+ 0.595699304f, 0.803207531f,
+ 0.615231591f, 0.788346428f,
+ 0.634393284f, 0.773010453f,
+ 0.653172843f, 0.757208847f,
+ 0.671558955f, 0.740951125f,
+ 0.689540545f, 0.724247083f,
+ 0.707106781f, 0.707106781f,
+ 0.724247083f, 0.689540545f,
+ 0.740951125f, 0.671558955f,
+ 0.757208847f, 0.653172843f,
+ 0.773010453f, 0.634393284f,
+ 0.788346428f, 0.615231591f,
+ 0.803207531f, 0.595699304f,
+ 0.817584813f, 0.575808191f,
+ 0.831469612f, 0.555570233f,
+ 0.844853565f, 0.534997620f,
+ 0.857728610f, 0.514102744f,
+ 0.870086991f, 0.492898192f,
+ 0.881921264f, 0.471396737f,
+ 0.893224301f, 0.449611330f,
+ 0.903989293f, 0.427555093f,
+ 0.914209756f, 0.405241314f,
+ 0.923879533f, 0.382683432f,
+ 0.932992799f, 0.359895037f,
+ 0.941544065f, 0.336889853f,
+ 0.949528181f, 0.313681740f,
+ 0.956940336f, 0.290284677f,
+ 0.963776066f, 0.266712757f,
+ 0.970031253f, 0.242980180f,
+ 0.975702130f, 0.219101240f,
+ 0.980785280f, 0.195090322f,
+ 0.985277642f, 0.170961889f,
+ 0.989176510f, 0.146730474f,
+ 0.992479535f, 0.122410675f,
+ 0.995184727f, 0.098017140f,
+ 0.997290457f, 0.073564564f,
+ 0.998795456f, 0.049067674f,
+ 0.999698819f, 0.024541229f,
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, -0.024541229f,
+ 0.998795456f, -0.049067674f,
+ 0.997290457f, -0.073564564f,
+ 0.995184727f, -0.098017140f,
+ 0.992479535f, -0.122410675f,
+ 0.989176510f, -0.146730474f,
+ 0.985277642f, -0.170961889f,
+ 0.980785280f, -0.195090322f,
+ 0.975702130f, -0.219101240f,
+ 0.970031253f, -0.242980180f,
+ 0.963776066f, -0.266712757f,
+ 0.956940336f, -0.290284677f,
+ 0.949528181f, -0.313681740f,
+ 0.941544065f, -0.336889853f,
+ 0.932992799f, -0.359895037f,
+ 0.923879533f, -0.382683432f,
+ 0.914209756f, -0.405241314f,
+ 0.903989293f, -0.427555093f,
+ 0.893224301f, -0.449611330f,
+ 0.881921264f, -0.471396737f,
+ 0.870086991f, -0.492898192f,
+ 0.857728610f, -0.514102744f,
+ 0.844853565f, -0.534997620f,
+ 0.831469612f, -0.555570233f,
+ 0.817584813f, -0.575808191f,
+ 0.803207531f, -0.595699304f,
+ 0.788346428f, -0.615231591f,
+ 0.773010453f, -0.634393284f,
+ 0.757208847f, -0.653172843f,
+ 0.740951125f, -0.671558955f,
+ 0.724247083f, -0.689540545f,
+ 0.707106781f, -0.707106781f,
+ 0.689540545f, -0.724247083f,
+ 0.671558955f, -0.740951125f,
+ 0.653172843f, -0.757208847f,
+ 0.634393284f, -0.773010453f,
+ 0.615231591f, -0.788346428f,
+ 0.595699304f, -0.803207531f,
+ 0.575808191f, -0.817584813f,
+ 0.555570233f, -0.831469612f,
+ 0.534997620f, -0.844853565f,
+ 0.514102744f, -0.857728610f,
+ 0.492898192f, -0.870086991f,
+ 0.471396737f, -0.881921264f,
+ 0.449611330f, -0.893224301f,
+ 0.427555093f, -0.903989293f,
+ 0.405241314f, -0.914209756f,
+ 0.382683432f, -0.923879533f,
+ 0.359895037f, -0.932992799f,
+ 0.336889853f, -0.941544065f,
+ 0.313681740f, -0.949528181f,
+ 0.290284677f, -0.956940336f,
+ 0.266712757f, -0.963776066f,
+ 0.242980180f, -0.970031253f,
+ 0.219101240f, -0.975702130f,
+ 0.195090322f, -0.980785280f,
+ 0.170961889f, -0.985277642f,
+ 0.146730474f, -0.989176510f,
+ 0.122410675f, -0.992479535f,
+ 0.098017140f, -0.995184727f,
+ 0.073564564f, -0.997290457f,
+ 0.049067674f, -0.998795456f,
+ 0.024541229f, -0.999698819f
+};
+
+const float32_t twiddleCoef_rfft_512[512] = {
+ 0.000000000f, 1.000000000f,
+ 0.012271538f, 0.999924702f,
+ 0.024541229f, 0.999698819f,
+ 0.036807223f, 0.999322385f,
+ 0.049067674f, 0.998795456f,
+ 0.061320736f, 0.998118113f,
+ 0.073564564f, 0.997290457f,
+ 0.085797312f, 0.996312612f,
+ 0.098017140f, 0.995184727f,
+ 0.110222207f, 0.993906970f,
+ 0.122410675f, 0.992479535f,
+ 0.134580709f, 0.990902635f,
+ 0.146730474f, 0.989176510f,
+ 0.158858143f, 0.987301418f,
+ 0.170961889f, 0.985277642f,
+ 0.183039888f, 0.983105487f,
+ 0.195090322f, 0.980785280f,
+ 0.207111376f, 0.978317371f,
+ 0.219101240f, 0.975702130f,
+ 0.231058108f, 0.972939952f,
+ 0.242980180f, 0.970031253f,
+ 0.254865660f, 0.966976471f,
+ 0.266712757f, 0.963776066f,
+ 0.278519689f, 0.960430519f,
+ 0.290284677f, 0.956940336f,
+ 0.302005949f, 0.953306040f,
+ 0.313681740f, 0.949528181f,
+ 0.325310292f, 0.945607325f,
+ 0.336889853f, 0.941544065f,
+ 0.348418680f, 0.937339012f,
+ 0.359895037f, 0.932992799f,
+ 0.371317194f, 0.928506080f,
+ 0.382683432f, 0.923879533f,
+ 0.393992040f, 0.919113852f,
+ 0.405241314f, 0.914209756f,
+ 0.416429560f, 0.909167983f,
+ 0.427555093f, 0.903989293f,
+ 0.438616239f, 0.898674466f,
+ 0.449611330f, 0.893224301f,
+ 0.460538711f, 0.887639620f,
+ 0.471396737f, 0.881921264f,
+ 0.482183772f, 0.876070094f,
+ 0.492898192f, 0.870086991f,
+ 0.503538384f, 0.863972856f,
+ 0.514102744f, 0.857728610f,
+ 0.524589683f, 0.851355193f,
+ 0.534997620f, 0.844853565f,
+ 0.545324988f, 0.838224706f,
+ 0.555570233f, 0.831469612f,
+ 0.565731811f, 0.824589303f,
+ 0.575808191f, 0.817584813f,
+ 0.585797857f, 0.810457198f,
+ 0.595699304f, 0.803207531f,
+ 0.605511041f, 0.795836905f,
+ 0.615231591f, 0.788346428f,
+ 0.624859488f, 0.780737229f,
+ 0.634393284f, 0.773010453f,
+ 0.643831543f, 0.765167266f,
+ 0.653172843f, 0.757208847f,
+ 0.662415778f, 0.749136395f,
+ 0.671558955f, 0.740951125f,
+ 0.680600998f, 0.732654272f,
+ 0.689540545f, 0.724247083f,
+ 0.698376249f, 0.715730825f,
+ 0.707106781f, 0.707106781f,
+ 0.715730825f, 0.698376249f,
+ 0.724247083f, 0.689540545f,
+ 0.732654272f, 0.680600998f,
+ 0.740951125f, 0.671558955f,
+ 0.749136395f, 0.662415778f,
+ 0.757208847f, 0.653172843f,
+ 0.765167266f, 0.643831543f,
+ 0.773010453f, 0.634393284f,
+ 0.780737229f, 0.624859488f,
+ 0.788346428f, 0.615231591f,
+ 0.795836905f, 0.605511041f,
+ 0.803207531f, 0.595699304f,
+ 0.810457198f, 0.585797857f,
+ 0.817584813f, 0.575808191f,
+ 0.824589303f, 0.565731811f,
+ 0.831469612f, 0.555570233f,
+ 0.838224706f, 0.545324988f,
+ 0.844853565f, 0.534997620f,
+ 0.851355193f, 0.524589683f,
+ 0.857728610f, 0.514102744f,
+ 0.863972856f, 0.503538384f,
+ 0.870086991f, 0.492898192f,
+ 0.876070094f, 0.482183772f,
+ 0.881921264f, 0.471396737f,
+ 0.887639620f, 0.460538711f,
+ 0.893224301f, 0.449611330f,
+ 0.898674466f, 0.438616239f,
+ 0.903989293f, 0.427555093f,
+ 0.909167983f, 0.416429560f,
+ 0.914209756f, 0.405241314f,
+ 0.919113852f, 0.393992040f,
+ 0.923879533f, 0.382683432f,
+ 0.928506080f, 0.371317194f,
+ 0.932992799f, 0.359895037f,
+ 0.937339012f, 0.348418680f,
+ 0.941544065f, 0.336889853f,
+ 0.945607325f, 0.325310292f,
+ 0.949528181f, 0.313681740f,
+ 0.953306040f, 0.302005949f,
+ 0.956940336f, 0.290284677f,
+ 0.960430519f, 0.278519689f,
+ 0.963776066f, 0.266712757f,
+ 0.966976471f, 0.254865660f,
+ 0.970031253f, 0.242980180f,
+ 0.972939952f, 0.231058108f,
+ 0.975702130f, 0.219101240f,
+ 0.978317371f, 0.207111376f,
+ 0.980785280f, 0.195090322f,
+ 0.983105487f, 0.183039888f,
+ 0.985277642f, 0.170961889f,
+ 0.987301418f, 0.158858143f,
+ 0.989176510f, 0.146730474f,
+ 0.990902635f, 0.134580709f,
+ 0.992479535f, 0.122410675f,
+ 0.993906970f, 0.110222207f,
+ 0.995184727f, 0.098017140f,
+ 0.996312612f, 0.085797312f,
+ 0.997290457f, 0.073564564f,
+ 0.998118113f, 0.061320736f,
+ 0.998795456f, 0.049067674f,
+ 0.999322385f, 0.036807223f,
+ 0.999698819f, 0.024541229f,
+ 0.999924702f, 0.012271538f,
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, -0.012271538f,
+ 0.999698819f, -0.024541229f,
+ 0.999322385f, -0.036807223f,
+ 0.998795456f, -0.049067674f,
+ 0.998118113f, -0.061320736f,
+ 0.997290457f, -0.073564564f,
+ 0.996312612f, -0.085797312f,
+ 0.995184727f, -0.098017140f,
+ 0.993906970f, -0.110222207f,
+ 0.992479535f, -0.122410675f,
+ 0.990902635f, -0.134580709f,
+ 0.989176510f, -0.146730474f,
+ 0.987301418f, -0.158858143f,
+ 0.985277642f, -0.170961889f,
+ 0.983105487f, -0.183039888f,
+ 0.980785280f, -0.195090322f,
+ 0.978317371f, -0.207111376f,
+ 0.975702130f, -0.219101240f,
+ 0.972939952f, -0.231058108f,
+ 0.970031253f, -0.242980180f,
+ 0.966976471f, -0.254865660f,
+ 0.963776066f, -0.266712757f,
+ 0.960430519f, -0.278519689f,
+ 0.956940336f, -0.290284677f,
+ 0.953306040f, -0.302005949f,
+ 0.949528181f, -0.313681740f,
+ 0.945607325f, -0.325310292f,
+ 0.941544065f, -0.336889853f,
+ 0.937339012f, -0.348418680f,
+ 0.932992799f, -0.359895037f,
+ 0.928506080f, -0.371317194f,
+ 0.923879533f, -0.382683432f,
+ 0.919113852f, -0.393992040f,
+ 0.914209756f, -0.405241314f,
+ 0.909167983f, -0.416429560f,
+ 0.903989293f, -0.427555093f,
+ 0.898674466f, -0.438616239f,
+ 0.893224301f, -0.449611330f,
+ 0.887639620f, -0.460538711f,
+ 0.881921264f, -0.471396737f,
+ 0.876070094f, -0.482183772f,
+ 0.870086991f, -0.492898192f,
+ 0.863972856f, -0.503538384f,
+ 0.857728610f, -0.514102744f,
+ 0.851355193f, -0.524589683f,
+ 0.844853565f, -0.534997620f,
+ 0.838224706f, -0.545324988f,
+ 0.831469612f, -0.555570233f,
+ 0.824589303f, -0.565731811f,
+ 0.817584813f, -0.575808191f,
+ 0.810457198f, -0.585797857f,
+ 0.803207531f, -0.595699304f,
+ 0.795836905f, -0.605511041f,
+ 0.788346428f, -0.615231591f,
+ 0.780737229f, -0.624859488f,
+ 0.773010453f, -0.634393284f,
+ 0.765167266f, -0.643831543f,
+ 0.757208847f, -0.653172843f,
+ 0.749136395f, -0.662415778f,
+ 0.740951125f, -0.671558955f,
+ 0.732654272f, -0.680600998f,
+ 0.724247083f, -0.689540545f,
+ 0.715730825f, -0.698376249f,
+ 0.707106781f, -0.707106781f,
+ 0.698376249f, -0.715730825f,
+ 0.689540545f, -0.724247083f,
+ 0.680600998f, -0.732654272f,
+ 0.671558955f, -0.740951125f,
+ 0.662415778f, -0.749136395f,
+ 0.653172843f, -0.757208847f,
+ 0.643831543f, -0.765167266f,
+ 0.634393284f, -0.773010453f,
+ 0.624859488f, -0.780737229f,
+ 0.615231591f, -0.788346428f,
+ 0.605511041f, -0.795836905f,
+ 0.595699304f, -0.803207531f,
+ 0.585797857f, -0.810457198f,
+ 0.575808191f, -0.817584813f,
+ 0.565731811f, -0.824589303f,
+ 0.555570233f, -0.831469612f,
+ 0.545324988f, -0.838224706f,
+ 0.534997620f, -0.844853565f,
+ 0.524589683f, -0.851355193f,
+ 0.514102744f, -0.857728610f,
+ 0.503538384f, -0.863972856f,
+ 0.492898192f, -0.870086991f,
+ 0.482183772f, -0.876070094f,
+ 0.471396737f, -0.881921264f,
+ 0.460538711f, -0.887639620f,
+ 0.449611330f, -0.893224301f,
+ 0.438616239f, -0.898674466f,
+ 0.427555093f, -0.903989293f,
+ 0.416429560f, -0.909167983f,
+ 0.405241314f, -0.914209756f,
+ 0.393992040f, -0.919113852f,
+ 0.382683432f, -0.923879533f,
+ 0.371317194f, -0.928506080f,
+ 0.359895037f, -0.932992799f,
+ 0.348418680f, -0.937339012f,
+ 0.336889853f, -0.941544065f,
+ 0.325310292f, -0.945607325f,
+ 0.313681740f, -0.949528181f,
+ 0.302005949f, -0.953306040f,
+ 0.290284677f, -0.956940336f,
+ 0.278519689f, -0.960430519f,
+ 0.266712757f, -0.963776066f,
+ 0.254865660f, -0.966976471f,
+ 0.242980180f, -0.970031253f,
+ 0.231058108f, -0.972939952f,
+ 0.219101240f, -0.975702130f,
+ 0.207111376f, -0.978317371f,
+ 0.195090322f, -0.980785280f,
+ 0.183039888f, -0.983105487f,
+ 0.170961889f, -0.985277642f,
+ 0.158858143f, -0.987301418f,
+ 0.146730474f, -0.989176510f,
+ 0.134580709f, -0.990902635f,
+ 0.122410675f, -0.992479535f,
+ 0.110222207f, -0.993906970f,
+ 0.098017140f, -0.995184727f,
+ 0.085797312f, -0.996312612f,
+ 0.073564564f, -0.997290457f,
+ 0.061320736f, -0.998118113f,
+ 0.049067674f, -0.998795456f,
+ 0.036807223f, -0.999322385f,
+ 0.024541229f, -0.999698819f,
+ 0.012271538f, -0.999924702f
+};
+
+const float32_t twiddleCoef_rfft_1024[1024] = {
+ 0.000000000f, 1.000000000f,
+ 0.006135885f, 0.999981175f,
+ 0.012271538f, 0.999924702f,
+ 0.018406730f, 0.999830582f,
+ 0.024541229f, 0.999698819f,
+ 0.030674803f, 0.999529418f,
+ 0.036807223f, 0.999322385f,
+ 0.042938257f, 0.999077728f,
+ 0.049067674f, 0.998795456f,
+ 0.055195244f, 0.998475581f,
+ 0.061320736f, 0.998118113f,
+ 0.067443920f, 0.997723067f,
+ 0.073564564f, 0.997290457f,
+ 0.079682438f, 0.996820299f,
+ 0.085797312f, 0.996312612f,
+ 0.091908956f, 0.995767414f,
+ 0.098017140f, 0.995184727f,
+ 0.104121634f, 0.994564571f,
+ 0.110222207f, 0.993906970f,
+ 0.116318631f, 0.993211949f,
+ 0.122410675f, 0.992479535f,
+ 0.128498111f, 0.991709754f,
+ 0.134580709f, 0.990902635f,
+ 0.140658239f, 0.990058210f,
+ 0.146730474f, 0.989176510f,
+ 0.152797185f, 0.988257568f,
+ 0.158858143f, 0.987301418f,
+ 0.164913120f, 0.986308097f,
+ 0.170961889f, 0.985277642f,
+ 0.177004220f, 0.984210092f,
+ 0.183039888f, 0.983105487f,
+ 0.189068664f, 0.981963869f,
+ 0.195090322f, 0.980785280f,
+ 0.201104635f, 0.979569766f,
+ 0.207111376f, 0.978317371f,
+ 0.213110320f, 0.977028143f,
+ 0.219101240f, 0.975702130f,
+ 0.225083911f, 0.974339383f,
+ 0.231058108f, 0.972939952f,
+ 0.237023606f, 0.971503891f,
+ 0.242980180f, 0.970031253f,
+ 0.248927606f, 0.968522094f,
+ 0.254865660f, 0.966976471f,
+ 0.260794118f, 0.965394442f,
+ 0.266712757f, 0.963776066f,
+ 0.272621355f, 0.962121404f,
+ 0.278519689f, 0.960430519f,
+ 0.284407537f, 0.958703475f,
+ 0.290284677f, 0.956940336f,
+ 0.296150888f, 0.955141168f,
+ 0.302005949f, 0.953306040f,
+ 0.307849640f, 0.951435021f,
+ 0.313681740f, 0.949528181f,
+ 0.319502031f, 0.947585591f,
+ 0.325310292f, 0.945607325f,
+ 0.331106306f, 0.943593458f,
+ 0.336889853f, 0.941544065f,
+ 0.342660717f, 0.939459224f,
+ 0.348418680f, 0.937339012f,
+ 0.354163525f, 0.935183510f,
+ 0.359895037f, 0.932992799f,
+ 0.365612998f, 0.930766961f,
+ 0.371317194f, 0.928506080f,
+ 0.377007410f, 0.926210242f,
+ 0.382683432f, 0.923879533f,
+ 0.388345047f, 0.921514039f,
+ 0.393992040f, 0.919113852f,
+ 0.399624200f, 0.916679060f,
+ 0.405241314f, 0.914209756f,
+ 0.410843171f, 0.911706032f,
+ 0.416429560f, 0.909167983f,
+ 0.422000271f, 0.906595705f,
+ 0.427555093f, 0.903989293f,
+ 0.433093819f, 0.901348847f,
+ 0.438616239f, 0.898674466f,
+ 0.444122145f, 0.895966250f,
+ 0.449611330f, 0.893224301f,
+ 0.455083587f, 0.890448723f,
+ 0.460538711f, 0.887639620f,
+ 0.465976496f, 0.884797098f,
+ 0.471396737f, 0.881921264f,
+ 0.476799230f, 0.879012226f,
+ 0.482183772f, 0.876070094f,
+ 0.487550160f, 0.873094978f,
+ 0.492898192f, 0.870086991f,
+ 0.498227667f, 0.867046246f,
+ 0.503538384f, 0.863972856f,
+ 0.508830143f, 0.860866939f,
+ 0.514102744f, 0.857728610f,
+ 0.519355990f, 0.854557988f,
+ 0.524589683f, 0.851355193f,
+ 0.529803625f, 0.848120345f,
+ 0.534997620f, 0.844853565f,
+ 0.540171473f, 0.841554977f,
+ 0.545324988f, 0.838224706f,
+ 0.550457973f, 0.834862875f,
+ 0.555570233f, 0.831469612f,
+ 0.560661576f, 0.828045045f,
+ 0.565731811f, 0.824589303f,
+ 0.570780746f, 0.821102515f,
+ 0.575808191f, 0.817584813f,
+ 0.580813958f, 0.814036330f,
+ 0.585797857f, 0.810457198f,
+ 0.590759702f, 0.806847554f,
+ 0.595699304f, 0.803207531f,
+ 0.600616479f, 0.799537269f,
+ 0.605511041f, 0.795836905f,
+ 0.610382806f, 0.792106577f,
+ 0.615231591f, 0.788346428f,
+ 0.620057212f, 0.784556597f,
+ 0.624859488f, 0.780737229f,
+ 0.629638239f, 0.776888466f,
+ 0.634393284f, 0.773010453f,
+ 0.639124445f, 0.769103338f,
+ 0.643831543f, 0.765167266f,
+ 0.648514401f, 0.761202385f,
+ 0.653172843f, 0.757208847f,
+ 0.657806693f, 0.753186799f,
+ 0.662415778f, 0.749136395f,
+ 0.666999922f, 0.745057785f,
+ 0.671558955f, 0.740951125f,
+ 0.676092704f, 0.736816569f,
+ 0.680600998f, 0.732654272f,
+ 0.685083668f, 0.728464390f,
+ 0.689540545f, 0.724247083f,
+ 0.693971461f, 0.720002508f,
+ 0.698376249f, 0.715730825f,
+ 0.702754744f, 0.711432196f,
+ 0.707106781f, 0.707106781f,
+ 0.711432196f, 0.702754744f,
+ 0.715730825f, 0.698376249f,
+ 0.720002508f, 0.693971461f,
+ 0.724247083f, 0.689540545f,
+ 0.728464390f, 0.685083668f,
+ 0.732654272f, 0.680600998f,
+ 0.736816569f, 0.676092704f,
+ 0.740951125f, 0.671558955f,
+ 0.745057785f, 0.666999922f,
+ 0.749136395f, 0.662415778f,
+ 0.753186799f, 0.657806693f,
+ 0.757208847f, 0.653172843f,
+ 0.761202385f, 0.648514401f,
+ 0.765167266f, 0.643831543f,
+ 0.769103338f, 0.639124445f,
+ 0.773010453f, 0.634393284f,
+ 0.776888466f, 0.629638239f,
+ 0.780737229f, 0.624859488f,
+ 0.784556597f, 0.620057212f,
+ 0.788346428f, 0.615231591f,
+ 0.792106577f, 0.610382806f,
+ 0.795836905f, 0.605511041f,
+ 0.799537269f, 0.600616479f,
+ 0.803207531f, 0.595699304f,
+ 0.806847554f, 0.590759702f,
+ 0.810457198f, 0.585797857f,
+ 0.814036330f, 0.580813958f,
+ 0.817584813f, 0.575808191f,
+ 0.821102515f, 0.570780746f,
+ 0.824589303f, 0.565731811f,
+ 0.828045045f, 0.560661576f,
+ 0.831469612f, 0.555570233f,
+ 0.834862875f, 0.550457973f,
+ 0.838224706f, 0.545324988f,
+ 0.841554977f, 0.540171473f,
+ 0.844853565f, 0.534997620f,
+ 0.848120345f, 0.529803625f,
+ 0.851355193f, 0.524589683f,
+ 0.854557988f, 0.519355990f,
+ 0.857728610f, 0.514102744f,
+ 0.860866939f, 0.508830143f,
+ 0.863972856f, 0.503538384f,
+ 0.867046246f, 0.498227667f,
+ 0.870086991f, 0.492898192f,
+ 0.873094978f, 0.487550160f,
+ 0.876070094f, 0.482183772f,
+ 0.879012226f, 0.476799230f,
+ 0.881921264f, 0.471396737f,
+ 0.884797098f, 0.465976496f,
+ 0.887639620f, 0.460538711f,
+ 0.890448723f, 0.455083587f,
+ 0.893224301f, 0.449611330f,
+ 0.895966250f, 0.444122145f,
+ 0.898674466f, 0.438616239f,
+ 0.901348847f, 0.433093819f,
+ 0.903989293f, 0.427555093f,
+ 0.906595705f, 0.422000271f,
+ 0.909167983f, 0.416429560f,
+ 0.911706032f, 0.410843171f,
+ 0.914209756f, 0.405241314f,
+ 0.916679060f, 0.399624200f,
+ 0.919113852f, 0.393992040f,
+ 0.921514039f, 0.388345047f,
+ 0.923879533f, 0.382683432f,
+ 0.926210242f, 0.377007410f,
+ 0.928506080f, 0.371317194f,
+ 0.930766961f, 0.365612998f,
+ 0.932992799f, 0.359895037f,
+ 0.935183510f, 0.354163525f,
+ 0.937339012f, 0.348418680f,
+ 0.939459224f, 0.342660717f,
+ 0.941544065f, 0.336889853f,
+ 0.943593458f, 0.331106306f,
+ 0.945607325f, 0.325310292f,
+ 0.947585591f, 0.319502031f,
+ 0.949528181f, 0.313681740f,
+ 0.951435021f, 0.307849640f,
+ 0.953306040f, 0.302005949f,
+ 0.955141168f, 0.296150888f,
+ 0.956940336f, 0.290284677f,
+ 0.958703475f, 0.284407537f,
+ 0.960430519f, 0.278519689f,
+ 0.962121404f, 0.272621355f,
+ 0.963776066f, 0.266712757f,
+ 0.965394442f, 0.260794118f,
+ 0.966976471f, 0.254865660f,
+ 0.968522094f, 0.248927606f,
+ 0.970031253f, 0.242980180f,
+ 0.971503891f, 0.237023606f,
+ 0.972939952f, 0.231058108f,
+ 0.974339383f, 0.225083911f,
+ 0.975702130f, 0.219101240f,
+ 0.977028143f, 0.213110320f,
+ 0.978317371f, 0.207111376f,
+ 0.979569766f, 0.201104635f,
+ 0.980785280f, 0.195090322f,
+ 0.981963869f, 0.189068664f,
+ 0.983105487f, 0.183039888f,
+ 0.984210092f, 0.177004220f,
+ 0.985277642f, 0.170961889f,
+ 0.986308097f, 0.164913120f,
+ 0.987301418f, 0.158858143f,
+ 0.988257568f, 0.152797185f,
+ 0.989176510f, 0.146730474f,
+ 0.990058210f, 0.140658239f,
+ 0.990902635f, 0.134580709f,
+ 0.991709754f, 0.128498111f,
+ 0.992479535f, 0.122410675f,
+ 0.993211949f, 0.116318631f,
+ 0.993906970f, 0.110222207f,
+ 0.994564571f, 0.104121634f,
+ 0.995184727f, 0.098017140f,
+ 0.995767414f, 0.091908956f,
+ 0.996312612f, 0.085797312f,
+ 0.996820299f, 0.079682438f,
+ 0.997290457f, 0.073564564f,
+ 0.997723067f, 0.067443920f,
+ 0.998118113f, 0.061320736f,
+ 0.998475581f, 0.055195244f,
+ 0.998795456f, 0.049067674f,
+ 0.999077728f, 0.042938257f,
+ 0.999322385f, 0.036807223f,
+ 0.999529418f, 0.030674803f,
+ 0.999698819f, 0.024541229f,
+ 0.999830582f, 0.018406730f,
+ 0.999924702f, 0.012271538f,
+ 0.999981175f, 0.006135885f,
+ 1.000000000f, 0.000000000f,
+ 0.999981175f, -0.006135885f,
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+ 0.997290457f, -0.073564564f,
+ 0.996820299f, -0.079682438f,
+ 0.996312612f, -0.085797312f,
+ 0.995767414f, -0.091908956f,
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+ 0.990902635f, -0.134580709f,
+ 0.990058210f, -0.140658239f,
+ 0.989176510f, -0.146730474f,
+ 0.988257568f, -0.152797185f,
+ 0.987301418f, -0.158858143f,
+ 0.986308097f, -0.164913120f,
+ 0.985277642f, -0.170961889f,
+ 0.984210092f, -0.177004220f,
+ 0.983105487f, -0.183039888f,
+ 0.981963869f, -0.189068664f,
+ 0.980785280f, -0.195090322f,
+ 0.979569766f, -0.201104635f,
+ 0.978317371f, -0.207111376f,
+ 0.977028143f, -0.213110320f,
+ 0.975702130f, -0.219101240f,
+ 0.974339383f, -0.225083911f,
+ 0.972939952f, -0.231058108f,
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+ 0.955141168f, -0.296150888f,
+ 0.953306040f, -0.302005949f,
+ 0.951435021f, -0.307849640f,
+ 0.949528181f, -0.313681740f,
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+ 0.911706032f, -0.410843171f,
+ 0.909167983f, -0.416429560f,
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+ 0.841554977f, -0.540171473f,
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+ 0.831469612f, -0.555570233f,
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+ 0.821102515f, -0.570780746f,
+ 0.817584813f, -0.575808191f,
+ 0.814036330f, -0.580813958f,
+ 0.810457198f, -0.585797857f,
+ 0.806847554f, -0.590759702f,
+ 0.803207531f, -0.595699304f,
+ 0.799537269f, -0.600616479f,
+ 0.795836905f, -0.605511041f,
+ 0.792106577f, -0.610382806f,
+ 0.788346428f, -0.615231591f,
+ 0.784556597f, -0.620057212f,
+ 0.780737229f, -0.624859488f,
+ 0.776888466f, -0.629638239f,
+ 0.773010453f, -0.634393284f,
+ 0.769103338f, -0.639124445f,
+ 0.765167266f, -0.643831543f,
+ 0.761202385f, -0.648514401f,
+ 0.757208847f, -0.653172843f,
+ 0.753186799f, -0.657806693f,
+ 0.749136395f, -0.662415778f,
+ 0.745057785f, -0.666999922f,
+ 0.740951125f, -0.671558955f,
+ 0.736816569f, -0.676092704f,
+ 0.732654272f, -0.680600998f,
+ 0.728464390f, -0.685083668f,
+ 0.724247083f, -0.689540545f,
+ 0.720002508f, -0.693971461f,
+ 0.715730825f, -0.698376249f,
+ 0.711432196f, -0.702754744f,
+ 0.707106781f, -0.707106781f,
+ 0.702754744f, -0.711432196f,
+ 0.698376249f, -0.715730825f,
+ 0.693971461f, -0.720002508f,
+ 0.689540545f, -0.724247083f,
+ 0.685083668f, -0.728464390f,
+ 0.680600998f, -0.732654272f,
+ 0.676092704f, -0.736816569f,
+ 0.671558955f, -0.740951125f,
+ 0.666999922f, -0.745057785f,
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+ 0.657806693f, -0.753186799f,
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+ 0.648514401f, -0.761202385f,
+ 0.643831543f, -0.765167266f,
+ 0.639124445f, -0.769103338f,
+ 0.634393284f, -0.773010453f,
+ 0.629638239f, -0.776888466f,
+ 0.624859488f, -0.780737229f,
+ 0.620057212f, -0.784556597f,
+ 0.615231591f, -0.788346428f,
+ 0.610382806f, -0.792106577f,
+ 0.605511041f, -0.795836905f,
+ 0.600616479f, -0.799537269f,
+ 0.595699304f, -0.803207531f,
+ 0.590759702f, -0.806847554f,
+ 0.585797857f, -0.810457198f,
+ 0.580813958f, -0.814036330f,
+ 0.575808191f, -0.817584813f,
+ 0.570780746f, -0.821102515f,
+ 0.565731811f, -0.824589303f,
+ 0.560661576f, -0.828045045f,
+ 0.555570233f, -0.831469612f,
+ 0.550457973f, -0.834862875f,
+ 0.545324988f, -0.838224706f,
+ 0.540171473f, -0.841554977f,
+ 0.534997620f, -0.844853565f,
+ 0.529803625f, -0.848120345f,
+ 0.524589683f, -0.851355193f,
+ 0.519355990f, -0.854557988f,
+ 0.514102744f, -0.857728610f,
+ 0.508830143f, -0.860866939f,
+ 0.503538384f, -0.863972856f,
+ 0.498227667f, -0.867046246f,
+ 0.492898192f, -0.870086991f,
+ 0.487550160f, -0.873094978f,
+ 0.482183772f, -0.876070094f,
+ 0.476799230f, -0.879012226f,
+ 0.471396737f, -0.881921264f,
+ 0.465976496f, -0.884797098f,
+ 0.460538711f, -0.887639620f,
+ 0.455083587f, -0.890448723f,
+ 0.449611330f, -0.893224301f,
+ 0.444122145f, -0.895966250f,
+ 0.438616239f, -0.898674466f,
+ 0.433093819f, -0.901348847f,
+ 0.427555093f, -0.903989293f,
+ 0.422000271f, -0.906595705f,
+ 0.416429560f, -0.909167983f,
+ 0.410843171f, -0.911706032f,
+ 0.405241314f, -0.914209756f,
+ 0.399624200f, -0.916679060f,
+ 0.393992040f, -0.919113852f,
+ 0.388345047f, -0.921514039f,
+ 0.382683432f, -0.923879533f,
+ 0.377007410f, -0.926210242f,
+ 0.371317194f, -0.928506080f,
+ 0.365612998f, -0.930766961f,
+ 0.359895037f, -0.932992799f,
+ 0.354163525f, -0.935183510f,
+ 0.348418680f, -0.937339012f,
+ 0.342660717f, -0.939459224f,
+ 0.336889853f, -0.941544065f,
+ 0.331106306f, -0.943593458f,
+ 0.325310292f, -0.945607325f,
+ 0.319502031f, -0.947585591f,
+ 0.313681740f, -0.949528181f,
+ 0.307849640f, -0.951435021f,
+ 0.302005949f, -0.953306040f,
+ 0.296150888f, -0.955141168f,
+ 0.290284677f, -0.956940336f,
+ 0.284407537f, -0.958703475f,
+ 0.278519689f, -0.960430519f,
+ 0.272621355f, -0.962121404f,
+ 0.266712757f, -0.963776066f,
+ 0.260794118f, -0.965394442f,
+ 0.254865660f, -0.966976471f,
+ 0.248927606f, -0.968522094f,
+ 0.242980180f, -0.970031253f,
+ 0.237023606f, -0.971503891f,
+ 0.231058108f, -0.972939952f,
+ 0.225083911f, -0.974339383f,
+ 0.219101240f, -0.975702130f,
+ 0.213110320f, -0.977028143f,
+ 0.207111376f, -0.978317371f,
+ 0.201104635f, -0.979569766f,
+ 0.195090322f, -0.980785280f,
+ 0.189068664f, -0.981963869f,
+ 0.183039888f, -0.983105487f,
+ 0.177004220f, -0.984210092f,
+ 0.170961889f, -0.985277642f,
+ 0.164913120f, -0.986308097f,
+ 0.158858143f, -0.987301418f,
+ 0.152797185f, -0.988257568f,
+ 0.146730474f, -0.989176510f,
+ 0.140658239f, -0.990058210f,
+ 0.134580709f, -0.990902635f,
+ 0.128498111f, -0.991709754f,
+ 0.122410675f, -0.992479535f,
+ 0.116318631f, -0.993211949f,
+ 0.110222207f, -0.993906970f,
+ 0.104121634f, -0.994564571f,
+ 0.098017140f, -0.995184727f,
+ 0.091908956f, -0.995767414f,
+ 0.085797312f, -0.996312612f,
+ 0.079682438f, -0.996820299f,
+ 0.073564564f, -0.997290457f,
+ 0.067443920f, -0.997723067f,
+ 0.061320736f, -0.998118113f,
+ 0.055195244f, -0.998475581f,
+ 0.049067674f, -0.998795456f,
+ 0.042938257f, -0.999077728f,
+ 0.036807223f, -0.999322385f,
+ 0.030674803f, -0.999529418f,
+ 0.024541229f, -0.999698819f,
+ 0.018406730f, -0.999830582f,
+ 0.012271538f, -0.999924702f,
+ 0.006135885f, -0.999981175f
+};
+
+const float32_t twiddleCoef_rfft_2048[2048] = {
+ 0.000000000f, 1.000000000f,
+ 0.003067957f, 0.999995294f,
+ 0.006135885f, 0.999981175f,
+ 0.009203755f, 0.999957645f,
+ 0.012271538f, 0.999924702f,
+ 0.015339206f, 0.999882347f,
+ 0.018406730f, 0.999830582f,
+ 0.021474080f, 0.999769405f,
+ 0.024541229f, 0.999698819f,
+ 0.027608146f, 0.999618822f,
+ 0.030674803f, 0.999529418f,
+ 0.033741172f, 0.999430605f,
+ 0.036807223f, 0.999322385f,
+ 0.039872928f, 0.999204759f,
+ 0.042938257f, 0.999077728f,
+ 0.046003182f, 0.998941293f,
+ 0.049067674f, 0.998795456f,
+ 0.052131705f, 0.998640218f,
+ 0.055195244f, 0.998475581f,
+ 0.058258265f, 0.998301545f,
+ 0.061320736f, 0.998118113f,
+ 0.064382631f, 0.997925286f,
+ 0.067443920f, 0.997723067f,
+ 0.070504573f, 0.997511456f,
+ 0.073564564f, 0.997290457f,
+ 0.076623861f, 0.997060070f,
+ 0.079682438f, 0.996820299f,
+ 0.082740265f, 0.996571146f,
+ 0.085797312f, 0.996312612f,
+ 0.088853553f, 0.996044701f,
+ 0.091908956f, 0.995767414f,
+ 0.094963495f, 0.995480755f,
+ 0.098017140f, 0.995184727f,
+ 0.101069863f, 0.994879331f,
+ 0.104121634f, 0.994564571f,
+ 0.107172425f, 0.994240449f,
+ 0.110222207f, 0.993906970f,
+ 0.113270952f, 0.993564136f,
+ 0.116318631f, 0.993211949f,
+ 0.119365215f, 0.992850414f,
+ 0.122410675f, 0.992479535f,
+ 0.125454983f, 0.992099313f,
+ 0.128498111f, 0.991709754f,
+ 0.131540029f, 0.991310860f,
+ 0.134580709f, 0.990902635f,
+ 0.137620122f, 0.990485084f,
+ 0.140658239f, 0.990058210f,
+ 0.143695033f, 0.989622017f,
+ 0.146730474f, 0.989176510f,
+ 0.149764535f, 0.988721692f,
+ 0.152797185f, 0.988257568f,
+ 0.155828398f, 0.987784142f,
+ 0.158858143f, 0.987301418f,
+ 0.161886394f, 0.986809402f,
+ 0.164913120f, 0.986308097f,
+ 0.167938295f, 0.985797509f,
+ 0.170961889f, 0.985277642f,
+ 0.173983873f, 0.984748502f,
+ 0.177004220f, 0.984210092f,
+ 0.180022901f, 0.983662419f,
+ 0.183039888f, 0.983105487f,
+ 0.186055152f, 0.982539302f,
+ 0.189068664f, 0.981963869f,
+ 0.192080397f, 0.981379193f,
+ 0.195090322f, 0.980785280f,
+ 0.198098411f, 0.980182136f,
+ 0.201104635f, 0.979569766f,
+ 0.204108966f, 0.978948175f,
+ 0.207111376f, 0.978317371f,
+ 0.210111837f, 0.977677358f,
+ 0.213110320f, 0.977028143f,
+ 0.216106797f, 0.976369731f,
+ 0.219101240f, 0.975702130f,
+ 0.222093621f, 0.975025345f,
+ 0.225083911f, 0.974339383f,
+ 0.228072083f, 0.973644250f,
+ 0.231058108f, 0.972939952f,
+ 0.234041959f, 0.972226497f,
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+ 0.299079826f, -0.954228095f,
+ 0.296150888f, -0.955141168f,
+ 0.293219163f, -0.956045251f,
+ 0.290284677f, -0.956940336f,
+ 0.287347460f, -0.957826413f,
+ 0.284407537f, -0.958703475f,
+ 0.281464938f, -0.959571513f,
+ 0.278519689f, -0.960430519f,
+ 0.275571819f, -0.961280486f,
+ 0.272621355f, -0.962121404f,
+ 0.269668326f, -0.962953267f,
+ 0.266712757f, -0.963776066f,
+ 0.263754679f, -0.964589793f,
+ 0.260794118f, -0.965394442f,
+ 0.257831102f, -0.966190003f,
+ 0.254865660f, -0.966976471f,
+ 0.251897818f, -0.967753837f,
+ 0.248927606f, -0.968522094f,
+ 0.245955050f, -0.969281235f,
+ 0.242980180f, -0.970031253f,
+ 0.240003022f, -0.970772141f,
+ 0.237023606f, -0.971503891f,
+ 0.234041959f, -0.972226497f,
+ 0.231058108f, -0.972939952f,
+ 0.228072083f, -0.973644250f,
+ 0.225083911f, -0.974339383f,
+ 0.222093621f, -0.975025345f,
+ 0.219101240f, -0.975702130f,
+ 0.216106797f, -0.976369731f,
+ 0.213110320f, -0.977028143f,
+ 0.210111837f, -0.977677358f,
+ 0.207111376f, -0.978317371f,
+ 0.204108966f, -0.978948175f,
+ 0.201104635f, -0.979569766f,
+ 0.198098411f, -0.980182136f,
+ 0.195090322f, -0.980785280f,
+ 0.192080397f, -0.981379193f,
+ 0.189068664f, -0.981963869f,
+ 0.186055152f, -0.982539302f,
+ 0.183039888f, -0.983105487f,
+ 0.180022901f, -0.983662419f,
+ 0.177004220f, -0.984210092f,
+ 0.173983873f, -0.984748502f,
+ 0.170961889f, -0.985277642f,
+ 0.167938295f, -0.985797509f,
+ 0.164913120f, -0.986308097f,
+ 0.161886394f, -0.986809402f,
+ 0.158858143f, -0.987301418f,
+ 0.155828398f, -0.987784142f,
+ 0.152797185f, -0.988257568f,
+ 0.149764535f, -0.988721692f,
+ 0.146730474f, -0.989176510f,
+ 0.143695033f, -0.989622017f,
+ 0.140658239f, -0.990058210f,
+ 0.137620122f, -0.990485084f,
+ 0.134580709f, -0.990902635f,
+ 0.131540029f, -0.991310860f,
+ 0.128498111f, -0.991709754f,
+ 0.125454983f, -0.992099313f,
+ 0.122410675f, -0.992479535f,
+ 0.119365215f, -0.992850414f,
+ 0.116318631f, -0.993211949f,
+ 0.113270952f, -0.993564136f,
+ 0.110222207f, -0.993906970f,
+ 0.107172425f, -0.994240449f,
+ 0.104121634f, -0.994564571f,
+ 0.101069863f, -0.994879331f,
+ 0.098017140f, -0.995184727f,
+ 0.094963495f, -0.995480755f,
+ 0.091908956f, -0.995767414f,
+ 0.088853553f, -0.996044701f,
+ 0.085797312f, -0.996312612f,
+ 0.082740265f, -0.996571146f,
+ 0.079682438f, -0.996820299f,
+ 0.076623861f, -0.997060070f,
+ 0.073564564f, -0.997290457f,
+ 0.070504573f, -0.997511456f,
+ 0.067443920f, -0.997723067f,
+ 0.064382631f, -0.997925286f,
+ 0.061320736f, -0.998118113f,
+ 0.058258265f, -0.998301545f,
+ 0.055195244f, -0.998475581f,
+ 0.052131705f, -0.998640218f,
+ 0.049067674f, -0.998795456f,
+ 0.046003182f, -0.998941293f,
+ 0.042938257f, -0.999077728f,
+ 0.039872928f, -0.999204759f,
+ 0.036807223f, -0.999322385f,
+ 0.033741172f, -0.999430605f,
+ 0.030674803f, -0.999529418f,
+ 0.027608146f, -0.999618822f,
+ 0.024541229f, -0.999698819f,
+ 0.021474080f, -0.999769405f,
+ 0.018406730f, -0.999830582f,
+ 0.015339206f, -0.999882347f,
+ 0.012271538f, -0.999924702f,
+ 0.009203755f, -0.999957645f,
+ 0.006135885f, -0.999981175f,
+ 0.003067957f, -0.999995294f
+};
+
+const float32_t twiddleCoef_rfft_4096[4096] = {
+ 0.000000000f, 1.000000000f,
+ 0.001533980f, 0.999998823f,
+ 0.003067957f, 0.999995294f,
+ 0.004601926f, 0.999989411f,
+ 0.006135885f, 0.999981175f,
+ 0.007669829f, 0.999970586f,
+ 0.009203755f, 0.999957645f,
+ 0.010737659f, 0.999942350f,
+ 0.012271538f, 0.999924702f,
+ 0.013805389f, 0.999904701f,
+ 0.015339206f, 0.999882347f,
+ 0.016872988f, 0.999857641f,
+ 0.018406730f, 0.999830582f,
+ 0.019940429f, 0.999801170f,
+ 0.021474080f, 0.999769405f,
+ 0.023007681f, 0.999735288f,
+ 0.024541229f, 0.999698819f,
+ 0.026074718f, 0.999659997f,
+ 0.027608146f, 0.999618822f,
+ 0.029141509f, 0.999575296f,
+ 0.030674803f, 0.999529418f,
+ 0.032208025f, 0.999481187f,
+ 0.033741172f, 0.999430605f,
+ 0.035274239f, 0.999377670f,
+ 0.036807223f, 0.999322385f,
+ 0.038340120f, 0.999264747f,
+ 0.039872928f, 0.999204759f,
+ 0.041405641f, 0.999142419f,
+ 0.042938257f, 0.999077728f,
+ 0.044470772f, 0.999010686f,
+ 0.046003182f, 0.998941293f,
+ 0.047535484f, 0.998869550f,
+ 0.049067674f, 0.998795456f,
+ 0.050599749f, 0.998719012f,
+ 0.052131705f, 0.998640218f,
+ 0.053663538f, 0.998559074f,
+ 0.055195244f, 0.998475581f,
+ 0.056726821f, 0.998389737f,
+ 0.058258265f, 0.998301545f,
+ 0.059789571f, 0.998211003f,
+ 0.061320736f, 0.998118113f,
+ 0.062851758f, 0.998022874f,
+ 0.064382631f, 0.997925286f,
+ 0.065913353f, 0.997825350f,
+ 0.067443920f, 0.997723067f,
+ 0.068974328f, 0.997618435f,
+ 0.070504573f, 0.997511456f,
+ 0.072034653f, 0.997402130f,
+ 0.073564564f, 0.997290457f,
+ 0.075094301f, 0.997176437f,
+ 0.076623861f, 0.997060070f,
+ 0.078153242f, 0.996941358f,
+ 0.079682438f, 0.996820299f,
+ 0.081211447f, 0.996696895f,
+ 0.082740265f, 0.996571146f,
+ 0.084268888f, 0.996443051f,
+ 0.085797312f, 0.996312612f,
+ 0.087325535f, 0.996179829f,
+ 0.088853553f, 0.996044701f,
+ 0.090381361f, 0.995907229f,
+ 0.091908956f, 0.995767414f,
+ 0.093436336f, 0.995625256f,
+ 0.094963495f, 0.995480755f,
+ 0.096490431f, 0.995333912f,
+ 0.098017140f, 0.995184727f,
+ 0.099543619f, 0.995033199f,
+ 0.101069863f, 0.994879331f,
+ 0.102595869f, 0.994723121f,
+ 0.104121634f, 0.994564571f,
+ 0.105647154f, 0.994403680f,
+ 0.107172425f, 0.994240449f,
+ 0.108697444f, 0.994074879f,
+ 0.110222207f, 0.993906970f,
+ 0.111746711f, 0.993736722f,
+ 0.113270952f, 0.993564136f,
+ 0.114794927f, 0.993389211f,
+ 0.116318631f, 0.993211949f,
+ 0.117842062f, 0.993032350f,
+ 0.119365215f, 0.992850414f,
+ 0.120888087f, 0.992666142f,
+ 0.122410675f, 0.992479535f,
+ 0.123932975f, 0.992290591f,
+ 0.125454983f, 0.992099313f,
+ 0.126976696f, 0.991905700f,
+ 0.128498111f, 0.991709754f,
+ 0.130019223f, 0.991511473f,
+ 0.131540029f, 0.991310860f,
+ 0.133060525f, 0.991107914f,
+ 0.134580709f, 0.990902635f,
+ 0.136100575f, 0.990695025f,
+ 0.137620122f, 0.990485084f,
+ 0.139139344f, 0.990272812f,
+ 0.140658239f, 0.990058210f,
+ 0.142176804f, 0.989841278f,
+ 0.143695033f, 0.989622017f,
+ 0.145212925f, 0.989400428f,
+ 0.146730474f, 0.989176510f,
+ 0.148247679f, 0.988950265f,
+ 0.149764535f, 0.988721692f,
+ 0.151281038f, 0.988490793f,
+ 0.152797185f, 0.988257568f,
+ 0.154312973f, 0.988022017f,
+ 0.155828398f, 0.987784142f,
+ 0.157343456f, 0.987543942f,
+ 0.158858143f, 0.987301418f,
+ 0.160372457f, 0.987056571f,
+ 0.161886394f, 0.986809402f,
+ 0.163399949f, 0.986559910f,
+ 0.164913120f, 0.986308097f,
+ 0.166425904f, 0.986053963f,
+ 0.167938295f, 0.985797509f,
+ 0.169450291f, 0.985538735f,
+ 0.170961889f, 0.985277642f,
+ 0.172473084f, 0.985014231f,
+ 0.173983873f, 0.984748502f,
+ 0.175494253f, 0.984480455f,
+ 0.177004220f, 0.984210092f,
+ 0.178513771f, 0.983937413f,
+ 0.180022901f, 0.983662419f,
+ 0.181531608f, 0.983385110f,
+ 0.183039888f, 0.983105487f,
+ 0.184547737f, 0.982823551f,
+ 0.186055152f, 0.982539302f,
+ 0.187562129f, 0.982252741f,
+ 0.189068664f, 0.981963869f,
+ 0.190574755f, 0.981672686f,
+ 0.192080397f, 0.981379193f,
+ 0.193585587f, 0.981083391f,
+ 0.195090322f, 0.980785280f,
+ 0.196594598f, 0.980484862f,
+ 0.198098411f, 0.980182136f,
+ 0.199601758f, 0.979877104f,
+ 0.201104635f, 0.979569766f,
+ 0.202607039f, 0.979260123f,
+ 0.204108966f, 0.978948175f,
+ 0.205610413f, 0.978633924f,
+ 0.207111376f, 0.978317371f,
+ 0.208611852f, 0.977998515f,
+ 0.210111837f, 0.977677358f,
+ 0.211611327f, 0.977353900f,
+ 0.213110320f, 0.977028143f,
+ 0.214608811f, 0.976700086f,
+ 0.216106797f, 0.976369731f,
+ 0.217604275f, 0.976037079f,
+ 0.219101240f, 0.975702130f,
+ 0.220597690f, 0.975364885f,
+ 0.222093621f, 0.975025345f,
+ 0.223589029f, 0.974683511f,
+ 0.225083911f, 0.974339383f,
+ 0.226578264f, 0.973992962f,
+ 0.228072083f, 0.973644250f,
+ 0.229565366f, 0.973293246f,
+ 0.231058108f, 0.972939952f,
+ 0.232550307f, 0.972584369f,
+ 0.234041959f, 0.972226497f,
+ 0.235533059f, 0.971866337f,
+ 0.237023606f, 0.971503891f,
+ 0.238513595f, 0.971139158f,
+ 0.240003022f, 0.970772141f,
+ 0.241491885f, 0.970402839f,
+ 0.242980180f, 0.970031253f,
+ 0.244467903f, 0.969657385f,
+ 0.245955050f, 0.969281235f,
+ 0.247441619f, 0.968902805f,
+ 0.248927606f, 0.968522094f,
+ 0.250413007f, 0.968139105f,
+ 0.251897818f, 0.967753837f,
+ 0.253382037f, 0.967366292f,
+ 0.254865660f, 0.966976471f,
+ 0.256348682f, 0.966584374f,
+ 0.257831102f, 0.966190003f,
+ 0.259312915f, 0.965793359f,
+ 0.260794118f, 0.965394442f,
+ 0.262274707f, 0.964993253f,
+ 0.263754679f, 0.964589793f,
+ 0.265234030f, 0.964184064f,
+ 0.266712757f, 0.963776066f,
+ 0.268190857f, 0.963365800f,
+ 0.269668326f, 0.962953267f,
+ 0.271145160f, 0.962538468f,
+ 0.272621355f, 0.962121404f,
+ 0.274096910f, 0.961702077f,
+ 0.275571819f, 0.961280486f,
+ 0.277046080f, 0.960856633f,
+ 0.278519689f, 0.960430519f,
+ 0.279992643f, 0.960002146f,
+ 0.281464938f, 0.959571513f,
+ 0.282936570f, 0.959138622f,
+ 0.284407537f, 0.958703475f,
+ 0.285877835f, 0.958266071f,
+ 0.287347460f, 0.957826413f,
+ 0.288816408f, 0.957384501f,
+ 0.290284677f, 0.956940336f,
+ 0.291752263f, 0.956493919f,
+ 0.293219163f, 0.956045251f,
+ 0.294685372f, 0.955594334f,
+ 0.296150888f, 0.955141168f,
+ 0.297615707f, 0.954685755f,
+ 0.299079826f, 0.954228095f,
+ 0.300543241f, 0.953768190f,
+ 0.302005949f, 0.953306040f,
+ 0.303467947f, 0.952841648f,
+ 0.304929230f, 0.952375013f,
+ 0.306389795f, 0.951906137f,
+ 0.307849640f, 0.951435021f,
+ 0.309308760f, 0.950961666f,
+ 0.310767153f, 0.950486074f,
+ 0.312224814f, 0.950008245f,
+ 0.313681740f, 0.949528181f,
+ 0.315137929f, 0.949045882f,
+ 0.316593376f, 0.948561350f,
+ 0.318048077f, 0.948074586f,
+ 0.319502031f, 0.947585591f,
+ 0.320955232f, 0.947094366f,
+ 0.322407679f, 0.946600913f,
+ 0.323859367f, 0.946105232f,
+ 0.325310292f, 0.945607325f,
+ 0.326760452f, 0.945107193f,
+ 0.328209844f, 0.944604837f,
+ 0.329658463f, 0.944100258f,
+ 0.331106306f, 0.943593458f,
+ 0.332553370f, 0.943084437f,
+ 0.333999651f, 0.942573198f,
+ 0.335445147f, 0.942059740f,
+ 0.336889853f, 0.941544065f,
+ 0.338333767f, 0.941026175f,
+ 0.339776884f, 0.940506071f,
+ 0.341219202f, 0.939983753f,
+ 0.342660717f, 0.939459224f,
+ 0.344101426f, 0.938932484f,
+ 0.345541325f, 0.938403534f,
+ 0.346980411f, 0.937872376f,
+ 0.348418680f, 0.937339012f,
+ 0.349856130f, 0.936803442f,
+ 0.351292756f, 0.936265667f,
+ 0.352728556f, 0.935725689f,
+ 0.354163525f, 0.935183510f,
+ 0.355597662f, 0.934639130f,
+ 0.357030961f, 0.934092550f,
+ 0.358463421f, 0.933543773f,
+ 0.359895037f, 0.932992799f,
+ 0.361325806f, 0.932439629f,
+ 0.362755724f, 0.931884266f,
+ 0.364184790f, 0.931326709f,
+ 0.365612998f, 0.930766961f,
+ 0.367040346f, 0.930205023f,
+ 0.368466830f, 0.929640896f,
+ 0.369892447f, 0.929074581f,
+ 0.371317194f, 0.928506080f,
+ 0.372741067f, 0.927935395f,
+ 0.374164063f, 0.927362526f,
+ 0.375586178f, 0.926787474f,
+ 0.377007410f, 0.926210242f,
+ 0.378427755f, 0.925630831f,
+ 0.379847209f, 0.925049241f,
+ 0.381265769f, 0.924465474f,
+ 0.382683432f, 0.923879533f,
+ 0.384100195f, 0.923291417f,
+ 0.385516054f, 0.922701128f,
+ 0.386931006f, 0.922108669f,
+ 0.388345047f, 0.921514039f,
+ 0.389758174f, 0.920917242f,
+ 0.391170384f, 0.920318277f,
+ 0.392581674f, 0.919717146f,
+ 0.393992040f, 0.919113852f,
+ 0.395401479f, 0.918508394f,
+ 0.396809987f, 0.917900776f,
+ 0.398217562f, 0.917290997f,
+ 0.399624200f, 0.916679060f,
+ 0.401029897f, 0.916064966f,
+ 0.402434651f, 0.915448716f,
+ 0.403838458f, 0.914830312f,
+ 0.405241314f, 0.914209756f,
+ 0.406643217f, 0.913587048f,
+ 0.408044163f, 0.912962190f,
+ 0.409444149f, 0.912335185f,
+ 0.410843171f, 0.911706032f,
+ 0.412241227f, 0.911074734f,
+ 0.413638312f, 0.910441292f,
+ 0.415034424f, 0.909805708f,
+ 0.416429560f, 0.909167983f,
+ 0.417823716f, 0.908528119f,
+ 0.419216888f, 0.907886116f,
+ 0.420609074f, 0.907241978f,
+ 0.422000271f, 0.906595705f,
+ 0.423390474f, 0.905947298f,
+ 0.424779681f, 0.905296759f,
+ 0.426167889f, 0.904644091f,
+ 0.427555093f, 0.903989293f,
+ 0.428941292f, 0.903332368f,
+ 0.430326481f, 0.902673318f,
+ 0.431710658f, 0.902012144f,
+ 0.433093819f, 0.901348847f,
+ 0.434475961f, 0.900683429f,
+ 0.435857080f, 0.900015892f,
+ 0.437237174f, 0.899346237f,
+ 0.438616239f, 0.898674466f,
+ 0.439994271f, 0.898000580f,
+ 0.441371269f, 0.897324581f,
+ 0.442747228f, 0.896646470f,
+ 0.444122145f, 0.895966250f,
+ 0.445496017f, 0.895283921f,
+ 0.446868840f, 0.894599486f,
+ 0.448240612f, 0.893912945f,
+ 0.449611330f, 0.893224301f,
+ 0.450980989f, 0.892533555f,
+ 0.452349587f, 0.891840709f,
+ 0.453717121f, 0.891145765f,
+ 0.455083587f, 0.890448723f,
+ 0.456448982f, 0.889749586f,
+ 0.457813304f, 0.889048356f,
+ 0.459176548f, 0.888345033f,
+ 0.460538711f, 0.887639620f,
+ 0.461899791f, 0.886932119f,
+ 0.463259784f, 0.886222530f,
+ 0.464618686f, 0.885510856f,
+ 0.465976496f, 0.884797098f,
+ 0.467333209f, 0.884081259f,
+ 0.468688822f, 0.883363339f,
+ 0.470043332f, 0.882643340f,
+ 0.471396737f, 0.881921264f,
+ 0.472749032f, 0.881197113f,
+ 0.474100215f, 0.880470889f,
+ 0.475450282f, 0.879742593f,
+ 0.476799230f, 0.879012226f,
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+ 0.059789571f, -0.998211003f,
+ 0.058258265f, -0.998301545f,
+ 0.056726821f, -0.998389737f,
+ 0.055195244f, -0.998475581f,
+ 0.053663538f, -0.998559074f,
+ 0.052131705f, -0.998640218f,
+ 0.050599749f, -0.998719012f,
+ 0.049067674f, -0.998795456f,
+ 0.047535484f, -0.998869550f,
+ 0.046003182f, -0.998941293f,
+ 0.044470772f, -0.999010686f,
+ 0.042938257f, -0.999077728f,
+ 0.041405641f, -0.999142419f,
+ 0.039872928f, -0.999204759f,
+ 0.038340120f, -0.999264747f,
+ 0.036807223f, -0.999322385f,
+ 0.035274239f, -0.999377670f,
+ 0.033741172f, -0.999430605f,
+ 0.032208025f, -0.999481187f,
+ 0.030674803f, -0.999529418f,
+ 0.029141509f, -0.999575296f,
+ 0.027608146f, -0.999618822f,
+ 0.026074718f, -0.999659997f,
+ 0.024541229f, -0.999698819f,
+ 0.023007681f, -0.999735288f,
+ 0.021474080f, -0.999769405f,
+ 0.019940429f, -0.999801170f,
+ 0.018406730f, -0.999830582f,
+ 0.016872988f, -0.999857641f,
+ 0.015339206f, -0.999882347f,
+ 0.013805389f, -0.999904701f,
+ 0.012271538f, -0.999924702f,
+ 0.010737659f, -0.999942350f,
+ 0.009203755f, -0.999957645f,
+ 0.007669829f, -0.999970586f,
+ 0.006135885f, -0.999981175f,
+ 0.004601926f, -0.999989411f,
+ 0.003067957f, -0.999995294f,
+ 0.001533980f, -0.999998823f
+};
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
index 000000000..83d7fe7f9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_f32.c
+*
+* Description: Floating-point complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_conj Complex Conjugate
+ *
+ * Conjugates the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0)] = pSrc[(2*n)+0]; // real part
+ * pDst[(2*n)+1)] = -pSrc[(2*n)+1]; // imag part
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inR1, inR2, inR3, inR4;
+ float32_t inI1, inI2, inI3, inI4;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* read real input samples */
+ inR1 = pSrc[0];
+ /* store real samples to destination */
+ pDst[0] = inR1;
+ inR2 = pSrc[2];
+ pDst[2] = inR2;
+ inR3 = pSrc[4];
+ pDst[4] = inR3;
+ inR4 = pSrc[6];
+ pDst[6] = inR4;
+
+ /* read imaginary input samples */
+ inI1 = pSrc[1];
+ inI2 = pSrc[3];
+
+ /* conjugate input */
+ inI1 = -inI1;
+
+ /* read imaginary input samples */
+ inI3 = pSrc[5];
+
+ /* conjugate input */
+ inI2 = -inI2;
+
+ /* read imaginary input samples */
+ inI4 = pSrc[7];
+
+ /* conjugate input */
+ inI3 = -inI3;
+
+ /* store imaginary samples to destination */
+ pDst[1] = inI1;
+ pDst[3] = inI2;
+
+ /* conjugate input */
+ inI4 = -inI4;
+
+ /* store imaginary samples to destination */
+ pDst[5] = inI3;
+
+ /* increment source pointer by 8 to process next sampels */
+ pSrc += 8u;
+
+ /* store imaginary sample to destination */
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to store next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 000000000..5f13ca3cb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q15.c
+*
+* Description: Q15 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t zero = 0;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = __QASX(zero, in1);
+ in2 = __QASX(zero, in2);
+ in3 = __QASX(zero, in3);
+ in4 = __QASX(zero, in4);
+
+#else
+
+ in1 = __QSAX(zero, in1);
+ in2 = __QSAX(zero, in2);
+ in3 = __QSAX(zero, in3);
+ in4 = __QSAX(zero, in4);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+ in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+ in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+ in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+ *__SIMD32(pDst)++ = in1;
+ *__SIMD32(pDst)++ = in2;
+ *__SIMD32(pDst)++ = in3;
+ *__SIMD32(pDst)++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = __SSAT(-*pSrc++, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ q15_t in;
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 000000000..496107352
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q31.c
+*
+* Description: Q31 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
+ q31_t inI1, inI2, inI3, inI4; /* Temporary imaginary variables */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ /* read real input sample */
+ inR1 = pSrc[0];
+ /* store real input sample */
+ pDst[0] = inR1;
+
+ /* read imaginary input sample */
+ inI1 = pSrc[1];
+
+ /* read real input sample */
+ inR2 = pSrc[2];
+ /* store real input sample */
+ pDst[2] = inR2;
+
+ /* read imaginary input sample */
+ inI2 = pSrc[3];
+
+ /* negate imaginary input sample */
+ inI1 = __QSUB(0, inI1);
+
+ /* read real input sample */
+ inR3 = pSrc[4];
+ /* store real input sample */
+ pDst[4] = inR3;
+
+ /* read imaginary input sample */
+ inI3 = pSrc[5];
+
+ /* negate imaginary input sample */
+ inI2 = __QSUB(0, inI2);
+
+ /* read real input sample */
+ inR4 = pSrc[6];
+ /* store real input sample */
+ pDst[6] = inR4;
+
+ /* negate imaginary input sample */
+ inI3 = __QSUB(0, inI3);
+
+ /* store imaginary input sample */
+ inI4 = pSrc[7];
+
+ /* store imaginary input samples */
+ pDst[1] = inI1;
+
+ /* negate imaginary input sample */
+ inI4 = __QSUB(0, inI4);
+
+ /* store imaginary input samples */
+ pDst[3] = inI2;
+
+ /* increment source pointer by 8 to proecess next samples */
+ pSrc += 8u;
+
+ /* store imaginary input samples */
+ pDst[5] = inI3;
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to process next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 000000000..da7c5517c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_f32.c
+*
+* Description: Floating-point complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_dot_prod Complex Dot Product
+ *
+ * Computes the dot product of two complex vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * The <code>pSrcA</code> points to the first complex input vector and
+ * <code>pSrcB</code> points to the second complex input vector.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ * <pre>
+ * realResult=0;
+ * imagResult=0;
+ * for(n=0; n<numSamples; n++) {
+ * realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];
+ * imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in the destination buffers */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 000000000..1d168d7c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q15.c
+*
+* Description: Processing function for the Q15 Complex Dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q15 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.
+ * As a final step, the accumulators are converted to 8.24 format.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 8.24 format */
+ /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+ *realResult = (q31_t) (real_sum) >> 6;
+ /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+ *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 000000000..f7e2363bc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q31.c
+*
+* Description: Q31 complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q31 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 16.48 format */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 000000000..2dc16b1a7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_f32.c
+*
+* Description: Floating-point complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag Complex Magnitude
+ *
+ * Computes the magnitude of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+/**
+ * @brief Floating-point complex magnitude.
+ * @param[in] *pSrc points to complex input buffer
+ * @param[out] *pDst points to real output buffer
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t realIn, imagIn; /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 000000000..89decf2b5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q15.c
+*
+* Description: Q15 complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to hold input values */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt(real * real + imag * imag) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 000000000..c92fcb46f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q31.c
+*
+* Description: Q31 complex magnitude
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+/**
+ * @brief Q31 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to hold input values */
+ q31_t acc0, acc1; /* Accumulators */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
+ q31_t out1, out2, out3, out4; /* Accumulators */
+ q63_t mul1, mul2, mul3, mul4; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read complex input from source buffer */
+ real1 = pSrc[0];
+ imag1 = pSrc[1];
+ real2 = pSrc[2];
+ imag2 = pSrc[3];
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* read complex input from source buffer */
+ real1 = pSrc[4];
+ imag1 = pSrc[5];
+ real2 = pSrc[6];
+ imag2 = pSrc[7];
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[0]);
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[1]);
+
+ /* calculate power of input values */
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[2]);
+
+ /* increment destination by 8 to process next samples */
+ pSrc += 8u;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[3]);
+
+ /* increment destination by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 2.30 format in the destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 000000000..abc36976d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,215 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_f32.c
+*
+* Description: Floating-point complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared
+ *
+ * Computes the magnitude squared of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t real, imag; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
+ float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
+ float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
+ float32_t mul5, mul6, mul7, mul8; /* Temporary variables */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output values */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ /* read real input sample from source buffer */
+ real1 = pSrc[0];
+ /* read imaginary input sample from source buffer */
+ imag1 = pSrc[1];
+
+ /* calculate power of real value */
+ mul1 = real1 * real1;
+
+ /* read real input sample from source buffer */
+ real2 = pSrc[2];
+
+ /* calculate power of imaginary value */
+ mul2 = imag1 * imag1;
+
+ /* read imaginary input sample from source buffer */
+ imag2 = pSrc[3];
+
+ /* calculate power of real value */
+ mul3 = real2 * real2;
+
+ /* read real input sample from source buffer */
+ real3 = pSrc[4];
+
+ /* calculate power of imaginary value */
+ mul4 = imag2 * imag2;
+
+ /* read imaginary input sample from source buffer */
+ imag3 = pSrc[5];
+
+ /* calculate power of real value */
+ mul5 = real3 * real3;
+ /* calculate power of imaginary value */
+ mul6 = imag3 * imag3;
+
+ /* read real input sample from source buffer */
+ real4 = pSrc[6];
+
+ /* accumulate real and imaginary powers */
+ out1 = mul1 + mul2;
+
+ /* read imaginary input sample from source buffer */
+ imag4 = pSrc[7];
+
+ /* accumulate real and imaginary powers */
+ out2 = mul3 + mul4;
+
+ /* calculate power of real value */
+ mul7 = real4 * real4;
+ /* calculate power of imaginary value */
+ mul8 = imag4 * imag4;
+
+ /* store output to destination */
+ pDst[0] = out1;
+
+ /* accumulate real and imaginary powers */
+ out3 = mul5 + mul6;
+
+ /* store output to destination */
+ pDst[1] = out2;
+
+ /* accumulate real and imaginary powers */
+ out4 = mul7 + mul8;
+
+ /* store output to destination */
+ pDst[2] = out3;
+
+ /* increment destination pointer by 8 to process next samples */
+ pSrc += 8u;
+
+ /* store output to destination */
+ pDst[3] = out4;
+
+ /* increment destination pointer by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* out = (real * real) + (imag * imag) */
+ /* store the result in the destination buffer. */
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 000000000..2dfce2ca1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q15.c
+*
+* Description: Q15 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+ *pDst++ = (q15_t) (acc1 >> 17);
+ *pDst++ = (q15_t) (acc2 >> 17);
+ *pDst++ = (q15_t) (acc3 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to store real and imaginary values */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 000000000..3d1408069
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q31.c
+*
+* Description: Q31 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to store real and imaginary values */
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 000000000..1fe0f36b7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_f32.c
+*
+* Description: Floating-point complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+ *
+ * Multiplies a complex vector by another complex vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+ * pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
+ float32_t acc1, acc2, acc3, acc4;
+
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA; /* A[2 * i] */
+ c1 = *pSrcB; /* B[2 * i] */
+
+ b1 = *(pSrcA + 1); /* A[2 * i + 1] */
+ acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */
+
+ a2 = *(pSrcA + 2); /* A[2 * i + 2] */
+ acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+ d1 = *(pSrcB + 1); /* B[2 * i + 1] */
+ c2 = *(pSrcB + 2); /* B[2 * i + 2] */
+ acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ d2 = *(pSrcB + 3); /* B[2 * i + 3] */
+ acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */
+
+ b2 = *(pSrcA + 3); /* A[2 * i + 3] */
+ acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+ a1 = *(pSrcA + 4); /* A[2 * i + 4] */
+ acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */
+
+ c1 = *(pSrcB + 4); /* B[2 * i + 4] */
+ acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+ *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ b1 = *(pSrcA + 5); /* A[2 * i + 5] */
+ acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+ *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+ acc1 = (a1 * c1);
+
+ d1 = *(pSrcB + 5);
+ acc2 = (b1 * c1);
+
+ *(pDst + 2) = acc3;
+ *(pDst + 3) = acc4;
+
+ a2 = *(pSrcA + 6);
+ acc1 -= (b1 * d1);
+
+ c2 = *(pSrcB + 6);
+ acc2 += (a1 * d1);
+
+ b2 = *(pSrcA + 7);
+ acc3 = (a2 * c2);
+
+ d2 = *(pSrcB + 7);
+ acc4 = (b2 * c2);
+
+ *(pDst + 4) = acc1;
+ pSrcA += 8u;
+
+ acc3 -= (b2 * d2);
+ acc4 += (a2 * d2);
+
+ *(pDst + 5) = acc2;
+ pSrcB += 8u;
+
+ *(pDst + 6) = acc3;
+ *(pDst + 7) = acc4;
+
+ pDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA++;
+ b1 = *pSrcA++;
+ c1 = *pSrcB++;
+ d1 = *pSrcB++;
+
+ /* store the result in the destination buffer. */
+ *pDst++ = (a1 * c1) - (b1 * d1);
+ *pDst++ = (a1 * d1) + (b1 * c1);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 000000000..a775d9831
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q15.c
+*
+* Description: Q15 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 000000000..7b91b35ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q31.c
+*
+* Description: Q31 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+ q31_t mul1, mul2, mul3, mul4;
+ q31_t out1, out2;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 000000000..10d3f512c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_f32.c
+*
+* Description: Floating-point complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication
+ *
+ * Multiplies a complex vector by a real vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values while the real array has a total of <code>numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+ * pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
+ float32_t inA5, inA6, inA7, inA8; /* Temporary variables to hold input data */
+ float32_t inB1, inB2, inB3, inB4; /* Temporary variables to hold input data */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ float32_t out5, out6, out7, out8; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read input from complex input buffer */
+ inA1 = pSrcCmplx[0];
+ inA2 = pSrcCmplx[1];
+ /* read input from real input buffer */
+ inB1 = pSrcReal[0];
+
+ /* read input from complex input buffer */
+ inA3 = pSrcCmplx[2];
+
+ /* multiply complex buffer real input with real buffer input */
+ out1 = inA1 * inB1;
+
+ /* read input from complex input buffer */
+ inA4 = pSrcCmplx[3];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out2 = inA2 * inB1;
+
+ /* read input from real input buffer */
+ inB2 = pSrcReal[1];
+ /* read input from complex input buffer */
+ inA5 = pSrcCmplx[4];
+
+ /* multiply complex buffer real input with real buffer input */
+ out3 = inA3 * inB2;
+
+ /* read input from complex input buffer */
+ inA6 = pSrcCmplx[5];
+ /* read input from real input buffer */
+ inB3 = pSrcReal[2];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out4 = inA4 * inB2;
+
+ /* read input from complex input buffer */
+ inA7 = pSrcCmplx[6];
+
+ /* multiply complex buffer real input with real buffer input */
+ out5 = inA5 * inB3;
+
+ /* read input from complex input buffer */
+ inA8 = pSrcCmplx[7];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out6 = inA6 * inB3;
+
+ /* read input from real input buffer */
+ inB4 = pSrcReal[3];
+
+ /* store result to destination bufer */
+ pCmplxDst[0] = out1;
+
+ /* multiply complex buffer real input with real buffer input */
+ out7 = inA7 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[1] = out2;
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out8 = inA8 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[2] = out3;
+ pCmplxDst[3] = out4;
+ pCmplxDst[4] = out5;
+
+ /* incremnet complex input buffer by 8 to process next samples */
+ pSrcCmplx += 8u;
+
+ /* store result to destination bufer */
+ pCmplxDst[5] = out6;
+
+ /* increment real input buffer by 4 to process next samples */
+ pSrcReal += 4u;
+
+ /* store result to destination bufer */
+ pCmplxDst[6] = out7;
+ pCmplxDst[7] = out8;
+
+ /* increment destination buffer by 8 to process next sampels */
+ pCmplxDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 000000000..0bba42363
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q15.c
+*
+* Description: Q15 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q15_t in; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA1, inA2; /* Temporary variables to hold input data */
+ q31_t inB1; /* Temporary variables to hold input data */
+ q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read complex number both real and imaginary from complex input buffer */
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ /* read two real values at a time from real input buffer */
+ inB1 = *__SIMD32(pSrcReal)++;
+ /* read complex number both real and imaginary from complex input buffer */
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+ /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* saturate the result */
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ /* pack real and imaginary outputs and store them to destination */
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ inB1 = *__SIMD32(pSrcReal)++;
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagOut = imagA * realB. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 000000000..44641ea2b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q31.c
+*
+* Description: Q31 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q31_t inA1; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA2, inA3, inA4; /* Temporary variables to hold input data */
+ q31_t inB1, inB2; /* Temporary variabels to hold input data */
+ q31_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagReal = imagA * realB. */
+ inA1 = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 000000000..cc1fc99a0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_f32.c
+*
+* Description: Floating-point PID Control initialization function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state & 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag)
+{
+
+ /* Derived coefficient A0 */
+ S->A0 = S->Kp + S->Ki + S->Kd;
+
+ /* Derived coefficient A1 */
+ S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 000000000..8f293f6e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q15.c
+*
+* Description: Q15 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficients and pack into A1 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+ S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp; /*to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = S->Kp + S->Ki + S->Kd;
+ S->A0 = (q15_t) __SSAT(temp, 16);
+
+ /* Derived coefficients and pack into A1 */
+ temp = -(S->Kd + S->Kd + S->Kp);
+ S->A1 = (q15_t) __SSAT(temp, 16);
+ S->A2 = S->Kd;
+
+
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 000000000..b492cf79f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q31.c
+*
+* Description: Q31 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficient A1 */
+ S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp;
+
+ /* Derived coefficient A0 */
+ temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+ S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+ /* Derived coefficient A1 */
+ temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+ S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 000000000..c6753b1b5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_f32.c
+*
+* Description: Floating-point PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the floating-point PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 000000000..410339e59
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q15.c
+*
+* Description: Q15 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q15 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 000000000..fd8208008
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q31.c
+*
+* Description: Q31 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q31 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 000000000..4658f9a2a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,436 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_f32.c
+*
+* Description: Sine and Cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup SinCos Sine Cosine
+ *
+ * Computes the trigonometric sine and cosine values using a combination of table lookup
+ * and linear interpolation.
+ * There are separate functions for Q31 and floating-point data types.
+ * The input to the floating-point version is in degrees while the
+ * fixed-point Q31 have a scaled input with the range
+ * [-1 0.9999] mapping to [-180 179] degrees.
+ *
+ * The implementation is based on table lookup using 360 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index.
+ * -# Compute the fractional portion (fract) of the input.
+ * -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Sine value is computed as <code> *psinVal = y0 + (fract * (y1 - y0))</code>.
+ * -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Cosine value is computed as <code> *pcosVal = y0 + (fract * (y1 - y0))</code>.
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+
+/**
+* \par
+* Cosine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* cosTable[i]= cos((i-180) * PI/180.0);
+* } </pre>
+*/
+
+static const float32_t cosTable[360] = {
+ -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+ -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+ -0.992546151641321980f, -0.990268068741570250f,
+ -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+ -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+ -0.965925826289068200f, -0.961261695938318670f,
+ -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+ -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+ -0.920504853452440150f, -0.913545457642600760f,
+ -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+ -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+ -0.857167300702112220f, -0.848048096156425960f,
+ -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+ -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+ -0.777145961456970680f, -0.766044443118977900f,
+ -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+ -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+ -0.681998360062498370f, -0.669130606358858240f,
+ -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+ -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+ -0.573576436351045830f, -0.559192903470746680f,
+ -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+ -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+ -0.453990499739546750f, -0.438371146789077510f,
+ -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+ -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+ -0.325568154457156420f, -0.309016994374947340f,
+ -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+ -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+ -0.190808995376544800f, -0.173648177666930300f,
+ -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+ -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+ -0.052335956242943620f, -0.034899496702500733f,
+ -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+ 0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+ 0.087155742747658138f, 0.104528463267653460f,
+ 0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+ 0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+ 0.224951054343864920f, 0.241921895599667900f,
+ 0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+ 0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+ 0.358367949545300380f, 0.374606593415911960f,
+ 0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+ 0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+ 0.484809620246337110f, 0.500000000000000110f,
+ 0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+ 0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+ 0.601815023152048270f, 0.615661475325658290f,
+ 0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+ 0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+ 0.707106781186547570f, 0.719339800338651190f,
+ 0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+ 0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+ 0.798635510047292830f, 0.809016994374947450f,
+ 0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+ 0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+ 0.874619707139395740f, 0.882947592858926990f,
+ 0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+ 0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+ 0.933580426497201740f, 0.939692620785908430f,
+ 0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+ 0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+ 0.974370064785235250f, 0.978147600733805690f,
+ 0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+ 0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+ 0.996194698091745550f, 0.997564050259824200f,
+ 0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+ 1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+ 0.998629534754573830f, 0.997564050259824200f,
+ 0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+ 0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+ 0.981627183447663980f, 0.978147600733805690f,
+ 0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+ 0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+ 0.945518575599316850f, 0.939692620785908430f,
+ 0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+ 0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+ 0.891006524188367900f, 0.882947592858926990f,
+ 0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+ 0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+ 0.819152044288991800f, 0.809016994374947450f,
+ 0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+ 0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+ 0.731353701619170570f, 0.719339800338651190f,
+ 0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+ 0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+ 0.629320391049837500f, 0.615661475325658290f,
+ 0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+ 0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+ 0.515038074910054380f, 0.500000000000000110f,
+ 0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+ 0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+ 0.390731128489273940f, 0.374606593415911960f,
+ 0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+ 0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+ 0.258819045102520740f, 0.241921895599667900f,
+ 0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+ 0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+ 0.121869343405147490f, 0.104528463267653460f,
+ 0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+ 0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+ -0.017452406437283477f, -0.034899496702500733f,
+ -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+ -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+ -0.156434465040231040f, -0.173648177666930300f,
+ -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+ -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+ -0.292371704722736660f, -0.309016994374947340f,
+ -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+ -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+ -0.422618261740699330f, -0.438371146789077510f,
+ -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+ -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+ -0.544639035015027080f, -0.559192903470746680f,
+ -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+ -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+ -0.656059028990507500f, -0.669130606358858240f,
+ -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+ -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+ -0.754709580222772010f, -0.766044443118977900f,
+ -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+ -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+ -0.838670567945424160f, -0.848048096156425960f,
+ -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+ -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+ -0.906307787036649940f, -0.913545457642600760f,
+ -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+ -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+ -0.956304755963035440f, -0.961261695938318670f,
+ -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+ -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+ -0.987688340595137660f, -0.990268068741570250f,
+ -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+ -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+ -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**
+* \par
+* Sine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* sinTable[i]= sin((i-180) * PI/180.0);
+* } </pre>
+*/
+
+
+static const float32_t sinTable[360] = {
+ -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+ -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+ -0.121869343405147550f, -0.139173100960065740f,
+ -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+ -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+ -0.258819045102521020f, -0.275637355816999660f,
+ -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+ -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+ -0.390731128489274160f, -0.406736643075800430f,
+ -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+ -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+ -0.515038074910054380f, -0.529919264233204900f,
+ -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+ -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+ -0.629320391049837720f, -0.642787609686539470f,
+ -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+ -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+ -0.731353701619170570f, -0.743144825477394240f,
+ -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+ -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+ -0.819152044288992020f, -0.829037572555041740f,
+ -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+ -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+ -0.891006524188367900f, -0.898794046299166930f,
+ -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+ -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+ -0.945518575599316850f, -0.951056516295153640f,
+ -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+ -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+ -0.981627183447663980f, -0.984807753012208020f,
+ -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+ -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+ -0.998629534754573830f, -0.999390827019095760f,
+ -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+ -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+ -0.996194698091745550f, -0.994521895368273290f,
+ -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+ -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+ -0.974370064785235250f, -0.970295726275996470f,
+ -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+ -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+ -0.933580426497201740f, -0.927183854566787420f,
+ -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+ -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+ -0.874619707139395740f, -0.866025403784438600f,
+ -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+ -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+ -0.798635510047292830f, -0.788010753606722010f,
+ -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+ -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+ -0.707106781186547460f, -0.694658370458997250f,
+ -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+ -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+ -0.601815023152048270f, -0.587785252292473140f,
+ -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+ -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+ -0.484809620246337060f, -0.469471562785890810f,
+ -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+ -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+ -0.358367949545300270f, -0.342020143325668710f,
+ -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+ -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+ -0.224951054343865000f, -0.207911690817759310f,
+ -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+ -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+ -0.087155742747658166f, -0.069756473744125302f,
+ -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+ 0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+ 0.052335956242943828f, 0.069756473744125302f,
+ 0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+ 0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+ 0.190808995376544800f, 0.207911690817759310f,
+ 0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+ 0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+ 0.325568154457156640f, 0.342020143325668710f,
+ 0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+ 0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+ 0.453990499739546750f, 0.469471562785890810f,
+ 0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+ 0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+ 0.573576436351046050f, 0.587785252292473140f,
+ 0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+ 0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+ 0.681998360062498480f, 0.694658370458997250f,
+ 0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+ 0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+ 0.777145961456970790f, 0.788010753606722010f,
+ 0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+ 0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+ 0.857167300702112220f, 0.866025403784438600f,
+ 0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+ 0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+ 0.920504853452440260f, 0.927183854566787420f,
+ 0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+ 0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+ 0.965925826289068310f, 0.970295726275996470f,
+ 0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+ 0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+ 0.992546151641321980f, 0.994521895368273290f,
+ 0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+ 0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+ 0.999847695156391270f, 0.999390827019095760f,
+ 0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+ 0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+ 0.987688340595137660f, 0.984807753012208020f,
+ 0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+ 0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+ 0.956304755963035550f, 0.951056516295153640f,
+ 0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+ 0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+ 0.906307787036650050f, 0.898794046299166930f,
+ 0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+ 0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+ 0.838670567945424050f, 0.829037572555041740f,
+ 0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+ 0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+ 0.754709580222771790f, 0.743144825477394240f,
+ 0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+ 0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+ 0.656059028990507280f, 0.642787609686539470f,
+ 0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+ 0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+ 0.544639035015026860f, 0.529919264233204900f,
+ 0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+ 0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+ 0.422618261740699500f, 0.406736643075800430f,
+ 0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+ 0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+ 0.292371704722737050f, 0.275637355816999660f,
+ 0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+ 0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+ 0.156434465040230980f, 0.139173100960065740f,
+ 0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+ 0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+ 0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ int32_t i; /* Index for reading nearwst output values */
+ float32_t x1 = -179.0f; /* Initial input value */
+ float32_t y0, y1; /* nearest output values */
+ float32_t y2, y3;
+ float32_t fract; /* fractional part of input */
+
+ /* Calculation of fractional part */
+ if(theta > 0.0f)
+ {
+ fract = theta - (float32_t) ((int32_t) theta);
+ }
+ else
+ {
+ fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+ }
+
+ /* index calculation for reading nearest output values */
+ i = (uint32_t) (theta - x1);
+
+ /* Checking min and max index of table */
+ if(i < 0)
+ {
+ i = 0;
+ }
+ else if(i >= 359)
+ {
+ i = 358;
+ }
+
+ /* reading nearest sine output values */
+ y0 = sinTable[i];
+ y1 = sinTable[i + 1u];
+
+ /* reading nearest cosine output values */
+ y2 = cosTable[i];
+ y3 = cosTable[i + 1u];
+
+ y1 = y1 - y0;
+ y3 = y3 - y2;
+
+ y1 = fract * y1;
+ y3 = fract * y3;
+
+ /* Calculation of sine value */
+ *pSinVal = y0 + y1;
+
+ /* Calculation of cosine value */
+ *pCosVal = y2 + y3;
+
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 000000000..370b7b6ef
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,328 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_q31.c
+*
+* Description: Cosine & Sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+* \par
+* Sine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* sinTable[i]= sin((i-180) * PI/180.0);
+* } </pre>
+* Convert above coefficients to fixed point 1.31 format.
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+ 0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+ 0xf06695da,
+ 0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+ 0xe108b40d, 0xdedf047d,
+ 0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+ 0xd00ce422, 0xcdfc85bb,
+ 0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+ 0xc0000000, 0xbe133b7c,
+ 0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+ 0xb1320139, 0xaf726def,
+ 0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+ 0xa3ecac65, 0xa263007d,
+ 0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+ 0x98722192, 0x9726069c,
+ 0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+ 0x8efb92c2, 0x8df37f8b,
+ 0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+ 0x87b826f7, 0x86f93f50,
+ 0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+ 0x82cc0f36, 0x825a0a5b,
+ 0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+ 0x804fd23a, 0x802ce84c,
+ 0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+ 0x804fd23a, 0x807cb130,
+ 0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+ 0x82cc0f36, 0x8347d77b,
+ 0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+ 0x87b826f7, 0x88806fc4,
+ 0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+ 0x8efb92c2, 0x900c7621,
+ 0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+ 0x98722192, 0x99c64fc5,
+ 0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+ 0xa3ecac65, 0xa57d8666,
+ 0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+ 0xb1320139, 0xb2f7b9af,
+ 0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+ 0xc0000000, 0xc1f1c224,
+ 0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+ 0xd00ce422, 0xd220ffc0,
+ 0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+ 0xe108b40d, 0xe334cdc9,
+ 0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+ 0xf29ecfb2, 0xf4d814a4,
+ 0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+ 0x6b2f1d2,
+ 0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+ 0x163a1a7e, 0x186c6ddd,
+ 0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+ 0x278dde6e, 0x29ac37a0,
+ 0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+ 0x381c8bb5, 0x3a1c5c57,
+ 0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+ 0x4793a210, 0x496af3e2,
+ 0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+ 0x55a6125c, 0x574bb8e6,
+ 0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+ 0x620dbe8b, 0x637984d4,
+ 0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+ 0x6c8cd70b, 0x6db7a87a,
+ 0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+ 0x74ef0ebc, 0x75d31a61,
+ 0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+ 0x7b0a9f8d, 0x7ba3751d,
+ 0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+ 0x7ec11aa5, 0x7f0bc097,
+ 0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+ 0x7fffffff, 0x7ffb0260,
+ 0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+ 0x7ec11aa5, 0x7e6c9251,
+ 0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+ 0x7b0a9f8d, 0x7a6831ba,
+ 0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+ 0x74ef0ebc, 0x7401e4c1,
+ 0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+ 0x6c8cd70b, 0x6b598ea3,
+ 0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+ 0x620dbe8b, 0x609a52d3,
+ 0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+ 0x55a6125c, 0x53f9be05,
+ 0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+ 0x4793a210, 0x45b6bb5e,
+ 0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+ 0x381c8bb5, 0x36185aee,
+ 0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+ 0x278dde6e, 0x256c6f9f,
+ 0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+ 0x163a1a7e, 0x14060b68,
+ 0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+ 0x4779632, 0x23be165,
+
+
+};
+
+/**
+* \par
+* Cosine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* cosTable[i]= cos((i-180) * PI/180.0);
+* } </pre>
+* \par
+* Convert above coefficients to fixed point 1.31 format.
+*/
+static const int32_t cosTableQ31[360] = {
+ 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+ 0x80b381ac, 0x80f43f69,
+ 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+ 0x83cd5982, 0x845c8ae3,
+ 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+ 0x89520a1a, 0x8a2ce59f,
+ 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+ 0x9126145f, 0x92485786,
+ 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+ 0x9b2276b0, 0x9c867b2c,
+ 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+ 0xa7156f3c, 0xa8b4471a,
+ 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+ 0xb4c373ee, 0xb6950c1e,
+ 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+ 0xc3e85b18, 0xc5e3a3a9,
+ 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+ 0xd438af17, 0xd653c860,
+ 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+ 0xe5632654, 0xe7939223,
+ 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+ 0xf7123849, 0xf94d0e2e,
+ 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+ 0xb27eb5c,
+ 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+ 0x1a9cd9ac, 0x1ccb3237,
+ 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+ 0x2bc750e9, 0x2ddf0040,
+ 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+ 0x3c17a4e8, 0x3e0e3ddc,
+ 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+ 0x4b3c8c12, 0x4d084651,
+ 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+ 0x58ea90c4, 0x5a82799a,
+ 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+ 0x64dd8950, 0x6639b03b,
+ 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+ 0x6ed9eba1, 0x6ff389df,
+ 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+ 0x76adf5e6, 0x777f903c,
+ 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+ 0x7c32a67e, 0x7cb82885,
+ 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+ 0x7f4c7e54, 0x7f834ed0,
+ 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+ 0x7fec09e3, 0x7fd317b4,
+ 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+ 0x7e0e2e32, 0x7da5f5a5,
+ 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+ 0x79bc384d, 0x7906c0b0,
+ 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+ 0x730baeed, 0x720c8075,
+ 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+ 0x6a1de737, 0x68d9f964,
+ 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+ 0x5f1f5ea1, 0x5d9cff83,
+ 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+ 0x5246dd49, 0x508d9211,
+ 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+ 0x43d464fb, 0x41ecc484,
+ 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+ 0x340ff242, 0x32037a45,
+ 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+ 0x234815ba, 0x2120fb83,
+ 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+ 0x11d06c97, 0xf996a26,
+ 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+ 0xfdc41e9b,
+ 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+ 0xee2f9369, 0xebf9f498,
+ 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+ 0xdcb7ea46, 0xda939061,
+ 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+ 0xcbf00dbe, 0xc9e7a512,
+ 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+ 0xbc2b9b05, 0xba4944a2,
+ 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+ 0xadb922b7, 0xac0641fb,
+ 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+ 0xa0e0a15f, 0x9f65ad2d,
+ 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+ 0x95e218c9, 0x94a6715d,
+ 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+ 0x8cf45113, 0x8bfe1b3f,
+ 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+ 0x8643c7b3, 0x8597ce46,
+ 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+ 0x81f1d1ce, 0x81936daf,
+ 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+ 0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ *
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ *
+ */
+
+
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ q31_t x0; /* Nearest input value */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
+ uint32_t i; /* Index */
+ q31_t oneByXSpacing; /* 1/ xSpacing value */
+ q31_t out; /* temporary variable */
+ uint32_t sign_bits; /* No.of sign bits */
+ uint32_t firstX = 0x80000000; /* First X value */
+
+ /* Calculation of index */
+ i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+ /* Checking min and max index of table */
+ if(i >= 359)
+ {
+ i = 358;
+ }
+
+ /* Calculation of first nearest input value */
+ x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+ /* Reading nearest sine output values from table */
+ y0 = sinTableQ31[i];
+ y1 = sinTableQ31[i + 1u];
+
+ /* Calculation of 1/(x1-x0) */
+ /* (x1-x0) is xSpacing which is fixed value */
+ sign_bits = 8u;
+ oneByXSpacing = 0x5A000000;
+
+ /* Calculation of (theta - x0)/(x1-x0) */
+ out =
+ (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+ /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+ *pSinVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+ /* Reading nearest cosine output values from table */
+ y0 = cosTableQ31[i];
+ y1 = cosTableQ31[i + 1u];
+
+ /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+ *pCosVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 000000000..20a9f3657
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,290 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_f32.c
+*
+* Description: Fast cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup cos Cosine
+ *
+ * Computes the trigonometric cosine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>
+ *
+ * where
+ * <pre>
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ * </pre>
+ * and
+ * <pre>
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ * </pre>
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+
+/**
+* \par
+* <b>Example code for Generation of Cos Table:</b>
+* <pre>
+* tableSize = 256;
+* for(n = -1; n < (tableSize + 2); n++)
+* {
+* cosTable[n+1]= cos(2*pi*n/tableSize);
+* } </pre>
+* where pi value is 3.14159265358979
+*/
+
+static const float32_t cosTable[260] = {
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+ 0.992479562759399410f, 0.989176511764526370f,
+ 0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+ 0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+ 0.949528157711029050f, 0.941544055938720700f,
+ 0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+ 0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+ 0.870086967945098880f, 0.857728600502014160f,
+ 0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+ 0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+ 0.757208824157714840f, 0.740951120853424070f,
+ 0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+ 0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+ 0.615231573581695560f, 0.595699310302734380f,
+ 0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+ 0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+ 0.449611335992813110f, 0.427555084228515630f,
+ 0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+ 0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+ 0.266712754964828490f, 0.242980182170867920f,
+ 0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+ 0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+ 0.073564566671848297f, 0.049067676067352295f,
+ 0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+ -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+ -0.122410677373409270f, -0.146730467677116390f,
+ -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+ -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+ -0.313681751489639280f, -0.336889863014221190f,
+ -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+ -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+ -0.492898195981979370f, -0.514102756977081300f,
+ -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+ -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+ -0.653172850608825680f, -0.671558976173400880f,
+ -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+ -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+ -0.788346409797668460f, -0.803207516670227050f,
+ -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+ -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+ -0.893224298954010010f, -0.903989315032958980f,
+ -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+ -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+ -0.963776051998138430f, -0.970031261444091800f,
+ -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+ -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+ -0.997290432453155520f, -0.998795449733734130f,
+ -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+ -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+ -0.992479562759399410f, -0.989176511764526370f,
+ -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+ -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+ -0.949528157711029050f, -0.941544055938720700f,
+ -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+ -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+ -0.870086967945098880f, -0.857728600502014160f,
+ -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+ -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+ -0.757208824157714840f, -0.740951120853424070f,
+ -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+ -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+ -0.615231573581695560f, -0.595699310302734380f,
+ -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+ -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+ -0.449611335992813110f, -0.427555084228515630f,
+ -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+ -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+ -0.266712754964828490f, -0.242980182170867920f,
+ -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+ -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+ -0.073564566671848297f, -0.049067676067352295f,
+ -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+ 0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+ 0.122410677373409270f, 0.146730467677116390f,
+ 0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+ 0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+ 0.313681751489639280f, 0.336889863014221190f,
+ 0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+ 0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+ 0.492898195981979370f, 0.514102756977081300f,
+ 0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+ 0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+ 0.653172850608825680f, 0.671558976173400880f,
+ 0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+ 0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+ 0.788346409797668460f, 0.803207516670227050f,
+ 0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+ 0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+ 0.893224298954010010f, 0.903989315032958980f,
+ 0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+ 0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+ 0.963776051998138430f, 0.970031261444091800f,
+ 0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+ 0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+ 0.997290432453155520f, 0.998795449733734130f,
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f
+};
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+
+float32_t arm_cos_f32(
+ float32_t x)
+{
+ float32_t cosVal, fract, in;
+ int32_t index;
+ uint32_t tableSize = (uint32_t) TABLE_SIZE;
+ float32_t wa, wb, wc, wd;
+ float32_t a, b, c, d;
+ float32_t *tablePtr;
+ int32_t n;
+ float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+ float32_t oneminusfractby2;
+ float32_t frby2xfrsq, frby6xfrsq;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(x < 0.0f)
+ {
+ n = n - 1;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ index = (uint32_t) (tableSize * in);
+
+ /* fractional value calculation */
+ fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (float32_t *) & cosTable[index];
+
+ /* Read four nearest values of input value from the cos table */
+ a = tablePtr[0];
+ b = tablePtr[1];
+ c = tablePtr[2];
+ d = tablePtr[3];
+
+ /* Cubic interpolation process */
+ fractsq = fract * fract;
+ fractby2 = fract * 0.5f;
+ fractby6 = fract * 0.166666667f;
+ fractby3 = fract * 0.3333333333333f;
+ fractsqby2 = fractsq * 0.5f;
+ frby2xfrsq = (fractby2) * fractsq;
+ frby6xfrsq = (fractby6) * fractsq;
+ oneminusfractby2 = 1.0f - fractby2;
+ wb = fractsqby2 - fractby3;
+ wc = (fractsqby2 + fract);
+ wa = wb - frby6xfrsq;
+ wb = frby2xfrsq - fractsq;
+ cosVal = wa * a;
+ wc = wc - frby2xfrsq;
+ wd = (frby6xfrsq) - fractby6;
+ wb = wb + oneminusfractby2;
+
+ /* Calculate cos value */
+ cosVal = (cosVal + (b * wb)) + ((c * wc) + (d * wd));
+
+ /* Return the output value */
+ return (cosVal);
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 000000000..ffc0929f7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,214 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q15.c
+*
+* Description: Fast cosine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+* \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate cos values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * cosTable[n+1]= cos(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (fixed-point):
+ * (cosTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
+*/
+
+static const q15_t cosTableQ15[259] = {
+ 0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+ 0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+ 0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+ 0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+ 0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+ 0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+ 0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+ 0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+ 0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+ 0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+ 0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+ 0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+ 0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+ 0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+ 0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+ 0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+ 0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+ 0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+ 0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+ 0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+ 0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+ 0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+ 0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+ 0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+ 0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+ 0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+ 0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+ 0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+ 0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+ 0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+ 0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+ 0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+ 0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+ q15_t x)
+{
+ q31_t cosVal; /* Temporary variable for output */
+ q15_t *tablePtr; /* Pointer to table */
+ q15_t in, in2; /* Temporary variables for input */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q15_t a, b, c, d; /* Four nearest output values */
+ q15_t fract, fractCube, fractSquare; /* Variables for fractional value */
+ q15_t oneBy6 = 0x1555; /* Fixed point value of 1/6 */
+ q15_t tableSpacing = TABLE_SPACING_Q15; /* Table spacing */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (int32_t) in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q15_t) index *tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = (q15_t) ((fract * fract) >> 15);
+
+ /* fractCube = fract * fract * fract */
+ fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q15_t *) & cosTableQ15[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+ wa = (q31_t) oneBy6 *fractCube;
+ wa += (q31_t) 0x2AAA *fract;
+ wa = -(wa >> 15);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the cos table */
+ a = *tablePtr++;
+
+ /* cosVal = a * wa */
+ cosVal = a * wa;
+
+ /* Calculation of wb */
+ wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+ /* Read second nearest value of output from the cos table */
+ b = *tablePtr++;
+
+ /* cosVal += b*wb */
+ cosVal += b * wb;
+
+ /* Calculation of wc */
+ wc = -(q31_t) fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the cos table */
+ c = *tablePtr++;
+
+ /* cosVal += c*wc */
+ cosVal += c * wc;
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+ /* Read fourth nearest value of output from the cos table */
+ d = *tablePtr++;
+
+ /* cosVal += d*wd; */
+ cosVal += d * wd;
+
+ /* Convert output value in 1.15(q15) format and saturate */
+ cosVal = __SSAT((cosVal >> 15), 16);
+
+ /* Return the output value in 1.15(q15) format */
+ return ((q15_t) cosVal);
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 000000000..9ae4b5f80
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,249 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q31.c
+*
+* Description: Fast cosine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate cos values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * cosTable[n+1]= cos(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (cosTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+ 0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+ 0x7f0991c4, 0x7e9d55fc,
+ 0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+ 0x798a23b1, 0x78848414,
+ 0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+ 0x6f5f02b2, 0x6dca0d14,
+ 0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+ 0x60ec3830, 0x5ed77c8a,
+ 0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+ 0x4ebfe8a5, 0x4c3fdff4,
+ 0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+ 0x398cdd32, 0x36ba2014,
+ 0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+ 0x2223a4c5, 0x1f19f97b,
+ 0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+ 0x96a9049, 0x647d97c,
+ 0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+ 0xed37ef91,
+ 0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+ 0xd7d946d8, 0xd4e0cb15,
+ 0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+ 0xc0e8b648, 0xbe31e19b,
+ 0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+ 0xac64d510, 0xaa0a5b2e,
+ 0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+ 0x9b1776da, 0x99307ee0,
+ 0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+ 0x8daad37b, 0x8c4a142f,
+ 0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+ 0x84a2fc62, 0x83d60412,
+ 0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+ 0x8058c94c, 0x80277872,
+ 0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+ 0x80f66e3c, 0x8162aa04,
+ 0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+ 0x8675dc4f, 0x877b7bec,
+ 0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+ 0x90a0fd4e, 0x9235f2ec,
+ 0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+ 0x9f13c7d0, 0xa1288376,
+ 0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+ 0xb140175b, 0xb3c0200c,
+ 0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+ 0xc67322ce, 0xc945dfec,
+ 0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+ 0xdddc5b3b, 0xe0e60685,
+ 0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+ 0xf6956fb7, 0xf9b82684,
+ 0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+ 0x12c8106f,
+ 0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+ 0x2826b928, 0x2b1f34eb,
+ 0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+ 0x3f1749b8, 0x41ce1e65,
+ 0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+ 0x539b2af0, 0x55f5a4d2,
+ 0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+ 0x64e88926, 0x66cf8120,
+ 0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+ 0x72552c85, 0x73b5ebd1,
+ 0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+ 0x7b5d039e, 0x7c29fbee,
+ 0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+ 0x7fa736b4, 0x7fd8878e,
+ 0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+ q31_t x)
+{
+ q31_t cosVal, in, in2; /* Temporary variables for input, output */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q31_t a, b, c, d; /* Four nearest output values */
+ q31_t *tablePtr; /* Pointer to table */
+ q31_t fract, fractCube, fractSquare; /* Temporary values for fractional values */
+ q31_t oneBy6 = 0x15555555; /* Fixed point value of 1/6 */
+ q31_t tableSpacing = TABLE_SPACING_Q31; /* Table spacing */
+ q31_t temp; /* Temporary variable for intermediate process */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = ((q31_t) index) * tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+ fractSquare = fractSquare << 1;
+
+ /* fractCube = fract * fract * fract */
+ fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+ fractCube = fractCube << 1;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q31_t *) & cosTableQ31[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+ wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ temp = 0x2AAAAAAA;
+ wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+ wa = -(wa << 1u);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the cos table */
+ a = *tablePtr++;
+
+ /* cosVal = a*wa */
+ cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+ /* q31(1.31) Fixed point value of 1 */
+ temp = 0x7FFFFFFF;
+
+ /* Calculation of wb */
+ wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+ /* Read second nearest value of output from the cos table */
+ b = *tablePtr++;
+
+ /* cosVal += b*wb */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+ /* Calculation of wc */
+ wc = -fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+ /* Read third nearest values of output value from the cos table */
+ c = *tablePtr++;
+
+ /* cosVal += c*wc */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ wd = (wd << 1u);
+
+ /* Read fourth nearest value of output from the cos table */
+ d = *tablePtr++;
+
+ /* cosVal += d*wd; */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+
+ /* convert cosVal in 2.30 format to 1.31 format */
+ return (__QADD(cosVal, cosVal));
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 000000000..038229f06
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,291 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_f32.c
+*
+* Description: Fast sine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup sin Sine
+ *
+ * Computes the trigonometric sine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>
+ *
+ * where
+ * <pre>
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ * </pre>
+ * and
+ * <pre>
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ * </pre>
+ */
+
+/**
+ * @addtogroup sin
+ * @{
+ */
+
+
+/**
+ * \par
+ * Example code for the generation of the floating-point sine table:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]=sin(2*pi*n/tableSize);
+ * }</pre>
+ * \par
+ * where pi value is 3.14159265358979
+ */
+
+static const float32_t sinTable[259] = {
+ -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+ 0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+ 0.122410677373409270f, 0.146730467677116390f,
+ 0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+ 0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+ 0.313681751489639280f, 0.336889863014221190f,
+ 0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+ 0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+ 0.492898195981979370f, 0.514102756977081300f,
+ 0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+ 0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+ 0.653172850608825680f, 0.671558976173400880f,
+ 0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+ 0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+ 0.788346409797668460f, 0.803207516670227050f,
+ 0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+ 0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+ 0.893224298954010010f, 0.903989315032958980f,
+ 0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+ 0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+ 0.963776051998138430f, 0.970031261444091800f,
+ 0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+ 0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+ 0.997290432453155520f, 0.998795449733734130f,
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+ 0.992479562759399410f, 0.989176511764526370f,
+ 0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+ 0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+ 0.949528157711029050f, 0.941544055938720700f,
+ 0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+ 0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+ 0.870086967945098880f, 0.857728600502014160f,
+ 0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+ 0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+ 0.757208824157714840f, 0.740951120853424070f,
+ 0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+ 0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+ 0.615231573581695560f, 0.595699310302734380f,
+ 0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+ 0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+ 0.449611335992813110f, 0.427555084228515630f,
+ 0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+ 0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+ 0.266712754964828490f, 0.242980182170867920f,
+ 0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+ 0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+ 0.073564566671848297f, 0.049067676067352295f,
+ 0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+ -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+ -0.122410677373409270f, -0.146730467677116390f,
+ -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+ -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+ -0.313681751489639280f, -0.336889863014221190f,
+ -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+ -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+ -0.492898195981979370f, -0.514102756977081300f,
+ -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+ -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+ -0.653172850608825680f, -0.671558976173400880f,
+ -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+ -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+ -0.788346409797668460f, -0.803207516670227050f,
+ -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+ -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+ -0.893224298954010010f, -0.903989315032958980f,
+ -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+ -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+ -0.963776051998138430f, -0.970031261444091800f,
+ -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+ -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+ -0.997290432453155520f, -0.998795449733734130f,
+ -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+ -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+ -0.992479562759399410f, -0.989176511764526370f,
+ -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+ -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+ -0.949528157711029050f, -0.941544055938720700f,
+ -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+ -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+ -0.870086967945098880f, -0.857728600502014160f,
+ -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+ -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+ -0.757208824157714840f, -0.740951120853424070f,
+ -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+ -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+ -0.615231573581695560f, -0.595699310302734380f,
+ -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+ -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+ -0.449611335992813110f, -0.427555084228515630f,
+ -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+ -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+ -0.266712754964828490f, -0.242980182170867920f,
+ -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+ -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+ -0.073564566671848297f, -0.049067676067352295f,
+ -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+float32_t arm_sin_f32(
+ float32_t x)
+{
+ float32_t sinVal, fract, in; /* Temporary variables for input, output */
+ int32_t index; /* Index variable */
+ uint32_t tableSize = (uint32_t) TABLE_SIZE; /* Initialise tablesize */
+ float32_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ float32_t a, b, c, d; /* Four nearest output values */
+ float32_t *tablePtr; /* Pointer to table */
+ int32_t n;
+ float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+ float32_t oneminusfractby2;
+ float32_t frby2xfrsq, frby6xfrsq;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(x < 0.0f)
+ {
+ n = n - 1;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ index = (uint32_t) (tableSize * in);
+
+ /* fractional value calculation */
+ fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (float32_t *) & sinTable[index];
+
+ /* Read four nearest values of input value from the sin table */
+ a = tablePtr[0];
+ b = tablePtr[1];
+ c = tablePtr[2];
+ d = tablePtr[3];
+
+ /* Cubic interpolation process */
+ fractsq = fract * fract;
+ fractby2 = fract * 0.5f;
+ fractby6 = fract * 0.166666667f;
+ fractby3 = fract * 0.3333333333333f;
+ fractsqby2 = fractsq * 0.5f;
+ frby2xfrsq = (fractby2) * fractsq;
+ frby6xfrsq = (fractby6) * fractsq;
+ oneminusfractby2 = 1.0f - fractby2;
+ wb = fractsqby2 - fractby3;
+ wc = (fractsqby2 + fract);
+ wa = wb - frby6xfrsq;
+ wb = frby2xfrsq - fractsq;
+ sinVal = wa * a;
+ wc = wc - frby2xfrsq;
+ wd = (frby6xfrsq) - fractby6;
+ wb = wb + oneminusfractby2;
+
+ /* Calculate sin value */
+ sinVal = (sinVal + (b * wb)) + ((c * wc) + (d * wd));
+
+ /* Return the output value */
+ return (sinVal);
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 000000000..6bbacc634
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q15.c
+*
+* Description: Fast sine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+
+/**
+* \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (fixed-point):
+ * (sinTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+*/
+
+static const q15_t sinTableQ15[259] = {
+ 0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+ 0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+ 0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+ 0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+ 0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+ 0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+ 0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+ 0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+ 0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+ 0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+ 0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+ 0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+ 0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+ 0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+ 0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+ 0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+ 0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+ 0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+ 0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+ 0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+ 0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+ 0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+ 0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+ 0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+ 0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+ 0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+ 0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+ 0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+ 0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+ 0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+ 0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+ 0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+ 0xfcdc, 0x0, 0x324
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+ q15_t x)
+{
+ q31_t sinVal; /* Temporary variables output */
+ q15_t *tablePtr; /* Pointer to table */
+ q15_t fract, in, in2; /* Temporary variables for input, output */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q15_t a, b, c, d; /* Four nearest output values */
+ q15_t fractCube, fractSquare; /* Temporary values for fractional value */
+ q15_t oneBy6 = 0x1555; /* Fixed point value of 1/6 */
+ q15_t tableSpacing = TABLE_SPACING_Q15; /* Table spacing */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (int32_t) in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q15_t) ((index) * tableSpacing);
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = (q15_t) ((fract * fract) >> 15);
+
+ /* fractCube = fract * fract * fract */
+ fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q15_t *) & sinTableQ15[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+ wa = (q31_t) oneBy6 *fractCube;
+ wa += (q31_t) 0x2AAA *fract;
+ wa = -(wa >> 15);
+ wa += ((q31_t) fractSquare >> 1u);
+
+ /* Read first nearest value of output from the sin table */
+ a = *tablePtr++;
+
+ /* sinVal = a * wa */
+ sinVal = a * wa;
+
+ /* Calculation of wb */
+ wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+ (((q31_t) fract >> 1u) - 0x7FFF);
+
+ /* Read second nearest value of output from the sin table */
+ b = *tablePtr++;
+
+ /* sinVal += b*wb */
+ sinVal += b * wb;
+
+
+ /* Calculation of wc */
+ wc = -(q31_t) fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the sin table */
+ c = *tablePtr++;
+
+ /* sinVal += c*wc */
+ sinVal += c * wc;
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+ /* Read fourth nearest value of output from the sin table */
+ d = *tablePtr++;
+
+ /* sinVal += d*wd; */
+ sinVal += d * wd;
+
+ /* Convert output value in 1.15(q15) format and saturate */
+ sinVal = __SSAT((sinVal >> 15), 16);
+
+ /* Return the output value in 1.15(q15) format */
+ return ((q15_t) sinVal);
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 000000000..034a3b42c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q31.c
+*
+* Description: Fast sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (sinTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+
+static const q31_t sinTableQ31[259] = {
+ 0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+ 0x12c8106f,
+ 0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+ 0x2826b928, 0x2b1f34eb,
+ 0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+ 0x3f1749b8, 0x41ce1e65,
+ 0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+ 0x539b2af0, 0x55f5a4d2,
+ 0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+ 0x64e88926, 0x66cf8120,
+ 0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+ 0x72552c85, 0x73b5ebd1,
+ 0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+ 0x7b5d039e, 0x7c29fbee,
+ 0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+ 0x7fa736b4, 0x7fd8878e,
+ 0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+ 0x7f0991c4, 0x7e9d55fc,
+ 0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+ 0x798a23b1, 0x78848414,
+ 0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+ 0x6f5f02b2, 0x6dca0d14,
+ 0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+ 0x60ec3830, 0x5ed77c8a,
+ 0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+ 0x4ebfe8a5, 0x4c3fdff4,
+ 0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+ 0x398cdd32, 0x36ba2014,
+ 0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+ 0x2223a4c5, 0x1f19f97b,
+ 0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+ 0x96a9049, 0x647d97c,
+ 0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+ 0xed37ef91,
+ 0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+ 0xd7d946d8, 0xd4e0cb15,
+ 0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+ 0xc0e8b648, 0xbe31e19b,
+ 0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+ 0xac64d510, 0xaa0a5b2e,
+ 0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+ 0x9b1776da, 0x99307ee0,
+ 0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+ 0x8daad37b, 0x8c4a142f,
+ 0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+ 0x84a2fc62, 0x83d60412,
+ 0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+ 0x8058c94c, 0x80277872,
+ 0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+ 0x80f66e3c, 0x8162aa04,
+ 0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+ 0x8675dc4f, 0x877b7bec,
+ 0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+ 0x90a0fd4e, 0x9235f2ec,
+ 0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+ 0x9f13c7d0, 0xa1288376,
+ 0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+ 0xb140175b, 0xb3c0200c,
+ 0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+ 0xc67322ce, 0xc945dfec,
+ 0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+ 0xdddc5b3b, 0xe0e60685,
+ 0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+ 0xf6956fb7, 0xf9b82684,
+ 0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+ q31_t x)
+{
+ q31_t sinVal, in, in2; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q31_t a, b, c, d; /* Four nearest output values */
+ q31_t *tablePtr; /* Pointer to table */
+ q31_t fract, fractCube, fractSquare; /* Temporary values for fractional values */
+ q31_t oneBy6 = 0x15555555; /* Fixed point value of 1/6 */
+ q31_t tableSpacing = TABLE_SPACING_Q31; /* Table spacing */
+ q31_t temp; /* Temporary variable for intermediate process */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (uint32_t) in / (uint32_t) tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q31_t) index *tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+ fractSquare = fractSquare << 1;
+
+ /* fractCube = fract * fract * fract */
+ fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+ fractCube = fractCube << 1;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q31_t *) & sinTableQ31[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+ wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ temp = 0x2AAAAAAA;
+ wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+ wa = -(wa << 1u);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the sin table */
+ a = *tablePtr++;
+
+ /* sinVal = a*wa */
+ sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+ /* q31(1.31) Fixed point value of 1 */
+ temp = 0x7FFFFFFF;
+
+ /* Calculation of wb */
+ wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+ /* Read second nearest value of output from the sin table */
+ b = *tablePtr++;
+
+ /* sinVal += b*wb */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+ /* Calculation of wc */
+ wc = -fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the sin table */
+ c = *tablePtr++;
+
+ /* sinVal += c*wc */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+ /* Calculation of wd */
+ /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+ fractCube = fractCube - fract;
+ wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ wd = (wd << 1u);
+
+ /* Read fourth nearest value of output from the sin table */
+ d = *tablePtr++;
+
+ /* sinVal += d*wd; */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+ /* convert sinVal in 2.30 format to 1.31 format */
+ return (__QADD(sinVal, sinVal));
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 000000000..07b5a90c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q15.c
+*
+* Description: Q15 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut)
+{
+ q15_t number, temp1, var1, signBits1, half;
+ q31_t bits_val1;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 17;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 3.051757812500000e-005f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 16384);
+
+ /* 1st iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 2nd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 3rd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 000000000..7217834a8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q31.c
+*
+* Description: Q31 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut)
+{
+ q31_t number, temp1, bits_val1, var1, signBits1, half;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 1;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 4.6566128731e-010f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 1073741824);
+
+ /* 1st iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 2nd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 3rd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 000000000..dccba7b52
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_init_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the state array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 000000000..f6a4f83ec
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,561 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+ *
+ * This function implements a high precision Biquad cascade filter which operates on
+ * Q31 data values. The filter coefficients are in 1.31 format and the state variables
+ * are in 1.63 format. The double precision state variables reduce quantization noise
+ * in the filter and provide a cleaner output.
+ * These filters are particularly useful when implementing filters in which the
+ * singularities are close to the unit circle. This is common for low pass or high
+ * pass filters with very low cutoff frequencies.
+ *
+ * The function operates on blocks of input and output data
+ * and each call to the function processes <code>blockSize</code> samples through
+ * the filter. <code>pSrc</code> and <code>pDst</code> points to input and output arrays
+ * containing <code>blockSize</code> Q31 values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array .
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code> and each state variable in 1.63 format to improve precision.
+ * The state variables are arranged in the array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values of data in 1.63 format.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ *
+ * \par Init Function
+ * There is also an associated initialization function which performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * For example, to statically initialize the filter instance structure use
+ * <pre>
+ * arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied which is described in detail below.
+ * \par Fixed-Point Behavior
+ * Care must be taken while using Biquad Cascade 32x64 filter function.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Filter coefficients are represented as fractional values and
+ * restricted to lie in the range <code>[-1 +1)</code>.
+ * The processing function has an additional scaling parameter <code>postShift</code>
+ * which allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the Coefficient array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * The second thing to keep in mind is the gain through the filter.
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ * This is described in the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Two related functions are provided in the CMSIS DSP library.
+ * <code>arm_biquad_cascade_df1_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ * <code>arm_biquad_cascade_df1_fast_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = (q31_t) (pState[0]);
+ Xn2 = (q31_t) (pState[1]);
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut = acc_h;
+
+ /* Read the second input into Xn2, to reuse the value */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc += b1 * x[n-1] */
+ acc = (q63_t) Xn *b1;
+
+ /* acc = b0 * x[n] */
+ acc += (q63_t) Xn2 *b0;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn1 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Read the third input into Xn1, to reuse the value */
+ Xn1 = *pIn++;
+
+ /* The result is converted to 1.31 */
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = acc_h;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn1 *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn2 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 2u) = acc_h;
+
+ /* Read the fourth input into Xn, to reuse the value */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 3u) = acc_h;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* update output pointer */
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+// *pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ //*pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+ /**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 000000000..f3002bb3e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,425 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_f32.c
+*
+* Description: Processing function for the
+* floating-point Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+ *
+ * This set of functions implements arbitrary order recursive (IIR) filters.
+ * The filters are implemented as a cascade of second order Biquad sections.
+ * The functions support Q15, Q31 and floating-point data types.
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
+ *
+ * The functions operate on blocks of input and output data and each call to the function
+ * processes <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to the array of input data and
+ * <code>pDst</code> points to the array of output data.
+ * Both arrays contain <code>blockSize</code> values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1 and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Init Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * <b>Scaling of coefficients: </b>
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>
+ * which allow the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the pCoeffs array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * <b>Filter gain: </b>
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * <b>Overflow and saturation: </b>
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ */
+
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = blockSize & 0x3u;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+ /**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 000000000..65b0e41a8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q15.c
+*
+* Description: Fast processing function for the
+* Q15 Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ * The 2.30 accumulator is then shifted by <code>postShift</code> bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q15()</code> to initialize the filter structure.
+ *
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc; /* Accumulator */
+ int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = S->numStages; /* Stage loop counter */
+
+
+
+ do
+ {
+
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+ /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent (numStages - 1) occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 000000000..196047c39
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q31.c
+*
+* Description: Processing function for the
+* Q31 Fast Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q31()</code> to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t acc = 0; /* accumulator */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variables acc ... acc3 hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
+ mult_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the second input */
+ Xn2 = *(pIn + 1u);
+
+ /* Store the output in the destination buffer. */
+ *pOut = Yn2;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn2);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn1);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Read the third input */
+ Xn1 = *(pIn + 2u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = Yn1;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn2);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the forth input */
+ Xn = *(pIn + 3u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 2u) = Yn2;
+ pIn += 4u;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ Xn2 = Xn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Xn1 = Xn */
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 3u) = Yn1;
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc << shift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 000000000..5533f5095
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_f32.c
+*
+* Description: floating-point Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients array.
+ * @param[in] *pState points to the state array.
+ * @return none
+ *
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 000000000..b74734d35
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q15.c
+*
+* Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.
+ * The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4.
+ *
+ * \par
+ * The state variables are stored in the array <code>pState</code>.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 000000000..89b2477fc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q31.c
+*
+* Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 000000000..f891a412a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q15.c
+*
+* Description: Processing function for the
+* Q15 Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then shifted by <code>postShift</code> bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ * Finally, the result is saturated to 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q15()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc_l, acc_h;
+ q63_t acc; /* Accumulator */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+ int32_t uShift = (32 - lShift);
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input wire to the output wire. */
+ /* Subsequent numStages occur in-place in the output wire */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q31_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q31_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q31_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q31_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q31_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 000000000..174398b9d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q31.c
+*
+* Description: Processing function for the
+* Q31 Biquad cascade filter
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q63_t acc; /* accumulator */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t acc_l, acc_h; /* temporary output variables */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn2;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn1;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn1;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn2;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 000000000..1462d51e7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,359 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_f32.c
+*
+* Description: Processing function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes <code>blockSize</code> samples through the filter.
+* <code>pSrc</code> points to the array of input data and
+* <code>pDst</code> points to the array of output data.
+* Both arrays contain <code>blockSize</code> values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* <pre>
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+* </pre>
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* <pre>
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+* </pre>
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* <code>numStages</code> refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+*
+* \par
+* <code>pState</code> points to the state variable array.
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
+* The state variables are arranged in the <code>pState</code> array as:
+* <pre>
+* {d11, d12, d21, d22, ...}
+* </pre>
+* where <code>d1x</code> refers to the state variables for the first Biquad and
+* <code>d2x</code> refers to the state variables for the second Biquad.
+* The state array has a total length of <code>2*numStages</code> values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* <pre>
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* </pre>
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
+* <code>pCoeffs</code> is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1; /* temporary input */
+ float32_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ float32_t Xn2, Xn3, Xn4; /* Input State variables */
+ float32_t acc2, acc3, acc4; /* accumulator */
+
+
+ float32_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3u;
+ while(sample > 0u) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 000000000..a84d095d7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_init_f32.c
+*
+* Description: Initialization function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of <code>2*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 000000000..dd9c95ae7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,647 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_f32.c
+*
+* Description: Convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Conv Convolution
+ *
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * Then the convolution
+ *
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ *
+ * \par
+ * is defined as
+ * \image html ConvolutionEquation.gif
+ * \par
+ * Note that <code>c[n]</code> is of length <code>srcALen + srcBLen - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., srcALen + srcBLen - 2</code>.
+ * <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and
+ * <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>srcALen+srcBLen-1</code> words for the result.
+ *
+ * \par
+ * Conceptually, when two signals <code>a[n]</code> and <code>b[n]</code> are convolved,
+ * the signal <code>b[n]</code> slides over <code>a[n]</code>.
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
+ *
+ * \par
+ * Note that convolution is a commutative operation:
+ *
+ * <pre>
+ * a[n] * b[n] = b[n] * a[n].
+ * </pre>
+ *
+ * \par
+ * This means that switching the A and B arguments to the convolution functions has no effect.
+ *
+ * <b>Fixed-Point Behavior</b>
+ *
+ * \par
+ * Convolution requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px + 3u);
+ px += 4u;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 000000000..339854e4a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_opt_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 000000000..56bce36ca
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1410 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+ q15_t a, b;
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 000000000..b30d32589
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,577 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q31.c
+*
+* Description: Q31 Convolution (fast version).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ *
+ * \par
+ * See <code>arm_conv_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 000000000..ff0b949b8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 000000000..e3dc97ea7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ */
+
+void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 000000000..0ced29916
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,662 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_f32.c
+*
+* Description: Partial convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup PartialConv Partial Convolution
+ *
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ * Each function has two additional arguments.
+ * <code>firstIndex</code> specifies the starting index of the subset of output samples.
+ * <code>numPoints</code> is the number of output samples to compute.
+ * The function computes the output in the range
+ * <code>[firstIndex, ..., firstIndex+numPoints-1]</code>.
+ * The output array <code>pDst</code> contains <code>numPoints</code> values.
+ *
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ * Otherwise the functions return ARM_MATH_SUCCESS.
+ * \note Refer arm_conv_f32() for details on fixed point behavior.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count = 0u, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = (int32_t) check - (int32_t) srcALen;
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + firstIndex;
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc1;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations for inputs */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 000000000..3df1d3f21
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,768 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_opt_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status;
+
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 000000000..42a96ce3e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1478 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+ q15_t a, b;
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 000000000..3b31583f6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,604 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q31.c
+*
+* Description: Fast Q31 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * See <code>arm_conv_partial_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 000000000..412c0eefa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+ acc2 += (q63_t) x20 *y10;
+ acc2 += (q63_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q63_t) x11 *y10;
+ acc1 += (q63_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x21 *y10;
+ acc3 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x20 *y10;
+ acc0 += (q63_t) x21 *y11;
+ acc2 += (q63_t) x10 *y10;
+ acc2 += (q63_t) x11 *y11;
+ acc1 += (q63_t) x21 *y10;
+ acc1 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x11 *y10;
+ acc3 += (q63_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 000000000..8c277c1e6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,807 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ *
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pScr2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+
+ }
+
+ return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t x10, x11, x20, x21; /* Temporary input variables */
+ q15_t y10, y11; /* Temporary input variables */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y10 = *pScr2;
+ y11 = *(pScr2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pScr2 + 2u);
+ y11 = *(pScr2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+
+ pScr1 += 4u;
+ pScr2 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pScr2++;
+ y11 = *pScr2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ return (status);
+
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 000000000..920f8a16f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,779 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+
+arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 000000000..fb97eabfc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,600 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q31.c
+*
+* Description: Partial convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blkCnt */
+
+ blkCnt = blockSize2 / 3;
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += (q63_t) x1 *c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += (q63_t) x2 *c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += (q63_t) x0 *c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += (q63_t) x2 *c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += (q63_t) x0 *c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += (q63_t) x1 *c0;
+
+
+ px += 3u;
+
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 000000000..6eea774ad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2;
+ q15_t in1, in2;
+ q7_t x0, x1, x2, x3, c0, c1;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status;
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q31_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q31_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q31_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q31_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB; /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 000000000..d4daec59e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ blockSize3 = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* input pointer */
+ q15_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 000000000..c5ce68e97
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q31.c
+*
+* Description: Convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum; /* Accumulator */
+ q63_t acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (q31_t *) pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = (q31_t *) pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[3] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* input pointer */
+ q31_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 000000000..ab7b12f30
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,690 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = (srcALen - srcBLen) + 1u;
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* input pointer */
+ q7_t *pIn2 = pSrcB; /* coefficient pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 000000000..317120906
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,739 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_f32.c
+*
+* Description: Correlation of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Corr Correlation
+ *
+ * Correlation is a mathematical operation that is similar to convolution.
+ * As with convolution, correlation uses two signals to produce a third signal.
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
+ * Correlation is commonly used to measure the similarity between two signals.
+ * It has applications in pattern recognition, cryptanalysis, and searching.
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
+ * Fast versions of the Q15 and Q31 functions are also provided.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * The convolution of the two signals is denoted by
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ * In correlation, one of the signals is flipped in time
+ * <pre>
+ * c[n] = a[n] * b[-n]
+ * </pre>
+ *
+ * \par
+ * and this is mathematically defined as
+ * \image html CorrelateEquation.gif
+ * \par
+ * The <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The result <code>c[n]</code> is of length <code>2 * max(srcALen, srcBLen) - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2)</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>2 * max(srcALen, srcBLen) - 1</code> words for the result.
+ *
+ * <b>Note</b>
+ * \par
+ * The <code>pDst</code> should be initialized to all zeros before being used.
+ *
+ * <b>Fixed-Point Behavior</b>
+ * \par
+ * Correlation requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counters */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding has to be done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ //while(j > 0u)
+ //{
+ // /* Zero is stored in the destination buffer */
+ // *pOut++ = 0.0f;
+
+ // /* Decrement the loop counter */
+ // j--;
+ //}
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += *px++ * *py++;
+ /* x[1] * y[srcBLen - 3] */
+ sum += *px++ * *py++;
+ /* x[2] * y[srcBLen - 2] */
+ sum += *px++ * *py++;
+ /* x[3] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += x0 * c0;
+ /* acc1 += x[1] * y[0] */
+ acc1 += x1 * c0;
+ /* acc2 += x[2] * y[0] */
+ acc2 += x2 * c0;
+ /* acc3 += x[3] * y[0] */
+ acc3 += x3 * c0;
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[1] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[1] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[1] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[1] */
+ acc3 += x0 * c0;
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[2] */
+ acc3 += x1 * c0;
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[3] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[3] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[3] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[4] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[4] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[4] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = acc0;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = acc1;
+ pOut += inc;
+
+ *pOut = acc2;
+ pOut += inc;
+
+ *pOut = acc3;
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = sum;
+ else
+ *pDst++ = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 000000000..bd600765a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_opt_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input and coefficient values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 000000000..184492f87
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1319 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ q15_t a, b;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3], x[4] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ a = *(py + 2);
+ b = *(py + 3);
+
+ py += 4u;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px + 1);
+
+ px++;;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ py += 2u;
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 000000000..b86f55080
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,612 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q31.c
+*
+* Description: Fast Q31 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ *
+ * \par
+ * See <code>arm_correlate_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[1] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[3] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[0] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[0] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[0] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 << 1);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc3 << 1);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
index 000000000..bb236d818
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,513 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+
+void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input1 and input2 values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ //pIn1 += srcALen;
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
index 000000000..adaea59d7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ *
+ */
+
+
+
+void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t j, k = 0u, blkCnt; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t outBlockSize; /* loop counter */
+ q15_t x4; /* Temporary input variable */
+ uint32_t tapCnt; /* loop counter */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+
+ /* Copy (srcBLen) samples in scratch buffer */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for second sequence */
+ py = pScratch2;
+
+ /* Initialization of pScr2 pointer */
+ pScr2 = pScratch2;
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 000000000..7f861b35c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,719 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_correlate_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+
+ c0 = (*py);
+
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+ pOut += inc;
+
+ /* Increment the count by 4 as 4 output values are computed */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment count by 1, as one output value is computed */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+ else
+ *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 000000000..53ba335f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q31.c
+*
+* Description: Correlation of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulators */
+ q31_t x0, x1, x2, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[1] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[3] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[0] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[0] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[1] sample */
+ c0 = *(py + 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[1] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[1] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[2] sample */
+ c0 = *(py + 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py += 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 >> 31);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 >> 31);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using correlation but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate correlation for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to correlation equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q31_t) (sum >> 31u);
+ else
+ *pDst++ = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 000000000..f0f7d12ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,790 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function <code>arm_correlate_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t input1, input2; /* temporary variables */
+ q15_t in1, in2; /* temporary variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 4] , y[srcBLen - 3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 4] */
+ /* x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 2] , y[srcBLen - 1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 2] */
+ /* x[3] * y[srcBLen - 1] */
+ sum = __SMLAD(input1, input2, sum);
+
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q31_t) ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *py++;
+ /* Read y[1] sample */
+ c1 = *py++;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] and y[1] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[2] sample */
+ c0 = *py++;
+ /* Read y[3] sample */
+ c1 = *py++;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] and y[3] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *py++;
+
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[4] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+ pOut += inc;
+
+ count += 4u;
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] , y[1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] , y[3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+ else
+ *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 000000000..2c3d82a66
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,524 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_f32.c
+*
+* Description: FIR decimation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
+ *
+ * These functions combine an FIR filter together with a decimator.
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
+ * When decimating by a factor of <code>M</code>, the signal should be prefiltered by a lowpass filter with a normalized
+ * cutoff frequency of <code>1/M</code> in order to prevent aliasing distortion.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
+ * Instead of calculating all of the FIR filter outputs and discarding <code>M-1</code> out of every <code>M</code>, only the
+ * samples output by the decimator are computed.
+ * The functions operate on blocks of input and output data.
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and
+ * <code>pDst</code> points to an array of <code>blockSize/M</code> output values.
+ * In order to have an integer number of output samples <code>blockSize</code>
+ * must always be a multiple of the decimation factor <code>M</code>.
+ *
+ * The library provides separate functions for Q15, Q31 and floating-point data types.
+ *
+ * \par Algorithm:
+ * The FIR portion of the algorithm uses the standard form filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ * where, <code>b[n]</code> are the filter coefficients.
+ * \par
+ * The <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+ * </pre>
+ * where <code>M</code> is the decimation factor; <code>numTaps</code> is the number of filter coefficients in the filter;
+ * <code>pCoeffs</code> is the address of the coefficient buffer;
+ * <code>pState</code> is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulator */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t blkCntN4;
+ float32_t *px0, *px1, *px2, *px3;
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 4;
+ blkCntN4 = outBlockSize - (4 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = 4 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + 4 * S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 000000000..261be56ec
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,598 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q15.c
+*
+* Description: Fast Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_decimate_init_q15()</code> to initialize the filter structure.
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 000000000..623f080a5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q31.c
+*
+* Description: Fast Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_decimate_init_q31()</code> to initialize the filter structure.
+ */
+
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q31_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+ uint32_t blkCntN2;
+ q31_t x1;
+ q31_t acc0, acc1;
+ q31_t *px0, *px1;
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+
+ blkCnt = outBlockSize / 2;
+ blkCntN2 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb);
+
+ /* Read x[n-numTaps-1] for sample 0 sample 1 */
+ x0 = *(px0);
+ x1 = *(px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 1u);
+
+ /* Read x[n-numTaps-2] for sample 0 sample 1 */
+ x0 = *(px0 + 1u);
+ x1 = *(px1 + 1u);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb + 2u);
+
+ /* Read x[n-numTaps-3] for sample 0 sample 1 */
+ x0 = *(px0 + 2u);
+ x1 = *(px1 + 2u);
+ pb += 4u;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb - 1u);
+
+ /* Read x[n-numTaps-4] for sample 0 sample 1 */
+ x0 = *(px0 + 3u);
+ x1 = *(px1 + 3u);
+
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* update state pointers */
+ px0 += 4u;
+ px1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px0++);
+ x1 = *(px1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN2 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 << 1);
+
+ /* Decrement the loop counter */
+ blkCntN2--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 000000000..1bc8ce0d5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,117 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_f32.c
+*
+* Description: Floating-point FIR Decimator initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_f32()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 000000000..3127360c6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q15.c
+*
+* Description: Initialization function for the Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples
+ * to the call <code>arm_fir_decimate_q15()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size of buffer is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 000000000..20eebc7c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q31.c
+*
+* Description: Initialization function for Q31 FIR Decimation filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_q31()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 000000000..cb86bac06
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,696 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q15.c
+*
+* Description: Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_fast_q15()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q31_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /*Store filter output , smlad will return the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+}
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 000000000..8c75e7f63
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q31.c
+*
+* Description: Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q63_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 000000000..f921acb31
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,651 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_f32.c
+*
+* Description: Floating-point FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup FIR Finite Impulse Response (FIR) Filters
+*
+* This set of functions implements Finite Impulse Response (FIR) filters
+* for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided.
+* The functions operate on blocks of input and output data and each call to the function processes
+* <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+* <code>pDst</code> points to input and output arrays containing <code>blockSize</code> values.
+*
+* \par Algorithm:
+* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.
+* Each filter coefficient <code>b[n]</code> is multiplied by a state variable which equals a previous input sample <code>x[n]</code>.
+* <pre>
+* y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+* </pre>
+* \par
+* \image html FIR.gif "Finite Impulse Response filter"
+* \par
+* <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+* Coefficients are stored in time reversed order.
+* \par
+* <pre>
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* </pre>
+* \par
+* <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+* Samples in the state buffer are stored in the following order.
+* \par
+* <pre>
+* {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+* </pre>
+* \par
+* Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code>.
+* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,
+* to be avoided and yields a significant speed improvement.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+* There are separate instance structure declarations for each of the 4 supported data types.
+*
+* \par Initialization Functions
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* The code below statically initializes each of the 4 different data type filter instance structures
+* <pre>
+*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q7 S = {numTaps, pState, pCoeffs};
+* </pre>
+*
+* where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;
+* <code>pCoeffs</code> is the address of the coefficient buffer.
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the FIR filter functions.
+* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+/**
+* @addtogroup FIR
+* @{
+*/
+
+/**
+*
+* @param[in] *S points to an instance of the floating-point FIR filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data.
+* @param[in] blockSize number of samples to process per call.
+* @return none.
+*
+*/
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
+ float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7; /* Temporary product values */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 8 output values simultaneously.
+ * The variables acc0 ... acc7 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 3;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+ acc4 = 0.0f;
+ acc5 = 0.0f;
+ acc6 = 0.0f;
+ acc7 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* This is separated from the others to avoid
+ * a call to __aeabi_memmove which would be slower
+ */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+ x3 = *px++;
+ x4 = *px++;
+ x5 = *px++;
+ x6 = *px++;
+
+ /* Loop unrolling. Process 8 taps at a time. */
+ tapCnt = numTaps >> 3u;
+
+ /* Loop over the number of taps. Unroll by a factor of 8.
+ ** Repeat until we've computed numTaps-8 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x7 = *(px++);
+
+ /* acc0 += b[numTaps-1] * x[n-numTaps] */
+ p0 = x0 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
+ p1 = x1 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
+ p2 = x2 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
+ p3 = x3 * c0;
+
+ /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
+ p4 = x4 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
+ p5 = x5 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
+ p6 = x6 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
+ p7 = x7 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+
+ /* Perform the multiply-accumulate */
+ p0 = x1 * c0;
+ p1 = x2 * c0;
+ p2 = x3 * c0;
+ p3 = x4 * c0;
+ p4 = x5 * c0;
+ p5 = x6 * c0;
+ p6 = x7 * c0;
+ p7 = x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x2 * c0;
+ p1 = x3 * c0;
+ p2 = x4 * c0;
+ p3 = x5 * c0;
+ p4 = x6 * c0;
+ p5 = x7 * c0;
+ p6 = x0 * c0;
+ p7 = x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x3 * c0;
+ p1 = x4 * c0;
+ p2 = x5 * c0;
+ p3 = x6 * c0;
+ p4 = x7 * c0;
+ p5 = x0 * c0;
+ p6 = x1 * c0;
+ p7 = x2 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x3 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x4 * c0;
+ p1 = x5 * c0;
+ p2 = x6 * c0;
+ p3 = x7 * c0;
+ p4 = x0 * c0;
+ p5 = x1 * c0;
+ p6 = x2 * c0;
+ p7 = x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x4 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x5 * c0;
+ p1 = x6 * c0;
+ p2 = x7 * c0;
+ p3 = x0 * c0;
+ p4 = x1 * c0;
+ p5 = x2 * c0;
+ p6 = x3 * c0;
+ p7 = x4 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x5 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x6 * c0;
+ p1 = x7 * c0;
+ p2 = x0 * c0;
+ p3 = x1 * c0;
+ p4 = x2 * c0;
+ p5 = x3 * c0;
+ p6 = x4 * c0;
+ p7 = x5 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x6 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x7 * c0;
+ p1 = x0 * c0;
+ p2 = x1 * c0;
+ p3 = x2 * c0;
+ p4 = x3 * c0;
+ p5 = x4 * c0;
+ p6 = x5 * c0;
+ p7 = x6 * c0;
+
+ tapCnt--;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+ }
+
+ /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+ tapCnt = numTaps % 0x8u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x7 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ p0 = x0 * c0;
+ p1 = x1 * c0;
+ p2 = x2 * c0;
+ p3 = x3 * c0;
+ p4 = x4 * c0;
+ p5 = x5 * c0;
+ p6 = x6 * c0;
+ p7 = x7 * c0;
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+ x3 = x4;
+ x4 = x5;
+ x5 = x6;
+ x6 = x7;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by 8 to process the next group of 8 samples */
+ pState = pState + 8;
+
+ /* The results in the 8 accumulators, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+ *pDst++ = acc4;
+ *pDst++ = acc5;
+ *pDst++ = acc6;
+ *pDst++ = acc7;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x8u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc0;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+/**
+* @} end of FIR group
+*/
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 000000000..e701ed2c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q15.c
+*
+* Description: Q15 Fast FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_init_q15()</code> to initialize the filter structure.
+ */
+
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLADX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 000000000..1ba7e38c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,299 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q31.c
+*
+* Description: Processing function for the Q31 Fast FIR filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_init_q31()</code> to initialize the filter structure.
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *(px++);
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x1, c0);
+ multAcc_32x32_keep32_R(acc1, x2, c0);
+ multAcc_32x32_keep32_R(acc2, x3, c0);
+ multAcc_32x32_keep32_R(acc3, x0, c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x2, c0);
+ multAcc_32x32_keep32_R(acc1, x3, c0);
+ multAcc_32x32_keep32_R(acc2, x0, c0);
+ multAcc_32x32_keep32_R(acc3, x1, c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x3, c0);
+ multAcc_32x32_keep32_R(acc1, x0, c0);
+ multAcc_32x32_keep32_R(acc2, x1, c0);
+ multAcc_32x32_keep32_R(acc3, x2, c0);
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+ *pDst++ = (q31_t) (acc2 << 1);
+ *pDst++ = (q31_t) (acc3 << 1);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 000000000..429c958eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_f32.c
+*
+* Description: Floating-point FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_f32()</code>.
+ */
+
+void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 000000000..279757fca
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q15.c
+*
+* Description: Q15 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize is number of samples processed per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not greater than or equal to 4 and even.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * Note that <code>numTaps</code> must be even and greater than or equal to 4.
+ * To implement an odd length filter simply increase <code>numTaps</code> by 1 and set the last coefficient to zero.
+ * For example, to implement a filter with <code>numTaps=3</code> and coefficients
+ * <pre>
+ * {0.3, -0.8, 0.3}
+ * </pre>
+ * set <code>numTaps=4</code> and use the coefficients:
+ * <pre>
+ * {0.3, -0.8, 0.3, 0}.
+ * </pre>
+ * Similarly, to implement a two point filter
+ * <pre>
+ * {0.3, -0.3}
+ * </pre>
+ * set <code>numTaps=4</code> and use the coefficients:
+ * <pre>
+ * {0.3, -0.3, 0, 0}.
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize</code>, when running on Cortex-M4 and Cortex-M3 and is of length <code>numTaps+blockSize-1</code>, when running on Cortex-M0 where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q15()</code>.
+ */
+
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* The Number of filter coefficients in the filter must be even and at least 4 */
+ if(numTaps & 0x1u)
+ {
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps ) */
+ memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 000000000..2dfc87692
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q31.c
+*
+* Description: Q31 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q31()</code>.
+ */
+
+void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+ memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 000000000..107bfb37f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q7.c
+*
+* Description: Q7 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+/**
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q7()</code>.
+ */
+
+void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize)
+{
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 000000000..9f0cd46f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,581 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_f32.c
+*
+* Description: FIR interpolation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
+ *
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
+ * After upsampling by a factor of <code>L</code>, the signal should be filtered by a lowpass filter with a normalized
+ * cutoff frequency of <code>1/L</code> in order to eliminate high frequency copies of the spectrum.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
+ * The upsampler inserts <code>L-1</code> zeros between each sample.
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.
+ * This leads to an efficient implementation without any wasted effort.
+ * The functions operate on blocks of input and output data.
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and
+ * <code>pDst</code> points to an array of <code>blockSize*L</code> output values.
+ *
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ *
+ * \par Algorithm:
+ * The functions use a polyphase filter structure:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[L] * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+ * y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+ * ...
+ * y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+ * </pre>
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.
+ * With this method the computation is reduced by a factor of <code>1/L</code> when compared to using a standard FIR filter.
+ * \par
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code> and this is checked by the
+ * initialization functions.
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length
+ * <code>phaseLength=numTaps/L</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>blockSize + phaseLength - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+ * </pre>
+ * where <code>L</code> is the interpolation factor; <code>phaseLength=numTaps/L</code> is the
+ * length of each of the shorter FIR filters used internally,
+ * <code>pCoeffs</code> is the address of the coefficient buffer;
+ * <code>pState</code> is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulators */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+ uint32_t blkCntN4;
+ float32_t c1, c2, c3;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 4;
+ blkCntN4 = blockSize - (4 * blkCnt);
+
+ /* Samples loop unrolled by 4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x1 * c1;
+ acc1 += x2 * c1;
+ acc2 += x3 * c1;
+ acc3 += x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x2 * c2;
+ acc1 += x3 * c2;
+ acc2 += x0 * c2;
+ acc3 += x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x3 * c3;
+ acc1 += x0 * c3;
+ acc2 += x1 * c3;
+ acc3 += x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = acc0;
+ *(pDst + S->L) = acc1;
+ *(pDst + 2 * S->L) = acc2;
+ *(pDst + 3 * S->L) = acc3;
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *(ptr1++) * (*ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+
+ float32_t sum; /* Accumulator */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *ptr1++ * *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 000000000..ffcb7e8cf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_f32.c
+*
+* Description: Floating-point FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_f32()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize +
+ ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 000000000..1beeac21c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,120 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q15.c
+*
+* Description: Q15 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q15()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 000000000..cb2ab0441
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q31.c
+*
+* Description: Q31 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q31()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 000000000..836169237
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,508 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q15.c
+*
+* Description: Q15 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q15_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum; /* Accumulator */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = (uint32_t) phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) x0 * c0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result after converting to 1.15 format in the destination buffer */
+ *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (uint32_t) phaseLen - 1u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 000000000..33ecec21d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,504 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q31.c
+*
+* Description: Q31 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by <code>1/(numTaps/L)</code>.
+ * since <code>numTaps/L</code> additions occur per output sample.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q31_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q31_t) (acc0 >> 31);
+ *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+ /* Run the below code for Cortex-M0 */
+
+ q63_t sum; /* Accumulator */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum >> 31);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 000000000..0e9990b15
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_f32.c
+*
+* Description: Processing function for the floating-point FIR Lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
+ *
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure is feedforward and
+ * the net impulse response is finite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.
+ *
+ * \par Algorithm:
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
+ * The following difference equation is implemented:
+ * <pre>
+ * f0[n] = g0[n] = x[n]
+ * fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+ * gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+ * y[n] = fM[n]
+ * </pre>
+ * \par
+ * <code>pCoeffs</code> points to tha array of reflection coefficients of size <code>numStages</code>.
+ * Reflection Coefficients are stored in the following order.
+ * \par
+ * <pre>
+ * {k1, k2, ..., kM}
+ * </pre>
+ * where M is number of stages
+ * \par
+ * <code>pState</code> points to a state array of size <code>numStages</code>.
+ * The state variables (g values) hold previous inputs and are stored in the following order.
+ * <pre>
+ * {g0[n], g1[n], g2[n] ...gM-1[n]}
+ * </pre>
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * <pre>
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+ * </pre>
+ * \par
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* temporary state pointer */
+ float32_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t fcurr1, fnext1, gcurr1, gnext1; /* temporary variables for first sample in loop unrolling */
+ float32_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ float32_t fcurr3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ float32_t fcurr4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ gcurr1 = 0.0f;
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurr1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * fcurr1);
+ gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr3 = *pSrc++;
+ fcurr4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which will be used for next four samples processing */
+ *px++ = fcurr4;
+
+ /* Process third sample for first tap */
+ fnext3 = fcurr3 + ((*pk) * fcurr2);
+ gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+ /* Process fourth sample for first tap */
+ fnext4 = fcurr4 + ((*pk) * fcurr3);
+ gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g2(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g3(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurr1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+ *pDst++ = fcurr3;
+ *pDst++ = fcurr4;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* save f0(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 000000000..0580f4032
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_f32.c
+*
+* Description: Floating-point FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 000000000..cb6a8eadc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q15.c
+*
+* Description: Q15 FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 000000000..51acb790a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q31.c
+*
+* Description: Q31 FIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 000000000..06dfff9cb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q15.c
+*
+* Description: Q15 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* temporary state pointer */
+ q15_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurnt2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ q31_t fcurnt3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ q31_t fcurnt4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+ fcurnt2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurnt1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+ gnext2 = __SSAT(gnext2, 16);
+
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurnt3 = *pSrc++;
+ fcurnt4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which is used for next four samples processing */
+ *px++ = (q15_t) fcurnt4;
+
+ /* Process third sample for first tap */
+ fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ /* Process fourth sample for first tap */
+ fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+ gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2;
+
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurnt1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) fcurnt1;
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt1, 16);
+
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+ /* save f0(n) in state buffer */
+ *px++ = (q15_t) fcurnt;
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = (q15_t) gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt, 16);
+
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 000000000..c0ddf9693
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q31.c
+*
+* Description: Q31 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr1, fnext1, gcurr1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+ q31_t k;
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* f0(n) = x(n) */
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+ gnext2 = fcurr1 + (gnext2 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr2;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext2;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ gnext2 = gnext1 + (gnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+ /* save g1(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 000000000..840507fb7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q15.c
+*
+* Description: Q15 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_fast_q15()</code> for a faster but less precise implementation of this function.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px1; /* Temporary q15 pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = _SIMD32_OFFSET(px1);
+
+ /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+ x1 = _SIMD32_OFFSET(px1 + 1u);
+
+ px1 += 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read state x[n-N-2], x[n-N-3] */
+ x2 = _SIMD32_OFFSET(px1);
+
+ /* Read state x[n-N-3], x[n-N-4] */
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px1 + 2u);
+
+ /* Read state x[n-N-5], x[n-N-6] */
+ x1 = _SIMD32_OFFSET(px1 + 3u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ px1 += 4u;
+
+ tapCnt--;
+
+ }
+
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+ /* Read 2 coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Fetch 4 state variables */
+ x2 = _SIMD32_OFFSET(px1);
+
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ px1 += 2u;
+
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x2, c0, acc2);
+ acc3 = __SMLALD(x3, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1;
+
+ do
+ {
+
+ c0 = *__SIMD32(pb)++;
+ x0 = *__SIMD32(px1)++;
+
+ acc0 = __SMLALD(x0, c0, acc0);
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Copy state values to start of state buffer */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLALDX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0_FAMILY */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of nTaps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ } while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 000000000..dc43626b1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,365 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q31.c
+*
+* Description: Q31 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t x0, x1, x2; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc0, acc1, acc2; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, tapCntN3; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize / 3;
+ blockSize = blockSize - (3 * blkCnt);
+
+ tapCnt = numTaps / 3;
+ tapCntN3 = numTaps - (3 * tapCnt);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy three new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1] */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Loop unrolling. Process 3 taps at a time. */
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-2] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 1u);
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x1 * c0);
+ acc1 += ((q63_t) x2 * c0);
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 2u);
+ x1 = *(px++);
+
+ /* update coefficient pointer */
+ pb += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x2 * c0);
+ acc1 += ((q63_t) x0 * c0);
+ acc2 += ((q63_t) x1 * c0);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+ i = tapCntN3;
+
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 3 to process the next group of 3 samples */
+ pState = pState + 3;
+
+ /* The results in the 3 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 3 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+ *pDst++ = (q31_t) (acc1 >> 31u);
+ *pDst++ = (q31_t) (acc2 >> 31u);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blockSize > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q63_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Length of the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q63_t) * px++ * *pb++;
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 000000000..e7cd81e2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,390 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q7.c
+*
+* Description: Q7 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+ q7_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q7_t c0; /* Temporary variable to hold coefficient value */
+ q7_t *px; /* Temporary pointer for state */
+ q7_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *(px++);
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ acc0 += ((q15_t) x0 * c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ acc1 += ((q15_t) x1 * c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ acc2 += ((q15_t) x2 * c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x1 * c0);
+ acc1 += ((q15_t) x2 * c0);
+ acc2 += ((q15_t) x3 * c0);
+ acc3 += ((q15_t) x0 * c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x2 * c0);
+ acc1 += ((q15_t) x3 * c0);
+ acc2 += ((q15_t) x0 * c0);
+ acc3 += ((q15_t) x1 * c0);
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x3 * c0);
+ acc1 += ((q15_t) x0 * c0);
+ acc2 += ((q15_t) x1 * c0);
+ acc3 += ((q15_t) x2 * c0);
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x0 * c0);
+ acc1 += ((q15_t) x1 * c0);
+ acc2 += ((q15_t) x2 * c0);
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ acc0 = __SSAT((acc0 >> 7u), 8);
+ *pDst++ = acc0;
+ acc1 = __SSAT((acc1 >> 7u), 8);
+ *pDst++ = acc1;
+ acc2 = __SSAT((acc2 >> 7u), 8);
+ *pDst++ = acc2;
+ acc3 = __SSAT((acc3 >> 7u), 8);
+ *pDst++ = acc3;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q15_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.14 format. Convert to 1.7
+ ** Then store the output in the destination buffer. */
+ *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px, *pb; /* Temporary pointers to state and coeff */
+ q31_t acc = 0; /* Accumlator */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ /* Perform filtering upto BlockSize - BlockSize%4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer of type q7 */
+ px = pState;
+
+ /* Initialize coeff pointer of type q7 */
+ pb = pCoeffs;
+
+
+ i = numTaps;
+
+ while(i > 0u)
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q15_t) * px++ * *pb++;
+ i--;
+ }
+
+ /* Store the 1.7 format filter output in destination buffer */
+ *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+ /* Advance the state pointer by 1 to process the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* Copy q7_t data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 000000000..3a3db2c10
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,372 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_f32.c
+*
+* Description: Floating-point sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
+ *
+ * This group of functions implements sparse FIR filters.
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
+ * Sparse filters are used for simulating reflections in communications and audio applications.
+ *
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.
+ * The functions operate on blocks of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> points to input and output arrays respectively containing <code>blockSize</code> values.
+ *
+ * \par Algorithm:
+ * The sparse filter instant structure contains an array of tap indices <code>pTapDelay</code> which specifies the locations of the non-zero coefficients.
+ * This is in addition to the coefficient array <code>b</code>.
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.
+ * <pre>
+ * y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+ * </pre>
+ * \par
+ * \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients"
+ * \par
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>;
+ * <code>pTapDelay</code> points to an array of nonzero indices and is also of size <code>numTaps</code>;
+ * <code>pState</code> points to a state array of size <code>maxDelay + blockSize</code>, where
+ * <code>maxDelay</code> is the largest offset value that is ever used in the <code>pTapDelay</code> array.
+ * Some of the processing functions also require temporary working buffers.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 4 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 4 different data type filter instance structures
+ * <pre>
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q7 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ * </pre>
+ * \par
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Scratch buffer pointer */
+ float32_t *py = pState; /* Temporary pointers for state buffer */
+ float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ float32_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 000000000..fe48f35ad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_f32.c
+*
+* Description: Floating-point sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of samples processed by the <code>arm_fir_sparse_f32()</code> function.
+ */
+
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 000000000..ef50dbffe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q15.c
+*
+* Description: Q15 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of words processed by <code>arm_fir_sparse_q15()</code> function.
+ */
+
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 000000000..3ba24559b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q31.c
+*
+* Description: Q31 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the number of words processed by <code>arm_fir_sparse_q31()</code> function.
+ */
+
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 000000000..205721378
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q7.c
+*
+* Description: Q7 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of samples processed by the <code>arm_fir_sparse_q7()</code> function.
+ */
+
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 000000000..bd363bb56
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q15.c
+*
+* Description: Q15 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
+ * If the accumulator result overflows it will wrap around rather than saturate.
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pIn = pSrc; /* Working pointer for input */
+ q15_t *pOut = pDst; /* Working pointer for output */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary pointers for scratch buffer */
+ q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q15_t *py = pState; /* Temporary pointers for state buffer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = *pScr2++;
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pScr2++;
+
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 000000000..88b7181e2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,375 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q31.c
+*
+* Description: Q31 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
+ * If the accumulator result overflows, it wraps around rather than saturate.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Scratch buffer pointer */
+ q31_t *py = pState; /* Temporary pointers for state buffer */
+ q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q31_t *pOut; /* Destination pointer */
+ q63_t out; /* Temporary output variable */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t in;
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * process 4 output samples at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * process the remaining output samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 000000000..33067b6c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q7.c
+*
+* Description: Q7 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px; /* Scratch buffer pointer */
+ q7_t *py = pState; /* Temporary pointers for state buffer */
+ q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q7_t *pOut = pDst; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q7_t coeff = *pCoeffs++; /* Read the coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q31_t in;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t in1, in2, in3, in4;
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 000000000..8c6c8ef7a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,447 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_f32.c
+*
+* Description: Floating-point IIR Lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
+ *
+ * This set of functions implements lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure has feedforward and
+ * feedback components and the net impulse response is infinite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.
+
+ * \par Algorithm:
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
+ * <pre>
+ * fN(n) = x(n)
+ * fm-1(n) = fm(n) - km * gm-1(n-1) for m = N, N-1, ...1
+ * gm(n) = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1
+ * y(n) = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+ * </pre>
+ * \par
+ * <code>pkCoeffs</code> points to array of reflection coefficients of size <code>numStages</code>.
+ * Reflection coefficients are stored in time-reversed order.
+ * \par
+ * <pre>
+ * {kN, kN-1, ....k1}
+ * </pre>
+ * <code>pvCoeffs</code> points to the array of ladder coefficients of size <code>(numStages+1)</code>.
+ * Ladder coefficients are stored in time-reversed order.
+ * \par
+ * <pre>
+ * {vN, vN-1, ...v0}
+ * </pre>
+ * <code>pState</code> points to a state array of size <code>numStages + blockSize</code>.
+ * The state variables shown in the figure above (the g values) are stored in the <code>pState</code> array.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * <pre>
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ * </pre>
+ * \par
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> points to the state buffer array;
+ * <code>pkCoeffs</code> points to array of the reflection coefficients; <code>pvCoeffs</code> points to the array of ladder coefficients.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fnext1, gcurr1, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+ float32_t k1, k2;
+ float32_t v1, v2, v3, v4;
+ float32_t gcurr2;
+ float32_t fnext2;
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ /* initialise state pointer */
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fnext2 = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0.0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read gN-1(n-1) from state buffer */
+ gcurr1 = *px1;
+
+ /* read reflection coefficient kN */
+ k1 = *pk;
+
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* read ladder coefficient vN */
+ v1 = *pv;
+
+ /* read next reflection coefficient kN-1 */
+ k2 = *(pk + 1u);
+
+ /* Read gN-2(n-1) from state buffer */
+ gcurr2 = *(px1 + 1u);
+
+ /* read next ladder coefficient vN-1 */
+ v2 = *(pv + 1u);
+
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read reflection coefficient kN-2 */
+ k1 = *(pk + 2u);
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Read gN-3(n-1) from state buffer */
+ gcurr1 = *(px1 + 2u);
+
+ /* y(n) += gN(n) * vN */
+ acc += (gnext * v1);
+
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = gcurr2 + (k2 * fnext2);
+
+ /* Read gN-4(n-1) from state buffer */
+ gcurr2 = *(px1 + 3u);
+
+ /* y(n) += gN-1(n) * vN-1 */
+ acc += (gnext * v2);
+
+ /* read reflection coefficient kN-3 */
+ k2 = *(pk + 3u);
+
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read ladder coefficient vN-2 */
+ v3 = *(pv + 2u);
+
+ /* y(n) += gN-2(n) * vN-2 */
+ acc += (gnext * v3);
+
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointer */
+ pk += 4u;
+
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = (fnext2 * k2) + gcurr2;
+
+ /* read next ladder coefficient vN-3 */
+ v4 = *(pv + 3u);
+
+ /* y(n) += gN-4(n) * vN-4 */
+ acc += (gnext * v4);
+
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointers */
+ px1 += 4u;
+ pv += 4u;
+
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr1 = *px1++;
+ /* Process sample for last taps */
+ fnext1 = fnext2 - ((*pk) * gcurr1);
+ gnext = (fnext1 * (*pk++)) + gcurr1;
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fnext2 = fnext1;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext2 * (*pv));
+
+ *px2++ = fnext2;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0.0f;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for numStages */
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - ((*pk) * gcurr);
+ gnext = (fnext * (*pk++)) + gcurr;
+
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ /* Decrementing loop counter */
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext * (*pv));
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 000000000..6538364f9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_f32.c
+*
+* Description: Floating-point IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+ /**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 000000000..55a31289f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q15.c
+*
+* Description: Q15 IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 000000000..84dcabf46
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q31.c
+*
+* Description: Initialization function for the Q31 IIR lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 000000000..9b0ff9869
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q15.c
+*
+* Description: Q15 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurr, fnext, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+ q31_t v; /* Temporary variable for ladder coefficient */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ q15_t v1, v2;
+#endif
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th ...taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 2nd, 6th .. taps */
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-1(n) into state */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-2(n) into state */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-3(n) for the next sample process */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-4(n) for the next sample process */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-3(n) and gN-4(n) */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples for last taps */
+ acc += (q31_t) (((q31_t) gnext * (*pv++)));
+ *px2++ = (q15_t) gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = (numStages >> 2u);
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ stgCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ stgCnt = (numStages) % 0x4u;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - ((gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) ((fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = numStages;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 000000000..978c4a70d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q31.c
+*
+* Description: Q31 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
+ */
+
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q31_t *pState; /* State pointer */
+ q31_t *pStateCurnt; /* State current pointer */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th .. taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-4(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* Output samples for last taps */
+ acc += ((q63_t) gnext * *pv++);
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ };
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext =
+ clip_q63_to_q31(((q63_t) fcurr -
+ ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext =
+ clip_q63_to_q31(((q63_t) gcurr +
+ ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 000000000..cca785fae
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,442 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_f32.c
+*
+* Description: Processing function for the floating-point LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS Least Mean Square (LMS) Filters
+ *
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
+ *
+ * An LMS filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The LMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.
+ * All arrays contain <code>blockSize</code> values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ *
+ * \par
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:
+ * <pre>
+ * e[n] = d[n] - y[n].
+ * </pre>
+ *
+ * \par
+ * After each sample of the error signal is computed, the filter coefficients <code>b[k]</code> are updated on a sample-by-sample basis:
+ * <pre>
+ * b[k] = b[k] + e[n] * mu * x[n-k], for k=0, 1, ..., numTaps-1
+ * </pre>
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+ * arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * </pre>
+ * where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>mu</code> is the step size parameter; and <code>postShift</code> is the shift applied to coefficients.
+ *
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+ * @details
+ * This function operates on floating-point data types.
+ *
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w = 0.0f; /* weight factor */
+
+ e = 0.0f;
+ d = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for the updating filter coefficients */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Weighting factor for the LMS version */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ * start of the state buffer. This prepares the state buffer for the
+ * next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 000000000..05f3416c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,95 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_f32.c
+*
+* Description: Floating-point LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+/**
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_f32()</code>.
+ */
+
+void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 000000000..a49d821b8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q15.c
+*
+* Description: Q15 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 LMS filter.
+* @param[in] *S points to an instance of the Q15 LMS filter structure.
+* @param[in] numTaps number of filter coefficients.
+* @param[in] *pCoeffs points to the coefficient buffer.
+* @param[in] *pState points to the state buffer.
+* @param[in] mu step size that controls filter coefficient updates.
+* @param[in] blockSize number of samples to process.
+* @param[in] postShift bit shift applied to coefficients.
+* @return none.
+*
+* \par Description:
+* <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+* <pre>
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* </pre>
+* The initial filter coefficients serve as a starting point for the adaptive filter.
+* <code>pState</code> points to the array of state variables and size of array is
+* <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of
+* input samples processed by each call to <code>arm_lms_q15()</code>.
+*/
+
+void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 000000000..2519b0d53
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q31.c
+*
+* Description: Q31 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to
+ * <code>arm_lms_q31()</code>.
+ */
+
+void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 000000000..5357ee87e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_f32.c
+*
+* Description: Processing function for the floating-point Normalised LMS.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS_NORM Normalized LMS Filters
+ *
+ * This set of functions implements a commonly used adaptive filter.
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
+ * factor which increases the adaptation rate of the filter.
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ *
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The NLMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.
+ * All arrays contain <code>blockSize</code> values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ *
+ * \par
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:
+ * <pre>
+ * e[n] = d[n] - y[n].
+ * </pre>
+ *
+ * \par
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
+ * <pre>
+ * E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+ * </pre>
+ * The filter coefficients <code>b[k]</code> are then updated on a sample-by-sample basis:
+ * <pre>
+ * b[k] = b[k] + e[n] * (mu/E) * x[n-k], for k=0, 1, ..., numTaps-1
+ * </pre>
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
+ * For Q7, Q15, and Q31 the following fields must also be initialized;
+ * recipTable, postShift
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ d = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCcoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 000000000..070377823
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_f32.c
+*
+* Description: Floating-point NLMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_f32()</code>.
+ */
+
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialise Energy to zero */
+ S->energy = 0.0f;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0.0f;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 000000000..8ed6db428
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q15.c
+*
+* Description: Q15 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to the array of state variables and size of array is
+ * <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed
+ * by each call to <code>arm_lms_norm_q15()</code>.
+ */
+
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q15_t *) armRecipTableQ15;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 000000000..c422f77f2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q31.c
+*
+* Description: Q31 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_q31()</code>.
+ */
+
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q31_t *) armRecipTableQ31;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 000000000..795b03bee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q15.c
+*
+* Description: Q15 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q15 normalized LMS filter.
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* <b>Scaling and Overflow Behavior:</b>
+* \par
+* The function is implemented using a 64-bit internal accumulator.
+* Both coefficients and state variables are represented in 1.15 format and
+* multiplications yield a 2.30 result. The 2.30 intermediate results are
+* accumulated in a 64-bit accumulator in 34.30 format.
+* There is no risk of internal overflow with this approach and the full
+* precision of intermediate multiplications is preserved. After all additions
+* have been performed, the accumulator is truncated to 34.15 format by
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a
+* result in 1.15 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+*
+ */
+
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q31_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0, d = 0; /* error, reference data sample */
+ q15_t w = 0, in; /* weight factor and state */
+ q15_t x0; /* temporary variable to hold input sample */
+ //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+ q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Converting the result to 1.15 format */
+ //acc = __SSAT((acc >> (16u - shift)), 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy (numTaps - 1u) data */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 000000000..223816a04
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q31.c
+*
+* Description: Processing function for the Q31 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q31 normalized LMS filter.
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* <b>Scaling and Overflow Behavior:</b>
+* \par
+* The function is implemented using an internal 64-bit accumulator.
+* The accumulator has a 2.62 format and maintains full precision of the intermediate
+* multiplication results but provides only a single guard bit.
+* Thus, if the accumulator result overflows it wraps around rather than clip.
+* In order to avoid overflows completely the input signal must be scaled down by
+* log2(numTaps) bits. The reference signal should not be scaled down.
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+* and saturated to 1.31 format to yield the final result.
+* The output signal and error signal are in 1.31 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the
+* updation of filter cofficients are saturted.
+*
+*/
+
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0, d = 0; /* error, reference data sample */
+ q31_t w = 0, in; /* weight factor and state */
+ q31_t x0; /* temporary variable to hold input sample */
+// uint32_t shift = 32u - ((uint32_t) S->postShift + 1u); /* Shift to be applied to the output */
+ q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy = (q31_t) ((((q63_t) energy << 32) -
+ (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift = arm_recip_q31(energy + DELTA_Q31,
+ &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy =
+ (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+ //acc = (q31_t) (acc >> shift);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift =
+ arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 000000000..a52a04bf6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q15.c
+*
+* Description: Processing function for the Q15 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ *
+ */
+
+void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t mu = S->mu; /* Adaptive factor */
+ q15_t *px; /* Temporary pointer for state */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0; /* error of data sample */
+ q15_t alpha; /* Intermediate constant for taps update */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t coef; /* Teporary variable for coefficient */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 000000000..0356133df
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q31.c
+*
+* Description: Processing function for the Q31 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clips.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(numTaps) bits.
+ * The reference signal should not be scaled down.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ * and saturated to 1.31 format to yield the final result.
+ * The output signal and error signal are in 1.31 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t mu = S->mu; /* Adaptive factor */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0; /* error of data sample */
+ q31_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-1] * x[n-N-1] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-2] * x[n-N-2] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-3] * x[n-N-3] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Store the result from accumulator into the destination buffer. */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Weighting factor for the LMS version */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb += (coef << 1u);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 000000000..5bb93007b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_f32.c
+*
+* Description: Floating-point matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixAdd Matrix Addition
+ *
+ * Adds two matrices.
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) + (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 000000000..668937648
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q15.c
+*
+* Description: Q15 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop unrolling */
+ blkCnt = (uint32_t) numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) numSamples % 0x4u;
+
+ /* q15 pointers of input and output are initialized */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (uint32_t) numSamples;
+
+
+ /* q15 pointers of input and output are initialized */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 000000000..08f06f08e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q31.c
+*
+* Description: Q31 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Add and saturate */
+ out2 = __QADD(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+ out2 = __QADD(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QADD(inA1, inB1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ *pOut++ = inA1;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 000000000..6932adcba
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_f32.c
+*
+* Description: Floating-point matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ * Initializes the underlying matrix data structure.
+ * The functions set the <code>numRows</code>,
+ * <code>numCols</code>, and <code>pData</code> fields
+ * of the matrix data structure.
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 000000000..2c499b1ce
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q15.c
+*
+* Description: Q15 matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 000000000..5dabc779c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q31.c
+*
+* Description: Q31 matrix initialization.
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 000000000..52d83aa7d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,700 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 1. March 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_inverse_f32.c
+*
+* Description: Floating-point matrix inverse.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations till it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * <code>ARM_MATH_SINGULAR</code>.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns
+ * <code>ARM_MATH_SIZE_MISMATCH</code> if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * <code>ARM_MATH_SINGULAR</code>. Otherwise, the function returns <code>ARM_MATH_SUCCESS</code>.
+ */
+
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
+ float32_t *pInT3, *pInT4; /* Temporary output data matrix pointer */
+ float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
+ uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
+ uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t maxC; /* maximum value in the column */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t Xchg, in = 0.0f, in1; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _
+ * | a11 a12 | 1 0 | | X11 X12 |
+ * | | | = | |
+ * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for column i is the greatest of the column.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is not the most significant of the coluimns, exchange that row with a row
+ * below it that does contain the most significant value in column i. If the most
+ * significant value of the column is zero, then an inverse to that matrix does not exist.
+ * The most significant value of the column is the absolut maximum.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+ * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pInT2 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pInT2++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pInT3 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Grab the most significant value from column l */
+ maxC = 0;
+ for (i = 0; i < numRows; i++)
+ {
+ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+ pInT1 += numCols;
+ }
+
+ /* Update the status if the matrix is singular */
+ if(maxC == 0.0f)
+ {
+ status = ARM_MATH_SINGULAR;
+ break;
+ }
+
+ /* Restore pInT1 */
+ pInT1 -= numRows * numCols;
+
+ /* Check if the pivot element is the most significant of the column */
+ if( (in > 0.0f ? in : -in) != maxC)
+ {
+ /* Loop over the number rows present below */
+ i = numRows - (l + 1u);
+
+ while(i > 0u)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pInT4 = pInT3 + (numCols * k);
+
+ /* Look for the most significant element to
+ * replace in the rows below */
+ if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = numCols - l;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the destination matrix */
+ Xchg = *pInT4;
+ *pInT4++ = *pInT3;
+ *pInT3++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+
+ break;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *pPivotRowIn;
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ in1 = *pInT1;
+ *pInT1++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ in1 = *pInT2;
+ *pInT2++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ /* index used to check for pivot element */
+ i = 0u;
+
+ /* Loop over number of rows */
+ /* to be replaced by the sum of that row and a multiple of row i */
+ k = numRows;
+
+ while(k > 0u)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT1;
+ *pInT1++ = in1 - (in * *pPRT_in++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT2;
+ *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ }
+
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+
+ /* Decrement the loop counter */
+ k--;
+
+ /* Increment the pivot index */
+ i++;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t Xchg, in = 0.0f; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _ _ _ _ _
+ * | | a11 a12 | | | 1 0 | | | X11 X12 |
+ * | | | | | | | = | |
+ * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for row i is zero.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is zero, exchange that row with a row below it that does not
+ * contain a zero in column i. If this is not possible, then an inverse
+ * to that matrix does not exist.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+ * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pInT2 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pInT2++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+ //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pInT3 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is zero */
+ if(*pInT1 == 0.0f)
+ {
+ /* Loop over the number rows present below */
+ for (i = (l + 1u); i < numRows; i++)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pInT4 = pInT3 + (numCols * k);
+
+ /* Check if there is a non zero pivot element to
+ * replace in the rows below */
+ if(*pInT2 != 0.0f)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+ }
+
+ for (j = 0u; j < numCols; j++)
+ {
+ Xchg = *pInT4;
+ *pInT4++ = *pInT3;
+ *pInT3++ = Xchg;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+
+ break;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *(pIn + (l * numCols));
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ *pInT1 = *pInT1 / in;
+ pInT1++;
+ }
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ *pInT2 = *pInT2 / in;
+ pInT2++;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ for (i = 0u; i < numRows; i++)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT1 = *pInT1 - (in * *pPRT_in++);
+ pInT1++;
+ }
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT2 = *pInT2 - (in * *pPRT_pDst++);
+ pInT2++;
+ }
+
+ }
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+ }
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+ }
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 000000000..bae73f146
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_f32.c
+*
+* Description: Floating-point matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixMult Matrix Multiplication
+ *
+ * Multiplies two matrices.
+ *
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"
+
+ * Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an <code>M x N</code> matrix with an <code>N x P</code> matrix results
+ * in an <code>M x P</code> matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * <code>pSrcA</code> and <code>pSrcB</code> are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of <code>pSrcA</code> and <code>pSrcB</code>.
+ */
+
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ float32_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t in1, in2, in3, in4;
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2u;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[0];
+ in2 = pIn1[1];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[2];
+ in2 = pIn1[3];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+ pIn1 += 4u;
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 000000000..cf587ef16
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q15.c
+*
+* Description: Q15 matrix multiplication (fast variant)
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.15 x 1.15 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 16 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See <code>arm_mat_mult_q15()</code> for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState)
+{
+ q31_t sum; /* accumulator */
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t inA1, inA2, inB1, inB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inA2, inB1, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ inA1 = *__SIMD32(pInA)++;
+ inB1 = *__SIMD32(pInB)++;
+ inA2 = *__SIMD32(pInA)++;
+ inB2 = *__SIMD32(pInB)++;
+
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+#else
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += (q31_t) (*pInA++) * (*pInB++);
+
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (sum >> 15);
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 000000000..1c5f41434
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q31.c
+*
+* Description: Q31 matrix multiplication (fast variant).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.31 x 1.31 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See <code>arm_mat_mult_q31()</code> for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+// q31_t *pSrcB = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q31_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ inB1 = *pIn2;
+ pIn2 += numColsB;
+
+ inA1 = pIn1[0];
+ inA2 = pIn1[1];
+
+ inB2 = *pIn2;
+ pIn2 += numColsB;
+
+ inB3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
+
+ inA3 = pIn1[2];
+ inA4 = pIn1[3];
+
+ inB4 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
+
+ pIn1 += 4u;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+ *px++ = sum << 1;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 000000000..1e112ab77
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,469 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q15.c
+*
+* Description: Q15 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_mat_mult_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState CMSIS_UNUSED)
+{
+ q63_t sum; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inB1, inA2, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA1 = *__SIMD32(pInA)++;
+ pSourceB1 = *__SIMD32(pInB)++;
+
+ pSourceA2 = *__SIMD32(pInA)++;
+ pSourceB2 = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+ sum = __SMLALD(pSourceA1, pSourceB1, sum);
+ sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ /* Multiply and Accumlates */
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process remaining column samples */
+ colCnt = numColsA & 3u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pInA++ * *pInB++;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (__SSAT((sum >> 15), 16));
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q31_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+ /* Saturate and store the result in the destination buffer */
+ *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+ /* Update the pointer pSrcA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 000000000..218b7f53f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,294 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q31.c
+*
+* Description: Q31 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_mat_mult_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q63_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ b0 = *pIn2;
+ pIn2 += numColsB;
+
+ a0 = *pIn1++;
+ a1 = *pIn1++;
+
+ b1 = *pIn2;
+ pIn2 += numColsB;
+ b2 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a0 *b0;
+ sum += (q63_t) a1 *b1;
+
+ a2 = *pIn1++;
+ a3 = *pIn1++;
+
+ b3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a2 *b2;
+ sum += (q63_t) a3 *b3;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) (sum >> 31);
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = (pSrcB->pData) + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) (sum >> 31);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 000000000..a242c91c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_f32.c
+*
+* Description: Multiplies a floating-point matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixScale Matrix Scale
+ *
+ * Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the
+ * matrix by the scalar. For example:
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"
+ *
+ * The function checks to make sure that the input and output matrices are of the same size.
+ *
+ * In the fixed-point Q15 and Q31 functions, <code>scale</code> is represented by
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The overall scale factor applied to the fixed-point data is
+ * <pre>
+ * scale = scaleFract * 2^shift.
+ * </pre>
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ */
+
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t in1, in2, in3, in4; /* temporary variables */
+ float32_t out1, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* Scaling and results are stored in the destination buffer. */
+ in1 = pIn[0];
+ in2 = pIn[1];
+ in3 = pIn[2];
+ in4 = pIn[3];
+
+ out1 = in1 * scale;
+ out2 = in2 * scale;
+ out3 = in3 * scale;
+ out4 = in4 * scale;
+
+
+ pOut[0] = out1;
+ pOut[1] = out2;
+ pOut[2] = out3;
+ pOut[3] = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* The results are stored in the destination buffer. */
+ *pOut++ = (*pIn++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 000000000..bb28cfc11
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q15.c
+*
+* Description: Multiplies a Q15 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = 15 - shift; /* total shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q15_t in1, in2, in3, in4;
+ q31_t out1, out2, out3, out4;
+ q31_t inA1, inA2;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ /* Reading 2 inputs from memory */
+ inA1 = _SIMD32_OFFSET(pIn);
+ inA2 = _SIMD32_OFFSET(pIn + 2);
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ out1 = out1 >> totShift;
+ inA1 = _SIMD32_OFFSET(pIn + 4);
+ out2 = out2 >> totShift;
+ inA2 = _SIMD32_OFFSET(pIn + 6);
+ out3 = out3 >> totShift;
+ out4 = out4 >> totShift;
+
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+ _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ *pOut++ =
+ (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 000000000..6b2b1046b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q31.c
+*
+* Description: Multiplies a Q31 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = shift + 1; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+ q31_t in1, in2, out1; /* temporary variabels */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in3, in4, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Read values from input */
+ in1 = *pIn;
+ in2 = *(pIn + 1);
+ in3 = *(pIn + 2);
+ in4 = *(pIn + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << totShift;
+ out2 = in2 << totShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> totShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << totShift;
+ out4 = in4 << totShift;
+
+ *pOut = out1;
+ *(pOut + 1) = out2;
+
+ if(in3 != (out3 >> totShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> totShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+ *(pOut + 2) = out3;
+ *(pOut + 3) = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ in1 = *pIn++;
+
+ in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+ out1 = in2 << totShift;
+
+ if(in2 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pOut++ = out1;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 000000000..0b83133ca
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_f32.c
+*
+* Description: Floating-point matrix subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixSub Matrix Subtraction
+ *
+ * Subtract two matrices.
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) - (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 000000000..ff7c30432
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q15.c
+*
+* Description: Q15 Matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Apply loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 000000000..c2edef1eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q31.c
+*
+* Description: Q31 matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next samples */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QSUB(inA1, inB1);
+
+ *pOut++ = inA1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 000000000..4cd968ae1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,218 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_f32.c
+*
+* Description: Floating-point matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @defgroup MatrixTrans Matrix Transpose
+ *
+ * Tranposes a matrix.
+ * Transposing an <code>M x N</code> matrix flips it around the center diagonal and results in an <code>N x M</code> matrix.
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of rows */
+ uint16_t nColumns = pSrc->numCols; /* number of columns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Loop Unrolling */
+ blkCnt = nColumns >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u) /* column loop */
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u); /* row loop end */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 000000000..ee4eea605
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q15.c
+*
+* Description: Q15 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+ uint16_t col, row = nRows, i = 0u; /* row and column loop counters */
+ arm_status status; /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* variable to hold temporary output */
+
+#else
+
+ q15_t in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = nColumns >> 2u;
+
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pSrcA)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in = *__SIMD32(pSrcA)++;
+
+#else
+
+ in = *__SIMD32(pSrcA)++;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ col = nColumns % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *pOut = *pSrcA++;
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 000000000..636eb45eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q31.c
+*
+* Description: Q31 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ blkCnt = nColumns >> 2u;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ }
+ while(row > 0u); /* row loop end */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 000000000..eb19ebbc1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_f32.c
+*
+* Description: Maximum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Max Maximum
+ *
+ * Computes the maximum value of an array of data.
+ * The function returns both the maximum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 000000000..e4a90ef44
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q15.c
+*
+* Description: Maximum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 000000000..d1bb6cad5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q31.c
+*
+* Description: Maximum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 000000000..c9bcc645d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q7.c
+*
+* Description: Maximum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q7_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 000000000..cb36be661
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_f32.c
+*
+* Description: Mean value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup mean Mean
+ *
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ */
+
+
+void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = sum / (float32_t) blockSize;
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 000000000..e599287bd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q15.c
+*
+* Description: Mean value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.15 format and is accumulated in a 32-bit
+ * accumulator in 17.15 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.
+ *
+ */
+
+
+void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q15_t) (sum / blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 000000000..5d41bde26
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q31.c
+*
+* Description: Mean value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *\par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format and is accumulated in a 64-bit
+ * accumulator in 33.31 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.
+ *
+ */
+
+
+void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 000000000..b71145fe5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q7.c
+*
+* Description: Mean value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format and is accumulated in a 32-bit
+ * accumulator in 25.7 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.
+ *
+ */
+
+
+void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+
+ sum += ((in << 24) >> 24);
+ sum += ((in << 16) >> 24);
+ sum += ((in << 8) >> 24);
+ sum += (in >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 000000000..61af82686
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_f32.c
+*
+* Description: Minimum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Min Minimum
+ *
+ * Computes the minimum value of an array of data.
+ * The function returns both the minimum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 000000000..a31ca72bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q15.c
+*
+* Description: Minimum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 000000000..fe0a5131c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q31.c
+*
+* Description: Minimum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 000000000..335aee702
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q7.c
+*
+* Description: Minimum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 000000000..464265e16
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_f32.c
+*
+* Description: Sum of the squares of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup power Power
+ *
+ * Calculates the sum of the squares of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result to the destination */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 000000000..9005e3d97
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q15.c
+*
+* Description: Sum of the squares of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 34.30 format.
+ *
+ */
+
+void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in32; /* Temporary variable to store input value */
+ q15_t in16; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in16 = *pSrc++;
+ sum = __SMLALD(in16, in16, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the results in 34.30 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 000000000..344a3a369
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q31.c
+*
+* Description: Sum of the squares of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format.
+ * Intermediate multiplication yields a 2.62 format, and this
+ * result is truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 16.48 format.
+ *
+ */
+
+void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ q31_t in;
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the results in 16.48 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 000000000..872e36b4c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q7.c
+*
+* Description: Sum of the squares of the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format.
+ * Intermediate multiplication yields a 2.14 format, and this
+ * result is added without saturation to an accumulator in 18.14 format.
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 18.14 format.
+ *
+ */
+
+void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ q7_t in; /* Temporary variable to store input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1; /* Temporary variable to store packed input */
+ q31_t in1, in2; /* Temporary variables to store input */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading two inputs of pSrc vector and packing */
+ input1 = *__SIMD32(pSrc)++;
+
+ in1 = __SXTB16(__ROR(input1, 8));
+ in2 = __SXTB16(input1);
+
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* calculate power and accumulate to accumulator */
+ sum = __SMLAD(in1, in1, sum);
+ sum = __SMLAD(in2, in2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in 18.14 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 000000000..b3f67db03
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_f32.c
+*
+* Description: Root mean square value of an array of F32 type
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup RMS Root mean square (RMS)
+ *
+ *
+ * Calculates the Root Mean Sqaure of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ */
+
+void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Accumulator */
+ float32_t in; /* Tempoprary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Rms and store the result in the destination */
+ arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 000000000..5de2f2a8a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q15.c
+*
+* Description: Root Mean Square of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* temporary variable to store the input value */
+ q15_t in1; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in1 = *pSrc++;
+ sum = __SMLALD(in1, in1, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ in = (q31_t)(sum >> 15);
+
+ in1 = __SSAT(in / blockSize, 16);
+
+ /* Store the result in the destination */
+ arm_sqrt_q15(in1, pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* temporary variable to store the input value */
+ q31_t tmp; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ tmp = (q31_t)(sum >> 15);
+
+ in = __SSAT(tmp / blockSize, 16);
+
+ /* Store the result in the destination */
+ arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 000000000..0a8bf1f73
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q31.c
+*
+* Description: Root Mean Square of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows, it wraps around and distorts the result.
+ * In order to avoid overflows completely, the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+ q31_t in; /* Temporary variable to store the input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ /* read two samples from source buffer */
+ in1 = pSrc[0];
+ in2 = pSrc[1];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in1 *in1;
+ sum += (q63_t) in2 *in2;
+
+ /* read two samples from source buffer */
+ in3 = pSrc[2];
+ in4 = pSrc[3];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in3 *in3;
+ sum += (q63_t) in4 *in4;
+
+
+ /* update source buffer to process next samples */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += (q63_t) in *in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+
+ sum = __SSAT(sum >> 31, 31);
+
+
+ /* Compute Rms and store the result in the destination vector */
+ arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 000000000..135eb74d6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_f32.c
+*
+* Description: Standard deviation of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup STD Standard deviation
+ *
+ * Calculates the standard deviation of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = sqrt((sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1))
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t squareOfSum; /* Square of Sum */
+ float32_t var; /* Temporary varaince storage */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 000000000..b6c2d13d2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q15.c
+*
+* Description: Standard deviation of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q15_t mean; /* mean */
+ uint32_t blkCnt; /* loop counter */
+ q15_t t; /* Temporary variable */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* input value */
+ q15_t in1; /* input value */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+ sum += in1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+ /* Compute mean of all input values */
+ t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+ mean = (q15_t) __SSAT(sum, 16u);
+
+ /* Compute square of mean */
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* mean of the squares minus the square of the mean. */
+ in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(in1, pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t in; /* input value */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+ /* Compute mean of all input values */
+ mean = (q15_t) __SSAT(sum, 16u);
+
+ /* Compute square of mean of the input samples
+ * and then store the result in a temporary variable, squareOfMean.*/
+ t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* mean of the squares minus the square of the mean. */
+ in = (q15_t) (meanOfSquares - squareOfMean);
+
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 000000000..ae830e772
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q31.c
+*
+* Description: Standard deviation of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t mean; /* mean */
+ q31_t in; /* input value */
+ q31_t t; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ sumOfSquares = (sumOfSquares >> 31);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+ sumOfSquares = (sumOfSquares >> 31);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute mean of all input values */
+ t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+ mean = (q31_t) (sum);
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 000000000..e3e46ff01
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_f32.c
+*
+* Description: Variance of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup variance Variance
+ *
+ * Calculates the variance of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = (sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1)
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t squareOfSum; /* Square of Sum */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 000000000..695f08e50
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q15.c
+*
+* Description: Variance of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+
+void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* Mean of square and square of mean */
+ q15_t mean; /* mean */
+ uint32_t blkCnt; /* loop counter */
+ q15_t t; /* Temporary variable */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* Input variable */
+ q15_t in1; /* Temporary variable */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sum += in1;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary variable */
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute mean of all input values */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+ mean = __SSAT(sum, 16u);
+
+ /* Compute square of mean */
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 000000000..3d6492ab0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q31.c
+*
+* Description: Variance of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0, sumSquare = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t mean; /* mean */
+ q31_t in; /* input value */
+ q31_t t; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q63_t sumSquare1 = 0; /* Accumulator */
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ /* read input samples from source buffer */
+ in1 = pSrc[0];
+ in2 = pSrc[1];
+
+ /* calculate sum of inputs */
+ sum += in1;
+ /* calculate sum of squares */
+ sumSquare += ((q63_t) (in1) * (in1));
+ in3 = pSrc[2];
+ sum += in2;
+ sumSquare1 += ((q63_t) (in2) * (in2));
+ in4 = pSrc[3];
+ sum += in3;
+ sumSquare += ((q63_t) (in3) * (in3));
+ sum += in4;
+ sumSquare1 += ((q63_t) (in4) * (in4));
+
+ /* update input pointer to process next samples */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* add two accumulators */
+ sumSquare = sumSquare + sumSquare1;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sumSquare += ((q63_t) (in) * (in));
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ sumSquare = (sumSquare >> 31);
+ meanOfSquares = (q31_t) ((sumSquare * t) >> 30);
+
+ /* Compute mean of all input values */
+ t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+ mean = (q31_t) (sum);
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 000000000..f50cb532f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_f32.c
+*
+* Description: Copies the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup copy Vector Copy
+ *
+ * Copies sample by sample from source vector to destination vector.
+ *
+ * <pre>
+ * pDst[n] = pSrc[n]; 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 000000000..b60e68ac1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q15.c
+*
+* Description: Copies the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Read two inputs */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 000000000..3654d3d30
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q31.c
+*
+* Description: Copies the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the values in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 000000000..303286fe5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q7.c
+*
+* Description: Copies the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ /* 4 samples are copied and stored at a time using SIMD */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 000000000..3f5f86e0e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_f32.c
+*
+* Description: Fills a constant value into a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup Fill Vector Fill
+ *
+ * Fills the destination vector with a constant value.
+ *
+ * <pre>
+ * pDst[n] = value; 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1 = value;
+ float32_t in2 = value;
+ float32_t in3 = value;
+ float32_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 000000000..5c73cf627
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q15.c
+*
+* Description: Fills a constant value into a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PKHBT(value, value, 16u);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 000000000..2e8c133ae
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q31.c
+*
+* Description: Fills a constant value into a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1 = value;
+ q31_t in2 = value;
+ q31_t in3 = value;
+ q31_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 000000000..376b7a588
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q7.c
+*
+* Description: Fills a constant value into a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PACKq7(value, value, value, value);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 000000000..cfa5ec651
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q15.c
+*
+* Description: Converts the elements of the floating-point vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * <pre>
+ * pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
+ * </pre>
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ *
+ */
+
+
+void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 000000000..a39fbe7e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q31.c
+*
+* Description: Converts the elements of the floating-point vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup float_to_x Convert 32-bit floating point value
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
+ * </pre>
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ *
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 32768 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 000000000..2820af7e6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q7.c
+*
+* Description: Converts the elements of the floating-point vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * <pre>
+ * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
+ * </pre>
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 000000000..2310b909d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_float.c
+*
+* Description: Converts the elements of the Q15 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q15_to_x Convert 16-bit Integer value
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 000000000..2d5c86e22
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q31.c
+*
+* Description: Converts the elements of the Q15 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* extract lower 16 bits to 32 bit result */
+ out1 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out2 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out3 = in2 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out4 = in2 & 0xFFFF0000;
+
+#else
+
+ /* extract upper 16 bits to 32 bit result */
+ out1 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out2 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out3 = in2 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out4 = in2 << 16u;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = out1;
+ *pDst++ = out2;
+ *pDst++ = out3;
+ *pDst++ = out4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 000000000..d26122150
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q7.c
+*
+* Description: Converts the elements of the Q15 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in1, in2, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* rotate packed value by 24 */
+ out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+ /* anding with 0xff00ff00 to get two 8 bit values */
+ out1 = out1 & 0xFF00FF00;
+ /* anding with 0x00ff00ff to get two 8 bit values */
+ out2 = out2 & 0x00FF00FF;
+
+ /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+ out1 = out1 | out2;
+
+ /* store 4 samples at a time to destiantion buffer */
+ *__SIMD32(pDst)++ = out1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 000000000..4f60511c2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_float.c
+*
+* Description: Converts the elements of the Q31 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q31_to_x Convert 32-bit Integer value
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 000000000..a2b9fde74
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q15.c
+*
+* Description: Converts the elements of the Q31 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHTB(in3, in4, 16);
+
+#endif // #ifdef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 000000000..c2f9b9a04
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q7.c
+*
+* Description: Converts the elements of the Q31 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q7_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ out1 = (q7_t) (in1 >> 24);
+ out2 = (q7_t) (in2 >> 24);
+ out3 = (q7_t) (in3 >> 24);
+ out4 = (q7_t) (in4 >> 24);
+
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 000000000..3b7f586a5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_float.c
+*
+* Description: Converts the elements of the Q7 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q7_to_x Convert 8-bit Integer value
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 000000000..444321c60
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q15.c
+*
+* Description: Converts the elements of the Q7 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ q31_t in;
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+ /* rotatate in by 8 and extend two q7_t values to q15_t values */
+ in1 = __SXTB16(__ROR(in, 8));
+
+ /* extend remainig two q7_t values to q15_t values */
+ in2 = __SXTB16(in);
+
+ in1 = in1 << 8u;
+ in2 = in2 << 8u;
+
+ in1 = in1 & 0xFF00FF00;
+ in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out2 = __PKHTB(in1, in2, 16);
+ out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) * pIn++ << 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 000000000..fefd78a01
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q31.c
+*
+* Description: Converts the elements of the Q7 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (in & 0xFF000000);
+
+#else
+
+ *pDst++ = (in & 0xFF000000);
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 24;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c
new file mode 100644
index 000000000..522f5a676
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c
@@ -0,0 +1,460 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param float* Pointer to the reference buffer
+ * @param float* Pointer to the test buffer
+ * @param uint32_t total number of samples
+ * @return float SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q15_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q15_t* Pointer to Ref buffer
+ * @param q15_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff;
+ uint32_t diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if(diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q31_t* Pointer to Ref buffer
+ * @param q31_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff;
+ uint32_t diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if(diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param uint32_t number of additions
+ * @return none
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Converts Q15 to floating-point
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t * pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param uint32_t number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param pIn input buffer
+ * @param numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if(pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c
new file mode 100644
index 000000000..7e1795db3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,242 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_bitreversal.c
+*
+* Description: This file has common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftSize length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+* @param[in] *pBitRevTab points to the bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ uint16_t fftLenBy2, fftLenBy2p1;
+ uint16_t i, j;
+ float32_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftSize >> 1u;
+ fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
+
+
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+* @param[in] *pBitRevTab points to bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTable)
+{
+ uint32_t fftLenBy2, fftLenBy2p1, i, j;
+ q31_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTable;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTable += bitRevFactor;
+ }
+}
+
+
+
+/*
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+*/
+
+void arm_bitreversal_q15(
+q15_t * pSrc16,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ q31_t *pSrc = (q31_t *) pSrc16;
+ q31_t in;
+ uint32_t fftLenBy2, fftLenBy2p1;
+ uint32_t i, j;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[i];
+ pSrc[i] = pSrc[j];
+ pSrc[j] = in;
+
+ /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */
+ /* pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+ in = pSrc[i + fftLenBy2p1];
+ pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+ pSrc[j + fftLenBy2p1] = in;
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+fftLenBy2]; */
+ /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1u] */
+ in = pSrc[i + 1u];
+ pSrc[i + 1u] = pSrc[j + fftLenBy2];
+ pSrc[j + fftLenBy2] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S
new file mode 100644
index 000000000..7a2885b1e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S
@@ -0,0 +1,148 @@
+;/* ----------------------------------------------------------------------
+;* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+;*
+;* $Date: 17. January 2013
+;* $Revision: V1.4.1
+;*
+;* Project: CMSIS DSP Library
+;* Title: arm_bitreversal2.S
+;*
+;* Description: This is the arm_bitreversal_32 function done in
+;* assembly for maximum speed. This function is called
+;* after doing an fft to reorder the output. The function
+;* is loop unrolled by 2.
+;*
+;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions
+;* are met:
+;* - Redistributions of source code must retain the above copyright
+;* notice, this list of conditions and the following disclaimer.
+;* - Redistributions in binary form must reproduce the above copyright
+;* notice, this list of conditions and the following disclaimer in
+;* the documentation and/or other materials provided with the
+;* distribution.
+;* - Neither the name of ARM LIMITED nor the names of its contributors
+;* may be used to endorse or promote products derived from this
+;* software without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;* -------------------------------------------------------------------- */
+#if defined(__CC_ARM) //Keil
+ #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
+ #define LABEL
+#elif defined(__IASMARM__) //IAR
+ #define CODESECT SECTION `.text`:CODE
+ #define PROC
+ #define LABEL
+ #define ENDP
+ #define EXPORT PUBLIC
+#elif defined (__GNUC__) //GCC
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ #define THUMB .thumb
+ #define CODESECT .section text
+ #define EXPORT .global
+ #define PROC :
+ #define LABEL :
+ #define ENDP
+ #define END
+#endif
+
+ CODESECT
+ THUMB
+
+;/*
+;* @brief In-place bit reversal function.
+;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
+;* @param[in] bitRevLen bit reversal table length
+;* @param[in] *pBitRevTab points to bit reversal table.
+;* @return none.
+;*/
+ EXPORT arm_bitreversal_32
+
+#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ PUSH {r4-r6}
+ ADDS r1,r2,#0
+ LSRS r3,r3,#1
+arm_bitreversal_32_0 LABEL
+ LDRH r2,[r1,#2]
+ LDRH r6,[r1,#0]
+ ADD r2,r0,r2
+ ADD r6,r0,r6
+ LDR r5,[r2,#0]
+ LDR r4,[r6,#0]
+ STR r5,[r6,#0]
+ STR r4,[r2,#0]
+ LDR r5,[r2,#4]
+ LDR r4,[r6,#4]
+ STR r5,[r6,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#4
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r6}
+ BX lr
+ ENDP
+
+#else
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ CMP r3,#1
+ IT LS
+ BXLS lr
+ PUSH {r4-r9}
+ ADDS r1,r2,#2
+ LSRS r3,r3,#2
+arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
+ LDRH r8,[r1,#4]
+ LDRH r9,[r1,#2]
+ LDRH r2,[r1,#0]
+ LDRH r12,[r1,#-2]
+ ADD r8,r0,r8
+ ADD r9,r0,r9
+ ADD r2,r0,r2
+ ADD r12,r0,r12
+ LDR r7,[r9,#0]
+ LDR r6,[r8,#0]
+ LDR r5,[r2,#0]
+ LDR r4,[r12,#0]
+ STR r6,[r9,#0]
+ STR r7,[r8,#0]
+ STR r5,[r12,#0]
+ STR r4,[r2,#0]
+ LDR r7,[r9,#4]
+ LDR r6,[r8,#4]
+ LDR r5,[r2,#4]
+ LDR r4,[r12,#4]
+ STR r6,[r9,#4]
+ STR r7,[r8,#4]
+ STR r5,[r12,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#8
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r9}
+ BX lr
+ ENDP
+
+#endif
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c
new file mode 100644
index 000000000..8a13dfa95
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_f32.c
+*
+* Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+ uint32_t * pSrc,
+ const uint16_t bitRevLen,
+ const uint16_t * pBitRevTable);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup ComplexFFT Complex FFT Functions
+*
+* \par
+* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+* Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster
+* than the DFT, especially for long lengths.
+* The algorithms described in this section
+* operate on complex data. A separate set of functions is devoted to handling
+* of real sequences.
+* \par
+* There are separate algorithms for handling floating-point, Q15, and Q31 data
+* types. The algorithms available for each data type are described next.
+* \par
+* The FFT functions operate in-place. That is, the array holding the input data
+* will also be used to hold the corresponding result. The input data is complex
+* and contains <code>2*fftLen</code> interleaved values as shown below.
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>
+* The FFT result will be contained in the same array and the frequency domain
+* values will have the same interleaving.
+*
+* \par Floating-point
+* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8
+* stages are performed along with a single radix-2 or radix-4 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of <code>fftLen</code> when computing the forward transform. The
+* inverse transform includes a scale of <code>1/fftLen</code> as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Preinitialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in <code>arm_const_structs.h</code>. Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_f32. For example:
+* \par
+* <code>arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)</code>
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation. The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data. These functions are still
+* provided but are deprecated. The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_f32 function follows:
+* \par
+* const static arm_cfft_instance_f32 *S;
+* ...
+* switch (length) {
+* case 16:
+* S = & arm_cfft_sR_f32_len16;
+* break;
+* case 32:
+* S = & arm_cfft_sR_f32_len32;
+* break;
+* case 64:
+* S = & arm_cfft_sR_f32_len64;
+* break;
+* case 128:
+* S = & arm_cfft_sR_f32_len128;
+* break;
+* case 256:
+* S = & arm_cfft_sR_f32_len256;
+* break;
+* case 512:
+* S = & arm_cfft_sR_f32_len512;
+* break;
+* case 1024:
+* S = & arm_cfft_sR_f32_len1024;
+* break;
+* case 2048:
+* S = & arm_cfft_sR_f32_len2048;
+* break;
+* case 4096:
+* S = & arm_cfft_sR_f32_len4096;
+* break;
+* }
+* \par Q15 and Q31
+* The library provides radix-2 and radix-4 FFT algorithms for fixed-point data. The
+* radix-2 algorithm supports lengths of [16, 32, 64, ..., 4096]. The radix-4
+* algorithm supports lengths of [16, 64, 256, ..., 4096]. When possible, you
+* should use the radix-4 algorithm since it is faster than the radix-2 of the
+* same length.
+* \par
+* The forward FFTs include scaling in order to prevent results from overflowing.
+* Intermediate results are scaled down during each butterfly stage. In the
+* radix-2 algorithm, a scale of 0.5 is applied during each butterfly. In the
+* radix-4 algorithm, a scale of 0.25 is applied. The scaling applies to both
+* the forward and the inverse FFTs. Thus the forward FFT contains an additional
+* scale factor of <code>1/fftLen</code> as compared to the standard textbook
+* definition of the FFT. The inverse FFT also scales down during each butterfly
+* stage and this corresponds to the standard textbook definition.
+* \par
+* A separate instance structure must be defined for each transform used but
+* twiddle factor and bit reversal tables can be reused.
+* \par
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Initializes twiddle factor table and bit reversal table pointers.
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure
+* cannot be placed into a const data section. To place an instance structure
+* into a const data section, the instance structure should be manually
+* initialized as follows:
+* <pre>
+*arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_instance_f32 S = {fftLen, pTwiddle, pBitRevTable, bitRevLength};
+* </pre>
+* \par
+* where <code>fftLen</code> length of CFFT/CIFFT; <code>ifftFlag</code> Flag for
+* selection of forward or inverse transform. When ifftFlag is set the inverse
+* transform is calculated.
+* <code>bitReverseFlag</code> Flag for selection of output order (Set bitReverseFlag to output in normal order otherwise output in bit reversed order);
+* <code>pTwiddle</code>points to array of twiddle coefficients; <code>pBitRevTable</code> points to the bit reversal table.
+* <code>twidCoefModifier</code> modifier for twiddle factor table which supports all FFT lengths with same table;
+* <code>pBitRevTable</code> modifier for bit reversal table which supports all FFT lengths with same table.
+* <code>onebyfftLen</code> value of 1/fftLen to calculate CIFFT;
+* \par
+* The Q15 and Q31 FFT functions use a large bit reversal and twiddle factor
+* table. The tables are defined for the maximum length transform and a subset
+* of the coefficients are used in shorter transforms.
+*
+*/
+
+void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen;
+ float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+ float32_t * p2 = p1 + L;
+ const float32_t * tw = (float32_t *) S->pTwiddle;
+ float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+ float32_t m0, m1, m2, m3;
+ uint32_t l;
+
+ pCol1 = p1;
+ pCol2 = p2;
+
+ // Define new length
+ L >>= 1;
+ // Initialize mid pointers
+ pMid1 = p1 + L;
+ pMid2 = p2 + L;
+
+ // do two dot Fourier transform
+ for ( l = L >> 2; l > 0; l-- )
+ {
+ t1[0] = p1[0];
+ t1[1] = p1[1];
+ t1[2] = p1[2];
+ t1[3] = p1[3];
+
+ t2[0] = p2[0];
+ t2[1] = p2[1];
+ t2[2] = p2[2];
+ t2[3] = p2[3];
+
+ t3[0] = pMid1[0];
+ t3[1] = pMid1[1];
+ t3[2] = pMid1[2];
+ t3[3] = pMid1[3];
+
+ t4[0] = pMid2[0];
+ t4[1] = pMid2[1];
+ t4[2] = pMid2[2];
+ t4[3] = pMid2[3];
+
+ *p1++ = t1[0] + t2[0];
+ *p1++ = t1[1] + t2[1];
+ *p1++ = t1[2] + t2[2];
+ *p1++ = t1[3] + t2[3]; // col 1
+
+ t2[0] = t1[0] - t2[0];
+ t2[1] = t1[1] - t2[1];
+ t2[2] = t1[2] - t2[2];
+ t2[3] = t1[3] - t2[3]; // for col 2
+
+ *pMid1++ = t3[0] + t4[0];
+ *pMid1++ = t3[1] + t4[1];
+ *pMid1++ = t3[2] + t4[2];
+ *pMid1++ = t3[3] + t4[3]; // col 1
+
+ t4[0] = t4[0] - t3[0];
+ t4[1] = t4[1] - t3[1];
+ t4[2] = t4[2] - t3[2];
+ t4[3] = t4[3] - t3[3]; // for col 2
+
+ twR = *tw++;
+ twI = *tw++;
+
+ // multiply by twiddle factors
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ // R = R * Tr - I * Ti
+ *p2++ = m0 + m1;
+ // I = I * Tr + R * Ti
+ *p2++ = m2 - m3;
+
+ // use vertical symmetry
+ // 0.9988 - 0.0491i <==> -0.0491 - 0.9988i
+ m0 = t4[0] * twI;
+ m1 = t4[1] * twR;
+ m2 = t4[1] * twI;
+ m3 = t4[0] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+
+ twR = *tw++;
+ twI = *tw++;
+
+ m0 = t2[2] * twR;
+ m1 = t2[3] * twI;
+ m2 = t2[3] * twR;
+ m3 = t2[2] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+
+ m0 = t4[2] * twI;
+ m1 = t4[3] * twR;
+ m2 = t4[3] * twI;
+ m3 = t4[2] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+ }
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
+
+}
+
+void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen >> 1;
+ float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+ const float32_t *tw2, *tw3, *tw4;
+ float32_t * p2 = p1 + L;
+ float32_t * p3 = p2 + L;
+ float32_t * p4 = p3 + L;
+ float32_t t2[4], t3[4], t4[4], twR, twI;
+ float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+ float32_t m0, m1, m2, m3;
+ uint32_t l, twMod2, twMod3, twMod4;
+
+ pCol1 = p1; // points to real values by default
+ pCol2 = p2;
+ pCol3 = p3;
+ pCol4 = p4;
+ pEnd1 = p2 - 1; // points to imaginary values by default
+ pEnd2 = p3 - 1;
+ pEnd3 = p4 - 1;
+ pEnd4 = pEnd3 + L;
+
+ tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+ L >>= 1;
+
+ // do four dot Fourier transform
+
+ twMod2 = 2;
+ twMod3 = 4;
+ twMod4 = 6;
+
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // Twiddle factors are ones
+ *p2++ = t2[0];
+ *p2++ = t2[1];
+ *p3++ = t3[0];
+ *p3++ = t3[1];
+ *p4++ = t4[0];
+ *p4++ = t4[1];
+
+ tw2 += twMod2;
+ tw3 += twMod3;
+ tw4 += twMod4;
+
+ for (l = (L - 2) >> 1; l > 0; l-- )
+ {
+
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // BOTTOM
+ p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+ p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+ p1ap3_0 = pEnd1[0] + pEnd3[0];
+ p1sp3_0 = pEnd1[0] - pEnd3[0];
+ // col 2
+ t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1;
+ t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+ // col 3
+ t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+ t3[3] = p1ap3_0 - pEnd2[0] - pEnd4[0];
+ // col 4
+ t4[2] = pEnd2[0] - pEnd4[0] - p1sp3_1;
+ t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+ // col 1 - Bottom
+ *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
+ *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+ // COL 2
+ // read twiddle factors
+ twR = *tw2++;
+ twI = *tw2++;
+ // multiply by twiddle factors
+ // let Z1 = a + i(b), Z2 = c + i(d)
+ // => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d)
+ // Top
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // use vertical symmetry col 2
+ // 0.9997 - 0.0245i <==> 0.0245 - 0.9997i
+ // Bottom
+ m0 = t2[3] * twI;
+ m1 = t2[2] * twR;
+ m2 = t2[2] * twI;
+ m3 = t2[3] * twR;
+
+ *pEnd2-- = m0 - m1;
+ *pEnd2-- = m2 + m3;
+
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+ tw3 += twMod3;
+ // Top
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // use vertical symmetry col 3
+ // 0.9988 - 0.0491i <==> -0.9988 - 0.0491i
+ // Bottom
+ m0 = -t3[3] * twR;
+ m1 = t3[2] * twI;
+ m2 = t3[2] * twR;
+ m3 = t3[3] * twI;
+
+ *pEnd3-- = m0 - m1;
+ *pEnd3-- = m3 - m2;
+
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+ tw4 += twMod4;
+ // Top
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+ // use vertical symmetry col 4
+ // 0.9973 - 0.0736i <==> -0.0736 + 0.9973i
+ // Bottom
+ m0 = t4[3] * twI;
+ m1 = t4[2] * twR;
+ m2 = t4[2] * twI;
+ m3 = t4[3] * twR;
+
+ *pEnd4-- = m0 - m1;
+ *pEnd4-- = m2 + m3;
+ }
+
+ //MIDDLE
+ // Twiddle factors are
+ // 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - Top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // COL 2
+ twR = tw2[0];
+ twI = tw2[1];
+
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
+ // third col
+ arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
+ // fourth col
+ arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
+
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point complex FFT.
+* @param[in] *S points to an instance of the floating-point CFFT structure.
+* @param[in, out] *p1 points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+
+ uint32_t L = S->fftLen, l;
+ float32_t invL, * pSrc;
+
+ if(ifftFlag == 1u)
+ {
+ /* Conjugate input data */
+ pSrc = p1 + 1;
+ for(l=0; l<L; l++) {
+ *pSrc = -*pSrc;
+ pSrc += 2;
+ }
+ }
+
+ switch (L) {
+ case 16:
+ case 128:
+ case 1024:
+ arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 32:
+ case 256:
+ case 2048:
+ arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 64:
+ case 512:
+ case 4096:
+ arm_radix8_butterfly_f32( p1, L, (float32_t *) S->pTwiddle, 1);
+ break;
+ }
+
+ if( bitReverseFlag )
+ arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+
+ if(ifftFlag == 1u)
+ {
+ invL = 1.0f/(float32_t)L;
+ /* Conjugate and scale output data */
+ pSrc = p1;
+ for(l=0; l<L; l++) {
+ *pSrc++ *= invL ;
+ *pSrc = -(*pSrc) * invL;
+ pSrc++;
+ }
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
index 000000000..b5b3eb51a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_f32.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Radix-2 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-2 */
+ arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-2 */
+ arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+
+/**
+* @} end of ComplexFFT group
+*/
+
+
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix2_butterfly_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Initializations for the first stage */
+ n2 = fftLen >> 1;
+ ia = 0;
+ i = 0;
+
+ // loop for groups
+ for (k = n2; k > 0; k--)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ /* Twiddle coefficients index modifier */
+ ia += twidCoefModifier;
+
+ /* index calculation for the input as, */
+ /* pSrc[i + 0], pSrc[i + fftLen/1] */
+ l = i + n2;
+
+ /* Butterfly implementation */
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i++;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = n2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2); // groups loop end
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+ pSrc[2 * i + 2] = xt;
+ pSrc[2 * i + 3] = yt;
+ } // groups loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 1; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while(i < fftLen);
+ j++;
+ } while(j < n2);
+ twidCoefModifier <<= 1u;
+ }
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ n2 = fftLen >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while(j < n2); // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2 * i + 1] = p1;
+ pSrc[2 * i + 2] = p2;
+ pSrc[2 * i + 3] = p3;
+ } // butterfly loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2 ); // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2u * l] = p2;
+
+ pSrc[2 * i + 1] = p1;
+ pSrc[2u * l + 1u] = p3;
+ } // butterfly loop end
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
index 000000000..81932bc1e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.00048828125;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.001953125;
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ S->onebyfftLen = 0.0078125;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ S->onebyfftLen = 0.03125;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100644
index 000000000..e96ba3f16
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q15.c
+*
+* Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoefQ15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+ S->twidCoefModifier = 8u;
+ S->bitRevFactor = 8u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100644
index 000000000..d2e84d586
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q31.c
+*
+* Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoefQ31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 2048 point FFT */
+ case 2048u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ /* Initializations of structure parameters for 512 point FFT */
+ case 512u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100644
index 000000000..0caf6021d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,741 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q15.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the fixed-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+ * @return none.
+ */
+
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ i += n1;
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // groups loop end
+
+
+#else
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#else
+
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // groups loop end
+
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100644
index 000000000..bda6a3906
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q31.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the fixed-point CFFT/CIFFT.
+* @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_q31(
+const arm_cfft_radix2_instance_q31 * S,
+q31_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_radix2_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l, m;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ m = fftLen / n1;
+ do
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ i += n1;
+ m--;
+ } while( m > 0); // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 000000000..5acaf768b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_f32.c
+*
+* Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ /* Updating input index */
+ i0++;
+
+ }
+ while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = ya + yb + yc + yd */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa+yb-xc-yd) */
+ a4 = (Xaminusc + Ybminusd);
+ /* yb' = (ya-xb-yc+xd) */
+ a5 = (Yaminusc - Xbminusd);
+ /* xd' = (xa-yb-xc+yd)) */
+ a6 = (Xaminusc - Ybminusd);
+ /* yd' = (ya+xb-yc-xd) */
+ a7 = (Xbminusd + Yaminusc);
+
+ ptr1[0] = a0;
+ ptr1[1] = a1;
+ ptr1[2] = a2;
+ ptr1[3] = a3;
+ ptr1[4] = a4;
+ ptr1[5] = a5;
+ ptr1[6] = a6;
+ ptr1[7] = a7;
+
+ /* increment pointer by 8 */
+ ptr1 += 8u;
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the fft calculation */
+ n2 = fftLen;
+ n1 = n2;
+ for (k = fftLen; k > 1u; k >>= 2u)
+ {
+ /* Initializations for the fft calculation */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* FFT Calculation */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+
+}
+
+/*
+* @brief Core function for the floating-point CIFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @param[in] onebyfftLen value of 1/fftLen.
+* @return none.
+*/
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ a4 = (Xaminusc - Ybminusd);
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ a5 = (Yaminusc + Xbminusd);
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ a6 = (Xaminusc + Ybminusd);
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ a7 = (Yaminusc - Xbminusd);
+
+ p0 = a0 * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p2 = a2 * onebyfftLen;
+ p3 = a3 * onebyfftLen;
+ p4 = a4 * onebyfftLen;
+ p5 = a5 * onebyfftLen;
+ p6 = a6 * onebyfftLen;
+ p7 = a7 * onebyfftLen;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ ptr1[0] = p0;
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ ptr1[1] = p1;
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ ptr1[2] = p2;
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ ptr1[3] = p3;
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[4] = p4;
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ ptr1[5] = p5;
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[6] = p6;
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ ptr1[7] = p7;
+
+ /* increment source pointer by 8 for next calculations */
+ ptr1 = ptr1 + 8u;
+
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* Calculation of first stage */
+ for (k = fftLen; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Calculations of last stage */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xc + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+ /* (xa + xb) - (xc + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb-yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb-xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = r1 * onebyfftLen;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+ /* (xa - xc) - (yb-yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb-yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb-xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb-xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = r1 * onebyfftLen;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = r2 * onebyfftLen;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix4_f32(
+const arm_cfft_radix4_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 000000000..18f93f169
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 000000000..10c9fad75
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q15.c
+*
+* Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoefQ15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 000000000..8d4e792e6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q31.c
+*
+* Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoefQ31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 000000000..567603257
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1917 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q15.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+ * @details
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"
+ */
+
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+ q15_t in;
+
+ q15_t *ptr1;
+
+
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUAD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QASX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUAD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUAD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUSDX(R, C3) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+ out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUAD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUAD(C1, S) >> 16u;
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(C3, R) >> 16u;
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ out1 = __SMUSDX(R, C3) >> 16u;
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ /* R1 = (xa + xc) */
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc) */
+ S0 = __SSAT(T0 - S0, 16);
+ /* S1 = (xa - xc) */
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+ /* T0 = (yb + yd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ /* T1 = (xb + xd) */
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* ya' = ya + yb + yc + yd */
+ /* xa' = xa + xb + xc + xd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd) */
+ /* R1 = (xa + xc) - (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2;
+ T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd */
+ U0 = pSrc16[i3 * 2u] >> 2;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+ /* T0 = yb-yd */
+ T0 = __SSAT(T0 - U0, 16);
+ /* T1 = xb-xd */
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */
+ R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+ R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+ S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+ S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * (ic * 2u)];
+ Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16);
+ R1 = __SSAT(T1 + S1, 16);
+
+ /* S0 = (ya - yc), S1 =(xa - xc) */
+ S0 = __SSAT(T0 - S0, 16);
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16);
+ T1 = __SSAT(T1 + U1, 16);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ pSrc16[i0 * 2u] = out1;
+ pSrc16[(2u * i0) + 1u] = out2;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd */
+ T0 = __SSAT(T0 - U0, 16);
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+ R0 = (S0 >> 1u) - (T1 >> 1u);
+ R1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+ S0 = (S0 >> 1u) + (T1 >> 1u);
+ S1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+ out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+ out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd)) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+ }
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+ q15_t in;
+
+ q15_t *ptr1;
+
+
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUSD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(C2, R) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */
+ S = __QASX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUSD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUADX(C1, S) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUSD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUADX(C3, R) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+ out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUSD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSD(C1, S) >> 16u;
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUADX(S, C1) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(C3, R) >> 16u;
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ out1 = __SMUADX(C3, R) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* Start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+ /* Read yd (real), xd(imag) input */
+ /* input is down scale by 4 to avoid overflow */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1u];
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd) */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+ R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+ /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+ S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* End of first stage process */
+
+ /* data is in 4.11(q11) format */
+
+
+ /* Start of Middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[2u * ic * 2u + 1u];
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+ out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+ /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (S0 >> 1u) + (T1 >> 1u);
+ R1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (S0 >> 1u) - (T1 >> 1u);
+ S1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+ out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+ out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* End of Middle stages process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* start of last stage process */
+
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd) */
+ /* yb' = (ya+xb-yc-xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd) */
+ /* yd' = (ya-xb-yc+xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+ }
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 000000000..b56a0e082
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,911 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q31.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"
+ *
+ */
+
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+*
+* Butterfly implementation:
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+
+ /* start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* end of first stage process */
+
+ /* data is in 5.27(q27) format */
+
+
+ /* start of Middle stages process */
+
+
+ /* each stage in middle stages provides two down scaling of the input */
+
+ twidCoefModifier <<= 2u;
+
+
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* start of Last stage process */
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa + yb - xc - yd);
+ yb_out = (ya - xb - yc + xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa - yb - xc + yd);
+ yd_out = (ya + xb - yc - xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+
+}
+
+
+/**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT Function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+
+ /* input is be 1.31(q31) format for all FFT sizes */
+ /* Total process is divided into three stages */
+ /* process first stage, middle stages, & last stage */
+
+ /* Start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ do
+ {
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* data is in 5.27(q27) format */
+ /* each stage provides two down scaling of the input */
+
+
+ /* Start of Middle stages process */
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ for (j = 0; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] =
+ (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* Start of last stage process */
+
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+#ifndef ARM_MATH_BIG_ENDIAN
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa - yb - xc + yd);
+ yb_out = (ya + xb - yc - xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa + yb - xc - yd);
+ yd_out = (ya - xb - yc + xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100644
index 000000000..7ae0bfda5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix8_f32.c
+*
+* Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions
+*
+* \par
+* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).
+* Computational complexity of CFFT reduces drastically when compared to DFT.
+* \par
+* This set of functions implements CFFT/CIFFT
+* for floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output.
+* Complex input is stored in input buffer in an interleaved fashion.
+*
+* \par
+* The functions operate on blocks of input and output data and each call to the function processes
+* <code>2*fftLen</code> samples through the transform. <code>pSrc</code> points to In-place arrays containing <code>2*fftLen</code> values.
+* \par
+* The <code>pSrc</code> points to the array of in-place buffer of size <code>2*fftLen</code> and inputs and outputs are stored in an interleaved fashion as shown below.
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>
+*
+* \par Lengths supported by the transform:
+* \par
+* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm
+* and the size of the FFT supported are of the lengths [ 64, 512, 4096].
+*
+*
+* \par Algorithm:
+*
+* <b>Complex Fast Fourier Transform:</b>
+* \par
+* Input real and imaginary data:
+* <pre>
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+* </pre>
+* where N is length of FFT
+* \par
+* Output real and imaginary data:
+* <pre>
+* X(4r) = xa'+ j * ya'
+* X(4r+1) = xb'+ j * yb'
+* X(4r+2) = xc'+ j * yc'
+* X(4r+3) = xd'+ j * yd'
+* </pre>
+* \par
+* Twiddle factors for Radix-8 FFT:
+* <pre>
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+* </pre>
+*
+* \par
+* \image html CFFT.gif "Radix-8 Decimation-in Frequency Complex Fast Fourier Transform"
+*
+* \par
+* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.
+* \par
+* <b> Butterfly CFFT equations:</b>
+* <pre>
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+* </pre>
+*
+* \par
+* where <code>fftLen</code> length of CFFT/CIFFT; <code>ifftFlag</code> Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);
+* <code>bitReverseFlag</code> Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);
+* <code>pTwiddle</code>points to array of twiddle coefficients; <code>pBitRevTable</code> points to the array of bit reversal table.
+* <code>twidCoefModifier</code> modifier for twiddle factor table which supports all FFT lengths with same table;
+* <code>pBitRevTable</code> modifier for bit reversal table which supports all FFT lengths with same table.
+* <code>onebyfftLen</code> value of 1/fftLen to calculate CIFFT;
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix8_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+const float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+ uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+ uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+ uint32_t id;
+ uint32_t n1, n2, j;
+
+ float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+ float32_t t1, t2;
+ float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+ float32_t p1, p2, p3, p4;
+ float32_t co2, co3, co4, co5, co6, co7, co8;
+ float32_t si2, si3, si4, si5, si6, si7, si8;
+ const float32_t C81 = 0.70710678118f;
+
+ n2 = fftLen;
+
+ do
+ {
+ n1 = n2;
+ n2 = n2 >> 3;
+ i1 = 0;
+
+ do
+ {
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ pSrc[2 * i5] = r1 - r2;
+ r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = r1 - s3;
+ r1 = r1 + s3;
+ s3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1 + 1] = r1 + r2;
+ pSrc[2 * i5 + 1] = r1 - r2;
+ pSrc[2 * i3] = t1 + s3;
+ pSrc[2 * i7] = t1 - s3;
+ pSrc[2 * i3 + 1] = t2 - r3;
+ pSrc[2 * i7 + 1] = t2 + r3;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ r2 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - r2;
+ s5 = s5 + r2;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ pSrc[2 * i2] = r5 + s7;
+ pSrc[2 * i8] = r5 - s7;
+ pSrc[2 * i6] = t1 + s8;
+ pSrc[2 * i4] = t1 - s8;
+ pSrc[2 * i2 + 1] = s5 - r7;
+ pSrc[2 * i8 + 1] = s5 + r7;
+ pSrc[2 * i6 + 1] = t2 - r8;
+ pSrc[2 * i4 + 1] = t2 + r8;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ if(n2 < 8)
+ break;
+
+ ia1 = 0;
+ j = 1;
+
+ do
+ {
+ /* index calculation for the coefficients */
+ id = ia1 + twidCoefModifier;
+ ia1 = id;
+ ia2 = ia1 + id;
+ ia3 = ia2 + id;
+ ia4 = ia3 + id;
+ ia5 = ia4 + id;
+ ia6 = ia5 + id;
+ ia7 = ia6 + id;
+
+ co2 = pCoef[2 * ia1];
+ co3 = pCoef[2 * ia2];
+ co4 = pCoef[2 * ia3];
+ co5 = pCoef[2 * ia4];
+ co6 = pCoef[2 * ia5];
+ co7 = pCoef[2 * ia6];
+ co8 = pCoef[2 * ia7];
+ si2 = pCoef[2 * ia1 + 1];
+ si3 = pCoef[2 * ia2 + 1];
+ si4 = pCoef[2 * ia3 + 1];
+ si5 = pCoef[2 * ia4 + 1];
+ si6 = pCoef[2 * ia5 + 1];
+ si7 = pCoef[2 * ia6 + 1];
+ si8 = pCoef[2 * ia7 + 1];
+
+ i1 = j;
+
+ do
+ {
+ /* index calculation for the input */
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ r2 = r1 - r2;
+ s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = s1 - s3;
+ s1 = s1 + s3;
+ s3 = s2 - s4;
+ s2 = s2 + s4;
+ r1 = t1 + s3;
+ t1 = t1 - s3;
+ pSrc[2 * i1 + 1] = s1 + s2;
+ s2 = s1 - s2;
+ s1 = t2 - r3;
+ t2 = t2 + r3;
+ p1 = co5 * r2;
+ p2 = si5 * s2;
+ p3 = co5 * s2;
+ p4 = si5 * r2;
+ pSrc[2 * i5] = p1 + p2;
+ pSrc[2 * i5 + 1] = p3 - p4;
+ p1 = co3 * r1;
+ p2 = si3 * s1;
+ p3 = co3 * s1;
+ p4 = si3 * r1;
+ pSrc[2 * i3] = p1 + p2;
+ pSrc[2 * i3 + 1] = p3 - p4;
+ p1 = co7 * t1;
+ p2 = si7 * t2;
+ p3 = co7 * t2;
+ p4 = si7 * t1;
+ pSrc[2 * i7] = p1 + p2;
+ pSrc[2 * i7 + 1] = p3 - p4;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ s1 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - s1;
+ s5 = s5 + s1;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ r1 = r5 + s7;
+ r5 = r5 - s7;
+ r6 = t1 + s8;
+ t1 = t1 - s8;
+ s1 = s5 - r7;
+ s5 = s5 + r7;
+ s6 = t2 - r8;
+ t2 = t2 + r8;
+ p1 = co2 * r1;
+ p2 = si2 * s1;
+ p3 = co2 * s1;
+ p4 = si2 * r1;
+ pSrc[2 * i2] = p1 + p2;
+ pSrc[2 * i2 + 1] = p3 - p4;
+ p1 = co8 * r5;
+ p2 = si8 * s5;
+ p3 = co8 * s5;
+ p4 = si8 * r5;
+ pSrc[2 * i8] = p1 + p2;
+ pSrc[2 * i8 + 1] = p3 - p4;
+ p1 = co6 * r6;
+ p2 = si6 * s6;
+ p3 = co6 * s6;
+ p4 = si6 * r6;
+ pSrc[2 * i6] = p1 + p2;
+ pSrc[2 * i6 + 1] = p3 - p4;
+ p1 = co4 * t1;
+ p2 = si4 * t2;
+ p3 = co4 * t2;
+ p4 = si4 * t1;
+ pSrc[2 * i4] = p1 + p2;
+ pSrc[2 * i4 + 1] = p3 - p4;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ j++;
+ } while(j < n2);
+
+ twidCoefModifier <<= 3;
+ } while(n2 > 7);
+}
+
+/**
+* @} end of Radix8_CFFT_CIFFT group
+*/
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 000000000..9c61a6167
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_f32.c
+*
+* Description: Processing function of DCT4 & IDCT4 F32.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions
+ * Representation of signals by minimum number of values is important for storage and transmission.
+ * The possibility of large discontinuity between the beginning and end of a period of a signal
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
+ * spectrum and is very widely used in signal and image coding applications.
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
+ *
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
+ * Reordering of the input data makes the computation of DCT just a problem of
+ * computing the DFT of a real signal with a few additional operations.
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
+ *
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
+ * DCT2 implementation can be described in the following steps:
+ * - Re-ordering input
+ * - Calculating Real FFT
+ * - Multiplication of weights and Real FFT output and getting real part from the product.
+ *
+ * This process is explained by the block diagram below:
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"
+ *
+ * \par Algorithm:
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:
+ * \image html DCT4Equation.gif
+ * where <code>k = 0,1,2,.....N-1</code>
+ *\par
+ * Its inverse is defined as follows:
+ * \image html IDCT4Equation.gif
+ * where <code>n = 0,1,2,.....N-1</code>
+ *\par
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward
+ * and inverse transform computation are identical.
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
+ *
+ * \par Lengths supported by the transform:
+ * As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ * \par Instance Structure
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
+ * A separate instance structure must be defined for each transform.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Manually initialize the instance structure as follows:
+ * <pre>
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ * </pre>
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
+ * \c normalize is normalizing factor used and is equal to <code>sqrt(2/N)</code>;
+ * \c pTwiddle points to the twiddle factor table;
+ * \c pCosFactor points to the cosFactor table;
+ * \c pRfft points to the real FFT instance;
+ * \c pCfft points to the complex FFT instance;
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
+ * and arm_rfft_f32() respectively for details regarding static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ float32_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+ arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as,
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 000000000..eade6eeba
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16519 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_f32.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 F32
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* Where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const float32_t Weights_128[256] = {
+ 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+ -0.012271538285719925f,
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+ -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
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+
+static const float32_t Weights_8192[16384] = {
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+ -0.999986598406848000,
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+ -0.999988510290275690,
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+ -0.999991892856248010,
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+ -0.999993363538295150,
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+ -0.999994687152754080,
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+ -0.999995863699429940,
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+ -0.999996893178149880,
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+ -0.999997775588762350,
+ 0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
+ -0.999998510931137790,
+ 0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
+ -0.999999099205167830,
+ 0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
+ -0.999999540410766110,
+ 0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
+ -0.999999834547867670,
+ 0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
+ -0.999999981616429330,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>
+* \par
+* C command to generate the table
+* \par
+* <pre> for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+*/
+static const float32_t cos_factors_128[128] = {
+ 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+ 0.999077727752645360f,
+ 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+ 0.995767414467659820f,
+ 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+ 0.990058210262297120f,
+ 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+ 0.981963869109555240f,
+ 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+ 0.971503890986251780f,
+ 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+ 0.958703474895871600f,
+ 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+ 0.943593458161960390f,
+ 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+ 0.926210242138311380f,
+ 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+ 0.906595704514915330f,
+ 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+ 0.884797098430937790f,
+ 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+ 0.860866938637767310f,
+ 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+ 0.834862874986380010f,
+ 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+ 0.806847553543799330f,
+ 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+ 0.776888465673232440f,
+ 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+ 0.745057785441466060f,
+ 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+ 0.711432195745216430f,
+ 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+ 0.676092703575316030f,
+ 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+ 0.639124444863775730f,
+ 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+ 0.600616479383868970f,
+ 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+ 0.560661576197336030f,
+ 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+ 0.519355990165589530f,
+ 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+ 0.476799230063322250f,
+ 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+ 0.433093818853152010f,
+ 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+ 0.388345046698826300f,
+ 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+ 0.342660717311994380f,
+ 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+ 0.296150888243623960f,
+ 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+ 0.248927605745720260f,
+ 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+ 0.201104634842091960f,
+ 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+ 0.152797185258443410f,
+ 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+ 0.104121633872054730f,
+ 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+ 0.055195244349690031f,
+ 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+ 0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+ 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+ 0.999942349676023910f,
+ 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+ 0.999735288260561680f,
+ 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+ 0.999377670388002850f,
+ 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+ 0.998869549914283560f,
+ 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+ 0.998211003360478190f,
+ 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+ 0.997402129901275300f,
+ 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+ 0.996443051350042630f,
+ 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+ 0.995333912140482280f,
+ 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+ 0.994074879304879370f,
+ 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+ 0.992666142448948020f,
+ 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+ 0.991107913723276890f,
+ 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+ 0.989400427791380380f,
+ 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+ 0.987543941794359230f,
+ 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+ 0.985538735312176060f,
+ 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+ 0.983385110321551180f,
+ 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+ 0.981083391150486710f,
+ 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+ 0.978633924429423210f,
+ 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+ 0.976037079039039020f,
+ 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+ 0.973293246054698250f,
+ 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+ 0.970402838687555500f,
+ 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+ 0.967366292222328510f,
+ 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+ 0.964184063951745830f,
+ 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+ 0.960856633107679660f,
+ 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+ 0.957384500788975860f,
+ 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+ 0.953768189885990330f,
+ 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+ 0.950008245001843000f,
+ 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+ 0.946105232370403450f,
+ 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+ 0.942059739771017310f,
+ 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+ 0.937872376439989890f,
+ 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+ 0.933543772978836170f,
+ 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+ 0.929074581259315860f,
+ 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+ 0.924465474325262600f,
+ 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+ 0.919717146291227360f,
+ 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+ 0.914830312237946200f,
+ 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+ 0.909805708104652220f,
+ 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+ 0.904644090578246240f,
+ 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+ 0.899346236979341570f,
+ 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+ 0.893912945145203250f,
+ 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+ 0.888345033309596350f,
+ 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+ 0.882643339979562790f,
+ 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+ 0.876808723809145650f,
+ 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+ 0.870842063470078980f,
+ 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+ 0.864744257519462380f,
+ 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+ 0.858516224264442740f,
+ 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+ 0.852158901623919830f,
+ 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+ 0.845673246987299070f,
+ 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+ 0.839060237070312740f,
+ 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+ 0.832320867767929680f,
+ 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+ 0.825456154004377550f,
+ 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+ 0.818467129580298660f,
+ 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+ 0.811354847017063730f,
+ 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+ 0.804120377398265810f,
+ 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+ 0.796764810208418830f,
+ 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+ 0.789289253168885650f,
+ 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+ 0.781694832071059390f,
+ 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+ 0.773982690606822900f,
+ 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+ 0.766153990196312920f,
+ 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+ 0.758209909813015280f,
+ 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+ 0.750151645806215070f,
+ 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+ 0.741980411720831070f,
+ 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+ 0.733697438114660370f,
+ 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+ 0.725303972373060770f,
+ 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+ 0.716801278521099540f,
+ 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+ 0.708190637033195400f,
+ 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+ 0.699473344640283770f,
+ 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+ 0.690650714134534720f,
+ 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+ 0.681724074171649820f,
+ 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+ 0.672694769070772970f,
+ 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+ 0.663564158612039880f,
+ 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+ 0.654333617831800550f,
+ 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+ 0.645004536815544040f,
+ 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+ 0.635578320488556230f,
+ 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+ 0.626056388404343520f,
+ 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+ 0.616440174530853650f,
+ 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+ 0.606731127034524480f,
+ 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+ 0.596930708062196500f,
+ 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+ 0.587040393520918080f,
+ 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+ 0.577061672855679550f,
+ 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+ 0.566996048825108680f,
+ 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+ 0.556845037275160100f,
+ 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+ 0.546610166910834860f,
+ 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+ 0.536292979065963180f,
+ 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+ 0.525895027471084740f,
+ 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+ 0.515417878019463150f,
+ 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+ 0.504863108531267480f,
+ 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+ 0.494232308515959730f,
+ 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+ 0.483527078932918740f,
+ 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+ 0.472749031950342900f,
+ 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+ 0.461899790702462840f,
+ 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+ 0.450980989045103810f,
+ 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+ 0.439994271309633260f,
+ 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+ 0.428941292055329550f,
+ 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+ 0.417823715820212380f,
+ 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+ 0.406643216870369140f,
+ 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+ 0.395401478947816300f,
+ 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+ 0.384100195016935040f,
+ 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+ 0.372741067009515810f,
+ 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+ 0.361325805568454340f,
+ 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+ 0.349856129790135030f,
+ 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+ 0.338333766965541290f,
+ 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+ 0.326760452320131790f,
+ 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+ 0.315137928752522440f,
+ 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+ 0.303467946572011370f,
+ 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+ 0.291752263234989370f,
+ 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+ 0.279992643080273380f,
+ 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+ 0.268190857063403180f,
+ 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+ 0.256348682489942910f,
+ 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+ 0.244467902747824210f,
+ 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+ 0.232550307038775330f,
+ 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+ 0.220597690108873650f,
+ 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+ 0.208611851978263460f,
+ 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+ 0.196594597670080220f,
+ 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+ 0.184547736938619640f,
+ 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+ 0.172473083996796030f,
+ 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+ 0.160372457242928400f,
+ 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+ 0.148247678986896200f,
+ 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+ 0.136100575175706200f,
+ 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+ 0.123932975118512200f,
+ 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+ 0.111746711211126660f,
+ 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+ 0.099543618660069444f,
+ 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+ 0.087325535206192226f,
+ 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+ 0.075094300847921291f,
+ 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+ 0.062851757564161420f,
+ 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+ 0.050599749036899337f,
+ 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+ 0.038340120373552791f,
+ 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+ 0.026074717829104040f,
+ 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+ 0.013805388528060349f,
+ 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+ 0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+ 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+ 0.999996396822294350f,
+ 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+ 0.999983454831937730f,
+ 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+ 0.999961100616462820f,
+ 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+ 0.999929334386276070f,
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+ 0.119745959389479630f,
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+ 0.116699514361267840f,
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+ 0.113651970912781920f,
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+ 0.110603357728661910f,
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+ 0.083122438703613077f,
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+ 0.080064707899690932f,
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+ 0.077006223496245585f,
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+ 0.067826536598810966f,
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+ 0.064765325740339871f,
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+ 0.058641104054683348f,
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+ 0.055578150871004817f,
+ 0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+ 0.052514674564603257f,
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+ 0.049450703970084824f,
+ 0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+ 0.046386267926707213f,
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+ 0.043321395278109784f,
+ 0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+ 0.040256114872041358f,
+ 0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+ 0.037190455560088091f,
+ 0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+ 0.034124446197403423f,
+ 0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+ 0.031058115642434700f,
+ 0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+ 0.027991492756653365f,
+ 0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+ 0.024924606404281485f,
+ 0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+ 0.021857485452021874f,
+ 0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+ 0.018790158768784596f,
+ 0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+ 0.015722655225417017f,
+ 0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+ 0.012655003694430301f,
+ 0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+ 0.009587233049729183f,
+ 0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+ 0.006519372166339549f,
+ 0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+ 0.003451449920135975f,
+ 0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+ 0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+ 1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
+ 1.999999549602533100,
+ 1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
+ 1.999997931848645600,
+ 1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
+ 1.999995137547503600,
+ 1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
+ 1.999991166700750800,
+ 1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
+ 1.999986019310723500,
+ 1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
+ 1.999979695380449400,
+ 1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
+ 1.999972194913648900,
+ 1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
+ 1.999963517914734100,
+ 1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
+ 1.999953664388809800,
+ 1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
+ 1.999942634341672600,
+ 1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
+ 1.999930427779810900,
+ 1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
+ 1.999917044710405500,
+ 1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
+ 1.999902485141329400,
+ 1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
+ 1.999886749081147800,
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+ 1.999869836539117700,
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+ 1.999812040124888700,
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+ 1.999790421761877400,
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+ 1.999767626973684400,
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+ 1.999200138197791100,
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+ 1.999156170719930100,
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+ 1.999017212080857400,
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+ 1.998968540556831800,
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+ 1.998918693091116200,
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+ 1.998867669713034500,
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+ 1.998355548434686400,
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+ 1.997891398191342400,
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+ 1.996702884526087900,
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+ 1.993158147667842800,
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+ 0.159556013108654580,
+ 0.159173737312218650, 0.158791455663418930, 0.158409168176311760,
+ 0.158026874864951870,
+ 0.157644575743395960, 0.157262270825699210, 0.156879960125918730,
+ 0.156497643658110590,
+ 0.156115321436331000, 0.155732993474637760, 0.155350659787087090,
+ 0.154968320387737170,
+ 0.154585975290645110, 0.154203624509868190, 0.153821268059465250,
+ 0.153438905953493550,
+ 0.153056538206012340, 0.152674164831079730, 0.152291785842754070,
+ 0.151909401255095250,
+ 0.151527011082161540, 0.151144615338013210, 0.150762214036709470,
+ 0.150379807192309620,
+ 0.149997394818874590, 0.149614976930463660, 0.149232553541138180,
+ 0.148850124664957870,
+ 0.148467690315984390, 0.148085250508278370, 0.147702805255900570,
+ 0.147320354572913260,
+ 0.146937898473377210, 0.146555436971355090, 0.146172970080908520,
+ 0.145790497816099230,
+ 0.145408020190990560, 0.145025537219644170, 0.144643048916123810,
+ 0.144260555294492000,
+ 0.143878056368811510, 0.143495552153146630, 0.143113042661560050,
+ 0.142730527908116440,
+ 0.142348007906879320, 0.141965482671912420, 0.141582952217280980,
+ 0.141200416557048680,
+ 0.140817875705281120, 0.140435329676042390, 0.140052778483398480,
+ 0.139670222141414250,
+ 0.139287660664154770, 0.138905094065686600, 0.138522522360074780,
+ 0.138139945561386200,
+ 0.137757363683686740, 0.137374776741042340, 0.136992184747520560,
+ 0.136609587717187310,
+ 0.136226985664110460, 0.135844378602356760, 0.135461766545993150,
+ 0.135079149509088060,
+ 0.134696527505708320, 0.134313900549922760, 0.133931268655799020,
+ 0.133548631837404950,
+ 0.133165990108809860, 0.132783343484081580, 0.132400691977289760,
+ 0.132018035602502530,
+ 0.131635374373789940, 0.131252708305220960, 0.130870037410864640,
+ 0.130487361704791580,
+ 0.130104681201070800, 0.129721995913773260, 0.129339305856968730,
+ 0.128956611044727220,
+ 0.128573911491120210, 0.128191207210217570, 0.127808498216091110,
+ 0.127425784522811530,
+ 0.127043066144449680, 0.126660343095077900, 0.126277615388766920,
+ 0.125894883039589430,
+ 0.125512146061616980, 0.125129404468921260, 0.124746658275575490,
+ 0.124363907495651240,
+ 0.123981152143222060, 0.123598392232359880, 0.123215627777138580,
+ 0.122832858791630880,
+ 0.122450085289909640, 0.122067307286049230, 0.121684524794122440,
+ 0.121301737828203960,
+ 0.120918946402367330, 0.120536150530686250, 0.120153350227235940,
+ 0.119770545506089950,
+ 0.119387736381323830, 0.119004922867011920, 0.118622104977228730,
+ 0.118239282726050290,
+ 0.117856456127550970, 0.117473625195807100, 0.117090789944893860,
+ 0.116707950388886520,
+ 0.116325106541861910, 0.115942258417895240, 0.115559406031063570,
+ 0.115176549395442460,
+ 0.114793688525109290, 0.114410823434140360, 0.114027954136612060,
+ 0.113645080646602280,
+ 0.113262202978187320, 0.112879321145445350, 0.112496435162453430,
+ 0.112113545043288730,
+ 0.111730650802029900, 0.111347752452754000, 0.110964850009539970,
+ 0.110581943486465610,
+ 0.110199032897608850, 0.109816118257049110, 0.109433199578864170,
+ 0.109050276877133770,
+ 0.108667350165936400, 0.108284419459350770, 0.107901484771457020,
+ 0.107518546116333660,
+ 0.107135603508061170, 0.106752656960718350, 0.106369706488385940,
+ 0.105986752105143480,
+ 0.105603793825070680, 0.105220831662248700, 0.104837865630757090,
+ 0.104454895744677270,
+ 0.104071922018089540, 0.103688944465074300, 0.103305963099713400,
+ 0.102922977936087120,
+ 0.102539988988277600, 0.102156996270365800, 0.101773999796432830,
+ 0.101390999580561250,
+ 0.101007995636832020, 0.100624987979327970, 0.100241976622130760,
+ 0.099858961579322170,
+ 0.099475942864985456, 0.099092920493202258, 0.098709894478056073,
+ 0.098326864833628791,
+ 0.097943831574004214, 0.097560794713264939, 0.097177754265493674,
+ 0.096794710244774623,
+ 0.096411662665190329, 0.096028611540825232, 0.095645556885762609,
+ 0.095262498714085819,
+ 0.094879437039879722, 0.094496371877227495, 0.094113303240214247,
+ 0.093730231142923864,
+ 0.093347155599440373, 0.092964076623849271, 0.092580994230234359,
+ 0.092197908432681386,
+ 0.091814819245274432, 0.091431726682099479, 0.091048630757241303,
+ 0.090665531484784803,
+ 0.090282428878816323, 0.089899322953420582, 0.089516213722684160,
+ 0.089133101200692441,
+ 0.088749985401530951, 0.088366866339286629, 0.087983744028044805,
+ 0.087600618481892656,
+ 0.087217489714916191, 0.086834357741201490, 0.086451222574836131,
+ 0.086068084229906014,
+ 0.085684942720498897, 0.085301798060701386, 0.084918650264600160,
+ 0.084535499346283349,
+ 0.084152345319837438, 0.083769188199350780, 0.083386027998910095,
+ 0.083002864732603973,
+ 0.082619698414519799, 0.082236529058745025, 0.081853356679368619,
+ 0.081470181290477811,
+ 0.081087002906161790, 0.080703821540508452, 0.080320637207605849,
+ 0.079937449921543474,
+ 0.079554259696409127, 0.079171066546292510, 0.078787870485282088,
+ 0.078404671527466441,
+ 0.078021469686935602, 0.077638264977777913, 0.077255057414083589,
+ 0.076871847009941652,
+ 0.076488633779441206, 0.076105417736672773, 0.075722198895725248,
+ 0.075338977270689375,
+ 0.074955752875654230, 0.074572525724710764, 0.074189295831948693,
+ 0.073806063211457842,
+ 0.073422827877329483, 0.073039589843653177, 0.072656349124520389,
+ 0.072273105734021334,
+ 0.071889859686246352, 0.071506610995287156, 0.071123359675233852,
+ 0.070740105740178361,
+ 0.070356849204211397, 0.069973590081423773, 0.069590328385907715,
+ 0.069207064131753759,
+ 0.068823797333054326, 0.068440528003900616, 0.068057256158383886,
+ 0.067673981810596848,
+ 0.067290704974630494, 0.066907425664577733, 0.066524143894529736,
+ 0.066140859678579578,
+ 0.065757573030819083, 0.065374283965340146, 0.064990992496236119,
+ 0.064607698637598646,
+ 0.064224402403521202, 0.063841103808096086, 0.063457802865415636,
+ 0.063074499589573618,
+ 0.062691193994662109, 0.062307886094775049, 0.061924575904005130,
+ 0.061541263436445129,
+ 0.061157948706189229, 0.060774631727329942, 0.060391312513961619,
+ 0.060007991080177375,
+ 0.059624667440070382, 0.059241341607735261, 0.058858013597264912,
+ 0.058474683422754095,
+ 0.058091351098295878, 0.057708016637985186, 0.057324680055915692,
+ 0.056941341366181127,
+ 0.056558000582876661, 0.056174657720095743, 0.055791312791933681,
+ 0.055407965812484541,
+ 0.055024616795842439, 0.054641265756102911, 0.054257912707359794,
+ 0.053874557663708772,
+ 0.053491200639244271, 0.053107841648060788, 0.052724480704254229,
+ 0.052341117821918783,
+ 0.051957753015150501, 0.051574386298044173, 0.051191017684694640,
+ 0.050807647189198162,
+ 0.050424274825649297, 0.050040900608144430, 0.049657524550778251,
+ 0.049274146667647289,
+ 0.048890766972846805, 0.048507385480472134, 0.048124002204620014,
+ 0.047740617159385448,
+ 0.047357230358865306, 0.046973841817155179, 0.046590451548350717,
+ 0.046207059566548990,
+ 0.045823665885845313, 0.045440270520336883, 0.045056873484119603,
+ 0.044673474791289434,
+ 0.044290074455943754, 0.043906672492178188, 0.043523268914090238,
+ 0.043139863735776100,
+ 0.042756456971332048, 0.042373048634855741, 0.041989638740443119,
+ 0.041606227302191955,
+ 0.041222814334198304, 0.040839399850560058, 0.040455983865373815,
+ 0.040072566392736257,
+ 0.039689147446745419, 0.039305727041497644, 0.038922305191091085,
+ 0.038538881909622631,
+ 0.038155457211189216, 0.037772031109889144, 0.037388603619819022,
+ 0.037005174755077273,
+ 0.036621744529761024, 0.036238312957967478, 0.035854880053795196,
+ 0.035471445831341021,
+ 0.035088010304703626, 0.034704573487980395, 0.034321135395268765,
+ 0.033937696040667535,
+ 0.033554255438273790, 0.033170813602186440, 0.032787370546502645,
+ 0.032403926285321405,
+ 0.032020480832740429, 0.031637034202857461, 0.031253586409771626,
+ 0.030870137467580314,
+ 0.030486687390382738, 0.030103236192276818, 0.029719783887360508,
+ 0.029336330489733147,
+ 0.028952876013492331, 0.028569420472737472, 0.028185963881566689,
+ 0.027802506254078142,
+ 0.027419047604371360, 0.027035587946544135, 0.026652127294696067,
+ 0.026268665662925468,
+ 0.025885203065330677, 0.025501739516011413, 0.025118275029065638,
+ 0.024734809618593138,
+ 0.024351343298691951, 0.023967876083461924, 0.023584407987001611,
+ 0.023200939023409587,
+ 0.022817469206785804, 0.022433998551228459, 0.022050527070837558,
+ 0.021667054779711814,
+ 0.021283581691949955, 0.020900107821652084, 0.020516633182916549,
+ 0.020133157789843505,
+ 0.019749681656531803, 0.019366204797080316, 0.018982727225589285,
+ 0.018599248956157190,
+ 0.018215770002884327, 0.017832290379869671, 0.017448810101212228,
+ 0.017065329181012358,
+ 0.016681847633368677, 0.016298365472381587, 0.015914882712149747,
+ 0.015531399366773606,
+ 0.015147915450352307, 0.014764430976985016, 0.014380945960772247,
+ 0.013997460415812761,
+ 0.013613974356207112, 0.013230487796054543, 0.012847000749454314,
+ 0.012463513230507034,
+ 0.012080025253311559, 0.011696536831968529, 0.011313047980577277,
+ 0.010929558713237145,
+ 0.010546069044048827, 0.010162578987111254, 0.009779088556525145,
+ 0.009395597766389905,
+ 0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
+ 0.007861631292354124,
+ 0.007478138915970929, 0.007094646264638386, 0.006711153352455981,
+ 0.006327660193523208,
+ 0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
+ 0.004793685372293270,
+ 0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
+ 0.003259707731061291,
+ 0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
+ 0.001725728172227238,
+ 0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
+ 0.000191747598192208,
+
+};
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingF32Table.gif
+ */
+
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize)
+{
+ /* Initialize the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ float32_t *twiddlePtr[4] =
+ { (float32_t *) Weights_128, (float32_t *) Weights_512,
+ (float32_t *) Weights_2048, (float32_t *) Weights_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ float32_t *pCosFactor[4] =
+ { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+ (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 000000000..1e0ad73d4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q15.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q15
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+ 0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+ 0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+ 0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+ 0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+ 0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+ 0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+ 0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+ 0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+ 0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+ 0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+ 0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+ 0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+ 0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+ 0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+ 0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+ 0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+ 0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+ 0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+ 0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+ 0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+ 0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+ 0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+ 0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+ 0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+ 0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+ 0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+ 0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+ 0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+ 0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+ 0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+ 0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+ 0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+ 0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+ 0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+ 0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+ 0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+ 0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+ 0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+ 0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+ 0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+ 0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+ 0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+ 0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+ 0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+ 0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+ 0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+ 0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+ 0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+ 0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+ 0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+ 0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+ 0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+ 0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+ 0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+ 0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+ 0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+ 0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+ 0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+ 0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+ 0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+ 0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+ 0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+ 0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+ 0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+ 0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+ 0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+ 0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+ 0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+ 0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+ 0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+ 0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+ 0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+ 0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+ 0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+ 0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+ 0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+ 0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+ 0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+ 0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+ 0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+ 0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+ 0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+ 0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+ 0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+ 0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+ 0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+ 0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+ 0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+ 0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+ 0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+ 0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+ 0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+ 0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+ 0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+ 0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+ 0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+ 0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+ 0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+ 0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+ 0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+ 0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+ 0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+ 0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+ 0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+ 0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+ 0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+ 0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+ 0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+ 0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+ 0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+ 0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+ 0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+ 0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+ 0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+ 0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+ 0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+ 0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+ 0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+ 0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+ 0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+ 0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+ 0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+ 0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+ 0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+ 0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+ 0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+ 0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+ 0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+ 0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+ 0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+ 0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+ 0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+ 0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+ 0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+ 0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+ 0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+ 0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+ 0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+ 0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+ 0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+ 0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+ 0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+ 0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+ 0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+ 0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+ 0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+ 0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+ 0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+ 0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+ 0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+ 0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+ 0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+ 0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+ 0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+ 0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+ 0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+ 0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+ 0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+ 0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+ 0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+ 0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+ 0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+ 0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+ 0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+ 0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+ 0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+ 0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+ 0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+ 0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+ 0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+ 0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+ 0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+ 0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+ 0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+ 0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+ 0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+ 0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+ 0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+ 0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+ 0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+ 0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+ 0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+ 0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+ 0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+ 0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+ 0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+ 0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+ 0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+ 0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+ 0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+ 0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+ 0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+ 0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+ 0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+ 0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+ 0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+ 0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+ 0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+ 0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+ 0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+ 0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+ 0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+ 0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+ 0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+ 0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+ 0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+ 0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+ 0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+ 0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+ 0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+ 0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+ 0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+ 0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+ 0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+ 0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+ 0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+ 0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+ 0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+ 0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+ 0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+ 0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+ 0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+ 0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+ 0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+ 0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+ 0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+ 0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+ 0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+ 0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+ 0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+ 0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+ 0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+ 0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+ 0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+ 0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+ 0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+ 0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+ 0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+ 0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+ 0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+ 0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+ 0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+ 0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+ 0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+ 0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+ 0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+ 0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+ 0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+ 0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+ 0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+ 0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+ 0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+ 0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+ 0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+ 0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+ 0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+ 0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+ 0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+ 0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+ 0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+ 0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+ 0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+ 0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+ 0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+ 0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+ 0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+ 0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+ 0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+ 0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+ 0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+ 0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+ 0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+ 0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+ 0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+ 0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+ 0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+ 0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+ 0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+ 0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+ 0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+ 0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+ 0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+ 0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+ 0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+ 0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+ 0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+ 0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+ 0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+ 0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+ 0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+ 0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+ 0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+ 0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+ 0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+ 0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+ 0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+ 0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+ 0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+ 0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+ 0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+ 0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+ 0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+ 0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+ 0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+ 0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+ 0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+ 0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+ 0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+ 0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+ 0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+ 0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+ 0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+ 0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+ 0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+ 0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+ 0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+ 0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+ 0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+ 0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+ 0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+ 0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+ 0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+ 0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+ 0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+ 0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+ 0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+ 0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+ 0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+ 0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+ 0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+ 0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+ 0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+ 0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+ 0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+ 0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+ 0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+ 0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+ 0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+ 0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+ 0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+ 0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+ 0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+ 0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+ 0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+ 0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+ 0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+ 0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+ 0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+ 0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+ 0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+ 0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+ 0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+ 0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+ 0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+ 0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+ 0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+ 0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+ 0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+ 0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+ 0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+ 0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+ 0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+ 0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+ 0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+ 0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+ 0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+ 0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+ 0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+ 0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+ 0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+ 0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+ 0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+ 0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+ 0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+ 0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+ 0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+ 0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+ 0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+ 0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+ 0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+ 0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+ 0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+ 0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+ 0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+ 0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+ 0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+ 0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+ 0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+ 0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+ 0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+ 0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+ 0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+ 0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+ 0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+ 0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+ 0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+ 0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+ 0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+ 0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+ 0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+ 0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+ 0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+ 0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+ 0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+ 0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+ 0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+ 0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+ 0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+ 0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+ 0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+ 0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+ 0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+ 0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+ 0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+ 0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+ 0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+ 0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+ 0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+ 0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+ 0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+ 0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+ 0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+ 0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+ 0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+ 0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+ 0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+ 0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+ 0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+ 0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+ 0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+ 0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+ 0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+ 0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+ 0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+ 0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+ 0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+ 0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+ 0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+ 0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+ 0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+ 0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+ 0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+ 0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+ 0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+ 0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+ 0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+ 0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+ 0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+ 0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+ 0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+ 0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+ 0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+ 0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+ 0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+ 0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+ 0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+ 0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+ 0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+ 0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+ 0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+ 0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+ 0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+ 0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+ 0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+ 0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+ 0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+ 0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+ 0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+ 0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+ 0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+ 0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+ 0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+ 0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+ 0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+ 0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+ 0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+ 0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+ 0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+ 0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+ 0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
+ 0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,
+ 0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,
+ 0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,
+ 0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,
+ 0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,
+ 0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,
+ 0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,
+ 0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,
+ 0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,
+ 0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,
+ 0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+ 0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+ 0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+ 0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+ 0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
+ 0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,
+ 0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,
+ 0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+ 0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+ 0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+ 0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+ 0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+ 0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+ 0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+ 0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+ 0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+ 0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+ 0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+ 0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+ 0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+ 0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+ 0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+ 0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+ 0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+ 0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+ 0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+ 0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+ 0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+ 0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+ 0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+ 0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+ 0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+ 0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+ 0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+ 0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+ 0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+ 0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+ 0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+ 0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+ 0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+ 0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+ 0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+ 0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+ 0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+ 0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+ 0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+ 0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+ 0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+ 0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+ 0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+ 0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+ 0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+ 0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
+ 0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,
+ 0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
+ 0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,
+ 0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
+ 0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,
+ 0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,
+ 0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+ 0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+ 0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+ 0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+ 0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+ 0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+ 0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+ 0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+ 0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+ 0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+ 0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+ 0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+ 0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+ 0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+ 0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+ 0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+ 0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+ 0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+ 0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+ 0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+ 0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+ 0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+ 0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+ 0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+ 0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+ 0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+ 0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+ 0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+ 0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+ 0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+ 0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+ 0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+ 0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+ 0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+ 0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+ 0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+ 0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+ 0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+ 0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+ 0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+ 0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+ 0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+ 0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+ 0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+ 0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+ 0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+ 0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+ 0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+ 0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+ 0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+ 0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+ 0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+ 0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+ 0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+ 0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+ 0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+ 0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+ 0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+ 0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+ 0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+ 0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+ 0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+ 0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+ 0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+ 0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+ 0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+ 0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+ 0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+ 0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+ 0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+ 0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+ 0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+ 0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+ 0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+ 0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+ 0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+ 0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+ 0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+ 0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+ 0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+ 0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+ 0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+ 0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+ 0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+ 0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+ 0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+ 0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+ 0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+ 0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+ 0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+ 0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+ 0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+ 0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+ 0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+ 0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+ 0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+ 0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+ 0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+ 0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+ 0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+ 0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+ 0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+ 0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+ 0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+ 0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+ 0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+ 0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+ 0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+ 0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+ 0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+ 0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+ 0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+ 0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+ 0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+ 0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+ 0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+ 0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+ 0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+ 0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+ 0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+ 0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
+ 0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
+ 0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
+ 0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
+ 0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
+ 0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
+ 0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
+ 0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
+ 0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
+ 0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
+ 0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
+ 0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
+ 0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
+ 0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
+ 0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
+ 0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
+ 0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
+ 0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
+ 0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
+ 0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
+ 0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
+ 0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
+ 0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
+ 0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
+ 0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
+ 0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
+ 0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
+ 0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
+ 0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
+ 0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
+ 0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
+ 0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
+ 0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
+ 0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
+ 0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
+ 0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
+ 0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
+ 0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
+ 0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
+ 0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
+ 0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
+ 0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
+ 0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
+ 0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
+ 0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
+ 0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
+ 0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
+ 0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
+ 0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
+ 0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
+ 0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
+ 0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
+ 0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
+ 0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
+ 0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
+ 0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
+ 0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
+ 0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
+ 0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
+ 0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
+ 0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
+ 0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
+ 0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
+ 0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
+ 0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
+ 0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
+ 0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
+ 0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
+ 0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
+ 0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
+ 0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
+ 0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
+ 0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
+ 0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
+ 0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
+ 0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
+ 0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
+ 0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
+ 0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
+ 0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
+ 0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
+ 0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
+ 0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
+ 0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
+ 0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
+ 0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
+ 0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
+ 0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
+ 0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
+ 0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
+ 0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
+ 0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
+ 0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
+ 0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
+ 0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
+ 0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
+ 0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
+ 0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
+ 0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
+ 0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
+ 0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
+ 0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
+ 0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
+ 0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
+ 0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
+ 0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
+ 0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
+ 0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
+ 0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
+ 0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
+ 0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
+ 0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
+ 0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
+ 0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
+ 0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
+ 0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
+ 0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
+ 0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
+ 0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
+ 0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
+ 0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
+ 0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
+ 0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
+ 0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
+ 0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
+ 0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
+ 0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
+ 0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
+ 0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
+ 0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
+ 0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
+ 0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
+ 0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
+ 0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
+ 0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
+ 0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
+ 0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
+ 0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
+ 0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
+ 0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
+ 0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
+ 0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
+ 0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
+ 0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
+ 0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
+ 0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
+ 0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
+ 0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
+ 0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
+ 0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
+ 0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
+ 0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
+ 0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
+ 0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
+ 0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
+ 0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
+ 0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
+ 0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
+ 0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
+ 0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
+ 0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
+ 0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
+ 0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
+ 0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
+ 0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
+ 0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
+ 0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
+ 0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
+ 0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
+ 0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
+ 0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
+ 0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
+ 0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
+ 0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
+ 0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
+ 0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
+ 0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
+ 0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
+ 0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
+ 0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
+ 0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
+ 0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
+ 0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
+ 0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
+ 0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
+ 0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
+ 0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
+ 0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
+ 0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
+ 0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
+ 0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
+ 0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
+ 0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
+ 0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
+ 0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
+ 0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
+ 0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
+ 0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
+ 0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
+ 0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
+ 0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
+ 0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
+ 0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
+ 0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
+ 0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
+ 0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
+ 0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
+ 0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
+ 0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
+ 0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
+ 0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
+ 0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
+ 0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
+ 0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
+ 0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
+ 0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
+ 0x7e32, 0xea9a, 0x7e31, 0xea94, 0x7e30, 0xea8e, 0x7e2f, 0xea88,
+ 0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
+ 0x7e2a, 0xea69, 0x7e29, 0xea63, 0x7e28, 0xea5c, 0x7e27, 0xea56,
+ 0x7e26, 0xea50, 0x7e25, 0xea4a, 0x7e24, 0xea44, 0x7e22, 0xea3d,
+ 0x7e21, 0xea37, 0x7e20, 0xea31, 0x7e1f, 0xea2b, 0x7e1e, 0xea25,
+ 0x7e1d, 0xea1e, 0x7e1c, 0xea18, 0x7e1b, 0xea12, 0x7e1a, 0xea0c,
+ 0x7e19, 0xea06, 0x7e18, 0xe9ff, 0x7e17, 0xe9f9, 0x7e16, 0xe9f3,
+ 0x7e14, 0xe9ed, 0x7e13, 0xe9e7, 0x7e12, 0xe9e1, 0x7e11, 0xe9da,
+ 0x7e10, 0xe9d4, 0x7e0f, 0xe9ce, 0x7e0e, 0xe9c8, 0x7e0d, 0xe9c2,
+ 0x7e0c, 0xe9bb, 0x7e0b, 0xe9b5, 0x7e0a, 0xe9af, 0x7e08, 0xe9a9,
+ 0x7e07, 0xe9a3, 0x7e06, 0xe99c, 0x7e05, 0xe996, 0x7e04, 0xe990,
+ 0x7e03, 0xe98a, 0x7e02, 0xe984, 0x7e01, 0xe97e, 0x7e00, 0xe977,
+ 0x7dff, 0xe971, 0x7dfd, 0xe96b, 0x7dfc, 0xe965, 0x7dfb, 0xe95f,
+ 0x7dfa, 0xe958, 0x7df9, 0xe952, 0x7df8, 0xe94c, 0x7df7, 0xe946,
+ 0x7df6, 0xe940, 0x7df5, 0xe93a, 0x7df3, 0xe933, 0x7df2, 0xe92d,
+ 0x7df1, 0xe927, 0x7df0, 0xe921, 0x7def, 0xe91b, 0x7dee, 0xe914,
+ 0x7ded, 0xe90e, 0x7dec, 0xe908, 0x7dea, 0xe902, 0x7de9, 0xe8fc,
+ 0x7de8, 0xe8f6, 0x7de7, 0xe8ef, 0x7de6, 0xe8e9, 0x7de5, 0xe8e3,
+ 0x7de4, 0xe8dd, 0x7de2, 0xe8d7, 0x7de1, 0xe8d0, 0x7de0, 0xe8ca,
+ 0x7ddf, 0xe8c4, 0x7dde, 0xe8be, 0x7ddd, 0xe8b8, 0x7ddc, 0xe8b2,
+ 0x7dda, 0xe8ab, 0x7dd9, 0xe8a5, 0x7dd8, 0xe89f, 0x7dd7, 0xe899,
+ 0x7dd6, 0xe893, 0x7dd5, 0xe88c, 0x7dd4, 0xe886, 0x7dd2, 0xe880,
+ 0x7dd1, 0xe87a, 0x7dd0, 0xe874, 0x7dcf, 0xe86e, 0x7dce, 0xe867,
+ 0x7dcd, 0xe861, 0x7dcc, 0xe85b, 0x7dca, 0xe855, 0x7dc9, 0xe84f,
+ 0x7dc8, 0xe849, 0x7dc7, 0xe842, 0x7dc6, 0xe83c, 0x7dc5, 0xe836,
+ 0x7dc3, 0xe830, 0x7dc2, 0xe82a, 0x7dc1, 0xe823, 0x7dc0, 0xe81d,
+ 0x7dbf, 0xe817, 0x7dbd, 0xe811, 0x7dbc, 0xe80b, 0x7dbb, 0xe805,
+ 0x7dba, 0xe7fe, 0x7db9, 0xe7f8, 0x7db8, 0xe7f2, 0x7db6, 0xe7ec,
+ 0x7db5, 0xe7e6, 0x7db4, 0xe7e0, 0x7db3, 0xe7d9, 0x7db2, 0xe7d3,
+ 0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
+ 0x7dac, 0xe7b4, 0x7dab, 0xe7ae, 0x7da9, 0xe7a8, 0x7da8, 0xe7a2,
+ 0x7da7, 0xe79c, 0x7da6, 0xe796, 0x7da5, 0xe78f, 0x7da3, 0xe789,
+ 0x7da2, 0xe783, 0x7da1, 0xe77d, 0x7da0, 0xe777, 0x7d9f, 0xe771,
+ 0x7d9d, 0xe76a, 0x7d9c, 0xe764, 0x7d9b, 0xe75e, 0x7d9a, 0xe758,
+ 0x7d98, 0xe752, 0x7d97, 0xe74c, 0x7d96, 0xe745, 0x7d95, 0xe73f,
+ 0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
+ 0x7d8f, 0xe720, 0x7d8e, 0xe71a, 0x7d8c, 0xe714, 0x7d8b, 0xe70e,
+ 0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
+ 0x7d85, 0xe6ef, 0x7d84, 0xe6e9, 0x7d82, 0xe6e3, 0x7d81, 0xe6dd,
+ 0x7d80, 0xe6d6, 0x7d7f, 0xe6d0, 0x7d7e, 0xe6ca, 0x7d7c, 0xe6c4,
+ 0x7d7b, 0xe6be, 0x7d7a, 0xe6b8, 0x7d79, 0xe6b2, 0x7d77, 0xe6ab,
+ 0x7d76, 0xe6a5, 0x7d75, 0xe69f, 0x7d74, 0xe699, 0x7d72, 0xe693,
+ 0x7d71, 0xe68d, 0x7d70, 0xe686, 0x7d6f, 0xe680, 0x7d6d, 0xe67a,
+ 0x7d6c, 0xe674, 0x7d6b, 0xe66e, 0x7d6a, 0xe668, 0x7d68, 0xe661,
+ 0x7d67, 0xe65b, 0x7d66, 0xe655, 0x7d65, 0xe64f, 0x7d63, 0xe649,
+ 0x7d62, 0xe643, 0x7d61, 0xe63d, 0x7d60, 0xe636, 0x7d5e, 0xe630,
+ 0x7d5d, 0xe62a, 0x7d5c, 0xe624, 0x7d5a, 0xe61e, 0x7d59, 0xe618,
+ 0x7d58, 0xe611, 0x7d57, 0xe60b, 0x7d55, 0xe605, 0x7d54, 0xe5ff,
+ 0x7d53, 0xe5f9, 0x7d52, 0xe5f3, 0x7d50, 0xe5ed, 0x7d4f, 0xe5e6,
+ 0x7d4e, 0xe5e0, 0x7d4c, 0xe5da, 0x7d4b, 0xe5d4, 0x7d4a, 0xe5ce,
+ 0x7d49, 0xe5c8, 0x7d47, 0xe5c2, 0x7d46, 0xe5bb, 0x7d45, 0xe5b5,
+ 0x7d43, 0xe5af, 0x7d42, 0xe5a9, 0x7d41, 0xe5a3, 0x7d3f, 0xe59d,
+ 0x7d3e, 0xe596, 0x7d3d, 0xe590, 0x7d3c, 0xe58a, 0x7d3a, 0xe584,
+ 0x7d39, 0xe57e, 0x7d38, 0xe578, 0x7d36, 0xe572, 0x7d35, 0xe56b,
+ 0x7d34, 0xe565, 0x7d32, 0xe55f, 0x7d31, 0xe559, 0x7d30, 0xe553,
+ 0x7d2f, 0xe54d, 0x7d2d, 0xe547, 0x7d2c, 0xe540, 0x7d2b, 0xe53a,
+ 0x7d29, 0xe534, 0x7d28, 0xe52e, 0x7d27, 0xe528, 0x7d25, 0xe522,
+ 0x7d24, 0xe51c, 0x7d23, 0xe515, 0x7d21, 0xe50f, 0x7d20, 0xe509,
+ 0x7d1f, 0xe503, 0x7d1d, 0xe4fd, 0x7d1c, 0xe4f7, 0x7d1b, 0xe4f1,
+ 0x7d19, 0xe4ea, 0x7d18, 0xe4e4, 0x7d17, 0xe4de, 0x7d15, 0xe4d8,
+ 0x7d14, 0xe4d2, 0x7d13, 0xe4cc, 0x7d11, 0xe4c6, 0x7d10, 0xe4bf,
+ 0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
+ 0x7d09, 0xe4a1, 0x7d08, 0xe49b, 0x7d07, 0xe494, 0x7d05, 0xe48e,
+ 0x7d04, 0xe488, 0x7d03, 0xe482, 0x7d01, 0xe47c, 0x7d00, 0xe476,
+ 0x7cff, 0xe470, 0x7cfd, 0xe46a, 0x7cfc, 0xe463, 0x7cfb, 0xe45d,
+ 0x7cf9, 0xe457, 0x7cf8, 0xe451, 0x7cf6, 0xe44b, 0x7cf5, 0xe445,
+ 0x7cf4, 0xe43f, 0x7cf2, 0xe438, 0x7cf1, 0xe432, 0x7cf0, 0xe42c,
+ 0x7cee, 0xe426, 0x7ced, 0xe420, 0x7cec, 0xe41a, 0x7cea, 0xe414,
+ 0x7ce9, 0xe40e, 0x7ce7, 0xe407, 0x7ce6, 0xe401, 0x7ce5, 0xe3fb,
+ 0x7ce3, 0xe3f5, 0x7ce2, 0xe3ef, 0x7ce1, 0xe3e9, 0x7cdf, 0xe3e3,
+ 0x7cde, 0xe3dc, 0x7cdc, 0xe3d6, 0x7cdb, 0xe3d0, 0x7cda, 0xe3ca,
+ 0x7cd8, 0xe3c4, 0x7cd7, 0xe3be, 0x7cd5, 0xe3b8, 0x7cd4, 0xe3b2,
+ 0x7cd3, 0xe3ab, 0x7cd1, 0xe3a5, 0x7cd0, 0xe39f, 0x7ccf, 0xe399,
+ 0x7ccd, 0xe393, 0x7ccc, 0xe38d, 0x7cca, 0xe387, 0x7cc9, 0xe381,
+ 0x7cc8, 0xe37a, 0x7cc6, 0xe374, 0x7cc5, 0xe36e, 0x7cc3, 0xe368,
+ 0x7cc2, 0xe362, 0x7cc1, 0xe35c, 0x7cbf, 0xe356, 0x7cbe, 0xe350,
+ 0x7cbc, 0xe349, 0x7cbb, 0xe343, 0x7cb9, 0xe33d, 0x7cb8, 0xe337,
+ 0x7cb7, 0xe331, 0x7cb5, 0xe32b, 0x7cb4, 0xe325, 0x7cb2, 0xe31f,
+ 0x7cb1, 0xe318, 0x7cb0, 0xe312, 0x7cae, 0xe30c, 0x7cad, 0xe306,
+ 0x7cab, 0xe300, 0x7caa, 0xe2fa, 0x7ca8, 0xe2f4, 0x7ca7, 0xe2ee,
+ 0x7ca6, 0xe2e8, 0x7ca4, 0xe2e1, 0x7ca3, 0xe2db, 0x7ca1, 0xe2d5,
+ 0x7ca0, 0xe2cf, 0x7c9e, 0xe2c9, 0x7c9d, 0xe2c3, 0x7c9c, 0xe2bd,
+ 0x7c9a, 0xe2b7, 0x7c99, 0xe2b0, 0x7c97, 0xe2aa, 0x7c96, 0xe2a4,
+ 0x7c94, 0xe29e, 0x7c93, 0xe298, 0x7c91, 0xe292, 0x7c90, 0xe28c,
+ 0x7c8f, 0xe286, 0x7c8d, 0xe280, 0x7c8c, 0xe279, 0x7c8a, 0xe273,
+ 0x7c89, 0xe26d, 0x7c87, 0xe267, 0x7c86, 0xe261, 0x7c84, 0xe25b,
+ 0x7c83, 0xe255, 0x7c82, 0xe24f, 0x7c80, 0xe249, 0x7c7f, 0xe242,
+ 0x7c7d, 0xe23c, 0x7c7c, 0xe236, 0x7c7a, 0xe230, 0x7c79, 0xe22a,
+ 0x7c77, 0xe224, 0x7c76, 0xe21e, 0x7c74, 0xe218, 0x7c73, 0xe212,
+ 0x7c71, 0xe20b, 0x7c70, 0xe205, 0x7c6e, 0xe1ff, 0x7c6d, 0xe1f9,
+ 0x7c6c, 0xe1f3, 0x7c6a, 0xe1ed, 0x7c69, 0xe1e7, 0x7c67, 0xe1e1,
+ 0x7c66, 0xe1db, 0x7c64, 0xe1d4, 0x7c63, 0xe1ce, 0x7c61, 0xe1c8,
+ 0x7c60, 0xe1c2, 0x7c5e, 0xe1bc, 0x7c5d, 0xe1b6, 0x7c5b, 0xe1b0,
+ 0x7c5a, 0xe1aa, 0x7c58, 0xe1a4, 0x7c57, 0xe19e, 0x7c55, 0xe197,
+ 0x7c54, 0xe191, 0x7c52, 0xe18b, 0x7c51, 0xe185, 0x7c4f, 0xe17f,
+ 0x7c4e, 0xe179, 0x7c4c, 0xe173, 0x7c4b, 0xe16d, 0x7c49, 0xe167,
+ 0x7c48, 0xe160, 0x7c46, 0xe15a, 0x7c45, 0xe154, 0x7c43, 0xe14e,
+ 0x7c42, 0xe148, 0x7c40, 0xe142, 0x7c3f, 0xe13c, 0x7c3d, 0xe136,
+ 0x7c3c, 0xe130, 0x7c3a, 0xe12a, 0x7c39, 0xe123, 0x7c37, 0xe11d,
+ 0x7c36, 0xe117, 0x7c34, 0xe111, 0x7c33, 0xe10b, 0x7c31, 0xe105,
+ 0x7c30, 0xe0ff, 0x7c2e, 0xe0f9, 0x7c2d, 0xe0f3, 0x7c2b, 0xe0ed,
+ 0x7c29, 0xe0e7, 0x7c28, 0xe0e0, 0x7c26, 0xe0da, 0x7c25, 0xe0d4,
+ 0x7c23, 0xe0ce, 0x7c22, 0xe0c8, 0x7c20, 0xe0c2, 0x7c1f, 0xe0bc,
+ 0x7c1d, 0xe0b6, 0x7c1c, 0xe0b0, 0x7c1a, 0xe0aa, 0x7c19, 0xe0a3,
+ 0x7c17, 0xe09d, 0x7c16, 0xe097, 0x7c14, 0xe091, 0x7c12, 0xe08b,
+ 0x7c11, 0xe085, 0x7c0f, 0xe07f, 0x7c0e, 0xe079, 0x7c0c, 0xe073,
+ 0x7c0b, 0xe06d, 0x7c09, 0xe067, 0x7c08, 0xe061, 0x7c06, 0xe05a,
+ 0x7c05, 0xe054, 0x7c03, 0xe04e, 0x7c01, 0xe048, 0x7c00, 0xe042,
+ 0x7bfe, 0xe03c, 0x7bfd, 0xe036, 0x7bfb, 0xe030, 0x7bfa, 0xe02a,
+ 0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
+ 0x7bf2, 0xe00b, 0x7bf0, 0xe005, 0x7bef, 0xdfff, 0x7bed, 0xdff9,
+ 0x7beb, 0xdff3, 0x7bea, 0xdfed, 0x7be8, 0xdfe7, 0x7be7, 0xdfe1,
+ 0x7be5, 0xdfdb, 0x7be4, 0xdfd5, 0x7be2, 0xdfce, 0x7be0, 0xdfc8,
+ 0x7bdf, 0xdfc2, 0x7bdd, 0xdfbc, 0x7bdc, 0xdfb6, 0x7bda, 0xdfb0,
+ 0x7bd9, 0xdfaa, 0x7bd7, 0xdfa4, 0x7bd5, 0xdf9e, 0x7bd4, 0xdf98,
+ 0x7bd2, 0xdf92, 0x7bd1, 0xdf8c, 0x7bcf, 0xdf86, 0x7bcd, 0xdf7f,
+ 0x7bcc, 0xdf79, 0x7bca, 0xdf73, 0x7bc9, 0xdf6d, 0x7bc7, 0xdf67,
+ 0x7bc5, 0xdf61, 0x7bc4, 0xdf5b, 0x7bc2, 0xdf55, 0x7bc1, 0xdf4f,
+ 0x7bbf, 0xdf49, 0x7bbd, 0xdf43, 0x7bbc, 0xdf3d, 0x7bba, 0xdf37,
+ 0x7bb9, 0xdf30, 0x7bb7, 0xdf2a, 0x7bb5, 0xdf24, 0x7bb4, 0xdf1e,
+ 0x7bb2, 0xdf18, 0x7bb0, 0xdf12, 0x7baf, 0xdf0c, 0x7bad, 0xdf06,
+ 0x7bac, 0xdf00, 0x7baa, 0xdefa, 0x7ba8, 0xdef4, 0x7ba7, 0xdeee,
+ 0x7ba5, 0xdee8, 0x7ba3, 0xdee2, 0x7ba2, 0xdedb, 0x7ba0, 0xded5,
+ 0x7b9f, 0xdecf, 0x7b9d, 0xdec9, 0x7b9b, 0xdec3, 0x7b9a, 0xdebd,
+ 0x7b98, 0xdeb7, 0x7b96, 0xdeb1, 0x7b95, 0xdeab, 0x7b93, 0xdea5,
+ 0x7b92, 0xde9f, 0x7b90, 0xde99, 0x7b8e, 0xde93, 0x7b8d, 0xde8d,
+ 0x7b8b, 0xde87, 0x7b89, 0xde80, 0x7b88, 0xde7a, 0x7b86, 0xde74,
+ 0x7b84, 0xde6e, 0x7b83, 0xde68, 0x7b81, 0xde62, 0x7b7f, 0xde5c,
+ 0x7b7e, 0xde56, 0x7b7c, 0xde50, 0x7b7a, 0xde4a, 0x7b79, 0xde44,
+ 0x7b77, 0xde3e, 0x7b76, 0xde38, 0x7b74, 0xde32, 0x7b72, 0xde2c,
+ 0x7b71, 0xde26, 0x7b6f, 0xde1f, 0x7b6d, 0xde19, 0x7b6c, 0xde13,
+ 0x7b6a, 0xde0d, 0x7b68, 0xde07, 0x7b67, 0xde01, 0x7b65, 0xddfb,
+ 0x7b63, 0xddf5, 0x7b62, 0xddef, 0x7b60, 0xdde9, 0x7b5e, 0xdde3,
+ 0x7b5d, 0xdddd, 0x7b5b, 0xddd7, 0x7b59, 0xddd1, 0x7b57, 0xddcb,
+ 0x7b56, 0xddc5, 0x7b54, 0xddbf, 0x7b52, 0xddb9, 0x7b51, 0xddb2,
+ 0x7b4f, 0xddac, 0x7b4d, 0xdda6, 0x7b4c, 0xdda0, 0x7b4a, 0xdd9a,
+ 0x7b48, 0xdd94, 0x7b47, 0xdd8e, 0x7b45, 0xdd88, 0x7b43, 0xdd82,
+ 0x7b42, 0xdd7c, 0x7b40, 0xdd76, 0x7b3e, 0xdd70, 0x7b3c, 0xdd6a,
+ 0x7b3b, 0xdd64, 0x7b39, 0xdd5e, 0x7b37, 0xdd58, 0x7b36, 0xdd52,
+ 0x7b34, 0xdd4c, 0x7b32, 0xdd46, 0x7b31, 0xdd40, 0x7b2f, 0xdd39,
+ 0x7b2d, 0xdd33, 0x7b2b, 0xdd2d, 0x7b2a, 0xdd27, 0x7b28, 0xdd21,
+ 0x7b26, 0xdd1b, 0x7b25, 0xdd15, 0x7b23, 0xdd0f, 0x7b21, 0xdd09,
+ 0x7b1f, 0xdd03, 0x7b1e, 0xdcfd, 0x7b1c, 0xdcf7, 0x7b1a, 0xdcf1,
+ 0x7b19, 0xdceb, 0x7b17, 0xdce5, 0x7b15, 0xdcdf, 0x7b13, 0xdcd9,
+ 0x7b12, 0xdcd3, 0x7b10, 0xdccd, 0x7b0e, 0xdcc7, 0x7b0c, 0xdcc1,
+ 0x7b0b, 0xdcbb, 0x7b09, 0xdcb5, 0x7b07, 0xdcae, 0x7b06, 0xdca8,
+ 0x7b04, 0xdca2, 0x7b02, 0xdc9c, 0x7b00, 0xdc96, 0x7aff, 0xdc90,
+ 0x7afd, 0xdc8a, 0x7afb, 0xdc84, 0x7af9, 0xdc7e, 0x7af8, 0xdc78,
+ 0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
+ 0x7aef, 0xdc5a, 0x7aed, 0xdc54, 0x7aeb, 0xdc4e, 0x7aea, 0xdc48,
+ 0x7ae8, 0xdc42, 0x7ae6, 0xdc3c, 0x7ae4, 0xdc36, 0x7ae3, 0xdc30,
+ 0x7ae1, 0xdc2a, 0x7adf, 0xdc24, 0x7add, 0xdc1e, 0x7adc, 0xdc18,
+ 0x7ada, 0xdc12, 0x7ad8, 0xdc0c, 0x7ad6, 0xdc06, 0x7ad5, 0xdbff,
+ 0x7ad3, 0xdbf9, 0x7ad1, 0xdbf3, 0x7acf, 0xdbed, 0x7acd, 0xdbe7,
+ 0x7acc, 0xdbe1, 0x7aca, 0xdbdb, 0x7ac8, 0xdbd5, 0x7ac6, 0xdbcf,
+ 0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
+ 0x7abd, 0xdbb1, 0x7abc, 0xdbab, 0x7aba, 0xdba5, 0x7ab8, 0xdb9f,
+ 0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
+ 0x7aaf, 0xdb81, 0x7aad, 0xdb7b, 0x7aac, 0xdb75, 0x7aaa, 0xdb6f,
+ 0x7aa8, 0xdb69, 0x7aa6, 0xdb63, 0x7aa4, 0xdb5d, 0x7aa3, 0xdb57,
+ 0x7aa1, 0xdb51, 0x7a9f, 0xdb4b, 0x7a9d, 0xdb45, 0x7a9b, 0xdb3f,
+ 0x7a9a, 0xdb39, 0x7a98, 0xdb33, 0x7a96, 0xdb2d, 0x7a94, 0xdb27,
+ 0x7a92, 0xdb21, 0x7a91, 0xdb1b, 0x7a8f, 0xdb15, 0x7a8d, 0xdb0f,
+ 0x7a8b, 0xdb09, 0x7a89, 0xdb03, 0x7a87, 0xdafd, 0x7a86, 0xdaf7,
+ 0x7a84, 0xdaf1, 0x7a82, 0xdaea, 0x7a80, 0xdae4, 0x7a7e, 0xdade,
+ 0x7a7d, 0xdad8, 0x7a7b, 0xdad2, 0x7a79, 0xdacc, 0x7a77, 0xdac6,
+ 0x7a75, 0xdac0, 0x7a73, 0xdaba, 0x7a72, 0xdab4, 0x7a70, 0xdaae,
+ 0x7a6e, 0xdaa8, 0x7a6c, 0xdaa2, 0x7a6a, 0xda9c, 0x7a68, 0xda96,
+ 0x7a67, 0xda90, 0x7a65, 0xda8a, 0x7a63, 0xda84, 0x7a61, 0xda7e,
+ 0x7a5f, 0xda78, 0x7a5d, 0xda72, 0x7a5c, 0xda6c, 0x7a5a, 0xda66,
+ 0x7a58, 0xda60, 0x7a56, 0xda5a, 0x7a54, 0xda54, 0x7a52, 0xda4e,
+ 0x7a50, 0xda48, 0x7a4f, 0xda42, 0x7a4d, 0xda3c, 0x7a4b, 0xda36,
+ 0x7a49, 0xda30, 0x7a47, 0xda2a, 0x7a45, 0xda24, 0x7a43, 0xda1e,
+ 0x7a42, 0xda18, 0x7a40, 0xda12, 0x7a3e, 0xda0c, 0x7a3c, 0xda06,
+ 0x7a3a, 0xda00, 0x7a38, 0xd9fa, 0x7a36, 0xd9f4, 0x7a35, 0xd9ee,
+ 0x7a33, 0xd9e8, 0x7a31, 0xd9e2, 0x7a2f, 0xd9dc, 0x7a2d, 0xd9d6,
+ 0x7a2b, 0xd9d0, 0x7a29, 0xd9ca, 0x7a27, 0xd9c4, 0x7a26, 0xd9be,
+ 0x7a24, 0xd9b8, 0x7a22, 0xd9b2, 0x7a20, 0xd9ac, 0x7a1e, 0xd9a6,
+ 0x7a1c, 0xd9a0, 0x7a1a, 0xd99a, 0x7a18, 0xd994, 0x7a16, 0xd98e,
+ 0x7a15, 0xd988, 0x7a13, 0xd982, 0x7a11, 0xd97c, 0x7a0f, 0xd976,
+ 0x7a0d, 0xd970, 0x7a0b, 0xd96a, 0x7a09, 0xd964, 0x7a07, 0xd95e,
+ 0x7a05, 0xd958, 0x7a04, 0xd952, 0x7a02, 0xd94c, 0x7a00, 0xd946,
+ 0x79fe, 0xd940, 0x79fc, 0xd93a, 0x79fa, 0xd934, 0x79f8, 0xd92e,
+ 0x79f6, 0xd928, 0x79f4, 0xd922, 0x79f2, 0xd91c, 0x79f0, 0xd917,
+ 0x79ef, 0xd911, 0x79ed, 0xd90b, 0x79eb, 0xd905, 0x79e9, 0xd8ff,
+ 0x79e7, 0xd8f9, 0x79e5, 0xd8f3, 0x79e3, 0xd8ed, 0x79e1, 0xd8e7,
+ 0x79df, 0xd8e1, 0x79dd, 0xd8db, 0x79db, 0xd8d5, 0x79d9, 0xd8cf,
+ 0x79d8, 0xd8c9, 0x79d6, 0xd8c3, 0x79d4, 0xd8bd, 0x79d2, 0xd8b7,
+ 0x79d0, 0xd8b1, 0x79ce, 0xd8ab, 0x79cc, 0xd8a5, 0x79ca, 0xd89f,
+ 0x79c8, 0xd899, 0x79c6, 0xd893, 0x79c4, 0xd88d, 0x79c2, 0xd887,
+ 0x79c0, 0xd881, 0x79be, 0xd87b, 0x79bc, 0xd875, 0x79bb, 0xd86f,
+ 0x79b9, 0xd869, 0x79b7, 0xd863, 0x79b5, 0xd85d, 0x79b3, 0xd857,
+ 0x79b1, 0xd851, 0x79af, 0xd84b, 0x79ad, 0xd845, 0x79ab, 0xd83f,
+ 0x79a9, 0xd839, 0x79a7, 0xd833, 0x79a5, 0xd82d, 0x79a3, 0xd827,
+ 0x79a1, 0xd821, 0x799f, 0xd81b, 0x799d, 0xd815, 0x799b, 0xd80f,
+ 0x7999, 0xd80a, 0x7997, 0xd804, 0x7995, 0xd7fe, 0x7993, 0xd7f8,
+ 0x7992, 0xd7f2, 0x7990, 0xd7ec, 0x798e, 0xd7e6, 0x798c, 0xd7e0,
+ 0x798a, 0xd7da, 0x7988, 0xd7d4, 0x7986, 0xd7ce, 0x7984, 0xd7c8,
+ 0x7982, 0xd7c2, 0x7980, 0xd7bc, 0x797e, 0xd7b6, 0x797c, 0xd7b0,
+ 0x797a, 0xd7aa, 0x7978, 0xd7a4, 0x7976, 0xd79e, 0x7974, 0xd798,
+ 0x7972, 0xd792, 0x7970, 0xd78c, 0x796e, 0xd786, 0x796c, 0xd780,
+ 0x796a, 0xd77a, 0x7968, 0xd774, 0x7966, 0xd76e, 0x7964, 0xd768,
+ 0x7962, 0xd763, 0x7960, 0xd75d, 0x795e, 0xd757, 0x795c, 0xd751,
+ 0x795a, 0xd74b, 0x7958, 0xd745, 0x7956, 0xd73f, 0x7954, 0xd739,
+ 0x7952, 0xd733, 0x7950, 0xd72d, 0x794e, 0xd727, 0x794c, 0xd721,
+ 0x794a, 0xd71b, 0x7948, 0xd715, 0x7946, 0xd70f, 0x7944, 0xd709,
+ 0x7942, 0xd703, 0x7940, 0xd6fd, 0x793e, 0xd6f7, 0x793c, 0xd6f1,
+ 0x793a, 0xd6eb, 0x7938, 0xd6e5, 0x7936, 0xd6e0, 0x7934, 0xd6da,
+ 0x7932, 0xd6d4, 0x7930, 0xd6ce, 0x792e, 0xd6c8, 0x792c, 0xd6c2,
+ 0x792a, 0xd6bc, 0x7928, 0xd6b6, 0x7926, 0xd6b0, 0x7924, 0xd6aa,
+ 0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
+ 0x7919, 0xd68c, 0x7917, 0xd686, 0x7915, 0xd680, 0x7913, 0xd67a,
+ 0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
+ 0x7909, 0xd65d, 0x7907, 0xd657, 0x7905, 0xd651, 0x7903, 0xd64b,
+ 0x7901, 0xd645, 0x78ff, 0xd63f, 0x78fd, 0xd639, 0x78fb, 0xd633,
+ 0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
+ 0x78f1, 0xd615, 0x78ee, 0xd610, 0x78ec, 0xd60a, 0x78ea, 0xd604,
+ 0x78e8, 0xd5fe, 0x78e6, 0xd5f8, 0x78e4, 0xd5f2, 0x78e2, 0xd5ec,
+ 0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
+ 0x78d8, 0xd5ce, 0x78d6, 0xd5c8, 0x78d4, 0xd5c2, 0x78d2, 0xd5bc,
+ 0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
+ 0x78c7, 0xd59f, 0x78c5, 0xd599, 0x78c3, 0xd593, 0x78c1, 0xd58d,
+ 0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
+ 0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
+ 0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
+ 0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
+ 0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
+ 0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
+ 0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
+ 0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
+ 0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
+ 0x7873, 0xd4b2, 0x7871, 0xd4ac, 0x786f, 0xd4a6, 0x786d, 0xd4a0,
+ 0x786b, 0xd49a, 0x7868, 0xd494, 0x7866, 0xd48f, 0x7864, 0xd489,
+ 0x7862, 0xd483, 0x7860, 0xd47d, 0x785e, 0xd477, 0x785c, 0xd471,
+ 0x7859, 0xd46b, 0x7857, 0xd465, 0x7855, 0xd45f, 0x7853, 0xd459,
+ 0x7851, 0xd453, 0x784f, 0xd44e, 0x784d, 0xd448, 0x784a, 0xd442,
+ 0x7848, 0xd43c, 0x7846, 0xd436, 0x7844, 0xd430, 0x7842, 0xd42a,
+ 0x7840, 0xd424, 0x783e, 0xd41e, 0x783b, 0xd418, 0x7839, 0xd412,
+ 0x7837, 0xd40d, 0x7835, 0xd407, 0x7833, 0xd401, 0x7831, 0xd3fb,
+ 0x782e, 0xd3f5, 0x782c, 0xd3ef, 0x782a, 0xd3e9, 0x7828, 0xd3e3,
+ 0x7826, 0xd3dd, 0x7824, 0xd3d7, 0x7821, 0xd3d2, 0x781f, 0xd3cc,
+ 0x781d, 0xd3c6, 0x781b, 0xd3c0, 0x7819, 0xd3ba, 0x7817, 0xd3b4,
+ 0x7814, 0xd3ae, 0x7812, 0xd3a8, 0x7810, 0xd3a2, 0x780e, 0xd39d,
+ 0x780c, 0xd397, 0x780a, 0xd391, 0x7807, 0xd38b, 0x7805, 0xd385,
+ 0x7803, 0xd37f, 0x7801, 0xd379, 0x77ff, 0xd373, 0x77fc, 0xd36d,
+ 0x77fa, 0xd368, 0x77f8, 0xd362, 0x77f6, 0xd35c, 0x77f4, 0xd356,
+ 0x77f1, 0xd350, 0x77ef, 0xd34a, 0x77ed, 0xd344, 0x77eb, 0xd33e,
+ 0x77e9, 0xd338, 0x77e6, 0xd333, 0x77e4, 0xd32d, 0x77e2, 0xd327,
+ 0x77e0, 0xd321, 0x77de, 0xd31b, 0x77db, 0xd315, 0x77d9, 0xd30f,
+ 0x77d7, 0xd309, 0x77d5, 0xd303, 0x77d3, 0xd2fe, 0x77d0, 0xd2f8,
+ 0x77ce, 0xd2f2, 0x77cc, 0xd2ec, 0x77ca, 0xd2e6, 0x77c8, 0xd2e0,
+ 0x77c5, 0xd2da, 0x77c3, 0xd2d4, 0x77c1, 0xd2cf, 0x77bf, 0xd2c9,
+ 0x77bc, 0xd2c3, 0x77ba, 0xd2bd, 0x77b8, 0xd2b7, 0x77b6, 0xd2b1,
+ 0x77b4, 0xd2ab, 0x77b1, 0xd2a5, 0x77af, 0xd2a0, 0x77ad, 0xd29a,
+ 0x77ab, 0xd294, 0x77a8, 0xd28e, 0x77a6, 0xd288, 0x77a4, 0xd282,
+ 0x77a2, 0xd27c, 0x77a0, 0xd276, 0x779d, 0xd271, 0x779b, 0xd26b,
+ 0x7799, 0xd265, 0x7797, 0xd25f, 0x7794, 0xd259, 0x7792, 0xd253,
+ 0x7790, 0xd24d, 0x778e, 0xd247, 0x778b, 0xd242, 0x7789, 0xd23c,
+ 0x7787, 0xd236, 0x7785, 0xd230, 0x7782, 0xd22a, 0x7780, 0xd224,
+ 0x777e, 0xd21e, 0x777c, 0xd219, 0x7779, 0xd213, 0x7777, 0xd20d,
+ 0x7775, 0xd207, 0x7773, 0xd201, 0x7770, 0xd1fb, 0x776e, 0xd1f5,
+ 0x776c, 0xd1ef, 0x776a, 0xd1ea, 0x7767, 0xd1e4, 0x7765, 0xd1de,
+ 0x7763, 0xd1d8, 0x7760, 0xd1d2, 0x775e, 0xd1cc, 0x775c, 0xd1c6,
+ 0x775a, 0xd1c1, 0x7757, 0xd1bb, 0x7755, 0xd1b5, 0x7753, 0xd1af,
+ 0x7751, 0xd1a9, 0x774e, 0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,
+ 0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,
+ 0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,
+ 0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,
+ 0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,
+ 0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,
+ 0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,
+ 0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,
+ 0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,
+ 0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,
+ 0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,
+ 0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,
+ 0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,
+ 0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,
+ 0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,
+ 0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,
+ 0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,
+ 0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,
+ 0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,
+ 0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,
+ 0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,
+ 0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,
+ 0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,
+ 0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,
+ 0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,
+ 0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,
+ 0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,
+ 0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,
+ 0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,
+ 0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,
+ 0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,
+ 0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,
+ 0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,
+ 0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,
+ 0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,
+ 0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,
+ 0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,
+ 0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,
+ 0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,
+ 0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,
+ 0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,
+ 0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,
+ 0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,
+ 0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,
+ 0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,
+ 0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,
+ 0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,
+ 0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,
+ 0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,
+ 0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,
+ 0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,
+ 0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,
+ 0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,
+ 0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,
+ 0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,
+ 0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,
+ 0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,
+ 0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,
+ 0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,
+ 0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,
+ 0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,
+ 0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,
+ 0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,
+ 0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,
+ 0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,
+ 0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,
+ 0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,
+ 0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,
+ 0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,
+ 0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,
+ 0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,
+ 0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,
+ 0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,
+ 0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,
+ 0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,
+ 0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,
+ 0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,
+ 0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,
+ 0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,
+ 0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,
+ 0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,
+ 0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,
+ 0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,
+ 0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,
+ 0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,
+ 0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,
+ 0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,
+ 0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,
+ 0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,
+ 0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,
+ 0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,
+ 0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,
+ 0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,
+ 0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,
+ 0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,
+ 0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,
+ 0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,
+ 0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,
+ 0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,
+ 0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,
+ 0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,
+ 0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,
+ 0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,
+ 0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,
+ 0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,
+ 0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,
+ 0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,
+ 0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,
+ 0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,
+ 0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,
+ 0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,
+ 0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,
+ 0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,
+ 0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,
+ 0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,
+ 0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,
+ 0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,
+ 0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,
+ 0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,
+ 0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,
+ 0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,
+ 0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,
+ 0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,
+ 0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,
+ 0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,
+ 0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,
+ 0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,
+ 0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,
+ 0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,
+ 0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,
+ 0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,
+ 0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,
+ 0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,
+ 0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,
+ 0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,
+ 0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,
+ 0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,
+ 0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,
+ 0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,
+ 0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,
+ 0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,
+ 0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,
+ 0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,
+ 0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,
+ 0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,
+ 0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,
+ 0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,
+ 0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,
+ 0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,
+ 0x7141, 0xc45b, 0x713e, 0xc456, 0x713b, 0xc450, 0x7138, 0xc44b,
+ 0x7135, 0xc445, 0x7132, 0xc440, 0x712f, 0xc43a, 0x712c, 0xc434,
+ 0x7129, 0xc42f, 0x7126, 0xc429, 0x7123, 0xc424, 0x7120, 0xc41e,
+ 0x711d, 0xc419, 0x711a, 0xc413, 0x7117, 0xc40e, 0x7114, 0xc408,
+ 0x7112, 0xc403, 0x710f, 0xc3fd, 0x710c, 0xc3f7, 0x7109, 0xc3f2,
+ 0x7106, 0xc3ec, 0x7103, 0xc3e7, 0x7100, 0xc3e1, 0x70fd, 0xc3dc,
+ 0x70fa, 0xc3d6, 0x70f7, 0xc3d1, 0x70f4, 0xc3cb, 0x70f1, 0xc3c5,
+ 0x70ee, 0xc3c0, 0x70eb, 0xc3ba, 0x70e8, 0xc3b5, 0x70e5, 0xc3af,
+ 0x70e2, 0xc3aa, 0x70df, 0xc3a4, 0x70dc, 0xc39f, 0x70d9, 0xc399,
+ 0x70d6, 0xc394, 0x70d3, 0xc38e, 0x70d1, 0xc389, 0x70ce, 0xc383,
+ 0x70cb, 0xc37d, 0x70c8, 0xc378, 0x70c5, 0xc372, 0x70c2, 0xc36d,
+ 0x70bf, 0xc367, 0x70bc, 0xc362, 0x70b9, 0xc35c, 0x70b6, 0xc357,
+ 0x70b3, 0xc351, 0x70b0, 0xc34c, 0x70ad, 0xc346, 0x70aa, 0xc341,
+ 0x70a7, 0xc33b, 0x70a4, 0xc336, 0x70a1, 0xc330, 0x709e, 0xc32a,
+ 0x709b, 0xc325, 0x7098, 0xc31f, 0x7095, 0xc31a, 0x7092, 0xc314,
+ 0x708f, 0xc30f, 0x708c, 0xc309, 0x7089, 0xc304, 0x7086, 0xc2fe,
+ 0x7083, 0xc2f9, 0x7080, 0xc2f3, 0x707d, 0xc2ee, 0x707a, 0xc2e8,
+ 0x7077, 0xc2e3, 0x7074, 0xc2dd, 0x7071, 0xc2d8, 0x706e, 0xc2d2,
+ 0x706b, 0xc2cd, 0x7068, 0xc2c7, 0x7065, 0xc2c2, 0x7062, 0xc2bc,
+ 0x705f, 0xc2b7, 0x705c, 0xc2b1, 0x7059, 0xc2ab, 0x7056, 0xc2a6,
+ 0x7053, 0xc2a0, 0x7050, 0xc29b, 0x704d, 0xc295, 0x704a, 0xc290,
+ 0x7047, 0xc28a, 0x7044, 0xc285, 0x7041, 0xc27f, 0x703e, 0xc27a,
+ 0x703b, 0xc274, 0x7038, 0xc26f, 0x7035, 0xc269, 0x7032, 0xc264,
+ 0x702f, 0xc25e, 0x702c, 0xc259, 0x7029, 0xc253, 0x7026, 0xc24e,
+ 0x7023, 0xc248, 0x7020, 0xc243, 0x701d, 0xc23d, 0x7019, 0xc238,
+ 0x7016, 0xc232, 0x7013, 0xc22d, 0x7010, 0xc227, 0x700d, 0xc222,
+ 0x700a, 0xc21c, 0x7007, 0xc217, 0x7004, 0xc211, 0x7001, 0xc20c,
+ 0x6ffe, 0xc206, 0x6ffb, 0xc201, 0x6ff8, 0xc1fb, 0x6ff5, 0xc1f6,
+ 0x6ff2, 0xc1f0, 0x6fef, 0xc1eb, 0x6fec, 0xc1e5, 0x6fe9, 0xc1e0,
+ 0x6fe6, 0xc1da, 0x6fe3, 0xc1d5, 0x6fe0, 0xc1cf, 0x6fdd, 0xc1ca,
+ 0x6fda, 0xc1c4, 0x6fd6, 0xc1bf, 0x6fd3, 0xc1b9, 0x6fd0, 0xc1b4,
+ 0x6fcd, 0xc1ae, 0x6fca, 0xc1a9, 0x6fc7, 0xc1a3, 0x6fc4, 0xc19e,
+ 0x6fc1, 0xc198, 0x6fbe, 0xc193, 0x6fbb, 0xc18d, 0x6fb8, 0xc188,
+ 0x6fb5, 0xc183, 0x6fb2, 0xc17d, 0x6faf, 0xc178, 0x6fac, 0xc172,
+ 0x6fa9, 0xc16d, 0x6fa5, 0xc167, 0x6fa2, 0xc162, 0x6f9f, 0xc15c,
+ 0x6f9c, 0xc157, 0x6f99, 0xc151, 0x6f96, 0xc14c, 0x6f93, 0xc146,
+ 0x6f90, 0xc141, 0x6f8d, 0xc13b, 0x6f8a, 0xc136, 0x6f87, 0xc130,
+ 0x6f84, 0xc12b, 0x6f81, 0xc125, 0x6f7d, 0xc120, 0x6f7a, 0xc11a,
+ 0x6f77, 0xc115, 0x6f74, 0xc10f, 0x6f71, 0xc10a, 0x6f6e, 0xc105,
+ 0x6f6b, 0xc0ff, 0x6f68, 0xc0fa, 0x6f65, 0xc0f4, 0x6f62, 0xc0ef,
+ 0x6f5f, 0xc0e9, 0x6f5b, 0xc0e4, 0x6f58, 0xc0de, 0x6f55, 0xc0d9,
+ 0x6f52, 0xc0d3, 0x6f4f, 0xc0ce, 0x6f4c, 0xc0c8, 0x6f49, 0xc0c3,
+ 0x6f46, 0xc0bd, 0x6f43, 0xc0b8, 0x6f3f, 0xc0b3, 0x6f3c, 0xc0ad,
+ 0x6f39, 0xc0a8, 0x6f36, 0xc0a2, 0x6f33, 0xc09d, 0x6f30, 0xc097,
+ 0x6f2d, 0xc092, 0x6f2a, 0xc08c, 0x6f27, 0xc087, 0x6f23, 0xc081,
+ 0x6f20, 0xc07c, 0x6f1d, 0xc077, 0x6f1a, 0xc071, 0x6f17, 0xc06c,
+ 0x6f14, 0xc066, 0x6f11, 0xc061, 0x6f0e, 0xc05b, 0x6f0b, 0xc056,
+ 0x6f07, 0xc050, 0x6f04, 0xc04b, 0x6f01, 0xc045, 0x6efe, 0xc040,
+ 0x6efb, 0xc03b, 0x6ef8, 0xc035, 0x6ef5, 0xc030, 0x6ef1, 0xc02a,
+ 0x6eee, 0xc025, 0x6eeb, 0xc01f, 0x6ee8, 0xc01a, 0x6ee5, 0xc014,
+ 0x6ee2, 0xc00f, 0x6edf, 0xc00a, 0x6edc, 0xc004, 0x6ed8, 0xbfff,
+ 0x6ed5, 0xbff9, 0x6ed2, 0xbff4, 0x6ecf, 0xbfee, 0x6ecc, 0xbfe9,
+ 0x6ec9, 0xbfe3, 0x6ec6, 0xbfde, 0x6ec2, 0xbfd9, 0x6ebf, 0xbfd3,
+ 0x6ebc, 0xbfce, 0x6eb9, 0xbfc8, 0x6eb6, 0xbfc3, 0x6eb3, 0xbfbd,
+ 0x6eaf, 0xbfb8, 0x6eac, 0xbfb3, 0x6ea9, 0xbfad, 0x6ea6, 0xbfa8,
+ 0x6ea3, 0xbfa2, 0x6ea0, 0xbf9d, 0x6e9c, 0xbf97, 0x6e99, 0xbf92,
+ 0x6e96, 0xbf8d, 0x6e93, 0xbf87, 0x6e90, 0xbf82, 0x6e8d, 0xbf7c,
+ 0x6e89, 0xbf77, 0x6e86, 0xbf71, 0x6e83, 0xbf6c, 0x6e80, 0xbf67,
+ 0x6e7d, 0xbf61, 0x6e7a, 0xbf5c, 0x6e76, 0xbf56, 0x6e73, 0xbf51,
+ 0x6e70, 0xbf4b, 0x6e6d, 0xbf46, 0x6e6a, 0xbf41, 0x6e67, 0xbf3b,
+ 0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,
+ 0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,
+ 0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,
+ 0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,
+ 0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,
+ 0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,
+ 0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,
+ 0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,
+ 0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,
+ 0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,
+ 0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,
+ 0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,
+ 0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,
+ 0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,
+ 0x6db0, 0xbe07, 0x6dac, 0xbe02, 0x6da9, 0xbdfd, 0x6da6, 0xbdf7,
+ 0x6da3, 0xbdf2, 0x6d9f, 0xbdec, 0x6d9c, 0xbde7, 0x6d99, 0xbde2,
+ 0x6d96, 0xbddc, 0x6d92, 0xbdd7, 0x6d8f, 0xbdd1, 0x6d8c, 0xbdcc,
+ 0x6d89, 0xbdc7, 0x6d85, 0xbdc1, 0x6d82, 0xbdbc, 0x6d7f, 0xbdb7,
+ 0x6d7c, 0xbdb1, 0x6d78, 0xbdac, 0x6d75, 0xbda6, 0x6d72, 0xbda1,
+ 0x6d6f, 0xbd9c, 0x6d6b, 0xbd96, 0x6d68, 0xbd91, 0x6d65, 0xbd8c,
+ 0x6d62, 0xbd86, 0x6d5e, 0xbd81, 0x6d5b, 0xbd7c, 0x6d58, 0xbd76,
+ 0x6d55, 0xbd71, 0x6d51, 0xbd6b, 0x6d4e, 0xbd66, 0x6d4b, 0xbd61,
+ 0x6d48, 0xbd5b, 0x6d44, 0xbd56, 0x6d41, 0xbd51, 0x6d3e, 0xbd4b,
+ 0x6d3a, 0xbd46, 0x6d37, 0xbd40, 0x6d34, 0xbd3b, 0x6d31, 0xbd36,
+ 0x6d2d, 0xbd30, 0x6d2a, 0xbd2b, 0x6d27, 0xbd26, 0x6d23, 0xbd20,
+ 0x6d20, 0xbd1b, 0x6d1d, 0xbd16, 0x6d1a, 0xbd10, 0x6d16, 0xbd0b,
+ 0x6d13, 0xbd06, 0x6d10, 0xbd00, 0x6d0c, 0xbcfb, 0x6d09, 0xbcf5,
+ 0x6d06, 0xbcf0, 0x6d03, 0xbceb, 0x6cff, 0xbce5, 0x6cfc, 0xbce0,
+ 0x6cf9, 0xbcdb, 0x6cf5, 0xbcd5, 0x6cf2, 0xbcd0, 0x6cef, 0xbccb,
+ 0x6cec, 0xbcc5, 0x6ce8, 0xbcc0, 0x6ce5, 0xbcbb, 0x6ce2, 0xbcb5,
+ 0x6cde, 0xbcb0, 0x6cdb, 0xbcab, 0x6cd8, 0xbca5, 0x6cd4, 0xbca0,
+ 0x6cd1, 0xbc9b, 0x6cce, 0xbc95, 0x6cca, 0xbc90, 0x6cc7, 0xbc8b,
+ 0x6cc4, 0xbc85, 0x6cc1, 0xbc80, 0x6cbd, 0xbc7b, 0x6cba, 0xbc75,
+ 0x6cb7, 0xbc70, 0x6cb3, 0xbc6b, 0x6cb0, 0xbc65, 0x6cad, 0xbc60,
+ 0x6ca9, 0xbc5b, 0x6ca6, 0xbc55, 0x6ca3, 0xbc50, 0x6c9f, 0xbc4b,
+ 0x6c9c, 0xbc45, 0x6c99, 0xbc40, 0x6c95, 0xbc3b, 0x6c92, 0xbc35,
+ 0x6c8f, 0xbc30, 0x6c8b, 0xbc2b, 0x6c88, 0xbc25, 0x6c85, 0xbc20,
+ 0x6c81, 0xbc1b, 0x6c7e, 0xbc15, 0x6c7b, 0xbc10, 0x6c77, 0xbc0b,
+ 0x6c74, 0xbc05, 0x6c71, 0xbc00, 0x6c6d, 0xbbfb, 0x6c6a, 0xbbf5,
+ 0x6c67, 0xbbf0, 0x6c63, 0xbbeb, 0x6c60, 0xbbe5, 0x6c5d, 0xbbe0,
+ 0x6c59, 0xbbdb, 0x6c56, 0xbbd5, 0x6c53, 0xbbd0, 0x6c4f, 0xbbcb,
+ 0x6c4c, 0xbbc5, 0x6c49, 0xbbc0, 0x6c45, 0xbbbb, 0x6c42, 0xbbb5,
+ 0x6c3f, 0xbbb0, 0x6c3b, 0xbbab, 0x6c38, 0xbba6, 0x6c34, 0xbba0,
+ 0x6c31, 0xbb9b, 0x6c2e, 0xbb96, 0x6c2a, 0xbb90, 0x6c27, 0xbb8b,
+ 0x6c24, 0xbb86, 0x6c20, 0xbb80, 0x6c1d, 0xbb7b, 0x6c1a, 0xbb76,
+ 0x6c16, 0xbb70, 0x6c13, 0xbb6b, 0x6c0f, 0xbb66, 0x6c0c, 0xbb61,
+ 0x6c09, 0xbb5b, 0x6c05, 0xbb56, 0x6c02, 0xbb51, 0x6bff, 0xbb4b,
+ 0x6bfb, 0xbb46, 0x6bf8, 0xbb41, 0x6bf5, 0xbb3b, 0x6bf1, 0xbb36,
+ 0x6bee, 0xbb31, 0x6bea, 0xbb2c, 0x6be7, 0xbb26, 0x6be4, 0xbb21,
+ 0x6be0, 0xbb1c, 0x6bdd, 0xbb16, 0x6bd9, 0xbb11, 0x6bd6, 0xbb0c,
+ 0x6bd3, 0xbb06, 0x6bcf, 0xbb01, 0x6bcc, 0xbafc, 0x6bc9, 0xbaf7,
+ 0x6bc5, 0xbaf1, 0x6bc2, 0xbaec, 0x6bbe, 0xbae7, 0x6bbb, 0xbae1,
+ 0x6bb8, 0xbadc, 0x6bb4, 0xbad7, 0x6bb1, 0xbad2, 0x6bad, 0xbacc,
+ 0x6baa, 0xbac7, 0x6ba7, 0xbac2, 0x6ba3, 0xbabc, 0x6ba0, 0xbab7,
+ 0x6b9c, 0xbab2, 0x6b99, 0xbaad, 0x6b96, 0xbaa7, 0x6b92, 0xbaa2,
+ 0x6b8f, 0xba9d, 0x6b8b, 0xba97, 0x6b88, 0xba92, 0x6b85, 0xba8d,
+ 0x6b81, 0xba88, 0x6b7e, 0xba82, 0x6b7a, 0xba7d, 0x6b77, 0xba78,
+ 0x6b73, 0xba73, 0x6b70, 0xba6d, 0x6b6d, 0xba68, 0x6b69, 0xba63,
+ 0x6b66, 0xba5d, 0x6b62, 0xba58, 0x6b5f, 0xba53, 0x6b5c, 0xba4e,
+ 0x6b58, 0xba48, 0x6b55, 0xba43, 0x6b51, 0xba3e, 0x6b4e, 0xba39,
+ 0x6b4a, 0xba33, 0x6b47, 0xba2e, 0x6b44, 0xba29, 0x6b40, 0xba23,
+ 0x6b3d, 0xba1e, 0x6b39, 0xba19, 0x6b36, 0xba14, 0x6b32, 0xba0e,
+ 0x6b2f, 0xba09, 0x6b2c, 0xba04, 0x6b28, 0xb9ff, 0x6b25, 0xb9f9,
+ 0x6b21, 0xb9f4, 0x6b1e, 0xb9ef, 0x6b1a, 0xb9ea, 0x6b17, 0xb9e4,
+ 0x6b13, 0xb9df, 0x6b10, 0xb9da, 0x6b0d, 0xb9d5, 0x6b09, 0xb9cf,
+ 0x6b06, 0xb9ca, 0x6b02, 0xb9c5, 0x6aff, 0xb9c0, 0x6afb, 0xb9ba,
+ 0x6af8, 0xb9b5, 0x6af4, 0xb9b0, 0x6af1, 0xb9ab, 0x6aee, 0xb9a5,
+ 0x6aea, 0xb9a0, 0x6ae7, 0xb99b, 0x6ae3, 0xb996, 0x6ae0, 0xb990,
+ 0x6adc, 0xb98b, 0x6ad9, 0xb986, 0x6ad5, 0xb981, 0x6ad2, 0xb97b,
+ 0x6ace, 0xb976, 0x6acb, 0xb971, 0x6ac8, 0xb96c, 0x6ac4, 0xb966,
+ 0x6ac1, 0xb961, 0x6abd, 0xb95c, 0x6aba, 0xb957, 0x6ab6, 0xb951,
+ 0x6ab3, 0xb94c, 0x6aaf, 0xb947, 0x6aac, 0xb942, 0x6aa8, 0xb93c,
+ 0x6aa5, 0xb937, 0x6aa1, 0xb932, 0x6a9e, 0xb92d, 0x6a9a, 0xb928,
+ 0x6a97, 0xb922, 0x6a93, 0xb91d, 0x6a90, 0xb918, 0x6a8c, 0xb913,
+ 0x6a89, 0xb90d, 0x6a86, 0xb908, 0x6a82, 0xb903, 0x6a7f, 0xb8fe,
+ 0x6a7b, 0xb8f8, 0x6a78, 0xb8f3, 0x6a74, 0xb8ee, 0x6a71, 0xb8e9,
+ 0x6a6d, 0xb8e4, 0x6a6a, 0xb8de, 0x6a66, 0xb8d9, 0x6a63, 0xb8d4,
+ 0x6a5f, 0xb8cf, 0x6a5c, 0xb8c9, 0x6a58, 0xb8c4, 0x6a55, 0xb8bf,
+ 0x6a51, 0xb8ba, 0x6a4e, 0xb8b5, 0x6a4a, 0xb8af, 0x6a47, 0xb8aa,
+ 0x6a43, 0xb8a5, 0x6a40, 0xb8a0, 0x6a3c, 0xb89b, 0x6a39, 0xb895,
+ 0x6a35, 0xb890, 0x6a32, 0xb88b, 0x6a2e, 0xb886, 0x6a2b, 0xb880,
+ 0x6a27, 0xb87b, 0x6a24, 0xb876, 0x6a20, 0xb871, 0x6a1d, 0xb86c,
+ 0x6a19, 0xb866, 0x6a16, 0xb861, 0x6a12, 0xb85c, 0x6a0e, 0xb857,
+ 0x6a0b, 0xb852, 0x6a07, 0xb84c, 0x6a04, 0xb847, 0x6a00, 0xb842,
+ 0x69fd, 0xb83d, 0x69f9, 0xb838, 0x69f6, 0xb832, 0x69f2, 0xb82d,
+ 0x69ef, 0xb828, 0x69eb, 0xb823, 0x69e8, 0xb81e, 0x69e4, 0xb818,
+ 0x69e1, 0xb813, 0x69dd, 0xb80e, 0x69da, 0xb809, 0x69d6, 0xb804,
+ 0x69d3, 0xb7fe, 0x69cf, 0xb7f9, 0x69cb, 0xb7f4, 0x69c8, 0xb7ef,
+ 0x69c4, 0xb7ea, 0x69c1, 0xb7e4, 0x69bd, 0xb7df, 0x69ba, 0xb7da,
+ 0x69b6, 0xb7d5, 0x69b3, 0xb7d0, 0x69af, 0xb7ca, 0x69ac, 0xb7c5,
+ 0x69a8, 0xb7c0, 0x69a5, 0xb7bb, 0x69a1, 0xb7b6, 0x699d, 0xb7b1,
+ 0x699a, 0xb7ab, 0x6996, 0xb7a6, 0x6993, 0xb7a1, 0x698f, 0xb79c,
+ 0x698c, 0xb797, 0x6988, 0xb791, 0x6985, 0xb78c, 0x6981, 0xb787,
+ 0x697d, 0xb782, 0x697a, 0xb77d, 0x6976, 0xb778, 0x6973, 0xb772,
+ 0x696f, 0xb76d, 0x696c, 0xb768, 0x6968, 0xb763, 0x6964, 0xb75e,
+ 0x6961, 0xb758, 0x695d, 0xb753, 0x695a, 0xb74e, 0x6956, 0xb749,
+ 0x6953, 0xb744, 0x694f, 0xb73f, 0x694b, 0xb739, 0x6948, 0xb734,
+ 0x6944, 0xb72f, 0x6941, 0xb72a, 0x693d, 0xb725, 0x693a, 0xb720,
+ 0x6936, 0xb71a, 0x6932, 0xb715, 0x692f, 0xb710, 0x692b, 0xb70b,
+ 0x6928, 0xb706, 0x6924, 0xb701, 0x6921, 0xb6fb, 0x691d, 0xb6f6,
+ 0x6919, 0xb6f1, 0x6916, 0xb6ec, 0x6912, 0xb6e7, 0x690f, 0xb6e2,
+ 0x690b, 0xb6dd, 0x6907, 0xb6d7, 0x6904, 0xb6d2, 0x6900, 0xb6cd,
+ 0x68fd, 0xb6c8, 0x68f9, 0xb6c3, 0x68f5, 0xb6be, 0x68f2, 0xb6b8,
+ 0x68ee, 0xb6b3, 0x68eb, 0xb6ae, 0x68e7, 0xb6a9, 0x68e3, 0xb6a4,
+ 0x68e0, 0xb69f, 0x68dc, 0xb69a, 0x68d9, 0xb694, 0x68d5, 0xb68f,
+ 0x68d1, 0xb68a, 0x68ce, 0xb685, 0x68ca, 0xb680, 0x68c7, 0xb67b,
+ 0x68c3, 0xb676, 0x68bf, 0xb670, 0x68bc, 0xb66b, 0x68b8, 0xb666,
+ 0x68b5, 0xb661, 0x68b1, 0xb65c, 0x68ad, 0xb657, 0x68aa, 0xb652,
+ 0x68a6, 0xb64c, 0x68a3, 0xb647, 0x689f, 0xb642, 0x689b, 0xb63d,
+ 0x6898, 0xb638, 0x6894, 0xb633, 0x6890, 0xb62e, 0x688d, 0xb628,
+ 0x6889, 0xb623, 0x6886, 0xb61e, 0x6882, 0xb619, 0x687e, 0xb614,
+ 0x687b, 0xb60f, 0x6877, 0xb60a, 0x6873, 0xb605, 0x6870, 0xb5ff,
+ 0x686c, 0xb5fa, 0x6868, 0xb5f5, 0x6865, 0xb5f0, 0x6861, 0xb5eb,
+ 0x685e, 0xb5e6, 0x685a, 0xb5e1, 0x6856, 0xb5dc, 0x6853, 0xb5d6,
+ 0x684f, 0xb5d1, 0x684b, 0xb5cc, 0x6848, 0xb5c7, 0x6844, 0xb5c2,
+ 0x6840, 0xb5bd, 0x683d, 0xb5b8, 0x6839, 0xb5b3, 0x6835, 0xb5ae,
+ 0x6832, 0xb5a8, 0x682e, 0xb5a3, 0x682b, 0xb59e, 0x6827, 0xb599,
+ 0x6823, 0xb594, 0x6820, 0xb58f, 0x681c, 0xb58a, 0x6818, 0xb585,
+ 0x6815, 0xb57f, 0x6811, 0xb57a, 0x680d, 0xb575, 0x680a, 0xb570,
+ 0x6806, 0xb56b, 0x6802, 0xb566, 0x67ff, 0xb561, 0x67fb, 0xb55c,
+ 0x67f7, 0xb557, 0x67f4, 0xb552, 0x67f0, 0xb54c, 0x67ec, 0xb547,
+ 0x67e9, 0xb542, 0x67e5, 0xb53d, 0x67e1, 0xb538, 0x67de, 0xb533,
+ 0x67da, 0xb52e, 0x67d6, 0xb529, 0x67d3, 0xb524, 0x67cf, 0xb51f,
+ 0x67cb, 0xb519, 0x67c8, 0xb514, 0x67c4, 0xb50f, 0x67c0, 0xb50a,
+ 0x67bd, 0xb505, 0x67b9, 0xb500, 0x67b5, 0xb4fb, 0x67b2, 0xb4f6,
+ 0x67ae, 0xb4f1, 0x67aa, 0xb4ec, 0x67a6, 0xb4e7, 0x67a3, 0xb4e1,
+ 0x679f, 0xb4dc, 0x679b, 0xb4d7, 0x6798, 0xb4d2, 0x6794, 0xb4cd,
+ 0x6790, 0xb4c8, 0x678d, 0xb4c3, 0x6789, 0xb4be, 0x6785, 0xb4b9,
+ 0x6782, 0xb4b4, 0x677e, 0xb4af, 0x677a, 0xb4aa, 0x6776, 0xb4a4,
+ 0x6773, 0xb49f, 0x676f, 0xb49a, 0x676b, 0xb495, 0x6768, 0xb490,
+ 0x6764, 0xb48b, 0x6760, 0xb486, 0x675d, 0xb481, 0x6759, 0xb47c,
+ 0x6755, 0xb477, 0x6751, 0xb472, 0x674e, 0xb46d, 0x674a, 0xb468,
+ 0x6746, 0xb462, 0x6743, 0xb45d, 0x673f, 0xb458, 0x673b, 0xb453,
+ 0x6737, 0xb44e, 0x6734, 0xb449, 0x6730, 0xb444, 0x672c, 0xb43f,
+ 0x6729, 0xb43a, 0x6725, 0xb435, 0x6721, 0xb430, 0x671d, 0xb42b,
+ 0x671a, 0xb426, 0x6716, 0xb421, 0x6712, 0xb41c, 0x670e, 0xb417,
+ 0x670b, 0xb411, 0x6707, 0xb40c, 0x6703, 0xb407, 0x6700, 0xb402,
+ 0x66fc, 0xb3fd, 0x66f8, 0xb3f8, 0x66f4, 0xb3f3, 0x66f1, 0xb3ee,
+ 0x66ed, 0xb3e9, 0x66e9, 0xb3e4, 0x66e5, 0xb3df, 0x66e2, 0xb3da,
+ 0x66de, 0xb3d5, 0x66da, 0xb3d0, 0x66d6, 0xb3cb, 0x66d3, 0xb3c6,
+ 0x66cf, 0xb3c1, 0x66cb, 0xb3bc, 0x66c8, 0xb3b7, 0x66c4, 0xb3b1,
+ 0x66c0, 0xb3ac, 0x66bc, 0xb3a7, 0x66b9, 0xb3a2, 0x66b5, 0xb39d,
+ 0x66b1, 0xb398, 0x66ad, 0xb393, 0x66aa, 0xb38e, 0x66a6, 0xb389,
+ 0x66a2, 0xb384, 0x669e, 0xb37f, 0x669b, 0xb37a, 0x6697, 0xb375,
+ 0x6693, 0xb370, 0x668f, 0xb36b, 0x668b, 0xb366, 0x6688, 0xb361,
+ 0x6684, 0xb35c, 0x6680, 0xb357, 0x667c, 0xb352, 0x6679, 0xb34d,
+ 0x6675, 0xb348, 0x6671, 0xb343, 0x666d, 0xb33e, 0x666a, 0xb339,
+ 0x6666, 0xb334, 0x6662, 0xb32f, 0x665e, 0xb32a, 0x665b, 0xb325,
+ 0x6657, 0xb31f, 0x6653, 0xb31a, 0x664f, 0xb315, 0x664b, 0xb310,
+ 0x6648, 0xb30b, 0x6644, 0xb306, 0x6640, 0xb301, 0x663c, 0xb2fc,
+ 0x6639, 0xb2f7, 0x6635, 0xb2f2, 0x6631, 0xb2ed, 0x662d, 0xb2e8,
+ 0x6629, 0xb2e3, 0x6626, 0xb2de, 0x6622, 0xb2d9, 0x661e, 0xb2d4,
+ 0x661a, 0xb2cf, 0x6616, 0xb2ca, 0x6613, 0xb2c5, 0x660f, 0xb2c0,
+ 0x660b, 0xb2bb, 0x6607, 0xb2b6, 0x6603, 0xb2b1, 0x6600, 0xb2ac,
+ 0x65fc, 0xb2a7, 0x65f8, 0xb2a2, 0x65f4, 0xb29d, 0x65f0, 0xb298,
+ 0x65ed, 0xb293, 0x65e9, 0xb28e, 0x65e5, 0xb289, 0x65e1, 0xb284,
+ 0x65dd, 0xb27f, 0x65da, 0xb27a, 0x65d6, 0xb275, 0x65d2, 0xb270,
+ 0x65ce, 0xb26b, 0x65ca, 0xb266, 0x65c7, 0xb261, 0x65c3, 0xb25c,
+ 0x65bf, 0xb257, 0x65bb, 0xb252, 0x65b7, 0xb24d, 0x65b4, 0xb248,
+ 0x65b0, 0xb243, 0x65ac, 0xb23e, 0x65a8, 0xb239, 0x65a4, 0xb234,
+ 0x65a0, 0xb22f, 0x659d, 0xb22a, 0x6599, 0xb225, 0x6595, 0xb220,
+ 0x6591, 0xb21b, 0x658d, 0xb216, 0x658a, 0xb211, 0x6586, 0xb20c,
+ 0x6582, 0xb207, 0x657e, 0xb202, 0x657a, 0xb1fd, 0x6576, 0xb1f8,
+ 0x6573, 0xb1f3, 0x656f, 0xb1ee, 0x656b, 0xb1e9, 0x6567, 0xb1e4,
+ 0x6563, 0xb1df, 0x655f, 0xb1da, 0x655c, 0xb1d6, 0x6558, 0xb1d1,
+ 0x6554, 0xb1cc, 0x6550, 0xb1c7, 0x654c, 0xb1c2, 0x6548, 0xb1bd,
+ 0x6545, 0xb1b8, 0x6541, 0xb1b3, 0x653d, 0xb1ae, 0x6539, 0xb1a9,
+ 0x6535, 0xb1a4, 0x6531, 0xb19f, 0x652d, 0xb19a, 0x652a, 0xb195,
+ 0x6526, 0xb190, 0x6522, 0xb18b, 0x651e, 0xb186, 0x651a, 0xb181,
+ 0x6516, 0xb17c, 0x6513, 0xb177, 0x650f, 0xb172, 0x650b, 0xb16d,
+ 0x6507, 0xb168, 0x6503, 0xb163, 0x64ff, 0xb15e, 0x64fb, 0xb159,
+ 0x64f7, 0xb154, 0x64f4, 0xb14f, 0x64f0, 0xb14a, 0x64ec, 0xb146,
+ 0x64e8, 0xb141, 0x64e4, 0xb13c, 0x64e0, 0xb137, 0x64dc, 0xb132,
+ 0x64d9, 0xb12d, 0x64d5, 0xb128, 0x64d1, 0xb123, 0x64cd, 0xb11e,
+ 0x64c9, 0xb119, 0x64c5, 0xb114, 0x64c1, 0xb10f, 0x64bd, 0xb10a,
+ 0x64ba, 0xb105, 0x64b6, 0xb100, 0x64b2, 0xb0fb, 0x64ae, 0xb0f6,
+ 0x64aa, 0xb0f1, 0x64a6, 0xb0ec, 0x64a2, 0xb0e8, 0x649e, 0xb0e3,
+ 0x649b, 0xb0de, 0x6497, 0xb0d9, 0x6493, 0xb0d4, 0x648f, 0xb0cf,
+ 0x648b, 0xb0ca, 0x6487, 0xb0c5, 0x6483, 0xb0c0, 0x647f, 0xb0bb,
+ 0x647b, 0xb0b6, 0x6478, 0xb0b1, 0x6474, 0xb0ac, 0x6470, 0xb0a7,
+ 0x646c, 0xb0a2, 0x6468, 0xb09e, 0x6464, 0xb099, 0x6460, 0xb094,
+ 0x645c, 0xb08f, 0x6458, 0xb08a, 0x6454, 0xb085, 0x6451, 0xb080,
+ 0x644d, 0xb07b, 0x6449, 0xb076, 0x6445, 0xb071, 0x6441, 0xb06c,
+ 0x643d, 0xb067, 0x6439, 0xb062, 0x6435, 0xb05e, 0x6431, 0xb059,
+ 0x642d, 0xb054, 0x6429, 0xb04f, 0x6426, 0xb04a, 0x6422, 0xb045,
+ 0x641e, 0xb040, 0x641a, 0xb03b, 0x6416, 0xb036, 0x6412, 0xb031,
+ 0x640e, 0xb02c, 0x640a, 0xb027, 0x6406, 0xb023, 0x6402, 0xb01e,
+ 0x63fe, 0xb019, 0x63fa, 0xb014, 0x63f7, 0xb00f, 0x63f3, 0xb00a,
+ 0x63ef, 0xb005, 0x63eb, 0xb000, 0x63e7, 0xaffb, 0x63e3, 0xaff6,
+ 0x63df, 0xaff1, 0x63db, 0xafed, 0x63d7, 0xafe8, 0x63d3, 0xafe3,
+ 0x63cf, 0xafde, 0x63cb, 0xafd9, 0x63c7, 0xafd4, 0x63c3, 0xafcf,
+ 0x63c0, 0xafca, 0x63bc, 0xafc5, 0x63b8, 0xafc1, 0x63b4, 0xafbc,
+ 0x63b0, 0xafb7, 0x63ac, 0xafb2, 0x63a8, 0xafad, 0x63a4, 0xafa8,
+ 0x63a0, 0xafa3, 0x639c, 0xaf9e, 0x6398, 0xaf99, 0x6394, 0xaf94,
+ 0x6390, 0xaf90, 0x638c, 0xaf8b, 0x6388, 0xaf86, 0x6384, 0xaf81,
+ 0x6380, 0xaf7c, 0x637c, 0xaf77, 0x6378, 0xaf72, 0x6375, 0xaf6d,
+ 0x6371, 0xaf69, 0x636d, 0xaf64, 0x6369, 0xaf5f, 0x6365, 0xaf5a,
+ 0x6361, 0xaf55, 0x635d, 0xaf50, 0x6359, 0xaf4b, 0x6355, 0xaf46,
+ 0x6351, 0xaf41, 0x634d, 0xaf3d, 0x6349, 0xaf38, 0x6345, 0xaf33,
+ 0x6341, 0xaf2e, 0x633d, 0xaf29, 0x6339, 0xaf24, 0x6335, 0xaf1f,
+ 0x6331, 0xaf1b, 0x632d, 0xaf16, 0x6329, 0xaf11, 0x6325, 0xaf0c,
+ 0x6321, 0xaf07, 0x631d, 0xaf02, 0x6319, 0xaefd, 0x6315, 0xaef8,
+ 0x6311, 0xaef4, 0x630d, 0xaeef, 0x6309, 0xaeea, 0x6305, 0xaee5,
+ 0x6301, 0xaee0, 0x62fd, 0xaedb, 0x62f9, 0xaed6, 0x62f5, 0xaed2,
+ 0x62f2, 0xaecd, 0x62ee, 0xaec8, 0x62ea, 0xaec3, 0x62e6, 0xaebe,
+ 0x62e2, 0xaeb9, 0x62de, 0xaeb4, 0x62da, 0xaeb0, 0x62d6, 0xaeab,
+ 0x62d2, 0xaea6, 0x62ce, 0xaea1, 0x62ca, 0xae9c, 0x62c6, 0xae97,
+ 0x62c2, 0xae92, 0x62be, 0xae8e, 0x62ba, 0xae89, 0x62b6, 0xae84,
+ 0x62b2, 0xae7f, 0x62ae, 0xae7a, 0x62aa, 0xae75, 0x62a6, 0xae71,
+ 0x62a2, 0xae6c, 0x629e, 0xae67, 0x629a, 0xae62, 0x6296, 0xae5d,
+ 0x6292, 0xae58, 0x628e, 0xae54, 0x628a, 0xae4f, 0x6286, 0xae4a,
+ 0x6282, 0xae45, 0x627e, 0xae40, 0x627a, 0xae3b, 0x6275, 0xae37,
+ 0x6271, 0xae32, 0x626d, 0xae2d, 0x6269, 0xae28, 0x6265, 0xae23,
+ 0x6261, 0xae1e, 0x625d, 0xae1a, 0x6259, 0xae15, 0x6255, 0xae10,
+ 0x6251, 0xae0b, 0x624d, 0xae06, 0x6249, 0xae01, 0x6245, 0xadfd,
+ 0x6241, 0xadf8, 0x623d, 0xadf3, 0x6239, 0xadee, 0x6235, 0xade9,
+ 0x6231, 0xade4, 0x622d, 0xade0, 0x6229, 0xaddb, 0x6225, 0xadd6,
+ 0x6221, 0xadd1, 0x621d, 0xadcc, 0x6219, 0xadc8, 0x6215, 0xadc3,
+ 0x6211, 0xadbe, 0x620d, 0xadb9, 0x6209, 0xadb4, 0x6205, 0xadaf,
+ 0x6201, 0xadab, 0x61fd, 0xada6, 0x61f9, 0xada1, 0x61f5, 0xad9c,
+ 0x61f1, 0xad97, 0x61ec, 0xad93, 0x61e8, 0xad8e, 0x61e4, 0xad89,
+ 0x61e0, 0xad84, 0x61dc, 0xad7f, 0x61d8, 0xad7b, 0x61d4, 0xad76,
+ 0x61d0, 0xad71, 0x61cc, 0xad6c, 0x61c8, 0xad67, 0x61c4, 0xad63,
+ 0x61c0, 0xad5e, 0x61bc, 0xad59, 0x61b8, 0xad54, 0x61b4, 0xad4f,
+ 0x61b0, 0xad4b, 0x61ac, 0xad46, 0x61a8, 0xad41, 0x61a3, 0xad3c,
+ 0x619f, 0xad37, 0x619b, 0xad33, 0x6197, 0xad2e, 0x6193, 0xad29,
+ 0x618f, 0xad24, 0x618b, 0xad1f, 0x6187, 0xad1b, 0x6183, 0xad16,
+ 0x617f, 0xad11, 0x617b, 0xad0c, 0x6177, 0xad08, 0x6173, 0xad03,
+ 0x616f, 0xacfe, 0x616b, 0xacf9, 0x6166, 0xacf4, 0x6162, 0xacf0,
+ 0x615e, 0xaceb, 0x615a, 0xace6, 0x6156, 0xace1, 0x6152, 0xacdd,
+ 0x614e, 0xacd8, 0x614a, 0xacd3, 0x6146, 0xacce, 0x6142, 0xacc9,
+ 0x613e, 0xacc5, 0x613a, 0xacc0, 0x6135, 0xacbb, 0x6131, 0xacb6,
+ 0x612d, 0xacb2, 0x6129, 0xacad, 0x6125, 0xaca8, 0x6121, 0xaca3,
+ 0x611d, 0xac9e, 0x6119, 0xac9a, 0x6115, 0xac95, 0x6111, 0xac90,
+ 0x610d, 0xac8b, 0x6108, 0xac87, 0x6104, 0xac82, 0x6100, 0xac7d,
+ 0x60fc, 0xac78, 0x60f8, 0xac74, 0x60f4, 0xac6f, 0x60f0, 0xac6a,
+ 0x60ec, 0xac65, 0x60e8, 0xac61, 0x60e4, 0xac5c, 0x60df, 0xac57,
+ 0x60db, 0xac52, 0x60d7, 0xac4e, 0x60d3, 0xac49, 0x60cf, 0xac44,
+ 0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,
+ 0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,
+ 0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,
+ 0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,
+ 0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,
+ 0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,
+ 0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,
+ 0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,
+ 0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,
+ 0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,
+ 0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,
+ 0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,
+ 0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,
+ 0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,
+ 0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,
+ 0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,
+ 0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,
+ 0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,
+ 0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,
+ 0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,
+ 0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,
+ 0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,
+ 0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,
+ 0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,
+ 0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,
+ 0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,
+ 0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,
+ 0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,
+ 0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,
+ 0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,
+ 0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,
+ 0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,
+ 0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,
+ 0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,
+ 0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,
+ 0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,
+ 0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,
+ 0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,
+ 0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,
+ 0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,
+ 0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,
+ 0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,
+ 0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,
+ 0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,
+ 0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,
+ 0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
+ 0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
+ 0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
+ 0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
+ 0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
+ 0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
+ 0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
+ 0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
+ 0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
+ 0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
+ 0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
+ 0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
+ 0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
+ 0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
+ 0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
+ 0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
+ 0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
+ 0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
+ 0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
+ 0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
+ 0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
+ 0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
+ 0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
+ 0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
+ 0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
+ 0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
+ 0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
+ 0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
+ 0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
+ 0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
+ 0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
+ 0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
+ 0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
+ 0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
+ 0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
+ 0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
+ 0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
+ 0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
+ 0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
+ 0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
+ 0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
+ 0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
+ 0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
+ 0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
+ 0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
+ 0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
+ 0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
+ 0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
+ 0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
+ 0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
+ 0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
+ 0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
+ 0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
+ 0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
+ 0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
+ 0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
+ 0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
+ 0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
+ 0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
+ 0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
+ 0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
+ 0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
+ 0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
+ 0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
+ 0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
+ 0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
+ 0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
+ 0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
+ 0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
+ 0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
+ 0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
+ 0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
+ 0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
+ 0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
+ 0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
+ 0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
+ 0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
+ 0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
+ 0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
+ 0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
+ 0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
+ 0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
+ 0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
+ 0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
+ 0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
+ 0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
+ 0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
+ 0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
+ 0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
+ 0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
+ 0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
+ 0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
+ 0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
+ 0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
+ 0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
+ 0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
+ 0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
+ 0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
+ 0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
+ 0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
+ 0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
+ 0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
+ 0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
+ 0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
+ 0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
+ 0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
+ 0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
+ 0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,
+ 0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
+ 0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
+ 0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
+ 0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
+ 0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
+ 0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
+ 0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,
+ 0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,
+ 0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
+ 0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
+ 0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,
+ 0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
+ 0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,
+ 0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
+ 0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,
+ 0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,
+ 0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,
+ 0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,
+ 0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,
+ 0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,
+ 0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,
+ 0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,
+ 0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
+ 0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
+ 0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
+ 0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
+ 0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,
+ 0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,
+ 0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,
+ 0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,
+ 0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,
+ 0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,
+ 0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,
+ 0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,
+ 0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,
+ 0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,
+ 0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,
+ 0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,
+ 0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,
+ 0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,
+ 0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,
+ 0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,
+ 0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,
+ 0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,
+ 0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,
+ 0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,
+ 0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,
+ 0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,
+ 0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,
+ 0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,
+ 0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,
+ 0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,
+ 0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,
+ 0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,
+ 0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,
+ 0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,
+ 0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,
+ 0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,
+ 0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,
+ 0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,
+ 0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,
+ 0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,
+ 0x51bb, 0x9d7e, 0x51b6, 0x9d7a, 0x51b1, 0x9d76, 0x51ac, 0x9d72,
+ 0x51a8, 0x9d6e, 0x51a3, 0x9d6a, 0x519e, 0x9d66, 0x5199, 0x9d62,
+ 0x5194, 0x9d5e, 0x518f, 0x9d5a, 0x518b, 0x9d56, 0x5186, 0x9d52,
+ 0x5181, 0x9d4e, 0x517c, 0x9d4a, 0x5177, 0x9d46, 0x5172, 0x9d42,
+ 0x516e, 0x9d3e, 0x5169, 0x9d3a, 0x5164, 0x9d36, 0x515f, 0x9d32,
+ 0x515a, 0x9d2e, 0x5155, 0x9d2a, 0x5150, 0x9d26, 0x514c, 0x9d22,
+ 0x5147, 0x9d1e, 0x5142, 0x9d1a, 0x513d, 0x9d16, 0x5138, 0x9d12,
+ 0x5133, 0x9d0e, 0x512e, 0x9d0b, 0x512a, 0x9d07, 0x5125, 0x9d03,
+ 0x5120, 0x9cff, 0x511b, 0x9cfb, 0x5116, 0x9cf7, 0x5111, 0x9cf3,
+ 0x510c, 0x9cef, 0x5108, 0x9ceb, 0x5103, 0x9ce7, 0x50fe, 0x9ce3,
+ 0x50f9, 0x9cdf, 0x50f4, 0x9cdb, 0x50ef, 0x9cd7, 0x50ea, 0x9cd3,
+ 0x50e5, 0x9ccf, 0x50e1, 0x9ccb, 0x50dc, 0x9cc7, 0x50d7, 0x9cc3,
+ 0x50d2, 0x9cbf, 0x50cd, 0x9cbb, 0x50c8, 0x9cb7, 0x50c3, 0x9cb3,
+ 0x50bf, 0x9caf, 0x50ba, 0x9cab, 0x50b5, 0x9ca7, 0x50b0, 0x9ca3,
+ 0x50ab, 0x9c9f, 0x50a6, 0x9c9b, 0x50a1, 0x9c97, 0x509c, 0x9c93,
+ 0x5097, 0x9c8f, 0x5093, 0x9c8b, 0x508e, 0x9c88, 0x5089, 0x9c84,
+ 0x5084, 0x9c80, 0x507f, 0x9c7c, 0x507a, 0x9c78, 0x5075, 0x9c74,
+ 0x5070, 0x9c70, 0x506c, 0x9c6c, 0x5067, 0x9c68, 0x5062, 0x9c64,
+ 0x505d, 0x9c60, 0x5058, 0x9c5c, 0x5053, 0x9c58, 0x504e, 0x9c54,
+ 0x5049, 0x9c50, 0x5044, 0x9c4c, 0x503f, 0x9c48, 0x503b, 0x9c44,
+ 0x5036, 0x9c40, 0x5031, 0x9c3d, 0x502c, 0x9c39, 0x5027, 0x9c35,
+ 0x5022, 0x9c31, 0x501d, 0x9c2d, 0x5018, 0x9c29, 0x5013, 0x9c25,
+ 0x500f, 0x9c21, 0x500a, 0x9c1d, 0x5005, 0x9c19, 0x5000, 0x9c15,
+ 0x4ffb, 0x9c11, 0x4ff6, 0x9c0d, 0x4ff1, 0x9c09, 0x4fec, 0x9c06,
+ 0x4fe7, 0x9c02, 0x4fe2, 0x9bfe, 0x4fdd, 0x9bfa, 0x4fd9, 0x9bf6,
+ 0x4fd4, 0x9bf2, 0x4fcf, 0x9bee, 0x4fca, 0x9bea, 0x4fc5, 0x9be6,
+ 0x4fc0, 0x9be2, 0x4fbb, 0x9bde, 0x4fb6, 0x9bda, 0x4fb1, 0x9bd7,
+ 0x4fac, 0x9bd3, 0x4fa7, 0x9bcf, 0x4fa2, 0x9bcb, 0x4f9e, 0x9bc7,
+ 0x4f99, 0x9bc3, 0x4f94, 0x9bbf, 0x4f8f, 0x9bbb, 0x4f8a, 0x9bb7,
+ 0x4f85, 0x9bb3, 0x4f80, 0x9baf, 0x4f7b, 0x9bac, 0x4f76, 0x9ba8,
+ 0x4f71, 0x9ba4, 0x4f6c, 0x9ba0, 0x4f67, 0x9b9c, 0x4f62, 0x9b98,
+ 0x4f5e, 0x9b94, 0x4f59, 0x9b90, 0x4f54, 0x9b8c, 0x4f4f, 0x9b88,
+ 0x4f4a, 0x9b85, 0x4f45, 0x9b81, 0x4f40, 0x9b7d, 0x4f3b, 0x9b79,
+ 0x4f36, 0x9b75, 0x4f31, 0x9b71, 0x4f2c, 0x9b6d, 0x4f27, 0x9b69,
+ 0x4f22, 0x9b65, 0x4f1d, 0x9b62, 0x4f18, 0x9b5e, 0x4f14, 0x9b5a,
+ 0x4f0f, 0x9b56, 0x4f0a, 0x9b52, 0x4f05, 0x9b4e, 0x4f00, 0x9b4a,
+ 0x4efb, 0x9b46, 0x4ef6, 0x9b43, 0x4ef1, 0x9b3f, 0x4eec, 0x9b3b,
+ 0x4ee7, 0x9b37, 0x4ee2, 0x9b33, 0x4edd, 0x9b2f, 0x4ed8, 0x9b2b,
+ 0x4ed3, 0x9b27, 0x4ece, 0x9b24, 0x4ec9, 0x9b20, 0x4ec4, 0x9b1c,
+ 0x4ebf, 0x9b18, 0x4eba, 0x9b14, 0x4eb6, 0x9b10, 0x4eb1, 0x9b0c,
+ 0x4eac, 0x9b09, 0x4ea7, 0x9b05, 0x4ea2, 0x9b01, 0x4e9d, 0x9afd,
+ 0x4e98, 0x9af9, 0x4e93, 0x9af5, 0x4e8e, 0x9af1, 0x4e89, 0x9aed,
+ 0x4e84, 0x9aea, 0x4e7f, 0x9ae6, 0x4e7a, 0x9ae2, 0x4e75, 0x9ade,
+ 0x4e70, 0x9ada, 0x4e6b, 0x9ad6, 0x4e66, 0x9ad3, 0x4e61, 0x9acf,
+ 0x4e5c, 0x9acb, 0x4e57, 0x9ac7, 0x4e52, 0x9ac3, 0x4e4d, 0x9abf,
+ 0x4e48, 0x9abb, 0x4e43, 0x9ab8, 0x4e3e, 0x9ab4, 0x4e39, 0x9ab0,
+ 0x4e34, 0x9aac, 0x4e2f, 0x9aa8, 0x4e2a, 0x9aa4, 0x4e26, 0x9aa1,
+ 0x4e21, 0x9a9d, 0x4e1c, 0x9a99, 0x4e17, 0x9a95, 0x4e12, 0x9a91,
+ 0x4e0d, 0x9a8d, 0x4e08, 0x9a8a, 0x4e03, 0x9a86, 0x4dfe, 0x9a82,
+ 0x4df9, 0x9a7e, 0x4df4, 0x9a7a, 0x4def, 0x9a76, 0x4dea, 0x9a73,
+ 0x4de5, 0x9a6f, 0x4de0, 0x9a6b, 0x4ddb, 0x9a67, 0x4dd6, 0x9a63,
+ 0x4dd1, 0x9a60, 0x4dcc, 0x9a5c, 0x4dc7, 0x9a58, 0x4dc2, 0x9a54,
+ 0x4dbd, 0x9a50, 0x4db8, 0x9a4c, 0x4db3, 0x9a49, 0x4dae, 0x9a45,
+ 0x4da9, 0x9a41, 0x4da4, 0x9a3d, 0x4d9f, 0x9a39, 0x4d9a, 0x9a36,
+ 0x4d95, 0x9a32, 0x4d90, 0x9a2e, 0x4d8b, 0x9a2a, 0x4d86, 0x9a26,
+ 0x4d81, 0x9a23, 0x4d7c, 0x9a1f, 0x4d77, 0x9a1b, 0x4d72, 0x9a17,
+ 0x4d6d, 0x9a13, 0x4d68, 0x9a10, 0x4d63, 0x9a0c, 0x4d5e, 0x9a08,
+ 0x4d59, 0x9a04, 0x4d54, 0x9a00, 0x4d4f, 0x99fd, 0x4d4a, 0x99f9,
+ 0x4d45, 0x99f5, 0x4d40, 0x99f1, 0x4d3b, 0x99ed, 0x4d36, 0x99ea,
+ 0x4d31, 0x99e6, 0x4d2c, 0x99e2, 0x4d27, 0x99de, 0x4d22, 0x99da,
+ 0x4d1d, 0x99d7, 0x4d18, 0x99d3, 0x4d13, 0x99cf, 0x4d0e, 0x99cb,
+ 0x4d09, 0x99c7, 0x4d04, 0x99c4, 0x4cff, 0x99c0, 0x4cfa, 0x99bc,
+ 0x4cf5, 0x99b8, 0x4cf0, 0x99b5, 0x4ceb, 0x99b1, 0x4ce6, 0x99ad,
+ 0x4ce1, 0x99a9, 0x4cdb, 0x99a5, 0x4cd6, 0x99a2, 0x4cd1, 0x999e,
+ 0x4ccc, 0x999a, 0x4cc7, 0x9996, 0x4cc2, 0x9993, 0x4cbd, 0x998f,
+ 0x4cb8, 0x998b, 0x4cb3, 0x9987, 0x4cae, 0x9984, 0x4ca9, 0x9980,
+ 0x4ca4, 0x997c, 0x4c9f, 0x9978, 0x4c9a, 0x9975, 0x4c95, 0x9971,
+ 0x4c90, 0x996d, 0x4c8b, 0x9969, 0x4c86, 0x9965, 0x4c81, 0x9962,
+ 0x4c7c, 0x995e, 0x4c77, 0x995a, 0x4c72, 0x9956, 0x4c6d, 0x9953,
+ 0x4c68, 0x994f, 0x4c63, 0x994b, 0x4c5e, 0x9947, 0x4c59, 0x9944,
+ 0x4c54, 0x9940, 0x4c4f, 0x993c, 0x4c49, 0x9938, 0x4c44, 0x9935,
+ 0x4c3f, 0x9931, 0x4c3a, 0x992d, 0x4c35, 0x992a, 0x4c30, 0x9926,
+ 0x4c2b, 0x9922, 0x4c26, 0x991e, 0x4c21, 0x991b, 0x4c1c, 0x9917,
+ 0x4c17, 0x9913, 0x4c12, 0x990f, 0x4c0d, 0x990c, 0x4c08, 0x9908,
+ 0x4c03, 0x9904, 0x4bfe, 0x9900, 0x4bf9, 0x98fd, 0x4bf4, 0x98f9,
+ 0x4bef, 0x98f5, 0x4be9, 0x98f2, 0x4be4, 0x98ee, 0x4bdf, 0x98ea,
+ 0x4bda, 0x98e6, 0x4bd5, 0x98e3, 0x4bd0, 0x98df, 0x4bcb, 0x98db,
+ 0x4bc6, 0x98d7, 0x4bc1, 0x98d4, 0x4bbc, 0x98d0, 0x4bb7, 0x98cc,
+ 0x4bb2, 0x98c9, 0x4bad, 0x98c5, 0x4ba8, 0x98c1, 0x4ba3, 0x98bd,
+ 0x4b9e, 0x98ba, 0x4b98, 0x98b6, 0x4b93, 0x98b2, 0x4b8e, 0x98af,
+ 0x4b89, 0x98ab, 0x4b84, 0x98a7, 0x4b7f, 0x98a3, 0x4b7a, 0x98a0,
+ 0x4b75, 0x989c, 0x4b70, 0x9898, 0x4b6b, 0x9895, 0x4b66, 0x9891,
+ 0x4b61, 0x988d, 0x4b5c, 0x988a, 0x4b56, 0x9886, 0x4b51, 0x9882,
+ 0x4b4c, 0x987e, 0x4b47, 0x987b, 0x4b42, 0x9877, 0x4b3d, 0x9873,
+ 0x4b38, 0x9870, 0x4b33, 0x986c, 0x4b2e, 0x9868, 0x4b29, 0x9865,
+ 0x4b24, 0x9861, 0x4b1f, 0x985d, 0x4b19, 0x985a, 0x4b14, 0x9856,
+ 0x4b0f, 0x9852, 0x4b0a, 0x984e, 0x4b05, 0x984b, 0x4b00, 0x9847,
+ 0x4afb, 0x9843, 0x4af6, 0x9840, 0x4af1, 0x983c, 0x4aec, 0x9838,
+ 0x4ae7, 0x9835, 0x4ae1, 0x9831, 0x4adc, 0x982d, 0x4ad7, 0x982a,
+ 0x4ad2, 0x9826, 0x4acd, 0x9822, 0x4ac8, 0x981f, 0x4ac3, 0x981b,
+ 0x4abe, 0x9817, 0x4ab9, 0x9814, 0x4ab4, 0x9810, 0x4aae, 0x980c,
+ 0x4aa9, 0x9809, 0x4aa4, 0x9805, 0x4a9f, 0x9801, 0x4a9a, 0x97fe,
+ 0x4a95, 0x97fa, 0x4a90, 0x97f6, 0x4a8b, 0x97f3, 0x4a86, 0x97ef,
+ 0x4a81, 0x97eb, 0x4a7b, 0x97e8, 0x4a76, 0x97e4, 0x4a71, 0x97e0,
+ 0x4a6c, 0x97dd, 0x4a67, 0x97d9, 0x4a62, 0x97d5, 0x4a5d, 0x97d2,
+ 0x4a58, 0x97ce, 0x4a52, 0x97cb, 0x4a4d, 0x97c7, 0x4a48, 0x97c3,
+ 0x4a43, 0x97c0, 0x4a3e, 0x97bc, 0x4a39, 0x97b8, 0x4a34, 0x97b5,
+ 0x4a2f, 0x97b1, 0x4a2a, 0x97ad, 0x4a24, 0x97aa, 0x4a1f, 0x97a6,
+ 0x4a1a, 0x97a2, 0x4a15, 0x979f, 0x4a10, 0x979b, 0x4a0b, 0x9798,
+ 0x4a06, 0x9794, 0x4a01, 0x9790, 0x49fb, 0x978d, 0x49f6, 0x9789,
+ 0x49f1, 0x9785, 0x49ec, 0x9782, 0x49e7, 0x977e, 0x49e2, 0x977a,
+ 0x49dd, 0x9777, 0x49d8, 0x9773, 0x49d2, 0x9770, 0x49cd, 0x976c,
+ 0x49c8, 0x9768, 0x49c3, 0x9765, 0x49be, 0x9761, 0x49b9, 0x975d,
+ 0x49b4, 0x975a, 0x49ae, 0x9756, 0x49a9, 0x9753, 0x49a4, 0x974f,
+ 0x499f, 0x974b, 0x499a, 0x9748, 0x4995, 0x9744, 0x4990, 0x9741,
+ 0x498a, 0x973d, 0x4985, 0x9739, 0x4980, 0x9736, 0x497b, 0x9732,
+ 0x4976, 0x972f, 0x4971, 0x972b, 0x496c, 0x9727, 0x4966, 0x9724,
+ 0x4961, 0x9720, 0x495c, 0x971d, 0x4957, 0x9719, 0x4952, 0x9715,
+ 0x494d, 0x9712, 0x4948, 0x970e, 0x4942, 0x970b, 0x493d, 0x9707,
+ 0x4938, 0x9703, 0x4933, 0x9700, 0x492e, 0x96fc, 0x4929, 0x96f9,
+ 0x4923, 0x96f5, 0x491e, 0x96f1, 0x4919, 0x96ee, 0x4914, 0x96ea,
+ 0x490f, 0x96e7, 0x490a, 0x96e3, 0x4905, 0x96df, 0x48ff, 0x96dc,
+ 0x48fa, 0x96d8, 0x48f5, 0x96d5, 0x48f0, 0x96d1, 0x48eb, 0x96ce,
+ 0x48e6, 0x96ca, 0x48e0, 0x96c6, 0x48db, 0x96c3, 0x48d6, 0x96bf,
+ 0x48d1, 0x96bc, 0x48cc, 0x96b8, 0x48c7, 0x96b5, 0x48c1, 0x96b1,
+ 0x48bc, 0x96ad, 0x48b7, 0x96aa, 0x48b2, 0x96a6, 0x48ad, 0x96a3,
+ 0x48a8, 0x969f, 0x48a2, 0x969c, 0x489d, 0x9698, 0x4898, 0x9694,
+ 0x4893, 0x9691, 0x488e, 0x968d, 0x4888, 0x968a, 0x4883, 0x9686,
+ 0x487e, 0x9683, 0x4879, 0x967f, 0x4874, 0x967b, 0x486f, 0x9678,
+ 0x4869, 0x9674, 0x4864, 0x9671, 0x485f, 0x966d, 0x485a, 0x966a,
+ 0x4855, 0x9666, 0x484f, 0x9663, 0x484a, 0x965f, 0x4845, 0x965b,
+ 0x4840, 0x9658, 0x483b, 0x9654, 0x4836, 0x9651, 0x4830, 0x964d,
+ 0x482b, 0x964a, 0x4826, 0x9646, 0x4821, 0x9643, 0x481c, 0x963f,
+ 0x4816, 0x963c, 0x4811, 0x9638, 0x480c, 0x9635, 0x4807, 0x9631,
+ 0x4802, 0x962d, 0x47fc, 0x962a, 0x47f7, 0x9626, 0x47f2, 0x9623,
+ 0x47ed, 0x961f, 0x47e8, 0x961c, 0x47e2, 0x9618, 0x47dd, 0x9615,
+ 0x47d8, 0x9611, 0x47d3, 0x960e, 0x47ce, 0x960a, 0x47c8, 0x9607,
+ 0x47c3, 0x9603, 0x47be, 0x9600, 0x47b9, 0x95fc, 0x47b4, 0x95f9,
+ 0x47ae, 0x95f5, 0x47a9, 0x95f2, 0x47a4, 0x95ee, 0x479f, 0x95ea,
+ 0x479a, 0x95e7, 0x4794, 0x95e3, 0x478f, 0x95e0, 0x478a, 0x95dc,
+ 0x4785, 0x95d9, 0x4780, 0x95d5, 0x477a, 0x95d2, 0x4775, 0x95ce,
+ 0x4770, 0x95cb, 0x476b, 0x95c7, 0x4765, 0x95c4, 0x4760, 0x95c0,
+ 0x475b, 0x95bd, 0x4756, 0x95b9, 0x4751, 0x95b6, 0x474b, 0x95b2,
+ 0x4746, 0x95af, 0x4741, 0x95ab, 0x473c, 0x95a8, 0x4737, 0x95a4,
+ 0x4731, 0x95a1, 0x472c, 0x959d, 0x4727, 0x959a, 0x4722, 0x9596,
+ 0x471c, 0x9593, 0x4717, 0x958f, 0x4712, 0x958c, 0x470d, 0x9588,
+ 0x4708, 0x9585, 0x4702, 0x9581, 0x46fd, 0x957e, 0x46f8, 0x957a,
+ 0x46f3, 0x9577, 0x46ed, 0x9574, 0x46e8, 0x9570, 0x46e3, 0x956d,
+ 0x46de, 0x9569, 0x46d8, 0x9566, 0x46d3, 0x9562, 0x46ce, 0x955f,
+ 0x46c9, 0x955b, 0x46c4, 0x9558, 0x46be, 0x9554, 0x46b9, 0x9551,
+ 0x46b4, 0x954d, 0x46af, 0x954a, 0x46a9, 0x9546, 0x46a4, 0x9543,
+ 0x469f, 0x953f, 0x469a, 0x953c, 0x4694, 0x9538, 0x468f, 0x9535,
+ 0x468a, 0x9532, 0x4685, 0x952e, 0x467f, 0x952b, 0x467a, 0x9527,
+ 0x4675, 0x9524, 0x4670, 0x9520, 0x466a, 0x951d, 0x4665, 0x9519,
+ 0x4660, 0x9516, 0x465b, 0x9512, 0x4655, 0x950f, 0x4650, 0x950c,
+ 0x464b, 0x9508, 0x4646, 0x9505, 0x4640, 0x9501, 0x463b, 0x94fe,
+ 0x4636, 0x94fa, 0x4631, 0x94f7, 0x462b, 0x94f3, 0x4626, 0x94f0,
+ 0x4621, 0x94ed, 0x461c, 0x94e9, 0x4616, 0x94e6, 0x4611, 0x94e2,
+ 0x460c, 0x94df, 0x4607, 0x94db, 0x4601, 0x94d8, 0x45fc, 0x94d4,
+ 0x45f7, 0x94d1, 0x45f2, 0x94ce, 0x45ec, 0x94ca, 0x45e7, 0x94c7,
+ 0x45e2, 0x94c3, 0x45dd, 0x94c0, 0x45d7, 0x94bc, 0x45d2, 0x94b9,
+ 0x45cd, 0x94b6, 0x45c7, 0x94b2, 0x45c2, 0x94af, 0x45bd, 0x94ab,
+ 0x45b8, 0x94a8, 0x45b2, 0x94a4, 0x45ad, 0x94a1, 0x45a8, 0x949e,
+ 0x45a3, 0x949a, 0x459d, 0x9497, 0x4598, 0x9493, 0x4593, 0x9490,
+ 0x458d, 0x948d, 0x4588, 0x9489, 0x4583, 0x9486, 0x457e, 0x9482,
+ 0x4578, 0x947f, 0x4573, 0x947b, 0x456e, 0x9478, 0x4569, 0x9475,
+ 0x4563, 0x9471, 0x455e, 0x946e, 0x4559, 0x946a, 0x4553, 0x9467,
+ 0x454e, 0x9464, 0x4549, 0x9460, 0x4544, 0x945d, 0x453e, 0x9459,
+ 0x4539, 0x9456, 0x4534, 0x9453, 0x452e, 0x944f, 0x4529, 0x944c,
+ 0x4524, 0x9448, 0x451f, 0x9445, 0x4519, 0x9442, 0x4514, 0x943e,
+ 0x450f, 0x943b, 0x4509, 0x9437, 0x4504, 0x9434, 0x44ff, 0x9431,
+ 0x44fa, 0x942d, 0x44f4, 0x942a, 0x44ef, 0x9427, 0x44ea, 0x9423,
+ 0x44e4, 0x9420, 0x44df, 0x941c, 0x44da, 0x9419, 0x44d4, 0x9416,
+ 0x44cf, 0x9412, 0x44ca, 0x940f, 0x44c5, 0x940b, 0x44bf, 0x9408,
+ 0x44ba, 0x9405, 0x44b5, 0x9401, 0x44af, 0x93fe, 0x44aa, 0x93fb,
+ 0x44a5, 0x93f7, 0x449f, 0x93f4, 0x449a, 0x93f1, 0x4495, 0x93ed,
+ 0x4490, 0x93ea, 0x448a, 0x93e6, 0x4485, 0x93e3, 0x4480, 0x93e0,
+ 0x447a, 0x93dc, 0x4475, 0x93d9, 0x4470, 0x93d6, 0x446a, 0x93d2,
+ 0x4465, 0x93cf, 0x4460, 0x93cc, 0x445a, 0x93c8, 0x4455, 0x93c5,
+ 0x4450, 0x93c1, 0x444b, 0x93be, 0x4445, 0x93bb, 0x4440, 0x93b7,
+ 0x443b, 0x93b4, 0x4435, 0x93b1, 0x4430, 0x93ad, 0x442b, 0x93aa,
+ 0x4425, 0x93a7, 0x4420, 0x93a3, 0x441b, 0x93a0, 0x4415, 0x939d,
+ 0x4410, 0x9399, 0x440b, 0x9396, 0x4405, 0x9393, 0x4400, 0x938f,
+ 0x43fb, 0x938c, 0x43f5, 0x9389, 0x43f0, 0x9385, 0x43eb, 0x9382,
+ 0x43e5, 0x937f, 0x43e0, 0x937b, 0x43db, 0x9378, 0x43d5, 0x9375,
+ 0x43d0, 0x9371, 0x43cb, 0x936e, 0x43c5, 0x936b, 0x43c0, 0x9367,
+ 0x43bb, 0x9364, 0x43b5, 0x9361, 0x43b0, 0x935d, 0x43ab, 0x935a,
+ 0x43a5, 0x9357, 0x43a0, 0x9353, 0x439b, 0x9350, 0x4395, 0x934d,
+ 0x4390, 0x9349, 0x438b, 0x9346, 0x4385, 0x9343, 0x4380, 0x933f,
+ 0x437b, 0x933c, 0x4375, 0x9339, 0x4370, 0x9336, 0x436b, 0x9332,
+ 0x4365, 0x932f, 0x4360, 0x932c, 0x435b, 0x9328, 0x4355, 0x9325,
+ 0x4350, 0x9322, 0x434b, 0x931e, 0x4345, 0x931b, 0x4340, 0x9318,
+ 0x433b, 0x9314, 0x4335, 0x9311, 0x4330, 0x930e, 0x432b, 0x930b,
+ 0x4325, 0x9307, 0x4320, 0x9304, 0x431b, 0x9301, 0x4315, 0x92fd,
+ 0x4310, 0x92fa, 0x430b, 0x92f7, 0x4305, 0x92f4, 0x4300, 0x92f0,
+ 0x42fa, 0x92ed, 0x42f5, 0x92ea, 0x42f0, 0x92e6, 0x42ea, 0x92e3,
+ 0x42e5, 0x92e0, 0x42e0, 0x92dd, 0x42da, 0x92d9, 0x42d5, 0x92d6,
+ 0x42d0, 0x92d3, 0x42ca, 0x92cf, 0x42c5, 0x92cc, 0x42c0, 0x92c9,
+ 0x42ba, 0x92c6, 0x42b5, 0x92c2, 0x42af, 0x92bf, 0x42aa, 0x92bc,
+ 0x42a5, 0x92b8, 0x429f, 0x92b5, 0x429a, 0x92b2, 0x4295, 0x92af,
+ 0x428f, 0x92ab, 0x428a, 0x92a8, 0x4284, 0x92a5, 0x427f, 0x92a2,
+ 0x427a, 0x929e, 0x4274, 0x929b, 0x426f, 0x9298, 0x426a, 0x9295,
+ 0x4264, 0x9291, 0x425f, 0x928e, 0x425a, 0x928b, 0x4254, 0x9288,
+ 0x424f, 0x9284, 0x4249, 0x9281, 0x4244, 0x927e, 0x423f, 0x927b,
+ 0x4239, 0x9277, 0x4234, 0x9274, 0x422f, 0x9271, 0x4229, 0x926e,
+ 0x4224, 0x926a, 0x421e, 0x9267, 0x4219, 0x9264, 0x4214, 0x9261,
+ 0x420e, 0x925d, 0x4209, 0x925a, 0x4203, 0x9257, 0x41fe, 0x9254,
+ 0x41f9, 0x9250, 0x41f3, 0x924d, 0x41ee, 0x924a, 0x41e9, 0x9247,
+ 0x41e3, 0x9243, 0x41de, 0x9240, 0x41d8, 0x923d, 0x41d3, 0x923a,
+ 0x41ce, 0x9236, 0x41c8, 0x9233, 0x41c3, 0x9230, 0x41bd, 0x922d,
+ 0x41b8, 0x922a, 0x41b3, 0x9226, 0x41ad, 0x9223, 0x41a8, 0x9220,
+ 0x41a2, 0x921d, 0x419d, 0x9219, 0x4198, 0x9216, 0x4192, 0x9213,
+ 0x418d, 0x9210, 0x4188, 0x920d, 0x4182, 0x9209, 0x417d, 0x9206,
+ 0x4177, 0x9203, 0x4172, 0x9200, 0x416d, 0x91fc, 0x4167, 0x91f9,
+ 0x4162, 0x91f6, 0x415c, 0x91f3, 0x4157, 0x91f0, 0x4152, 0x91ec,
+ 0x414c, 0x91e9, 0x4147, 0x91e6, 0x4141, 0x91e3, 0x413c, 0x91e0,
+ 0x4136, 0x91dc, 0x4131, 0x91d9, 0x412c, 0x91d6, 0x4126, 0x91d3,
+ 0x4121, 0x91d0, 0x411b, 0x91cc, 0x4116, 0x91c9, 0x4111, 0x91c6,
+ 0x410b, 0x91c3, 0x4106, 0x91c0, 0x4100, 0x91bc, 0x40fb, 0x91b9,
+ 0x40f6, 0x91b6, 0x40f0, 0x91b3, 0x40eb, 0x91b0, 0x40e5, 0x91ad,
+ 0x40e0, 0x91a9, 0x40da, 0x91a6, 0x40d5, 0x91a3, 0x40d0, 0x91a0,
+ 0x40ca, 0x919d, 0x40c5, 0x9199, 0x40bf, 0x9196, 0x40ba, 0x9193,
+ 0x40b5, 0x9190, 0x40af, 0x918d, 0x40aa, 0x918a, 0x40a4, 0x9186,
+ 0x409f, 0x9183, 0x4099, 0x9180, 0x4094, 0x917d, 0x408f, 0x917a,
+ 0x4089, 0x9177, 0x4084, 0x9173, 0x407e, 0x9170, 0x4079, 0x916d,
+ 0x4073, 0x916a, 0x406e, 0x9167, 0x4069, 0x9164, 0x4063, 0x9160,
+ 0x405e, 0x915d, 0x4058, 0x915a, 0x4053, 0x9157, 0x404d, 0x9154,
+ 0x4048, 0x9151, 0x4043, 0x914d, 0x403d, 0x914a, 0x4038, 0x9147,
+ 0x4032, 0x9144, 0x402d, 0x9141, 0x4027, 0x913e, 0x4022, 0x913a,
+ 0x401d, 0x9137, 0x4017, 0x9134, 0x4012, 0x9131, 0x400c, 0x912e,
+ 0x4007, 0x912b, 0x4001, 0x9128, 0x3ffc, 0x9124, 0x3ff6, 0x9121,
+ 0x3ff1, 0x911e, 0x3fec, 0x911b, 0x3fe6, 0x9118, 0x3fe1, 0x9115,
+ 0x3fdb, 0x9112, 0x3fd6, 0x910f, 0x3fd0, 0x910b, 0x3fcb, 0x9108,
+ 0x3fc5, 0x9105, 0x3fc0, 0x9102, 0x3fbb, 0x90ff, 0x3fb5, 0x90fc,
+ 0x3fb0, 0x90f9, 0x3faa, 0x90f5, 0x3fa5, 0x90f2, 0x3f9f, 0x90ef,
+ 0x3f9a, 0x90ec, 0x3f94, 0x90e9, 0x3f8f, 0x90e6, 0x3f89, 0x90e3,
+ 0x3f84, 0x90e0, 0x3f7f, 0x90dd, 0x3f79, 0x90d9, 0x3f74, 0x90d6,
+ 0x3f6e, 0x90d3, 0x3f69, 0x90d0, 0x3f63, 0x90cd, 0x3f5e, 0x90ca,
+ 0x3f58, 0x90c7, 0x3f53, 0x90c4, 0x3f4d, 0x90c1, 0x3f48, 0x90bd,
+ 0x3f43, 0x90ba, 0x3f3d, 0x90b7, 0x3f38, 0x90b4, 0x3f32, 0x90b1,
+ 0x3f2d, 0x90ae, 0x3f27, 0x90ab, 0x3f22, 0x90a8, 0x3f1c, 0x90a5,
+ 0x3f17, 0x90a1, 0x3f11, 0x909e, 0x3f0c, 0x909b, 0x3f06, 0x9098,
+ 0x3f01, 0x9095, 0x3efb, 0x9092, 0x3ef6, 0x908f, 0x3ef1, 0x908c,
+ 0x3eeb, 0x9089, 0x3ee6, 0x9086, 0x3ee0, 0x9083, 0x3edb, 0x907f,
+ 0x3ed5, 0x907c, 0x3ed0, 0x9079, 0x3eca, 0x9076, 0x3ec5, 0x9073,
+ 0x3ebf, 0x9070, 0x3eba, 0x906d, 0x3eb4, 0x906a, 0x3eaf, 0x9067,
+ 0x3ea9, 0x9064, 0x3ea4, 0x9061, 0x3e9e, 0x905e, 0x3e99, 0x905b,
+ 0x3e93, 0x9057, 0x3e8e, 0x9054, 0x3e88, 0x9051, 0x3e83, 0x904e,
+ 0x3e7d, 0x904b, 0x3e78, 0x9048, 0x3e73, 0x9045, 0x3e6d, 0x9042,
+ 0x3e68, 0x903f, 0x3e62, 0x903c, 0x3e5d, 0x9039, 0x3e57, 0x9036,
+ 0x3e52, 0x9033, 0x3e4c, 0x9030, 0x3e47, 0x902d, 0x3e41, 0x902a,
+ 0x3e3c, 0x9026, 0x3e36, 0x9023, 0x3e31, 0x9020, 0x3e2b, 0x901d,
+ 0x3e26, 0x901a, 0x3e20, 0x9017, 0x3e1b, 0x9014, 0x3e15, 0x9011,
+ 0x3e10, 0x900e, 0x3e0a, 0x900b, 0x3e05, 0x9008, 0x3dff, 0x9005,
+ 0x3dfa, 0x9002, 0x3df4, 0x8fff, 0x3def, 0x8ffc, 0x3de9, 0x8ff9,
+ 0x3de4, 0x8ff6, 0x3dde, 0x8ff3, 0x3dd9, 0x8ff0, 0x3dd3, 0x8fed,
+ 0x3dce, 0x8fea, 0x3dc8, 0x8fe7, 0x3dc3, 0x8fe3, 0x3dbd, 0x8fe0,
+ 0x3db8, 0x8fdd, 0x3db2, 0x8fda, 0x3dad, 0x8fd7, 0x3da7, 0x8fd4,
+ 0x3da2, 0x8fd1, 0x3d9c, 0x8fce, 0x3d97, 0x8fcb, 0x3d91, 0x8fc8,
+ 0x3d8c, 0x8fc5, 0x3d86, 0x8fc2, 0x3d81, 0x8fbf, 0x3d7b, 0x8fbc,
+ 0x3d76, 0x8fb9, 0x3d70, 0x8fb6, 0x3d6b, 0x8fb3, 0x3d65, 0x8fb0,
+ 0x3d60, 0x8fad, 0x3d5a, 0x8faa, 0x3d55, 0x8fa7, 0x3d4f, 0x8fa4,
+ 0x3d49, 0x8fa1, 0x3d44, 0x8f9e, 0x3d3e, 0x8f9b, 0x3d39, 0x8f98,
+ 0x3d33, 0x8f95, 0x3d2e, 0x8f92, 0x3d28, 0x8f8f, 0x3d23, 0x8f8c,
+ 0x3d1d, 0x8f89, 0x3d18, 0x8f86, 0x3d12, 0x8f83, 0x3d0d, 0x8f80,
+ 0x3d07, 0x8f7d, 0x3d02, 0x8f7a, 0x3cfc, 0x8f77, 0x3cf7, 0x8f74,
+ 0x3cf1, 0x8f71, 0x3cec, 0x8f6e, 0x3ce6, 0x8f6b, 0x3ce1, 0x8f68,
+ 0x3cdb, 0x8f65, 0x3cd6, 0x8f62, 0x3cd0, 0x8f5f, 0x3cca, 0x8f5c,
+ 0x3cc5, 0x8f59, 0x3cbf, 0x8f56, 0x3cba, 0x8f53, 0x3cb4, 0x8f50,
+ 0x3caf, 0x8f4d, 0x3ca9, 0x8f4a, 0x3ca4, 0x8f47, 0x3c9e, 0x8f44,
+ 0x3c99, 0x8f41, 0x3c93, 0x8f3e, 0x3c8e, 0x8f3b, 0x3c88, 0x8f38,
+ 0x3c83, 0x8f35, 0x3c7d, 0x8f32, 0x3c77, 0x8f2f, 0x3c72, 0x8f2d,
+ 0x3c6c, 0x8f2a, 0x3c67, 0x8f27, 0x3c61, 0x8f24, 0x3c5c, 0x8f21,
+ 0x3c56, 0x8f1e, 0x3c51, 0x8f1b, 0x3c4b, 0x8f18, 0x3c46, 0x8f15,
+ 0x3c40, 0x8f12, 0x3c3b, 0x8f0f, 0x3c35, 0x8f0c, 0x3c2f, 0x8f09,
+ 0x3c2a, 0x8f06, 0x3c24, 0x8f03, 0x3c1f, 0x8f00, 0x3c19, 0x8efd,
+ 0x3c14, 0x8efa, 0x3c0e, 0x8ef7, 0x3c09, 0x8ef4, 0x3c03, 0x8ef1,
+ 0x3bfd, 0x8eee, 0x3bf8, 0x8eec, 0x3bf2, 0x8ee9, 0x3bed, 0x8ee6,
+ 0x3be7, 0x8ee3, 0x3be2, 0x8ee0, 0x3bdc, 0x8edd, 0x3bd7, 0x8eda,
+ 0x3bd1, 0x8ed7, 0x3bcc, 0x8ed4, 0x3bc6, 0x8ed1, 0x3bc0, 0x8ece,
+ 0x3bbb, 0x8ecb, 0x3bb5, 0x8ec8, 0x3bb0, 0x8ec5, 0x3baa, 0x8ec2,
+ 0x3ba5, 0x8ebf, 0x3b9f, 0x8ebd, 0x3b99, 0x8eba, 0x3b94, 0x8eb7,
+ 0x3b8e, 0x8eb4, 0x3b89, 0x8eb1, 0x3b83, 0x8eae, 0x3b7e, 0x8eab,
+ 0x3b78, 0x8ea8, 0x3b73, 0x8ea5, 0x3b6d, 0x8ea2, 0x3b67, 0x8e9f,
+ 0x3b62, 0x8e9c, 0x3b5c, 0x8e99, 0x3b57, 0x8e97, 0x3b51, 0x8e94,
+ 0x3b4c, 0x8e91, 0x3b46, 0x8e8e, 0x3b40, 0x8e8b, 0x3b3b, 0x8e88,
+ 0x3b35, 0x8e85, 0x3b30, 0x8e82, 0x3b2a, 0x8e7f, 0x3b25, 0x8e7c,
+ 0x3b1f, 0x8e7a, 0x3b19, 0x8e77, 0x3b14, 0x8e74, 0x3b0e, 0x8e71,
+ 0x3b09, 0x8e6e, 0x3b03, 0x8e6b, 0x3afe, 0x8e68, 0x3af8, 0x8e65,
+ 0x3af2, 0x8e62, 0x3aed, 0x8e5f, 0x3ae7, 0x8e5d, 0x3ae2, 0x8e5a,
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+ 0x3aaf, 0x8e40, 0x3aaa, 0x8e3d, 0x3aa4, 0x8e3a, 0x3a9f, 0x8e37,
+ 0x3a99, 0x8e34, 0x3a94, 0x8e31, 0x3a8e, 0x8e2e, 0x3a88, 0x8e2c,
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+ 0x3a13, 0x8def, 0x3a0d, 0x8ded, 0x3a08, 0x8dea, 0x3a02, 0x8de7,
+ 0x39fd, 0x8de4, 0x39f7, 0x8de1, 0x39f1, 0x8dde, 0x39ec, 0x8ddc,
+ 0x39e6, 0x8dd9, 0x39e0, 0x8dd6, 0x39db, 0x8dd3, 0x39d5, 0x8dd0,
+ 0x39d0, 0x8dcd, 0x39ca, 0x8dca, 0x39c4, 0x8dc8, 0x39bf, 0x8dc5,
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+ 0x39a3, 0x8db7, 0x399d, 0x8db4, 0x3998, 0x8db1, 0x3992, 0x8dae,
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+ 0x3976, 0x8da0, 0x3970, 0x8d9d, 0x396b, 0x8d9a, 0x3965, 0x8d98,
+ 0x395f, 0x8d95, 0x395a, 0x8d92, 0x3954, 0x8d8f, 0x394f, 0x8d8c,
+ 0x3949, 0x8d8a, 0x3943, 0x8d87, 0x393e, 0x8d84, 0x3938, 0x8d81,
+ 0x3932, 0x8d7e, 0x392d, 0x8d7b, 0x3927, 0x8d79, 0x3922, 0x8d76,
+ 0x391c, 0x8d73, 0x3916, 0x8d70, 0x3911, 0x8d6d, 0x390b, 0x8d6b,
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+ 0x38ef, 0x8d5d, 0x38e9, 0x8d5a, 0x38e4, 0x8d57, 0x38de, 0x8d54,
+ 0x38d8, 0x8d51, 0x38d3, 0x8d4f, 0x38cd, 0x8d4c, 0x38c8, 0x8d49,
+ 0x38c2, 0x8d46, 0x38bc, 0x8d44, 0x38b7, 0x8d41, 0x38b1, 0x8d3e,
+ 0x38ab, 0x8d3b, 0x38a6, 0x8d38, 0x38a0, 0x8d36, 0x389b, 0x8d33,
+ 0x3895, 0x8d30, 0x388f, 0x8d2d, 0x388a, 0x8d2b, 0x3884, 0x8d28,
+ 0x387e, 0x8d25, 0x3879, 0x8d22, 0x3873, 0x8d1f, 0x386d, 0x8d1d,
+ 0x3868, 0x8d1a, 0x3862, 0x8d17, 0x385d, 0x8d14, 0x3857, 0x8d12,
+ 0x3851, 0x8d0f, 0x384c, 0x8d0c, 0x3846, 0x8d09, 0x3840, 0x8d07,
+ 0x383b, 0x8d04, 0x3835, 0x8d01, 0x382f, 0x8cfe, 0x382a, 0x8cfb,
+ 0x3824, 0x8cf9, 0x381e, 0x8cf6, 0x3819, 0x8cf3, 0x3813, 0x8cf0,
+ 0x380d, 0x8cee, 0x3808, 0x8ceb, 0x3802, 0x8ce8, 0x37fd, 0x8ce5,
+ 0x37f7, 0x8ce3, 0x37f1, 0x8ce0, 0x37ec, 0x8cdd, 0x37e6, 0x8cda,
+ 0x37e0, 0x8cd8, 0x37db, 0x8cd5, 0x37d5, 0x8cd2, 0x37cf, 0x8cd0,
+ 0x37ca, 0x8ccd, 0x37c4, 0x8cca, 0x37be, 0x8cc7, 0x37b9, 0x8cc5,
+ 0x37b3, 0x8cc2, 0x37ad, 0x8cbf, 0x37a8, 0x8cbc, 0x37a2, 0x8cba,
+ 0x379c, 0x8cb7, 0x3797, 0x8cb4, 0x3791, 0x8cb1, 0x378b, 0x8caf,
+ 0x3786, 0x8cac, 0x3780, 0x8ca9, 0x377a, 0x8ca7, 0x3775, 0x8ca4,
+ 0x376f, 0x8ca1, 0x3769, 0x8c9e, 0x3764, 0x8c9c, 0x375e, 0x8c99,
+ 0x3758, 0x8c96, 0x3753, 0x8c94, 0x374d, 0x8c91, 0x3747, 0x8c8e,
+ 0x3742, 0x8c8b, 0x373c, 0x8c89, 0x3736, 0x8c86, 0x3731, 0x8c83,
+ 0x372b, 0x8c81, 0x3725, 0x8c7e, 0x3720, 0x8c7b, 0x371a, 0x8c78,
+ 0x3714, 0x8c76, 0x370f, 0x8c73, 0x3709, 0x8c70, 0x3703, 0x8c6e,
+ 0x36fe, 0x8c6b, 0x36f8, 0x8c68, 0x36f2, 0x8c65, 0x36ed, 0x8c63,
+ 0x36e7, 0x8c60, 0x36e1, 0x8c5d, 0x36dc, 0x8c5b, 0x36d6, 0x8c58,
+ 0x36d0, 0x8c55, 0x36cb, 0x8c53, 0x36c5, 0x8c50, 0x36bf, 0x8c4d,
+ 0x36ba, 0x8c4b, 0x36b4, 0x8c48, 0x36ae, 0x8c45, 0x36a9, 0x8c43,
+ 0x36a3, 0x8c40, 0x369d, 0x8c3d, 0x3698, 0x8c3a, 0x3692, 0x8c38,
+ 0x368c, 0x8c35, 0x3686, 0x8c32, 0x3681, 0x8c30, 0x367b, 0x8c2d,
+ 0x3675, 0x8c2a, 0x3670, 0x8c28, 0x366a, 0x8c25, 0x3664, 0x8c22,
+ 0x365f, 0x8c20, 0x3659, 0x8c1d, 0x3653, 0x8c1a, 0x364e, 0x8c18,
+ 0x3648, 0x8c15, 0x3642, 0x8c12, 0x363d, 0x8c10, 0x3637, 0x8c0d,
+ 0x3631, 0x8c0a, 0x362b, 0x8c08, 0x3626, 0x8c05, 0x3620, 0x8c02,
+ 0x361a, 0x8c00, 0x3615, 0x8bfd, 0x360f, 0x8bfa, 0x3609, 0x8bf8,
+ 0x3604, 0x8bf5, 0x35fe, 0x8bf3, 0x35f8, 0x8bf0, 0x35f3, 0x8bed,
+ 0x35ed, 0x8beb, 0x35e7, 0x8be8, 0x35e1, 0x8be5, 0x35dc, 0x8be3,
+ 0x35d6, 0x8be0, 0x35d0, 0x8bdd, 0x35cb, 0x8bdb, 0x35c5, 0x8bd8,
+ 0x35bf, 0x8bd5, 0x35ba, 0x8bd3, 0x35b4, 0x8bd0, 0x35ae, 0x8bce,
+ 0x35a8, 0x8bcb, 0x35a3, 0x8bc8, 0x359d, 0x8bc6, 0x3597, 0x8bc3,
+ 0x3592, 0x8bc0, 0x358c, 0x8bbe, 0x3586, 0x8bbb, 0x3580, 0x8bb8,
+ 0x357b, 0x8bb6, 0x3575, 0x8bb3, 0x356f, 0x8bb1, 0x356a, 0x8bae,
+ 0x3564, 0x8bab, 0x355e, 0x8ba9, 0x3558, 0x8ba6, 0x3553, 0x8ba4,
+ 0x354d, 0x8ba1, 0x3547, 0x8b9e, 0x3542, 0x8b9c, 0x353c, 0x8b99,
+ 0x3536, 0x8b96, 0x3530, 0x8b94, 0x352b, 0x8b91, 0x3525, 0x8b8f,
+ 0x351f, 0x8b8c, 0x351a, 0x8b89, 0x3514, 0x8b87, 0x350e, 0x8b84,
+ 0x3508, 0x8b82, 0x3503, 0x8b7f, 0x34fd, 0x8b7c, 0x34f7, 0x8b7a,
+ 0x34f2, 0x8b77, 0x34ec, 0x8b75, 0x34e6, 0x8b72, 0x34e0, 0x8b6f,
+ 0x34db, 0x8b6d, 0x34d5, 0x8b6a, 0x34cf, 0x8b68, 0x34ca, 0x8b65,
+ 0x34c4, 0x8b62, 0x34be, 0x8b60, 0x34b8, 0x8b5d, 0x34b3, 0x8b5b,
+ 0x34ad, 0x8b58, 0x34a7, 0x8b55, 0x34a1, 0x8b53, 0x349c, 0x8b50,
+ 0x3496, 0x8b4e, 0x3490, 0x8b4b, 0x348b, 0x8b49, 0x3485, 0x8b46,
+ 0x347f, 0x8b43, 0x3479, 0x8b41, 0x3474, 0x8b3e, 0x346e, 0x8b3c,
+ 0x3468, 0x8b39, 0x3462, 0x8b37, 0x345d, 0x8b34, 0x3457, 0x8b31,
+ 0x3451, 0x8b2f, 0x344b, 0x8b2c, 0x3446, 0x8b2a, 0x3440, 0x8b27,
+ 0x343a, 0x8b25, 0x3435, 0x8b22, 0x342f, 0x8b1f, 0x3429, 0x8b1d,
+ 0x3423, 0x8b1a, 0x341e, 0x8b18, 0x3418, 0x8b15, 0x3412, 0x8b13,
+ 0x340c, 0x8b10, 0x3407, 0x8b0e, 0x3401, 0x8b0b, 0x33fb, 0x8b08,
+ 0x33f5, 0x8b06, 0x33f0, 0x8b03, 0x33ea, 0x8b01, 0x33e4, 0x8afe,
+ 0x33de, 0x8afc, 0x33d9, 0x8af9, 0x33d3, 0x8af7, 0x33cd, 0x8af4,
+ 0x33c7, 0x8af1, 0x33c2, 0x8aef, 0x33bc, 0x8aec, 0x33b6, 0x8aea,
+ 0x33b0, 0x8ae7, 0x33ab, 0x8ae5, 0x33a5, 0x8ae2, 0x339f, 0x8ae0,
+ 0x3399, 0x8add, 0x3394, 0x8adb, 0x338e, 0x8ad8, 0x3388, 0x8ad6,
+ 0x3382, 0x8ad3, 0x337d, 0x8ad1, 0x3377, 0x8ace, 0x3371, 0x8acb,
+ 0x336b, 0x8ac9, 0x3366, 0x8ac6, 0x3360, 0x8ac4, 0x335a, 0x8ac1,
+ 0x3354, 0x8abf, 0x334f, 0x8abc, 0x3349, 0x8aba, 0x3343, 0x8ab7,
+ 0x333d, 0x8ab5, 0x3338, 0x8ab2, 0x3332, 0x8ab0, 0x332c, 0x8aad,
+ 0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,
+ 0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,
+ 0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,
+ 0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,
+ 0x32ca, 0x8a83, 0x32c4, 0x8a80, 0x32bf, 0x8a7e, 0x32b9, 0x8a7b,
+ 0x32b3, 0x8a79, 0x32ad, 0x8a76, 0x32a8, 0x8a74, 0x32a2, 0x8a71,
+ 0x329c, 0x8a6f, 0x3296, 0x8a6c, 0x3290, 0x8a6a, 0x328b, 0x8a67,
+ 0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,
+ 0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,
+ 0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,
+ 0x3240, 0x8a47, 0x323a, 0x8a45, 0x3234, 0x8a42, 0x322e, 0x8a40,
+ 0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,
+ 0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,
+ 0x31fa, 0x8a2a, 0x31f4, 0x8a27, 0x31ef, 0x8a25, 0x31e9, 0x8a22,
+ 0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,
+ 0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,
+ 0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,
+ 0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,
+ 0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,
+ 0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,
+ 0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,
+ 0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,
+ 0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,
+ 0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,
+ 0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,
+ 0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,
+ 0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,
+ 0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,
+ 0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,
+ 0x3087, 0x898f, 0x3081, 0x898d, 0x307b, 0x898a, 0x3076, 0x8988,
+ 0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,
+ 0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,
+ 0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,
+ 0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,
+ 0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,
+ 0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,
+ 0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,
+ 0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,
+ 0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,
+ 0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,
+ 0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,
+ 0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,
+ 0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,
+ 0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,
+ 0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,
+ 0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,
+ 0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,
+ 0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,
+ 0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,
+ 0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,
+ 0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,
+ 0x2e86, 0x88c2, 0x2e80, 0x88bf, 0x2e7a, 0x88bd, 0x2e74, 0x88bb,
+ 0x2e6e, 0x88b9, 0x2e68, 0x88b6, 0x2e63, 0x88b4, 0x2e5d, 0x88b2,
+ 0x2e57, 0x88af, 0x2e51, 0x88ad, 0x2e4b, 0x88ab, 0x2e45, 0x88a9,
+ 0x2e3f, 0x88a6, 0x2e3a, 0x88a4, 0x2e34, 0x88a2, 0x2e2e, 0x88a0,
+ 0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,
+ 0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,
+ 0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,
+ 0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,
+ 0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,
+ 0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,
+ 0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,
+ 0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,
+ 0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,
+ 0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,
+ 0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,
+ 0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,
+ 0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,
+ 0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,
+ 0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,
+ 0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,
+ 0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,
+ 0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,
+ 0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,
+ 0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,
+ 0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,
+ 0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,
+ 0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,
+ 0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,
+ 0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,
+ 0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,
+ 0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,
+ 0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,
+ 0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,
+ 0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,
+ 0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,
+ 0x2b4e, 0x878d, 0x2b48, 0x878b, 0x2b42, 0x8789, 0x2b3c, 0x8787,
+ 0x2b36, 0x8784, 0x2b30, 0x8782, 0x2b2b, 0x8780, 0x2b25, 0x877e,
+ 0x2b1f, 0x877c, 0x2b19, 0x877a, 0x2b13, 0x8778, 0x2b0d, 0x8776,
+ 0x2b07, 0x8774, 0x2b01, 0x8771, 0x2afb, 0x876f, 0x2af5, 0x876d,
+ 0x2aef, 0x876b, 0x2ae9, 0x8769, 0x2ae4, 0x8767, 0x2ade, 0x8765,
+ 0x2ad8, 0x8763, 0x2ad2, 0x8761, 0x2acc, 0x875e, 0x2ac6, 0x875c,
+ 0x2ac0, 0x875a, 0x2aba, 0x8758, 0x2ab4, 0x8756, 0x2aae, 0x8754,
+ 0x2aa8, 0x8752, 0x2aa2, 0x8750, 0x2a9c, 0x874e, 0x2a97, 0x874c,
+ 0x2a91, 0x874a, 0x2a8b, 0x8747, 0x2a85, 0x8745, 0x2a7f, 0x8743,
+ 0x2a79, 0x8741, 0x2a73, 0x873f, 0x2a6d, 0x873d, 0x2a67, 0x873b,
+ 0x2a61, 0x8739, 0x2a5b, 0x8737, 0x2a55, 0x8735, 0x2a4f, 0x8733,
+ 0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,
+ 0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,
+ 0x2a1a, 0x8720, 0x2a14, 0x871e, 0x2a0e, 0x871c, 0x2a08, 0x871a,
+ 0x2a02, 0x8718, 0x29fc, 0x8716, 0x29f6, 0x8714, 0x29f0, 0x8712,
+ 0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,
+ 0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,
+ 0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,
+ 0x29a3, 0x86f7, 0x299d, 0x86f5, 0x2997, 0x86f3, 0x2991, 0x86f1,
+ 0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,
+ 0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,
+ 0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,
+ 0x2944, 0x86d6, 0x293e, 0x86d4, 0x2938, 0x86d2, 0x2932, 0x86d0,
+ 0x292c, 0x86ce, 0x2926, 0x86cc, 0x2920, 0x86ca, 0x291b, 0x86c8,
+ 0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,
+ 0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,
+ 0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,
+ 0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,
+ 0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,
+ 0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,
+ 0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,
+ 0x286e, 0x868e, 0x2868, 0x868c, 0x2862, 0x868a, 0x285c, 0x8688,
+ 0x2856, 0x8686, 0x2850, 0x8684, 0x284a, 0x8682, 0x2844, 0x8680,
+ 0x283e, 0x867e, 0x2838, 0x867c, 0x2832, 0x867a, 0x282c, 0x8678,
+ 0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,
+ 0x280e, 0x866e, 0x2808, 0x866d, 0x2802, 0x866b, 0x27fc, 0x8669,
+ 0x27f6, 0x8667, 0x27f1, 0x8665, 0x27eb, 0x8663, 0x27e5, 0x8661,
+ 0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,
+ 0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,
+ 0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,
+ 0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,
+ 0x277f, 0x8640, 0x2779, 0x863e, 0x2773, 0x863c, 0x276d, 0x863a,
+ 0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,
+ 0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,
+ 0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,
+ 0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,
+ 0x2707, 0x8619, 0x2701, 0x8617, 0x26fb, 0x8615, 0x26f5, 0x8613,
+ 0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,
+ 0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,
+ 0x26c0, 0x8602, 0x26ba, 0x8600, 0x26b4, 0x85fe, 0x26ae, 0x85fc,
+ 0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,
+ 0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,
+ 0x2678, 0x85eb, 0x2672, 0x85ea, 0x266c, 0x85e8, 0x2666, 0x85e6,
+ 0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,
+ 0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,
+ 0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,
+ 0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,
+ 0x2600, 0x85c6, 0x25fa, 0x85c4, 0x25f4, 0x85c2, 0x25ee, 0x85c0,
+ 0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,
+ 0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,
+ 0x25b8, 0x85b0, 0x25b2, 0x85ae, 0x25ac, 0x85ac, 0x25a6, 0x85aa,
+ 0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,
+ 0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,
+ 0x2570, 0x8599, 0x256a, 0x8598, 0x2564, 0x8596, 0x255e, 0x8594,
+ 0x2558, 0x8592, 0x2552, 0x8590, 0x254c, 0x858e, 0x2546, 0x858d,
+ 0x2540, 0x858b, 0x253a, 0x8589, 0x2534, 0x8587, 0x252e, 0x8585,
+ 0x2528, 0x8583, 0x2522, 0x8582, 0x251c, 0x8580, 0x2516, 0x857e,
+ 0x250f, 0x857c, 0x2509, 0x857a, 0x2503, 0x8579, 0x24fd, 0x8577,
+ 0x24f7, 0x8575, 0x24f1, 0x8573, 0x24eb, 0x8571, 0x24e5, 0x856f,
+ 0x24df, 0x856e, 0x24d9, 0x856c, 0x24d3, 0x856a, 0x24cd, 0x8568,
+ 0x24c7, 0x8566, 0x24c1, 0x8565, 0x24bb, 0x8563, 0x24b5, 0x8561,
+ 0x24af, 0x855f, 0x24a9, 0x855d, 0x24a3, 0x855c, 0x249d, 0x855a,
+ 0x2497, 0x8558, 0x2491, 0x8556, 0x248b, 0x8554, 0x2485, 0x8553,
+ 0x247f, 0x8551, 0x2479, 0x854f, 0x2473, 0x854d, 0x246d, 0x854b,
+ 0x2467, 0x854a, 0x2461, 0x8548, 0x245b, 0x8546, 0x2455, 0x8544,
+ 0x244f, 0x8543, 0x2449, 0x8541, 0x2443, 0x853f, 0x243d, 0x853d,
+ 0x2437, 0x853b, 0x2431, 0x853a, 0x242b, 0x8538, 0x2425, 0x8536,
+ 0x241f, 0x8534, 0x2419, 0x8533, 0x2413, 0x8531, 0x240d, 0x852f,
+ 0x2407, 0x852d, 0x2401, 0x852b, 0x23fa, 0x852a, 0x23f4, 0x8528,
+ 0x23ee, 0x8526, 0x23e8, 0x8524, 0x23e2, 0x8523, 0x23dc, 0x8521,
+ 0x23d6, 0x851f, 0x23d0, 0x851d, 0x23ca, 0x851c, 0x23c4, 0x851a,
+ 0x23be, 0x8518, 0x23b8, 0x8516, 0x23b2, 0x8515, 0x23ac, 0x8513,
+ 0x23a6, 0x8511, 0x23a0, 0x850f, 0x239a, 0x850e, 0x2394, 0x850c,
+ 0x238e, 0x850a, 0x2388, 0x8508, 0x2382, 0x8507, 0x237c, 0x8505,
+ 0x2376, 0x8503, 0x2370, 0x8501, 0x236a, 0x8500, 0x2364, 0x84fe,
+ 0x235e, 0x84fc, 0x2358, 0x84fa, 0x2352, 0x84f9, 0x234b, 0x84f7,
+ 0x2345, 0x84f5, 0x233f, 0x84f4, 0x2339, 0x84f2, 0x2333, 0x84f0,
+ 0x232d, 0x84ee, 0x2327, 0x84ed, 0x2321, 0x84eb, 0x231b, 0x84e9,
+ 0x2315, 0x84e7, 0x230f, 0x84e6, 0x2309, 0x84e4, 0x2303, 0x84e2,
+ 0x22fd, 0x84e1, 0x22f7, 0x84df, 0x22f1, 0x84dd, 0x22eb, 0x84db,
+ 0x22e5, 0x84da, 0x22df, 0x84d8, 0x22d9, 0x84d6, 0x22d3, 0x84d5,
+ 0x22cd, 0x84d3, 0x22c7, 0x84d1, 0x22c0, 0x84cf, 0x22ba, 0x84ce,
+ 0x22b4, 0x84cc, 0x22ae, 0x84ca, 0x22a8, 0x84c9, 0x22a2, 0x84c7,
+ 0x229c, 0x84c5, 0x2296, 0x84c4, 0x2290, 0x84c2, 0x228a, 0x84c0,
+ 0x2284, 0x84be, 0x227e, 0x84bd, 0x2278, 0x84bb, 0x2272, 0x84b9,
+ 0x226c, 0x84b8, 0x2266, 0x84b6, 0x2260, 0x84b4, 0x225a, 0x84b3,
+ 0x2254, 0x84b1, 0x224e, 0x84af, 0x2247, 0x84ae, 0x2241, 0x84ac,
+ 0x223b, 0x84aa, 0x2235, 0x84a9, 0x222f, 0x84a7, 0x2229, 0x84a5,
+ 0x2223, 0x84a3, 0x221d, 0x84a2, 0x2217, 0x84a0, 0x2211, 0x849e,
+ 0x220b, 0x849d, 0x2205, 0x849b, 0x21ff, 0x8499, 0x21f9, 0x8498,
+ 0x21f3, 0x8496, 0x21ed, 0x8494, 0x21e7, 0x8493, 0x21e1, 0x8491,
+ 0x21da, 0x848f, 0x21d4, 0x848e, 0x21ce, 0x848c, 0x21c8, 0x848a,
+ 0x21c2, 0x8489, 0x21bc, 0x8487, 0x21b6, 0x8486, 0x21b0, 0x8484,
+ 0x21aa, 0x8482, 0x21a4, 0x8481, 0x219e, 0x847f, 0x2198, 0x847d,
+ 0x2192, 0x847c, 0x218c, 0x847a, 0x2186, 0x8478, 0x2180, 0x8477,
+ 0x2179, 0x8475, 0x2173, 0x8473, 0x216d, 0x8472, 0x2167, 0x8470,
+ 0x2161, 0x846e, 0x215b, 0x846d, 0x2155, 0x846b, 0x214f, 0x846a,
+ 0x2149, 0x8468, 0x2143, 0x8466, 0x213d, 0x8465, 0x2137, 0x8463,
+ 0x2131, 0x8461, 0x212b, 0x8460, 0x2125, 0x845e, 0x211e, 0x845d,
+ 0x2118, 0x845b, 0x2112, 0x8459, 0x210c, 0x8458, 0x2106, 0x8456,
+ 0x2100, 0x8454, 0x20fa, 0x8453, 0x20f4, 0x8451, 0x20ee, 0x8450,
+ 0x20e8, 0x844e, 0x20e2, 0x844c, 0x20dc, 0x844b, 0x20d6, 0x8449,
+ 0x20d0, 0x8447, 0x20c9, 0x8446, 0x20c3, 0x8444, 0x20bd, 0x8443,
+ 0x20b7, 0x8441, 0x20b1, 0x843f, 0x20ab, 0x843e, 0x20a5, 0x843c,
+ 0x209f, 0x843b, 0x2099, 0x8439, 0x2093, 0x8437, 0x208d, 0x8436,
+ 0x2087, 0x8434, 0x2081, 0x8433, 0x207a, 0x8431, 0x2074, 0x842f,
+ 0x206e, 0x842e, 0x2068, 0x842c, 0x2062, 0x842b, 0x205c, 0x8429,
+ 0x2056, 0x8427, 0x2050, 0x8426, 0x204a, 0x8424, 0x2044, 0x8423,
+ 0x203e, 0x8421, 0x2038, 0x8420, 0x2032, 0x841e, 0x202b, 0x841c,
+ 0x2025, 0x841b, 0x201f, 0x8419, 0x2019, 0x8418, 0x2013, 0x8416,
+ 0x200d, 0x8415, 0x2007, 0x8413, 0x2001, 0x8411, 0x1ffb, 0x8410,
+ 0x1ff5, 0x840e, 0x1fef, 0x840d, 0x1fe9, 0x840b, 0x1fe2, 0x840a,
+ 0x1fdc, 0x8408, 0x1fd6, 0x8406, 0x1fd0, 0x8405, 0x1fca, 0x8403,
+ 0x1fc4, 0x8402, 0x1fbe, 0x8400, 0x1fb8, 0x83ff, 0x1fb2, 0x83fd,
+ 0x1fac, 0x83fb, 0x1fa6, 0x83fa, 0x1f9f, 0x83f8, 0x1f99, 0x83f7,
+ 0x1f93, 0x83f5, 0x1f8d, 0x83f4, 0x1f87, 0x83f2, 0x1f81, 0x83f1,
+ 0x1f7b, 0x83ef, 0x1f75, 0x83ee, 0x1f6f, 0x83ec, 0x1f69, 0x83ea,
+ 0x1f63, 0x83e9, 0x1f5d, 0x83e7, 0x1f56, 0x83e6, 0x1f50, 0x83e4,
+ 0x1f4a, 0x83e3, 0x1f44, 0x83e1, 0x1f3e, 0x83e0, 0x1f38, 0x83de,
+ 0x1f32, 0x83dd, 0x1f2c, 0x83db, 0x1f26, 0x83da, 0x1f20, 0x83d8,
+ 0x1f19, 0x83d7, 0x1f13, 0x83d5, 0x1f0d, 0x83d3, 0x1f07, 0x83d2,
+ 0x1f01, 0x83d0, 0x1efb, 0x83cf, 0x1ef5, 0x83cd, 0x1eef, 0x83cc,
+ 0x1ee9, 0x83ca, 0x1ee3, 0x83c9, 0x1edd, 0x83c7, 0x1ed6, 0x83c6,
+ 0x1ed0, 0x83c4, 0x1eca, 0x83c3, 0x1ec4, 0x83c1, 0x1ebe, 0x83c0,
+ 0x1eb8, 0x83be, 0x1eb2, 0x83bd, 0x1eac, 0x83bb, 0x1ea6, 0x83ba,
+ 0x1ea0, 0x83b8, 0x1e99, 0x83b7, 0x1e93, 0x83b5, 0x1e8d, 0x83b4,
+ 0x1e87, 0x83b2, 0x1e81, 0x83b1, 0x1e7b, 0x83af, 0x1e75, 0x83ae,
+ 0x1e6f, 0x83ac, 0x1e69, 0x83ab, 0x1e62, 0x83a9, 0x1e5c, 0x83a8,
+ 0x1e56, 0x83a6, 0x1e50, 0x83a5, 0x1e4a, 0x83a3, 0x1e44, 0x83a2,
+ 0x1e3e, 0x83a0, 0x1e38, 0x839f, 0x1e32, 0x839d, 0x1e2c, 0x839c,
+ 0x1e25, 0x839a, 0x1e1f, 0x8399, 0x1e19, 0x8397, 0x1e13, 0x8396,
+ 0x1e0d, 0x8394, 0x1e07, 0x8393, 0x1e01, 0x8392, 0x1dfb, 0x8390,
+ 0x1df5, 0x838f, 0x1dee, 0x838d, 0x1de8, 0x838c, 0x1de2, 0x838a,
+ 0x1ddc, 0x8389, 0x1dd6, 0x8387, 0x1dd0, 0x8386, 0x1dca, 0x8384,
+ 0x1dc4, 0x8383, 0x1dbe, 0x8381, 0x1db7, 0x8380, 0x1db1, 0x837e,
+ 0x1dab, 0x837d, 0x1da5, 0x837c, 0x1d9f, 0x837a, 0x1d99, 0x8379,
+ 0x1d93, 0x8377, 0x1d8d, 0x8376, 0x1d87, 0x8374, 0x1d80, 0x8373,
+ 0x1d7a, 0x8371, 0x1d74, 0x8370, 0x1d6e, 0x836f, 0x1d68, 0x836d,
+ 0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,
+ 0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,
+ 0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,
+ 0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,
+ 0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,
+ 0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,
+ 0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,
+ 0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,
+ 0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,
+ 0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,
+ 0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,
+ 0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,
+ 0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,
+ 0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,
+ 0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,
+ 0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,
+ 0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,
+ 0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,
+ 0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,
+ 0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,
+ 0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,
+ 0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,
+ 0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,
+ 0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,
+ 0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,
+ 0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,
+ 0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,
+ 0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,
+ 0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,
+ 0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,
+ 0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,
+ 0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,
+ 0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,
+ 0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,
+ 0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,
+ 0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,
+ 0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,
+ 0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,
+ 0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,
+ 0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,
+ 0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,
+ 0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,
+ 0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,
+ 0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,
+ 0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,
+ 0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,
+ 0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,
+ 0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,
+ 0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,
+ 0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,
+ 0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,
+ 0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,
+ 0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,
+ 0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,
+ 0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,
+ 0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,
+ 0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,
+ 0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,
+ 0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,
+ 0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,
+ 0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,
+ 0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,
+ 0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,
+ 0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,
+ 0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,
+ 0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,
+ 0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,
+ 0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,
+ 0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,
+ 0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,
+ 0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,
+ 0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,
+ 0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,
+ 0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,
+ 0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,
+ 0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,
+ 0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,
+ 0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,
+ 0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,
+ 0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,
+ 0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,
+ 0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,
+ 0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,
+ 0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,
+ 0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,
+ 0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,
+ 0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,
+ 0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,
+ 0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,
+ 0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,
+ 0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,
+ 0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,
+ 0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,
+ 0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,
+ 0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,
+ 0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,
+ 0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,
+ 0x140b, 0x8195, 0x1404, 0x8194, 0x13fe, 0x8193, 0x13f8, 0x8192,
+ 0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,
+ 0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,
+ 0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,
+ 0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,
+ 0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,
+ 0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,
+ 0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,
+ 0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,
+ 0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,
+ 0x1312, 0x816e, 0x130c, 0x816d, 0x1306, 0x816c, 0x12ff, 0x816c,
+ 0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,
+ 0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,
+ 0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,
+ 0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,
+ 0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,
+ 0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,
+ 0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,
+ 0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,
+ 0x1232, 0x814d, 0x122c, 0x814c, 0x1226, 0x814c, 0x1220, 0x814b,
+ 0x1219, 0x814a, 0x1213, 0x8149, 0x120d, 0x8148, 0x1207, 0x8147,
+ 0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,
+ 0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,
+ 0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,
+ 0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,
+ 0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,
+ 0x1184, 0x8135, 0x117e, 0x8134, 0x1178, 0x8133, 0x1171, 0x8132,
+ 0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,
+ 0x1152, 0x812e, 0x114c, 0x812d, 0x1146, 0x812c, 0x1140, 0x812b,
+ 0x1139, 0x812b, 0x1133, 0x812a, 0x112d, 0x8129, 0x1127, 0x8128,
+ 0x1121, 0x8127, 0x111a, 0x8126, 0x1114, 0x8126, 0x110e, 0x8125,
+ 0x1108, 0x8124, 0x1101, 0x8123, 0x10fb, 0x8122, 0x10f5, 0x8121,
+ 0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,
+ 0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,
+ 0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,
+ 0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,
+ 0x108b, 0x8113, 0x1085, 0x8113, 0x107f, 0x8112, 0x1078, 0x8111,
+ 0x1072, 0x8110, 0x106c, 0x810f, 0x1066, 0x810f, 0x105f, 0x810e,
+ 0x1059, 0x810d, 0x1053, 0x810c, 0x104d, 0x810b, 0x1047, 0x810b,
+ 0x1040, 0x810a, 0x103a, 0x8109, 0x1034, 0x8108, 0x102e, 0x8107,
+ 0x1027, 0x8107, 0x1021, 0x8106, 0x101b, 0x8105, 0x1015, 0x8104,
+ 0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,
+ 0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,
+ 0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,
+ 0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,
+ 0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,
+ 0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,
+ 0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,
+ 0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,
+ 0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,
+ 0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,
+ 0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,
+ 0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,
+ 0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,
+ 0xeca, 0x80dc, 0xec4, 0x80db, 0xebe, 0x80db, 0xeb7, 0x80da,
+ 0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,
+ 0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,
+ 0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,
+ 0xe66, 0x80d1, 0xe60, 0x80d0, 0xe5a, 0x80cf, 0xe53, 0x80ce,
+ 0xe4d, 0x80ce, 0xe47, 0x80cd, 0xe41, 0x80cc, 0xe3a, 0x80cc,
+ 0xe34, 0x80cb, 0xe2e, 0x80ca, 0xe28, 0x80ca, 0xe22, 0x80c9,
+ 0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,
+ 0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,
+ 0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,
+ 0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,
+ 0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,
+ 0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,
+ 0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,
+ 0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,
+ 0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,
+ 0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
+ 0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
+ 0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
+ 0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
+ 0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
+ 0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
+ 0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
+ 0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
+ 0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
+ 0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
+ 0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
+ 0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
+ 0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
+ 0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
+ 0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
+ 0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
+ 0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
+ 0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
+ 0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
+ 0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
+ 0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
+ 0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
+ 0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
+ 0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
+ 0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
+ 0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
+ 0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
+ 0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
+ 0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
+ 0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
+ 0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
+ 0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
+ 0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
+ 0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
+ 0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
+ 0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
+ 0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
+ 0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
+ 0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
+ 0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
+ 0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
+ 0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
+ 0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
+ 0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
+ 0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
+ 0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
+ 0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
+ 0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
+ 0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
+ 0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
+ 0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
+ 0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
+ 0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
+ 0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
+ 0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
+ 0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
+ 0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
+ 0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
+ 0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
+ 0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
+ 0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
+ 0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
+ 0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
+ 0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
+ 0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
+ 0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
+ 0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
+ 0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
+ 0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
+ 0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
+ 0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
+ 0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
+ 0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
+ 0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
+ 0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
+ 0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
+ 0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
+ 0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
+ 0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
+ 0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
+ 0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
+ 0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
+ 0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
+ 0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
+ 0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
+ 0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
+ 0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
+ 0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
+ 0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
+ 0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
+ 0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
+ 0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
+ 0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
+ 0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
+ 0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
+ 0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
+ 0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
+ 0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
+ 0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
+ 0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
+ 0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
+ 0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
+ 0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
+ 0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
+ 0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
+ 0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
+ 0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
+ 0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
+ 0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
+ 0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
+ 0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
+ 0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
+ 0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
+ 0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
+ 0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
+ 0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
+ 0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
+ 0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
+ 0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
+ 0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
+ 0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
+ 0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
+ 0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
+ 0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
+ 0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
+ 0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
+ 0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
+ 0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
+ 0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
+ 0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
+ 0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
+ 0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
+ 0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
+ 0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
+ 0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
+};
+
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre> cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) </pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.
+
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+ 0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+ 0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+ 0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+ 0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+ 0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+ 0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+ 0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+ 0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+ 0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+ 0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+ 0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+ 0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+ 0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+ 0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+ 0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+ 0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+ 0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+ 0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+ 0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+ 0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+ 0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+ 0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+ 0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+ 0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+ 0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+ 0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+ 0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+ 0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+ 0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+ 0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+ 0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+ 0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+ 0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+ 0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+ 0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+ 0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+ 0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+ 0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+ 0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+ 0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+ 0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+ 0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+ 0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+ 0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+ 0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+ 0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+ 0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+ 0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+ 0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+ 0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+ 0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+ 0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+ 0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+ 0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+ 0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+ 0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+ 0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+ 0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+ 0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+ 0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+ 0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+ 0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+ 0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+ 0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+ 0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+ 0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+ 0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+ 0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+ 0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+ 0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+ 0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+ 0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+ 0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+ 0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+ 0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+ 0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+ 0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+ 0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+ 0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+ 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+ 0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+ 0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+ 0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+ 0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+ 0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+ 0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+ 0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+ 0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+ 0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+ 0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+ 0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+ 0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+ 0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+ 0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+ 0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+ 0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+ 0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+ 0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+ 0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+ 0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+ 0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+ 0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+ 0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+ 0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+ 0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+ 0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+ 0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+ 0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+ 0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+ 0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+ 0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+ 0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+ 0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+ 0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+ 0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+ 0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+ 0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+ 0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+ 0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+ 0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+ 0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+ 0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+ 0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+ 0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+ 0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+ 0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+ 0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+ 0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
+ 0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
+ 0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
+ 0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
+ 0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
+ 0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
+ 0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
+ 0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
+ 0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
+ 0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
+ 0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
+ 0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
+ 0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
+ 0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
+ 0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
+ 0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
+ 0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
+ 0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
+ 0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
+ 0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
+ 0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
+ 0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
+ 0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
+ 0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
+ 0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
+ 0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
+ 0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
+ 0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
+ 0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
+ 0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
+ 0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
+ 0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
+ 0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
+ 0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
+ 0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
+ 0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
+ 0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
+ 0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
+ 0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
+ 0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
+ 0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
+ 0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
+ 0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
+ 0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
+ 0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
+ 0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
+ 0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
+ 0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
+ 0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
+ 0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
+ 0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
+ 0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
+ 0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
+ 0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
+ 0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
+ 0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
+ 0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
+ 0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
+ 0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
+ 0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
+ 0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
+ 0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
+ 0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
+ 0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
+ 0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
+ 0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
+ 0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
+ 0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
+ 0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
+ 0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
+ 0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
+ 0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
+ 0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
+ 0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
+ 0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
+ 0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
+ 0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
+ 0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
+ 0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
+ 0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
+ 0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
+ 0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
+ 0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
+ 0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
+ 0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+ 0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+ 0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
+ 0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
+ 0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
+ 0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+ 0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+ 0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+ 0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+ 0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+ 0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+ 0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+ 0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+ 0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+ 0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+ 0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+ 0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+ 0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+ 0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+ 0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+ 0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+ 0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+ 0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+ 0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+ 0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+ 0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+ 0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+ 0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+ 0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+ 0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+ 0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+ 0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+ 0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+ 0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+ 0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+ 0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+ 0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+ 0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+ 0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+ 0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+ 0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+ 0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+ 0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+ 0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+ 0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+ 0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+ 0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+ 0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+ 0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+ 0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+ 0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+ 0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+ 0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+ 0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+ 0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+ 0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+ 0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+ 0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+ 0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+ 0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+ 0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+ 0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+ 0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+ 0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+ 0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+ 0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+ 0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+ 0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+ 0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+ 0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+ 0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+ 0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+ 0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+ 0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+ 0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+ 0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+ 0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+ 0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+ 0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+ 0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+ 0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+ 0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+ 0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+ 0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+ 0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+ 0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+ 0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+ 0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+ 0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+ 0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+ 0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+ 0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+ 0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+ 0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+ 0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+ 0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+ 0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+ 0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+ 0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+ 0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+ 0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+ 0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+ 0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+ 0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+ 0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+ 0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+ 0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+ 0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+ 0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+ 0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+ 0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+ 0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+ 0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+ 0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+ 0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+ 0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+ 0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+ 0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+ 0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+ 0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+ 0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
+ 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
+ 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
+ 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
+ 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
+ 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
+ 0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
+ 0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
+ 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
+ 0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
+ 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
+ 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
+ 0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
+ 0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
+ 0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
+ 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
+ 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
+ 0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
+ 0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
+ 0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
+ 0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+ 0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
+ 0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
+ 0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
+ 0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
+ 0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
+ 0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
+ 0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
+ 0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
+ 0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
+ 0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
+ 0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
+ 0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
+ 0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
+ 0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
+ 0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
+ 0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
+ 0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
+ 0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
+ 0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
+ 0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
+ 0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
+ 0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
+ 0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
+ 0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
+ 0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
+ 0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
+ 0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
+ 0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,
+ 0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
+ 0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,
+ 0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,
+ 0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,
+ 0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,
+ 0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,
+ 0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,
+ 0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,
+ 0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
+ 0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,
+ 0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,
+ 0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
+ 0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
+ 0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
+ 0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
+ 0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
+ 0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
+ 0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
+ 0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
+ 0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
+ 0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
+ 0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
+ 0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
+ 0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
+ 0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
+ 0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
+ 0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
+ 0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
+ 0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
+ 0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
+ 0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
+ 0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
+ 0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
+ 0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
+ 0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
+ 0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
+ 0x7ea4, 0x7ea3, 0x7ea2, 0x7ea1, 0x7ea0, 0x7e9f, 0x7e9e, 0x7e9d,
+ 0x7e9c, 0x7e9b, 0x7e9b, 0x7e9a, 0x7e99, 0x7e98, 0x7e97, 0x7e96,
+ 0x7e95, 0x7e94, 0x7e93, 0x7e92, 0x7e91, 0x7e90, 0x7e8f, 0x7e8e,
+ 0x7e8d, 0x7e8d, 0x7e8c, 0x7e8b, 0x7e8a, 0x7e89, 0x7e88, 0x7e87,
+ 0x7e86, 0x7e85, 0x7e84, 0x7e83, 0x7e82, 0x7e81, 0x7e80, 0x7e7f,
+ 0x7e7e, 0x7e7d, 0x7e7c, 0x7e7b, 0x7e7a, 0x7e79, 0x7e78, 0x7e77,
+ 0x7e77, 0x7e76, 0x7e75, 0x7e74, 0x7e73, 0x7e72, 0x7e71, 0x7e70,
+ 0x7e6f, 0x7e6e, 0x7e6d, 0x7e6c, 0x7e6b, 0x7e6a, 0x7e69, 0x7e68,
+ 0x7e67, 0x7e66, 0x7e65, 0x7e64, 0x7e63, 0x7e62, 0x7e61, 0x7e60,
+ 0x7e5f, 0x7e5e, 0x7e5d, 0x7e5c, 0x7e5b, 0x7e5a, 0x7e59, 0x7e58,
+ 0x7e57, 0x7e56, 0x7e55, 0x7e54, 0x7e53, 0x7e52, 0x7e51, 0x7e50,
+ 0x7e4f, 0x7e4e, 0x7e4d, 0x7e4c, 0x7e4b, 0x7e4a, 0x7e49, 0x7e48,
+ 0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,
+ 0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,
+ 0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,
+ 0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,
+ 0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,
+ 0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,
+ 0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,
+ 0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,
+ 0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,
+ 0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,
+ 0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,
+ 0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,
+ 0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,
+ 0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,
+ 0x7dcc, 0x7dcb, 0x7dca, 0x7dc9, 0x7dc7, 0x7dc6, 0x7dc5, 0x7dc4,
+ 0x7dc3, 0x7dc2, 0x7dc0, 0x7dbf, 0x7dbe, 0x7dbd, 0x7dbc, 0x7dbb,
+ 0x7db9, 0x7db8, 0x7db7, 0x7db6, 0x7db5, 0x7db3, 0x7db2, 0x7db1,
+ 0x7db0, 0x7daf, 0x7dae, 0x7dac, 0x7dab, 0x7daa, 0x7da9, 0x7da8,
+ 0x7da6, 0x7da5, 0x7da4, 0x7da3, 0x7da2, 0x7da0, 0x7d9f, 0x7d9e,
+ 0x7d9d, 0x7d9c, 0x7d9a, 0x7d99, 0x7d98, 0x7d97, 0x7d95, 0x7d94,
+ 0x7d93, 0x7d92, 0x7d91, 0x7d8f, 0x7d8e, 0x7d8d, 0x7d8c, 0x7d8a,
+ 0x7d89, 0x7d88, 0x7d87, 0x7d86, 0x7d84, 0x7d83, 0x7d82, 0x7d81,
+ 0x7d7f, 0x7d7e, 0x7d7d, 0x7d7c, 0x7d7a, 0x7d79, 0x7d78, 0x7d77,
+ 0x7d75, 0x7d74, 0x7d73, 0x7d72, 0x7d70, 0x7d6f, 0x7d6e, 0x7d6d,
+ 0x7d6b, 0x7d6a, 0x7d69, 0x7d68, 0x7d66, 0x7d65, 0x7d64, 0x7d63,
+ 0x7d61, 0x7d60, 0x7d5f, 0x7d5e, 0x7d5c, 0x7d5b, 0x7d5a, 0x7d59,
+ 0x7d57, 0x7d56, 0x7d55, 0x7d53, 0x7d52, 0x7d51, 0x7d50, 0x7d4e,
+ 0x7d4d, 0x7d4c, 0x7d4a, 0x7d49, 0x7d48, 0x7d47, 0x7d45, 0x7d44,
+ 0x7d43, 0x7d41, 0x7d40, 0x7d3f, 0x7d3e, 0x7d3c, 0x7d3b, 0x7d3a,
+ 0x7d38, 0x7d37, 0x7d36, 0x7d34, 0x7d33, 0x7d32, 0x7d31, 0x7d2f,
+ 0x7d2e, 0x7d2d, 0x7d2b, 0x7d2a, 0x7d29, 0x7d27, 0x7d26, 0x7d25,
+ 0x7d23, 0x7d22, 0x7d21, 0x7d1f, 0x7d1e, 0x7d1d, 0x7d1b, 0x7d1a,
+ 0x7d19, 0x7d17, 0x7d16, 0x7d15, 0x7d13, 0x7d12, 0x7d11, 0x7d0f,
+ 0x7d0e, 0x7d0d, 0x7d0b, 0x7d0a, 0x7d09, 0x7d07, 0x7d06, 0x7d05,
+ 0x7d03, 0x7d02, 0x7d01, 0x7cff, 0x7cfe, 0x7cfd, 0x7cfb, 0x7cfa,
+ 0x7cf9, 0x7cf7, 0x7cf6, 0x7cf4, 0x7cf3, 0x7cf2, 0x7cf0, 0x7cef,
+ 0x7cee, 0x7cec, 0x7ceb, 0x7ce9, 0x7ce8, 0x7ce7, 0x7ce5, 0x7ce4,
+ 0x7ce3, 0x7ce1, 0x7ce0, 0x7cde, 0x7cdd, 0x7cdc, 0x7cda, 0x7cd9,
+ 0x7cd8, 0x7cd6, 0x7cd5, 0x7cd3, 0x7cd2, 0x7cd1, 0x7ccf, 0x7cce,
+ 0x7ccc, 0x7ccb, 0x7cca, 0x7cc8, 0x7cc7, 0x7cc5, 0x7cc4, 0x7cc3,
+ 0x7cc1, 0x7cc0, 0x7cbe, 0x7cbd, 0x7cbc, 0x7cba, 0x7cb9, 0x7cb7,
+ 0x7cb6, 0x7cb5, 0x7cb3, 0x7cb2, 0x7cb0, 0x7caf, 0x7cad, 0x7cac,
+ 0x7cab, 0x7ca9, 0x7ca8, 0x7ca6, 0x7ca5, 0x7ca3, 0x7ca2, 0x7ca1,
+ 0x7c9f, 0x7c9e, 0x7c9c, 0x7c9b, 0x7c99, 0x7c98, 0x7c97, 0x7c95,
+ 0x7c94, 0x7c92, 0x7c91, 0x7c8f, 0x7c8e, 0x7c8c, 0x7c8b, 0x7c8a,
+ 0x7c88, 0x7c87, 0x7c85, 0x7c84, 0x7c82, 0x7c81, 0x7c7f, 0x7c7e,
+ 0x7c7c, 0x7c7b, 0x7c79, 0x7c78, 0x7c77, 0x7c75, 0x7c74, 0x7c72,
+ 0x7c71, 0x7c6f, 0x7c6e, 0x7c6c, 0x7c6b, 0x7c69, 0x7c68, 0x7c66,
+ 0x7c65, 0x7c63, 0x7c62, 0x7c60, 0x7c5f, 0x7c5d, 0x7c5c, 0x7c5a,
+ 0x7c59, 0x7c58, 0x7c56, 0x7c55, 0x7c53, 0x7c52, 0x7c50, 0x7c4f,
+ 0x7c4d, 0x7c4c, 0x7c4a, 0x7c49, 0x7c47, 0x7c46, 0x7c44, 0x7c43,
+ 0x7c41, 0x7c3f, 0x7c3e, 0x7c3c, 0x7c3b, 0x7c39, 0x7c38, 0x7c36,
+ 0x7c35, 0x7c33, 0x7c32, 0x7c30, 0x7c2f, 0x7c2d, 0x7c2c, 0x7c2a,
+ 0x7c29, 0x7c27, 0x7c26, 0x7c24, 0x7c23, 0x7c21, 0x7c20, 0x7c1e,
+ 0x7c1c, 0x7c1b, 0x7c19, 0x7c18, 0x7c16, 0x7c15, 0x7c13, 0x7c12,
+ 0x7c10, 0x7c0f, 0x7c0d, 0x7c0b, 0x7c0a, 0x7c08, 0x7c07, 0x7c05,
+ 0x7c04, 0x7c02, 0x7c01, 0x7bff, 0x7bfd, 0x7bfc, 0x7bfa, 0x7bf9,
+ 0x7bf7, 0x7bf6, 0x7bf4, 0x7bf3, 0x7bf1, 0x7bef, 0x7bee, 0x7bec,
+ 0x7beb, 0x7be9, 0x7be8, 0x7be6, 0x7be4, 0x7be3, 0x7be1, 0x7be0,
+ 0x7bde, 0x7bdc, 0x7bdb, 0x7bd9, 0x7bd8, 0x7bd6, 0x7bd5, 0x7bd3,
+ 0x7bd1, 0x7bd0, 0x7bce, 0x7bcd, 0x7bcb, 0x7bc9, 0x7bc8, 0x7bc6,
+ 0x7bc5, 0x7bc3, 0x7bc1, 0x7bc0, 0x7bbe, 0x7bbd, 0x7bbb, 0x7bb9,
+ 0x7bb8, 0x7bb6, 0x7bb5, 0x7bb3, 0x7bb1, 0x7bb0, 0x7bae, 0x7bac,
+ 0x7bab, 0x7ba9, 0x7ba8, 0x7ba6, 0x7ba4, 0x7ba3, 0x7ba1, 0x7b9f,
+ 0x7b9e, 0x7b9c, 0x7b9b, 0x7b99, 0x7b97, 0x7b96, 0x7b94, 0x7b92,
+ 0x7b91, 0x7b8f, 0x7b8d, 0x7b8c, 0x7b8a, 0x7b89, 0x7b87, 0x7b85,
+ 0x7b84, 0x7b82, 0x7b80, 0x7b7f, 0x7b7d, 0x7b7b, 0x7b7a, 0x7b78,
+ 0x7b76, 0x7b75, 0x7b73, 0x7b71, 0x7b70, 0x7b6e, 0x7b6c, 0x7b6b,
+ 0x7b69, 0x7b67, 0x7b66, 0x7b64, 0x7b62, 0x7b61, 0x7b5f, 0x7b5d,
+ 0x7b5c, 0x7b5a, 0x7b58, 0x7b57, 0x7b55, 0x7b53, 0x7b52, 0x7b50,
+ 0x7b4e, 0x7b4d, 0x7b4b, 0x7b49, 0x7b47, 0x7b46, 0x7b44, 0x7b42,
+ 0x7b41, 0x7b3f, 0x7b3d, 0x7b3c, 0x7b3a, 0x7b38, 0x7b37, 0x7b35,
+ 0x7b33, 0x7b31, 0x7b30, 0x7b2e, 0x7b2c, 0x7b2b, 0x7b29, 0x7b27,
+ 0x7b25, 0x7b24, 0x7b22, 0x7b20, 0x7b1f, 0x7b1d, 0x7b1b, 0x7b19,
+ 0x7b18, 0x7b16, 0x7b14, 0x7b13, 0x7b11, 0x7b0f, 0x7b0d, 0x7b0c,
+ 0x7b0a, 0x7b08, 0x7b06, 0x7b05, 0x7b03, 0x7b01, 0x7aff, 0x7afe,
+ 0x7afc, 0x7afa, 0x7af8, 0x7af7, 0x7af5, 0x7af3, 0x7af2, 0x7af0,
+ 0x7aee, 0x7aec, 0x7aeb, 0x7ae9, 0x7ae7, 0x7ae5, 0x7ae3, 0x7ae2,
+ 0x7ae0, 0x7ade, 0x7adc, 0x7adb, 0x7ad9, 0x7ad7, 0x7ad5, 0x7ad4,
+ 0x7ad2, 0x7ad0, 0x7ace, 0x7acd, 0x7acb, 0x7ac9, 0x7ac7, 0x7ac5,
+ 0x7ac4, 0x7ac2, 0x7ac0, 0x7abe, 0x7abd, 0x7abb, 0x7ab9, 0x7ab7,
+ 0x7ab5, 0x7ab4, 0x7ab2, 0x7ab0, 0x7aae, 0x7aac, 0x7aab, 0x7aa9,
+ 0x7aa7, 0x7aa5, 0x7aa3, 0x7aa2, 0x7aa0, 0x7a9e, 0x7a9c, 0x7a9a,
+ 0x7a99, 0x7a97, 0x7a95, 0x7a93, 0x7a91, 0x7a90, 0x7a8e, 0x7a8c,
+ 0x7a8a, 0x7a88, 0x7a87, 0x7a85, 0x7a83, 0x7a81, 0x7a7f, 0x7a7d,
+ 0x7a7c, 0x7a7a, 0x7a78, 0x7a76, 0x7a74, 0x7a72, 0x7a71, 0x7a6f,
+ 0x7a6d, 0x7a6b, 0x7a69, 0x7a67, 0x7a66, 0x7a64, 0x7a62, 0x7a60,
+ 0x7a5e, 0x7a5c, 0x7a5b, 0x7a59, 0x7a57, 0x7a55, 0x7a53, 0x7a51,
+ 0x7a4f, 0x7a4e, 0x7a4c, 0x7a4a, 0x7a48, 0x7a46, 0x7a44, 0x7a42,
+ 0x7a41, 0x7a3f, 0x7a3d, 0x7a3b, 0x7a39, 0x7a37, 0x7a35, 0x7a34,
+ 0x7a32, 0x7a30, 0x7a2e, 0x7a2c, 0x7a2a, 0x7a28, 0x7a26, 0x7a25,
+ 0x7a23, 0x7a21, 0x7a1f, 0x7a1d, 0x7a1b, 0x7a19, 0x7a17, 0x7a16,
+ 0x7a14, 0x7a12, 0x7a10, 0x7a0e, 0x7a0c, 0x7a0a, 0x7a08, 0x7a06,
+ 0x7a04, 0x7a03, 0x7a01, 0x79ff, 0x79fd, 0x79fb, 0x79f9, 0x79f7,
+ 0x79f5, 0x79f3, 0x79f1, 0x79f0, 0x79ee, 0x79ec, 0x79ea, 0x79e8,
+ 0x79e6, 0x79e4, 0x79e2, 0x79e0, 0x79de, 0x79dc, 0x79da, 0x79d9,
+ 0x79d7, 0x79d5, 0x79d3, 0x79d1, 0x79cf, 0x79cd, 0x79cb, 0x79c9,
+ 0x79c7, 0x79c5, 0x79c3, 0x79c1, 0x79bf, 0x79bd, 0x79bc, 0x79ba,
+ 0x79b8, 0x79b6, 0x79b4, 0x79b2, 0x79b0, 0x79ae, 0x79ac, 0x79aa,
+ 0x79a8, 0x79a6, 0x79a4, 0x79a2, 0x79a0, 0x799e, 0x799c, 0x799a,
+ 0x7998, 0x7996, 0x7994, 0x7992, 0x7991, 0x798f, 0x798d, 0x798b,
+ 0x7989, 0x7987, 0x7985, 0x7983, 0x7981, 0x797f, 0x797d, 0x797b,
+ 0x7979, 0x7977, 0x7975, 0x7973, 0x7971, 0x796f, 0x796d, 0x796b,
+ 0x7969, 0x7967, 0x7965, 0x7963, 0x7961, 0x795f, 0x795d, 0x795b,
+ 0x7959, 0x7957, 0x7955, 0x7953, 0x7951, 0x794f, 0x794d, 0x794b,
+ 0x7949, 0x7947, 0x7945, 0x7943, 0x7941, 0x793f, 0x793d, 0x793b,
+ 0x7939, 0x7937, 0x7935, 0x7933, 0x7931, 0x792f, 0x792d, 0x792b,
+ 0x7929, 0x7927, 0x7925, 0x7923, 0x7921, 0x791f, 0x791d, 0x791a,
+ 0x7918, 0x7916, 0x7914, 0x7912, 0x7910, 0x790e, 0x790c, 0x790a,
+ 0x7908, 0x7906, 0x7904, 0x7902, 0x7900, 0x78fe, 0x78fc, 0x78fa,
+ 0x78f8, 0x78f6, 0x78f4, 0x78f2, 0x78f0, 0x78ed, 0x78eb, 0x78e9,
+ 0x78e7, 0x78e5, 0x78e3, 0x78e1, 0x78df, 0x78dd, 0x78db, 0x78d9,
+ 0x78d7, 0x78d5, 0x78d3, 0x78d1, 0x78ce, 0x78cc, 0x78ca, 0x78c8,
+ 0x78c6, 0x78c4, 0x78c2, 0x78c0, 0x78be, 0x78bc, 0x78ba, 0x78b8,
+ 0x78b5, 0x78b3, 0x78b1, 0x78af, 0x78ad, 0x78ab, 0x78a9, 0x78a7,
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+ 0x7894, 0x7892, 0x7890, 0x788e, 0x788b, 0x7889, 0x7887, 0x7885,
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+ 0x5300, 0x52fb, 0x52f6, 0x52f1, 0x52ec, 0x52e8, 0x52e3, 0x52de,
+ 0x52d9, 0x52d5, 0x52d0, 0x52cb, 0x52c6, 0x52c1, 0x52bd, 0x52b8,
+ 0x52b3, 0x52ae, 0x52a9, 0x52a5, 0x52a0, 0x529b, 0x5296, 0x5291,
+ 0x528d, 0x5288, 0x5283, 0x527e, 0x5279, 0x5275, 0x5270, 0x526b,
+ 0x5266, 0x5261, 0x525d, 0x5258, 0x5253, 0x524e, 0x5249, 0x5244,
+ 0x5240, 0x523b, 0x5236, 0x5231, 0x522c, 0x5228, 0x5223, 0x521e,
+ 0x5219, 0x5214, 0x520f, 0x520b, 0x5206, 0x5201, 0x51fc, 0x51f7,
+ 0x51f3, 0x51ee, 0x51e9, 0x51e4, 0x51df, 0x51da, 0x51d6, 0x51d1,
+ 0x51cc, 0x51c7, 0x51c2, 0x51bd, 0x51b9, 0x51b4, 0x51af, 0x51aa,
+ 0x51a5, 0x51a0, 0x519c, 0x5197, 0x5192, 0x518d, 0x5188, 0x5183,
+ 0x517e, 0x517a, 0x5175, 0x5170, 0x516b, 0x5166, 0x5161, 0x515d,
+ 0x5158, 0x5153, 0x514e, 0x5149, 0x5144, 0x513f, 0x513b, 0x5136,
+ 0x5131, 0x512c, 0x5127, 0x5122, 0x511d, 0x5119, 0x5114, 0x510f,
+ 0x510a, 0x5105, 0x5100, 0x50fb, 0x50f7, 0x50f2, 0x50ed, 0x50e8,
+ 0x50e3, 0x50de, 0x50d9, 0x50d4, 0x50d0, 0x50cb, 0x50c6, 0x50c1,
+ 0x50bc, 0x50b7, 0x50b2, 0x50ad, 0x50a9, 0x50a4, 0x509f, 0x509a,
+ 0x5095, 0x5090, 0x508b, 0x5086, 0x5082, 0x507d, 0x5078, 0x5073,
+ 0x506e, 0x5069, 0x5064, 0x505f, 0x505a, 0x5056, 0x5051, 0x504c,
+ 0x5047, 0x5042, 0x503d, 0x5038, 0x5033, 0x502e, 0x5029, 0x5025,
+ 0x5020, 0x501b, 0x5016, 0x5011, 0x500c, 0x5007, 0x5002, 0x4ffd,
+ 0x4ff8, 0x4ff4, 0x4fef, 0x4fea, 0x4fe5, 0x4fe0, 0x4fdb, 0x4fd6,
+ 0x4fd1, 0x4fcc, 0x4fc7, 0x4fc2, 0x4fbe, 0x4fb9, 0x4fb4, 0x4faf,
+ 0x4faa, 0x4fa5, 0x4fa0, 0x4f9b, 0x4f96, 0x4f91, 0x4f8c, 0x4f87,
+ 0x4f82, 0x4f7e, 0x4f79, 0x4f74, 0x4f6f, 0x4f6a, 0x4f65, 0x4f60,
+ 0x4f5b, 0x4f56, 0x4f51, 0x4f4c, 0x4f47, 0x4f42, 0x4f3d, 0x4f39,
+ 0x4f34, 0x4f2f, 0x4f2a, 0x4f25, 0x4f20, 0x4f1b, 0x4f16, 0x4f11,
+ 0x4f0c, 0x4f07, 0x4f02, 0x4efd, 0x4ef8, 0x4ef3, 0x4eee, 0x4ee9,
+ 0x4ee5, 0x4ee0, 0x4edb, 0x4ed6, 0x4ed1, 0x4ecc, 0x4ec7, 0x4ec2,
+ 0x4ebd, 0x4eb8, 0x4eb3, 0x4eae, 0x4ea9, 0x4ea4, 0x4e9f, 0x4e9a,
+ 0x4e95, 0x4e90, 0x4e8b, 0x4e86, 0x4e81, 0x4e7c, 0x4e78, 0x4e73,
+ 0x4e6e, 0x4e69, 0x4e64, 0x4e5f, 0x4e5a, 0x4e55, 0x4e50, 0x4e4b,
+ 0x4e46, 0x4e41, 0x4e3c, 0x4e37, 0x4e32, 0x4e2d, 0x4e28, 0x4e23,
+ 0x4e1e, 0x4e19, 0x4e14, 0x4e0f, 0x4e0a, 0x4e05, 0x4e00, 0x4dfb,
+ 0x4df6, 0x4df1, 0x4dec, 0x4de7, 0x4de2, 0x4ddd, 0x4dd8, 0x4dd3,
+ 0x4dce, 0x4dc9, 0x4dc4, 0x4dbf, 0x4dba, 0x4db5, 0x4db0, 0x4dab,
+ 0x4da6, 0x4da1, 0x4d9c, 0x4d97, 0x4d92, 0x4d8d, 0x4d88, 0x4d83,
+ 0x4d7e, 0x4d79, 0x4d74, 0x4d6f, 0x4d6a, 0x4d65, 0x4d60, 0x4d5b,
+ 0x4d56, 0x4d51, 0x4d4c, 0x4d47, 0x4d42, 0x4d3d, 0x4d38, 0x4d33,
+ 0x4d2e, 0x4d29, 0x4d24, 0x4d1f, 0x4d1a, 0x4d15, 0x4d10, 0x4d0b,
+ 0x4d06, 0x4d01, 0x4cfc, 0x4cf7, 0x4cf2, 0x4ced, 0x4ce8, 0x4ce3,
+ 0x4cde, 0x4cd9, 0x4cd4, 0x4ccf, 0x4cca, 0x4cc5, 0x4cc0, 0x4cbb,
+ 0x4cb6, 0x4cb1, 0x4cac, 0x4ca7, 0x4ca2, 0x4c9d, 0x4c98, 0x4c93,
+ 0x4c8e, 0x4c88, 0x4c83, 0x4c7e, 0x4c79, 0x4c74, 0x4c6f, 0x4c6a,
+ 0x4c65, 0x4c60, 0x4c5b, 0x4c56, 0x4c51, 0x4c4c, 0x4c47, 0x4c42,
+ 0x4c3d, 0x4c38, 0x4c33, 0x4c2e, 0x4c29, 0x4c24, 0x4c1f, 0x4c1a,
+ 0x4c14, 0x4c0f, 0x4c0a, 0x4c05, 0x4c00, 0x4bfb, 0x4bf6, 0x4bf1,
+ 0x4bec, 0x4be7, 0x4be2, 0x4bdd, 0x4bd8, 0x4bd3, 0x4bce, 0x4bc9,
+ 0x4bc4, 0x4bbe, 0x4bb9, 0x4bb4, 0x4baf, 0x4baa, 0x4ba5, 0x4ba0,
+ 0x4b9b, 0x4b96, 0x4b91, 0x4b8c, 0x4b87, 0x4b82, 0x4b7d, 0x4b77,
+ 0x4b72, 0x4b6d, 0x4b68, 0x4b63, 0x4b5e, 0x4b59, 0x4b54, 0x4b4f,
+ 0x4b4a, 0x4b45, 0x4b40, 0x4b3b, 0x4b35, 0x4b30, 0x4b2b, 0x4b26,
+ 0x4b21, 0x4b1c, 0x4b17, 0x4b12, 0x4b0d, 0x4b08, 0x4b03, 0x4afd,
+ 0x4af8, 0x4af3, 0x4aee, 0x4ae9, 0x4ae4, 0x4adf, 0x4ada, 0x4ad5,
+ 0x4ad0, 0x4acb, 0x4ac5, 0x4ac0, 0x4abb, 0x4ab6, 0x4ab1, 0x4aac,
+ 0x4aa7, 0x4aa2, 0x4a9d, 0x4a97, 0x4a92, 0x4a8d, 0x4a88, 0x4a83,
+ 0x4a7e, 0x4a79, 0x4a74, 0x4a6f, 0x4a6a, 0x4a64, 0x4a5f, 0x4a5a,
+ 0x4a55, 0x4a50, 0x4a4b, 0x4a46, 0x4a41, 0x4a3b, 0x4a36, 0x4a31,
+ 0x4a2c, 0x4a27, 0x4a22, 0x4a1d, 0x4a18, 0x4a12, 0x4a0d, 0x4a08,
+ 0x4a03, 0x49fe, 0x49f9, 0x49f4, 0x49ef, 0x49e9, 0x49e4, 0x49df,
+ 0x49da, 0x49d5, 0x49d0, 0x49cb, 0x49c6, 0x49c0, 0x49bb, 0x49b6,
+ 0x49b1, 0x49ac, 0x49a7, 0x49a2, 0x499c, 0x4997, 0x4992, 0x498d,
+ 0x4988, 0x4983, 0x497e, 0x4978, 0x4973, 0x496e, 0x4969, 0x4964,
+ 0x495f, 0x495a, 0x4954, 0x494f, 0x494a, 0x4945, 0x4940, 0x493b,
+ 0x4936, 0x4930, 0x492b, 0x4926, 0x4921, 0x491c, 0x4917, 0x4911,
+ 0x490c, 0x4907, 0x4902, 0x48fd, 0x48f8, 0x48f2, 0x48ed, 0x48e8,
+ 0x48e3, 0x48de, 0x48d9, 0x48d3, 0x48ce, 0x48c9, 0x48c4, 0x48bf,
+ 0x48ba, 0x48b4, 0x48af, 0x48aa, 0x48a5, 0x48a0, 0x489b, 0x4895,
+ 0x4890, 0x488b, 0x4886, 0x4881, 0x487c, 0x4876, 0x4871, 0x486c,
+ 0x4867, 0x4862, 0x485c, 0x4857, 0x4852, 0x484d, 0x4848, 0x4843,
+ 0x483d, 0x4838, 0x4833, 0x482e, 0x4829, 0x4823, 0x481e, 0x4819,
+ 0x4814, 0x480f, 0x4809, 0x4804, 0x47ff, 0x47fa, 0x47f5, 0x47ef,
+ 0x47ea, 0x47e5, 0x47e0, 0x47db, 0x47d5, 0x47d0, 0x47cb, 0x47c6,
+ 0x47c1, 0x47bb, 0x47b6, 0x47b1, 0x47ac, 0x47a7, 0x47a1, 0x479c,
+ 0x4797, 0x4792, 0x478d, 0x4787, 0x4782, 0x477d, 0x4778, 0x4773,
+ 0x476d, 0x4768, 0x4763, 0x475e, 0x4758, 0x4753, 0x474e, 0x4749,
+ 0x4744, 0x473e, 0x4739, 0x4734, 0x472f, 0x4729, 0x4724, 0x471f,
+ 0x471a, 0x4715, 0x470f, 0x470a, 0x4705, 0x4700, 0x46fa, 0x46f5,
+ 0x46f0, 0x46eb, 0x46e6, 0x46e0, 0x46db, 0x46d6, 0x46d1, 0x46cb,
+ 0x46c6, 0x46c1, 0x46bc, 0x46b6, 0x46b1, 0x46ac, 0x46a7, 0x46a1,
+ 0x469c, 0x4697, 0x4692, 0x468d, 0x4687, 0x4682, 0x467d, 0x4678,
+ 0x4672, 0x466d, 0x4668, 0x4663, 0x465d, 0x4658, 0x4653, 0x464e,
+ 0x4648, 0x4643, 0x463e, 0x4639, 0x4633, 0x462e, 0x4629, 0x4624,
+ 0x461e, 0x4619, 0x4614, 0x460e, 0x4609, 0x4604, 0x45ff, 0x45f9,
+ 0x45f4, 0x45ef, 0x45ea, 0x45e4, 0x45df, 0x45da, 0x45d5, 0x45cf,
+ 0x45ca, 0x45c5, 0x45c0, 0x45ba, 0x45b5, 0x45b0, 0x45aa, 0x45a5,
+ 0x45a0, 0x459b, 0x4595, 0x4590, 0x458b, 0x4586, 0x4580, 0x457b,
+ 0x4576, 0x4570, 0x456b, 0x4566, 0x4561, 0x455b, 0x4556, 0x4551,
+ 0x454b, 0x4546, 0x4541, 0x453c, 0x4536, 0x4531, 0x452c, 0x4526,
+ 0x4521, 0x451c, 0x4517, 0x4511, 0x450c, 0x4507, 0x4501, 0x44fc,
+ 0x44f7, 0x44f2, 0x44ec, 0x44e7, 0x44e2, 0x44dc, 0x44d7, 0x44d2,
+ 0x44cd, 0x44c7, 0x44c2, 0x44bd, 0x44b7, 0x44b2, 0x44ad, 0x44a7,
+ 0x44a2, 0x449d, 0x4497, 0x4492, 0x448d, 0x4488, 0x4482, 0x447d,
+ 0x4478, 0x4472, 0x446d, 0x4468, 0x4462, 0x445d, 0x4458, 0x4452,
+ 0x444d, 0x4448, 0x4443, 0x443d, 0x4438, 0x4433, 0x442d, 0x4428,
+ 0x4423, 0x441d, 0x4418, 0x4413, 0x440d, 0x4408, 0x4403, 0x43fd,
+ 0x43f8, 0x43f3, 0x43ed, 0x43e8, 0x43e3, 0x43dd, 0x43d8, 0x43d3,
+ 0x43cd, 0x43c8, 0x43c3, 0x43bd, 0x43b8, 0x43b3, 0x43ad, 0x43a8,
+ 0x43a3, 0x439d, 0x4398, 0x4393, 0x438d, 0x4388, 0x4383, 0x437d,
+ 0x4378, 0x4373, 0x436d, 0x4368, 0x4363, 0x435d, 0x4358, 0x4353,
+ 0x434d, 0x4348, 0x4343, 0x433d, 0x4338, 0x4333, 0x432d, 0x4328,
+ 0x4323, 0x431d, 0x4318, 0x4313, 0x430d, 0x4308, 0x4302, 0x42fd,
+ 0x42f8, 0x42f2, 0x42ed, 0x42e8, 0x42e2, 0x42dd, 0x42d8, 0x42d2,
+ 0x42cd, 0x42c8, 0x42c2, 0x42bd, 0x42b7, 0x42b2, 0x42ad, 0x42a7,
+ 0x42a2, 0x429d, 0x4297, 0x4292, 0x428d, 0x4287, 0x4282, 0x427c,
+ 0x4277, 0x4272, 0x426c, 0x4267, 0x4262, 0x425c, 0x4257, 0x4251,
+ 0x424c, 0x4247, 0x4241, 0x423c, 0x4237, 0x4231, 0x422c, 0x4226,
+ 0x4221, 0x421c, 0x4216, 0x4211, 0x420c, 0x4206, 0x4201, 0x41fb,
+ 0x41f6, 0x41f1, 0x41eb, 0x41e6, 0x41e0, 0x41db, 0x41d6, 0x41d0,
+ 0x41cb, 0x41c6, 0x41c0, 0x41bb, 0x41b5, 0x41b0, 0x41ab, 0x41a5,
+ 0x41a0, 0x419a, 0x4195, 0x4190, 0x418a, 0x4185, 0x417f, 0x417a,
+ 0x4175, 0x416f, 0x416a, 0x4164, 0x415f, 0x415a, 0x4154, 0x414f,
+ 0x4149, 0x4144, 0x413f, 0x4139, 0x4134, 0x412e, 0x4129, 0x4124,
+ 0x411e, 0x4119, 0x4113, 0x410e, 0x4108, 0x4103, 0x40fe, 0x40f8,
+ 0x40f3, 0x40ed, 0x40e8, 0x40e3, 0x40dd, 0x40d8, 0x40d2, 0x40cd,
+ 0x40c8, 0x40c2, 0x40bd, 0x40b7, 0x40b2, 0x40ac, 0x40a7, 0x40a2,
+ 0x409c, 0x4097, 0x4091, 0x408c, 0x4086, 0x4081, 0x407c, 0x4076,
+ 0x4071, 0x406b, 0x4066, 0x4060, 0x405b, 0x4056, 0x4050, 0x404b,
+ 0x4045, 0x4040, 0x403a, 0x4035, 0x4030, 0x402a, 0x4025, 0x401f,
+ 0x401a, 0x4014, 0x400f, 0x4009, 0x4004, 0x3fff, 0x3ff9, 0x3ff4,
+ 0x3fee, 0x3fe9, 0x3fe3, 0x3fde, 0x3fd8, 0x3fd3, 0x3fce, 0x3fc8,
+ 0x3fc3, 0x3fbd, 0x3fb8, 0x3fb2, 0x3fad, 0x3fa7, 0x3fa2, 0x3f9d,
+ 0x3f97, 0x3f92, 0x3f8c, 0x3f87, 0x3f81, 0x3f7c, 0x3f76, 0x3f71,
+ 0x3f6b, 0x3f66, 0x3f61, 0x3f5b, 0x3f56, 0x3f50, 0x3f4b, 0x3f45,
+ 0x3f40, 0x3f3a, 0x3f35, 0x3f2f, 0x3f2a, 0x3f24, 0x3f1f, 0x3f1a,
+ 0x3f14, 0x3f0f, 0x3f09, 0x3f04, 0x3efe, 0x3ef9, 0x3ef3, 0x3eee,
+ 0x3ee8, 0x3ee3, 0x3edd, 0x3ed8, 0x3ed2, 0x3ecd, 0x3ec7, 0x3ec2,
+ 0x3ebd, 0x3eb7, 0x3eb2, 0x3eac, 0x3ea7, 0x3ea1, 0x3e9c, 0x3e96,
+ 0x3e91, 0x3e8b, 0x3e86, 0x3e80, 0x3e7b, 0x3e75, 0x3e70, 0x3e6a,
+ 0x3e65, 0x3e5f, 0x3e5a, 0x3e54, 0x3e4f, 0x3e49, 0x3e44, 0x3e3e,
+ 0x3e39, 0x3e33, 0x3e2e, 0x3e28, 0x3e23, 0x3e1d, 0x3e18, 0x3e12,
+ 0x3e0d, 0x3e07, 0x3e02, 0x3dfc, 0x3df7, 0x3df1, 0x3dec, 0x3de6,
+ 0x3de1, 0x3ddb, 0x3dd6, 0x3dd0, 0x3dcb, 0x3dc5, 0x3dc0, 0x3dba,
+ 0x3db5, 0x3daf, 0x3daa, 0x3da4, 0x3d9f, 0x3d99, 0x3d94, 0x3d8e,
+ 0x3d89, 0x3d83, 0x3d7e, 0x3d78, 0x3d73, 0x3d6d, 0x3d68, 0x3d62,
+ 0x3d5d, 0x3d57, 0x3d52, 0x3d4c, 0x3d47, 0x3d41, 0x3d3c, 0x3d36,
+ 0x3d31, 0x3d2b, 0x3d26, 0x3d20, 0x3d1b, 0x3d15, 0x3d10, 0x3d0a,
+ 0x3d04, 0x3cff, 0x3cf9, 0x3cf4, 0x3cee, 0x3ce9, 0x3ce3, 0x3cde,
+ 0x3cd8, 0x3cd3, 0x3ccd, 0x3cc8, 0x3cc2, 0x3cbd, 0x3cb7, 0x3cb2,
+ 0x3cac, 0x3ca7, 0x3ca1, 0x3c9b, 0x3c96, 0x3c90, 0x3c8b, 0x3c85,
+ 0x3c80, 0x3c7a, 0x3c75, 0x3c6f, 0x3c6a, 0x3c64, 0x3c5f, 0x3c59,
+ 0x3c53, 0x3c4e, 0x3c48, 0x3c43, 0x3c3d, 0x3c38, 0x3c32, 0x3c2d,
+ 0x3c27, 0x3c22, 0x3c1c, 0x3c16, 0x3c11, 0x3c0b, 0x3c06, 0x3c00,
+ 0x3bfb, 0x3bf5, 0x3bf0, 0x3bea, 0x3be5, 0x3bdf, 0x3bd9, 0x3bd4,
+ 0x3bce, 0x3bc9, 0x3bc3, 0x3bbe, 0x3bb8, 0x3bb3, 0x3bad, 0x3ba7,
+ 0x3ba2, 0x3b9c, 0x3b97, 0x3b91, 0x3b8c, 0x3b86, 0x3b80, 0x3b7b,
+ 0x3b75, 0x3b70, 0x3b6a, 0x3b65, 0x3b5f, 0x3b5a, 0x3b54, 0x3b4e,
+ 0x3b49, 0x3b43, 0x3b3e, 0x3b38, 0x3b33, 0x3b2d, 0x3b27, 0x3b22,
+ 0x3b1c, 0x3b17, 0x3b11, 0x3b0c, 0x3b06, 0x3b00, 0x3afb, 0x3af5,
+ 0x3af0, 0x3aea, 0x3ae4, 0x3adf, 0x3ad9, 0x3ad4, 0x3ace, 0x3ac9,
+ 0x3ac3, 0x3abd, 0x3ab8, 0x3ab2, 0x3aad, 0x3aa7, 0x3aa2, 0x3a9c,
+ 0x3a96, 0x3a91, 0x3a8b, 0x3a86, 0x3a80, 0x3a7a, 0x3a75, 0x3a6f,
+ 0x3a6a, 0x3a64, 0x3a5e, 0x3a59, 0x3a53, 0x3a4e, 0x3a48, 0x3a42,
+ 0x3a3d, 0x3a37, 0x3a32, 0x3a2c, 0x3a26, 0x3a21, 0x3a1b, 0x3a16,
+ 0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,
+ 0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,
+ 0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,
+ 0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,
+ 0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,
+ 0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,
+ 0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,
+ 0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,
+ 0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,
+ 0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,
+ 0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,
+ 0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,
+ 0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,
+ 0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,
+ 0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,
+ 0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,
+ 0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,
+ 0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,
+ 0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,
+ 0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,
+ 0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,
+ 0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,
+ 0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,
+ 0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,
+ 0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,
+ 0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,
+ 0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,
+ 0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,
+ 0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,
+ 0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,
+ 0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,
+ 0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,
+ 0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,
+ 0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,
+ 0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,
+ 0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,
+ 0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,
+ 0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,
+ 0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,
+ 0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,
+ 0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,
+ 0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,
+ 0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,
+ 0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,
+ 0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,
+ 0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,
+ 0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,
+ 0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,
+ 0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,
+ 0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,
+ 0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,
+ 0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,
+ 0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,
+ 0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,
+ 0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,
+ 0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,
+ 0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,
+ 0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,
+ 0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,
+ 0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,
+ 0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,
+ 0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,
+ 0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,
+ 0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,
+ 0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,
+ 0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,
+ 0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,
+ 0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,
+ 0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,
+ 0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,
+ 0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,
+ 0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,
+ 0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,
+ 0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,
+ 0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,
+ 0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,
+ 0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,
+ 0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,
+ 0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,
+ 0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,
+ 0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,
+ 0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,
+ 0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,
+ 0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,
+ 0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,
+ 0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,
+ 0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,
+ 0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,
+ 0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,
+ 0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,
+ 0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,
+ 0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,
+ 0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,
+ 0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,
+ 0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,
+ 0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,
+ 0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,
+ 0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,
+ 0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,
+ 0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,
+ 0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,
+ 0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,
+ 0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,
+ 0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,
+ 0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,
+ 0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,
+ 0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,
+ 0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,
+ 0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,
+ 0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,
+ 0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,
+ 0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,
+ 0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,
+ 0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,
+ 0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,
+ 0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,
+ 0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,
+ 0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,
+ 0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,
+ 0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,
+ 0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,
+ 0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,
+ 0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,
+ 0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,
+ 0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,
+ 0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,
+ 0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,
+ 0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,
+ 0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,
+ 0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,
+ 0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
+ 0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
+ 0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
+ 0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
+ 0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
+ 0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
+ 0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
+ 0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
+ 0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
+ 0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
+ 0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
+ 0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
+ 0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
+ 0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
+ 0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
+ 0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
+ 0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
+ 0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
+ 0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
+ 0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
+ 0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
+ 0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
+ 0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
+ 0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
+ 0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
+ 0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
+ 0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
+ 0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
+ 0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
+ 0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
+ 0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
+ 0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
+ 0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
+ 0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
+ 0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
+ 0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
+ 0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
+ 0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
+ 0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
+ 0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
+ 0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
+ 0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
+ 0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
+ 0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
+ 0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
+ 0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
+ 0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
+ 0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
+ 0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
+ 0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
+ 0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
+ 0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
+ 0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
+ 0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
+ 0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
+ 0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
+ 0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
+ 0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
+ 0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
+ 0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
+ 0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
+ 0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
+ 0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
+ 0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
+ 0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
+ 0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
+ 0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
+ 0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
+ 0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
+ 0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
+ 0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
+ 0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
+ 0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
+ 0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
+ 0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
+ 0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
+ 0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
+ 0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
+ 0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
+ 0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
+ 0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
+ 0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
+ 0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
+ 0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
+ 0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
+ 0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
+ 0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
+ 0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
+ 0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
+ 0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
+ 0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
+ 0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
+ 0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
+ 0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
+ 0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
+ 0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
+ 0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
+ 0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
+ 0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
+ 0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
+ 0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
+ 0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
+ 0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
+ 0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
+ 0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
+ 0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
+ 0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
+ 0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
+ 0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
+ 0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
+ 0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
+ 0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
+ 0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
+ 0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
+ 0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
+ 0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
+ 0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
+ 0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
+ 0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
+ 0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
+ 0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
+ 0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
+ 0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
+ 0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
+ 0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
+ 0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
+ 0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
+ 0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
+ 0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
+ 0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
+ 0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
+ 0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
+ 0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
+ 0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
+ 0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
+ 0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
+ 0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
+ 0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
+ 0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
+ 0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
+ 0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
+ 0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
+ 0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
+ 0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
+ 0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
+ 0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
+ 0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
+ 0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
+ 0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
+ 0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
+ 0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
+ 0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
+ 0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
+ 0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
+ 0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
+ 0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
+ 0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
+ 0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
+ 0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
+ 0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
+ 0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
+ 0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
+ 0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
+ 0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
+ 0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
+ 0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
+ 0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
+ 0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
+ 0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
+ 0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
+ 0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
+ 0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
+ 0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
+ 0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
+ 0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
+ 0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
+ 0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
+};
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ15Table.gif
+ */
+
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+ (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q15_t *pCosFactor[4] =
+ { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+ (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 000000000..673628db0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,8364 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q31.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q31
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+ 0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+ 0xfb49e6a3,
+ 0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+ 0x7f872bf3, 0xf50497fb,
+ 0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+ 0x7ed5e5c6, 0xeec60f31,
+ 0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+ 0x7dd6668f, 0xe8922622,
+ 0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+ 0x7c894bde, 0xe26cb01b,
+ 0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+ 0x7aef6323, 0xdc597781,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+ 0x7909a92d, 0xd65c3b7b,
+ 0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+ 0x76d94989, 0xd078ad9e,
+ 0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+ 0x745f9dd1, 0xcab26fa9,
+ 0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+ 0x719e2cd2, 0xc50d1149,
+ 0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+ 0x6e96a99d, 0xbf8c0de3,
+ 0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+ 0x6b4af279, 0xba32ca71,
+ 0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+ 0x67bd0fbd, 0xb5049368,
+ 0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+ 0x63ef3290, 0xb0049ab3,
+ 0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+ 0x5fe3b38d, 0xab35f5b5,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+ 0x5b9d1154, 0xa69b9b68,
+ 0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+ 0x571deefa, 0xa2386284,
+ 0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+ 0x5269126e, 0x9e0effc1,
+ 0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+ 0x4d8162c4, 0x9a22042d,
+ 0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+ 0x4869e665, 0x9673db94,
+ 0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+ 0x4325c135, 0x9306cb04,
+ 0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+ 0x3db832a6, 0x8fdcef66,
+ 0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+ 0x382493b0, 0x8cf83c30,
+ 0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+ 0x326e54c7, 0x8a5a7a31,
+ 0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+ 0x2c98fbba, 0x88054677,
+ 0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+ 0x26a82186, 0x85fa1153,
+ 0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+ 0x209f701c, 0x843a1d70,
+ 0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+ 0x1a82a026, 0x82c67f14,
+ 0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+ 0x145576b1, 0x81a01b6d,
+ 0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+ 0xe1bc2e4, 0x80c7a80a,
+ 0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+ 0x7d95b9e, 0x803daa6a,
+ 0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+ 0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+ 0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+ 0xfed2694f,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+ 0x7ff871a2, 0xfd40565c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+ 0x7fed5791, 0xfbae5e89,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+ 0x7fdd4eec, 0xfa1c9157,
+ 0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+ 0x7fc85854, 0xf88afe42,
+ 0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+ 0x7fae7495, 0xf6f9b4c6,
+ 0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+ 0x7f8fa4b0, 0xf568c45b,
+ 0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+ 0x7f6be9d4, 0xf3d83c77,
+ 0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+ 0x7f434563, 0xf2482c8a,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+ 0x7f15b8ee, 0xf0b8a401,
+ 0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+ 0x7ee34636, 0xef29b243,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+ 0x7eabef2c, 0xed9b66b2,
+ 0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+ 0x7e6fb5f4, 0xec0dd0a8,
+ 0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+ 0x7e2e9cdf, 0xea80ff7a,
+ 0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+ 0x7de8a670, 0xe8f50273,
+ 0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+ 0x7d9dd55a, 0xe769e8d8,
+ 0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+ 0x7d4e2c7f, 0xe5dfc1e5,
+ 0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+ 0x7cf9aef0, 0xe4569ccb,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+ 0x7ca05ff1, 0xe2ce88b3,
+ 0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+ 0x7c4242f2, 0xe14794ba,
+ 0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+ 0x7bdf5b94, 0xdfc1cff3,
+ 0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+ 0x7b77ada8, 0xde3d4964,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+ 0x7b0b3d2c, 0xdcba1008,
+ 0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+ 0x7a9a0e50, 0xdb3832cd,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+ 0x7a24256f, 0xd9b7c094,
+ 0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+ 0x79a98715, 0xd838c82d,
+ 0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+ 0x792a37fe, 0xd6bb585e,
+ 0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+ 0x78a63d11, 0xd53f7fda,
+ 0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+ 0x781d9b65, 0xd3c54d47,
+ 0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+ 0x7790583e, 0xd24ccf39,
+ 0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+ 0x76fe790e, 0xd0d61434,
+ 0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+ 0x76680376, 0xcf612aaa,
+ 0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+ 0x75ccfd42, 0xcdee20fc,
+ 0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+ 0x752d6c6c, 0xcc7d0578,
+ 0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+ 0x7489571c, 0xcb0de658,
+ 0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+ 0x73e0c3a3, 0xc9a0d1c5,
+ 0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+ 0x7333b883, 0xc835d5d0,
+ 0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+ 0x72823c67, 0xc6cd0079,
+ 0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+ 0x71cc5626, 0xc5665fa9,
+ 0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+ 0x71120cc5, 0xc4020133,
+ 0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+ 0x70536771, 0xc29ff2d4,
+ 0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+ 0x6f906d84, 0xc1404233,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+ 0x6ec92683, 0xbfe2fcdf,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+ 0x6dfd9a1c, 0xbe88304f,
+ 0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+ 0x6d2dd027, 0xbd2fe9e2,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+ 0x6c59d0a9, 0xbbda36dd,
+ 0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+ 0x6b81a3cd, 0xba87246d,
+ 0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+ 0x6aa551e9, 0xb936bfa4,
+ 0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+ 0x69c4e37a, 0xb7e9157a,
+ 0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+ 0x68e06129, 0xb69e32cd,
+ 0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+ 0x67f7d3c5, 0xb556245e,
+ 0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+ 0x670b4444, 0xb410f6d3,
+ 0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+ 0x661abbc5, 0xb2ceb6b5,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+ 0x6526438f, 0xb18f7071,
+ 0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+ 0x642de50d, 0xb0533055,
+ 0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+ 0x6331a9d4, 0xaf1a0293,
+ 0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+ 0x62319b9d, 0xade3f33e,
+ 0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+ 0x612dc447, 0xacb10e4b,
+ 0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+ 0x60262dd6, 0xab815f8d,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+ 0x5f1ae274, 0xaa54f2ba,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+ 0x5e0bec6e, 0xa92bd367,
+ 0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+ 0x5cf95638, 0xa8060d08,
+ 0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+ 0x5be32a67, 0xa6e3aaf2,
+ 0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+ 0x5ac973b5, 0xa5c4b855,
+ 0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+ 0x59ac3cfd, 0xa4a94043,
+ 0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+ 0x588b9140, 0xa3914da8,
+ 0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+ 0x57677b9d, 0xa27ceb4f,
+ 0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+ 0x56400758, 0xa16c23e1,
+ 0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+ 0x55153fd4, 0xa05f01e1,
+ 0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+ 0x53e73097, 0x9f558fb0,
+ 0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+ 0x52b5e546, 0x9e4fd78a,
+ 0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+ 0x518169a5, 0x9d4de385,
+ 0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+ 0x5049c999, 0x9c4fbd93,
+ 0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+ 0x4f0f1126, 0x9b556f81,
+ 0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+ 0x4dd14c6e, 0x9a5f02f5,
+ 0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+ 0x4c9087b1, 0x996c816f,
+ 0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+ 0x4b4ccf4d, 0x987df449,
+ 0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+ 0x4a062fbd, 0x979364b5,
+ 0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+ 0x48bcb599, 0x96acdbbe,
+ 0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+ 0x47706d93, 0x95ca6247,
+ 0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+ 0x4621647d, 0x94ec010b,
+ 0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+ 0x44cfa740, 0x9411c09e,
+ 0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+ 0x437b42e1, 0x933ba968,
+ 0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+ 0x42244481, 0x9269c3ac,
+ 0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+ 0x40cab958, 0x919c1781,
+ 0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+ 0x3f6eaeb8, 0x90d2acd4,
+ 0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+ 0x3e10320d, 0x900d8b69,
+ 0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+ 0x3caf50da, 0x8f4cbadb,
+ 0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+ 0x3b4c18ba, 0x8e904298,
+ 0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+ 0x39e6975e, 0x8dd829e4,
+ 0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+ 0x387eda8e, 0x8d2477d8,
+ 0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+ 0x3714f02a, 0x8c753362,
+ 0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+ 0x35a8e625, 0x8bca6343,
+ 0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+ 0x343aca87, 0x8b240e11,
+ 0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+ 0x32caab6f, 0x8a823a36,
+ 0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+ 0x3158970e, 0x89e4edef,
+ 0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+ 0x2fe49ba7, 0x894c2f4c,
+ 0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+ 0x2e6ec792, 0x88b80432,
+ 0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+ 0x2cf72939, 0x88287256,
+ 0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+ 0x2b7dcf17, 0x879d7f41,
+ 0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+ 0x2a02c7b8, 0x8717304e,
+ 0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+ 0x288621b9, 0x86958aac,
+ 0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+ 0x2707ebc7, 0x86189359,
+ 0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+ 0x2588349d, 0x85a04f28,
+ 0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+ 0x24070b08, 0x852cc2bb,
+ 0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+ 0x22847de0, 0x84bdf286,
+ 0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+ 0x21009c0c, 0x8453e2cf,
+ 0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+ 0x1f7b7481, 0x83ee97ad,
+ 0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+ 0x1df5163f, 0x838e1507,
+ 0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+ 0x1c6d9053, 0x83325e97,
+ 0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+ 0x1ae4f1d6, 0x82db77e5,
+ 0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+ 0x195b49ea, 0x8289644b,
+ 0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+ 0x17d0a7bc, 0x823c26f3,
+ 0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+ 0x16451a83, 0x81f3c2d7,
+ 0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+ 0x14b8b17f, 0x81b03ac2,
+ 0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+ 0x132b7bf9, 0x8171914e,
+ 0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+ 0x119d8941, 0x8137c8e6,
+ 0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+ 0x100ee8ad, 0x8102e3c4,
+ 0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+ 0xe7fa99e, 0x80d2e3f2,
+ 0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+ 0xcefdb76, 0x80a7cb49,
+ 0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+ 0xb5f8d9f, 0x80819b74,
+ 0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+ 0x9cecf89, 0x806055eb,
+ 0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+ 0x83db0a7, 0x8043fbf6,
+ 0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+ 0x6ac406f, 0x802c8ead,
+ 0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+ 0x51a8e5c, 0x801a0ef8,
+ 0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+ 0x388a9ea, 0x800c7d8c,
+ 0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+ 0x1f6a297, 0x8003daf1,
+ 0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+ 0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+ 0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+ 0xffb49a12,
+ 0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+ 0x7fff8719, 0xff501258,
+ 0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+ 0x7ffed572, 0xfeeb8b0a,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+ 0x7ffdd4d7, 0xfe870467,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+ 0x7ffc8549, 0xfe227eac,
+ 0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+ 0x7ffae6c7, 0xfdbdfa18,
+ 0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+ 0x7ff8f954, 0xfd5976e9,
+ 0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+ 0x7ff6bcf0, 0xfcf4f55c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+ 0x7ff4319d, 0xfc9075af,
+ 0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+ 0x7ff1575d, 0xfc2bf821,
+ 0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+ 0x7fee2e30, 0xfbc77cf0,
+ 0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+ 0x7feab61a, 0xfb630459,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+ 0x7fe6ef1c, 0xfafe8e9b,
+ 0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+ 0x7fe2d938, 0xfa9a1bf3,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+ 0x7fde7471, 0xfa35ac9f,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+ 0x7fd9c0ca, 0xf9d140de,
+ 0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+ 0x7fd4be46, 0xf96cd8ed,
+ 0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+ 0x7fcf6ce8, 0xf908750a,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+ 0x7fc9ccb2, 0xf8a41574,
+ 0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+ 0x7fc3dda9, 0xf83fba68,
+ 0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+ 0x7fbd9fd0, 0xf7db6423,
+ 0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+ 0x7fb7132b, 0xf77712e5,
+ 0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+ 0x7fb037bf, 0xf712c6ea,
+ 0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+ 0x7fa90d8e, 0xf6ae8071,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+ 0x7fa1949e, 0xf64a3fb8,
+ 0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+ 0x7f99ccf4, 0xf5e604fc,
+ 0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+ 0x7f91b694, 0xf581d07b,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+ 0x7f895182, 0xf51da273,
+ 0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+ 0x7f809dc5, 0xf4b97b21,
+ 0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+ 0x7f779b62, 0xf4555ac5,
+ 0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+ 0x7f6e4a5e, 0xf3f1419a,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+ 0x7f64aabf, 0xf38d2fe0,
+ 0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+ 0x7f5abc8a, 0xf32925d3,
+ 0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+ 0x7f507fc7, 0xf2c523b2,
+ 0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+ 0x7f45f47b, 0xf26129ba,
+ 0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+ 0x7f3b1aad, 0xf1fd3829,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+ 0x7f2ff263, 0xf1994f3d,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+ 0x7f247ba5, 0xf1356f32,
+ 0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+ 0x7f18b679, 0xf0d19848,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+ 0x7f0ca2e7, 0xf06dcaba,
+ 0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+ 0x7f0040f6, 0xf00a06c8,
+ 0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+ 0x7ef390ae, 0xefa64cae,
+ 0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+ 0x7ee69217, 0xef429caa,
+ 0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+ 0x7ed94538, 0xeedef6f9,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+ 0x7ecbaa1a, 0xee7b5bd9,
+ 0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+ 0x7ebdc0c6, 0xee17cb88,
+ 0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+ 0x7eaf8943, 0xedb44642,
+ 0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+ 0x7ea1039b, 0xed50cc46,
+ 0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+ 0x7e922fd6, 0xeced5dd0,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+ 0x7e830dff, 0xec89fb1e,
+ 0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+ 0x7e739e1d, 0xec26a46d,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+ 0x7e63e03b, 0xebc359fb,
+ 0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+ 0x7e53d462, 0xeb601c04,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+ 0x7e437a9c, 0xeafceac6,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+ 0x7e32d2f4, 0xea99c67e,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+ 0x7e21dd73, 0xea36af69,
+ 0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+ 0x7e109a24, 0xe9d3a5c5,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+ 0x7dff0911, 0xe970a9ce,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+ 0x7ded2a47, 0xe90dbbc2,
+ 0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+ 0x7ddafdce, 0xe8aadbde,
+ 0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+ 0x7dc883b4, 0xe8480a5d,
+ 0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+ 0x7db5bc02, 0xe7e5477f,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+ 0x7da2a6c6, 0xe782937e,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+ 0x7d8f4409, 0xe71fee99,
+ 0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+ 0x7d7b93da, 0xe6bd590d,
+ 0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+ 0x7d679642, 0xe65ad315,
+ 0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+ 0x7d534b50, 0xe5f85cef,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+ 0x7d3eb30f, 0xe595f6d7,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+ 0x7d29cd8c, 0xe533a10a,
+ 0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+ 0x7d149ad5, 0xe4d15bc6,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+ 0x7cff1af5, 0xe46f2745,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+ 0x7ce94dfb, 0xe40d03c6,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+ 0x7cd333f3, 0xe3aaf184,
+ 0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+ 0x7cbcccec, 0xe348f0bd,
+ 0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+ 0x7ca618f3, 0xe2e701ac,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+ 0x7c8f1817, 0xe285248d,
+ 0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+ 0x7c77ca65, 0xe223599e,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+ 0x7c602fec, 0xe1c1a11b,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+ 0x7c4848ba, 0xe15ffb3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+ 0x7c3014de, 0xe0fe6848,
+ 0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+ 0x7c179467, 0xe09ce871,
+ 0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+ 0x7bfec765, 0xe03b7bf6,
+ 0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+ 0x7be5ade6, 0xdfda2314,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+ 0x7bcc47fa, 0xdf78de07,
+ 0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+ 0x7bb295b0, 0xdf17ad0a,
+ 0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+ 0x7b989719, 0xdeb69059,
+ 0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+ 0x7b7e4c45, 0xde558831,
+ 0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+ 0x7b63b543, 0xddf494ce,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+ 0x7b48d225, 0xdd93b66a,
+ 0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+ 0x7b2da2fa, 0xdd32ed43,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+ 0x7b1227d3, 0xdcd23993,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+ 0x7af660c2, 0xdc719b96,
+ 0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+ 0x7ada4dd8, 0xdc111388,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+ 0x7abdef25, 0xdbb0a1a4,
+ 0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+ 0x7aa144bc, 0xdb504626,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+ 0x7a844eae, 0xdaf00149,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+ 0x7a670d0d, 0xda8fd349,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+ 0x7a497feb, 0xda2fbc61,
+ 0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+ 0x7a2ba75a, 0xd9cfbccd,
+ 0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+ 0x7a0d836d, 0xd96fd4c7,
+ 0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+ 0x79ef1436, 0xd910048a,
+ 0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+ 0x79d059c8, 0xd8b04c52,
+ 0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+ 0x79b15435, 0xd850ac5a,
+ 0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+ 0x79920392, 0xd7f124dd,
+ 0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+ 0x797267f2, 0xd791b616,
+ 0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+ 0x79528167, 0xd732603f,
+ 0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+ 0x79325006, 0xd6d32393,
+ 0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+ 0x7911d3e2, 0xd674004e,
+ 0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+ 0x78f10d0f, 0xd614f6a9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+ 0x78cffba3, 0xd5b606e0,
+ 0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+ 0x78ae9fb0, 0xd557312d,
+ 0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+ 0x788cf94c, 0xd4f875ca,
+ 0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+ 0x786b088c, 0xd499d4f2,
+ 0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+ 0x7848cd83, 0xd43b4ee0,
+ 0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+ 0x78264849, 0xd3dce3cd,
+ 0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+ 0x780378f1, 0xd37e93f4,
+ 0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+ 0x77e05f91, 0xd3205f8f,
+ 0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+ 0x77bcfc3f, 0xd2c246d8,
+ 0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+ 0x77994f11, 0xd2644a0a,
+ 0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+ 0x7775581d, 0xd206695d,
+ 0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+ 0x77511778, 0xd1a8a50d,
+ 0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+ 0x772c8d3a, 0xd14afd52,
+ 0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+ 0x7707b979, 0xd0ed7267,
+ 0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+ 0x76e29c4b, 0xd0900486,
+ 0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+ 0x76bd35c7, 0xd032b3e7,
+ 0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+ 0x76978605, 0xcfd580c6,
+ 0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+ 0x76718d1c, 0xcf786b5a,
+ 0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+ 0x764b4b23, 0xcf1b73de,
+ 0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+ 0x7624c031, 0xcebe9a8a,
+ 0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+ 0x75fdec60, 0xce61df99,
+ 0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+ 0x75d6cfc5, 0xce054343,
+ 0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+ 0x75af6a7b, 0xcda8c5c1,
+ 0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+ 0x7587bc98, 0xcd4c674d,
+ 0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+ 0x755fc635, 0xccf0281f,
+ 0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+ 0x7537876c, 0xcc940871,
+ 0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+ 0x750f0054, 0xcc38087b,
+ 0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+ 0x74e63108, 0xcbdc2876,
+ 0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+ 0x74bd199f, 0xcb80689a,
+ 0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+ 0x7493ba34, 0xcb24c921,
+ 0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+ 0x746a12df, 0xcac94a42,
+ 0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+ 0x744023bc, 0xca6dec37,
+ 0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+ 0x7415ece2, 0xca12af37,
+ 0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+ 0x73eb6e6e, 0xc9b7937a,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+ 0x73c0a878, 0xc95c993a,
+ 0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+ 0x73959b1b, 0xc901c0ae,
+ 0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+ 0x736a4671, 0xc8a70a0e,
+ 0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+ 0x733eaa96, 0xc84c7593,
+ 0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+ 0x7312c7a5, 0xc7f20373,
+ 0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+ 0x72e69db7, 0xc797b3e7,
+ 0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+ 0x72ba2cea, 0xc73d8727,
+ 0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+ 0x728d7557, 0xc6e37d69,
+ 0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+ 0x7260771b, 0xc68996e7,
+ 0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+ 0x72333251, 0xc62fd3d6,
+ 0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+ 0x7205a716, 0xc5d6346f,
+ 0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+ 0x71d7d585, 0xc57cb8e9,
+ 0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+ 0x71a9bdba, 0xc523617a,
+ 0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+ 0x717b5fd3, 0xc4ca2e5b,
+ 0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+ 0x714cbbeb, 0xc4711fc2,
+ 0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+ 0x711dd220, 0xc41835e6,
+ 0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+ 0x70eea28e, 0xc3bf70fd,
+ 0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+ 0x70bf2d53, 0xc366d140,
+ 0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+ 0x708f728b, 0xc30e56e4,
+ 0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+ 0x705f7255, 0xc2b6021f,
+ 0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+ 0x702f2ccd, 0xc25dd329,
+ 0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+ 0x6ffea212, 0xc205ca38,
+ 0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+ 0x6fcdd241, 0xc1ade781,
+ 0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+ 0x6f9cbd79, 0xc1562b3d,
+ 0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+ 0x6f6b63d8, 0xc0fe959f,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+ 0x6f39c57d, 0xc0a726df,
+ 0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+ 0x6f07e285, 0xc04fdf32,
+ 0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+ 0x6ed5bb10, 0xbff8bece,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+ 0x6ea34f3d, 0xbfa1c5ea,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+ 0x6e709f2a, 0xbf4af4ba,
+ 0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+ 0x6e3daaf8, 0xbef44b74,
+ 0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+ 0x6e0a72c5, 0xbe9dca4e,
+ 0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+ 0x6dd6f6b1, 0xbe47717c,
+ 0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+ 0x6da336dc, 0xbdf14135,
+ 0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+ 0x6d6f3365, 0xbd9b39ad,
+ 0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+ 0x6d3aec6e, 0xbd455b1a,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+ 0x6d066215, 0xbcefa5b0,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+ 0x6cd1947c, 0xbc9a19a5,
+ 0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+ 0x6c9c83c3, 0xbc44b72c,
+ 0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+ 0x6c67300b, 0xbbef7e7c,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+ 0x6c319975, 0xbb9a6fc7,
+ 0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+ 0x6bfbc021, 0xbb458b43,
+ 0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+ 0x6bc5a431, 0xbaf0d125,
+ 0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+ 0x6b8f45c7, 0xba9c41a0,
+ 0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+ 0x6b58a503, 0xba47dce8,
+ 0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+ 0x6b21c208, 0xb9f3a332,
+ 0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+ 0x6aea9cf8, 0xb99f94b2,
+ 0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+ 0x6ab335f4, 0xb94bb19b,
+ 0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+ 0x6a7b8d1e, 0xb8f7fa21,
+ 0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+ 0x6a43a29a, 0xb8a46e78,
+ 0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+ 0x6a0b7689, 0xb8510ed4,
+ 0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+ 0x69d3090e, 0xb7fddb67,
+ 0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+ 0x699a5a4c, 0xb7aad465,
+ 0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+ 0x69616a65, 0xb757fa01,
+ 0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+ 0x6928397e, 0xb7054c6f,
+ 0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+ 0x68eec7b9, 0xb6b2cbe2,
+ 0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+ 0x68b5153a, 0xb660788c,
+ 0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+ 0x687b2224, 0xb60e529f,
+ 0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+ 0x6840ee9b, 0xb5bc5a50,
+ 0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+ 0x68067ac3, 0xb56a8fd0,
+ 0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+ 0x67cbc6c0, 0xb518f351,
+ 0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+ 0x6790d2b6, 0xb4c78507,
+ 0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+ 0x67559eca, 0xb4764523,
+ 0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+ 0x671a2b20, 0xb42533d8,
+ 0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+ 0x66de77dc, 0xb3d45157,
+ 0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+ 0x66a28524, 0xb3839dd3,
+ 0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+ 0x6666531d, 0xb333197c,
+ 0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+ 0x6629e1ec, 0xb2e2c486,
+ 0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+ 0x65ed31b5, 0xb2929f21,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+ 0x65b0429f, 0xb242a97e,
+ 0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+ 0x657314cf, 0xb1f2e3d0,
+ 0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+ 0x6535a86b, 0xb1a34e47,
+ 0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+ 0x64f7fd98, 0xb153e915,
+ 0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+ 0x64ba147d, 0xb104b46a,
+ 0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+ 0x647bed3f, 0xb0b5b077,
+ 0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+ 0x643d8806, 0xb066dd6d,
+ 0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+ 0x63fee4f8, 0xb0183b7d,
+ 0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+ 0x63c0043b, 0xafc9cad7,
+ 0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+ 0x6380e5f6, 0xaf7b8bac,
+ 0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+ 0x63418a50, 0xaf2d7e2b,
+ 0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+ 0x6301f171, 0xaedfa285,
+ 0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+ 0x62c21b7e, 0xae91f8eb,
+ 0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+ 0x628208a1, 0xae44818b,
+ 0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+ 0x6241b8ff, 0xadf73c96,
+ 0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+ 0x62012cc2, 0xadaa2a3b,
+ 0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+ 0x61c06410, 0xad5d4aaa,
+ 0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+ 0x617f5f12, 0xad109e12,
+ 0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+ 0x613e1df0, 0xacc424a3,
+ 0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+ 0x60fca0d2, 0xac77de8b,
+ 0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+ 0x60bae7e1, 0xac2bcbfa,
+ 0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+ 0x6078f344, 0xabdfed1f,
+ 0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+ 0x6036c325, 0xab944229,
+ 0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+ 0x5ff457ad, 0xab48cb46,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+ 0x5fb1b104, 0xaafd88a4,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+ 0x5f6ecf53, 0xaab27a73,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+ 0x5f2bb2c5, 0xaa67a0e0,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+ 0x5ee85b82, 0xaa1cfc1a,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+ 0x5ea4c9b3, 0xa9d28c4e,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+ 0x5e60fd84, 0xa98851ac,
+ 0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+ 0x5e1cf71c, 0xa93e4c5f,
+ 0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+ 0x5dd8b6a7, 0xa8f47c97,
+ 0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+ 0x5d943c4e, 0xa8aae280,
+ 0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+ 0x5d4f883b, 0xa8617e48,
+ 0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+ 0x5d0a9a9a, 0xa818501c,
+ 0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+ 0x5cc57394, 0xa7cf582a,
+ 0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+ 0x5c801354, 0xa786969e,
+ 0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+ 0x5c3a7a05, 0xa73e0ba5,
+ 0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+ 0x5bf4a7d2, 0xa6f5b76d,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+ 0x5bae9ce7, 0xa6ad9a21,
+ 0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+ 0x5b68596d, 0xa665b3ee,
+ 0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+ 0x5b21dd90, 0xa61e0501,
+ 0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+ 0x5adb297d, 0xa5d68d85,
+ 0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+ 0x5a943d5e, 0xa58f4da8,
+ 0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+ 0x5a4d1960, 0xa5484594,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+ 0x5a05bdae, 0xa5017575,
+ 0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+ 0x59be2a74, 0xa4badd78,
+ 0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+ 0x59765fde, 0xa4747dc7,
+ 0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+ 0x592e5e19, 0xa42e568f,
+ 0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+ 0x58e62552, 0xa3e867fa,
+ 0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+ 0x589db5b3, 0xa3a2b234,
+ 0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+ 0x58550f6c, 0xa35d3567,
+ 0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+ 0x580c32a7, 0xa317f1bf,
+ 0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+ 0x57c31f92, 0xa2d2e766,
+ 0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+ 0x5779d65b, 0xa28e1687,
+ 0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+ 0x5730572e, 0xa2497f4c,
+ 0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+ 0x56e6a239, 0xa20521e0,
+ 0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+ 0x569cb7a8, 0xa1c0fe6c,
+ 0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+ 0x565297ab, 0xa17d151b,
+ 0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+ 0x5608426e, 0xa1396617,
+ 0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+ 0x55bdb81f, 0xa0f5f189,
+ 0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+ 0x5572f8ed, 0xa0b2b79b,
+ 0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+ 0x55280505, 0xa06fb876,
+ 0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+ 0x54dcdc96, 0xa02cf444,
+ 0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+ 0x54917fce, 0x9fea6b2f,
+ 0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+ 0x5445eedb, 0x9fa81d5e,
+ 0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+ 0x53fa29ed, 0x9f660afb,
+ 0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+ 0x53ae3131, 0x9f24342f,
+ 0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+ 0x536204d7, 0x9ee29922,
+ 0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+ 0x5315a50e, 0x9ea139fd,
+ 0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+ 0x52c91204, 0x9e6016e8,
+ 0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+ 0x527c4bea, 0x9e1f300b,
+ 0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+ 0x522f52ee, 0x9dde858e,
+ 0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+ 0x51e22740, 0x9d9e179a,
+ 0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+ 0x5194c910, 0x9d5de656,
+ 0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+ 0x5147388c, 0x9d1df1e9,
+ 0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+ 0x50f975e6, 0x9cde3a7b,
+ 0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+ 0x50ab814d, 0x9c9ec033,
+ 0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+ 0x505d5af1, 0x9c5f8339,
+ 0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+ 0x500f0302, 0x9c2083b3,
+ 0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+ 0x4fc079b1, 0x9be1c1c8,
+ 0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+ 0x4f71bf2e, 0x9ba33da0,
+ 0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+ 0x4f22d3aa, 0x9b64f760,
+ 0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+ 0x4ed3b755, 0x9b26ef2f,
+ 0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+ 0x4e846a60, 0x9ae92533,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+ 0x4e34ecfc, 0x9aab9993,
+ 0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+ 0x4de53f5a, 0x9a6e4c74,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+ 0x4d9561ac, 0x9a313dfc,
+ 0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+ 0x4d455422, 0x99f46e51,
+ 0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+ 0x4cf516ee, 0x99b7dd99,
+ 0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+ 0x4ca4aa41, 0x997b8bf8,
+ 0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+ 0x4c540e4e, 0x993f7993,
+ 0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+ 0x4c034345, 0x9903a691,
+ 0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+ 0x4bb24958, 0x98c81316,
+ 0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+ 0x4b6120bb, 0x988cbf46,
+ 0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+ 0x4b0fc99d, 0x9851ab46,
+ 0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+ 0x4abe4433, 0x9816d73b,
+ 0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+ 0x4a6c90ad, 0x97dc4349,
+ 0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+ 0x4a1aaf3f, 0x97a1ef94,
+ 0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+ 0x49c8a01b, 0x9767dc41,
+ 0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+ 0x49766373, 0x972e0971,
+ 0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+ 0x4923f97b, 0x96f4774b,
+ 0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+ 0x48d16265, 0x96bb25f0,
+ 0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+ 0x487e9e64, 0x96821585,
+ 0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+ 0x482badab, 0x9649462d,
+ 0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+ 0x47d8906d, 0x9610b80a,
+ 0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+ 0x478546de, 0x95d86b3f,
+ 0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+ 0x4731d131, 0x95a05ff0,
+ 0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+ 0x46de2f99, 0x9568963f,
+ 0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+ 0x468a624a, 0x95310e4e,
+ 0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+ 0x46366978, 0x94f9c83f,
+ 0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+ 0x45e24556, 0x94c2c435,
+ 0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+ 0x458df619, 0x948c0252,
+ 0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+ 0x45397bf4, 0x945582b7,
+ 0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+ 0x44e4d71c, 0x941f4585,
+ 0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+ 0x449007c4, 0x93e94adf,
+ 0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+ 0x443b0e21, 0x93b392e6,
+ 0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+ 0x43e5ea68, 0x937e1dbb,
+ 0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+ 0x43909ccd, 0x9348eb7e,
+ 0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+ 0x433b2585, 0x9313fc51,
+ 0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+ 0x42e584c3, 0x92df5054,
+ 0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+ 0x428fbabe, 0x92aae7a8,
+ 0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+ 0x4239c7aa, 0x9276c26d,
+ 0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+ 0x41e3abbc, 0x9242e0c4,
+ 0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+ 0x418d6729, 0x920f42cb,
+ 0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+ 0x4136fa27, 0x91dbe8a4,
+ 0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+ 0x40e064ea, 0x91a8d26d,
+ 0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+ 0x4089a7a8, 0x91760047,
+ 0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+ 0x4032c297, 0x91437250,
+ 0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+ 0x3fdbb5ec, 0x911128a8,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+ 0x3f8481dd, 0x90df236e,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+ 0x3f2d26a0, 0x90ad62c0,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+ 0x3ed5a46b, 0x907be6be,
+ 0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+ 0x3e7dfb73, 0x904aaf86,
+ 0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+ 0x3e262bee, 0x9019bd36,
+ 0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+ 0x3dce3614, 0x8fe90fec,
+ 0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+ 0x3d761a19, 0x8fb8a7c7,
+ 0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+ 0x3d1dd835, 0x8f8884e4,
+ 0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+ 0x3cc5709e, 0x8f58a761,
+ 0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+ 0x3c6ce38a, 0x8f290f5c,
+ 0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+ 0x3c143130, 0x8ef9bcf2,
+ 0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+ 0x3bbb59c7, 0x8ecab040,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+ 0x3b625d86, 0x8e9be963,
+ 0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+ 0x3b093ca3, 0x8e6d6877,
+ 0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+ 0x3aaff755, 0x8e3f2d9b,
+ 0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+ 0x3a568dd4, 0x8e1138ea,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+ 0x39fd0056, 0x8de38a80,
+ 0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+ 0x39a34f13, 0x8db6227a,
+ 0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+ 0x39497a43, 0x8d8900f3,
+ 0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+ 0x38ef821c, 0x8d5c2609,
+ 0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+ 0x389566d6, 0x8d2f91d5,
+ 0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+ 0x383b28a9, 0x8d034474,
+ 0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+ 0x37e0c7cc, 0x8cd73e01,
+ 0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+ 0x37864477, 0x8cab7e98,
+ 0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+ 0x372b9ee3, 0x8c800652,
+ 0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+ 0x36d0d746, 0x8c54d54c,
+ 0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+ 0x3675edd9, 0x8c29eb9f,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+ 0x361ae2d3, 0x8bff4966,
+ 0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+ 0x35bfb66e, 0x8bd4eebc,
+ 0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+ 0x356468e2, 0x8baadbba,
+ 0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+ 0x3508fa66, 0x8b81107b,
+ 0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+ 0x34ad6b32, 0x8b578d18,
+ 0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+ 0x3451bb81, 0x8b2e51ab,
+ 0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+ 0x33f5eb89, 0x8b055e4d,
+ 0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+ 0x3399fb85, 0x8adcb318,
+ 0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+ 0x333debab, 0x8ab45024,
+ 0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+ 0x32e1bc36, 0x8a8c358b,
+ 0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+ 0x32856d5e, 0x8a646365,
+ 0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+ 0x3228ff5c, 0x8a3cd9cc,
+ 0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+ 0x31cc7269, 0x8a1598d6,
+ 0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+ 0x316fc6be, 0x89eea09d,
+ 0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+ 0x3112fc95, 0x89c7f138,
+ 0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+ 0x30b61426, 0x89a18ac0,
+ 0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+ 0x30590dab, 0x897b6d4c,
+ 0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+ 0x2ffbe95d, 0x895598f3,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+ 0x2f9ea775, 0x89300dce,
+ 0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+ 0x2f41482e, 0x890acbf2,
+ 0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+ 0x2ee3cbc1, 0x88e5d378,
+ 0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+ 0x2e863267, 0x88c12475,
+ 0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+ 0x2e287c5a, 0x889cbf01,
+ 0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+ 0x2dcaa9d5, 0x8878a332,
+ 0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+ 0x2d6cbb10, 0x8854d11e,
+ 0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+ 0x2d0eb046, 0x883148db,
+ 0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+ 0x2cb089b1, 0x880e0a7f,
+ 0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+ 0x2c52478a, 0x87eb1621,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+ 0x2bf3ea0d, 0x87c86bd5,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+ 0x2b957173, 0x87a60bb1,
+ 0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+ 0x2b36ddf7, 0x8783f5ca,
+ 0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+ 0x2ad82fd2, 0x87622a35,
+ 0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+ 0x2a796740, 0x8740a907,
+ 0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+ 0x2a1a847b, 0x871f7255,
+ 0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+ 0x29bb87bc, 0x86fe8633,
+ 0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+ 0x295c7140, 0x86dde4b5,
+ 0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+ 0x28fd4140, 0x86bd8df0,
+ 0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+ 0x289df7f8, 0x869d81f8,
+ 0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+ 0x283e95a1, 0x867dc0e0,
+ 0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+ 0x27df1a77, 0x865e4abb,
+ 0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+ 0x277f86b5, 0x863f1f9e,
+ 0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+ 0x271fda96, 0x86203f9c,
+ 0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+ 0x26c01655, 0x8601aac7,
+ 0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+ 0x26603a2c, 0x85e36132,
+ 0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+ 0x26004657, 0x85c562f1,
+ 0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+ 0x25a03b11, 0x85a7b015,
+ 0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+ 0x25401896, 0x858a48b1,
+ 0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+ 0x24dfdf20, 0x856d2cd7,
+ 0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+ 0x247f8eec, 0x85505c99,
+ 0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+ 0x241f2833, 0x8533d809,
+ 0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+ 0x23beab33, 0x85179f39,
+ 0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+ 0x235e1826, 0x84fbb239,
+ 0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+ 0x22fd6f48, 0x84e0111b,
+ 0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+ 0x229cb0d5, 0x84c4bbf0,
+ 0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+ 0x223bdd08, 0x84a9b2ca,
+ 0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+ 0x21daf41d, 0x848ef5b7,
+ 0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+ 0x2179f64f, 0x847484ca,
+ 0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+ 0x2118e3dc, 0x845a6012,
+ 0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+ 0x20b7bcfe, 0x844087a0,
+ 0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+ 0x205681f1, 0x8426fb84,
+ 0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+ 0x1ff532f2, 0x840dbbcc,
+ 0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+ 0x1f93d03c, 0x83f4c889,
+ 0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+ 0x1f325a0b, 0x83dc21cb,
+ 0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+ 0x1ed0d09d, 0x83c3c7a0,
+ 0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+ 0x1e6f342c, 0x83abba17,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+ 0x1e0d84f5, 0x8393f940,
+ 0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+ 0x1dabc334, 0x837c8528,
+ 0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+ 0x1d49ef26, 0x83655ddf,
+ 0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+ 0x1ce80906, 0x834e8373,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+ 0x1c861113, 0x8337f5f1,
+ 0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+ 0x1c240786, 0x8321b568,
+ 0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+ 0x1bc1ec9e, 0x830bc1e6,
+ 0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+ 0x1b5fc097, 0x82f61b77,
+ 0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+ 0x1afd83ad, 0x82e0c22a,
+ 0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+ 0x1a9b361d, 0x82cbb60b,
+ 0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+ 0x1a38d823, 0x82b6f727,
+ 0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+ 0x19d669fc, 0x82a2858c,
+ 0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+ 0x1973ebe6, 0x828e6146,
+ 0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+ 0x19115e1c, 0x827a8a61,
+ 0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+ 0x18aec0db, 0x826700e9,
+ 0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+ 0x184c1461, 0x8253c4eb,
+ 0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+ 0x17e958ea, 0x8240d673,
+ 0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+ 0x17868eb3, 0x822e358b,
+ 0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+ 0x1723b5f9, 0x821be240,
+ 0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+ 0x16c0cef9, 0x8209dc9e,
+ 0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+ 0x165dd9f0, 0x81f824ae,
+ 0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+ 0x15fad71b, 0x81e6ba7c,
+ 0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+ 0x1597c6b7, 0x81d59e13,
+ 0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+ 0x1534a901, 0x81c4cf7d,
+ 0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+ 0x14d17e36, 0x81b44ec4,
+ 0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+ 0x146e4694, 0x81a41bf4,
+ 0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+ 0x140b0258, 0x81943715,
+ 0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+ 0x13a7b1bf, 0x8184a032,
+ 0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+ 0x13445505, 0x81755754,
+ 0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+ 0x12e0ec6a, 0x81665c84,
+ 0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+ 0x127d7829, 0x8157afcd,
+ 0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+ 0x1219f880, 0x81495136,
+ 0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+ 0x11b66dad, 0x813b40ca,
+ 0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+ 0x1152d7ed, 0x812d7e8f,
+ 0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+ 0x10ef377d, 0x81200a90,
+ 0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+ 0x108b8c9b, 0x8112e4d4,
+ 0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+ 0x1027d784, 0x81060d63,
+ 0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+ 0xfc41876, 0x80f98446,
+ 0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+ 0xf604faf, 0x80ed4984,
+ 0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+ 0xefc7d6b, 0x80e15d24,
+ 0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+ 0xe98a1e9, 0x80d5bf2e,
+ 0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+ 0xe34bd66, 0x80ca6fa9,
+ 0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+ 0xdd0d01f, 0x80bf6e9c,
+ 0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+ 0xd6cda53, 0x80b4bc0e,
+ 0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+ 0xd08dc3f, 0x80aa5806,
+ 0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+ 0xca4d620, 0x80a04289,
+ 0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+ 0xc40c835, 0x80967b9f,
+ 0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+ 0xbdcb2bb, 0x808d034c,
+ 0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+ 0xb7895f0, 0x8083d998,
+ 0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+ 0xb147211, 0x807afe87,
+ 0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+ 0xab0475c, 0x8072721f,
+ 0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+ 0xa4c1610, 0x806a3466,
+ 0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+ 0x9e7de6a, 0x80624560,
+ 0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+ 0x983a0a7, 0x805aa512,
+ 0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+ 0x91f5d06, 0x80535381,
+ 0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+ 0x8bb13c5, 0x804c50b2,
+ 0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+ 0x856c520, 0x80459ca9,
+ 0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+ 0x7f27157, 0x803f376a,
+ 0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+ 0x78e18a7, 0x803920f8,
+ 0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+ 0x729bb4e, 0x80335959,
+ 0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+ 0x6c5598a, 0x802de08e,
+ 0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+ 0x660f398, 0x8028b69c,
+ 0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+ 0x5fc89b8, 0x8023db86,
+ 0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+ 0x5981c26, 0x801f4f4f,
+ 0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+ 0x533ab20, 0x801b11fa,
+ 0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+ 0x4cf36e5, 0x80172388,
+ 0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+ 0x46abfb3, 0x801383fe,
+ 0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+ 0x40645c7, 0x8010335c,
+ 0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+ 0x3a1c960, 0x800d31a5,
+ 0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+ 0x33d4abb, 0x800a7edb,
+ 0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+ 0x2d8ca16, 0x80081b00,
+ 0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+ 0x27447b0, 0x80060614,
+ 0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+ 0x20fc3c6, 0x8004401a,
+ 0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+ 0x1ab3e97, 0x8002c912,
+ 0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+ 0x146b860, 0x8001a0fd,
+ 0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+ 0xe23160, 0x8000c7dc,
+ 0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+ 0x80003daf,
+ 0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+ 0x80000278,
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+ 0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
+ 0xffed2684,
+ 0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
+ 0x7ffff872, 0xffd40489,
+ 0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
+ 0x7fffed57, 0xffbae290,
+ 0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
+ 0x7fffdd4d, 0xffa1c09a,
+ 0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
+ 0x7fffc854, 0xff889ea7,
+ 0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
+ 0x7fffae6c, 0xff6f7cba,
+ 0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
+ 0x7fff8f94, 0xff565ad1,
+ 0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
+ 0x7fff6bcd, 0xff3d38ef,
+ 0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
+ 0x7fff4317, 0xff241715,
+ 0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
+ 0x7fff1572, 0xff0af543,
+ 0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
+ 0x7ffee2dd, 0xfef1d37b,
+ 0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
+ 0x7ffeab59, 0xfed8b1bd,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
+ 0x7ffe6ee5, 0xfebf900a,
+ 0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
+ 0x7ffe2d83, 0xfea66e64,
+ 0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
+ 0x7ffde731, 0xfe8d4ccb,
+ 0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
+ 0x7ffd9bf0, 0xfe742b41,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
+ 0x7ffd4bc0, 0xfe5b09c5,
+ 0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
+ 0x7ffcf6a0, 0xfe41e85a,
+ 0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
+ 0x7ffc9c92, 0xfe28c700,
+ 0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
+ 0x7ffc3d94, 0xfe0fa5b8,
+ 0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
+ 0x7ffbd9a7, 0xfdf68484,
+ 0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
+ 0x7ffb70cb, 0xfddd6363,
+ 0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
+ 0x7ffb0300, 0xfdc44258,
+ 0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
+ 0x7ffa9045, 0xfdab2162,
+ 0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
+ 0x7ffa189c, 0xfd920084,
+ 0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
+ 0x7ff99c03, 0xfd78dfbd,
+ 0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
+ 0x7ff91a7b, 0xfd5fbf10,
+ 0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
+ 0x7ff89405, 0xfd469e7c,
+ 0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
+ 0x7ff8089f, 0xfd2d7e04,
+ 0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
+ 0x7ff7784a, 0xfd145da7,
+ 0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
+ 0x7ff6e307, 0xfcfb3d67,
+ 0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
+ 0x7ff648d4, 0xfce21d45,
+ 0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
+ 0x7ff5a9b2, 0xfcc8fd41,
+ 0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
+ 0x7ff505a2, 0xfcafdd5e,
+ 0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
+ 0x7ff45ca3, 0xfc96bd9b,
+ 0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
+ 0x7ff3aeb4, 0xfc7d9df9,
+ 0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
+ 0x7ff2fbd7, 0xfc647e7b,
+ 0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
+ 0x7ff2440b, 0xfc4b5f20,
+ 0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
+ 0x7ff18751, 0xfc323fe9,
+ 0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
+ 0x7ff0c5a7, 0xfc1920d8,
+ 0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
+ 0x7fefff0f, 0xfc0001ee,
+ 0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
+ 0x7fef3388, 0xfbe6e32b,
+ 0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
+ 0x7fee6313, 0xfbcdc490,
+ 0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
+ 0x7fed8daf, 0xfbb4a61f,
+ 0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
+ 0x7fecb35c, 0xfb9b87d8,
+ 0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
+ 0x7febd41b, 0xfb8269bd,
+ 0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
+ 0x7feaefeb, 0xfb694bce,
+ 0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
+ 0x7fea06cd, 0xfb502e0c,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
+ 0x7fe918c0, 0xfb371078,
+ 0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
+ 0x7fe825c5, 0xfb1df314,
+ 0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
+ 0x7fe72ddb, 0xfb04d5e0,
+ 0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
+ 0x7fe63103, 0xfaebb8dd,
+ 0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
+ 0x7fe52f3d, 0xfad29c0c,
+ 0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
+ 0x7fe42889, 0xfab97f6e,
+ 0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
+ 0x7fe31ce6, 0xfaa06305,
+ 0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
+ 0x7fe20c55, 0xfa8746d0,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
+ 0x7fe0f6d6, 0xfa6e2ad1,
+ 0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
+ 0x7fdfdc69, 0xfa550f0a,
+ 0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
+ 0x7fdebd0d, 0xfa3bf37a,
+ 0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
+ 0x7fdd98c4, 0xfa22d823,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
+ 0x7fdc6f8d, 0xfa09bd06,
+ 0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
+ 0x7fdb4167, 0xf9f0a224,
+ 0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
+ 0x7fda0e54, 0xf9d7877e,
+ 0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
+ 0x7fd8d653, 0xf9be6d15,
+ 0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
+ 0x7fd79965, 0xf9a552e9,
+ 0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
+ 0x7fd65788, 0xf98c38fc,
+ 0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
+ 0x7fd510be, 0xf9731f4e,
+ 0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
+ 0x7fd3c506, 0xf95a05e2,
+ 0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
+ 0x7fd27460, 0xf940ecb7,
+ 0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
+ 0x7fd11ecd, 0xf927d3ce,
+ 0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
+ 0x7fcfc44d, 0xf90ebb29,
+ 0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
+ 0x7fce64df, 0xf8f5a2c9,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
+ 0x7fcd0083, 0xf8dc8aae,
+ 0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
+ 0x7fcb973b, 0xf8c372d9,
+ 0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
+ 0x7fca2905, 0xf8aa5b4c,
+ 0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
+ 0x7fc8b5e1, 0xf8914407,
+ 0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
+ 0x7fc73dd1, 0xf8782d0c,
+ 0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
+ 0x7fc5c0d3, 0xf85f165b,
+ 0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
+ 0x7fc43ee9, 0xf845fff5,
+ 0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
+ 0x7fc2b811, 0xf82ce9dc,
+ 0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
+ 0x7fc12c4d, 0xf813d410,
+ 0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
+ 0x7fbf9b9b, 0xf7fabe92,
+ 0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
+ 0x7fbe05fd, 0xf7e1a963,
+ 0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
+ 0x7fbc6b72, 0xf7c89484,
+ 0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
+ 0x7fbacbfa, 0xf7af7ff6,
+ 0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
+ 0x7fb92796, 0xf7966bbb,
+ 0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
+ 0x7fb77e45, 0xf77d57d2,
+ 0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
+ 0x7fb5d007, 0xf764443d,
+ 0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
+ 0x7fb41cdd, 0xf74b30fe,
+ 0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
+ 0x7fb264c7, 0xf7321e14,
+ 0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
+ 0x7fb0a7c4, 0xf7190b81,
+ 0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
+ 0x7faee5d5, 0xf6fff946,
+ 0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
+ 0x7fad1efa, 0xf6e6e764,
+ 0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
+ 0x7fab5333, 0xf6cdd5dc,
+ 0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
+ 0x7fa98280, 0xf6b4c4ae,
+ 0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
+ 0x7fa7ace1, 0xf69bb3dd,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
+ 0x7fa5d256, 0xf682a367,
+ 0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
+ 0x7fa3f2df, 0xf6699350,
+ 0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
+ 0x7fa20e7c, 0xf6508397,
+ 0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
+ 0x7fa0252e, 0xf637743e,
+ 0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
+ 0x7f9e36f4, 0xf61e6545,
+ 0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
+ 0x7f9c43ce, 0xf60556ae,
+ 0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
+ 0x7f9a4bbd, 0xf5ec4879,
+ 0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
+ 0x7f984ec1, 0xf5d33aa8,
+ 0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
+ 0x7f964cd9, 0xf5ba2d3b,
+ 0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
+ 0x7f944606, 0xf5a12034,
+ 0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
+ 0x7f923a48, 0xf5881393,
+ 0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
+ 0x7f90299f, 0xf56f0759,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
+ 0x7f8e140a, 0xf555fb88,
+ 0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
+ 0x7f8bf98b, 0xf53cf01f,
+ 0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
+ 0x7f89da21, 0xf523e521,
+ 0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
+ 0x7f87b5cd, 0xf50ada8f,
+ 0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
+ 0x7f858c8d, 0xf4f1d068,
+ 0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
+ 0x7f835e64, 0xf4d8c6ae,
+ 0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
+ 0x7f812b4f, 0xf4bfbd63,
+ 0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
+ 0x7f7ef350, 0xf4a6b486,
+ 0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
+ 0x7f7cb667, 0xf48dac1a,
+ 0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
+ 0x7f7a7494, 0xf474a41f,
+ 0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
+ 0x7f782dd6, 0xf45b9c95,
+ 0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
+ 0x7f75e22e, 0xf442957e,
+ 0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
+ 0x7f73919d, 0xf4298edc,
+ 0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
+ 0x7f713c21, 0xf41088ae,
+ 0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
+ 0x7f6ee1bc, 0xf3f782f6,
+ 0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
+ 0x7f6c826d, 0xf3de7db4,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
+ 0x7f6a1e34, 0xf3c578eb,
+ 0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
+ 0x7f67b512, 0xf3ac749a,
+ 0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
+ 0x7f654706, 0xf39370c2,
+ 0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
+ 0x7f62d411, 0xf37a6d66,
+ 0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
+ 0x7f605c33, 0xf3616a85,
+ 0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
+ 0x7f5ddf6b, 0xf3486820,
+ 0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
+ 0x7f5b5dbb, 0xf32f6639,
+ 0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
+ 0x7f58d721, 0xf31664d1,
+ 0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
+ 0x7f564b9f, 0xf2fd63e8,
+ 0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
+ 0x7f53bb34, 0xf2e4637f,
+ 0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
+ 0x7f5125e0, 0xf2cb6398,
+ 0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
+ 0x7f4e8ba4, 0xf2b26433,
+ 0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
+ 0x7f4bec7f, 0xf2996551,
+ 0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
+ 0x7f494872, 0xf28066f4,
+ 0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
+ 0x7f469f7d, 0xf267691b,
+ 0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
+ 0x7f43f19f, 0xf24e6bc9,
+ 0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
+ 0x7f413ed9, 0xf2356efe,
+ 0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
+ 0x7f3e872c, 0xf21c72bc,
+ 0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
+ 0x7f3bca96, 0xf2037702,
+ 0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
+ 0x7f390919, 0xf1ea7bd2,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
+ 0x7f3642b4, 0xf1d1812e,
+ 0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
+ 0x7f337768, 0xf1b88715,
+ 0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
+ 0x7f30a734, 0xf19f8d89,
+ 0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
+ 0x7f2dd219, 0xf186948c,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
+ 0x7f2af817, 0xf16d9c1d,
+ 0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
+ 0x7f28192d, 0xf154a43d,
+ 0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
+ 0x7f25355d, 0xf13bacef,
+ 0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
+ 0x7f224ca6, 0xf122b632,
+ 0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
+ 0x7f1f5f08, 0xf109c009,
+ 0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
+ 0x7f1c6c83, 0xf0f0ca72,
+ 0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
+ 0x7f197518, 0xf0d7d571,
+ 0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
+ 0x7f1678c6, 0xf0bee105,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
+ 0x7f13778e, 0xf0a5ed2f,
+ 0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
+ 0x7f107170, 0xf08cf9f1,
+ 0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
+ 0x7f0d666c, 0xf074074c,
+ 0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
+ 0x7f0a5682, 0xf05b1540,
+ 0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
+ 0x7f0741b2, 0xf04223ce,
+ 0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
+ 0x7f0427fc, 0xf02932f8,
+ 0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
+ 0x7f010961, 0xf01042be,
+ 0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
+ 0x7efde5e0, 0xeff75321,
+ 0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
+ 0x7efabd7a, 0xefde6423,
+ 0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
+ 0x7ef7902f, 0xefc575c3,
+ 0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
+ 0x7ef45dfe, 0xefac8804,
+ 0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
+ 0x7ef126e9, 0xef939ae6,
+ 0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
+ 0x7eedeaee, 0xef7aae6b,
+ 0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
+ 0x7eeaaa0f, 0xef61c292,
+ 0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
+ 0x7ee7644c, 0xef48d75d,
+ 0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
+ 0x7ee419a3, 0xef2feccd,
+ 0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
+ 0x7ee0ca17, 0xef1702e4,
+ 0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
+ 0x7edd75a6, 0xeefe19a1,
+ 0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
+ 0x7eda1c51, 0xeee53105,
+ 0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
+ 0x7ed6be18, 0xeecc4913,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
+ 0x7ed35afb, 0xeeb361cb,
+ 0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
+ 0x7ecff2fb, 0xee9a7b2d,
+ 0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
+ 0x7ecc8617, 0xee81953b,
+ 0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
+ 0x7ec9144f, 0xee68aff6,
+ 0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
+ 0x7ec59da5, 0xee4fcb5e,
+ 0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
+ 0x7ec22217, 0xee36e775,
+ 0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
+ 0x7ebea1a6, 0xee1e043b,
+ 0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
+ 0x7ebb1c52, 0xee0521b2,
+ 0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
+ 0x7eb7921b, 0xedec3fda,
+ 0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
+ 0x7eb40301, 0xedd35eb5,
+ 0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
+ 0x7eb06f05, 0xedba7e43,
+ 0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
+ 0x7eacd627, 0xeda19e85,
+ 0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
+ 0x7ea93867, 0xed88bf7d,
+ 0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
+ 0x7ea595c4, 0xed6fe12b,
+ 0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
+ 0x7ea1ee3f, 0xed570390,
+ 0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
+ 0x7e9e41d9, 0xed3e26ad,
+ 0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
+ 0x7e9a9091, 0xed254a84,
+ 0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
+ 0x7e96da67, 0xed0c6f14,
+ 0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
+ 0x7e931f5c, 0xecf39460,
+ 0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
+ 0x7e8f5f70, 0xecdaba67,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
+ 0x7e8b9aa3, 0xecc1e12c,
+ 0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
+ 0x7e87d0f5, 0xeca908ae,
+ 0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
+ 0x7e840265, 0xec9030f0,
+ 0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
+ 0x7e802ef6, 0xec7759f1,
+ 0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
+ 0x7e7c56a5, 0xec5e83b3,
+ 0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
+ 0x7e787975, 0xec45ae36,
+ 0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
+ 0x7e749764, 0xec2cd97d,
+ 0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
+ 0x7e70b073, 0xec140587,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
+ 0x7e6cc4a2, 0xebfb3256,
+ 0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
+ 0x7e68d3f2, 0xebe25fea,
+ 0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
+ 0x7e64de62, 0xebc98e45,
+ 0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
+ 0x7e60e3f2, 0xebb0bd67,
+ 0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
+ 0x7e5ce4a3, 0xeb97ed52,
+ 0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
+ 0x7e58e075, 0xeb7f1e06,
+ 0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
+ 0x7e54d768, 0xeb664f84,
+ 0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
+ 0x7e50c97c, 0xeb4d81ce,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
+ 0x7e4cb6b1, 0xeb34b4e4,
+ 0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
+ 0x7e489f08, 0xeb1be8c8,
+ 0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
+ 0x7e448281, 0xeb031d79,
+ 0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
+ 0x7e40611b, 0xeaea52fa,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
+ 0x7e3c3ad7, 0xead1894b,
+ 0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
+ 0x7e380fb5, 0xeab8c06c,
+ 0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
+ 0x7e33dfb6, 0xea9ff860,
+ 0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
+ 0x7e2faad9, 0xea873127,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
+ 0x7e2b711f, 0xea6e6ac2,
+ 0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
+ 0x7e273287, 0xea55a531,
+ 0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
+ 0x7e22ef12, 0xea3ce077,
+ 0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
+ 0x7e1ea6c1, 0xea241c93,
+ 0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
+ 0x7e1a5992, 0xea0b5987,
+ 0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
+ 0x7e160787, 0xe9f29753,
+ 0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
+ 0x7e11b0a0, 0xe9d9d5fa,
+ 0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
+ 0x7e0d54dc, 0xe9c1157a,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
+ 0x7e08f43d, 0xe9a855d7,
+ 0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
+ 0x7e048ec1, 0xe98f9710,
+ 0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
+ 0x7e00246a, 0xe976d926,
+ 0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
+ 0x7dfbb537, 0xe95e1c1b,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
+ 0x7df74128, 0xe9455fef,
+ 0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
+ 0x7df2c83f, 0xe92ca4a4,
+ 0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
+ 0x7dee4a7a, 0xe913ea39,
+ 0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
+ 0x7de9c7da, 0xe8fb30b1,
+ 0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
+ 0x7de54060, 0xe8e2780d,
+ 0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
+ 0x7de0b40b, 0xe8c9c04c,
+ 0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
+ 0x7ddc22dc, 0xe8b10971,
+ 0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
+ 0x7dd78cd3, 0xe898537b,
+ 0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
+ 0x7dd2f1f0, 0xe87f9e6c,
+ 0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
+ 0x7dce5232, 0xe866ea46,
+ 0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
+ 0x7dc9ad9c, 0xe84e3708,
+ 0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
+ 0x7dc5042b, 0xe83584b4,
+ 0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
+ 0x7dc055e2, 0xe81cd34b,
+ 0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
+ 0x7dbba2bf, 0xe80422ce,
+ 0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
+ 0x7db6eac3, 0xe7eb733e,
+ 0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
+ 0x7db22def, 0xe7d2c49b,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
+ 0x7dad6c42, 0xe7ba16e7,
+ 0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
+ 0x7da8a5bc, 0xe7a16a22,
+ 0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
+ 0x7da3da5f, 0xe788be4e,
+ 0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
+ 0x7d9f0a29, 0xe770136b,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
+ 0x7d9a351c, 0xe757697b,
+ 0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
+ 0x7d955b37, 0xe73ec07e,
+ 0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
+ 0x7d907c7a, 0xe7261875,
+ 0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
+ 0x7d8b98e6, 0xe70d7162,
+ 0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
+ 0x7d86b07c, 0xe6f4cb45,
+ 0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
+ 0x7d81c33a, 0xe6dc261f,
+ 0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
+ 0x7d7cd121, 0xe6c381f1,
+ 0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
+ 0x7d77da32, 0xe6aadebc,
+ 0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
+ 0x7d72de6d, 0xe6923c82,
+ 0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
+ 0x7d6dddd2, 0xe6799b42,
+ 0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
+ 0x7d68d860, 0xe660fafe,
+ 0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
+ 0x7d63ce19, 0xe6485bb7,
+ 0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
+ 0x7d5ebefc, 0xe62fbd6e,
+ 0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
+ 0x7d59ab0a, 0xe6172024,
+ 0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
+ 0x7d549243, 0xe5fe83d9,
+ 0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
+ 0x7d4f74a7, 0xe5e5e88f,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
+ 0x7d4a5236, 0xe5cd4e47,
+ 0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
+ 0x7d452af1, 0xe5b4b501,
+ 0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
+ 0x7d3ffed7, 0xe59c1cbf,
+ 0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
+ 0x7d3acde9, 0xe5838581,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
+ 0x7d359827, 0xe56aef49,
+ 0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
+ 0x7d305d91, 0xe5525a17,
+ 0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
+ 0x7d2b1e28, 0xe539c5ec,
+ 0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
+ 0x7d25d9eb, 0xe52132c9,
+ 0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
+ 0x7d2090db, 0xe508a0b0,
+ 0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
+ 0x7d1b42f9, 0xe4f00fa1,
+ 0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
+ 0x7d15f043, 0xe4d77f9d,
+ 0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
+ 0x7d1098bb, 0xe4bef0a5,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
+ 0x7d0b3c60, 0xe4a662ba,
+ 0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
+ 0x7d05db34, 0xe48dd5dd,
+ 0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
+ 0x7d007535, 0xe4754a0e,
+ 0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
+ 0x7cfb0a65, 0xe45cbf50,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
+ 0x7cf59ac4, 0xe44435a2,
+ 0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
+ 0x7cf02651, 0xe42bad07,
+ 0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
+ 0x7ceaad0c, 0xe413257d,
+ 0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
+ 0x7ce52ef7, 0xe3fa9f08,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
+ 0x7cdfac12, 0xe3e219a7,
+ 0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
+ 0x7cda245c, 0xe3c9955b,
+ 0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
+ 0x7cd497d5, 0xe3b11226,
+ 0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
+ 0x7ccf067f, 0xe3989008,
+ 0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
+ 0x7cc97059, 0xe3800f03,
+ 0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
+ 0x7cc3d563, 0xe3678f17,
+ 0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
+ 0x7cbe359e, 0xe34f1045,
+ 0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
+ 0x7cb8910a, 0xe336928e,
+ 0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
+ 0x7cb2e7a6, 0xe31e15f4,
+ 0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
+ 0x7cad3974, 0xe3059a76,
+ 0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
+ 0x7ca78674, 0xe2ed2017,
+ 0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
+ 0x7ca1cea5, 0xe2d4a6d6,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
+ 0x7c9c1208, 0xe2bc2eb5,
+ 0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
+ 0x7c96509d, 0xe2a3b7b5,
+ 0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
+ 0x7c908a65, 0xe28b41d7,
+ 0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
+ 0x7c8abf5f, 0xe272cd1c,
+ 0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
+ 0x7c84ef8c, 0xe25a5984,
+ 0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
+ 0x7c7f1aed, 0xe241e711,
+ 0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
+ 0x7c794180, 0xe22975c4,
+ 0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
+ 0x7c736347, 0xe211059d,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
+ 0x7c6d8041, 0xe1f8969d,
+ 0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
+ 0x7c679870, 0xe1e028c6,
+ 0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
+ 0x7c61abd3, 0xe1c7bc18,
+ 0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
+ 0x7c5bba6a, 0xe1af5094,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
+ 0x7c55c436, 0xe196e63c,
+ 0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
+ 0x7c4fc936, 0xe17e7d0f,
+ 0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
+ 0x7c49c96c, 0xe1661510,
+ 0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
+ 0x7c43c4d7, 0xe14dae3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
+ 0x7c3dbb78, 0xe135489d,
+ 0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
+ 0x7c37ad4e, 0xe11ce42a,
+ 0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
+ 0x7c319a5a, 0xe10480e9,
+ 0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
+ 0x7c2b829d, 0xe0ec1ed9,
+ 0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
+ 0x7c256616, 0xe0d3bdfc,
+ 0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
+ 0x7c1f44c6, 0xe0bb5e53,
+ 0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
+ 0x7c191ead, 0xe0a2ffde,
+ 0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
+ 0x7c12f3cb, 0xe08aa29f,
+ 0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
+ 0x7c0cc421, 0xe0724696,
+ 0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
+ 0x7c068fae, 0xe059ebc5,
+ 0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
+ 0x7c005673, 0xe041922c,
+ 0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
+ 0x7bfa1870, 0xe02939cc,
+ 0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
+ 0x7bf3d5a6, 0xe010e2a7,
+ 0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
+ 0x7bed8e14, 0xdff88cbc,
+ 0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
+ 0x7be741bb, 0xdfe0380e,
+ 0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
+ 0x7be0f09b, 0xdfc7e49d,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
+ 0x7bda9ab5, 0xdfaf926a,
+ 0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
+ 0x7bd44008, 0xdf974176,
+ 0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
+ 0x7bcde095, 0xdf7ef1c2,
+ 0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
+ 0x7bc77c5d, 0xdf66a34e,
+ 0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
+ 0x7bc1135e, 0xdf4e561c,
+ 0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
+ 0x7bbaa59a, 0xdf360a2d,
+ 0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
+ 0x7bb43311, 0xdf1dbf82,
+ 0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
+ 0x7badbbc3, 0xdf05761b,
+ 0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
+ 0x7ba73fb1, 0xdeed2dfa,
+ 0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
+ 0x7ba0beda, 0xded4e71f,
+ 0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
+ 0x7b9a393f, 0xdebca18b,
+ 0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
+ 0x7b93aee0, 0xdea45d40,
+ 0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
+ 0x7b8d1fbd, 0xde8c1a3e,
+ 0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
+ 0x7b868bd7, 0xde73d886,
+ 0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
+ 0x7b7ff32e, 0xde5b9819,
+ 0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
+ 0x7b7955c2, 0xde4358f8,
+ 0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
+ 0x7b72b393, 0xde2b1b24,
+ 0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
+ 0x7b6c0ca2, 0xde12de9e,
+ 0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
+ 0x7b6560ee, 0xddfaa367,
+ 0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
+ 0x7b5eb079, 0xdde26980,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
+ 0x7b57fb42, 0xddca30e9,
+ 0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
+ 0x7b51414a, 0xddb1f9a4,
+ 0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
+ 0x7b4a8291, 0xdd99c3b2,
+ 0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
+ 0x7b43bf17, 0xdd818f13,
+ 0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
+ 0x7b3cf6dc, 0xdd695bc9,
+ 0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
+ 0x7b3629e1, 0xdd5129d4,
+ 0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
+ 0x7b2f5826, 0xdd38f935,
+ 0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
+ 0x7b2881ac, 0xdd20c9ed,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
+ 0x7b21a671, 0xdd089bfe,
+ 0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
+ 0x7b1ac678, 0xdcf06f68,
+ 0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
+ 0x7b13e1bf, 0xdcd8442b,
+ 0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
+ 0x7b0cf848, 0xdcc01a4a,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
+ 0x7b060a12, 0xdca7f1c5,
+ 0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
+ 0x7aff171e, 0xdc8fca9c,
+ 0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
+ 0x7af81f6c, 0xdc77a4d2,
+ 0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
+ 0x7af122fd, 0xdc5f8066,
+ 0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
+ 0x7aea21d0, 0xdc475d59,
+ 0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
+ 0x7ae31be6, 0xdc2f3bad,
+ 0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
+ 0x7adc113f, 0xdc171b63,
+ 0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
+ 0x7ad501dc, 0xdbfefc7b,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
+ 0x7acdedbc, 0xdbe6def6,
+ 0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
+ 0x7ac6d4e0, 0xdbcec2d6,
+ 0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
+ 0x7abfb749, 0xdbb6a81b,
+ 0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
+ 0x7ab894f6, 0xdb9e8ec6,
+ 0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
+ 0x7ab16de7, 0xdb8676d8,
+ 0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
+ 0x7aaa421e, 0xdb6e6052,
+ 0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
+ 0x7aa3119a, 0xdb564b35,
+ 0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
+ 0x7a9bdc5c, 0xdb3e3781,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
+ 0x7a94a264, 0xdb262539,
+ 0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
+ 0x7a8d63b2, 0xdb0e145c,
+ 0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
+ 0x7a862046, 0xdaf604ec,
+ 0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
+ 0x7a7ed821, 0xdaddf6ea,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
+ 0x7a778b43, 0xdac5ea56,
+ 0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
+ 0x7a7039ad, 0xdaaddf31,
+ 0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
+ 0x7a68e35e, 0xda95d57d,
+ 0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
+ 0x7a618857, 0xda7dcd3a,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
+ 0x7a5a2898, 0xda65c669,
+ 0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
+ 0x7a52c421, 0xda4dc10b,
+ 0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
+ 0x7a4b5af3, 0xda35bd22,
+ 0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
+ 0x7a43ed0e, 0xda1dbaad,
+ 0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
+ 0x7a3c7a73, 0xda05b9ae,
+ 0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
+ 0x7a350321, 0xd9edba26,
+ 0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
+ 0x7a2d8719, 0xd9d5bc16,
+ 0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
+ 0x7a26065b, 0xd9bdbf7e,
+ 0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
+ 0x7a1e80e7, 0xd9a5c461,
+ 0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
+ 0x7a16f6be, 0xd98dcabd,
+ 0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
+ 0x7a0f67e0, 0xd975d295,
+ 0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
+ 0x7a07d44e, 0xd95ddbea,
+ 0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
+ 0x7a003c07, 0xd945e6bb,
+ 0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
+ 0x79f89f0c, 0xd92df30b,
+ 0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
+ 0x79f0fd5d, 0xd91600da,
+ 0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
+ 0x79e956fb, 0xd8fe1029,
+ 0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
+ 0x79e1abe6, 0xd8e620fa,
+ 0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
+ 0x79d9fc1d, 0xd8ce334c,
+ 0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
+ 0x79d247a2, 0xd8b64720,
+ 0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
+ 0x79ca8e75, 0xd89e5c79,
+ 0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
+ 0x79c2d095, 0xd8867356,
+ 0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
+ 0x79bb0e04, 0xd86e8bb9,
+ 0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
+ 0x79b346c2, 0xd856a5a3,
+ 0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
+ 0x79ab7ace, 0xd83ec114,
+ 0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
+ 0x79a3aa29, 0xd826de0d,
+ 0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
+ 0x799bd4d4, 0xd80efc8f,
+ 0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
+ 0x7993facf, 0xd7f71c9c,
+ 0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
+ 0x798c1c1a, 0xd7df3e34,
+ 0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
+ 0x798438b5, 0xd7c76158,
+ 0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
+ 0x797c50a1, 0xd7af8609,
+ 0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
+ 0x797463de, 0xd797ac48,
+ 0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
+ 0x796c726c, 0xd77fd415,
+ 0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
+ 0x79647c4c, 0xd767fd72,
+ 0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
+ 0x795c817d, 0xd7502860,
+ 0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
+ 0x79548201, 0xd73854e0,
+ 0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
+ 0x794c7dd7, 0xd72082f2,
+ 0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
+ 0x79447500, 0xd708b297,
+ 0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
+ 0x793c677d, 0xd6f0e3d1,
+ 0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
+ 0x7934554d, 0xd6d916a0,
+ 0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
+ 0x792c3e70, 0xd6c14b05,
+ 0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
+ 0x792422e8, 0xd6a98101,
+ 0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
+ 0x791c02b4, 0xd691b895,
+ 0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
+ 0x7913ddd4, 0xd679f1c2,
+ 0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
+ 0x790bb44a, 0xd6622c89,
+ 0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
+ 0x79038615, 0xd64a68eb,
+ 0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
+ 0x78fb5336, 0xd632a6e8,
+ 0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
+ 0x78f31bac, 0xd61ae682,
+ 0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
+ 0x78eadf79, 0xd60327b9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
+ 0x78e29e9d, 0xd5eb6a8f,
+ 0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
+ 0x78da5917, 0xd5d3af04,
+ 0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
+ 0x78d20ee9, 0xd5bbf519,
+ 0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
+ 0x78c9c012, 0xd5a43cd0,
+ 0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
+ 0x78c16c93, 0xd58c8628,
+ 0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
+ 0x78b9146c, 0xd574d124,
+ 0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
+ 0x78b0b79e, 0xd55d1dc3,
+ 0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
+ 0x78a85628, 0xd5456c07,
+ 0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
+ 0x789ff00c, 0xd52dbbf1,
+ 0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
+ 0x78978549, 0xd5160d82,
+ 0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
+ 0x788f15e0, 0xd4fe60ba,
+ 0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
+ 0x7886a1d1, 0xd4e6b59a,
+ 0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
+ 0x787e291d, 0xd4cf0c24,
+ 0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
+ 0x7875abc3, 0xd4b76458,
+ 0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
+ 0x786d29c5, 0xd49fbe37,
+ 0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
+ 0x7864a322, 0xd48819c3,
+ 0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
+ 0x785c17db, 0xd47076fb,
+ 0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
+ 0x785387ef, 0xd458d5e2,
+ 0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
+ 0x784af361, 0xd4413677,
+ 0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
+ 0x78425a2f, 0xd42998bc,
+ 0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
+ 0x7839bc5a, 0xd411fcb2,
+ 0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
+ 0x783119e2, 0xd3fa6259,
+ 0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
+ 0x782872c8, 0xd3e2c9b2,
+ 0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
+ 0x781fc70d, 0xd3cb32c0,
+ 0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
+ 0x781716b0, 0xd3b39d81,
+ 0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
+ 0x780e61b1, 0xd39c09f7,
+ 0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
+ 0x7805a812, 0xd3847824,
+ 0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
+ 0x77fce9d2, 0xd36ce808,
+ 0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
+ 0x77f426f2, 0xd35559a4,
+ 0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
+ 0x77eb5f71, 0xd33dccf8,
+ 0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
+ 0x77e29352, 0xd3264206,
+ 0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
+ 0x77d9c293, 0xd30eb8cf,
+ 0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
+ 0x77d0ed35, 0xd2f73154,
+ 0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
+ 0x77c81339, 0xd2dfab95,
+ 0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
+ 0x77bf349f, 0xd2c82793,
+ 0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
+ 0x77b65166, 0xd2b0a54f,
+ 0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
+ 0x77ad6990, 0xd29924cb,
+ 0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
+ 0x77a47d1d, 0xd281a607,
+ 0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
+ 0x779b8c0e, 0xd26a2904,
+ 0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
+ 0x77929661, 0xd252adc3,
+ 0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
+ 0x77899c19, 0xd23b3444,
+ 0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
+ 0x77809d35, 0xd223bc8a,
+ 0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
+ 0x777799b5, 0xd20c4694,
+ 0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
+ 0x776e919a, 0xd1f4d263,
+ 0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
+ 0x776584e5, 0xd1dd5ff9,
+ 0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
+ 0x775c7395, 0xd1c5ef56,
+ 0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
+ 0x77535dab, 0xd1ae807c,
+ 0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
+ 0x774a4327, 0xd197136b,
+ 0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
+ 0x7741240a, 0xd17fa823,
+ 0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
+ 0x77380054, 0xd1683ea7,
+ 0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
+ 0x772ed805, 0xd150d6f6,
+ 0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
+ 0x7725ab1f, 0xd1397113,
+ 0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
+ 0x771c79a0, 0xd1220cfc,
+ 0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
+ 0x77134389, 0xd10aaab5,
+ 0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
+ 0x770a08dc, 0xd0f34a3d,
+ 0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
+ 0x7700c997, 0xd0dbeb95,
+ 0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
+ 0x76f785bc, 0xd0c48ebf,
+ 0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
+ 0x76ee3d4b, 0xd0ad33ba,
+ 0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
+ 0x76e4f044, 0xd095da89,
+ 0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
+ 0x76db9ea7, 0xd07e832c,
+ 0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
+ 0x76d24876, 0xd0672da3,
+ 0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
+ 0x76c8edb0, 0xd04fd9f1,
+ 0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
+ 0x76bf8e55, 0xd0388815,
+ 0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
+ 0x76b62a66, 0xd0213810,
+ 0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
+ 0x76acc1e4, 0xd009e9e4,
+ 0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
+ 0x76a354cf, 0xcff29d92,
+ 0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
+ 0x7699e326, 0xcfdb531a,
+ 0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
+ 0x76906ceb, 0xcfc40a7c,
+ 0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
+ 0x7686f21e, 0xcfacc3bb,
+ 0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
+ 0x767d72bf, 0xcf957ed7,
+ 0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
+ 0x7673eecf, 0xcf7e3bd1,
+ 0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
+ 0x766a664d, 0xcf66faa9,
+ 0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
+ 0x7660d93b, 0xcf4fbb61,
+ 0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
+ 0x76574798, 0xcf387dfa,
+ 0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
+ 0x764db166, 0xcf214274,
+ 0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
+ 0x764416a4, 0xcf0a08d0,
+ 0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
+ 0x763a7752, 0xcef2d110,
+ 0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
+ 0x7630d372, 0xcedb9b33,
+ 0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
+ 0x76272b03, 0xcec4673c,
+ 0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
+ 0x761d7e06, 0xcead352b,
+ 0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
+ 0x7613cc7c, 0xce960500,
+ 0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
+ 0x760a1664, 0xce7ed6bd,
+ 0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
+ 0x76005bbf, 0xce67aa63,
+ 0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
+ 0x75f69c8d, 0xce507ff2,
+ 0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
+ 0x75ecd8cf, 0xce39576c,
+ 0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
+ 0x75e31086, 0xce2230d0,
+ 0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
+ 0x75d943b0, 0xce0b0c21,
+ 0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
+ 0x75cf7250, 0xcdf3e95f,
+ 0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
+ 0x75c59c65, 0xcddcc88b,
+ 0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
+ 0x75bbc1ef, 0xcdc5a9a6,
+ 0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
+ 0x75b1e2f0, 0xcdae8cb1,
+ 0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
+ 0x75a7ff67, 0xcd9771ac,
+ 0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
+ 0x759e1755, 0xcd805899,
+ 0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
+ 0x75942ab9, 0xcd694178,
+ 0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
+ 0x758a3996, 0xcd522c4a,
+ 0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
+ 0x758043ea, 0xcd3b1911,
+ 0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
+ 0x757649b7, 0xcd2407cc,
+ 0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
+ 0x756c4afc, 0xcd0cf87e,
+ 0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
+ 0x756247bb, 0xccf5eb26,
+ 0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
+ 0x75583ff3, 0xccdedfc7,
+ 0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
+ 0x754e33a4, 0xccc7d65f,
+ 0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
+ 0x754422d0, 0xccb0cef2,
+ 0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
+ 0x753a0d77, 0xcc99c97e,
+ 0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
+ 0x752ff399, 0xcc82c607,
+ 0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
+ 0x7525d536, 0xcc6bc48b,
+ 0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
+ 0x751bb24f, 0xcc54c50c,
+ 0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
+ 0x75118ae4, 0xcc3dc78b,
+ 0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
+ 0x75075ef5, 0xcc26cc09,
+ 0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
+ 0x74fd2e84, 0xcc0fd287,
+ 0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
+ 0x74f2f990, 0xcbf8db05,
+ 0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
+ 0x74e8c01a, 0xcbe1e585,
+ 0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
+ 0x74de8221, 0xcbcaf208,
+ 0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
+ 0x74d43fa8, 0xcbb4008d,
+ 0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
+ 0x74c9f8ad, 0xcb9d1117,
+ 0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
+ 0x74bfad32, 0xcb8623a5,
+ 0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
+ 0x74b55d36, 0xcb6f383a,
+ 0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
+ 0x74ab08bb, 0xcb584ed6,
+ 0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
+ 0x74a0afc0, 0xcb416779,
+ 0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
+ 0x74965246, 0xcb2a8224,
+ 0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
+ 0x748bf04d, 0xcb139ed9,
+ 0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
+ 0x748189d7, 0xcafcbd99,
+ 0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
+ 0x74771ee2, 0xcae5de64,
+ 0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
+ 0x746caf70, 0xcacf013a,
+ 0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
+ 0x74623b80, 0xcab8261e,
+ 0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
+ 0x7457c314, 0xcaa14d10,
+ 0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
+ 0x744d462c, 0xca8a7610,
+ 0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
+ 0x7442c4c8, 0xca73a120,
+ 0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
+ 0x74383ee9, 0xca5cce40,
+ 0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
+ 0x742db48e, 0xca45fd72,
+ 0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
+ 0x742325b9, 0xca2f2eb6,
+ 0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
+ 0x74189269, 0xca18620e,
+ 0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
+ 0x740dfaa0, 0xca019779,
+ 0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
+ 0x74035e5d, 0xc9eacef9,
+ 0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
+ 0x73f8bda2, 0xc9d4088f,
+ 0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
+ 0x73ee186e, 0xc9bd443c,
+ 0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
+ 0x73e36ec1, 0xc9a68200,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
+ 0x73d8c09d, 0xc98fc1dc,
+ 0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
+ 0x73ce0e01, 0xc97903d2,
+ 0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
+ 0x73c356ef, 0xc96247e2,
+ 0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
+ 0x73b89b66, 0xc94b8e0d,
+ 0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
+ 0x73addb67, 0xc934d654,
+ 0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
+ 0x73a316f2, 0xc91e20b8,
+ 0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
+ 0x73984e07, 0xc9076d39,
+ 0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
+ 0x738d80a8, 0xc8f0bbd9,
+ 0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
+ 0x7382aed5, 0xc8da0c99,
+ 0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
+ 0x7377d88d, 0xc8c35f78,
+ 0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
+ 0x736cfdd2, 0xc8acb479,
+ 0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
+ 0x73621ea4, 0xc8960b9c,
+ 0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
+ 0x73573b03, 0xc87f64e2,
+ 0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
+ 0x734c52ef, 0xc868c04b,
+ 0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
+ 0x7341666a, 0xc8521dd9,
+ 0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
+ 0x73367572, 0xc83b7d8d,
+ 0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
+ 0x732b800a, 0xc824df67,
+ 0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
+ 0x73208632, 0xc80e4369,
+ 0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
+ 0x731587e8, 0xc7f7a992,
+ 0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
+ 0x730a8530, 0xc7e111e5,
+ 0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
+ 0x72ff7e07, 0xc7ca7c61,
+ 0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
+ 0x72f47270, 0xc7b3e909,
+ 0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
+ 0x72e9626a, 0xc79d57db,
+ 0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
+ 0x72de4df6, 0xc786c8db,
+ 0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
+ 0x72d33514, 0xc7703c08,
+ 0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
+ 0x72c817c6, 0xc759b163,
+ 0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
+ 0x72bcf60a, 0xc74328ed,
+ 0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
+ 0x72b1cfe1, 0xc72ca2a7,
+ 0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
+ 0x72a6a54d, 0xc7161e92,
+ 0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
+ 0x729b764d, 0xc6ff9cae,
+ 0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
+ 0x729042e3, 0xc6e91cfd,
+ 0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
+ 0x72850b0d, 0xc6d29f80,
+ 0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
+ 0x7279cecd, 0xc6bc2437,
+ 0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
+ 0x726e8e23, 0xc6a5ab23,
+ 0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
+ 0x72634910, 0xc68f3446,
+ 0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
+ 0x7257ff94, 0xc678bf9f,
+ 0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
+ 0x724cb1b0, 0xc6624d30,
+ 0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
+ 0x72415f63, 0xc64bdcf9,
+ 0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
+ 0x723608af, 0xc6356efc,
+ 0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
+ 0x722aad93, 0xc61f033a,
+ 0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
+ 0x721f4e11, 0xc60899b2,
+ 0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
+ 0x7213ea28, 0xc5f23267,
+ 0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
+ 0x720881d9, 0xc5dbcd59,
+ 0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
+ 0x71fd1525, 0xc5c56a89,
+ 0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
+ 0x71f1a40c, 0xc5af09f7,
+ 0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
+ 0x71e62e8f, 0xc598aba5,
+ 0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
+ 0x71dab4ad, 0xc5824f93,
+ 0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
+ 0x71cf3667, 0xc56bf5c2,
+ 0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
+ 0x71c3b3bf, 0xc5559e34,
+ 0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
+ 0x71b82cb3, 0xc53f48e9,
+ 0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
+ 0x71aca145, 0xc528f5e1,
+ 0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
+ 0x71a11175, 0xc512a51f,
+ 0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
+ 0x71957d44, 0xc4fc56a2,
+ 0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
+ 0x7189e4b2, 0xc4e60a6b,
+ 0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
+ 0x717e47bf, 0xc4cfc07c,
+ 0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
+ 0x7172a66c, 0xc4b978d4,
+ 0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
+ 0x716700b9, 0xc4a33376,
+ 0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
+ 0x715b56a7, 0xc48cf062,
+ 0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
+ 0x714fa836, 0xc476af98,
+ 0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
+ 0x7143f567, 0xc460711b,
+ 0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
+ 0x71383e3a, 0xc44a34e9,
+ 0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
+ 0x712c82b0, 0xc433fb05,
+ 0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
+ 0x7120c2c8, 0xc41dc36f,
+ 0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
+ 0x7114fe84, 0xc4078e28,
+ 0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
+ 0x710935e4, 0xc3f15b31,
+ 0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
+ 0x70fd68e9, 0xc3db2a8b,
+ 0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
+ 0x70f19792, 0xc3c4fc36,
+ 0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
+ 0x70e5c1e1, 0xc3aed034,
+ 0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
+ 0x70d9e7d5, 0xc398a685,
+ 0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
+ 0x70ce096f, 0xc3827f2a,
+ 0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
+ 0x70c226b0, 0xc36c5a24,
+ 0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
+ 0x70b63f99, 0xc3563774,
+ 0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
+ 0x70aa5428, 0xc340171b,
+ 0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
+ 0x709e6460, 0xc329f919,
+ 0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
+ 0x70927041, 0xc313dd70,
+ 0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
+ 0x708677ca, 0xc2fdc420,
+ 0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
+ 0x707a7afd, 0xc2e7ad2a,
+ 0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
+ 0x706e79d9, 0xc2d1988f,
+ 0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
+ 0x70627460, 0xc2bb8650,
+ 0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
+ 0x70566a92, 0xc2a5766e,
+ 0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
+ 0x704a5c6f, 0xc28f68e9,
+ 0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
+ 0x703e49f8, 0xc2795dc3,
+ 0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
+ 0x7032332d, 0xc26354fc,
+ 0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
+ 0x7026180e, 0xc24d4e95,
+ 0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
+ 0x7019f89d, 0xc2374a8f,
+ 0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
+ 0x700dd4da, 0xc22148ea,
+ 0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
+ 0x7001acc4, 0xc20b49a9,
+ 0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
+ 0x6ff5805d, 0xc1f54cca,
+ 0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
+ 0x6fe94fa5, 0xc1df5251,
+ 0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
+ 0x6fdd1a9c, 0xc1c95a3c,
+ 0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
+ 0x6fd0e144, 0xc1b3648d,
+ 0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
+ 0x6fc4a39c, 0xc19d7145,
+ 0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
+ 0x6fb861a4, 0xc1878065,
+ 0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
+ 0x6fac1b5f, 0xc17191ee,
+ 0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
+ 0x6f9fd0cb, 0xc15ba5df,
+ 0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
+ 0x6f9381e9, 0xc145bc3c,
+ 0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
+ 0x6f872eba, 0xc12fd503,
+ 0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
+ 0x6f7ad73e, 0xc119f036,
+ 0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
+ 0x6f6e7b76, 0xc1040dd6,
+ 0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
+ 0x6f621b62, 0xc0ee2de3,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
+ 0x6f55b703, 0xc0d8505f,
+ 0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
+ 0x6f494e5a, 0xc0c2754b,
+ 0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
+ 0x6f3ce165, 0xc0ac9ca6,
+ 0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
+ 0x6f307027, 0xc096c673,
+ 0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
+ 0x6f23faa0, 0xc080f2b1,
+ 0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
+ 0x6f1780cf, 0xc06b2162,
+ 0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
+ 0x6f0b02b6, 0xc0555287,
+ 0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
+ 0x6efe8056, 0xc03f8620,
+ 0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
+ 0x6ef1f9ad, 0xc029bc2e,
+ 0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
+ 0x6ee56ebe, 0xc013f4b2,
+ 0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
+ 0x6ed8df88, 0xbffe2fad,
+ 0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
+ 0x6ecc4c0d, 0xbfe86d20,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
+ 0x6ebfb44b, 0xbfd2ad0b,
+ 0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
+ 0x6eb31845, 0xbfbcef70,
+ 0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
+ 0x6ea677fa, 0xbfa7344f,
+ 0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
+ 0x6e99d36b, 0xbf917ba9,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
+ 0x6e8d2a99, 0xbf7bc57f,
+ 0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
+ 0x6e807d83, 0xbf6611d2,
+ 0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
+ 0x6e73cc2b, 0xbf5060a2,
+ 0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
+ 0x6e671690, 0xbf3ab1f1,
+ 0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
+ 0x6e5a5cb4, 0xbf2505bf,
+ 0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
+ 0x6e4d9e97, 0xbf0f5c0d,
+ 0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
+ 0x6e40dc39, 0xbef9b4dc,
+ 0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
+ 0x6e34159b, 0xbee4102d,
+ 0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
+ 0x6e274abe, 0xbece6e00,
+ 0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
+ 0x6e1a7ba1, 0xbeb8ce57,
+ 0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
+ 0x6e0da845, 0xbea33132,
+ 0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
+ 0x6e00d0ac, 0xbe8d9692,
+ 0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
+ 0x6df3f4d4, 0xbe77fe78,
+ 0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
+ 0x6de714c0, 0xbe6268e5,
+ 0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
+ 0x6dda306f, 0xbe4cd5da,
+ 0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
+ 0x6dcd47e1, 0xbe374557,
+ 0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
+ 0x6dc05b18, 0xbe21b75d,
+ 0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
+ 0x6db36a14, 0xbe0c2bed,
+ 0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
+ 0x6da674d5, 0xbdf6a309,
+ 0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
+ 0x6d997b5b, 0xbde11cb0,
+ 0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
+ 0x6d8c7da8, 0xbdcb98e3,
+ 0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
+ 0x6d7f7bbc, 0xbdb617a4,
+ 0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
+ 0x6d727597, 0xbda098f3,
+ 0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
+ 0x6d656b3a, 0xbd8b1cd2,
+ 0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
+ 0x6d585ca6, 0xbd75a340,
+ 0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
+ 0x6d4b49da, 0xbd602c3f,
+ 0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
+ 0x6d3e32d7, 0xbd4ab7cf,
+ 0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
+ 0x6d31179e, 0xbd3545f2,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
+ 0x6d23f830, 0xbd1fd6a8,
+ 0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
+ 0x6d16d48c, 0xbd0a69f2,
+ 0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
+ 0x6d09acb4, 0xbcf4ffd1,
+ 0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
+ 0x6cfc80a7, 0xbcdf9846,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
+ 0x6cef5067, 0xbcca3351,
+ 0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
+ 0x6ce21bf4, 0xbcb4d0f4,
+ 0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
+ 0x6cd4e34e, 0xbc9f712e,
+ 0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
+ 0x6cc7a676, 0xbc8a1402,
+ 0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
+ 0x6cba656c, 0xbc74b96f,
+ 0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
+ 0x6cad2031, 0xbc5f6177,
+ 0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
+ 0x6c9fd6c6, 0xbc4a0c1b,
+ 0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
+ 0x6c92892a, 0xbc34b95b,
+ 0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
+ 0x6c85375f, 0xbc1f6938,
+ 0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
+ 0x6c77e165, 0xbc0a1bb3,
+ 0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
+ 0x6c6a873d, 0xbbf4d0cc,
+ 0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
+ 0x6c5d28e6, 0xbbdf8885,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
+ 0x6c4fc662, 0xbbca42df,
+ 0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
+ 0x6c425fb1, 0xbbb4ffda,
+ 0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
+ 0x6c34f4d3, 0xbb9fbf77,
+ 0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
+ 0x6c2785ca, 0xbb8a81b6,
+ 0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
+ 0x6c1a1295, 0xbb754699,
+ 0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
+ 0x6c0c9b35, 0xbb600e21,
+ 0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
+ 0x6bff1faa, 0xbb4ad84e,
+ 0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
+ 0x6bf19ff6, 0xbb35a521,
+ 0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
+ 0x6be41c18, 0xbb20749c,
+ 0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
+ 0x6bd69412, 0xbb0b46bd,
+ 0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
+ 0x6bc907e3, 0xbaf61b88,
+ 0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
+ 0x6bbb778d, 0xbae0f2fc,
+ 0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
+ 0x6bade30f, 0xbacbcd1a,
+ 0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
+ 0x6ba04a6a, 0xbab6a9e3,
+ 0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
+ 0x6b92ada0, 0xbaa18958,
+ 0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
+ 0x6b850caf, 0xba8c6b79,
+ 0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
+ 0x6b776799, 0xba775048,
+ 0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
+ 0x6b69be5f, 0xba6237c5,
+ 0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
+ 0x6b5c1101, 0xba4d21f2,
+ 0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
+ 0x6b4e5f7f, 0xba380ece,
+ 0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
+ 0x6b40a9d9, 0xba22fe5b,
+ 0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
+ 0x6b32f012, 0xba0df099,
+ 0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
+ 0x6b253228, 0xb9f8e58a,
+ 0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
+ 0x6b17701d, 0xb9e3dd2e,
+ 0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
+ 0x6b09a9f1, 0xb9ced786,
+ 0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
+ 0x6afbdfa4, 0xb9b9d493,
+ 0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
+ 0x6aee1138, 0xb9a4d455,
+ 0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
+ 0x6ae03eac, 0xb98fd6cd,
+ 0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
+ 0x6ad26802, 0xb97adbfd,
+ 0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
+ 0x6ac48d39, 0xb965e3e5,
+ 0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
+ 0x6ab6ae52, 0xb950ee86,
+ 0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
+ 0x6aa8cb4e, 0xb93bfbe0,
+ 0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
+ 0x6a9ae42e, 0xb9270bf5,
+ 0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
+ 0x6a8cf8f1, 0xb9121ec5,
+ 0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
+ 0x6a7f0999, 0xb8fd3451,
+ 0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
+ 0x6a711625, 0xb8e84c99,
+ 0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
+ 0x6a631e97, 0xb8d367a0,
+ 0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
+ 0x6a5522ef, 0xb8be8565,
+ 0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
+ 0x6a47232e, 0xb8a9a5e9,
+ 0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
+ 0x6a391f54, 0xb894c92d,
+ 0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
+ 0x6a2b1761, 0xb87fef33,
+ 0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
+ 0x6a1d0b57, 0xb86b17f9,
+ 0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
+ 0x6a0efb35, 0xb8564383,
+ 0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
+ 0x6a00e6fc, 0xb84171cf,
+ 0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
+ 0x69f2cead, 0xb82ca2e0,
+ 0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
+ 0x69e4b249, 0xb817d6b6,
+ 0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
+ 0x69d691cf, 0xb8030d51,
+ 0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
+ 0x69c86d41, 0xb7ee46b3,
+ 0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
+ 0x69ba449f, 0xb7d982dc,
+ 0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
+ 0x69ac17e9, 0xb7c4c1cd,
+ 0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
+ 0x699de721, 0xb7b00387,
+ 0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
+ 0x698fb246, 0xb79b480b,
+ 0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
+ 0x69817959, 0xb7868f59,
+ 0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
+ 0x69733c5b, 0xb771d972,
+ 0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
+ 0x6964fb4c, 0xb75d2658,
+ 0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
+ 0x6956b62d, 0xb748760b,
+ 0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
+ 0x69486cfe, 0xb733c88b,
+ 0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
+ 0x693a1fc0, 0xb71f1dd9,
+ 0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
+ 0x692bce73, 0xb70a75f7,
+ 0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
+ 0x691d7919, 0xb6f5d0e5,
+ 0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
+ 0x690f1fb1, 0xb6e12ea4,
+ 0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
+ 0x6900c23c, 0xb6cc8f35,
+ 0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
+ 0x68f260bb, 0xb6b7f298,
+ 0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
+ 0x68e3fb2e, 0xb6a358ce,
+ 0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
+ 0x68d59196, 0xb68ec1d9,
+ 0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
+ 0x68c723f3, 0xb67a2db8,
+ 0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
+ 0x68b8b247, 0xb6659c6d,
+ 0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
+ 0x68aa3c90, 0xb6510df8,
+ 0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
+ 0x689bc2d1, 0xb63c825b,
+ 0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
+ 0x688d4509, 0xb627f995,
+ 0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
+ 0x687ec339, 0xb61373a9,
+ 0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
+ 0x68703d62, 0xb5fef095,
+ 0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
+ 0x6861b384, 0xb5ea705d,
+ 0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
+ 0x685325a0, 0xb5d5f2ff,
+ 0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
+ 0x684493b6, 0xb5c1787e,
+ 0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
+ 0x6835fdc7, 0xb5ad00d9,
+ 0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
+ 0x682763d4, 0xb5988c12,
+ 0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
+ 0x6818c5dd, 0xb5841a29,
+ 0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
+ 0x680a23e2, 0xb56fab1f,
+ 0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
+ 0x67fb7de5, 0xb55b3ef5,
+ 0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
+ 0x67ecd3e5, 0xb546d5ac,
+ 0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
+ 0x67de25e3, 0xb5326f45,
+ 0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
+ 0x67cf73e1, 0xb51e0bbf,
+ 0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
+ 0x67c0bddd, 0xb509ab1d,
+ 0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
+ 0x67b203da, 0xb4f54d5f,
+ 0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
+ 0x67a345d8, 0xb4e0f285,
+ 0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
+ 0x679483d6, 0xb4cc9a90,
+ 0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
+ 0x6785bdd6, 0xb4b84582,
+ 0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
+ 0x6776f3d9, 0xb4a3f35b,
+ 0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
+ 0x676825de, 0xb48fa41c,
+ 0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
+ 0x675953e7, 0xb47b57c5,
+ 0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
+ 0x674a7df4, 0xb4670e57,
+ 0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
+ 0x673ba405, 0xb452c7d4,
+ 0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
+ 0x672cc61c, 0xb43e843b,
+ 0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
+ 0x671de438, 0xb42a438e,
+ 0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
+ 0x670efe5a, 0xb41605ce,
+ 0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
+ 0x67001483, 0xb401cafb,
+ 0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
+ 0x66f126b4, 0xb3ed9316,
+ 0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
+ 0x66e234ed, 0xb3d95e1f,
+ 0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
+ 0x66d33f2e, 0xb3c52c19,
+ 0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
+ 0x66c44579, 0xb3b0fd02,
+ 0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
+ 0x66b547cd, 0xb39cd0dd,
+ 0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
+ 0x66a6462b, 0xb388a7aa,
+ 0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
+ 0x66974095, 0xb3748169,
+ 0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
+ 0x66883709, 0xb3605e1c,
+ 0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
+ 0x6679298a, 0xb34c3dc3,
+ 0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
+ 0x666a1818, 0xb338205f,
+ 0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
+ 0x665b02b3, 0xb32405f1,
+ 0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
+ 0x664be95b, 0xb30fee79,
+ 0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
+ 0x663ccc12, 0xb2fbd9f9,
+ 0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
+ 0x662daad8, 0xb2e7c871,
+ 0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
+ 0x661e85ad, 0xb2d3b9e2,
+ 0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
+ 0x660f5c93, 0xb2bfae4c,
+ 0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
+ 0x66002f89, 0xb2aba5b1,
+ 0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
+ 0x65f0fe91, 0xb297a011,
+ 0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
+ 0x65e1c9aa, 0xb2839d6d,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
+ 0x65d290d6, 0xb26f9dc6,
+ 0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
+ 0x65c35415, 0xb25ba11d,
+ 0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
+ 0x65b41367, 0xb247a771,
+ 0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
+ 0x65a4cece, 0xb233b0c5,
+ 0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
+ 0x6595864a, 0xb21fbd19,
+ 0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
+ 0x658639db, 0xb20bcc6d,
+ 0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
+ 0x6576e982, 0xb1f7dec2,
+ 0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
+ 0x6567953f, 0xb1e3f41a,
+ 0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
+ 0x65583d14, 0xb1d00c75,
+ 0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
+ 0x6548e101, 0xb1bc27d3,
+ 0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
+ 0x65398105, 0xb1a84636,
+ 0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
+ 0x652a1d23, 0xb194679e,
+ 0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
+ 0x651ab55b, 0xb1808c0c,
+ 0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
+ 0x650b49ac, 0xb16cb380,
+ 0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
+ 0x64fbda18, 0xb158ddfd,
+ 0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
+ 0x64ec66a0, 0xb1450b81,
+ 0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
+ 0x64dcef44, 0xb1313c0e,
+ 0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
+ 0x64cd7404, 0xb11d6fa6,
+ 0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
+ 0x64bdf4e1, 0xb109a648,
+ 0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
+ 0x64ae71dc, 0xb0f5dff5,
+ 0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
+ 0x649eeaf5, 0xb0e21cae,
+ 0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
+ 0x648f602d, 0xb0ce5c74,
+ 0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
+ 0x647fd185, 0xb0ba9f48,
+ 0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
+ 0x64703efc, 0xb0a6e52a,
+ 0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
+ 0x6460a895, 0xb0932e1b,
+ 0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
+ 0x64510e4e, 0xb07f7a1c,
+ 0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
+ 0x6441702a, 0xb06bc92e,
+ 0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
+ 0x6431ce28, 0xb0581b51,
+ 0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
+ 0x6422284a, 0xb0447087,
+ 0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
+ 0x64127e8f, 0xb030c8cf,
+ 0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
+ 0x6402d0f8, 0xb01d242b,
+ 0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
+ 0x63f31f86, 0xb009829c,
+ 0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
+ 0x63e36a3a, 0xaff5e421,
+ 0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
+ 0x63d3b114, 0xafe248bd,
+ 0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
+ 0x63c3f415, 0xafceb06f,
+ 0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
+ 0x63b4333d, 0xafbb1b39,
+ 0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
+ 0x63a46e8d, 0xafa7891b,
+ 0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
+ 0x6394a606, 0xaf93fa16,
+ 0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
+ 0x6384d9a7, 0xaf806e2b,
+ 0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
+ 0x63750973, 0xaf6ce55a,
+ 0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
+ 0x63653569, 0xaf595fa4,
+ 0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
+ 0x63555d8a, 0xaf45dd0b,
+ 0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
+ 0x634581d6, 0xaf325d8e,
+ 0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
+ 0x6335a24f, 0xaf1ee12e,
+ 0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
+ 0x6325bef5, 0xaf0b67ed,
+ 0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
+ 0x6315d7c8, 0xaef7f1cb,
+ 0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
+ 0x6305ecc9, 0xaee47ec9,
+ 0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
+ 0x62f5fdf9, 0xaed10ee7,
+ 0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
+ 0x62e60b58, 0xaebda227,
+ 0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
+ 0x62d614e7, 0xaeaa3888,
+ 0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
+ 0x62c61aa7, 0xae96d20c,
+ 0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
+ 0x62b61c98, 0xae836eb4,
+ 0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
+ 0x62a61aba, 0xae700e80,
+ 0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
+ 0x6296150f, 0xae5cb171,
+ 0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
+ 0x62860b97, 0xae495787,
+ 0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
+ 0x6275fe52, 0xae3600c4,
+ 0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
+ 0x6265ed42, 0xae22ad29,
+ 0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
+ 0x6255d866, 0xae0f5cb5,
+ 0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
+ 0x6245bfc0, 0xadfc0f6a,
+ 0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
+ 0x6235a351, 0xade8c548,
+ 0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
+ 0x62258317, 0xadd57e51,
+ 0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
+ 0x62155f16, 0xadc23a85,
+ 0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
+ 0x6205374c, 0xadaef9e4,
+ 0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
+ 0x61f50bba, 0xad9bbc70,
+ 0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
+ 0x61e4dc62, 0xad888229,
+ 0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
+ 0x61d4a944, 0xad754b0f,
+ 0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
+ 0x61c47260, 0xad621725,
+ 0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
+ 0x61b437b7, 0xad4ee66a,
+ 0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
+ 0x61a3f94a, 0xad3bb8df,
+ 0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
+ 0x6193b719, 0xad288e85,
+ 0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
+ 0x61837126, 0xad15675c,
+ 0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
+ 0x61732770, 0xad024366,
+ 0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
+ 0x6162d9f8, 0xacef22a3,
+ 0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
+ 0x615288be, 0xacdc0514,
+ 0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
+ 0x614233c5, 0xacc8eab9,
+ 0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
+ 0x6131db0b, 0xacb5d394,
+ 0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
+ 0x61217e92, 0xaca2bfa4,
+ 0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
+ 0x61111e5b, 0xac8faeec,
+ 0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
+ 0x6100ba65, 0xac7ca16b,
+ 0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
+ 0x60f052b2, 0xac699722,
+ 0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
+ 0x60dfe743, 0xac569012,
+ 0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
+ 0x60cf7817, 0xac438c3c,
+ 0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
+ 0x60bf0530, 0xac308ba0,
+ 0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
+ 0x60ae8e8d, 0xac1d8e40,
+ 0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
+ 0x609e1431, 0xac0a941b,
+ 0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
+ 0x608d961b, 0xabf79d33,
+ 0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
+ 0x607d144c, 0xabe4a988,
+ 0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
+ 0x606c8ec5, 0xabd1b91c,
+ 0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
+ 0x605c0587, 0xabbecbee,
+ 0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
+ 0x604b7891, 0xababe200,
+ 0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
+ 0x603ae7e5, 0xab98fb52,
+ 0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
+ 0x602a5383, 0xab8617e6,
+ 0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
+ 0x6019bb6b, 0xab7337bb,
+ 0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
+ 0x60091fa0, 0xab605ad2,
+ 0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
+ 0x5ff88021, 0xab4d812d,
+ 0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
+ 0x5fe7dcee, 0xab3aaacb,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
+ 0x5fd73609, 0xab27d7ae,
+ 0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
+ 0x5fc68b72, 0xab1507d7,
+ 0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
+ 0x5fb5dd29, 0xab023b46,
+ 0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
+ 0x5fa52b31, 0xaaef71fb,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
+ 0x5f947588, 0xaadcabf8,
+ 0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
+ 0x5f83bc2f, 0xaac9e93e,
+ 0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
+ 0x5f72ff28, 0xaab729cc,
+ 0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
+ 0x5f623e73, 0xaaa46da4,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
+ 0x5f517a11, 0xaa91b4c7,
+ 0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
+ 0x5f40b202, 0xaa7eff34,
+ 0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
+ 0x5f2fe647, 0xaa6c4cee,
+ 0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
+ 0x5f1f16e0, 0xaa599df4,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
+ 0x5f0e43ce, 0xaa46f248,
+ 0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
+ 0x5efd6d13, 0xaa3449e9,
+ 0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
+ 0x5eec92ae, 0xaa21a4d9,
+ 0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
+ 0x5edbb49f, 0xaa0f0319,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
+ 0x5ecad2e9, 0xa9fc64a9,
+ 0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
+ 0x5eb9ed8b, 0xa9e9c98a,
+ 0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
+ 0x5ea90487, 0xa9d731bd,
+ 0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
+ 0x5e9817dc, 0xa9c49d42,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
+ 0x5e87278b, 0xa9b20c1a,
+ 0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
+ 0x5e763395, 0xa99f7e46,
+ 0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
+ 0x5e653bfc, 0xa98cf3c6,
+ 0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
+ 0x5e5440be, 0xa97a6c9c,
+ 0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
+ 0x5e4341de, 0xa967e8c7,
+ 0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
+ 0x5e323f5b, 0xa9556849,
+ 0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
+ 0x5e213936, 0xa942eb23,
+ 0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
+ 0x5e102f71, 0xa9307155,
+ 0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
+ 0x5dff220b, 0xa91dfadf,
+ 0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
+ 0x5dee1105, 0xa90b87c3,
+ 0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
+ 0x5ddcfc61, 0xa8f91801,
+ 0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
+ 0x5dcbe41d, 0xa8e6ab9a,
+ 0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
+ 0x5dbac83d, 0xa8d4428f,
+ 0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
+ 0x5da9a8bf, 0xa8c1dce0,
+ 0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
+ 0x5d9885a5, 0xa8af7a8e,
+ 0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
+ 0x5d875eef, 0xa89d1b99,
+ 0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
+ 0x5d76349d, 0xa88ac004,
+ 0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
+ 0x5d6506b2, 0xa87867cd,
+ 0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
+ 0x5d53d52d, 0xa86612f6,
+ 0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
+ 0x5d42a00e, 0xa853c180,
+ 0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
+ 0x5d316757, 0xa841736c,
+ 0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
+ 0x5d202b09, 0xa82f28b9,
+ 0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
+ 0x5d0eeb23, 0xa81ce169,
+ 0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
+ 0x5cfda7a7, 0xa80a9d7c,
+ 0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
+ 0x5cec6095, 0xa7f85cf3,
+ 0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
+ 0x5cdb15ed, 0xa7e61fd0,
+ 0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
+ 0x5cc9c7b2, 0xa7d3e611,
+ 0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
+ 0x5cb875e3, 0xa7c1afb9,
+ 0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
+ 0x5ca72080, 0xa7af7cc8,
+ 0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
+ 0x5c95c78b, 0xa79d4d3f,
+ 0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
+ 0x5c846b05, 0xa78b211e,
+ 0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
+ 0x5c730aed, 0xa778f866,
+ 0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
+ 0x5c61a745, 0xa766d317,
+ 0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
+ 0x5c50400d, 0xa754b134,
+ 0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
+ 0x5c3ed545, 0xa74292bb,
+ 0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
+ 0x5c2d66f0, 0xa73077ae,
+ 0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
+ 0x5c1bf50d, 0xa71e600d,
+ 0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
+ 0x5c0a7f9c, 0xa70c4bda,
+ 0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
+ 0x5bf906a0, 0xa6fa3b15,
+ 0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
+ 0x5be78a17, 0xa6e82dbe,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
+ 0x5bd60a03, 0xa6d623d7,
+ 0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
+ 0x5bc48666, 0xa6c41d60,
+ 0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
+ 0x5bb2ff3e, 0xa6b21a59,
+ 0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
+ 0x5ba1748d, 0xa6a01ac4,
+ 0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
+ 0x5b8fe654, 0xa68e1ea1,
+ 0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
+ 0x5b7e5493, 0xa67c25f0,
+ 0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
+ 0x5b6cbf4c, 0xa66a30b3,
+ 0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
+ 0x5b5b267e, 0xa6583eeb,
+ 0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
+ 0x5b498a2a, 0xa6465097,
+ 0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
+ 0x5b37ea51, 0xa63465b9,
+ 0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
+ 0x5b2646f4, 0xa6227e50,
+ 0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
+ 0x5b14a014, 0xa6109a5f,
+ 0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
+ 0x5b02f5b0, 0xa5feb9e6,
+ 0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
+ 0x5af147ca, 0xa5ecdce5,
+ 0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
+ 0x5adf9663, 0xa5db035c,
+ 0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
+ 0x5acde17b, 0xa5c92d4e,
+ 0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
+ 0x5abc2912, 0xa5b75aba,
+ 0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
+ 0x5aaa6d2b, 0xa5a58ba1,
+ 0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
+ 0x5a98adc4, 0xa593c004,
+ 0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
+ 0x5a86eadf, 0xa581f7e3,
+ 0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
+ 0x5a75247c, 0xa570333f,
+ 0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
+ 0x5a635a9d, 0xa55e7219,
+ 0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
+ 0x5a518d42, 0xa54cb472,
+ 0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
+ 0x5a3fbc6b, 0xa53afa49,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
+ 0x5a2de81a, 0xa52943a1,
+ 0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
+ 0x5a1c104f, 0xa5179079,
+ 0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
+ 0x5a0a350a, 0xa505e0d2,
+ 0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
+ 0x59f8564c, 0xa4f434ae,
+ 0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
+ 0x59e67417, 0xa4e28c0c,
+ 0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
+ 0x59d48e6a, 0xa4d0e6ed,
+ 0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
+ 0x59c2a547, 0xa4bf4552,
+ 0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
+ 0x59b0b8ae, 0xa4ada73c,
+ 0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
+ 0x599ec8a0, 0xa49c0cab,
+ 0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
+ 0x598cd51d, 0xa48a75a0,
+ 0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
+ 0x597ade26, 0xa478e21b,
+ 0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
+ 0x5968e3bc, 0xa467521e,
+ 0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
+ 0x5956e5e0, 0xa455c5a9,
+ 0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
+ 0x5944e492, 0xa4443cbd,
+ 0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
+ 0x5932dfd3, 0xa432b75a,
+ 0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
+ 0x5920d7a3, 0xa4213581,
+ 0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
+ 0x590ecc04, 0xa40fb733,
+ 0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
+ 0x58fcbcf6, 0xa3fe3c71,
+ 0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
+ 0x58eaaa7a, 0xa3ecc53a,
+ 0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
+ 0x58d89490, 0xa3db5190,
+ 0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
+ 0x58c67b39, 0xa3c9e174,
+ 0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
+ 0x58b45e76, 0xa3b874e5,
+ 0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
+ 0x58a23e48, 0xa3a70be6,
+ 0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
+ 0x58901aaf, 0xa395a675,
+ 0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
+ 0x587df3ab, 0xa3844495,
+ 0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
+ 0x586bc93f, 0xa372e646,
+ 0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
+ 0x58599b69, 0xa3618b88,
+ 0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
+ 0x58476a2c, 0xa350345c,
+ 0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
+ 0x58353587, 0xa33ee0c3,
+ 0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
+ 0x5822fd7c, 0xa32d90be,
+ 0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
+ 0x5810c20b, 0xa31c444c,
+ 0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
+ 0x57fe8335, 0xa30afb70,
+ 0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
+ 0x57ec40fa, 0xa2f9b629,
+ 0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
+ 0x57d9fb5c, 0xa2e87477,
+ 0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
+ 0x57c7b25a, 0xa2d7365d,
+ 0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
+ 0x57b565f6, 0xa2c5fbda,
+ 0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
+ 0x57a31631, 0xa2b4c4f0,
+ 0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
+ 0x5790c30a, 0xa2a3919e,
+ 0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
+ 0x577e6c84, 0xa29261e5,
+ 0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
+ 0x576c129d, 0xa28135c7,
+ 0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
+ 0x5759b558, 0xa2700d43,
+ 0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
+ 0x574754b5, 0xa25ee85b,
+ 0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
+ 0x5734f0b5, 0xa24dc70f,
+ 0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
+ 0x57228957, 0xa23ca95f,
+ 0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
+ 0x57101e9e, 0xa22b8f4d,
+ 0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
+ 0x56fdb08a, 0xa21a78d9,
+ 0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
+ 0x56eb3f1a, 0xa2096604,
+ 0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
+ 0x56d8ca51, 0xa1f856ce,
+ 0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
+ 0x56c6522f, 0xa1e74b38,
+ 0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
+ 0x56b3d6b5, 0xa1d64343,
+ 0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
+ 0x56a157e3, 0xa1c53ef0,
+ 0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
+ 0x568ed5b9, 0xa1b43e3e,
+ 0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
+ 0x567c503a, 0xa1a3412f,
+ 0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
+ 0x5669c765, 0xa19247c3,
+ 0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
+ 0x56573b3b, 0xa18151fb,
+ 0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
+ 0x5644abbc, 0xa1705fd8,
+ 0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
+ 0x563218eb, 0xa15f715a,
+ 0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
+ 0x561f82c7, 0xa14e8682,
+ 0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
+ 0x560ce950, 0xa13d9f51,
+ 0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
+ 0x55fa4c89, 0xa12cbbc7,
+ 0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
+ 0x55e7ac71, 0xa11bdbe4,
+ 0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
+ 0x55d50909, 0xa10affab,
+ 0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
+ 0x55c26251, 0xa0fa271a,
+ 0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
+ 0x55afb84c, 0xa0e95234,
+ 0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
+ 0x559d0af9, 0xa0d880f7,
+ 0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
+ 0x558a5a58, 0xa0c7b366,
+ 0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
+ 0x5577a66c, 0xa0b6e981,
+ 0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
+ 0x5564ef34, 0xa0a62348,
+ 0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
+ 0x555234b1, 0xa09560bc,
+ 0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
+ 0x553f76e4, 0xa084a1de,
+ 0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
+ 0x552cb5ce, 0xa073e6af,
+ 0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
+ 0x5519f16f, 0xa0632f2e,
+ 0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
+ 0x550729c9, 0xa0527b5d,
+ 0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
+ 0x54f45edb, 0xa041cb3c,
+ 0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
+ 0x54e190a6, 0xa0311ecd,
+ 0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
+ 0x54cebf2c, 0xa020760e,
+ 0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
+ 0x54bbea6d, 0xa00fd102,
+ 0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
+ 0x54a91269, 0x9fff2fa9,
+ 0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
+ 0x54963722, 0x9fee9204,
+ 0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
+ 0x54835898, 0x9fddf812,
+ 0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
+ 0x547076cc, 0x9fcd61d6,
+ 0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
+ 0x545d91bf, 0x9fbccf4f,
+ 0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
+ 0x544aa971, 0x9fac407e,
+ 0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
+ 0x5437bde3, 0x9f9bb563,
+ 0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
+ 0x5424cf16, 0x9f8b2e00,
+ 0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
+ 0x5411dd0a, 0x9f7aaa55,
+ 0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
+ 0x53fee7c1, 0x9f6a2a63,
+ 0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
+ 0x53ebef3a, 0x9f59ae29,
+ 0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
+ 0x53d8f378, 0x9f4935aa,
+ 0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
+ 0x53c5f479, 0x9f38c0e5,
+ 0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
+ 0x53b2f240, 0x9f284fdc,
+ 0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
+ 0x539feccd, 0x9f17e28e,
+ 0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
+ 0x538ce421, 0x9f0778fd,
+ 0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
+ 0x5379d83c, 0x9ef71328,
+ 0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
+ 0x5366c91f, 0x9ee6b112,
+ 0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
+ 0x5353b6cb, 0x9ed652ba,
+ 0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
+ 0x5340a140, 0x9ec5f820,
+ 0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
+ 0x532d8880, 0x9eb5a146,
+ 0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
+ 0x531a6c8b, 0x9ea54e2d,
+ 0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
+ 0x53074d62, 0x9e94fed4,
+ 0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
+ 0x52f42b05, 0x9e84b33d,
+ 0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
+ 0x52e10576, 0x9e746b68,
+ 0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
+ 0x52cddcb5, 0x9e642756,
+ 0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
+ 0x52bab0c2, 0x9e53e707,
+ 0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
+ 0x52a7819f, 0x9e43aa7c,
+ 0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
+ 0x52944f4c, 0x9e3371b5,
+ 0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
+ 0x528119ca, 0x9e233cb4,
+ 0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
+ 0x526de11a, 0x9e130b79,
+ 0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
+ 0x525aa53c, 0x9e02de04,
+ 0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
+ 0x52476631, 0x9df2b456,
+ 0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
+ 0x523423fb, 0x9de28e70,
+ 0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
+ 0x5220de99, 0x9dd26c53,
+ 0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
+ 0x520d960c, 0x9dc24dfe,
+ 0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
+ 0x51fa4a56, 0x9db23373,
+ 0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
+ 0x51e6fb76, 0x9da21cb2,
+ 0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
+ 0x51d3a96f, 0x9d9209bd,
+ 0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
+ 0x51c0543f, 0x9d81fa92,
+ 0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
+ 0x51acfbe9, 0x9d71ef34,
+ 0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
+ 0x5199a06d, 0x9d61e7a2,
+ 0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
+ 0x518641cb, 0x9d51e3dd,
+ 0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
+ 0x5172e005, 0x9d41e3e7,
+ 0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
+ 0x515f7b1a, 0x9d31e7bf,
+ 0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
+ 0x514c130d, 0x9d21ef66,
+ 0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
+ 0x5138a7dd, 0x9d11fadd,
+ 0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
+ 0x5125398c, 0x9d020a25,
+ 0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
+ 0x5111c81a, 0x9cf21d3d,
+ 0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
+ 0x50fe5388, 0x9ce23427,
+ 0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
+ 0x50eadbd6, 0x9cd24ee4,
+ 0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
+ 0x50d76106, 0x9cc26d73,
+ 0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
+ 0x50c3e317, 0x9cb28fd5,
+ 0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
+ 0x50b0620c, 0x9ca2b60c,
+ 0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
+ 0x509cdde4, 0x9c92e017,
+ 0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
+ 0x508956a1, 0x9c830df8,
+ 0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
+ 0x5075cc43, 0x9c733faf,
+ 0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
+ 0x50623ecb, 0x9c63753c,
+ 0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
+ 0x504eae39, 0x9c53aea0,
+ 0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
+ 0x503b1a8f, 0x9c43ebdc,
+ 0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
+ 0x502783cd, 0x9c342cf0,
+ 0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
+ 0x5013e9f4, 0x9c2471de,
+ 0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
+ 0x50004d04, 0x9c14baa4,
+ 0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
+ 0x4fecacff, 0x9c050745,
+ 0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
+ 0x4fd909e5, 0x9bf557c1,
+ 0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
+ 0x4fc563b7, 0x9be5ac18,
+ 0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
+ 0x4fb1ba76, 0x9bd6044b,
+ 0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
+ 0x4f9e0e22, 0x9bc6605b,
+ 0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
+ 0x4f8a5ebd, 0x9bb6c048,
+ 0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
+ 0x4f76ac46, 0x9ba72413,
+ 0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
+ 0x4f62f6bf, 0x9b978bbc,
+ 0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
+ 0x4f4f3e29, 0x9b87f744,
+ 0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
+ 0x4f3b8284, 0x9b7866ab,
+ 0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
+ 0x4f27c3d1, 0x9b68d9f3,
+ 0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
+ 0x4f140210, 0x9b59511c,
+ 0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
+ 0x4f003d43, 0x9b49cc26,
+ 0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
+ 0x4eec756b, 0x9b3a4b11,
+ 0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
+ 0x4ed8aa87, 0x9b2acde0,
+ 0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
+ 0x4ec4dc99, 0x9b1b5492,
+ 0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
+ 0x4eb10ba2, 0x9b0bdf27,
+ 0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
+ 0x4e9d37a3, 0x9afc6da1,
+ 0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
+ 0x4e89609b, 0x9aed0000,
+ 0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
+ 0x4e75868c, 0x9add9644,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
+ 0x4e61a977, 0x9ace306f,
+ 0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
+ 0x4e4dc95c, 0x9abece80,
+ 0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
+ 0x4e39e63d, 0x9aaf7079,
+ 0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
+ 0x4e260019, 0x9aa01659,
+ 0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
+ 0x4e1216f2, 0x9a90c022,
+ 0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
+ 0x4dfe2ac9, 0x9a816dd5,
+ 0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
+ 0x4dea3b9d, 0x9a721f71,
+ 0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
+ 0x4dd64971, 0x9a62d4f7,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
+ 0x4dc25445, 0x9a538e68,
+ 0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
+ 0x4dae5c19, 0x9a444bc5,
+ 0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
+ 0x4d9a60ee, 0x9a350d0d,
+ 0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
+ 0x4d8662c6, 0x9a25d243,
+ 0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
+ 0x4d7261a0, 0x9a169b65,
+ 0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
+ 0x4d5e5d7e, 0x9a076875,
+ 0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
+ 0x4d4a5661, 0x99f83974,
+ 0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
+ 0x4d364c48, 0x99e90e62,
+ 0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
+ 0x4d223f36, 0x99d9e73f,
+ 0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
+ 0x4d0e2f2a, 0x99cac40d,
+ 0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
+ 0x4cfa1c26, 0x99bba4cb,
+ 0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
+ 0x4ce6062a, 0x99ac897b,
+ 0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
+ 0x4cd1ed37, 0x999d721c,
+ 0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
+ 0x4cbdd14e, 0x998e5eb1,
+ 0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
+ 0x4ca9b26f, 0x997f4f38,
+ 0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
+ 0x4c95909c, 0x997043b2,
+ 0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
+ 0x4c816bd5, 0x99613c22,
+ 0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
+ 0x4c6d441b, 0x99523885,
+ 0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
+ 0x4c59196f, 0x994338df,
+ 0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
+ 0x4c44ebd1, 0x99343d2e,
+ 0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
+ 0x4c30bb42, 0x99254574,
+ 0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
+ 0x4c1c87c3, 0x991651b1,
+ 0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
+ 0x4c085156, 0x990761e5,
+ 0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
+ 0x4bf417f9, 0x98f87612,
+ 0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
+ 0x4bdfdbaf, 0x98e98e38,
+ 0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
+ 0x4bcb9c79, 0x98daaa57,
+ 0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
+ 0x4bb75a56, 0x98cbca70,
+ 0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
+ 0x4ba31548, 0x98bcee84,
+ 0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
+ 0x4b8ecd4f, 0x98ae1693,
+ 0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
+ 0x4b7a826d, 0x989f429e,
+ 0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
+ 0x4b6634a2, 0x989072a5,
+ 0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
+ 0x4b51e3ee, 0x9881a6a9,
+ 0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
+ 0x4b3d9053, 0x9872deaa,
+ 0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
+ 0x4b2939d2, 0x98641aa9,
+ 0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
+ 0x4b14e06b, 0x98555aa7,
+ 0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
+ 0x4b00841f, 0x98469ea4,
+ 0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
+ 0x4aec24ee, 0x9837e6a1,
+ 0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
+ 0x4ad7c2da, 0x9829329e,
+ 0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
+ 0x4ac35de4, 0x981a829c,
+ 0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
+ 0x4aaef60b, 0x980bd69b,
+ 0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
+ 0x4a9a8b52, 0x97fd2e9c,
+ 0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
+ 0x4a861db8, 0x97ee8aa0,
+ 0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
+ 0x4a71ad3e, 0x97dfeaa7,
+ 0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
+ 0x4a5d39e6, 0x97d14eb2,
+ 0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
+ 0x4a48c3b0, 0x97c2b6c1,
+ 0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
+ 0x4a344a9d, 0x97b422d4,
+ 0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
+ 0x4a1fcead, 0x97a592ed,
+ 0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
+ 0x4a0b4fe2, 0x9797070c,
+ 0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
+ 0x49f6ce3c, 0x97887f32,
+ 0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
+ 0x49e249bc, 0x9779fb5e,
+ 0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
+ 0x49cdc263, 0x976b7b92,
+ 0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
+ 0x49b93832, 0x975cffcf,
+ 0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
+ 0x49a4ab28, 0x974e8813,
+ 0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
+ 0x49901b48, 0x97401462,
+ 0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
+ 0x497b8892, 0x9731a4ba,
+ 0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
+ 0x4966f307, 0x9723391c,
+ 0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
+ 0x49525aa7, 0x9714d18a,
+ 0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
+ 0x493dbf74, 0x97066e03,
+ 0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
+ 0x4929216e, 0x96f80e88,
+ 0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
+ 0x49148095, 0x96e9b319,
+ 0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
+ 0x48ffdcec, 0x96db5bb8,
+ 0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
+ 0x48eb3672, 0x96cd0865,
+ 0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
+ 0x48d68d28, 0x96beb91f,
+ 0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
+ 0x48c1e10f, 0x96b06de9,
+ 0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
+ 0x48ad3228, 0x96a226c2,
+ 0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
+ 0x48988074, 0x9693e3ab,
+ 0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
+ 0x4883cbf4, 0x9685a4a4,
+ 0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
+ 0x486f14a8, 0x967769af,
+ 0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
+ 0x485a5a90, 0x966932cb,
+ 0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
+ 0x48459daf, 0x965afff9,
+ 0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
+ 0x4830de05, 0x964cd139,
+ 0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
+ 0x481c1b92, 0x963ea68d,
+ 0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
+ 0x48075657, 0x96307ff5,
+ 0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
+ 0x47f28e56, 0x96225d71,
+ 0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
+ 0x47ddc38e, 0x96143f02,
+ 0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
+ 0x47c8f601, 0x960624a9,
+ 0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
+ 0x47b425af, 0x95f80e65,
+ 0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
+ 0x479f529a, 0x95e9fc38,
+ 0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
+ 0x478a7cc2, 0x95dbee21,
+ 0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
+ 0x4775a428, 0x95cde423,
+ 0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
+ 0x4760c8cd, 0x95bfde3c,
+ 0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
+ 0x474beab1, 0x95b1dc6e,
+ 0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
+ 0x473709d5, 0x95a3deb9,
+ 0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
+ 0x4722263b, 0x9595e51e,
+ 0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
+ 0x470d3fe3, 0x9587ef9e,
+ 0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
+ 0x46f856cd, 0x9579fe38,
+ 0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
+ 0x46e36afb, 0x956c10ed,
+ 0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
+ 0x46ce7c6d, 0x955e27bf,
+ 0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
+ 0x46b98b24, 0x955042ac,
+ 0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
+ 0x46a49722, 0x954261b7,
+ 0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
+ 0x468fa066, 0x953484df,
+ 0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
+ 0x467aa6f2, 0x9526ac25,
+ 0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
+ 0x4665aac6, 0x9518d78a,
+ 0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
+ 0x4650abe3, 0x950b070e,
+ 0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
+ 0x463baa4a, 0x94fd3ab1,
+ 0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
+ 0x4626a5fd, 0x94ef7275,
+ 0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
+ 0x46119efa, 0x94e1ae59,
+ 0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
+ 0x45fc9545, 0x94d3ee5f,
+ 0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
+ 0x45e788dc, 0x94c63286,
+ 0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
+ 0x45d279c2, 0x94b87ad0,
+ 0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
+ 0x45bd67f6, 0x94aac73c,
+ 0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
+ 0x45a8537a, 0x949d17cc,
+ 0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
+ 0x45933c4f, 0x948f6c7f,
+ 0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
+ 0x457e2275, 0x9481c557,
+ 0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
+ 0x456905ed, 0x94742254,
+ 0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
+ 0x4553e6b8, 0x94668376,
+ 0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
+ 0x453ec4d7, 0x9458e8bf,
+ 0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
+ 0x4529a04b, 0x944b522d,
+ 0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
+ 0x45147913, 0x943dbfc3,
+ 0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
+ 0x44ff4f32, 0x94303180,
+ 0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
+ 0x44ea22a9, 0x9422a766,
+ 0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
+ 0x44d4f376, 0x94152174,
+ 0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
+ 0x44bfc19d, 0x94079fab,
+ 0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
+ 0x44aa8d1d, 0x93fa220b,
+ 0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
+ 0x449555f7, 0x93eca896,
+ 0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
+ 0x44801c2d, 0x93df334c,
+ 0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
+ 0x446adfbe, 0x93d1c22c,
+ 0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
+ 0x4455a0ac, 0x93c45539,
+ 0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
+ 0x44405ef8, 0x93b6ec71,
+ 0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
+ 0x442b1aa2, 0x93a987d6,
+ 0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
+ 0x4415d3ab, 0x939c2769,
+ 0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
+ 0x44008a14, 0x938ecb29,
+ 0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
+ 0x43eb3ddf, 0x93817318,
+ 0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
+ 0x43d5ef0a, 0x93741f35,
+ 0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
+ 0x43c09d99, 0x9366cf82,
+ 0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
+ 0x43ab498a, 0x935983ff,
+ 0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
+ 0x4395f2e0, 0x934c3cab,
+ 0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
+ 0x4380999b, 0x933ef989,
+ 0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
+ 0x436b3dbb, 0x9331ba98,
+ 0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
+ 0x4355df42, 0x93247fd9,
+ 0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
+ 0x43407e31, 0x9317494c,
+ 0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
+ 0x432b1a87, 0x930a16f3,
+ 0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
+ 0x4315b447, 0x92fce8cc,
+ 0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
+ 0x43004b71, 0x92efbeda,
+ 0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
+ 0x42eae005, 0x92e2991c,
+ 0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
+ 0x42d57205, 0x92d57792,
+ 0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
+ 0x42c00172, 0x92c85a3f,
+ 0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
+ 0x42aa8e4b, 0x92bb4121,
+ 0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
+ 0x42951893, 0x92ae2c3a,
+ 0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
+ 0x427fa049, 0x92a11b89,
+ 0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
+ 0x426a256f, 0x92940f10,
+ 0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
+ 0x4254a806, 0x928706cf,
+ 0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
+ 0x423f280e, 0x927a02c7,
+ 0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
+ 0x4229a588, 0x926d02f7,
+ 0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
+ 0x42142075, 0x92600761,
+ 0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
+ 0x41fe98d6, 0x92531005,
+ 0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
+ 0x41e90eac, 0x92461ce3,
+ 0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
+ 0x41d381f7, 0x92392dfc,
+ 0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
+ 0x41bdf2b9, 0x922c4351,
+ 0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
+ 0x41a860f1, 0x921f5ce1,
+ 0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
+ 0x4192cca2, 0x92127aae,
+ 0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
+ 0x417d35cb, 0x92059cb8,
+ 0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
+ 0x41679c6f, 0x91f8c300,
+ 0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
+ 0x4152008c, 0x91ebed85,
+ 0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
+ 0x413c6225, 0x91df1c49,
+ 0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
+ 0x4126c13a, 0x91d24f4c,
+ 0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
+ 0x41111dcc, 0x91c5868e,
+ 0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
+ 0x40fb77dc, 0x91b8c210,
+ 0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
+ 0x40e5cf6a, 0x91ac01d2,
+ 0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
+ 0x40d02478, 0x919f45d6,
+ 0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
+ 0x40ba7706, 0x91928e1a,
+ 0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
+ 0x40a4c716, 0x9185daa1,
+ 0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
+ 0x408f14a7, 0x91792b6a,
+ 0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
+ 0x40795fbc, 0x916c8076,
+ 0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
+ 0x4063a854, 0x915fd9c5,
+ 0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
+ 0x404dee70, 0x91533758,
+ 0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
+ 0x40383212, 0x9146992f,
+ 0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
+ 0x4022733a, 0x9139ff4b,
+ 0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
+ 0x400cb1e9, 0x912d69ad,
+ 0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
+ 0x3ff6ee1f, 0x9120d854,
+ 0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
+ 0x3fe127df, 0x91144b41,
+ 0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
+ 0x3fcb5f28, 0x9107c276,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
+ 0x3fb593fb, 0x90fb3df1,
+ 0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
+ 0x3f9fc65a, 0x90eebdb4,
+ 0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
+ 0x3f89f645, 0x90e241bf,
+ 0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
+ 0x3f7423bc, 0x90d5ca13,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
+ 0x3f5e4ec2, 0x90c956b1,
+ 0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
+ 0x3f487755, 0x90bce797,
+ 0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
+ 0x3f329d79, 0x90b07cc8,
+ 0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
+ 0x3f1cc12c, 0x90a41644,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
+ 0x3f06e271, 0x9097b40a,
+ 0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
+ 0x3ef10148, 0x908b561c,
+ 0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
+ 0x3edb1db1, 0x907efc7a,
+ 0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
+ 0x3ec537ae, 0x9072a725,
+ 0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
+ 0x3eaf4f40, 0x9066561d,
+ 0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
+ 0x3e996467, 0x905a0962,
+ 0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
+ 0x3e837724, 0x904dc0f5,
+ 0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
+ 0x3e6d8778, 0x90417cd6,
+ 0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
+ 0x3e579564, 0x90353d06,
+ 0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
+ 0x3e41a0e8, 0x90290186,
+ 0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
+ 0x3e2baa07, 0x901cca55,
+ 0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
+ 0x3e15b0bf, 0x90109775,
+ 0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
+ 0x3dffb513, 0x900468e5,
+ 0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
+ 0x3de9b703, 0x8ff83ea7,
+ 0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
+ 0x3dd3b690, 0x8fec18ba,
+ 0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
+ 0x3dbdb3ba, 0x8fdff720,
+ 0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
+ 0x3da7ae84, 0x8fd3d9d8,
+ 0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
+ 0x3d91a6ed, 0x8fc7c0e3,
+ 0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
+ 0x3d7b9cf6, 0x8fbbac42,
+ 0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
+ 0x3d6590a0, 0x8faf9bf5,
+ 0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
+ 0x3d4f81ec, 0x8fa38ffc,
+ 0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
+ 0x3d3970dc, 0x8f978859,
+ 0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
+ 0x3d235d6f, 0x8f8b850a,
+ 0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
+ 0x3d0d47a6, 0x8f7f8612,
+ 0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
+ 0x3cf72f83, 0x8f738b70,
+ 0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
+ 0x3ce11507, 0x8f679525,
+ 0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
+ 0x3ccaf831, 0x8f5ba331,
+ 0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
+ 0x3cb4d904, 0x8f4fb595,
+ 0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
+ 0x3c9eb77f, 0x8f43cc50,
+ 0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
+ 0x3c8893a4, 0x8f37e765,
+ 0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
+ 0x3c726d73, 0x8f2c06d3,
+ 0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
+ 0x3c5c44ee, 0x8f202a9a,
+ 0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
+ 0x3c461a16, 0x8f1452bb,
+ 0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
+ 0x3c2fecea, 0x8f087f37,
+ 0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
+ 0x3c19bd6c, 0x8efcb00e,
+ 0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
+ 0x3c038b9e, 0x8ef0e540,
+ 0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
+ 0x3bed577e, 0x8ee51ece,
+ 0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
+ 0x3bd72110, 0x8ed95cb8,
+ 0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
+ 0x3bc0e853, 0x8ecd9eff,
+ 0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
+ 0x3baaad48, 0x8ec1e5a4,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
+ 0x3b946ff0, 0x8eb630a6,
+ 0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
+ 0x3b7e304c, 0x8eaa8006,
+ 0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
+ 0x3b67ee5d, 0x8e9ed3c4,
+ 0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
+ 0x3b51aa24, 0x8e932be2,
+ 0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
+ 0x3b3b63a1, 0x8e87885f,
+ 0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
+ 0x3b251ad6, 0x8e7be93c,
+ 0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
+ 0x3b0ecfc3, 0x8e704e79,
+ 0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
+ 0x3af88269, 0x8e64b817,
+ 0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
+ 0x3ae232c9, 0x8e592617,
+ 0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
+ 0x3acbe0e3, 0x8e4d9878,
+ 0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
+ 0x3ab58cba, 0x8e420f3b,
+ 0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
+ 0x3a9f364d, 0x8e368a61,
+ 0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
+ 0x3a88dd9d, 0x8e2b09e9,
+ 0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
+ 0x3a7282ac, 0x8e1f8dd6,
+ 0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
+ 0x3a5c257a, 0x8e141626,
+ 0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
+ 0x3a45c608, 0x8e08a2db,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
+ 0x3a2f6457, 0x8dfd33f4,
+ 0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
+ 0x3a190068, 0x8df1c973,
+ 0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
+ 0x3a029a3b, 0x8de66357,
+ 0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
+ 0x39ec31d1, 0x8ddb01a1,
+ 0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
+ 0x39d5c72c, 0x8dcfa452,
+ 0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
+ 0x39bf5a4d, 0x8dc44b6a,
+ 0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
+ 0x39a8eb33, 0x8db8f6ea,
+ 0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
+ 0x399279e0, 0x8dada6d1,
+ 0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
+ 0x397c0655, 0x8da25b21,
+ 0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
+ 0x39659092, 0x8d9713d9,
+ 0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
+ 0x394f1899, 0x8d8bd0fb,
+ 0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
+ 0x39389e6b, 0x8d809286,
+ 0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
+ 0x39222208, 0x8d75587b,
+ 0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
+ 0x390ba371, 0x8d6a22db,
+ 0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
+ 0x38f522a6, 0x8d5ef1a5,
+ 0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
+ 0x38de9faa, 0x8d53c4db,
+ 0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
+ 0x38c81a7c, 0x8d489c7d,
+ 0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
+ 0x38b1931e, 0x8d3d788b,
+ 0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
+ 0x389b0991, 0x8d325905,
+ 0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
+ 0x38847dd5, 0x8d273ded,
+ 0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
+ 0x386defeb, 0x8d1c2742,
+ 0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
+ 0x38575fd4, 0x8d111505,
+ 0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
+ 0x3840cd90, 0x8d060737,
+ 0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
+ 0x382a3922, 0x8cfafdd7,
+ 0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
+ 0x3813a28a, 0x8ceff8e6,
+ 0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
+ 0x37fd09c8, 0x8ce4f865,
+ 0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
+ 0x37e66edd, 0x8cd9fc54,
+ 0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
+ 0x37cfd1cb, 0x8ccf04b3,
+ 0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
+ 0x37b93292, 0x8cc41184,
+ 0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
+ 0x37a29132, 0x8cb922c6,
+ 0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
+ 0x378bedae, 0x8cae3879,
+ 0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
+ 0x37754806, 0x8ca3529f,
+ 0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
+ 0x375ea03a, 0x8c987137,
+ 0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
+ 0x3747f64c, 0x8c8d9442,
+ 0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
+ 0x37314a3c, 0x8c82bbc0,
+ 0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
+ 0x371a9c0b, 0x8c77e7b3,
+ 0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
+ 0x3703ebbb, 0x8c6d181a,
+ 0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
+ 0x36ed394b, 0x8c624cf5,
+ 0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
+ 0x36d684be, 0x8c578645,
+ 0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
+ 0x36bfce13, 0x8c4cc40b,
+ 0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
+ 0x36a9154c, 0x8c420647,
+ 0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
+ 0x36925a69, 0x8c374cf9,
+ 0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
+ 0x367b9d6c, 0x8c2c9822,
+ 0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
+ 0x3664de55, 0x8c21e7c2,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
+ 0x364e1d25, 0x8c173bda,
+ 0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
+ 0x363759de, 0x8c0c9469,
+ 0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
+ 0x3620947f, 0x8c01f171,
+ 0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
+ 0x3609cd0a, 0x8bf752f2,
+ 0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
+ 0x35f3037f, 0x8becb8ec,
+ 0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
+ 0x35dc37e0, 0x8be22360,
+ 0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
+ 0x35c56a2e, 0x8bd7924d,
+ 0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
+ 0x35ae9a69, 0x8bcd05b5,
+ 0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
+ 0x3597c892, 0x8bc27d98,
+ 0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
+ 0x3580f4aa, 0x8bb7f9f6,
+ 0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
+ 0x356a1eb2, 0x8bad7ad0,
+ 0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
+ 0x355346ab, 0x8ba30026,
+ 0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
+ 0x353c6c95, 0x8b9889f8,
+ 0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
+ 0x35259073, 0x8b8e1848,
+ 0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
+ 0x350eb243, 0x8b83ab14,
+ 0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
+ 0x34f7d208, 0x8b79425e,
+ 0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
+ 0x34e0efc2, 0x8b6ede26,
+ 0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
+ 0x34ca0b73, 0x8b647e6d,
+ 0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
+ 0x34b3251a, 0x8b5a2333,
+ 0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
+ 0x349c3cb9, 0x8b4fcc77,
+ 0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
+ 0x34855251, 0x8b457a3c,
+ 0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
+ 0x346e65e3, 0x8b3b2c80,
+ 0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
+ 0x3457776f, 0x8b30e345,
+ 0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
+ 0x344086f6, 0x8b269e8b,
+ 0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
+ 0x3429947a, 0x8b1c5e52,
+ 0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
+ 0x34129ffb, 0x8b12229b,
+ 0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
+ 0x33fba97a, 0x8b07eb66,
+ 0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
+ 0x33e4b0f8, 0x8afdb8b3,
+ 0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
+ 0x33cdb676, 0x8af38a83,
+ 0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
+ 0x33b6b9f4, 0x8ae960d6,
+ 0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
+ 0x339fbb74, 0x8adf3bad,
+ 0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
+ 0x3388baf7, 0x8ad51b08,
+ 0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
+ 0x3371b87d, 0x8acafee8,
+ 0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
+ 0x335ab407, 0x8ac0e74c,
+ 0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
+ 0x3343ad97, 0x8ab6d435,
+ 0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
+ 0x332ca52c, 0x8aacc5a4,
+ 0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
+ 0x33159ac8, 0x8aa2bb99,
+ 0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
+ 0x32fe8e6d, 0x8a98b614,
+ 0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
+ 0x32e7801a, 0x8a8eb516,
+ 0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
+ 0x32d06fd0, 0x8a84b89e,
+ 0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
+ 0x32b95d91, 0x8a7ac0af,
+ 0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
+ 0x32a2495d, 0x8a70cd47,
+ 0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
+ 0x328b3336, 0x8a66de68,
+ 0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
+ 0x32741b1c, 0x8a5cf411,
+ 0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
+ 0x325d0110, 0x8a530e43,
+ 0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
+ 0x3245e512, 0x8a492cff,
+ 0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
+ 0x322ec725, 0x8a3f5045,
+ 0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
+ 0x3217a748, 0x8a357814,
+ 0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
+ 0x3200857d, 0x8a2ba46e,
+ 0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
+ 0x31e961c5, 0x8a21d554,
+ 0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
+ 0x31d23c1f, 0x8a180ac4,
+ 0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
+ 0x31bb148f, 0x8a0e44c0,
+ 0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
+ 0x31a3eb13, 0x8a048348,
+ 0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
+ 0x318cbfad, 0x89fac65d,
+ 0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
+ 0x3175925e, 0x89f10dff,
+ 0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
+ 0x315e6328, 0x89e75a2d,
+ 0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
+ 0x31473209, 0x89ddaae9,
+ 0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
+ 0x312fff05, 0x89d40033,
+ 0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
+ 0x3118ca1b, 0x89ca5a0c,
+ 0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
+ 0x3101934d, 0x89c0b873,
+ 0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
+ 0x30ea5a9a, 0x89b71b69,
+ 0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
+ 0x30d32006, 0x89ad82ef,
+ 0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
+ 0x30bbe38f, 0x89a3ef04,
+ 0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
+ 0x30a4a537, 0x899a5faa,
+ 0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
+ 0x308d64ff, 0x8990d4e0,
+ 0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
+ 0x307622e8, 0x89874ea7,
+ 0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
+ 0x305edef3, 0x897dccff,
+ 0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
+ 0x30479920, 0x89744fe9,
+ 0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
+ 0x30305171, 0x896ad765,
+ 0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
+ 0x301907e6, 0x89616373,
+ 0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
+ 0x3001bc80, 0x8957f414,
+ 0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
+ 0x2fea6f41, 0x894e8948,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
+ 0x2fd32028, 0x89452310,
+ 0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
+ 0x2fbbcf38, 0x893bc16b,
+ 0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
+ 0x2fa47c71, 0x8932645b,
+ 0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
+ 0x2f8d27d3, 0x89290bdf,
+ 0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
+ 0x2f75d160, 0x891fb7f8,
+ 0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
+ 0x2f5e7919, 0x891668a6,
+ 0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
+ 0x2f471efe, 0x890d1dea,
+ 0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
+ 0x2f2fc310, 0x8903d7c4,
+ 0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
+ 0x2f186551, 0x88fa9634,
+ 0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
+ 0x2f0105c1, 0x88f1593b,
+ 0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
+ 0x2ee9a461, 0x88e820d9,
+ 0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
+ 0x2ed24132, 0x88deed0e,
+ 0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
+ 0x2ebadc35, 0x88d5bddb,
+ 0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
+ 0x2ea3756b, 0x88cc9340,
+ 0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
+ 0x2e8c0cd4, 0x88c36d3e,
+ 0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
+ 0x2e74a272, 0x88ba4bd4,
+ 0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
+ 0x2e5d3646, 0x88b12f04,
+ 0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
+ 0x2e45c850, 0x88a816cd,
+ 0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
+ 0x2e2e5891, 0x889f0330,
+ 0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
+ 0x2e16e70b, 0x8895f42d,
+ 0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
+ 0x2dff73bd, 0x888ce9c5,
+ 0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
+ 0x2de7feaa, 0x8883e3f8,
+ 0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
+ 0x2dd087d1, 0x887ae2c6,
+ 0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
+ 0x2db90f35, 0x8871e630,
+ 0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
+ 0x2da194d5, 0x8868ee35,
+ 0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
+ 0x2d8a18b3, 0x885ffad7,
+ 0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
+ 0x2d729acf, 0x88570c16,
+ 0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
+ 0x2d5b1b2b, 0x884e21f1,
+ 0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
+ 0x2d4399c7, 0x88453c6a,
+ 0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
+ 0x2d2c16a4, 0x883c5b81,
+ 0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
+ 0x2d1491c4, 0x88337f35,
+ 0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
+ 0x2cfd0b26, 0x882aa788,
+ 0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
+ 0x2ce582cd, 0x8821d47a,
+ 0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
+ 0x2ccdf8b8, 0x8819060a,
+ 0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
+ 0x2cb66ce9, 0x88103c3b,
+ 0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
+ 0x2c9edf61, 0x8807770a,
+ 0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
+ 0x2c875021, 0x87feb67a,
+ 0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
+ 0x2c6fbf29, 0x87f5fa8b,
+ 0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
+ 0x2c582c7b, 0x87ed433c,
+ 0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
+ 0x2c409816, 0x87e4908e,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
+ 0x2c2901fd, 0x87dbe281,
+ 0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
+ 0x2c116a31, 0x87d33916,
+ 0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
+ 0x2bf9d0b1, 0x87ca944e,
+ 0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
+ 0x2be2357f, 0x87c1f427,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
+ 0x2bca989d, 0x87b958a4,
+ 0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
+ 0x2bb2fa0a, 0x87b0c1c4,
+ 0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
+ 0x2b9b59c7, 0x87a82f87,
+ 0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
+ 0x2b83b7d7, 0x879fa1ed,
+ 0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
+ 0x2b6c1438, 0x879718f8,
+ 0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
+ 0x2b546eee, 0x878e94a7,
+ 0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
+ 0x2b3cc7f7, 0x878614fb,
+ 0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
+ 0x2b251f56, 0x877d99f4,
+ 0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
+ 0x2b0d750b, 0x87752392,
+ 0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
+ 0x2af5c917, 0x876cb1d6,
+ 0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
+ 0x2ade1b7c, 0x876444c1,
+ 0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
+ 0x2ac66c39, 0x875bdc51,
+ 0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
+ 0x2aaebb50, 0x87537888,
+ 0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
+ 0x2a9708c1, 0x874b1966,
+ 0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
+ 0x2a7f548e, 0x8742beec,
+ 0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
+ 0x2a679eb8, 0x873a6919,
+ 0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
+ 0x2a4fe740, 0x873217ee,
+ 0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
+ 0x2a382e25, 0x8729cb6b,
+ 0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
+ 0x2a20736a, 0x87218391,
+ 0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
+ 0x2a08b710, 0x87194060,
+ 0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
+ 0x29f0f916, 0x871101d8,
+ 0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
+ 0x29d9397f, 0x8708c7fa,
+ 0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
+ 0x29c1784a, 0x870092c5,
+ 0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
+ 0x29a9b579, 0x86f8623b,
+ 0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
+ 0x2991f10e, 0x86f0365c,
+ 0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
+ 0x297a2b07, 0x86e80f27,
+ 0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
+ 0x29626368, 0x86dfec9d,
+ 0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
+ 0x294a9a30, 0x86d7cebf,
+ 0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
+ 0x2932cf60, 0x86cfb58c,
+ 0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
+ 0x291b02fa, 0x86c7a106,
+ 0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
+ 0x290334ff, 0x86bf912c,
+ 0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
+ 0x28eb656e, 0x86b785ff,
+ 0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
+ 0x28d3944a, 0x86af7f7e,
+ 0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
+ 0x28bbc192, 0x86a77dab,
+ 0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
+ 0x28a3ed49, 0x869f8086,
+ 0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
+ 0x288c176e, 0x8697880f,
+ 0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
+ 0x28744004, 0x868f9445,
+ 0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
+ 0x285c670a, 0x8687a52b,
+ 0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
+ 0x28448c81, 0x867fbabf,
+ 0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
+ 0x282cb06c, 0x8677d503,
+ 0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
+ 0x2814d2c9, 0x866ff3f6,
+ 0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
+ 0x27fcf39c, 0x86681798,
+ 0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
+ 0x27e512e3, 0x86603feb,
+ 0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
+ 0x27cd30a1, 0x86586cee,
+ 0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
+ 0x27b54cd6, 0x86509ea2,
+ 0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
+ 0x279d6783, 0x8648d507,
+ 0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
+ 0x278580a9, 0x8641101d,
+ 0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
+ 0x276d9849, 0x86394fe5,
+ 0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
+ 0x2755ae64, 0x8631945e,
+ 0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
+ 0x273dc2fa, 0x8629dd8a,
+ 0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
+ 0x2725d60e, 0x86222b68,
+ 0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
+ 0x270de79f, 0x861a7df9,
+ 0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
+ 0x26f5f7ae, 0x8612d53d,
+ 0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
+ 0x26de063d, 0x860b3135,
+ 0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
+ 0x26c6134d, 0x860391e0,
+ 0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
+ 0x26ae1edd, 0x85fbf73f,
+ 0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
+ 0x269628f0, 0x85f46152,
+ 0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
+ 0x267e3186, 0x85ecd01a,
+ 0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
+ 0x266638a1, 0x85e54397,
+ 0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
+ 0x264e3e40, 0x85ddbbc9,
+ 0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
+ 0x26364265, 0x85d638b0,
+ 0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
+ 0x261e4511, 0x85ceba4d,
+ 0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
+ 0x26064645, 0x85c740a0,
+ 0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
+ 0x25ee4601, 0x85bfcba9,
+ 0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
+ 0x25d64447, 0x85b85b68,
+ 0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
+ 0x25be4118, 0x85b0efdf,
+ 0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
+ 0x25a63c74, 0x85a9890d,
+ 0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
+ 0x258e365d, 0x85a226f2,
+ 0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
+ 0x25762ed3, 0x859ac98f,
+ 0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
+ 0x255e25d7, 0x859370e4,
+ 0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
+ 0x25461b6b, 0x858c1cf1,
+ 0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
+ 0x252e0f8e, 0x8584cdb7,
+ 0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
+ 0x25160243, 0x857d8335,
+ 0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
+ 0x24fdf389, 0x85763d6d,
+ 0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
+ 0x24e5e363, 0x856efc5e,
+ 0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
+ 0x24cdd1d0, 0x8567c009,
+ 0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
+ 0x24b5bed2, 0x8560886d,
+ 0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
+ 0x249daa6a, 0x8559558c,
+ 0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
+ 0x24859498, 0x85522766,
+ 0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
+ 0x246d7d5e, 0x854afdfa,
+ 0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
+ 0x245564bd, 0x8543d949,
+ 0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
+ 0x243d4ab4, 0x853cb954,
+ 0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
+ 0x24252f47, 0x85359e1a,
+ 0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
+ 0x240d1274, 0x852e879d,
+ 0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
+ 0x23f4f43e, 0x852775db,
+ 0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
+ 0x23dcd4a4, 0x852068d6,
+ 0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
+ 0x23c4b3a9, 0x8519608d,
+ 0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
+ 0x23ac914d, 0x85125d02,
+ 0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
+ 0x23946d90, 0x850b5e34,
+ 0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
+ 0x237c4875, 0x85046423,
+ 0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
+ 0x236421fb, 0x84fd6ed0,
+ 0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
+ 0x234bfa24, 0x84f67e3b,
+ 0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
+ 0x2333d0f1, 0x84ef9265,
+ 0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
+ 0x231ba662, 0x84e8ab4d,
+ 0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
+ 0x23037a78, 0x84e1c8f3,
+ 0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
+ 0x22eb4d36, 0x84daeb5a,
+ 0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
+ 0x22d31e9a, 0x84d4127f,
+ 0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
+ 0x22baeea7, 0x84cd3e64,
+ 0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
+ 0x22a2bd5d, 0x84c66f09,
+ 0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
+ 0x228a8abd, 0x84bfa46e,
+ 0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
+ 0x227256c8, 0x84b8de94,
+ 0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
+ 0x225a217f, 0x84b21d7a,
+ 0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
+ 0x2241eae3, 0x84ab6122,
+ 0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
+ 0x2229b2f6, 0x84a4a98a,
+ 0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
+ 0x221179b7, 0x849df6b4,
+ 0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
+ 0x21f93f27, 0x849748a0,
+ 0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
+ 0x21e10349, 0x84909f4e,
+ 0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
+ 0x21c8c61c, 0x8489fabe,
+ 0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
+ 0x21b087a1, 0x84835af0,
+ 0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
+ 0x219847da, 0x847cbfe5,
+ 0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
+ 0x218006c8, 0x8476299e,
+ 0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
+ 0x2167c46b, 0x846f9819,
+ 0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
+ 0x214f80c4, 0x84690b58,
+ 0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
+ 0x21373bd4, 0x8462835b,
+ 0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
+ 0x211ef59d, 0x845c0022,
+ 0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
+ 0x2106ae1e, 0x845581ad,
+ 0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
+ 0x20ee655a, 0x844f07fd,
+ 0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
+ 0x20d61b51, 0x84489311,
+ 0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
+ 0x20bdd003, 0x844222eb,
+ 0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
+ 0x20a58373, 0x843bb78a,
+ 0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
+ 0x208d35a0, 0x843550ee,
+ 0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
+ 0x2074e68c, 0x842eef18,
+ 0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
+ 0x205c9638, 0x84289209,
+ 0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
+ 0x204444a4, 0x842239bf,
+ 0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
+ 0x202bf1d2, 0x841be63c,
+ 0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
+ 0x20139dc2, 0x84159780,
+ 0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
+ 0x1ffb4876, 0x840f4d8a,
+ 0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
+ 0x1fe2f1ee, 0x8409085c,
+ 0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
+ 0x1fca9a2b, 0x8402c7f6,
+ 0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
+ 0x1fb2412f, 0x83fc8c57,
+ 0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
+ 0x1f99e6fa, 0x83f65580,
+ 0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
+ 0x1f818b8d, 0x83f02371,
+ 0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
+ 0x1f692ee9, 0x83e9f62b,
+ 0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
+ 0x1f50d10e, 0x83e3cdad,
+ 0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
+ 0x1f3871ff, 0x83dda9f9,
+ 0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
+ 0x1f2011bc, 0x83d78b0d,
+ 0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
+ 0x1f07b045, 0x83d170eb,
+ 0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
+ 0x1eef4d9d, 0x83cb5b93,
+ 0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
+ 0x1ed6e9c3, 0x83c54b04,
+ 0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
+ 0x1ebe84b8, 0x83bf3f3f,
+ 0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
+ 0x1ea61e7e, 0x83b93845,
+ 0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
+ 0x1e8db716, 0x83b33616,
+ 0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
+ 0x1e754e80, 0x83ad38b1,
+ 0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
+ 0x1e5ce4be, 0x83a74017,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
+ 0x1e4479cf, 0x83a14c48,
+ 0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
+ 0x1e2c0db6, 0x839b5d45,
+ 0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
+ 0x1e13a074, 0x8395730e,
+ 0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
+ 0x1dfb3208, 0x838f8da2,
+ 0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
+ 0x1de2c275, 0x8389ad03,
+ 0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
+ 0x1dca51ba, 0x8383d130,
+ 0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
+ 0x1db1dfda, 0x837dfa2a,
+ 0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
+ 0x1d996cd4, 0x837827f0,
+ 0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
+ 0x1d80f8ab, 0x83725a84,
+ 0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
+ 0x1d68835e, 0x836c91e5,
+ 0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
+ 0x1d500cef, 0x8366ce14,
+ 0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
+ 0x1d37955e, 0x83610f10,
+ 0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
+ 0x1d1f1cae, 0x835b54da,
+ 0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
+ 0x1d06a2dd, 0x83559f72,
+ 0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
+ 0x1cee27ef, 0x834feed9,
+ 0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
+ 0x1cd5abe3, 0x834a430e,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
+ 0x1cbd2eba, 0x83449c12,
+ 0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
+ 0x1ca4b075, 0x833ef9e6,
+ 0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
+ 0x1c8c3116, 0x83395c88,
+ 0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
+ 0x1c73b09d, 0x8333c3fa,
+ 0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
+ 0x1c5b2f0c, 0x832e303c,
+ 0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
+ 0x1c42ac62, 0x8328a14d,
+ 0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
+ 0x1c2a28a2, 0x8323172f,
+ 0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
+ 0x1c11a3cb, 0x831d91e1,
+ 0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
+ 0x1bf91de0, 0x83181164,
+ 0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
+ 0x1be096e0, 0x831295b7,
+ 0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
+ 0x1bc80ece, 0x830d1edc,
+ 0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
+ 0x1baf85a9, 0x8307acd1,
+ 0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
+ 0x1b96fb73, 0x83023f98,
+ 0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
+ 0x1b7e702c, 0x82fcd731,
+ 0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
+ 0x1b65e3d7, 0x82f7739c,
+ 0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
+ 0x1b4d5672, 0x82f214d8,
+ 0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
+ 0x1b34c801, 0x82ecbae7,
+ 0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
+ 0x1b1c3883, 0x82e765c8,
+ 0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
+ 0x1b03a7f9, 0x82e2157c,
+ 0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
+ 0x1aeb1665, 0x82dcca02,
+ 0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
+ 0x1ad283c7, 0x82d7835c,
+ 0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
+ 0x1ab9f020, 0x82d24189,
+ 0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
+ 0x1aa15b71, 0x82cd048a,
+ 0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
+ 0x1a88c5bc, 0x82c7cc5e,
+ 0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
+ 0x1a702f01, 0x82c29906,
+ 0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
+ 0x1a579741, 0x82bd6a82,
+ 0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
+ 0x1a3efe7c, 0x82b840d2,
+ 0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
+ 0x1a2664b5, 0x82b31bf7,
+ 0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
+ 0x1a0dc9ec, 0x82adfbf0,
+ 0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
+ 0x19f52e22, 0x82a8e0bf,
+ 0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
+ 0x19dc9157, 0x82a3ca62,
+ 0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
+ 0x19c3f38d, 0x829eb8db,
+ 0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
+ 0x19ab54c5, 0x8299ac29,
+ 0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
+ 0x1992b4ff, 0x8294a44c,
+ 0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
+ 0x197a143e, 0x828fa146,
+ 0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
+ 0x19617280, 0x828aa316,
+ 0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
+ 0x1948cfc8, 0x8285a9bb,
+ 0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
+ 0x19302c17, 0x8280b538,
+ 0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
+ 0x1917876d, 0x827bc58a,
+ 0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
+ 0x18fee1cb, 0x8276dab4,
+ 0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
+ 0x18e63b33, 0x8271f4b5,
+ 0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
+ 0x18cd93a5, 0x826d138d,
+ 0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
+ 0x18b4eb22, 0x8268373c,
+ 0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
+ 0x189c41ab, 0x82635fc2,
+ 0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
+ 0x18839742, 0x825e8d21,
+ 0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
+ 0x186aebe6, 0x8259bf57,
+ 0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
+ 0x18523f9a, 0x8254f666,
+ 0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
+ 0x1839925d, 0x8250324d,
+ 0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
+ 0x1820e431, 0x824b730c,
+ 0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
+ 0x18083518, 0x8246b8a4,
+ 0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
+ 0x17ef8511, 0x82420315,
+ 0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
+ 0x17d6d41d, 0x823d525e,
+ 0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
+ 0x17be223f, 0x8238a681,
+ 0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
+ 0x17a56f76, 0x8233ff7e,
+ 0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
+ 0x178cbbc4, 0x822f5d54,
+ 0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
+ 0x17740729, 0x822ac004,
+ 0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
+ 0x175b51a7, 0x8226278d,
+ 0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
+ 0x17429b3e, 0x822193f1,
+ 0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
+ 0x1729e3f0, 0x821d052f,
+ 0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
+ 0x17112bbd, 0x82187b47,
+ 0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
+ 0x16f872a7, 0x8213f63a,
+ 0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
+ 0x16dfb8ae, 0x820f7608,
+ 0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
+ 0x16c6fdd3, 0x820afab1,
+ 0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
+ 0x16ae4217, 0x82068435,
+ 0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
+ 0x1695857b, 0x82021294,
+ 0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
+ 0x167cc801, 0x81fda5cf,
+ 0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
+ 0x166409a8, 0x81f93de6,
+ 0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
+ 0x164b4a73, 0x81f4dad8,
+ 0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
+ 0x16328a61, 0x81f07ca6,
+ 0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
+ 0x1619c975, 0x81ec2351,
+ 0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
+ 0x160107ae, 0x81e7ced8,
+ 0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
+ 0x15e8450e, 0x81e37f3b,
+ 0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
+ 0x15cf8196, 0x81df347b,
+ 0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
+ 0x15b6bd47, 0x81daee98,
+ 0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
+ 0x159df821, 0x81d6ad92,
+ 0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
+ 0x15853226, 0x81d27169,
+ 0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
+ 0x156c6b57, 0x81ce3a1d,
+ 0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
+ 0x1553a3b4, 0x81ca07af,
+ 0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
+ 0x153adb3f, 0x81c5da1e,
+ 0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
+ 0x152211f8, 0x81c1b16b,
+ 0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
+ 0x150947e1, 0x81bd8d97,
+ 0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
+ 0x14f07cf9, 0x81b96ea0,
+ 0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
+ 0x14d7b144, 0x81b55488,
+ 0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
+ 0x14bee4c0, 0x81b13f4e,
+ 0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
+ 0x14a61770, 0x81ad2ef2,
+ 0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
+ 0x148d4954, 0x81a92376,
+ 0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
+ 0x14747a6d, 0x81a51cd8,
+ 0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
+ 0x145baabd, 0x81a11b1a,
+ 0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
+ 0x1442da43, 0x819d1e3a,
+ 0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
+ 0x142a0902, 0x8199263a,
+ 0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
+ 0x141136f9, 0x8195331a,
+ 0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
+ 0x13f8642a, 0x819144d9,
+ 0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
+ 0x13df9097, 0x818d5b78,
+ 0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
+ 0x13c6bc3f, 0x818976f8,
+ 0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
+ 0x13ade724, 0x81859757,
+ 0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
+ 0x13951146, 0x8181bc96,
+ 0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
+ 0x137c3aa8, 0x817de6b6,
+ 0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
+ 0x13636349, 0x817a15b7,
+ 0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
+ 0x134a8b2b, 0x81764998,
+ 0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
+ 0x1331b24e, 0x8172825a,
+ 0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
+ 0x1318d8b4, 0x816ebffe,
+ 0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
+ 0x12fffe5d, 0x816b0282,
+ 0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
+ 0x12e7234b, 0x816749e8,
+ 0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
+ 0x12ce477f, 0x8163962f,
+ 0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
+ 0x12b56af9, 0x815fe758,
+ 0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
+ 0x129c8dba, 0x815c3d62,
+ 0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
+ 0x1283afc3, 0x8158984e,
+ 0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
+ 0x126ad116, 0x8154f81d,
+ 0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
+ 0x1251f1b3, 0x81515ccd,
+ 0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
+ 0x1239119b, 0x814dc660,
+ 0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
+ 0x122030cf, 0x814a34d6,
+ 0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
+ 0x12074f50, 0x8146a82e,
+ 0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
+ 0x11ee6d20, 0x81432068,
+ 0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
+ 0x11d58a3e, 0x813f9d86,
+ 0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
+ 0x11bca6ad, 0x813c1f86,
+ 0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
+ 0x11a3c26c, 0x8138a66a,
+ 0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
+ 0x118add7d, 0x81353230,
+ 0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
+ 0x1171f7e2, 0x8131c2db,
+ 0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
+ 0x1159119a, 0x812e5868,
+ 0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
+ 0x11402aa6, 0x812af2da,
+ 0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
+ 0x11274309, 0x8127922f,
+ 0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
+ 0x110e5ac2, 0x81243668,
+ 0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
+ 0x10f571d3, 0x8120df85,
+ 0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
+ 0x10dc883c, 0x811d8d86,
+ 0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
+ 0x10c39dff, 0x811a406c,
+ 0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
+ 0x10aab31d, 0x8116f836,
+ 0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
+ 0x1091c796, 0x8113b4e5,
+ 0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
+ 0x1078db6c, 0x81107678,
+ 0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
+ 0x105fee9f, 0x810d3cf0,
+ 0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
+ 0x10470130, 0x810a084d,
+ 0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
+ 0x102e1321, 0x8106d88f,
+ 0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
+ 0x10152472, 0x8103adb6,
+ 0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
+ 0xffc3524, 0x810087c3,
+ 0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
+ 0xfe34539, 0x80fd66b5,
+ 0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
+ 0xfca54b1, 0x80fa4a8c,
+ 0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
+ 0xfb1638d, 0x80f73349,
+ 0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
+ 0xf9871ce, 0x80f420ec,
+ 0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
+ 0xf7f7f75, 0x80f11375,
+ 0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
+ 0xf668c83, 0x80ee0ae4,
+ 0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
+ 0xf4d98f9, 0x80eb0739,
+ 0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
+ 0xf34a4d8, 0x80e80874,
+ 0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
+ 0xf1bb021, 0x80e50e96,
+ 0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
+ 0xf02bad5, 0x80e2199e,
+ 0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
+ 0xee9c4f5, 0x80df298c,
+ 0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
+ 0xed0ce82, 0x80dc3e62,
+ 0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
+ 0xeb7d77c, 0x80d9581e,
+ 0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
+ 0xe9edfe5, 0x80d676c1,
+ 0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
+ 0xe85e7be, 0x80d39a4b,
+ 0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
+ 0xe6cef07, 0x80d0c2bc,
+ 0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
+ 0xe53f5c2, 0x80cdf015,
+ 0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
+ 0xe3afbf0, 0x80cb2255,
+ 0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
+ 0xe220191, 0x80c8597c,
+ 0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
+ 0xe0906a7, 0x80c5958b,
+ 0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
+ 0xdf00b32, 0x80c2d682,
+ 0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
+ 0xdd70f34, 0x80c01c60,
+ 0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
+ 0xdbe12ad, 0x80bd6727,
+ 0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
+ 0xda5159f, 0x80bab6d5,
+ 0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
+ 0xd8c1809, 0x80b80b6c,
+ 0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
+ 0xd7319ee, 0x80b564ea,
+ 0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
+ 0xd5a1b4f, 0x80b2c351,
+ 0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
+ 0xd411c2b, 0x80b026a1,
+ 0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
+ 0xd281c85, 0x80ad8ed9,
+ 0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
+ 0xd0f1c5d, 0x80aafbf9,
+ 0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
+ 0xcf61bb4, 0x80a86e03,
+ 0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
+ 0xcdd1a8b, 0x80a5e4f5,
+ 0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
+ 0xcc418e3, 0x80a360d0,
+ 0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
+ 0xcab16bd, 0x80a0e194,
+ 0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
+ 0xc92141a, 0x809e6741,
+ 0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
+ 0xc7910fb, 0x809bf1d7,
+ 0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
+ 0xc600d61, 0x80998157,
+ 0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
+ 0xc47094d, 0x809715c0,
+ 0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
+ 0xc2e04c0, 0x8094af13,
+ 0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
+ 0xc14ffba, 0x80924d4f,
+ 0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
+ 0xbfbfa3d, 0x808ff074,
+ 0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
+ 0xbe2f44a, 0x808d9884,
+ 0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
+ 0xbc9ede2, 0x808b457d,
+ 0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
+ 0xbb0e705, 0x8088f761,
+ 0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
+ 0xb97dfb5, 0x8086ae2e,
+ 0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
+ 0xb7ed7f2, 0x808469e5,
+ 0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
+ 0xb65cfbe, 0x80822a87,
+ 0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
+ 0xb4cc719, 0x807ff013,
+ 0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
+ 0xb33be05, 0x807dba89,
+ 0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
+ 0xb1ab483, 0x807b89ea,
+ 0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
+ 0xb01aa92, 0x80795e36,
+ 0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
+ 0xae8a036, 0x8077376c,
+ 0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
+ 0xacf956d, 0x8075158c,
+ 0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
+ 0xab68a3a, 0x8072f898,
+ 0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
+ 0xa9d7e9d, 0x8070e08e,
+ 0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
+ 0xa847297, 0x806ecd6f,
+ 0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
+ 0xa6b662a, 0x806cbf3c,
+ 0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
+ 0xa525955, 0x806ab5f3,
+ 0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
+ 0xa394c1b, 0x8068b196,
+ 0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
+ 0xa203e7c, 0x8066b224,
+ 0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
+ 0xa073079, 0x8064b79d,
+ 0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
+ 0x9ee2213, 0x8062c202,
+ 0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
+ 0x9d5134b, 0x8060d152,
+ 0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
+ 0x9bc0421, 0x805ee58e,
+ 0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
+ 0x9a2f498, 0x805cfeb5,
+ 0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
+ 0x989e4b0, 0x805b1cc8,
+ 0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
+ 0x970d46a, 0x80593fc7,
+ 0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
+ 0x957c3c6, 0x805767b2,
+ 0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
+ 0x93eb2c6, 0x80559489,
+ 0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
+ 0x925a16b, 0x8053c64c,
+ 0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
+ 0x90c8fb6, 0x8051fcfb,
+ 0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
+ 0x8f37da7, 0x80503896,
+ 0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
+ 0x8da6b40, 0x804e791d,
+ 0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
+ 0x8c15882, 0x804cbe90,
+ 0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
+ 0x8a8456d, 0x804b08f0,
+ 0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
+ 0x88f3203, 0x8049583d,
+ 0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
+ 0x8761e44, 0x8047ac75,
+ 0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
+ 0x85d0a32, 0x8046059b,
+ 0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
+ 0x843f5cd, 0x804463ad,
+ 0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
+ 0x82ae117, 0x8042c6ab,
+ 0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
+ 0x811cc10, 0x80412e96,
+ 0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
+ 0x7f8b6b9, 0x803f9b6f,
+ 0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
+ 0x7dfa114, 0x803e0d34,
+ 0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
+ 0x7c68b21, 0x803c83e5,
+ 0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
+ 0x7ad74e1, 0x803aff84,
+ 0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
+ 0x7945e56, 0x80398010,
+ 0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
+ 0x77b4780, 0x80380589,
+ 0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
+ 0x762305f, 0x80368fef,
+ 0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
+ 0x74918f6, 0x80351f43,
+ 0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
+ 0x7300145, 0x8033b383,
+ 0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
+ 0x716e94e, 0x80324cb1,
+ 0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
+ 0x6fdd110, 0x8030eacd,
+ 0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
+ 0x6e4b88d, 0x802f8dd5,
+ 0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
+ 0x6cb9fc6, 0x802e35cb,
+ 0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
+ 0x6b286bc, 0x802ce2af,
+ 0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
+ 0x6996d70, 0x802b9480,
+ 0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
+ 0x68053e3, 0x802a4b3f,
+ 0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
+ 0x6673a16, 0x802906ec,
+ 0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
+ 0x64e2009, 0x8027c786,
+ 0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
+ 0x63505be, 0x80268d0e,
+ 0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
+ 0x61beb36, 0x80255784,
+ 0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
+ 0x602d072, 0x802426e8,
+ 0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
+ 0x5e9b572, 0x8022fb3a,
+ 0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
+ 0x5d09a38, 0x8021d47a,
+ 0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
+ 0x5b77ec5, 0x8020b2a7,
+ 0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
+ 0x59e6319, 0x801f95c3,
+ 0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
+ 0x5854736, 0x801e7dcd,
+ 0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
+ 0x56c2b1c, 0x801d6ac5,
+ 0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
+ 0x5530ecd, 0x801c5cab,
+ 0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
+ 0x539f249, 0x801b537f,
+ 0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
+ 0x520d592, 0x801a4f42,
+ 0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
+ 0x507b8a8, 0x80194ff3,
+ 0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
+ 0x4ee9b8c, 0x80185592,
+ 0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
+ 0x4d57e40, 0x80176020,
+ 0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
+ 0x4bc60c4, 0x80166f9c,
+ 0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
+ 0x4a34319, 0x80158406,
+ 0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
+ 0x48a2540, 0x80149d5f,
+ 0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
+ 0x471073b, 0x8013bba7,
+ 0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
+ 0x457e90a, 0x8012dedd,
+ 0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
+ 0x43ecaae, 0x80120701,
+ 0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
+ 0x425ac28, 0x80113414,
+ 0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
+ 0x40c8d79, 0x80106616,
+ 0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
+ 0x3f36ea2, 0x800f9d07,
+ 0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
+ 0x3da4fa4, 0x800ed8e6,
+ 0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
+ 0x3c13080, 0x800e19b4,
+ 0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
+ 0x3a81137, 0x800d5f71,
+ 0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
+ 0x38ef1ca, 0x800caa1c,
+ 0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
+ 0x375d23a, 0x800bf9b7,
+ 0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
+ 0x35cb288, 0x800b4e40,
+ 0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
+ 0x34392b4, 0x800aa7b8,
+ 0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
+ 0x32a72c1, 0x800a061f,
+ 0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
+ 0x31152ae, 0x80096975,
+ 0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
+ 0x2f8327d, 0x8008d1ba,
+ 0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
+ 0x2df122e, 0x80083eed,
+ 0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
+ 0x2c5f1c3, 0x8007b110,
+ 0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
+ 0x2acd13d, 0x80072822,
+ 0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
+ 0x293b09c, 0x8006a423,
+ 0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
+ 0x27a8fe2, 0x80062513,
+ 0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
+ 0x2616f10, 0x8005aaf2,
+ 0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
+ 0x2484e26, 0x800535c0,
+ 0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
+ 0x22f2d25, 0x8004c57d,
+ 0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
+ 0x2160c0f, 0x80045a29,
+ 0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
+ 0x1fceae4, 0x8003f3c5,
+ 0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
+ 0x1e3c9a6, 0x8003924f,
+ 0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
+ 0x1caa855, 0x800335c9,
+ 0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
+ 0x1b186f3, 0x8002de32,
+ 0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
+ 0x198657f, 0x80028b8a,
+ 0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
+ 0x17f43fc, 0x80023dd2,
+ 0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
+ 0x166226a, 0x8001f508,
+ 0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
+ 0x14d00ca, 0x8001b12e,
+ 0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
+ 0x133df1e, 0x80017243,
+ 0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
+ 0x11abd66, 0x80013847,
+ 0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
+ 0x1019ba2, 0x8001033b,
+ 0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
+ 0x8000d31e,
+ 0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
+ 0x8000a7f0,
+ 0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
+ 0x800081b1,
+ 0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
+ 0x80006062,
+ 0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
+ 0x80004402,
+ 0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
+ 0x80002c91,
+ 0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
+ 0x80001a10,
+ 0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
+ 0x80000c7e,
+ 0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
+ 0x800003db,
+ 0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
+ 0x80000027,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+ 0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+ 0x7f97cebd, 0x7f754e80,
+ 0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+ 0x7dfa98a8, 0x7db0fdf8,
+ 0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+ 0x7b26cb4f, 0x7ab6cba4,
+ 0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+ 0x77235f2d, 0x768e0ea6,
+ 0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+ 0x71fa3949, 0x71410805,
+ 0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+ 0x6bb812d1, 0x6adcc964,
+ 0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+ 0x646c59bf, 0x637114cc,
+ 0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+ 0x5c290acc, 0x5b1035cf,
+ 0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+ 0x53028518, 0x51ced46e,
+ 0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+ 0x490f57ee, 0x47c3c22f,
+ 0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+ 0x3e680b2c, 0x3d07c1d6,
+ 0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+ 0x3326e2c3, 0x31b54a5e,
+ 0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+ 0x27679df4, 0x25e845b6,
+ 0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+ 0x1b4732ef, 0x19bdcbf3,
+ 0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+ 0xee38766, 0xd53db92,
+ 0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+ 0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+ 0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+ 0x7ff97c18, 0x7ff75370,
+ 0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+ 0x7fdf9508, 0x7fdaf519,
+ 0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+ 0x7fb1f5fc, 0x7faadf7c,
+ 0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+ 0x7f70a5fe, 0x7f671a05,
+ 0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+ 0x7f1baf1e, 0x7f0faf25,
+ 0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+ 0x7eb31e78, 0x7ea4ac58,
+ 0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+ 0x7e37042a, 0x7e26221f,
+ 0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+ 0x7da77359, 0x7d9423fc,
+ 0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+ 0x7d048228, 0x7ceec873,
+ 0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+ 0x7c4e49b7, 0x7c362904,
+ 0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+ 0x7b84e61f, 0x7b6a6227,
+ 0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+ 0x7aa8766f, 0x7a8b9348,
+ 0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+ 0x79b91ca4, 0x7999dec4,
+ 0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+ 0x78b6fda8, 0x789569df,
+ 0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+ 0x77a24148, 0x777e5cc3,
+ 0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+ 0x767b1231, 0x7654e279,
+ 0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+ 0x75419de7, 0x751928e0,
+ 0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+ 0x73f614c0, 0x73cb60a8,
+ 0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+ 0x7298a9dd, 0x726bbd48,
+ 0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+ 0x7129931f, 0x70fa74fc,
+ 0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+ 0x6fa90921, 0x6f77c0b3,
+ 0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+ 0x6e174730, 0x6de3dc11,
+ 0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+ 0x6c748b3f, 0x6c3f055d,
+ 0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+ 0x6ac115e2, 0x6a897d7d,
+ 0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+ 0x68fd2a3d, 0x68c387e9,
+ 0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+ 0x67290e02, 0x66ed6aa1,
+ 0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+ 0x6545095f, 0x65076e25,
+ 0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+ 0x635166f9, 0x6311dd64,
+ 0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+ 0x614e73da, 0x610d05b7,
+ 0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+ 0x5f3c7f6b, 0x5ef936d1,
+ 0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+ 0x5d1bdb65, 0x5cd6c2b5,
+ 0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+ 0x5aecdbc5, 0x5aa5fda5,
+ 0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+ 0x58afd6bd, 0x58673e1b,
+ 0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+ 0x566524aa, 0x561adcb9,
+ 0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+ 0x540d2005, 0x53c13439,
+ 0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+ 0x51a82555, 0x515aa162,
+ 0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+ 0x4f369320, 0x4ee782fb,
+ 0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+ 0x4cb8c9dd, 0x4c6839b7,
+ 0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+ 0x4a2f2be6, 0x49dd282a,
+ 0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+ 0x479a1d67, 0x4746b2bc,
+ 0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+ 0x44fa0450, 0x44a53f93,
+ 0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+ 0x424f4845, 0x41f93689,
+ 0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+ 0x3f9a5290, 0x3f430119,
+ 0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+ 0x3cdb8e09, 0x3c830a50,
+ 0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+ 0x3a136712, 0x39b9bebc,
+ 0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+ 0x37424b7b, 0x36e78c5b,
+ 0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+ 0x3468aa76, 0x340ce28b,
+ 0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+ 0x3186f487, 0x312a31f8,
+ 0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+ 0x2e9d9b70, 0x2e3fec8b,
+ 0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+ 0x2bad1221, 0x2b4e8558,
+ 0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+ 0x28b5cca5, 0x2856708d,
+ 0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+ 0x25b84012, 0x2558235f,
+ 0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+ 0x22b4e274, 0x225413f8,
+ 0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+ 0x1fac2abf, 0x1f4ab968,
+ 0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+ 0x1c9e90b8, 0x1c3c8b8c,
+ 0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+ 0x198c8ce7, 0x192a0304,
+ 0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+ 0x1676987f, 0x16139918,
+ 0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+ 0x135d2d53, 0x12f9c7aa,
+ 0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+ 0x1040c5bb, 0xfdd0926,
+ 0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+ 0xcbdd865,
+ 0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+ 0x99cb0a7,
+ 0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+ 0x67a0d76,
+ 0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+ 0x3566a96,
+ 0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+ 0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+ 0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+ 0x7fff97c1, 0x7fff7536,
+ 0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+ 0x7ffdf93c, 0x7ffdaf37,
+ 0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+ 0x7ffb1ee9, 0x7ffaad6a,
+ 0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+ 0x7ff708ce, 0x7ff66fd7,
+ 0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+ 0x7ff1b6f6, 0x7ff0f688,
+ 0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+ 0x7feb296d, 0x7fea418b,
+ 0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+ 0x7fe36045, 0x7fe250ef,
+ 0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+ 0x7fda5b8f, 0x7fd924ca,
+ 0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+ 0x7fd01b63, 0x7fcebd31,
+ 0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+ 0x7fc49fda, 0x7fc31a3d,
+ 0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+ 0x7fb7e90f, 0x7fb63c0d,
+ 0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+ 0x7fa9f723, 0x7fa822bf,
+ 0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+ 0x7f9aca37, 0x7f98ce76,
+ 0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+ 0x7f8a6272, 0x7f883f58,
+ 0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+ 0x7f78bffb, 0x7f76758e,
+ 0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+ 0x7f65e2ff, 0x7f637144,
+ 0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+ 0x7f51cbab, 0x7f4f32a9,
+ 0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+ 0x7f3c7a31, 0x7f39b9ee,
+ 0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+ 0x7f25eec7, 0x7f230749,
+ 0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+ 0x7f0e29a3, 0x7f0b1af2,
+ 0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+ 0x7ef52b00, 0x7ef1f524,
+ 0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+ 0x7edaf31c, 0x7ed7961c,
+ 0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+ 0x7ebf8237, 0x7ebbfe1c,
+ 0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+ 0x7ea2d896, 0x7e9f2d68,
+ 0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+ 0x7e84f67e, 0x7e812447,
+ 0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+ 0x7e65dc3b, 0x7e61e303,
+ 0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+ 0x7e458a17, 0x7e4169e9,
+ 0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+ 0x7e240064, 0x7e1fb94a,
+ 0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+ 0x7e013f74, 0x7dfcd178,
+ 0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+ 0x7ddd479d, 0x7dd8b2ca,
+ 0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+ 0x7db81936, 0x7db35d98,
+ 0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+ 0x7d91b49e, 0x7d8cd240,
+ 0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+ 0x7d6a1a31, 0x7d65111f,
+ 0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+ 0x7d414a51, 0x7d3c1a98,
+ 0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+ 0x7d174564, 0x7d11ef11,
+ 0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+ 0x7cec0bd1, 0x7ce68ef0,
+ 0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+ 0x7cbf9e03, 0x7cb9faa2,
+ 0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+ 0x7c91fc66, 0x7c8c3294,
+ 0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+ 0x7c63276d, 0x7c5d3737,
+ 0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+ 0x7c331f8a, 0x7c2d08ff,
+ 0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+ 0x7c01e534, 0x7bfba863,
+ 0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+ 0x7bcf78e5, 0x7bc915dd,
+ 0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+ 0x7b9bdb18, 0x7b9551ea,
+ 0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+ 0x7b670c4d, 0x7b605d09,
+ 0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+ 0x7b310d07, 0x7b2a37bc,
+ 0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+ 0x7af9ddcb, 0x7af2e28b,
+ 0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+ 0x7ac17f20, 0x7aba5dfc,
+ 0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+ 0x7a87f192, 0x7a80aa9c,
+ 0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+ 0x7a4d35b0, 0x7a45c8f9,
+ 0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+ 0x7a114c09, 0x7a09b9a4,
+ 0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+ 0x79d43532, 0x79cc7d31,
+ 0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+ 0x7995f1c1, 0x798e1438,
+ 0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+ 0x79568250, 0x794e7f52,
+ 0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+ 0x7915e77c, 0x790dbf1d,
+ 0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+ 0x78d421e4, 0x78cbd437,
+ 0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+ 0x7891322a, 0x7888bf45,
+ 0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+ 0x784d18f4, 0x784480ea,
+ 0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+ 0x7807d6e9, 0x77ff19d1,
+ 0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+ 0x77c16cb4, 0x77b88aa3,
+ 0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+ 0x7779db03, 0x7770d40f,
+ 0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+ 0x77312287, 0x7727f6c6,
+ 0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+ 0x76e743f4, 0x76ddf37c,
+ 0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+ 0x769c3ffe, 0x7692cae8,
+ 0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+ 0x76501760, 0x76467dc2,
+ 0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+ 0x7602cad5, 0x75f90cc7,
+ 0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+ 0x75b45b1d, 0x75aa78b6,
+ 0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+ 0x7564c8f8, 0x755ac251,
+ 0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+ 0x7514152b, 0x7509ea5d,
+ 0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+ 0x74c2407d, 0x74b7f1a1,
+ 0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+ 0x746f4bb8, 0x7464d8e8,
+ 0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+ 0x741b37a9, 0x7410a0fe,
+ 0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+ 0x73c6051f, 0x73bb4ab3,
+ 0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+ 0x736fb4ec, 0x7364d6da,
+ 0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+ 0x731847e5, 0x730d4648,
+ 0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+ 0x72bfbee3, 0x72b499d6,
+ 0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+ 0x72661abf, 0x725ad25d,
+ 0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+ 0x720b5c57, 0x71fff0bc,
+ 0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+ 0x71af848a, 0x71a3f5d2,
+ 0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+ 0x7152943b, 0x7146e284,
+ 0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+ 0x70f48c50, 0x70e8b7b5,
+ 0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+ 0x70956db1, 0x70897650,
+ 0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+ 0x70353947, 0x70291f3e,
+ 0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+ 0x6fd3f001, 0x6fc7b36d,
+ 0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+ 0x6f7192cf, 0x6f6533ce,
+ 0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+ 0x6f0e22a3, 0x6f01a155,
+ 0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+ 0x6ea9a073, 0x6e9cfcf5,
+ 0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+ 0x6e440d37, 0x6e3747a9,
+ 0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+ 0x6ddd69e9, 0x6dd0826a,
+ 0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+ 0x6d75b786, 0x6d68ae37,
+ 0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+ 0x6d0cf70f, 0x6cffcc0f,
+ 0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+ 0x6ca32985, 0x6c95dcf6,
+ 0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+ 0x6c384fef, 0x6c2ae1f0,
+ 0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+ 0x6bcc6b53, 0x6bbedc06,
+ 0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+ 0x6b5f7cbc, 0x6b51cc42,
+ 0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+ 0x6af18536, 0x6ae3b3b2,
+ 0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+ 0x6a8285d1, 0x6a749365,
+ 0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+ 0x6a127f9f, 0x6a046c6c,
+ 0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+ 0x69a173b5, 0x69933fde,
+ 0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+ 0x692f6328, 0x69210ed1,
+ 0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+ 0x68bc4f13, 0x68adda5f,
+ 0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+ 0x68483891, 0x6839a3a4,
+ 0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+ 0x67d320c1, 0x67c46bbe,
+ 0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+ 0x675d08c4, 0x674e33d0,
+ 0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+ 0x66e5f1be, 0x66d6fcfd,
+ 0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+ 0x666ddcd3, 0x665ec86b,
+ 0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+ 0x65f4cb2d, 0x65e59742,
+ 0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+ 0x657abdf6, 0x656b6aae,
+ 0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+ 0x64ffb65b, 0x64f043dc,
+ 0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+ 0x6483b58c, 0x647423fb,
+ 0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+ 0x6406bcba, 0x63f70c3f,
+ 0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+ 0x6388cd1b, 0x6378fddc,
+ 0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+ 0x6309e7e4, 0x62f9fa09,
+ 0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+ 0x628a0e50, 0x627a01fe,
+ 0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+ 0x62094199, 0x61f916f9,
+ 0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+ 0x618782fd, 0x61773a37,
+ 0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+ 0x6104d3bc, 0x60f46cf9,
+ 0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+ 0x60813519, 0x6070b080,
+ 0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+ 0x5ffca859, 0x5fec0613,
+ 0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+ 0x5f772ec2, 0x5f666ef9,
+ 0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+ 0x5ef0c99f, 0x5edfec7b,
+ 0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+ 0x5e697a39, 0x5e587fe5,
+ 0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+ 0x5de141e1, 0x5dd02a85,
+ 0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+ 0x5d5821e4, 0x5d46edac,
+ 0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+ 0x5cce1b97, 0x5cbccaac,
+ 0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+ 0x5c43304d, 0x5c31c2db,
+ 0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+ 0x5bb7615d, 0x5ba5d78e,
+ 0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+ 0x5b2ab020, 0x5b190a20,
+ 0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+ 0x5a9d1df1, 0x5a8b5bec,
+ 0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+ 0x5a0eac2e, 0x59fcce4f,
+ 0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+ 0x597f5c36, 0x596d62a9,
+ 0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+ 0x58ef2f6b, 0x58dd1a5d,
+ 0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+ 0x585e2730, 0x584bf6cd,
+ 0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+ 0x57cc44ec, 0x57b9f960,
+ 0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+ 0x57398a05, 0x5727237f,
+ 0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+ 0x56a5f7e7, 0x56937694,
+ 0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+ 0x56118ffe, 0x55fef40a,
+ 0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+ 0x557c53b6, 0x55699d51,
+ 0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+ 0x54e64482, 0x54d373d9,
+ 0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+ 0x544f63d2, 0x543c7914,
+ 0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+ 0x53b7b31c, 0x53a4ae77,
+ 0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+ 0x531f33d5, 0x530c1579,
+ 0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+ 0x5285e777, 0x5272af92,
+ 0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+ 0x51ebcf7a, 0x51d87e3c,
+ 0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+ 0x5150ed5c, 0x513d82f4,
+ 0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+ 0x50b5429a, 0x50a1bf39,
+ 0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+ 0x5018d0b4, 0x5005348a,
+ 0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+ 0x4f7b992d, 0x4f67e46a,
+ 0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+ 0x4edd9d89, 0x4ec9d05e,
+ 0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+ 0x4e3edf4d, 0x4e2af9ea,
+ 0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+ 0x4d9f6001, 0x4d8b6298,
+ 0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+ 0x4cff212e, 0x4ceb0bf0,
+ 0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+ 0x4c5e2460, 0x4c49f77f,
+ 0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+ 0x4bbc6b25, 0x4ba826d1,
+ 0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+ 0x4b19f70a, 0x4b059b77,
+ 0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+ 0x4a76c9a2, 0x4a625701,
+ 0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+ 0x49d2e47e, 0x49be5b02,
+ 0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+ 0x492e4933, 0x4919a90f,
+ 0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+ 0x4888f957, 0x487442be,
+ 0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+ 0x47e2f682, 0x47ce29a7,
+ 0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+ 0x473c424e, 0x47275f63,
+ 0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+ 0x4694de56, 0x467fe590,
+ 0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+ 0x45eccc37, 0x45d7bdc9,
+ 0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+ 0x45440d90, 0x452ee9ae,
+ 0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+ 0x449aa400, 0x44856adf,
+ 0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+ 0x43f0912b, 0x43db42fe,
+ 0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+ 0x4345d6b3, 0x433073b0,
+ 0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+ 0x429a763f, 0x4284fe99,
+ 0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+ 0x41ee7174, 0x41d8e561,
+ 0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+ 0x4141c9fb, 0x412c29b1,
+ 0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+ 0x4094817f, 0x407ecd32,
+ 0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+ 0x3fe699aa, 0x3fd0d191,
+ 0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+ 0x3f38142a, 0x3f22387a,
+ 0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+ 0x3e88f2ae, 0x3e73039d,
+ 0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+ 0x3dd936e6, 0x3dc334a9,
+ 0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+ 0x3d28e282, 0x3d12cd51,
+ 0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+ 0x3c77f737, 0x3c61cf48,
+ 0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+ 0x3bc676b9, 0x3bb03c42,
+ 0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+ 0x3b1462be, 0x3afe15f6,
+ 0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+ 0x3a61bcfd, 0x3a4b5e1b,
+ 0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+ 0x39ae872f, 0x3998166a,
+ 0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+ 0x38fac30e, 0x38e4409e,
+ 0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+ 0x38467255, 0x382fde72,
+ 0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+ 0x379196c3, 0x377af1a3,
+ 0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+ 0x36dc3214, 0x36c57bf0,
+ 0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+ 0x36264609, 0x360f7f19,
+ 0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+ 0x356fd461, 0x3558fcde,
+ 0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+ 0x34b8dee1, 0x34a1f702,
+ 0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+ 0x3401674a, 0x33ea6f48,
+ 0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+ 0x33496f62, 0x33326776,
+ 0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+ 0x3290f8ef, 0x3279e151,
+ 0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+ 0x31d805b7, 0x31c0dea1,
+ 0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+ 0x311e9783, 0x3107612e,
+ 0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+ 0x3064b01d, 0x304d6ac1,
+ 0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+ 0x2faa514f, 0x2f92fd26,
+ 0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+ 0x2eef7ce5, 0x2ed81a29,
+ 0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+ 0x2e3434ac, 0x2e1cc397,
+ 0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+ 0x2d787a72, 0x2d60fb3e,
+ 0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+ 0x2cbc5006, 0x2ca4c2ed,
+ 0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+ 0x2bffb73a, 0x2be81c74,
+ 0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+ 0x2b42b1dd, 0x2b2b09a6,
+ 0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+ 0x2a8541c3, 0x2a6d8c55,
+ 0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+ 0x29c768be, 0x29afa654,
+ 0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+ 0x290928a3, 0x28f15978,
+ 0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+ 0x284a8349, 0x2832a796,
+ 0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+ 0x278b7a84, 0x27739285,
+ 0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+ 0x26cc102d, 0x26b41c1d,
+ 0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+ 0x260c461b, 0x25f44635,
+ 0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+ 0x254c1e28, 0x253412a8,
+ 0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+ 0x248b9a2f, 0x2473834f,
+ 0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+ 0x23cabc09, 0x23b29a05,
+ 0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+ 0x23098593, 0x22f158a7,
+ 0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+ 0x2247f8aa, 0x222fc111,
+ 0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+ 0x2186172b, 0x216dd521,
+ 0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+ 0x20c3e2f5, 0x20ab96b5,
+ 0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+ 0x20015de7, 0x1fe907ae,
+ 0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+ 0x1f3e89e0, 0x1f2629ea,
+ 0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+ 0x1e7b68c2, 0x1e62ff4a,
+ 0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+ 0x1db7fc6d, 0x1d9f89b1,
+ 0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+ 0x1cf446c5, 0x1cdbcb00,
+ 0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+ 0x1c3049ac, 0x1c17c51b,
+ 0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+ 0x1b6c0705, 0x1b5379e5,
+ 0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+ 0x1aa780b6, 0x1a8eeb42,
+ 0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+ 0x19e2b8a2, 0x19ca1b17,
+ 0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+ 0x191db0af, 0x19050b4b,
+ 0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+ 0x18586ac3, 0x183fbdc3,
+ 0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+ 0x1792e8c6, 0x177a3466,
+ 0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+ 0x16cd2c9f, 0x16b4711b,
+ 0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+ 0x16073834, 0x15ee75cb,
+ 0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+ 0x15410d70, 0x1528445d,
+ 0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+ 0x147aae3a, 0x1461debc,
+ 0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+ 0x13b41c7d, 0x139b46d0,
+ 0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+ 0x12ed5a21, 0x12d47e83,
+ 0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+ 0x12266913, 0x120d87c1,
+ 0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+ 0x115f4b3c, 0x11466473,
+ 0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+ 0x10980287, 0x107f1686,
+ 0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+ 0xfd090e1, 0xfb79fe4,
+ 0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+ 0xef0027b,
+ 0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+ 0xe284036,
+ 0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+ 0xd605b03,
+ 0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+ 0xc9854cf,
+ 0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+ 0xbd02f87,
+ 0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+ 0xb07ed19,
+ 0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+ 0xa3f8f73,
+ 0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+ 0x9771884,
+ 0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+ 0x8ae8a3a,
+ 0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+ 0x7e5e685,
+ 0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+ 0x71d2f52,
+ 0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+ 0x6546692,
+ 0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+ 0x58b8e34,
+ 0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+ 0x4c2a827,
+ 0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+ 0x3f9b65b,
+ 0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+ 0x330bac1,
+ 0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+ 0x267b747,
+ 0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+ 0x19eaddd,
+ 0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+ 0xd5a075,
+ 0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+ 0xc90fe,
+
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+ 0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
+ 0x7ffff97c, 0x7ffff753,
+ 0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
+ 0x7fffdf94, 0x7fffdaf3,
+ 0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
+ 0x7fffb1ee, 0x7fffaad6,
+ 0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
+ 0x7fff708b, 0x7fff66fc,
+ 0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
+ 0x7fff1b6b, 0x7fff0f64,
+ 0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
+ 0x7ffeb28e, 0x7ffea40f,
+ 0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
+ 0x7ffe35f4, 0x7ffe24fe,
+ 0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
+ 0x7ffda59d, 0x7ffd922f,
+ 0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
+ 0x7ffd0189, 0x7ffceba4,
+ 0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
+ 0x7ffc49b9, 0x7ffc315b,
+ 0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
+ 0x7ffb7e2b, 0x7ffb6356,
+ 0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
+ 0x7ffa9ee2, 0x7ffa8195,
+ 0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
+ 0x7ff9abdb, 0x7ff98c17,
+ 0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
+ 0x7ff8a519, 0x7ff882dd,
+ 0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
+ 0x7ff78a9a, 0x7ff765e7,
+ 0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
+ 0x7ff65c5f, 0x7ff63535,
+ 0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
+ 0x7ff51a69, 0x7ff4f0c7,
+ 0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
+ 0x7ff3c4b7, 0x7ff3989e,
+ 0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
+ 0x7ff25b4a, 0x7ff22cb9,
+ 0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
+ 0x7ff0de22, 0x7ff0ad19,
+ 0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
+ 0x7fef4d3e, 0x7fef19bf,
+ 0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
+ 0x7feda8a0, 0x7fed72aa,
+ 0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
+ 0x7febf048, 0x7febb7da,
+ 0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
+ 0x7fea2436, 0x7fe9e950,
+ 0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
+ 0x7fe84469, 0x7fe8070d,
+ 0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
+ 0x7fe650e3, 0x7fe61110,
+ 0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
+ 0x7fe449a4, 0x7fe40759,
+ 0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
+ 0x7fe22eac, 0x7fe1e9ea,
+ 0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
+ 0x7fdffffb, 0x7fdfb8c2,
+ 0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
+ 0x7fddbd92, 0x7fdd73e2,
+ 0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
+ 0x7fdb6771, 0x7fdb1b4a,
+ 0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
+ 0x7fd8fd98, 0x7fd8aefa,
+ 0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
+ 0x7fd68009, 0x7fd62ef4,
+ 0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
+ 0x7fd3eec2, 0x7fd39b36,
+ 0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
+ 0x7fd149c5, 0x7fd0f3c2,
+ 0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
+ 0x7fce9112, 0x7fce3898,
+ 0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
+ 0x7fcbc4a9, 0x7fcb69b9,
+ 0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
+ 0x7fc8e48b, 0x7fc88724,
+ 0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
+ 0x7fc5f0b8, 0x7fc590db,
+ 0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
+ 0x7fc2e931, 0x7fc286de,
+ 0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
+ 0x7fbfcdf6, 0x7fbf692c,
+ 0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
+ 0x7fbc9f08, 0x7fbc37c8,
+ 0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
+ 0x7fb95c67, 0x7fb8f2b0,
+ 0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
+ 0x7fb60614, 0x7fb599e7,
+ 0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
+ 0x7fb29c0f, 0x7fb22d6c,
+ 0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
+ 0x7faf1e58, 0x7faead3f,
+ 0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
+ 0x7fab8cf1, 0x7fab1962,
+ 0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
+ 0x7fa7e7d9, 0x7fa771d4,
+ 0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
+ 0x7fa42f12, 0x7fa3b697,
+ 0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
+ 0x7fa0629c, 0x7f9fe7ab,
+ 0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
+ 0x7f9c8278, 0x7f9c0511,
+ 0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
+ 0x7f988ea5, 0x7f980ec8,
+ 0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
+ 0x7f948725, 0x7f9404d3,
+ 0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
+ 0x7f906bf9, 0x7f8fe731,
+ 0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
+ 0x7f8c3d20, 0x7f8bb5e3,
+ 0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
+ 0x7f87fa9c, 0x7f8770ea,
+ 0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
+ 0x7f83a46e, 0x7f831846,
+ 0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
+ 0x7f7f3a95, 0x7f7eabf8,
+ 0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
+ 0x7f7abd13, 0x7f7a2c01,
+ 0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
+ 0x7f762be8, 0x7f759861,
+ 0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
+ 0x7f718715, 0x7f70f119,
+ 0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
+ 0x7f6cce9b, 0x7f6c362a,
+ 0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
+ 0x7f68027b, 0x7f676795,
+ 0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
+ 0x7f6322b4, 0x7f62855a,
+ 0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
+ 0x7f5e2f49, 0x7f5d8f7a,
+ 0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
+ 0x7f592839, 0x7f5885f6,
+ 0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
+ 0x7f540d86, 0x7f5368ce,
+ 0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
+ 0x7f4edf30, 0x7f4e3804,
+ 0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
+ 0x7f499d38, 0x7f48f398,
+ 0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
+ 0x7f44479f, 0x7f439b8b,
+ 0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
+ 0x7f3ede66, 0x7f3e2fde,
+ 0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
+ 0x7f39618e, 0x7f38b091,
+ 0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
+ 0x7f33d116, 0x7f331da6,
+ 0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
+ 0x7f2e2d01, 0x7f2d771e,
+ 0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
+ 0x7f28754f, 0x7f27bcf8,
+ 0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
+ 0x7f22aa01, 0x7f21ef37,
+ 0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
+ 0x7f1ccb18, 0x7f1c0dda,
+ 0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
+ 0x7f16d895, 0x7f1618e4,
+ 0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
+ 0x7f10d279, 0x7f101054,
+ 0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
+ 0x7f0ab8c4, 0x7f09f42d,
+ 0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
+ 0x7f048b78, 0x7f03c46d,
+ 0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
+ 0x7efe4a95, 0x7efd8118,
+ 0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
+ 0x7ef7f61d, 0x7ef72a2d,
+ 0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
+ 0x7ef18e10, 0x7ef0bfae,
+ 0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
+ 0x7eeb1270, 0x7eea419b,
+ 0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
+ 0x7ee4833d, 0x7ee3aff6,
+ 0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
+ 0x7edde079, 0x7edd0ac0,
+ 0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
+ 0x7ed72a24, 0x7ed651f9,
+ 0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
+ 0x7ed0603f, 0x7ecf85a3,
+ 0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
+ 0x7ec982cd, 0x7ec8a5bf,
+ 0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
+ 0x7ec291cd, 0x7ec1b24d,
+ 0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
+ 0x7ebb8d40, 0x7ebaab4f,
+ 0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
+ 0x7eb47529, 0x7eb390c6,
+ 0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
+ 0x7ead4987, 0x7eac62b3,
+ 0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
+ 0x7ea60a5d, 0x7ea52118,
+ 0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
+ 0x7e9eb7aa, 0x7e9dcbf4,
+ 0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
+ 0x7e975171, 0x7e96634a,
+ 0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
+ 0x7e8fd7b2, 0x7e8ee71b,
+ 0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
+ 0x7e884a6f, 0x7e875767,
+ 0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
+ 0x7e80a9a8, 0x7e7fb430,
+ 0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
+ 0x7e78f55f, 0x7e77fd77,
+ 0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
+ 0x7e712d96, 0x7e70333d,
+ 0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
+ 0x7e69524c, 0x7e685584,
+ 0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
+ 0x7e616384, 0x7e60644c,
+ 0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
+ 0x7e59613f, 0x7e585f97,
+ 0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
+ 0x7e514b7e, 0x7e504767,
+ 0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
+ 0x7e492241, 0x7e481bbb,
+ 0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
+ 0x7e40e58c, 0x7e3fdc97,
+ 0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
+ 0x7e38955e, 0x7e3789fa,
+ 0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
+ 0x7e3031b9, 0x7e2f23e6,
+ 0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
+ 0x7e27ba9e, 0x7e26aa5d,
+ 0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
+ 0x7e1f300f, 0x7e1e1d5f,
+ 0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
+ 0x7e16920d, 0x7e157cee,
+ 0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
+ 0x7e0de099, 0x7e0cc90c,
+ 0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
+ 0x7e051bb4, 0x7e0401ba,
+ 0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
+ 0x7dfc4361, 0x7dfb26f9,
+ 0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
+ 0x7df357a0, 0x7df238ca,
+ 0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
+ 0x7dea5872, 0x7de9372f,
+ 0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
+ 0x7de145da, 0x7de02229,
+ 0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
+ 0x7dd81fd8, 0x7dd6f9ba,
+ 0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
+ 0x7dcee66e, 0x7dcdbde3,
+ 0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
+ 0x7dc5999d, 0x7dc46ea6,
+ 0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
+ 0x7dbc3967, 0x7dbb0c03,
+ 0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
+ 0x7db2c5cd, 0x7db195fd,
+ 0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
+ 0x7da93ed1, 0x7da80c95,
+ 0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
+ 0x7d9fa474, 0x7d9e6fcb,
+ 0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
+ 0x7d95f6b7, 0x7d94bfa3,
+ 0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
+ 0x7d8c359d, 0x7d8afc1d,
+ 0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
+ 0x7d826126, 0x7d81253a,
+ 0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
+ 0x7d787954, 0x7d773afd,
+ 0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
+ 0x7d6e7e29, 0x7d6d3d67,
+ 0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
+ 0x7d646fa6, 0x7d632c79,
+ 0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
+ 0x7d5a4dcc, 0x7d590835,
+ 0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
+ 0x7d50189e, 0x7d4ed09d,
+ 0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
+ 0x7d45d01d, 0x7d4485b1,
+ 0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
+ 0x7d3b744a, 0x7d3a2774,
+ 0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
+ 0x7d310527, 0x7d2fb5e7,
+ 0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
+ 0x7d2682b6, 0x7d25310d,
+ 0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
+ 0x7d1becf8, 0x7d1a98e5,
+ 0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
+ 0x7d1143ef, 0x7d0fed73,
+ 0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
+ 0x7d06879d, 0x7d052eb8,
+ 0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
+ 0x7cfbb803, 0x7cfa5cb4,
+ 0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
+ 0x7cf0d522, 0x7cef776b,
+ 0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
+ 0x7ce5defd, 0x7ce47ede,
+ 0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
+ 0x7cdad596, 0x7cd9730e,
+ 0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
+ 0x7ccfb8ed, 0x7cce53fe,
+ 0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
+ 0x7cc48905, 0x7cc321ae,
+ 0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
+ 0x7cb945df, 0x7cb7dc20,
+ 0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
+ 0x7cadef7e, 0x7cac8358,
+ 0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
+ 0x7ca285e2, 0x7ca11755,
+ 0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
+ 0x7c97090e, 0x7c95981a,
+ 0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
+ 0x7c8b7903, 0x7c8a05a8,
+ 0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
+ 0x7c7fd5c4, 0x7c7e6002,
+ 0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
+ 0x7c741f51, 0x7c72a729,
+ 0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
+ 0x7c6855ad, 0x7c66db1f,
+ 0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
+ 0x7c5c78da, 0x7c5afbe6,
+ 0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
+ 0x7c5088d9, 0x7c4f0980,
+ 0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
+ 0x7c4485ad, 0x7c4303ee,
+ 0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
+ 0x7c386f56, 0x7c36eb33,
+ 0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
+ 0x7c2c45d8, 0x7c2abf4f,
+ 0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
+ 0x7c200933, 0x7c1e8046,
+ 0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
+ 0x7c13b96a, 0x7c122e19,
+ 0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
+ 0x7c07567f, 0x7c05c8c9,
+ 0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
+ 0x7bfae073, 0x7bf9505a,
+ 0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
+ 0x7bee5749, 0x7becc4cc,
+ 0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
+ 0x7be1bb02, 0x7be02621,
+ 0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
+ 0x7bd50ba1, 0x7bd3745d,
+ 0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
+ 0x7bc84927, 0x7bc6af80,
+ 0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
+ 0x7bbb7396, 0x7bb9d78c,
+ 0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
+ 0x7bae8af0, 0x7bacec84,
+ 0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
+ 0x7ba18f38, 0x7b9fee69,
+ 0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
+ 0x7b94806e, 0x7b92dd3e,
+ 0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
+ 0x7b875e96, 0x7b85b904,
+ 0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
+ 0x7b7a29b2, 0x7b7881be,
+ 0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
+ 0x7b6ce1c2, 0x7b6b376e,
+ 0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
+ 0x7b5f86ca, 0x7b5dda15,
+ 0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
+ 0x7b5218cc, 0x7b5069b6,
+ 0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
+ 0x7b4497c9, 0x7b42e652,
+ 0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
+ 0x7b3703c3, 0x7b354fed,
+ 0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
+ 0x7b295cbe, 0x7b27a687,
+ 0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
+ 0x7b1ba2b9, 0x7b19ea23,
+ 0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
+ 0x7b0dd5b9, 0x7b0c1ac4,
+ 0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
+ 0x7afff5bf, 0x7afe386a,
+ 0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
+ 0x7af202cd, 0x7af0431a,
+ 0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
+ 0x7ae3fce6, 0x7ae23ad4,
+ 0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
+ 0x7ad5e40a, 0x7ad41f9a,
+ 0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
+ 0x7ac7b83e, 0x7ac5f170,
+ 0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
+ 0x7ab97982, 0x7ab7b056,
+ 0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
+ 0x7aab27da, 0x7aa95c50,
+ 0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
+ 0x7a9cc346, 0x7a9af55f,
+ 0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
+ 0x7a8e4bca, 0x7a8c7b87,
+ 0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
+ 0x7a7fc168, 0x7a7deec8,
+ 0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
+ 0x7a712422, 0x7a6f4f25,
+ 0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
+ 0x7a6273fa, 0x7a609ca1,
+ 0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
+ 0x7a53b0f2, 0x7a51d73d,
+ 0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
+ 0x7a44db0d, 0x7a42fefd,
+ 0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
+ 0x7a35f24d, 0x7a3413e2,
+ 0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
+ 0x7a26f6b4, 0x7a2515ee,
+ 0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
+ 0x7a17e845, 0x7a160524,
+ 0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
+ 0x7a08c702, 0x7a06e187,
+ 0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
+ 0x79f992ed, 0x79f7ab18,
+ 0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
+ 0x79ea4c09, 0x79e861da,
+ 0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
+ 0x79daf258, 0x79d905d0,
+ 0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
+ 0x79cb85dc, 0x79c996fb,
+ 0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
+ 0x79bc0698, 0x79ba155e,
+ 0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
+ 0x79ac748e, 0x79aa80fb,
+ 0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
+ 0x799ccfc1, 0x799ad9d5,
+ 0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
+ 0x798d1832, 0x798b1fef,
+ 0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
+ 0x797d4de5, 0x797b534a,
+ 0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
+ 0x796d70dc, 0x796b73e9,
+ 0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
+ 0x795d8118, 0x795b81cf,
+ 0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
+ 0x794d7e9e, 0x794b7cfe,
+ 0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
+ 0x793d696f, 0x793b6578,
+ 0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
+ 0x792d418d, 0x792b3b40,
+ 0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
+ 0x791d06fb, 0x791afe59,
+ 0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
+ 0x790cb9bd, 0x790aaec5,
+ 0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
+ 0x78fc59d3, 0x78fa4c86,
+ 0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
+ 0x78ebe741, 0x78e9d79f,
+ 0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
+ 0x78db6209, 0x78d95012,
+ 0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
+ 0x78caca2e, 0x78c8b5e3,
+ 0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
+ 0x78ba1fb2, 0x78b80913,
+ 0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
+ 0x78a96298, 0x78a749a6,
+ 0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
+ 0x789892e3, 0x7896779d,
+ 0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
+ 0x7887b094, 0x788592fc,
+ 0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
+ 0x7876bbb0, 0x78749bc5,
+ 0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
+ 0x7865b437, 0x786391fa,
+ 0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
+ 0x78549a2e, 0x7852759e,
+ 0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
+ 0x78436d96, 0x784146b5,
+ 0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
+ 0x78322e72, 0x78300540,
+ 0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
+ 0x7820dcc5, 0x781eb142,
+ 0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
+ 0x780f7892, 0x780d4abe,
+ 0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
+ 0x77fe01db, 0x77fbd1b6,
+ 0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
+ 0x77ec78a2, 0x77ea462e,
+ 0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
+ 0x77dadcec, 0x77d8a828,
+ 0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
+ 0x77c92eb9, 0x77c6f7a6,
+ 0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
+ 0x77b76e0e, 0x77b534ac,
+ 0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
+ 0x77a59aec, 0x77a35f3c,
+ 0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
+ 0x7793b557, 0x77917759,
+ 0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
+ 0x7781bd52, 0x777f7d05,
+ 0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
+ 0x776fb2de, 0x776d7044,
+ 0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
+ 0x775d95ff, 0x775b5118,
+ 0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
+ 0x774b66b8, 0x77491f84,
+ 0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
+ 0x7739250b, 0x7736db8b,
+ 0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
+ 0x7726d0fc, 0x7724852f,
+ 0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
+ 0x77146a8c, 0x77121c74,
+ 0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
+ 0x7701f1c0, 0x76ffa15c,
+ 0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
+ 0x76ef6699, 0x76ed13ea,
+ 0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
+ 0x76dcc91b, 0x76da7421,
+ 0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
+ 0x76ca1948, 0x76c7c204,
+ 0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
+ 0x76b75724, 0x76b4fd96,
+ 0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
+ 0x76a482b1, 0x76a226da,
+ 0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
+ 0x76919bf3, 0x768f3dd2,
+ 0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
+ 0x767ea2eb, 0x767c4281,
+ 0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
+ 0x766b979d, 0x766934eb,
+ 0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
+ 0x76587a0d, 0x76561512,
+ 0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
+ 0x76454a3c, 0x7642e2f9,
+ 0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
+ 0x7632082e, 0x762f9ea4,
+ 0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
+ 0x761eb3e6, 0x761c4815,
+ 0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
+ 0x760b4d67, 0x7608df4f,
+ 0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
+ 0x75f7d4b3, 0x75f56455,
+ 0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
+ 0x75e449ce, 0x75e1d72b,
+ 0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
+ 0x75d0acbc, 0x75ce37d2,
+ 0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
+ 0x75bcfd7e, 0x75ba864f,
+ 0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
+ 0x75a93c18, 0x75a6c2a4,
+ 0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
+ 0x7595688c, 0x7592ecd4,
+ 0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
+ 0x758182df, 0x757f04e3,
+ 0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
+ 0x756d8b13, 0x756b0ad3,
+ 0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
+ 0x7559812b, 0x7556fea8,
+ 0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
+ 0x7545652a, 0x7542e065,
+ 0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
+ 0x75313714, 0x752eb00c,
+ 0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
+ 0x751cf6eb, 0x751a6da0,
+ 0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
+ 0x7508a4b2, 0x75061926,
+ 0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
+ 0x74f4406d, 0x74f1b2a0,
+ 0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
+ 0x74dfca20, 0x74dd3a11,
+ 0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
+ 0x74cb41cc, 0x74c8af7d,
+ 0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
+ 0x74b6a775, 0x74b412e6,
+ 0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
+ 0x74a1fb1e, 0x749f6450,
+ 0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
+ 0x748d3ccb, 0x748aa3be,
+ 0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
+ 0x74786c7f, 0x7475d132,
+ 0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
+ 0x74638a3d, 0x7460ecb2,
+ 0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
+ 0x744e9608, 0x744bf63e,
+ 0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
+ 0x74398fe3, 0x7436eddc,
+ 0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
+ 0x742477d2, 0x7421d38e,
+ 0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
+ 0x740f4dd8, 0x740ca756,
+ 0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
+ 0x73fa11f8, 0x73f7693a,
+ 0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
+ 0x73e4c435, 0x73e2193b,
+ 0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
+ 0x73cf6493, 0x73ccb75d,
+ 0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
+ 0x73b9f315, 0x73b743a4,
+ 0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
+ 0x73a46fbf, 0x73a1be13,
+ 0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
+ 0x738eda93, 0x738c26ac,
+ 0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
+ 0x73793395, 0x73767d74,
+ 0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
+ 0x73637ac8, 0x7360c26e,
+ 0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
+ 0x734db030, 0x734af59d,
+ 0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
+ 0x7337d3d0, 0x73351704,
+ 0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
+ 0x7321e5ab, 0x731f26a7,
+ 0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
+ 0x730be5c5, 0x73092489,
+ 0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
+ 0x72f5d421, 0x72f310ad,
+ 0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
+ 0x72dfb0c3, 0x72dceb18,
+ 0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
+ 0x72c97bad, 0x72c6b3cc,
+ 0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
+ 0x72b334e4, 0x72b06acd,
+ 0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
+ 0x729cdc6b, 0x729a101e,
+ 0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
+ 0x72867245, 0x7283a3c3,
+ 0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
+ 0x726ff676, 0x726d25bf,
+ 0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
+ 0x72596901, 0x72569615,
+ 0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
+ 0x7242c9ea, 0x723ff4ca,
+ 0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
+ 0x722c1934, 0x722941e0,
+ 0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
+ 0x721556e3, 0x72127d5c,
+ 0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
+ 0x71fe82f9, 0x71fba740,
+ 0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
+ 0x71e79d7c, 0x71e4bf90,
+ 0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
+ 0x71d0a66d, 0x71cdc650,
+ 0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
+ 0x71b99dd2, 0x71b6bb83,
+ 0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
+ 0x71a283ad, 0x719f9f2c,
+ 0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
+ 0x718b5801, 0x71887151,
+ 0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
+ 0x71741ad3, 0x717131f3,
+ 0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
+ 0x715ccc26, 0x7159e116,
+ 0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
+ 0x71456bfe, 0x71427ebf,
+ 0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
+ 0x712dfa5e, 0x712b0af0,
+ 0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
+ 0x7116774a, 0x711385ad,
+ 0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
+ 0x70fee2c5, 0x70fbeefb,
+ 0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
+ 0x70e73cd4, 0x70e446dc,
+ 0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
+ 0x70cf8579, 0x70cc8d54,
+ 0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
+ 0x70b7bcb8, 0x70b4c267,
+ 0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
+ 0x709fe296, 0x709ce619,
+ 0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
+ 0x7087f715, 0x7084f86d,
+ 0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
+ 0x706ffa3a, 0x706cf967,
+ 0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
+ 0x7057ec08, 0x7054e90a,
+ 0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
+ 0x703fcc83, 0x703cc75b,
+ 0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
+ 0x70279baf, 0x7024945d,
+ 0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
+ 0x700f598e, 0x700c5013,
+ 0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
+ 0x6ff70626, 0x6ff3fa82,
+ 0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
+ 0x6fdea17a, 0x6fdb93ae,
+ 0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
+ 0x6fc62b8d, 0x6fc31b99,
+ 0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
+ 0x6fada464, 0x6faa9248,
+ 0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
+ 0x6f950c01, 0x6f91f7bf,
+ 0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
+ 0x6f7c626a, 0x6f794c01,
+ 0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
+ 0x6f63a7a1, 0x6f608f13,
+ 0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
+ 0x6f4adbab, 0x6f47c0f7,
+ 0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
+ 0x6f31fe8b, 0x6f2ee1b2,
+ 0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
+ 0x6f191045, 0x6f15f148,
+ 0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
+ 0x6f0010de, 0x6efcefbd,
+ 0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
+ 0x6ee70058, 0x6ee3dd13,
+ 0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
+ 0x6ecddeb8, 0x6ecab950,
+ 0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
+ 0x6eb4ac02, 0x6eb18477,
+ 0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
+ 0x6e9b6839, 0x6e983e8d,
+ 0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
+ 0x6e821361, 0x6e7ee794,
+ 0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
+ 0x6e68ad7f, 0x6e657f90,
+ 0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
+ 0x6e4f3696, 0x6e4c0687,
+ 0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
+ 0x6e35aeab, 0x6e327c7b,
+ 0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
+ 0x6e1c15c0, 0x6e18e171,
+ 0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
+ 0x6e026bda, 0x6dff356c,
+ 0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
+ 0x6de8b0fe, 0x6de57871,
+ 0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
+ 0x6dcee52e, 0x6dcbaa83,
+ 0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
+ 0x6db5086f, 0x6db1cba7,
+ 0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
+ 0x6d9b1ac6, 0x6d97dbe0,
+ 0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
+ 0x6d811c35, 0x6d7ddb33,
+ 0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
+ 0x6d670cc1, 0x6d63c9a3,
+ 0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
+ 0x6d4cec6e, 0x6d49a734,
+ 0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
+ 0x6d32bb40, 0x6d2f73eb,
+ 0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
+ 0x6d18793b, 0x6d152fcc,
+ 0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
+ 0x6cfe2663, 0x6cfadada,
+ 0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
+ 0x6ce3c2bd, 0x6ce0751a,
+ 0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
+ 0x6cc94e4b, 0x6cc5fe8f,
+ 0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
+ 0x6caec913, 0x6cab773e,
+ 0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
+ 0x6c943318, 0x6c90df2c,
+ 0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
+ 0x6c798c5f, 0x6c76365b,
+ 0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
+ 0x6c5ed4eb, 0x6c5b7cd0,
+ 0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
+ 0x6c440cc1, 0x6c40b28f,
+ 0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
+ 0x6c2933e5, 0x6c25d79d,
+ 0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
+ 0x6c0e4a5b, 0x6c0aebfe,
+ 0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
+ 0x6bf35027, 0x6befefb5,
+ 0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
+ 0x6bd8454d, 0x6bd4e2c6,
+ 0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
+ 0x6bbd29d2, 0x6bb9c537,
+ 0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
+ 0x6ba1fdb9, 0x6b9e970b,
+ 0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
+ 0x6b86c107, 0x6b835846,
+ 0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
+ 0x6b6b73c0, 0x6b6808ed,
+ 0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
+ 0x6b5015e9, 0x6b4ca904,
+ 0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
+ 0x6b34a785, 0x6b31388e,
+ 0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
+ 0x6b192898, 0x6b15b791,
+ 0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
+ 0x6afd9928, 0x6afa2610,
+ 0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
+ 0x6ae1f937, 0x6ade8410,
+ 0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
+ 0x6ac648cb, 0x6ac2d195,
+ 0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
+ 0x6aaa87e8, 0x6aa70ea4,
+ 0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
+ 0x6a8eb692, 0x6a8b3b3f,
+ 0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
+ 0x6a72d4cd, 0x6a6f576d,
+ 0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
+ 0x6a56e29e, 0x6a536331,
+ 0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
+ 0x6a3ae008, 0x6a375e8f,
+ 0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
+ 0x6a1ecd11, 0x6a1b498c,
+ 0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
+ 0x6a02a9bc, 0x69ff242b,
+ 0x69fb9e59, 0x69f81845, 0x69f491f0, 0x69f10b5a, 0x69ed8482, 0x69e9fd69,
+ 0x69e6760f, 0x69e2ee73,
+ 0x69df6696, 0x69dbde77, 0x69d85618, 0x69d4cd77, 0x69d14494, 0x69cdbb71,
+ 0x69ca320c, 0x69c6a866,
+ 0x69c31e7f, 0x69bf9456, 0x69bc09ec, 0x69b87f41, 0x69b4f455, 0x69b16928,
+ 0x69adddb9, 0x69aa5209,
+ 0x69a6c618, 0x69a339e6, 0x699fad73, 0x699c20be, 0x699893c9, 0x69950692,
+ 0x6991791a, 0x698deb61,
+ 0x698a5d67, 0x6986cf2c, 0x698340af, 0x697fb1f2, 0x697c22f3, 0x697893b4,
+ 0x69750433, 0x69717472,
+ 0x696de46f, 0x696a542b, 0x6966c3a6, 0x696332e1, 0x695fa1da, 0x695c1092,
+ 0x69587f09, 0x6954ed40,
+ 0x69515b35, 0x694dc8e9, 0x694a365c, 0x6946a38f, 0x69431080, 0x693f7d31,
+ 0x693be9a0, 0x693855cf,
+ 0x6934c1bd, 0x69312d6a, 0x692d98d6, 0x692a0401, 0x69266eeb, 0x6922d995,
+ 0x691f43fd, 0x691bae25,
+ 0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
+ 0x69028e24, 0x68fef645,
+ 0x68fb5e25, 0x68f7c5c5, 0x68f42d24, 0x68f09442, 0x68ecfb20, 0x68e961bd,
+ 0x68e5c819, 0x68e22e34,
+ 0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
+ 0x68c8f1e0, 0x68c555f6,
+ 0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
+ 0x68ac0b7f, 0x68a86d91,
+ 0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
+ 0x688f14fa, 0x688b7507,
+ 0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
+ 0x68720e55, 0x686e6c5e,
+ 0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
+ 0x6854f795, 0x6851539b,
+ 0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
+ 0x6837d0bd, 0x68342ac1,
+ 0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
+ 0x681a99d4, 0x6816f1d6,
+ 0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
+ 0x67fd52dc, 0x67f9a8dd,
+ 0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
+ 0x67dffbdc, 0x67dc4fdb,
+ 0x67d8a39a, 0x67d4f71a, 0x67d14a59, 0x67cd9d58, 0x67c9f017, 0x67c64297,
+ 0x67c294d6, 0x67bee6d5,
+ 0x67bb3894, 0x67b78a13, 0x67b3db53, 0x67b02c52, 0x67ac7d11, 0x67a8cd91,
+ 0x67a51dd0, 0x67a16dcf,
+ 0x679dbd8f, 0x679a0d0f, 0x67965c4e, 0x6792ab4e, 0x678efa0e, 0x678b488e,
+ 0x678796ce, 0x6783e4cf,
+ 0x6780328f, 0x677c8010, 0x6778cd50, 0x67751a51, 0x67716713, 0x676db394,
+ 0x6769ffd5, 0x67664bd7,
+ 0x67629799, 0x675ee31b, 0x675b2e5e, 0x67577960, 0x6753c423, 0x67500ea7,
+ 0x674c58ea, 0x6748a2ee,
+ 0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
+ 0x672ea210, 0x672aea17,
+ 0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
+ 0x6710db4d, 0x670d2157,
+ 0x67096721, 0x6705acab, 0x6701f1f6, 0x66fe3701, 0x66fa7bcd, 0x66f6c059,
+ 0x66f304a6, 0x66ef48b3,
+ 0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
+ 0x66d51e1d, 0x66d1602f,
+ 0x66cda201, 0x66c9e393, 0x66c624e7, 0x66c265fa, 0x66bea6cf, 0x66bae764,
+ 0x66b727ba, 0x66b367d0,
+ 0x66afa7a7, 0x66abe73f, 0x66a82697, 0x66a465b0, 0x66a0a489, 0x669ce324,
+ 0x6699217f, 0x66955f9b,
+ 0x66919d77, 0x668ddb14, 0x668a1872, 0x66865591, 0x66829270, 0x667ecf11,
+ 0x667b0b72, 0x66774793,
+ 0x66738376, 0x666fbf19, 0x666bfa7d, 0x666835a2, 0x66647088, 0x6660ab2f,
+ 0x665ce596, 0x66591fbf,
+ 0x665559a8, 0x66519352, 0x664dccbd, 0x664a05e9, 0x66463ed6, 0x66427784,
+ 0x663eaff2, 0x663ae822,
+ 0x66372012, 0x663357c4, 0x662f8f36, 0x662bc66a, 0x6627fd5e, 0x66243413,
+ 0x66206a8a, 0x661ca0c1,
+ 0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
+ 0x66021561, 0x65fe49a1,
+ 0x65fa7da2, 0x65f6b164, 0x65f2e4e7, 0x65ef182b, 0x65eb4b30, 0x65e77df6,
+ 0x65e3b07e, 0x65dfe2c6,
+ 0x65dc14d0, 0x65d8469b, 0x65d47827, 0x65d0a975, 0x65ccda83, 0x65c90b53,
+ 0x65c53be4, 0x65c16c36,
+ 0x65bd9c49, 0x65b9cc1e, 0x65b5fbb4, 0x65b22b0b, 0x65ae5a23, 0x65aa88fd,
+ 0x65a6b798, 0x65a2e5f4,
+ 0x659f1412, 0x659b41f1, 0x65976f91, 0x65939cf3, 0x658fca15, 0x658bf6fa,
+ 0x6588239f, 0x65845006,
+ 0x65807c2f, 0x657ca818, 0x6578d3c4, 0x6574ff30, 0x65712a5e, 0x656d554d,
+ 0x65697ffe, 0x6565aa71,
+ 0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
+ 0x654accba, 0x6546f538,
+ 0x65431d77, 0x653f4579, 0x653b6d3b, 0x653794c0, 0x6533bc06, 0x652fe30d,
+ 0x652c09d6, 0x65283061,
+ 0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
+ 0x650d3759, 0x65095bf0,
+ 0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
+ 0x64ee5546, 0x64ea77eb,
+ 0x64e69a52, 0x64e2bc7b, 0x64dede66, 0x64db0012, 0x64d72180, 0x64d342b0,
+ 0x64cf63a2, 0x64cb8456,
+ 0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
+ 0x64b06273, 0x64ac8135,
+ 0x64a89fba, 0x64a4be00, 0x64a0dc08, 0x649cf9d2, 0x6499175e, 0x649534ac,
+ 0x649151bc, 0x648d6e8e,
+ 0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
+ 0x64723184, 0x646e4c66,
+ 0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
+ 0x645301cd, 0x644f1ac0,
+ 0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
+ 0x6433c29f, 0x642fd9a3,
+ 0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
+ 0x641473fc, 0x64108912,
+ 0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
+ 0x63f515eb, 0x63f12913,
+ 0x63ed3bfd, 0x63e94eaa, 0x63e5611a, 0x63e1734b, 0x63dd853f, 0x63d996f6,
+ 0x63d5a86f, 0x63d1b9aa,
+ 0x63cdcaa8, 0x63c9db68, 0x63c5ebeb, 0x63c1fc30, 0x63be0c37, 0x63ba1c01,
+ 0x63b62b8e, 0x63b23add,
+ 0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
+ 0x63969f4c, 0x6392acaf,
+ 0x638eb9d5, 0x638ac6be, 0x6386d369, 0x6382dfd6, 0x637eec07, 0x637af7fa,
+ 0x637703af, 0x63730f27,
+ 0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
+ 0x635758bb, 0x63536249,
+ 0x634f6b99, 0x634b74ad, 0x63477d82, 0x6343861b, 0x633f8e76, 0x633b9695,
+ 0x63379e76, 0x6333a619,
+ 0x632fad80, 0x632bb4a9, 0x6327bb96, 0x6323c245, 0x631fc8b7, 0x631bceeb,
+ 0x6317d4e3, 0x6313da9e,
+ 0x630fe01b, 0x630be55b, 0x6307ea5e, 0x6303ef25, 0x62fff3ae, 0x62fbf7fa,
+ 0x62f7fc08, 0x62f3ffda,
+ 0x62f0036f, 0x62ec06c7, 0x62e809e2, 0x62e40cbf, 0x62e00f60, 0x62dc11c4,
+ 0x62d813eb, 0x62d415d4,
+ 0x62d01781, 0x62cc18f1, 0x62c81a24, 0x62c41b1a, 0x62c01bd3, 0x62bc1c4f,
+ 0x62b81c8f, 0x62b41c91,
+ 0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
+ 0x629815fa, 0x62941415,
+ 0x629011f4, 0x628c0f96, 0x62880cfb, 0x62840a23, 0x6280070f, 0x627c03be,
+ 0x62780030, 0x6273fc65,
+ 0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
+ 0x6257db37, 0x6253d587,
+ 0x624fcf9a, 0x624bc970, 0x6247c30a, 0x6243bc68, 0x623fb588, 0x623bae6c,
+ 0x6237a714, 0x62339f7e,
+ 0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
+ 0x621763cb, 0x62135a51,
+ 0x620f509b, 0x620b46a9, 0x62073c7a, 0x6203320e, 0x61ff2766, 0x61fb1c82,
+ 0x61f71161, 0x61f30604,
+ 0x61eefa6b, 0x61eaee95, 0x61e6e282, 0x61e2d633, 0x61dec9a8, 0x61dabce0,
+ 0x61d6afdd, 0x61d2a29c,
+ 0x61ce9520, 0x61ca8767, 0x61c67971, 0x61c26b40, 0x61be5cd2, 0x61ba4e28,
+ 0x61b63f41, 0x61b2301e,
+ 0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
+ 0x6195bf94, 0x6191ae90,
+ 0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
+ 0x617530db, 0x61711df5,
+ 0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
+ 0x6154931a, 0x61507e54,
+ 0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
+ 0x6133e657, 0x612fcfb0,
+ 0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
+ 0x61132a96, 0x610f1210,
+ 0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
+ 0x60f25fdd, 0x60ee4579,
+ 0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
+ 0x60d18631, 0x60cd69ee,
+ 0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
+ 0x60b09d96, 0x60ac7f76,
+ 0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
+ 0x608fa612, 0x608b8616,
+ 0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
+ 0x606e9faa, 0x606a7dd2,
+ 0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
+ 0x604d8a63, 0x604966af,
+ 0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
+ 0x602c6643, 0x602840b4,
+ 0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
+ 0x600b334d, 0x60070be4,
+ 0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
+ 0x5fe9f188, 0x5fe5c845,
+ 0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
+ 0x5fc8a0f8, 0x5fc475dc,
+ 0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
+ 0x5fa741a3, 0x5fa314af,
+ 0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
+ 0x5f85d38e, 0x5f81a4c2,
+ 0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
+ 0x5f6456be, 0x5f60261b,
+ 0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
+ 0x5f42cb37, 0x5f3e98be,
+ 0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
+ 0x5f213100, 0x5f1cfcb1,
+ 0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
+ 0x5eff881d, 0x5efb51f9,
+ 0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
+ 0x5eddd094, 0x5ed9989c,
+ 0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
+ 0x5ebc0a6a, 0x5eb7d09e,
+ 0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
+ 0x5e9a35a4, 0x5e95fa05,
+ 0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
+ 0x5e785247, 0x5e7414d5,
+ 0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
+ 0x5e566059, 0x5e522115,
+ 0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
+ 0x5e345fde, 0x5e301ec9,
+ 0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
+ 0x5e1250dc, 0x5e0e0df7,
+ 0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
+ 0x5df03359, 0x5debeea3,
+ 0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
+ 0x5dce0759, 0x5dc9c0d4,
+ 0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
+ 0x5dabcce1, 0x5da7848e,
+ 0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
+ 0x5d8983f8, 0x5d8539d7,
+ 0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
+ 0x5d672ca2, 0x5d62e0b4,
+ 0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
+ 0x5d44c6e4, 0x5d40792a,
+ 0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
+ 0x5d2252c5, 0x5d1e033e,
+ 0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
+ 0x5cffd048, 0x5cfb7ef7,
+ 0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
+ 0x5cdd3f75, 0x5cd8ec58,
+ 0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
+ 0x5cbaa04f, 0x5cb64b68,
+ 0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
+ 0x5c97f2dc, 0x5c939c2c,
+ 0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
+ 0x5c753722, 0x5c70deaa,
+ 0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
+ 0x5c526d25, 0x5c4e12e5,
+ 0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
+ 0x5c2f94ec, 0x5c2b38e5,
+ 0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
+ 0x5c0cae7c, 0x5c0850ae,
+ 0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
+ 0x5be9b9da, 0x5be55a46,
+ 0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
+ 0x5bc6b70b, 0x5bc255b2,
+ 0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
+ 0x5ba3a615, 0x5b9f42f7,
+ 0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
+ 0x5b8086fd, 0x5b7c221c,
+ 0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
+ 0x5b5d59c9, 0x5b58f324,
+ 0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
+ 0x5b3a1e7e, 0x5b35b617,
+ 0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
+ 0x5b16d521, 0x5b126af8,
+ 0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
+ 0x5af37db8, 0x5aef11cf,
+ 0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
+ 0x5ad01849, 0x5acbaa9f,
+ 0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
+ 0x5aaca4d8, 0x5aa8356f,
+ 0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
+ 0x5a89236c, 0x5a84b243,
+ 0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
+ 0x5a65940a, 0x5a612123,
+ 0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
+ 0x5a41f6b7, 0x5a3d8212,
+ 0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
+ 0x5a1e4b79, 0x5a19d517,
+ 0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
+ 0x59fa9255, 0x59f61a36,
+ 0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
+ 0x59d6cb50, 0x59d25176,
+ 0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
+ 0x59b2f671, 0x59ae7add,
+ 0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
+ 0x598f13bd, 0x598a966e,
+ 0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
+ 0x596b233a, 0x5966a431,
+ 0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
+ 0x594724ec, 0x5942a42a,
+ 0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
+ 0x592318d9, 0x591e9660,
+ 0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
+ 0x58feff08, 0x58fa7ad7,
+ 0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
+ 0x58dad77d, 0x58d65195,
+ 0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
+ 0x58b6a23e, 0x58b21aa0,
+ 0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
+ 0x58925f52, 0x588dd5fe,
+ 0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
+ 0x586e0ebc, 0x586983b4,
+ 0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
+ 0x5849b083, 0x584523c7,
+ 0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
+ 0x582544ad, 0x5820b63e,
+ 0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
+ 0x5800cb3f, 0x57fc3b1d,
+ 0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
+ 0x57dc443f, 0x57d7b26b,
+ 0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
+ 0x57b7afb2, 0x57b31c2d,
+ 0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
+ 0x57930d9e, 0x578e7869,
+ 0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
+ 0x576e5e09, 0x5769c724,
+ 0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
+ 0x5749a0f9, 0x57450864,
+ 0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
+ 0x5724d672, 0x57203c2f,
+ 0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
+ 0x56fffe7b, 0x56fb628b,
+ 0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
+ 0x56db1919, 0x56d67b7c,
+ 0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
+ 0x56b62653, 0x56b18709,
+ 0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
+ 0x5691262d, 0x568c8538,
+ 0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
+ 0x566c18ae, 0x5667760e,
+ 0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
+ 0x5646fddb, 0x56425991,
+ 0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
+ 0x5621d5ba, 0x561d2fc6,
+ 0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
+ 0x55fca050, 0x55f7f8b4,
+ 0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
+ 0x55d75da4, 0x55d2b460,
+ 0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
+ 0x55b20dbb, 0x55ad62d0,
+ 0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
+ 0x558cb09b, 0x55880409,
+ 0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
+ 0x55674649, 0x55629812,
+ 0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
+ 0x5541cecc, 0x553d1ef0,
+ 0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
+ 0x551c4a29, 0x551798a8,
+ 0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
+ 0x54f6b866, 0x54f20542,
+ 0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
+ 0x54d11989, 0x54cc64c2,
+ 0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
+ 0x54ab6d97, 0x54a6b72e,
+ 0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
+ 0x5485b497, 0x5480fc8c,
+ 0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
+ 0x545fee8e, 0x545b34e3,
+ 0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
+ 0x543a1b82, 0x54356037,
+ 0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
+ 0x54143b79, 0x540f7e8e,
+ 0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
+ 0x53ee4e78, 0x53e98fef,
+ 0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
+ 0x53c85486, 0x53c3945f,
+ 0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
+ 0x53a24da9, 0x539d8be5,
+ 0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
+ 0x537c39e6, 0x53777685,
+ 0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
+ 0x53561942, 0x53515447,
+ 0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
+ 0x532febc5, 0x532b252f,
+ 0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
+ 0x5309b174, 0x5304e943,
+ 0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
+ 0x52e36a55, 0x52dea08a,
+ 0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
+ 0x52bd166d, 0x52b84b0a,
+ 0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
+ 0x5296b5c3, 0x5291e8c8,
+ 0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
+ 0x5270485c, 0x526b79ca,
+ 0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
+ 0x5249ce3f, 0x5244fe17,
+ 0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
+ 0x52234771, 0x521e75b3,
+ 0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
+ 0x51fcb3f9, 0x51f7e0a6,
+ 0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
+ 0x51d613dc, 0x51d13ef5,
+ 0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
+ 0x51af6720, 0x51aa90a5,
+ 0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
+ 0x5188adcb, 0x5183d5be,
+ 0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
+ 0x5161e7e4, 0x515d0e45,
+ 0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
+ 0x513b156f, 0x51363a3f,
+ 0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
+ 0x51143674, 0x510f59b3,
+ 0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
+ 0x50ed4af8, 0x50e86ca8,
+ 0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
+ 0x50c65301, 0x50c17322,
+ 0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
+ 0x509f4e95, 0x509a6d28,
+ 0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
+ 0x50783dba, 0x50735abf,
+ 0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
+ 0x50512077, 0x504c3bef,
+ 0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
+ 0x5029f6d1, 0x502510bd,
+ 0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
+ 0x5002c0cd, 0x4ffdd92f,
+ 0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
+ 0x4fdb7e74, 0x4fd6954b,
+ 0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
+ 0x4fb42fc9, 0x4faf4517,
+ 0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
+ 0x4f8cd4d4, 0x4f87e899,
+ 0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
+ 0x4f656d9b, 0x4f607fd7,
+ 0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
+ 0x4f3dfa23, 0x4f390ad8,
+ 0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
+ 0x4f167a73, 0x4f1189a1,
+ 0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
+ 0x4eeeee90, 0x4ee9fc39,
+ 0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
+ 0x4ec75682, 0x4ec262a5,
+ 0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
+ 0x4e9fb24d, 0x4e9abcec,
+ 0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
+ 0x4e7801f8, 0x4e730b14,
+ 0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
+ 0x4e50458a, 0x4e4b4d22,
+ 0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
+ 0x4e287d08, 0x4e23831e,
+ 0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
+ 0x4e00a878, 0x4dfbad0d,
+ 0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
+ 0x4dd8c7e1, 0x4dd3caf6,
+ 0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
+ 0x4db0db48, 0x4dabdcdd,
+ 0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
+ 0x4d88e2b5, 0x4d83e2cb,
+ 0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
+ 0x4d60de2c, 0x4d5bdcc4,
+ 0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
+ 0x4d38cdb5, 0x4d33cad0,
+ 0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
+ 0x4d10b155, 0x4d0bacf3,
+ 0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
+ 0x4ce88913, 0x4ce38335,
+ 0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
+ 0x4cc054f4, 0x4cbb4d9b,
+ 0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
+ 0x4c981500, 0x4c930c2d,
+ 0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
+ 0x4c6fc93b, 0x4c6abeef,
+ 0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
+ 0x4c4771ae, 0x4c4265e8,
+ 0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
+ 0x4c1f0e5c, 0x4c1a011f,
+ 0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
+ 0x4bf69f4e, 0x4bf19099,
+ 0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
+ 0x4bce2488, 0x4bc9145d,
+ 0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
+ 0x4ba59e12, 0x4ba08c72,
+ 0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
+ 0x4b7d0bf2, 0x4b77f8dc,
+ 0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
+ 0x4b546e2d, 0x4b4f59a4,
+ 0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
+ 0x4b2bc4cb, 0x4b26aece,
+ 0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
+ 0x4b030fd1, 0x4afdf861,
+ 0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
+ 0x4ada4f45, 0x4ad53664,
+ 0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
+ 0x4ab1832f, 0x4aac68dc,
+ 0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
+ 0x4a88ab93, 0x4a838fd1,
+ 0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
+ 0x4a5fc879, 0x4a5aab48,
+ 0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
+ 0x4a36d9e7, 0x4a31bb47,
+ 0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
+ 0x4a0ddfe4, 0x4a08bfd5,
+ 0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
+ 0x49e4da74, 0x49dfb8f9,
+ 0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
+ 0x49bbc9a0, 0x49b6a6b8,
+ 0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
+ 0x4992ad6c, 0x498d8919,
+ 0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
+ 0x496985e0, 0x49646023,
+ 0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
+ 0x49405302, 0x493b2bdb,
+ 0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
+ 0x491714d8, 0x4911ec47,
+ 0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
+ 0x48edcb68, 0x48e8a170,
+ 0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
+ 0x48c476b9, 0x48bf4b59,
+ 0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
+ 0x489b16d2, 0x4895ea0b,
+ 0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
+ 0x4871abb8, 0x486c7d8c,
+ 0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
+ 0x48483572, 0x484305e1,
+ 0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
+ 0x481eb407, 0x48198311,
+ 0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
+ 0x47f5277d, 0x47eff523,
+ 0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
+ 0x47cb8fd9, 0x47c65c1d,
+ 0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
+ 0x47a1ed24, 0x479cb806,
+ 0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
+ 0x47783f62, 0x477308e3,
+ 0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
+ 0x474e869b, 0x47494ebc,
+ 0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
+ 0x4724c2d5, 0x471f8996,
+ 0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
+ 0x46faf416, 0x46f5b979,
+ 0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
+ 0x46d11a65, 0x46cbde6a,
+ 0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
+ 0x46a735c8, 0x46a1f870,
+ 0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
+ 0x467d4646, 0x46780792,
+ 0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
+ 0x46534be5, 0x464e0bd6,
+ 0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
+ 0x462946ac, 0x46240542,
+ 0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
+ 0x45ff36a1, 0x45f9f3dd,
+ 0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
+ 0x45d51bcb, 0x45cfd7ae,
+ 0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
+ 0x45aaf630, 0x45a5b0bb,
+ 0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
+ 0x4580c5d6, 0x457b7f0a,
+ 0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
+ 0x45568ac4, 0x455142a2,
+ 0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
+ 0x452c4502, 0x4526fb89,
+ 0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
+ 0x4501f494, 0x44fca9c6,
+ 0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
+ 0x44d79982, 0x44d24d60,
+ 0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
+ 0x44ad33d2, 0x44a7e65d,
+ 0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
+ 0x4482c38b, 0x447d74c4,
+ 0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
+ 0x445848b3, 0x4452f89b,
+ 0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
+ 0x442dc351, 0x442871e8,
+ 0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
+ 0x4403336c, 0x43fde0b2,
+ 0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
+ 0x43d8990a, 0x43d34501,
+ 0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
+ 0x43adf431, 0x43a89ed9,
+ 0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
+ 0x438344e8, 0x437dee43,
+ 0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
+ 0x43588b36, 0x43533344,
+ 0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
+ 0x432dc721, 0x43286de4,
+ 0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
+ 0x4302f8b0, 0x42fd9e28,
+ 0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
+ 0x42d81fe9, 0x42d2c417,
+ 0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
+ 0x42ad3cd4, 0x42a7dfb8,
+ 0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
+ 0x42824f76, 0x427cf112,
+ 0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
+ 0x425757d7, 0x4251f82b,
+ 0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
+ 0x422c55fd, 0x4226f50a,
+ 0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
+ 0x420149ee, 0x41fbe7b5,
+ 0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
+ 0x41d633b1, 0x41d0d033,
+ 0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
+ 0x41ab134e, 0x41a5ae8b,
+ 0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
+ 0x417fe8ca, 0x417a82c3,
+ 0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
+ 0x4154b42c, 0x414f4ce2,
+ 0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
+ 0x4129757b, 0x41240cef,
+ 0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
+ 0x40fe2cbd, 0x40f8c2f1,
+ 0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
+ 0x40d2d9f9, 0x40cd6eed,
+ 0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
+ 0x40a77d37, 0x40a210eb,
+ 0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
+ 0x407c167c, 0x4076a8f1,
+ 0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
+ 0x4050a5cf, 0x404b3707,
+ 0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
+ 0x40252b37, 0x401fbb32,
+ 0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
+ 0x3ff9a6bb, 0x3ff4357a,
+ 0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
+ 0x3fce1861, 0x3fc8a5e5,
+ 0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
+ 0x3fa28031, 0x3f9d0c7a,
+ 0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
+ 0x3f76de30, 0x3f71693f,
+ 0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
+ 0x3f4b3265, 0x3f45bc3c,
+ 0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
+ 0x3f1f7cd8, 0x3f1a0577,
+ 0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
+ 0x3ef3bd8f, 0x3eee44f7,
+ 0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
+ 0x3ec7f491, 0x3ec27ac2,
+ 0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
+ 0x3e9c21e4, 0x3e96a6e0,
+ 0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
+ 0x3e70458f, 0x3e6ac957,
+ 0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
+ 0x3e445f99, 0x3e3ee22e,
+ 0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
+ 0x3e18700a, 0x3e12f16b,
+ 0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
+ 0x3dec76e6, 0x3de6f716,
+ 0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
+ 0x3dc07436, 0x3dbaf335,
+ 0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
+ 0x3d946801, 0x3d8ee5cf,
+ 0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
+ 0x3d68524c, 0x3d62ceeb,
+ 0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
+ 0x3d3c331f, 0x3d36ae8f,
+ 0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
+ 0x3d100a80, 0x3d0a84c3,
+ 0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
+ 0x3ce3d877, 0x3cde518d,
+ 0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
+ 0x3cb79d0a, 0x3cb214f4,
+ 0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
+ 0x3c8b5840, 0x3c85cefe,
+ 0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
+ 0x3c5f0a20, 0x3c597fb4,
+ 0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
+ 0x3c32b2b0, 0x3c2d271b,
+ 0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
+ 0x3c0651f8, 0x3c00c53a,
+ 0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
+ 0x3bd9e7fe, 0x3bd45a19,
+ 0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
+ 0x3bad74c9, 0x3ba7e5bd,
+ 0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
+ 0x3b80f861, 0x3b7b682e,
+ 0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
+ 0x3b5472cb, 0x3b4ee173,
+ 0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
+ 0x3b27e40f, 0x3b225193,
+ 0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
+ 0x3afb4c34, 0x3af5b894,
+ 0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
+ 0x3aceab40, 0x3ac9167e,
+ 0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
+ 0x3aa2013a, 0x3a9c6b57,
+ 0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
+ 0x3a754e2a, 0x3a6fb726,
+ 0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
+ 0x3a489216, 0x3a42f9f2,
+ 0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
+ 0x3a1bcd05, 0x3a1633c1,
+ 0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
+ 0x39eefefe, 0x39e9649c,
+ 0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
+ 0x39c22808, 0x39bc8c89,
+ 0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
+ 0x39954829, 0x398fab8e,
+ 0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
+ 0x39685f6a, 0x3962c1b2,
+ 0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
+ 0x393b6dd0, 0x3935cefd,
+ 0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
+ 0x390e7362, 0x3908d376,
+ 0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
+ 0x38e17028, 0x38dbcf23,
+ 0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
+ 0x38b46429, 0x38aec20b,
+ 0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
+ 0x38874f6b, 0x3881ac36,
+ 0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
+ 0x385a31f5, 0x38548daa,
+ 0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
+ 0x382d0bce, 0x3827666d,
+ 0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
+ 0x37ffdcfe, 0x37fa3688,
+ 0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
+ 0x37d2a58b, 0x37ccfe02,
+ 0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
+ 0x37a5657c, 0x379fbce0,
+ 0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
+ 0x37781cd9, 0x3772732a,
+ 0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
+ 0x374acba7, 0x374520e7,
+ 0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
+ 0x371d71ef, 0x3717c61f,
+ 0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
+ 0x36f00fb7, 0x36ea62d7,
+ 0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
+ 0x36c2a506, 0x36bcf718,
+ 0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
+ 0x369531e3, 0x368f82e7,
+ 0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
+ 0x3667b655, 0x3662064c,
+ 0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
+ 0x363a3264, 0x3634814f,
+ 0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
+ 0x360ca615, 0x3606f3f5,
+ 0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
+ 0x35df1171, 0x35d95e47,
+ 0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
+ 0x35b1747e, 0x35abc04b,
+ 0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
+ 0x3583cf44, 0x357e1a08,
+ 0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
+ 0x355621c9, 0x35506b85,
+ 0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
+ 0x35286c14, 0x3522b4c9,
+ 0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
+ 0x34faae2c, 0x34f4f5dc,
+ 0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
+ 0x34cce819, 0x34c72ec4,
+ 0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
+ 0x349f19e2, 0x34995f88,
+ 0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
+ 0x3471438d, 0x346b8830,
+ 0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
+ 0x34436521, 0x343da8c3,
+ 0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
+ 0x34157ea7, 0x340fc147,
+ 0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
+ 0x33e79024, 0x33e1d1c4,
+ 0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
+ 0x33b999a0, 0x33b3da40,
+ 0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
+ 0x338b9b22, 0x3385dac4,
+ 0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
+ 0x335d94b2, 0x3357d355,
+ 0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
+ 0x332f8655, 0x3329c3fb,
+ 0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
+ 0x33017014, 0x32fbacbe,
+ 0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
+ 0x32d351f5, 0x32cd8da4,
+ 0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
+ 0x32a52bff, 0x329f66b4,
+ 0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
+ 0x3276fe3a, 0x327137f6,
+ 0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
+ 0x3248c8ad, 0x32430170,
+ 0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
+ 0x321a8b5f, 0x3214c32a,
+ 0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
+ 0x31ec4657, 0x31e67d2b,
+ 0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
+ 0x31bdf99b, 0x31b82f7a,
+ 0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
+ 0x318fa535, 0x3189da1e,
+ 0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
+ 0x31614929, 0x315b7d1e,
+ 0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
+ 0x3132e580, 0x312d1882,
+ 0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
+ 0x31047a41, 0x30feac51,
+ 0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
+ 0x30d60772, 0x30d03891,
+ 0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
+ 0x30a78d1c, 0x30a1bd4a,
+ 0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
+ 0x30790b45, 0x30733a83,
+ 0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
+ 0x304a81f4, 0x3044b044,
+ 0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
+ 0x301bf131, 0x30161e93,
+ 0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
+ 0x2fed5902, 0x2fe78577,
+ 0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
+ 0x2fbeb970, 0x2fb8e4f9,
+ 0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
+ 0x2f901280, 0x2f8a3d1e,
+ 0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
+ 0x2f61643b, 0x2f5b8def,
+ 0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
+ 0x2f32aea8, 0x2f2cd772,
+ 0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
+ 0x2f03f1cd, 0x2efe19ae,
+ 0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
+ 0x2ed52db1, 0x2ecf54ac,
+ 0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
+ 0x2ea6625d, 0x2ea08871,
+ 0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
+ 0x2e778fd8, 0x2e71b506,
+ 0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
+ 0x2e48b628, 0x2e42da71,
+ 0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
+ 0x2e19d554, 0x2e13f8ba,
+ 0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
+ 0x2deaed65, 0x2de50fe8,
+ 0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
+ 0x2dbbfe61, 0x2db62001,
+ 0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
+ 0x2d8d084f, 0x2d87290f,
+ 0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
+ 0x2d5e0b38, 0x2d582b17,
+ 0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
+ 0x2d2f0721, 0x2d292620,
+ 0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
+ 0x2cfffc12, 0x2cfa1a33,
+ 0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
+ 0x2cd0ea13, 0x2ccb0756,
+ 0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
+ 0x2ca1d12a, 0x2c9bed91,
+ 0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
+ 0x2c72b160, 0x2c6ccceb,
+ 0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
+ 0x2c438abb, 0x2c3da56b,
+ 0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
+ 0x2c145d42, 0x2c0e7719,
+ 0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
+ 0x2be528fd, 0x2bdf41fb,
+ 0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
+ 0x2bb5edf4, 0x2bb00619,
+ 0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
+ 0x2b86ac2c, 0x2b80c37a,
+ 0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
+ 0x2b5763ae, 0x2b517a26,
+ 0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
+ 0x2b281482, 0x2b222a24,
+ 0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
+ 0x2af8bead, 0x2af2d37b,
+ 0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
+ 0x2ac96238, 0x2ac37633,
+ 0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
+ 0x2a99ff2a, 0x2a941252,
+ 0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
+ 0x2a6a958a, 0x2a64a7e0,
+ 0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
+ 0x2a3b2560, 0x2a3536e5,
+ 0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
+ 0x2a0baeb2, 0x2a05bf67,
+ 0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
+ 0x29dc3188, 0x29d6416f,
+ 0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
+ 0x29acadea, 0x29a6bd02,
+ 0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
+ 0x297d23df, 0x2977322a,
+ 0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
+ 0x294d936d, 0x2947a0ec,
+ 0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
+ 0x291dfc9d, 0x29180951,
+ 0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
+ 0x28ee5f76, 0x28e86b5f,
+ 0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
+ 0x28bebbff, 0x28b8c71f,
+ 0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
+ 0x288f123f, 0x28891c97,
+ 0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
+ 0x285f623f, 0x28596bce,
+ 0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
+ 0x282fac04, 0x2829b4cd,
+ 0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
+ 0x27ffef97, 0x27f9f79a,
+ 0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
+ 0x27d02cff, 0x27ca343d,
+ 0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
+ 0x27a06443, 0x279a6abd,
+ 0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
+ 0x2770956a, 0x276a9b21,
+ 0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
+ 0x2740c07d, 0x273ac572,
+ 0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
+ 0x2710e582, 0x270ae9b6,
+ 0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
+ 0x26e10480, 0x26db07f4,
+ 0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
+ 0x26b11d80, 0x26ab2034,
+ 0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
+ 0x26813088, 0x267b327e,
+ 0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
+ 0x26513da1, 0x264b3ed9,
+ 0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
+ 0x262144d0, 0x261b454c,
+ 0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
+ 0x25f1461e, 0x25eb45de,
+ 0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
+ 0x25c14192, 0x25bb4098,
+ 0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
+ 0x25913734, 0x258b3580,
+ 0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
+ 0x2561270b, 0x255b249e,
+ 0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
+ 0x2531111e, 0x252b0df9,
+ 0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
+ 0x2500f574, 0x24faf198,
+ 0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
+ 0x24d0d416, 0x24cacf84,
+ 0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
+ 0x24a0ad0b, 0x249aa7c4,
+ 0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
+ 0x24708059, 0x246a7a5e,
+ 0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
+ 0x24404e09, 0x243a475a,
+ 0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
+ 0x24101622, 0x240a0ec1,
+ 0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
+ 0x23dfd8ab, 0x23d9d098,
+ 0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
+ 0x23af95ac, 0x23a98ce8,
+ 0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
+ 0x237f4d2b, 0x237943b9,
+ 0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
+ 0x234eff32, 0x2348f511,
+ 0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
+ 0x231eabc7, 0x2318a0f8,
+ 0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
+ 0x22ee52f1, 0x22e84775,
+ 0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
+ 0x22bdf4b8, 0x22b7e890,
+ 0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
+ 0x228d9123, 0x22878451,
+ 0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
+ 0x225d283b, 0x22571abe,
+ 0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
+ 0x222cba06, 0x2226abe0,
+ 0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
+ 0x21fc468b, 0x21f637be,
+ 0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
+ 0x21cbcdd3, 0x21c5be5e,
+ 0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
+ 0x219b4fe5, 0x21953fca,
+ 0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
+ 0x216accc8, 0x2164bc08,
+ 0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
+ 0x213a4484, 0x2134331f,
+ 0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
+ 0x2109b720, 0x2103a518,
+ 0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
+ 0x20d924a4, 0x20d311f9,
+ 0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
+ 0x20a88d17, 0x20a279ca,
+ 0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
+ 0x2077f080, 0x2071dc93,
+ 0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
+ 0x20474ee8, 0x20413a5b,
+ 0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
+ 0x2016a856, 0x2010932a,
+ 0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
+ 0x1fe5fcd0, 0x1fdfe707,
+ 0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
+ 0x1fb54c60, 0x1faf35f9,
+ 0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
+ 0x1f84970b, 0x1f7e8009,
+ 0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
+ 0x1f53dcdb, 0x1f4dc53d,
+ 0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
+ 0x1f231dd5, 0x1f1d059e,
+ 0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
+ 0x1ef25a03, 0x1eec4132,
+ 0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
+ 0x1ec1916a, 0x1ebb7802,
+ 0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
+ 0x1e90c414, 0x1e8aaa14,
+ 0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
+ 0x1e5ff206, 0x1e59d770,
+ 0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
+ 0x1e2f1b4a, 0x1e29001e,
+ 0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
+ 0x1dfe3fe6, 0x1df82426,
+ 0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
+ 0x1dcd5fe2, 0x1dc7438e,
+ 0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
+ 0x1d9c7b45, 0x1d965e5f,
+ 0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
+ 0x1d6b9217, 0x1d6574a0,
+ 0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
+ 0x1d3aa460, 0x1d348658,
+ 0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
+ 0x1d09b227, 0x1d03938f,
+ 0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
+ 0x1cd8bb74, 0x1cd29c4d,
+ 0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
+ 0x1ca7c04d, 0x1ca1a099,
+ 0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
+ 0x1c76c0bc, 0x1c70a07b,
+ 0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
+ 0x1c45bcc7, 0x1c3f9bf9,
+ 0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
+ 0x1c14b475, 0x1c0e931d,
+ 0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
+ 0x1be3a7cf, 0x1bdd85ed,
+ 0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
+ 0x1bb296dc, 0x1bac7471,
+ 0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
+ 0x1b8181a4, 0x1b7b5eb0,
+ 0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
+ 0x1b50682e, 0x1b4a44b3,
+ 0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
+ 0x1b1f4a81, 0x1b192680,
+ 0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
+ 0x1aee28a6, 0x1ae8041f,
+ 0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
+ 0x1abd02a3, 0x1ab6dd98,
+ 0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
+ 0x1a8bd881, 0x1a85b2f3,
+ 0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
+ 0x1a5aaa47, 0x1a548436,
+ 0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
+ 0x1a2977fc, 0x1a23516a,
+ 0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
+ 0x19f841a9, 0x19f21a96,
+ 0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
+ 0x19c70754, 0x19c0dfc2,
+ 0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
+ 0x1995c906, 0x198fa0f5,
+ 0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
+ 0x196486c6, 0x195e5e37,
+ 0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
+ 0x1933409b, 0x192d178f,
+ 0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
+ 0x1901f68d, 0x18fbcd06,
+ 0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
+ 0x18d0a8a4, 0x18ca7ea2,
+ 0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
+ 0x189f56e8, 0x18992c6b,
+ 0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
+ 0x186e015f, 0x1867d66a,
+ 0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
+ 0x183ca812, 0x18367ca5,
+ 0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
+ 0x180b4b08, 0x18051f24,
+ 0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
+ 0x17d9ea49, 0x17d3bdee,
+ 0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
+ 0x17a885dc, 0x17a2590d,
+ 0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
+ 0x17771dc9, 0x1770f086,
+ 0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
+ 0x1745b218, 0x173f8461,
+ 0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
+ 0x171442d0, 0x170e14a7,
+ 0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
+ 0x16e2cff9, 0x16dca15f,
+ 0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
+ 0x16b1599b, 0x16ab2a90,
+ 0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
+ 0x167fdfbc, 0x1679b042,
+ 0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
+ 0x164e6266, 0x1648327d,
+ 0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
+ 0x161ce19e, 0x1616b148,
+ 0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
+ 0x15eb5d6e, 0x15e52cab,
+ 0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
+ 0x15b9d5dd, 0x15b3a4ae,
+ 0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
+ 0x15884af1, 0x15821958,
+ 0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
+ 0x1556bcb4, 0x15508ab1,
+ 0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
+ 0x15252b2c, 0x151ef8c0,
+ 0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
+ 0x14f39662, 0x14ed638e,
+ 0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
+ 0x14c1fe5c, 0x14bbcb22,
+ 0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
+ 0x14906323, 0x148a2f82,
+ 0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
+ 0x145ec4be, 0x145890b9,
+ 0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
+ 0x142d2335, 0x1426eecb,
+ 0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
+ 0x13fb7e8f, 0x13f549c3,
+ 0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
+ 0x13c9d6d4, 0x13c3a1a6,
+ 0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
+ 0x13982c0d, 0x1391f67d,
+ 0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
+ 0x13667e3f, 0x13604850,
+ 0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
+ 0x1334cd74, 0x132e9725,
+ 0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
+ 0x130319b3, 0x12fce305,
+ 0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
+ 0x12d16303, 0x12cb2bf8,
+ 0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
+ 0x129fa96c, 0x12997205,
+ 0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
+ 0x126decf5, 0x1267b533,
+ 0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
+ 0x123c2da8, 0x1235f58b,
+ 0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
+ 0x120a6b8a, 0x12043314,
+ 0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
+ 0x11d8a6a4, 0x11d26dd6,
+ 0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
+ 0x11a6defe, 0x11a0a5d8,
+ 0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
+ 0x1175149e, 0x116edb22,
+ 0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
+ 0x1143478e, 0x113d0dbc,
+ 0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
+ 0x111177d4, 0x110b3dad,
+ 0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
+ 0x10dfa578, 0x10d96afe,
+ 0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
+ 0x10add082, 0x10a795b5,
+ 0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
+ 0x107bf8fa, 0x1075bddb,
+ 0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
+ 0x104a1ee7, 0x1043e377,
+ 0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
+ 0x10184251, 0x10120691,
+ 0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
+ 0xfe6633f, 0xfe02730,
+ 0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
+ 0xfae455d,
+ 0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
+ 0xf7c611f,
+ 0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
+ 0xf4a7a7d,
+ 0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
+ 0xf189180,
+ 0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
+ 0xee6a62f,
+ 0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
+ 0xeb4b891,
+ 0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
+ 0xe82c8af,
+ 0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
+ 0xe50d690,
+ 0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
+ 0xe1ee23c,
+ 0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
+ 0xdecebba,
+ 0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
+ 0xdbaf313,
+ 0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
+ 0xd88f84d,
+ 0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
+ 0xd56fb71,
+ 0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
+ 0xd24fc87,
+ 0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
+ 0xcf2fb96,
+ 0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
+ 0xcc0f8a5,
+ 0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
+ 0xc8ef3bd,
+ 0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
+ 0xc5cece5,
+ 0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
+ 0xc2ae425,
+ 0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
+ 0xbf8d985,
+ 0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
+ 0xbc6cd0c,
+ 0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
+ 0xb94bec2,
+ 0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
+ 0xb62aeaf,
+ 0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
+ 0xb309cdb,
+ 0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
+ 0xafe894d,
+ 0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
+ 0xacc740c,
+ 0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
+ 0xa9a5d22,
+ 0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
+ 0xa684495,
+ 0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
+ 0xa362a6d,
+ 0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
+ 0xa040eb1,
+ 0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
+ 0x9d1f16b,
+ 0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
+ 0x99fd2a0,
+ 0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
+ 0x96db25a,
+ 0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
+ 0x93b90a0,
+ 0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
+ 0x9096d79,
+ 0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
+ 0x8d748ed,
+ 0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
+ 0x8a52304,
+ 0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
+ 0x872fbc6,
+ 0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
+ 0x840d33b,
+ 0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
+ 0x80ea969,
+ 0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
+ 0x7dc7e5a,
+ 0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
+ 0x7aa5214,
+ 0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
+ 0x77824a0,
+ 0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
+ 0x745f604,
+ 0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
+ 0x713c64a,
+ 0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
+ 0x6e19578,
+ 0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
+ 0x6af6396,
+ 0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
+ 0x67d30ad,
+ 0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
+ 0x64afcc3,
+ 0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
+ 0x618c7e1,
+ 0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
+ 0x5e6920e,
+ 0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
+ 0x5b45b53,
+ 0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
+ 0x58223b6,
+ 0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
+ 0x54feb3f,
+ 0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
+ 0x51db1f7,
+ 0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
+ 0x4eb77e5,
+ 0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
+ 0x4b93d11,
+ 0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
+ 0x4870182,
+ 0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
+ 0x454c541,
+ 0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
+ 0x4228854,
+ 0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
+ 0x3f04ac4,
+ 0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
+ 0x3be0c99,
+ 0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
+ 0x38bcdda,
+ 0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
+ 0x3598e8f,
+ 0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
+ 0x3274ec0,
+ 0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
+ 0x2f50e74,
+ 0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
+ 0x2c2cdb4,
+ 0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
+ 0x2908c87,
+ 0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
+ 0x25e4af4,
+ 0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
+ 0x22c0904,
+ 0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
+ 0x1f9c6be,
+ 0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
+ 0x1c7842a,
+ 0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
+ 0x1954150,
+ 0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
+ 0x162fe37,
+ 0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
+ 0x130bae7,
+ 0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
+ 0xfe7769,
+ 0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
+ 0xcc33c3,
+ 0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
+ 0x99effe,
+ 0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
+ 0x67ac21,
+ 0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
+ 0x356835,
+ 0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
+
+};
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ31Table.gif
+ */
+
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+ (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q31_t *pCosFactor[4] =
+ { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+ (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT Function */
+ arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 000000000..cc7e76c7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,394 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q15.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q15.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ15Table.gif
+ */
+
+void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q15_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 000000000..546686b34
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q31.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q31.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ * \par Input an output formats:
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,
+ * as the conversion from DCT2 to DCT4 involves one subtraction.
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ31Table.gif
+ */
+
+void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer)
+{
+ uint16_t i; /* Loop counter */
+ q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q31_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = (S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = (S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = (S->N - 1u);
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 000000000..bb3f35dd4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,329 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/*--------------------------------------------------------------------
+ * Internal functions prototypes
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed
+ * in the future.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst)
+{
+ const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+ /* Calculation of Real IFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+ /* Complex radix-4 IFFT process */
+ arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier,
+ S_CFFT->onebyfftLen);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+
+ /* Calculation of RFFT of input */
+
+ /* Complex radix-4 FFT process */
+ arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+
+ /* Real FFT core process */
+ arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+/**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u]; /* temp pointers for output buffer */
+ float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u]; /* temp pointers for input buffer */
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ /* read pATable[2 * i] */
+ CoefA1 = *pCoefA++;
+ /* pATable[2 * i + 1] */
+ CoefA2 = *pCoefA;
+
+ /* pSrc[2 * i] * pATable[2 * i] */
+ outR = *pSrc1 * CoefA1;
+ /* pSrc[2 * i] * CoefA2 */
+ outI = *pSrc1++ * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR -= (*pSrc1 + *pSrc2) * CoefA2;
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += *pSrc1++ * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI -= *pSrc2 * CoefA2;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2-- * CoefB1;
+
+ /* write output */
+ *pDst1++ = outR;
+ *pDst1++ = outI;
+
+ /* write complex conjugate output */
+ *pDst2-- = -outI;
+ *pDst2-- = outR;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0.0f;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0.0f;
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * CoefA1 */
+ outR = *pSrc1 * CoefA1;
+
+ /* - pSrc[2 * i] * CoefA2 */
+ outI = -(*pSrc1++) * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += (*pSrc1++) * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2 * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI += *pSrc2-- * CoefA2;
+
+ /* write output */
+ *pDst++ = outR;
+ *pDst++ = outI;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+ }
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100644
index 000000000..17ef077a7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,354 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b; /* temporary variables */
+ float32_t p0, p1, p2, p3; /* temporary variables */
+
+
+ k = (S->Sint).fftLen - 1;
+
+ /* Pack first and last sample of the frequency domain together */
+
+ xBR = pB[0];
+ xBI = pB[1];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++ ;
+ twI = *pCoeff++ ;
+
+ // U1 = XA(1) + XB(1); % It is real
+ t1a = xBR + xAR ;
+
+ // U2 = XB(1) - XA(1); % It is imaginary
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ *pOut++ = 0.5f * ( t1a + t1b );
+ *pOut++ = 0.5f * ( t1a - t1b );
+
+ // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) ));
+ pB = p + 2*k;
+ pA += 2;
+
+ do
+ {
+ /*
+ function X = my_split_rfft(X, ifftFlag)
+ % X is a series of real numbers
+ L = length(X);
+ XC = X(1:2:end) +i*X(2:2:end);
+ XA = fft(XC);
+ XB = conj(XA([1 end:-1:2]));
+ TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+ for l = 2:L/2
+ XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+ end
+ XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+ X = XA;
+ */
+
+ xBI = pB[1];
+ xBR = pB[0];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xBR - xAR ;
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ p0 = twR * t1a;
+ p1 = twI * t1a;
+ p2 = twR * t1b;
+ p3 = twI * t1b;
+
+ *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ } while(k > 0u);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b, r, s, t, u; /* temporary variables */
+
+ k = (S->Sint).fftLen - 1;
+
+ xAR = pA[0];
+ xAI = pA[1];
+
+ pCoeff += 2 ;
+
+ *pOut++ = 0.5f * ( xAR + xAI );
+ *pOut++ = 0.5f * ( xAR - xAI );
+
+ pB = p + 2*k ;
+ pA += 2 ;
+
+ while(k > 0u)
+ {
+ /* G is half of the frequency complex spectrum */
+ //for k = 2:N
+ // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+ xBI = pB[1] ;
+ xBR = pB[0] ;
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xAR - xBR ;
+ t1b = xAI + xBI ;
+
+ r = twR * t1a;
+ s = twI * t1b;
+ t = twI * t1a;
+ u = twR * t1b;
+
+ // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+ // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+ *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ }
+
+}
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @defgroup Fast Real FFT Functions
+ *
+ * \par
+ * The CMSIS DSP library includes specialized algorithms for computing the
+ * FFT of real data sequences. The FFT is defined over complex data but
+ * in many applications the input is real. Real FFT algorithms take advantage
+ * of the symmetry properties of the FFT and have a speed advantage over complex
+ * algorithms of the same length.
+ * \par
+ * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ * \par
+ * The real length N forward FFT of a sequence is computed using the steps shown below.
+ * \par
+ * \image html RFFT.gif "Real Fast Fourier Transform"
+ * \par
+ * The real sequence is initially treated as if it were complex to perform a CFFT.
+ * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ * in complex format. Except the first complex number that contains the two real numbers
+ * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ * contains two real values packed.
+ * \par
+ * The input for the inverse RFFT should keep the same format as the output of the
+ * forward RFFT. A first processing stage pre-process the data to later perform an
+ * inverse CFFT.
+ * \par
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
+ * \par
+ * The algorithms for floating-point, Q15, and Q31 data are slightly different
+ * and we describe each algorithm in turn.
+ * \par Floating-point
+ * The main functions are <code>arm_rfft_fast_f32()</code>
+ * and <code>arm_rfft_fast_init_f32()</code>. The older functions
+ * <code>arm_rfft_f32()</code> and <code>arm_rfft_init_f32()</code> have been
+ * deprecated but are still documented.
+ * \par
+ * The FFT of a real N-point sequence has even symmetry in the frequency
+ * domain. The second half of the data equals the conjugate of the first half
+ * flipped in frequency:
+ * <pre>
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ *X[fftLen/2+1] - conjugate of X[fftLen/2-1]
+ *X[fftLen/2+2] - conjugate of X[fftLen/2-2]
+ *...
+ *X[fftLen-1] - conjugate of X[1]
+ * </pre>
+ * Looking at the data, we see that we can uniquely represent the FFT using only
+ * <pre>
+ *N/2+1 samples:
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ * </pre>
+ * Looking more closely we see that the first and last samples are real valued.
+ * They can be packed together and we can thus represent the FFT of an N-point
+ * real sequence by N/2 complex values:
+ * <pre>
+ *X[0],X[N/2] - packed real data: X[0] + jX[N/2]
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ * </pre>
+ * The real FFT functions pack the frequency domain data in this fashion. The
+ * forward transform outputs the data in this form and the inverse transform
+ * expects input data in this form. The function always performs the needed
+ * bitreversal so that the input and output data is always in normal order. The
+ * functions support lengths of [32, 64, 128, ..., 4096] samples.
+ * \par
+ * The forward and inverse real FFT functions apply the standard FFT scaling; no
+ * scaling on the forward transform and 1/fftLen scaling on the inverse
+ * transform.
+ * \par Q15 and Q31
+ * The real algorithms are defined in a similar manner and utilize N/2 complex
+ * transforms behind the scenes. In the case of fixed-point data, a radix-4
+ * complex transform is performed and this limits the allows sequence lengths to
+ * 128, 512, and 2048 samples.
+ * \par
+ * TBD. We need to document input and output order of data.
+ * \par
+ * The complex transforms used internally include scaling to prevent fixed-point
+ * overflows. The overall scaling equals 1/(fftLen/2).
+ * \par
+ * A separate instance structure must be defined for each transform used but
+ * twiddle factor and bit reversal tables can be reused.
+ * \par
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes twiddle factor table and bit reversal table pointers.
+ * - Initializes the internal complex FFT data structure.
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure
+ * cannot be placed into a const data section. To place an instance structure
+ * into a const data section, the instance structure should be manually
+ * initialized as follows:
+ * <pre>
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ * </pre>
+ * where <code>fftLenReal</code> is the length of the real transform;
+ * <code>fftLenBy2</code> length of the internal complex transform.
+ * <code>ifftFlagR</code> Selects forward (=0) or inverse (=1) transform.
+ * <code>bitReverseFlagR</code> Selects bit reversed output (=0) or normal order
+ * output (=1).
+ * <code>twidCoefRModifier</code> stride modifier for the twiddle factor table.
+ * The value is based on the FFT length;
+ * <code>pTwiddleAReal</code>points to the A array of twiddle coefficients;
+ * <code>pTwiddleBReal</code>points to the B array of twiddle coefficients;
+ * <code>pCfft</code> points to the CFFT Instance structure. The CFFT structure
+ * must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding
+ * static initialization of the complex FFT instance structure.
+ */
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point real FFT.
+* @param[in] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] *p points to the input buffer.
+* @param[in] *pOut points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] ifftFlag RFFT if flag is 0, RIFFT if flag is 1
+* @return none.
+*/
+
+void arm_rfft_fast_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut,
+uint8_t ifftFlag)
+{
+ arm_cfft_instance_f32 * Sint = &(S->Sint);
+ Sint->fftLen = S->fftLenRFFT / 2;
+
+ /* Calculation of Real FFT */
+ if(ifftFlag)
+ {
+ /* Real FFT comression */
+ merge_rfft_f32(S, p, pOut);
+
+ /* Complex radix-4 IFFT process */
+ arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+ arm_cfft_f32( Sint, p, ifftFlag, 1);
+
+ /* Real FFT extraction */
+ stage_rfft_f32(S, p, pOut);
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100644
index 000000000..c41537942
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_init_f32.c
+*
+* Description: Split Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point real FFT.
+* @param[in,out] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] fftLen length of the Real Sequence.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise RFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 16, 32, 64, 128, 256, 512, 1024, 2048, 4096.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_rfft_fast_init_f32(
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen)
+{
+ arm_cfft_instance_f32 * Sint;
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ Sint = &(S->Sint);
+ Sint->fftLen = fftLen/2;
+ S->fftLenRFFT = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ // S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (Sint->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+ /* Initialise the bit reversal table length */
+ Sint->bitRevLength = ARMBITREVINDEXTABLE4096_TABLE_LENGTH;
+ /* Initialise the bit reversal table pointer */
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable4096;
+ /* Initialise the 1/fftLen Value */
+ break;
+ case 2048u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+ break;
+ case 1024u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+ break;
+ case 512u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+ break;
+ case 256u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+ break;
+ case 128u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+ break;
+ case 64u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+ break;
+ case 32u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+ break;
+ case 16u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+ break;
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of RealFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 000000000..2f0032968
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,8376 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_f32.c
+*
+* Description: RFFT & RIFFT Floating point initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* \par
+* Generation of realCoefA array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+*/
+
+
+
+static const float32_t realCoefA[8192] = {
+ 0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
+ -0.499999850988388f,
+ 0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
+ -0.499998688697815f,
+ 0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
+ -0.499996334314346f,
+ 0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
+ -0.499992787837982f,
+ 0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
+ -0.499988079071045f,
+ 0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
+ -0.499982208013535f,
+ 0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
+ -0.499975144863129f,
+ 0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
+ -0.499966919422150f,
+ 0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
+ -0.499957501888275f,
+ 0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
+ -0.499946922063828f,
+ 0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
+ -0.499935150146484f,
+ 0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
+ -0.499922215938568f,
+ 0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
+ -0.499908089637756f,
+ 0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
+ -0.499892801046371f,
+ 0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
+ -0.499876320362091f,
+ 0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
+ -0.499858677387238f,
+ 0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
+ -0.499839842319489f,
+ 0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
+ -0.499819844961166f,
+ 0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
+ -0.499798685312271f,
+ 0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
+ -0.499776333570480f,
+ 0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
+ -0.499752789735794f,
+ 0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
+ -0.499728083610535f,
+ 0.483129411935806f, -0.499715298414230f, 0.482746154069901f,
+ -0.499702215194702f,
+ 0.482362866401672f, -0.499688833951950f, 0.481979638338089f,
+ -0.499675154685974f,
+ 0.481596380472183f, -0.499661177396774f, 0.481213152408600f,
+ -0.499646931886673f,
+ 0.480829954147339f, -0.499632388353348f, 0.480446726083755f,
+ -0.499617516994476f,
+ 0.480063527822495f, -0.499602377414703f, 0.479680359363556f,
+ -0.499586939811707f,
+ 0.479297190904617f, -0.499571204185486f, 0.478914022445679f,
+ -0.499555170536041f,
+ 0.478530883789063f, -0.499538868665695f, 0.478147745132446f,
+ -0.499522238969803f,
+ 0.477764606475830f, -0.499505341053009f, 0.477381497621536f,
+ -0.499488145112991f,
+ 0.476998418569565f, -0.499470651149750f, 0.476615339517593f,
+ -0.499452859163284f,
+ 0.476232260465622f, -0.499434769153595f, 0.475849211215973f,
+ -0.499416410923004f,
+ 0.475466161966324f, -0.499397724866867f, 0.475083142518997f,
+ -0.499378770589828f,
+ 0.474700123071671f, -0.499359518289566f, 0.474317133426666f,
+ -0.499339967966080f,
+ 0.473934143781662f, -0.499320119619370f, 0.473551183938980f,
+ -0.499299973249435f,
+ 0.473168224096298f, -0.499279528856277f, 0.472785294055939f,
+ -0.499258816242218f,
+ 0.472402364015579f, -0.499237775802612f, 0.472019463777542f,
+ -0.499216467142105f,
+ 0.471636593341827f, -0.499194860458374f, 0.471253722906113f,
+ -0.499172955751419f,
+ 0.470870882272720f, -0.499150782823563f, 0.470488041639328f,
+ -0.499128282070160f,
+ 0.470105201005936f, -0.499105513095856f, 0.469722419977188f,
+ -0.499082416296005f,
+ 0.469339638948441f, -0.499059051275253f, 0.468956857919693f,
+ -0.499035388231277f,
+ 0.468574106693268f, -0.499011427164078f, 0.468191385269165f,
+ -0.498987197875977f,
+ 0.467808693647385f, -0.498962640762329f, 0.467426002025604f,
+ -0.498937815427780f,
+ 0.467043310403824f, -0.498912662267685f, 0.466660678386688f,
+ -0.498887240886688f,
+ 0.466278046369553f, -0.498861521482468f, 0.465895414352417f,
+ -0.498835533857346f,
+ 0.465512841939926f, -0.498809218406677f, 0.465130269527435f,
+ -0.498782604932785f,
+ 0.464747726917267f, -0.498755723237991f, 0.464365184307098f,
+ -0.498728543519974f,
+ 0.463982671499252f, -0.498701065778732f, 0.463600188493729f,
+ -0.498673290014267f,
+ 0.463217705488205f, -0.498645216226578f, 0.462835282087326f,
+ -0.498616874217987f,
+ 0.462452858686447f, -0.498588204383850f, 0.462070435285568f,
+ -0.498559266328812f,
+ 0.461688071489334f, -0.498530030250549f, 0.461305707693100f,
+ -0.498500496149063f,
+ 0.460923373699188f, -0.498470664024353f, 0.460541069507599f,
+ -0.498440563678741f,
+ 0.460158795118332f, -0.498410135507584f, 0.459776520729065f,
+ -0.498379439115524f,
+ 0.459394276142120f, -0.498348444700241f, 0.459012061357498f,
+ -0.498317152261734f,
+ 0.458629876375198f, -0.498285561800003f, 0.458247691392899f,
+ -0.498253703117371f,
+ 0.457865566015244f, -0.498221516609192f, 0.457483440637589f,
+ -0.498189061880112f,
+ 0.457101345062256f, -0.498156309127808f, 0.456719279289246f,
+ -0.498123258352280f,
+ 0.456337243318558f, -0.498089909553528f, 0.455955207347870f,
+ -0.498056292533875f,
+ 0.455573230981827f, -0.498022347688675f, 0.455191254615784f,
+ -0.497988134622574f,
+ 0.454809308052063f, -0.497953623533249f, 0.454427421092987f,
+ -0.497918814420700f,
+ 0.454045534133911f, -0.497883707284927f, 0.453663676977158f,
+ -0.497848302125931f,
+ 0.453281819820404f, -0.497812628746033f, 0.452900022268295f,
+ -0.497776657342911f,
+ 0.452518254518509f, -0.497740387916565f, 0.452136516571045f,
+ -0.497703820466995f,
+ 0.451754778623581f, -0.497666954994202f, 0.451373100280762f,
+ -0.497629791498184f,
+ 0.450991421937943f, -0.497592359781265f, 0.450609803199768f,
+ -0.497554630041122f,
+ 0.450228184461594f, -0.497516602277756f, 0.449846625328064f,
+ -0.497478276491165f,
+ 0.449465066194534f, -0.497439652681351f, 0.449083566665649f,
+ -0.497400760650635f,
+ 0.448702067136765f, -0.497361570596695f, 0.448320597410202f,
+ -0.497322082519531f,
+ 0.447939187288284f, -0.497282296419144f, 0.447557777166367f,
+ -0.497242212295532f,
+ 0.447176426649094f, -0.497201830148697f, 0.446795076131821f,
+ -0.497161179780960f,
+ 0.446413785219193f, -0.497120231389999f, 0.446032524108887f,
+ -0.497078984975815f,
+ 0.445651292800903f, -0.497037440538406f, 0.445270061492920f,
+ -0.496995598077774f,
+ 0.444888889789581f, -0.496953487396240f, 0.444507747888565f,
+ -0.496911078691483f,
+ 0.444126635789871f, -0.496868371963501f, 0.443745553493500f,
+ -0.496825367212296f,
+ 0.443364530801773f, -0.496782064437866f, 0.442983508110046f,
+ -0.496738493442535f,
+ 0.442602545022964f, -0.496694594621658f, 0.442221581935883f,
+ -0.496650427579880f,
+ 0.441840678453445f, -0.496605962514877f, 0.441459804773331f,
+ -0.496561229228973f,
+ 0.441078960895538f, -0.496516168117523f, 0.440698176622391f,
+ -0.496470838785172f,
+ 0.440317392349243f, -0.496425211429596f, 0.439936667680740f,
+ -0.496379286050797f,
+ 0.439555943012238f, -0.496333062648773f, 0.439175277948380f,
+ -0.496286571025848f,
+ 0.438794672489166f, -0.496239781379700f, 0.438414067029953f,
+ -0.496192663908005f,
+ 0.438033521175385f, -0.496145308017731f, 0.437653005123138f,
+ -0.496097624301910f,
+ 0.437272518873215f, -0.496049642562866f, 0.436892062425613f,
+ -0.496001392602921f,
+ 0.436511665582657f, -0.495952844619751f, 0.436131268739700f,
+ -0.495903998613358f,
+ 0.435750931501389f, -0.495854884386063f, 0.435370653867722f,
+ -0.495805442333221f,
+ 0.434990376234055f, -0.495755732059479f, 0.434610158205032f,
+ -0.495705723762512f,
+ 0.434229999780655f, -0.495655417442322f, 0.433849841356277f,
+ -0.495604842901230f,
+ 0.433469742536545f, -0.495553970336914f, 0.433089673519135f,
+ -0.495502769947052f,
+ 0.432709634304047f, -0.495451331138611f, 0.432329654693604f,
+ -0.495399564504623f,
+ 0.431949704885483f, -0.495347499847412f, 0.431569814682007f,
+ -0.495295166969299f,
+ 0.431189924478531f, -0.495242536067963f, 0.430810123682022f,
+ -0.495189607143402f,
+ 0.430430322885513f, -0.495136409997940f, 0.430050581693649f,
+ -0.495082914829254f,
+ 0.429670870304108f, -0.495029091835022f, 0.429291218519211f,
+ -0.494975030422211f,
+ 0.428911596536636f, -0.494920641183853f, 0.428532034158707f,
+ -0.494865983724594f,
+ 0.428152471780777f, -0.494810998439789f, 0.427772998809814f,
+ -0.494755744934082f,
+ 0.427393525838852f, -0.494700223207474f, 0.427014142274857f,
+ -0.494644373655319f,
+ 0.426634758710861f, -0.494588255882263f, 0.426255434751511f,
+ -0.494531840085983f,
+ 0.425876170396805f, -0.494475126266479f, 0.425496935844421f,
+ -0.494418144226074f,
+ 0.425117731094360f, -0.494360834360123f, 0.424738585948944f,
+ -0.494303256273270f,
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+ 0.494187235832214f,
+ 0.424359470605850f, 0.494245409965515f, 0.424738585948944f,
+ 0.494303256273270f,
+ 0.425117731094360f, 0.494360834360123f, 0.425496935844421f,
+ 0.494418144226074f,
+ 0.425876170396805f, 0.494475126266479f, 0.426255434751511f,
+ 0.494531840085983f,
+ 0.426634758710861f, 0.494588255882263f, 0.427014142274857f,
+ 0.494644373655319f,
+ 0.427393525838852f, 0.494700223207474f, 0.427772998809814f,
+ 0.494755744934082f,
+ 0.428152471780777f, 0.494810998439789f, 0.428532034158707f,
+ 0.494865983724594f,
+ 0.428911596536636f, 0.494920641183853f, 0.429291218519211f,
+ 0.494975030422211f,
+ 0.429670870304108f, 0.495029091835022f, 0.430050581693649f,
+ 0.495082914829254f,
+ 0.430430322885513f, 0.495136409997940f, 0.430810123682022f,
+ 0.495189607143402f,
+ 0.431189924478531f, 0.495242536067963f, 0.431569814682007f,
+ 0.495295166969299f,
+ 0.431949704885483f, 0.495347499847412f, 0.432329654693604f,
+ 0.495399564504623f,
+ 0.432709634304047f, 0.495451331138611f, 0.433089673519135f,
+ 0.495502769947052f,
+ 0.433469742536545f, 0.495553970336914f, 0.433849841356277f,
+ 0.495604842901230f,
+ 0.434229999780655f, 0.495655417442322f, 0.434610158205032f,
+ 0.495705723762512f,
+ 0.434990376234055f, 0.495755732059479f, 0.435370653867722f,
+ 0.495805442333221f,
+ 0.435750931501389f, 0.495854884386063f, 0.436131268739700f,
+ 0.495903998613358f,
+ 0.436511665582657f, 0.495952844619751f, 0.436892062425613f,
+ 0.496001392602921f,
+ 0.437272518873215f, 0.496049642562866f, 0.437653005123138f,
+ 0.496097624301910f,
+ 0.438033521175385f, 0.496145308017731f, 0.438414067029953f,
+ 0.496192663908005f,
+ 0.438794672489166f, 0.496239781379700f, 0.439175277948380f,
+ 0.496286571025848f,
+ 0.439555943012238f, 0.496333062648773f, 0.439936667680740f,
+ 0.496379286050797f,
+ 0.440317392349243f, 0.496425211429596f, 0.440698176622391f,
+ 0.496470838785172f,
+ 0.441078960895538f, 0.496516168117523f, 0.441459804773331f,
+ 0.496561229228973f,
+ 0.441840678453445f, 0.496605962514877f, 0.442221581935883f,
+ 0.496650427579880f,
+ 0.442602545022964f, 0.496694594621658f, 0.442983508110046f,
+ 0.496738493442535f,
+ 0.443364530801773f, 0.496782064437866f, 0.443745553493500f,
+ 0.496825367212296f,
+ 0.444126635789871f, 0.496868371963501f, 0.444507747888565f,
+ 0.496911078691483f,
+ 0.444888889789581f, 0.496953487396240f, 0.445270061492920f,
+ 0.496995598077774f,
+ 0.445651292800903f, 0.497037440538406f, 0.446032524108887f,
+ 0.497078984975815f,
+ 0.446413785219193f, 0.497120231389999f, 0.446795076131821f,
+ 0.497161179780960f,
+ 0.447176426649094f, 0.497201830148697f, 0.447557777166367f,
+ 0.497242212295532f,
+ 0.447939187288284f, 0.497282296419144f, 0.448320597410202f,
+ 0.497322082519531f,
+ 0.448702067136765f, 0.497361570596695f, 0.449083566665649f,
+ 0.497400760650635f,
+ 0.449465066194534f, 0.497439652681351f, 0.449846625328064f,
+ 0.497478276491165f,
+ 0.450228184461594f, 0.497516602277756f, 0.450609803199768f,
+ 0.497554630041122f,
+ 0.450991421937943f, 0.497592359781265f, 0.451373100280762f,
+ 0.497629791498184f,
+ 0.451754778623581f, 0.497666954994202f, 0.452136516571045f,
+ 0.497703820466995f,
+ 0.452518254518509f, 0.497740387916565f, 0.452900022268295f,
+ 0.497776657342911f,
+ 0.453281819820404f, 0.497812628746033f, 0.453663676977158f,
+ 0.497848302125931f,
+ 0.454045534133911f, 0.497883707284927f, 0.454427421092987f,
+ 0.497918814420700f,
+ 0.454809308052063f, 0.497953623533249f, 0.455191254615784f,
+ 0.497988134622574f,
+ 0.455573230981827f, 0.498022347688675f, 0.455955207347870f,
+ 0.498056292533875f,
+ 0.456337243318558f, 0.498089909553528f, 0.456719279289246f,
+ 0.498123258352280f,
+ 0.457101345062256f, 0.498156309127808f, 0.457483440637589f,
+ 0.498189061880112f,
+ 0.457865566015244f, 0.498221516609192f, 0.458247691392899f,
+ 0.498253703117371f,
+ 0.458629876375198f, 0.498285561800003f, 0.459012061357498f,
+ 0.498317152261734f,
+ 0.459394276142120f, 0.498348444700241f, 0.459776520729065f,
+ 0.498379439115524f,
+ 0.460158795118332f, 0.498410135507584f, 0.460541069507599f,
+ 0.498440563678741f,
+ 0.460923373699188f, 0.498470664024353f, 0.461305707693100f,
+ 0.498500496149063f,
+ 0.461688071489334f, 0.498530030250549f, 0.462070435285568f,
+ 0.498559266328812f,
+ 0.462452858686447f, 0.498588204383850f, 0.462835282087326f,
+ 0.498616874217987f,
+ 0.463217705488205f, 0.498645216226578f, 0.463600188493729f,
+ 0.498673290014267f,
+ 0.463982671499252f, 0.498701065778732f, 0.464365184307098f,
+ 0.498728543519974f,
+ 0.464747726917267f, 0.498755723237991f, 0.465130269527435f,
+ 0.498782604932785f,
+ 0.465512841939926f, 0.498809218406677f, 0.465895414352417f,
+ 0.498835533857346f,
+ 0.466278046369553f, 0.498861521482468f, 0.466660678386688f,
+ 0.498887240886688f,
+ 0.467043310403824f, 0.498912662267685f, 0.467426002025604f,
+ 0.498937815427780f,
+ 0.467808693647385f, 0.498962640762329f, 0.468191385269165f,
+ 0.498987197875977f,
+ 0.468574106693268f, 0.499011427164078f, 0.468956857919693f,
+ 0.499035388231277f,
+ 0.469339638948441f, 0.499059051275253f, 0.469722419977188f,
+ 0.499082416296005f,
+ 0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
+ 0.499128282070160f,
+ 0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
+ 0.499172955751419f,
+ 0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
+ 0.499216467142105f,
+ 0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
+ 0.499258816242218f,
+ 0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
+ 0.499299973249435f,
+ 0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
+ 0.499339967966080f,
+ 0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
+ 0.499378770589828f,
+ 0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
+ 0.499416410923004f,
+ 0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
+ 0.499452859163284f,
+ 0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
+ 0.499488145112991f,
+ 0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
+ 0.499522238969803f,
+ 0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
+ 0.499555170536041f,
+ 0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
+ 0.499586939811707f,
+ 0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
+ 0.499617516994476f,
+ 0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
+ 0.499646931886673f,
+ 0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
+ 0.499675154685974f,
+ 0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
+ 0.499702215194702f,
+ 0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
+ 0.499728083610535f,
+ 0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
+ 0.499752789735794f,
+ 0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
+ 0.499776333570480f,
+ 0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
+ 0.499798685312271f,
+ 0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
+ 0.499819844961166f,
+ 0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
+ 0.499839842319489f,
+ 0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
+ 0.499858677387238f,
+ 0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
+ 0.499876320362091f,
+ 0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
+ 0.499892801046371f,
+ 0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
+ 0.499908089637756f,
+ 0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
+ 0.499922215938568f,
+ 0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
+ 0.499935150146484f,
+ 0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
+ 0.499946922063828f,
+ 0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
+ 0.499957501888275f,
+ 0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
+ 0.499966919422150f,
+ 0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
+ 0.499975144863129f,
+ 0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
+ 0.499982208013535f,
+ 0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
+ 0.499988079071045f,
+ 0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
+ 0.499992787837982f,
+ 0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
+ 0.499996334314346f,
+ 0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
+ 0.499998688697815f,
+ 0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
+ 0.499999850988388f,
+};
+
+
+/**
+* \par
+* Generation of realCoefB array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+*
+*/
+static const float32_t realCoefB[8192] = {
+ 0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
+ 0.499999850988388f,
+ 0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
+ 0.499998688697815f,
+ 0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
+ 0.499996334314346f,
+ 0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
+ 0.499992787837982f,
+ 0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
+ 0.499988079071045f,
+ 0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
+ 0.499982208013535f,
+ 0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
+ 0.499975144863129f,
+ 0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
+ 0.499966919422150f,
+ 0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
+ 0.499957501888275f,
+ 0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
+ 0.499946922063828f,
+ 0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
+ 0.499935150146484f,
+ 0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
+ 0.499922215938568f,
+ 0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
+ 0.499908089637756f,
+ 0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
+ 0.499892801046371f,
+ 0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
+ 0.499876320362091f,
+ 0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
+ 0.499858677387238f,
+ 0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
+ 0.499839842319489f,
+ 0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
+ 0.499819844961166f,
+ 0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
+ 0.499798685312271f,
+ 0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
+ 0.499776333570480f,
+ 0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
+ 0.499752789735794f,
+ 0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
+ 0.499728083610535f,
+ 0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
+ 0.499702215194702f,
+ 0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
+ 0.499675154685974f,
+ 0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
+ 0.499646931886673f,
+ 0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
+ 0.499617516994476f,
+ 0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
+ 0.499586939811707f,
+ 0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
+ 0.499555170536041f,
+ 0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
+ 0.499522238969803f,
+ 0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
+ 0.499488145112991f,
+ 0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
+ 0.499452859163284f,
+ 0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
+ 0.499416410923004f,
+ 0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
+ 0.499378770589828f,
+ 0.525299847126007f, 0.499359518289566f, 0.525682866573334f,
+ 0.499339967966080f,
+ 0.526065826416016f, 0.499320119619370f, 0.526448845863342f,
+ 0.499299973249435f,
+ 0.526831746101379f, 0.499279528856277f, 0.527214705944061f,
+ 0.499258816242218f,
+ 0.527597606182098f, 0.499237775802612f, 0.527980506420136f,
+ 0.499216467142105f,
+ 0.528363406658173f, 0.499194860458374f, 0.528746306896210f,
+ 0.499172955751419f,
+ 0.529129147529602f, 0.499150782823563f, 0.529511988162994f,
+ 0.499128282070160f,
+ 0.529894769191742f, 0.499105513095856f, 0.530277609825134f,
+ 0.499082416296005f,
+ 0.530660390853882f, 0.499059051275253f, 0.531043112277985f,
+ 0.499035388231277f,
+ 0.531425893306732f, 0.499011427164078f, 0.531808614730835f,
+ 0.498987197875977f,
+ 0.532191336154938f, 0.498962640762329f, 0.532573997974396f,
+ 0.498937815427780f,
+ 0.532956659793854f, 0.498912662267685f, 0.533339321613312f,
+ 0.498887240886688f,
+ 0.533721983432770f, 0.498861521482468f, 0.534104585647583f,
+ 0.498835533857346f,
+ 0.534487187862396f, 0.498809218406677f, 0.534869730472565f,
+ 0.498782604932785f,
+ 0.535252273082733f, 0.498755723237991f, 0.535634815692902f,
+ 0.498728543519974f,
+ 0.536017298698425f, 0.498701065778732f, 0.536399841308594f,
+ 0.498673290014267f,
+ 0.536782264709473f, 0.498645216226578f, 0.537164747714996f,
+ 0.498616874217987f,
+ 0.537547171115875f, 0.498588204383850f, 0.537929534912109f,
+ 0.498559266328812f,
+ 0.538311958312988f, 0.498530030250549f, 0.538694262504578f,
+ 0.498500496149063f,
+ 0.539076626300812f, 0.498470664024353f, 0.539458930492401f,
+ 0.498440563678741f,
+ 0.539841234683990f, 0.498410135507584f, 0.540223479270935f,
+ 0.498379439115524f,
+ 0.540605723857880f, 0.498348444700241f, 0.540987968444824f,
+ 0.498317152261734f,
+ 0.541370153427124f, 0.498285561800003f, 0.541752278804779f,
+ 0.498253703117371f,
+ 0.542134463787079f, 0.498221516609192f, 0.542516589164734f,
+ 0.498189061880112f,
+ 0.542898654937744f, 0.498156309127808f, 0.543280720710754f,
+ 0.498123258352280f,
+ 0.543662786483765f, 0.498089909553528f, 0.544044792652130f,
+ 0.498056292533875f,
+ 0.544426798820496f, 0.498022347688675f, 0.544808745384216f,
+ 0.497988134622574f,
+ 0.545190691947937f, 0.497953623533249f, 0.545572578907013f,
+ 0.497918814420700f,
+ 0.545954465866089f, 0.497883707284927f, 0.546336352825165f,
+ 0.497848302125931f,
+ 0.546718180179596f, 0.497812628746033f, 0.547099947929382f,
+ 0.497776657342911f,
+ 0.547481775283813f, 0.497740387916565f, 0.547863483428955f,
+ 0.497703820466995f,
+ 0.548245191574097f, 0.497666954994202f, 0.548626899719238f,
+ 0.497629791498184f,
+ 0.549008548259735f, 0.497592359781265f, 0.549390196800232f,
+ 0.497554630041122f,
+ 0.549771785736084f, 0.497516602277756f, 0.550153374671936f,
+ 0.497478276491165f,
+ 0.550534904003143f, 0.497439652681351f, 0.550916433334351f,
+ 0.497400760650635f,
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+ -0.499999850988388f,
+};
+
+
+
+/**
+* @brief Initialization function for the floating-point RFFT/RIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+* @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (float32_t *) realCoefA;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (float32_t *) realCoefB;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ /* Init table modifier value */
+ case 8192u:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 000000000..31fa6c2e5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2234 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q15.c
+*
+* Description: RFFT & RIFFT Q15 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+
+
+/**
+* \par
+* Generation floating point real_CoefA array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q15 format
+* round(pATable[i] * pow(2, 15))
+*/
+
+
+static const q15_t ALIGN4 realCoefAQ15[8192] = {
+ 0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
+ 0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
+ 0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
+ 0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
+ 0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
+ 0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
+ 0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
+ 0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
+ 0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
+ 0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
+ 0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
+ 0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
+ 0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
+ 0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
+ 0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
+ 0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
+ 0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
+ 0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
+ 0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
+ 0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
+ 0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
+ 0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
+ 0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
+ 0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
+ 0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
+ 0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
+ 0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
+ 0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
+ 0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
+ 0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
+ 0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
+ 0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
+ 0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
+ 0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
+ 0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
+ 0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
+ 0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
+ 0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
+ 0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
+ 0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
+ 0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
+ 0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
+ 0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
+ 0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
+ 0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
+ 0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
+ 0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
+ 0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
+ 0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
+ 0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
+ 0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
+ 0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
+ 0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
+ 0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
+ 0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
+ 0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
+ 0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
+ 0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
+ 0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
+ 0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
+ 0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
+ 0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
+ 0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
+ 0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
+ 0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
+ 0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
+ 0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
+ 0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
+ 0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
+ 0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
+ 0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
+ 0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
+ 0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
+ 0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
+ 0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
+ 0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
+ 0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
+ 0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
+ 0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
+ 0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
+ 0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
+ 0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
+ 0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
+ 0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
+ 0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
+ 0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
+ 0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
+ 0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
+ 0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
+ 0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
+ 0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
+ 0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
+ 0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
+ 0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
+ 0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
+ 0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
+ 0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
+ 0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
+ 0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
+ 0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
+ 0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
+ 0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
+ 0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
+ 0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
+ 0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
+ 0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
+ 0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
+ 0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
+ 0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
+ 0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
+ 0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
+ 0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
+ 0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
+ 0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
+ 0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
+ 0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
+ 0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
+ 0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
+ 0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
+ 0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
+ 0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
+ 0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
+ 0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
+ 0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
+ 0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
+ 0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
+ 0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
+ 0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
+ 0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
+ 0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
+ 0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
+ 0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
+ 0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
+ 0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
+ 0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
+ 0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
+ 0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
+ 0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
+ 0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
+ 0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
+ 0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
+ 0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
+ 0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
+ 0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
+ 0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
+ 0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
+ 0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
+ 0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
+ 0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
+ 0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
+ 0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
+ 0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
+ 0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
+ 0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
+ 0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
+ 0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
+ 0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
+ 0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
+ 0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
+ 0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
+ 0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
+ 0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
+ 0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
+ 0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
+ 0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
+ 0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
+ 0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
+ 0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
+ 0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
+ 0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
+ 0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
+ 0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
+ 0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
+ 0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
+ 0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
+ 0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
+ 0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
+ 0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
+ 0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
+ 0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
+ 0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
+ 0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
+ 0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
+ 0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
+ 0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
+ 0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
+ 0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
+ 0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
+ 0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
+ 0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
+ 0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
+ 0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
+ 0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
+ 0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
+ 0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
+ 0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
+ 0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
+ 0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
+ 0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
+ 0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
+ 0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
+ 0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
+ 0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
+ 0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
+ 0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
+ 0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
+ 0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
+ 0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
+ 0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
+ 0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
+ 0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
+ 0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
+ 0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
+ 0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
+ 0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
+ 0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
+ 0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
+ 0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
+ 0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
+ 0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
+ 0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
+ 0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
+ 0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
+ 0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
+ 0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
+ 0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
+ 0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
+ 0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
+ 0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
+ 0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
+ 0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
+ 0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
+ 0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
+ 0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
+ 0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
+ 0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
+ 0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
+ 0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
+ 0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
+ 0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
+ 0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
+ 0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
+ 0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
+ 0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
+ 0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
+ 0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
+ 0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
+ 0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
+ 0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
+ 0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
+ 0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
+ 0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
+ 0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
+ 0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
+ 0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
+ 0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
+ 0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
+ 0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
+ 0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
+ 0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
+ 0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
+ 0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
+ 0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
+ 0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
+ 0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
+ 0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
+ 0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
+ 0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
+ 0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
+ 0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
+ 0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
+ 0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
+ 0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
+ 0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
+ 0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
+ 0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
+ 0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
+ 0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
+ 0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
+ 0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
+ 0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
+ 0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
+ 0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
+ 0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
+ 0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
+ 0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
+ 0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
+ 0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
+ 0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
+ 0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
+ 0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
+ 0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
+ 0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
+ 0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
+ 0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
+ 0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
+ 0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
+ 0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
+ 0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
+ 0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
+ 0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
+ 0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
+ 0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
+ 0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
+ 0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
+ 0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
+ 0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
+ 0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
+ 0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
+ 0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
+ 0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
+ 0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
+ 0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
+ 0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
+ 0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
+ 0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
+ 0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
+ 0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
+ 0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
+ 0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
+ 0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
+ 0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
+ 0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
+ 0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
+ 0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
+ 0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
+ 0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
+ 0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
+ 0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
+ 0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
+ 0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
+ 0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
+ 0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
+ 0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
+ 0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
+ 0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
+ 0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
+ 0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
+ 0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
+ 0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
+ 0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
+ 0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
+ 0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
+ 0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
+ 0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
+ 0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
+ 0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
+ 0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
+ 0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
+ 0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
+ 0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
+ 0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
+ 0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
+ 0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
+ 0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
+ 0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
+ 0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
+ 0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
+ 0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
+ 0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
+ 0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
+ 0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
+ 0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
+ 0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
+ 0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
+ 0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
+ 0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
+ 0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
+ 0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
+ 0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
+ 0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
+ 0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
+ 0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
+ 0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
+ 0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
+ 0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
+ 0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
+ 0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
+ 0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
+ 0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
+ 0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
+ 0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
+ 0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
+ 0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
+ 0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
+ 0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
+ 0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
+ 0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
+ 0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
+ 0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
+ 0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
+ 0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
+ 0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
+ 0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
+ 0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
+ 0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
+ 0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
+ 0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
+ 0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
+ 0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
+ 0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
+ 0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
+ 0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
+ 0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
+ 0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
+ 0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
+ 0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
+ 0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
+ 0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
+ 0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
+ 0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
+ 0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
+ 0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
+ 0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
+ 0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
+ 0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
+ 0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
+ 0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
+ 0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
+ 0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
+ 0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
+ 0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
+ 0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
+ 0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
+ 0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
+ 0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
+ 0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
+ 0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
+ 0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
+ 0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
+ 0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
+ 0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
+ 0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
+ 0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
+ 0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
+ 0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
+ 0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
+ 0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
+ 0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
+ 0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
+ 0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
+ 0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
+ 0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
+ 0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
+ 0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
+ 0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
+ 0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
+ 0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
+ 0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
+ 0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
+ 0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
+ 0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
+ 0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
+ 0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
+ 0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
+ 0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
+ 0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
+ 0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
+ 0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
+ 0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
+ 0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
+ 0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
+ 0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
+ 0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
+ 0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
+ 0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
+ 0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
+ 0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
+ 0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
+ 0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
+ 0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
+ 0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
+ 0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
+ 0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
+ 0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
+ 0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
+ 0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
+ 0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
+ 0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
+ 0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
+ 0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
+ 0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
+ 0x45, 0xfa1e, 0x44, 0xfa2b, 0x43, 0xfa37, 0x42, 0xfa44,
+ 0x41, 0xfa50, 0x40, 0xfa5d, 0x3f, 0xfa69, 0x3d, 0xfa76,
+ 0x3c, 0xfa82, 0x3b, 0xfa8f, 0x3a, 0xfa9b, 0x39, 0xfaa8,
+ 0x38, 0xfab4, 0x37, 0xfac1, 0x36, 0xfacd, 0x35, 0xfada,
+ 0x34, 0xfae6, 0x33, 0xfaf3, 0x32, 0xfb00, 0x31, 0xfb0c,
+ 0x30, 0xfb19, 0x2f, 0xfb25, 0x2e, 0xfb32, 0x2d, 0xfb3e,
+ 0x2c, 0xfb4b, 0x2b, 0xfb57, 0x2b, 0xfb64, 0x2a, 0xfb70,
+ 0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,
+ 0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,
+ 0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,
+ 0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,
+ 0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,
+ 0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,
+ 0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,
+ 0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,
+ 0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,
+ 0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,
+ 0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,
+ 0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,
+ 0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,
+ 0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,
+ 0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,
+ 0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,
+ 0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,
+ 0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,
+ 0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,
+ 0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,
+ 0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,
+ 0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,
+ 0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,
+ 0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,
+ 0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,
+ 0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,
+ 0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,
+ 0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,
+ 0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,
+ 0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,
+ 0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,
+ 0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,
+ 0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,
+ 0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,
+ 0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,
+ 0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,
+ 0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,
+ 0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,
+ 0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,
+ 0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,
+ 0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,
+ 0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,
+ 0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,
+ 0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,
+ 0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,
+ 0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,
+ 0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,
+ 0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,
+ 0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,
+ 0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,
+ 0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,
+ 0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,
+ 0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,
+ 0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,
+ 0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,
+ 0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,
+ 0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,
+ 0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,
+ 0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,
+ 0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,
+ 0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,
+ 0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,
+ 0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,
+ 0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,
+ 0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,
+ 0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,
+ 0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,
+ 0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,
+ 0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,
+ 0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,
+ 0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,
+ 0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,
+ 0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,
+ 0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,
+ 0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,
+ 0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,
+ 0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,
+ 0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,
+ 0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,
+ 0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,
+ 0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,
+ 0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,
+ 0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,
+ 0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,
+ 0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,
+ 0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,
+ 0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,
+ 0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,
+ 0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,
+ 0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,
+ 0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,
+ 0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,
+ 0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,
+ 0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,
+ 0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,
+ 0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,
+ 0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,
+ 0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,
+ 0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,
+ 0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,
+ 0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,
+ 0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,
+ 0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,
+ 0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,
+ 0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,
+ 0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,
+ 0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,
+ 0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,
+ 0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,
+ 0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,
+ 0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,
+ 0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,
+ 0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,
+ 0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,
+ 0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,
+ 0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,
+ 0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,
+ 0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,
+ 0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,
+ 0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,
+ 0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,
+ 0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,
+ 0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,
+ 0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,
+ 0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,
+ 0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,
+ 0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,
+ 0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,
+ 0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,
+ 0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,
+ 0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,
+ 0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,
+ 0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,
+ 0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,
+ 0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,
+ 0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,
+ 0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,
+ 0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,
+ 0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,
+ 0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,
+ 0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,
+ 0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,
+ 0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,
+ 0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,
+ 0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,
+ 0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,
+ 0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,
+ 0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,
+ 0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,
+ 0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,
+ 0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,
+ 0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,
+ 0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,
+ 0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,
+ 0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,
+ 0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,
+ 0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,
+ 0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,
+ 0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,
+ 0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,
+ 0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,
+ 0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,
+ 0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,
+ 0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,
+ 0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,
+ 0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,
+ 0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,
+ 0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,
+ 0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,
+ 0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,
+ 0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,
+ 0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,
+ 0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,
+ 0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,
+ 0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,
+ 0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,
+ 0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,
+ 0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,
+ 0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,
+ 0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,
+ 0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,
+ 0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,
+ 0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,
+ 0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,
+ 0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,
+ 0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,
+ 0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,
+ 0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,
+ 0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,
+ 0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,
+ 0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,
+ 0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,
+ 0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,
+ 0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,
+ 0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,
+ 0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,
+ 0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,
+ 0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,
+ 0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,
+ 0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,
+ 0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,
+ 0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,
+ 0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,
+ 0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,
+ 0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,
+ 0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,
+ 0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,
+ 0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,
+ 0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,
+ 0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,
+ 0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,
+ 0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,
+ 0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,
+ 0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,
+ 0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,
+ 0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,
+ 0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,
+ 0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,
+ 0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,
+ 0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,
+ 0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,
+ 0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,
+ 0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,
+ 0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,
+ 0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,
+ 0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,
+ 0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,
+ 0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,
+ 0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,
+ 0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,
+ 0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,
+ 0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,
+ 0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,
+ 0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,
+ 0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,
+ 0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,
+ 0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,
+ 0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,
+ 0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,
+ 0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,
+ 0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,
+ 0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,
+ 0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,
+ 0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,
+ 0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,
+ 0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,
+ 0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,
+ 0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,
+ 0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,
+ 0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,
+ 0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,
+ 0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,
+ 0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,
+ 0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,
+ 0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,
+ 0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,
+ 0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,
+ 0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,
+ 0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,
+ 0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,
+ 0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,
+ 0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,
+ 0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,
+ 0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,
+ 0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,
+ 0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,
+ 0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,
+ 0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,
+ 0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,
+ 0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,
+ 0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,
+ 0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,
+ 0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,
+ 0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,
+ 0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,
+ 0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,
+ 0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,
+ 0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,
+ 0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,
+ 0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,
+ 0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,
+ 0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,
+ 0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,
+ 0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,
+ 0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,
+ 0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,
+ 0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,
+ 0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,
+ 0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,
+ 0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,
+ 0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,
+ 0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,
+ 0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,
+ 0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,
+ 0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,
+ 0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,
+ 0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,
+ 0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,
+ 0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,
+ 0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,
+ 0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,
+ 0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,
+ 0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,
+ 0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,
+ 0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,
+ 0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,
+ 0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,
+ 0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,
+ 0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,
+ 0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,
+ 0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,
+ 0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,
+ 0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,
+ 0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,
+ 0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,
+ 0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,
+ 0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,
+ 0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,
+ 0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,
+ 0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,
+ 0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,
+ 0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,
+ 0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,
+ 0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,
+ 0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,
+ 0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,
+ 0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,
+ 0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,
+ 0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,
+ 0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,
+ 0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,
+ 0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,
+ 0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,
+ 0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,
+ 0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,
+ 0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,
+ 0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,
+ 0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,
+ 0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,
+ 0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,
+ 0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,
+ 0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,
+ 0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,
+ 0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,
+ 0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,
+ 0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,
+ 0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,
+ 0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,
+ 0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,
+ 0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,
+ 0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,
+ 0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,
+ 0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,
+ 0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,
+ 0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,
+ 0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,
+ 0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,
+ 0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,
+ 0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,
+ 0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,
+ 0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,
+ 0x1f6f, 0x3718, 0x1f7a, 0x371f, 0x1f85, 0x3725, 0x1f90, 0x372c,
+ 0x1f9b, 0x3732, 0x1fa5, 0x3738, 0x1fb0, 0x373f, 0x1fbb, 0x3745,
+ 0x1fc6, 0x374b, 0x1fd1, 0x3752, 0x1fdc, 0x3758, 0x1fe7, 0x375e,
+ 0x1ff1, 0x3765, 0x1ffc, 0x376b, 0x2007, 0x3771, 0x2012, 0x3777,
+ 0x201d, 0x377e, 0x2028, 0x3784, 0x2033, 0x378a, 0x203e, 0x3790,
+ 0x2049, 0x3797, 0x2054, 0x379d, 0x205e, 0x37a3, 0x2069, 0x37a9,
+ 0x2074, 0x37b0, 0x207f, 0x37b6, 0x208a, 0x37bc, 0x2095, 0x37c2,
+ 0x20a0, 0x37c8, 0x20ab, 0x37ce, 0x20b6, 0x37d5, 0x20c1, 0x37db,
+ 0x20cc, 0x37e1, 0x20d7, 0x37e7, 0x20e2, 0x37ed, 0x20ed, 0x37f3,
+ 0x20f8, 0x37f9, 0x2103, 0x37ff, 0x210e, 0x3805, 0x2119, 0x380b,
+ 0x2124, 0x3812, 0x212f, 0x3818, 0x213a, 0x381e, 0x2145, 0x3824,
+ 0x2150, 0x382a, 0x215b, 0x3830, 0x2166, 0x3836, 0x2171, 0x383c,
+ 0x217c, 0x3842, 0x2187, 0x3848, 0x2192, 0x384e, 0x219d, 0x3854,
+ 0x21a8, 0x385a, 0x21b3, 0x3860, 0x21be, 0x3866, 0x21ca, 0x386b,
+ 0x21d5, 0x3871, 0x21e0, 0x3877, 0x21eb, 0x387d, 0x21f6, 0x3883,
+ 0x2201, 0x3889, 0x220c, 0x388f, 0x2217, 0x3895, 0x2222, 0x389b,
+ 0x222d, 0x38a1, 0x2239, 0x38a6, 0x2244, 0x38ac, 0x224f, 0x38b2,
+ 0x225a, 0x38b8, 0x2265, 0x38be, 0x2270, 0x38c3, 0x227b, 0x38c9,
+ 0x2287, 0x38cf, 0x2292, 0x38d5, 0x229d, 0x38db, 0x22a8, 0x38e0,
+ 0x22b3, 0x38e6, 0x22be, 0x38ec, 0x22ca, 0x38f2, 0x22d5, 0x38f7,
+ 0x22e0, 0x38fd, 0x22eb, 0x3903, 0x22f6, 0x3909, 0x2301, 0x390e,
+ 0x230d, 0x3914, 0x2318, 0x391a, 0x2323, 0x391f, 0x232e, 0x3925,
+ 0x233a, 0x392b, 0x2345, 0x3930, 0x2350, 0x3936, 0x235b, 0x393b,
+ 0x2367, 0x3941, 0x2372, 0x3947, 0x237d, 0x394c, 0x2388, 0x3952,
+ 0x2394, 0x3958, 0x239f, 0x395d, 0x23aa, 0x3963, 0x23b5, 0x3968,
+ 0x23c1, 0x396e, 0x23cc, 0x3973, 0x23d7, 0x3979, 0x23e2, 0x397e,
+ 0x23ee, 0x3984, 0x23f9, 0x3989, 0x2404, 0x398f, 0x2410, 0x3994,
+ 0x241b, 0x399a, 0x2426, 0x399f, 0x2432, 0x39a5, 0x243d, 0x39aa,
+ 0x2448, 0x39b0, 0x2454, 0x39b5, 0x245f, 0x39bb, 0x246a, 0x39c0,
+ 0x2476, 0x39c5, 0x2481, 0x39cb, 0x248c, 0x39d0, 0x2498, 0x39d6,
+ 0x24a3, 0x39db, 0x24ae, 0x39e0, 0x24ba, 0x39e6, 0x24c5, 0x39eb,
+ 0x24d0, 0x39f0, 0x24dc, 0x39f6, 0x24e7, 0x39fb, 0x24f3, 0x3a00,
+ 0x24fe, 0x3a06, 0x2509, 0x3a0b, 0x2515, 0x3a10, 0x2520, 0x3a16,
+ 0x252c, 0x3a1b, 0x2537, 0x3a20, 0x2542, 0x3a25, 0x254e, 0x3a2b,
+ 0x2559, 0x3a30, 0x2565, 0x3a35, 0x2570, 0x3a3a, 0x257c, 0x3a3f,
+ 0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,
+ 0x25b5, 0x3a59, 0x25c0, 0x3a5f, 0x25cc, 0x3a64, 0x25d7, 0x3a69,
+ 0x25e3, 0x3a6e, 0x25ee, 0x3a73, 0x25fa, 0x3a78, 0x2605, 0x3a7d,
+ 0x2611, 0x3a82, 0x261c, 0x3a88, 0x2628, 0x3a8d, 0x2633, 0x3a92,
+ 0x263f, 0x3a97, 0x264a, 0x3a9c, 0x2656, 0x3aa1, 0x2661, 0x3aa6,
+ 0x266d, 0x3aab, 0x2678, 0x3ab0, 0x2684, 0x3ab5, 0x268f, 0x3aba,
+ 0x269b, 0x3abf, 0x26a6, 0x3ac4, 0x26b2, 0x3ac9, 0x26bd, 0x3ace,
+ 0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,
+ 0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,
+ 0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,
+ 0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,
+ 0x2782, 0x3b21, 0x278e, 0x3b26, 0x2799, 0x3b2a, 0x27a5, 0x3b2f,
+ 0x27b1, 0x3b34, 0x27bc, 0x3b39, 0x27c8, 0x3b3e, 0x27d3, 0x3b42,
+ 0x27df, 0x3b47, 0x27eb, 0x3b4c, 0x27f6, 0x3b50, 0x2802, 0x3b55,
+ 0x280e, 0x3b5a, 0x2819, 0x3b5f, 0x2825, 0x3b63, 0x2831, 0x3b68,
+ 0x283c, 0x3b6d, 0x2848, 0x3b71, 0x2854, 0x3b76, 0x285f, 0x3b7b,
+ 0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,
+ 0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,
+ 0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,
+ 0x28f7, 0x3bb6, 0x2903, 0x3bbb, 0x290f, 0x3bbf, 0x291b, 0x3bc4,
+ 0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,
+ 0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,
+ 0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,
+ 0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,
+ 0x29e3, 0x3c0f, 0x29ee, 0x3c13, 0x29fa, 0x3c17, 0x2a06, 0x3c1c,
+ 0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,
+ 0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,
+ 0x2a70, 0x3c42, 0x2a7c, 0x3c46, 0x2a88, 0x3c4b, 0x2a94, 0x3c4f,
+ 0x2aa0, 0x3c53, 0x2aac, 0x3c57, 0x2ab7, 0x3c5b, 0x2ac3, 0x3c60,
+ 0x2acf, 0x3c64, 0x2adb, 0x3c68, 0x2ae7, 0x3c6c, 0x2af3, 0x3c70,
+ 0x2aff, 0x3c74, 0x2b0a, 0x3c79, 0x2b16, 0x3c7d, 0x2b22, 0x3c81,
+ 0x2b2e, 0x3c85, 0x2b3a, 0x3c89, 0x2b46, 0x3c8d, 0x2b52, 0x3c91,
+ 0x2b5e, 0x3c95, 0x2b6a, 0x3c99, 0x2b75, 0x3c9d, 0x2b81, 0x3ca1,
+ 0x2b8d, 0x3ca5, 0x2b99, 0x3ca9, 0x2ba5, 0x3cad, 0x2bb1, 0x3cb1,
+ 0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,
+ 0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,
+ 0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,
+ 0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,
+ 0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,
+ 0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,
+ 0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
+ 0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
+ 0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
+ 0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
+ 0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
+ 0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
+ 0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
+ 0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
+ 0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
+ 0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
+ 0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
+ 0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
+ 0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
+ 0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
+ 0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
+ 0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
+ 0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
+ 0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
+ 0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
+ 0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
+ 0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
+ 0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
+ 0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
+ 0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
+ 0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
+ 0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
+ 0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
+ 0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
+ 0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
+ 0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
+ 0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
+ 0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
+ 0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
+ 0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
+ 0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
+ 0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
+ 0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
+ 0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
+ 0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
+ 0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
+ 0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
+ 0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
+ 0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
+ 0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
+ 0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
+ 0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
+ 0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
+ 0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
+ 0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
+ 0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
+ 0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
+ 0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
+ 0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
+ 0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
+ 0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
+ 0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
+ 0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
+ 0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
+ 0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
+ 0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
+ 0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
+ 0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
+ 0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
+ 0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
+ 0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
+ 0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
+ 0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
+ 0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
+ 0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
+ 0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
+ 0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
+ 0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
+ 0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
+ 0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
+ 0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
+ 0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
+ 0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
+ 0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
+ 0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
+ 0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
+ 0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
+ 0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
+ 0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
+ 0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
+ 0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
+ 0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
+ 0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
+ 0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
+ 0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
+ 0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
+ 0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
+ 0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
+ 0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
+ 0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
+ 0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
+ 0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
+ 0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
+ 0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
+ 0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
+};
+
+/**
+* \par
+* Generation of real_CoefB array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q15 format
+* round(pBTable[i] * pow(2, 15))
+*
+*/
+
+static const q15_t ALIGN4 realCoefBQ15[8192] = {
+ 0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
+ 0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
+ 0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
+ 0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
+ 0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
+ 0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
+ 0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
+ 0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
+ 0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
+ 0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
+ 0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
+ 0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
+ 0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
+ 0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
+ 0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
+ 0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
+ 0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
+ 0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
+ 0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
+ 0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
+ 0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
+ 0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
+ 0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
+ 0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
+ 0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
+ 0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
+ 0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
+ 0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
+ 0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
+ 0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
+ 0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
+ 0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
+ 0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
+ 0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
+ 0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
+ 0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
+ 0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
+ 0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
+ 0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
+ 0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
+ 0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
+ 0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
+ 0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
+ 0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
+ 0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
+ 0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
+ 0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
+ 0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
+ 0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
+ 0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
+ 0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
+ 0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
+ 0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
+ 0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
+ 0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
+ 0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
+ 0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
+ 0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
+ 0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
+ 0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
+ 0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
+ 0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
+ 0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
+ 0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
+ 0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
+ 0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
+ 0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
+ 0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
+ 0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
+ 0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
+ 0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
+ 0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
+ 0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
+ 0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
+ 0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
+ 0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
+ 0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
+ 0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
+ 0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
+ 0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
+ 0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
+ 0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
+ 0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
+ 0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
+ 0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
+ 0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
+ 0x50b1, 0x3dc9, 0x50bd, 0x3dc6, 0x50c9, 0x3dc2, 0x50d5, 0x3dbf,
+ 0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
+ 0x5112, 0x3daf, 0x511e, 0x3dab, 0x512a, 0x3da8, 0x5136, 0x3da4,
+ 0x5142, 0x3da1, 0x514e, 0x3d9e, 0x515a, 0x3d9a, 0x5167, 0x3d97,
+ 0x5173, 0x3d93, 0x517f, 0x3d90, 0x518b, 0x3d8d, 0x5197, 0x3d89,
+ 0x51a3, 0x3d86, 0x51af, 0x3d82, 0x51bb, 0x3d7f, 0x51c7, 0x3d7b,
+ 0x51d3, 0x3d78, 0x51df, 0x3d74, 0x51eb, 0x3d71, 0x51f7, 0x3d6d,
+ 0x5204, 0x3d6a, 0x5210, 0x3d66, 0x521c, 0x3d63, 0x5228, 0x3d5f,
+ 0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
+ 0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
+ 0x5294, 0x3d3f, 0x52a0, 0x3d3b, 0x52ac, 0x3d37, 0x52b8, 0x3d34,
+ 0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
+ 0x52f4, 0x3d21, 0x5300, 0x3d1d, 0x530c, 0x3d1a, 0x5318, 0x3d16,
+ 0x5324, 0x3d12, 0x5330, 0x3d0e, 0x533c, 0x3d0b, 0x5348, 0x3d07,
+ 0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
+ 0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
+ 0x53b4, 0x3ce4, 0x53c0, 0x3ce0, 0x53cc, 0x3cdd, 0x53d8, 0x3cd9,
+ 0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
+ 0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
+ 0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
+ 0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
+ 0x54a2, 0x3c95, 0x54ae, 0x3c91, 0x54ba, 0x3c8d, 0x54c6, 0x3c89,
+ 0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
+ 0x5501, 0x3c74, 0x550d, 0x3c70, 0x5519, 0x3c6c, 0x5525, 0x3c68,
+ 0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
+ 0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
+ 0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
+ 0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
+ 0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
+ 0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
+ 0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
+ 0x567c, 0x3bec, 0x5687, 0x3be7, 0x5693, 0x3be3, 0x569f, 0x3bde,
+ 0x56ab, 0x3bda, 0x56b6, 0x3bd6, 0x56c2, 0x3bd1, 0x56ce, 0x3bcd,
+ 0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
+ 0x5709, 0x3bb6, 0x5714, 0x3bb2, 0x5720, 0x3bad, 0x572c, 0x3ba9,
+ 0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
+ 0x5766, 0x3b92, 0x5772, 0x3b8d, 0x577e, 0x3b88, 0x5789, 0x3b84,
+ 0x5795, 0x3b7f, 0x57a1, 0x3b7b, 0x57ac, 0x3b76, 0x57b8, 0x3b71,
+ 0x57c4, 0x3b6d, 0x57cf, 0x3b68, 0x57db, 0x3b63, 0x57e7, 0x3b5f,
+ 0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
+ 0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
+ 0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
+ 0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
+ 0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
+ 0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
+ 0x5909, 0x3ae6, 0x5914, 0x3ae2, 0x5920, 0x3add, 0x592c, 0x3ad8,
+ 0x5937, 0x3ad3, 0x5943, 0x3ace, 0x594e, 0x3ac9, 0x595a, 0x3ac4,
+ 0x5965, 0x3abf, 0x5971, 0x3aba, 0x597c, 0x3ab5, 0x5988, 0x3ab0,
+ 0x5993, 0x3aab, 0x599f, 0x3aa6, 0x59aa, 0x3aa1, 0x59b6, 0x3a9c,
+ 0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
+ 0x59ef, 0x3a82, 0x59fb, 0x3a7d, 0x5a06, 0x3a78, 0x5a12, 0x3a73,
+ 0x5a1d, 0x3a6e, 0x5a29, 0x3a69, 0x5a34, 0x3a64, 0x5a40, 0x3a5f,
+ 0x5a4b, 0x3a59, 0x5a57, 0x3a54, 0x5a62, 0x3a4f, 0x5a6e, 0x3a4a,
+ 0x5a79, 0x3a45, 0x5a84, 0x3a3f, 0x5a90, 0x3a3a, 0x5a9b, 0x3a35,
+ 0x5aa7, 0x3a30, 0x5ab2, 0x3a2b, 0x5abe, 0x3a25, 0x5ac9, 0x3a20,
+ 0x5ad4, 0x3a1b, 0x5ae0, 0x3a16, 0x5aeb, 0x3a10, 0x5af7, 0x3a0b,
+ 0x5b02, 0x3a06, 0x5b0d, 0x3a00, 0x5b19, 0x39fb, 0x5b24, 0x39f6,
+ 0x5b30, 0x39f0, 0x5b3b, 0x39eb, 0x5b46, 0x39e6, 0x5b52, 0x39e0,
+ 0x5b5d, 0x39db, 0x5b68, 0x39d6, 0x5b74, 0x39d0, 0x5b7f, 0x39cb,
+ 0x5b8a, 0x39c5, 0x5b96, 0x39c0, 0x5ba1, 0x39bb, 0x5bac, 0x39b5,
+ 0x5bb8, 0x39b0, 0x5bc3, 0x39aa, 0x5bce, 0x39a5, 0x5bda, 0x399f,
+ 0x5be5, 0x399a, 0x5bf0, 0x3994, 0x5bfc, 0x398f, 0x5c07, 0x3989,
+ 0x5c12, 0x3984, 0x5c1e, 0x397e, 0x5c29, 0x3979, 0x5c34, 0x3973,
+ 0x5c3f, 0x396e, 0x5c4b, 0x3968, 0x5c56, 0x3963, 0x5c61, 0x395d,
+ 0x5c6c, 0x3958, 0x5c78, 0x3952, 0x5c83, 0x394c, 0x5c8e, 0x3947,
+ 0x5c99, 0x3941, 0x5ca5, 0x393b, 0x5cb0, 0x3936, 0x5cbb, 0x3930,
+ 0x5cc6, 0x392b, 0x5cd2, 0x3925, 0x5cdd, 0x391f, 0x5ce8, 0x391a,
+ 0x5cf3, 0x3914, 0x5cff, 0x390e, 0x5d0a, 0x3909, 0x5d15, 0x3903,
+ 0x5d20, 0x38fd, 0x5d2b, 0x38f7, 0x5d36, 0x38f2, 0x5d42, 0x38ec,
+ 0x5d4d, 0x38e6, 0x5d58, 0x38e0, 0x5d63, 0x38db, 0x5d6e, 0x38d5,
+ 0x5d79, 0x38cf, 0x5d85, 0x38c9, 0x5d90, 0x38c3, 0x5d9b, 0x38be,
+ 0x5da6, 0x38b8, 0x5db1, 0x38b2, 0x5dbc, 0x38ac, 0x5dc7, 0x38a6,
+ 0x5dd3, 0x38a1, 0x5dde, 0x389b, 0x5de9, 0x3895, 0x5df4, 0x388f,
+ 0x5dff, 0x3889, 0x5e0a, 0x3883, 0x5e15, 0x387d, 0x5e20, 0x3877,
+ 0x5e2b, 0x3871, 0x5e36, 0x386b, 0x5e42, 0x3866, 0x5e4d, 0x3860,
+ 0x5e58, 0x385a, 0x5e63, 0x3854, 0x5e6e, 0x384e, 0x5e79, 0x3848,
+ 0x5e84, 0x3842, 0x5e8f, 0x383c, 0x5e9a, 0x3836, 0x5ea5, 0x3830,
+ 0x5eb0, 0x382a, 0x5ebb, 0x3824, 0x5ec6, 0x381e, 0x5ed1, 0x3818,
+ 0x5edc, 0x3812, 0x5ee7, 0x380b, 0x5ef2, 0x3805, 0x5efd, 0x37ff,
+ 0x5f08, 0x37f9, 0x5f13, 0x37f3, 0x5f1e, 0x37ed, 0x5f29, 0x37e7,
+ 0x5f34, 0x37e1, 0x5f3f, 0x37db, 0x5f4a, 0x37d5, 0x5f55, 0x37ce,
+ 0x5f60, 0x37c8, 0x5f6b, 0x37c2, 0x5f76, 0x37bc, 0x5f81, 0x37b6,
+ 0x5f8c, 0x37b0, 0x5f97, 0x37a9, 0x5fa2, 0x37a3, 0x5fac, 0x379d,
+ 0x5fb7, 0x3797, 0x5fc2, 0x3790, 0x5fcd, 0x378a, 0x5fd8, 0x3784,
+ 0x5fe3, 0x377e, 0x5fee, 0x3777, 0x5ff9, 0x3771, 0x6004, 0x376b,
+ 0x600f, 0x3765, 0x6019, 0x375e, 0x6024, 0x3758, 0x602f, 0x3752,
+ 0x603a, 0x374b, 0x6045, 0x3745, 0x6050, 0x373f, 0x605b, 0x3738,
+ 0x6065, 0x3732, 0x6070, 0x372c, 0x607b, 0x3725, 0x6086, 0x371f,
+ 0x6091, 0x3718, 0x609b, 0x3712, 0x60a6, 0x370c, 0x60b1, 0x3705,
+ 0x60bc, 0x36ff, 0x60c7, 0x36f8, 0x60d1, 0x36f2, 0x60dc, 0x36eb,
+ 0x60e7, 0x36e5, 0x60f2, 0x36df, 0x60fd, 0x36d8, 0x6107, 0x36d2,
+ 0x6112, 0x36cb, 0x611d, 0x36c5, 0x6128, 0x36be, 0x6132, 0x36b8,
+ 0x613d, 0x36b1, 0x6148, 0x36ab, 0x6153, 0x36a4, 0x615d, 0x369d,
+ 0x6168, 0x3697, 0x6173, 0x3690, 0x617d, 0x368a, 0x6188, 0x3683,
+ 0x6193, 0x367d, 0x619e, 0x3676, 0x61a8, 0x366f, 0x61b3, 0x3669,
+ 0x61be, 0x3662, 0x61c8, 0x365c, 0x61d3, 0x3655, 0x61de, 0x364e,
+ 0x61e8, 0x3648, 0x61f3, 0x3641, 0x61fe, 0x363a, 0x6208, 0x3634,
+ 0x6213, 0x362d, 0x621e, 0x3626, 0x6228, 0x3620, 0x6233, 0x3619,
+ 0x623d, 0x3612, 0x6248, 0x360b, 0x6253, 0x3605, 0x625d, 0x35fe,
+ 0x6268, 0x35f7, 0x6272, 0x35f0, 0x627d, 0x35ea, 0x6288, 0x35e3,
+ 0x6292, 0x35dc, 0x629d, 0x35d5, 0x62a7, 0x35ce, 0x62b2, 0x35c8,
+ 0x62bc, 0x35c1, 0x62c7, 0x35ba, 0x62d2, 0x35b3, 0x62dc, 0x35ac,
+ 0x62e7, 0x35a5, 0x62f1, 0x359f, 0x62fc, 0x3598, 0x6306, 0x3591,
+ 0x6311, 0x358a, 0x631b, 0x3583, 0x6326, 0x357c, 0x6330, 0x3575,
+ 0x633b, 0x356e, 0x6345, 0x3567, 0x6350, 0x3561, 0x635a, 0x355a,
+ 0x6365, 0x3553, 0x636f, 0x354c, 0x637a, 0x3545, 0x6384, 0x353e,
+ 0x638e, 0x3537, 0x6399, 0x3530, 0x63a3, 0x3529, 0x63ae, 0x3522,
+ 0x63b8, 0x351b, 0x63c3, 0x3514, 0x63cd, 0x350d, 0x63d7, 0x3506,
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+ 0x7984, 0x1c12, 0x7989, 0x1c07, 0x798f, 0x1bfc, 0x7994, 0x1bf0,
+ 0x799a, 0x1be5, 0x799f, 0x1bda, 0x79a5, 0x1bce, 0x79aa, 0x1bc3,
+ 0x79b0, 0x1bb8, 0x79b5, 0x1bac, 0x79bb, 0x1ba1, 0x79c0, 0x1b96,
+ 0x79c5, 0x1b8a, 0x79cb, 0x1b7f, 0x79d0, 0x1b74, 0x79d6, 0x1b68,
+ 0x79db, 0x1b5d, 0x79e0, 0x1b52, 0x79e6, 0x1b46, 0x79eb, 0x1b3b,
+ 0x79f0, 0x1b30, 0x79f6, 0x1b24, 0x79fb, 0x1b19, 0x7a00, 0x1b0d,
+ 0x7a06, 0x1b02, 0x7a0b, 0x1af7, 0x7a10, 0x1aeb, 0x7a16, 0x1ae0,
+ 0x7a1b, 0x1ad4, 0x7a20, 0x1ac9, 0x7a25, 0x1abe, 0x7a2b, 0x1ab2,
+ 0x7a30, 0x1aa7, 0x7a35, 0x1a9b, 0x7a3a, 0x1a90, 0x7a3f, 0x1a84,
+ 0x7a45, 0x1a79, 0x7a4a, 0x1a6e, 0x7a4f, 0x1a62, 0x7a54, 0x1a57,
+ 0x7a59, 0x1a4b, 0x7a5f, 0x1a40, 0x7a64, 0x1a34, 0x7a69, 0x1a29,
+ 0x7a6e, 0x1a1d, 0x7a73, 0x1a12, 0x7a78, 0x1a06, 0x7a7d, 0x19fb,
+ 0x7a82, 0x19ef, 0x7a88, 0x19e4, 0x7a8d, 0x19d8, 0x7a92, 0x19cd,
+ 0x7a97, 0x19c1, 0x7a9c, 0x19b6, 0x7aa1, 0x19aa, 0x7aa6, 0x199f,
+ 0x7aab, 0x1993, 0x7ab0, 0x1988, 0x7ab5, 0x197c, 0x7aba, 0x1971,
+ 0x7abf, 0x1965, 0x7ac4, 0x195a, 0x7ac9, 0x194e, 0x7ace, 0x1943,
+ 0x7ad3, 0x1937, 0x7ad8, 0x192c, 0x7add, 0x1920, 0x7ae2, 0x1914,
+ 0x7ae6, 0x1909, 0x7aeb, 0x18fd, 0x7af0, 0x18f2, 0x7af5, 0x18e6,
+ 0x7afa, 0x18db, 0x7aff, 0x18cf, 0x7b04, 0x18c3, 0x7b09, 0x18b8,
+ 0x7b0e, 0x18ac, 0x7b12, 0x18a1, 0x7b17, 0x1895, 0x7b1c, 0x1889,
+ 0x7b21, 0x187e, 0x7b26, 0x1872, 0x7b2a, 0x1867, 0x7b2f, 0x185b,
+ 0x7b34, 0x184f, 0x7b39, 0x1844, 0x7b3e, 0x1838, 0x7b42, 0x182d,
+ 0x7b47, 0x1821, 0x7b4c, 0x1815, 0x7b50, 0x180a, 0x7b55, 0x17fe,
+ 0x7b5a, 0x17f2, 0x7b5f, 0x17e7, 0x7b63, 0x17db, 0x7b68, 0x17cf,
+ 0x7b6d, 0x17c4, 0x7b71, 0x17b8, 0x7b76, 0x17ac, 0x7b7b, 0x17a1,
+ 0x7b7f, 0x1795, 0x7b84, 0x1789, 0x7b88, 0x177e, 0x7b8d, 0x1772,
+ 0x7b92, 0x1766, 0x7b96, 0x175b, 0x7b9b, 0x174f, 0x7b9f, 0x1743,
+ 0x7ba4, 0x1737, 0x7ba9, 0x172c, 0x7bad, 0x1720, 0x7bb2, 0x1714,
+ 0x7bb6, 0x1709, 0x7bbb, 0x16fd, 0x7bbf, 0x16f1, 0x7bc4, 0x16e5,
+ 0x7bc8, 0x16da, 0x7bcd, 0x16ce, 0x7bd1, 0x16c2, 0x7bd6, 0x16b6,
+ 0x7bda, 0x16ab, 0x7bde, 0x169f, 0x7be3, 0x1693, 0x7be7, 0x1687,
+ 0x7bec, 0x167c, 0x7bf0, 0x1670, 0x7bf5, 0x1664, 0x7bf9, 0x1658,
+ 0x7bfd, 0x164c, 0x7c02, 0x1641, 0x7c06, 0x1635, 0x7c0a, 0x1629,
+ 0x7c0f, 0x161d, 0x7c13, 0x1612, 0x7c17, 0x1606, 0x7c1c, 0x15fa,
+ 0x7c20, 0x15ee, 0x7c24, 0x15e2, 0x7c29, 0x15d7, 0x7c2d, 0x15cb,
+ 0x7c31, 0x15bf, 0x7c36, 0x15b3, 0x7c3a, 0x15a7, 0x7c3e, 0x159b,
+ 0x7c42, 0x1590, 0x7c46, 0x1584, 0x7c4b, 0x1578, 0x7c4f, 0x156c,
+ 0x7c53, 0x1560, 0x7c57, 0x1554, 0x7c5b, 0x1549, 0x7c60, 0x153d,
+ 0x7c64, 0x1531, 0x7c68, 0x1525, 0x7c6c, 0x1519, 0x7c70, 0x150d,
+ 0x7c74, 0x1501, 0x7c79, 0x14f6, 0x7c7d, 0x14ea, 0x7c81, 0x14de,
+ 0x7c85, 0x14d2, 0x7c89, 0x14c6, 0x7c8d, 0x14ba, 0x7c91, 0x14ae,
+ 0x7c95, 0x14a2, 0x7c99, 0x1496, 0x7c9d, 0x148b, 0x7ca1, 0x147f,
+ 0x7ca5, 0x1473, 0x7ca9, 0x1467, 0x7cad, 0x145b, 0x7cb1, 0x144f,
+ 0x7cb5, 0x1443, 0x7cb9, 0x1437, 0x7cbd, 0x142b, 0x7cc1, 0x141f,
+ 0x7cc5, 0x1413, 0x7cc9, 0x1407, 0x7ccd, 0x13fb, 0x7cd1, 0x13f0,
+ 0x7cd5, 0x13e4, 0x7cd9, 0x13d8, 0x7cdd, 0x13cc, 0x7ce0, 0x13c0,
+ 0x7ce4, 0x13b4, 0x7ce8, 0x13a8, 0x7cec, 0x139c, 0x7cf0, 0x1390,
+ 0x7cf4, 0x1384, 0x7cf8, 0x1378, 0x7cfb, 0x136c, 0x7cff, 0x1360,
+ 0x7d03, 0x1354, 0x7d07, 0x1348, 0x7d0b, 0x133c, 0x7d0e, 0x1330,
+ 0x7d12, 0x1324, 0x7d16, 0x1318, 0x7d1a, 0x130c, 0x7d1d, 0x1300,
+ 0x7d21, 0x12f4, 0x7d25, 0x12e8, 0x7d28, 0x12dc, 0x7d2c, 0x12d0,
+ 0x7d30, 0x12c4, 0x7d34, 0x12b8, 0x7d37, 0x12ac, 0x7d3b, 0x12a0,
+ 0x7d3f, 0x1294, 0x7d42, 0x1288, 0x7d46, 0x127c, 0x7d49, 0x1270,
+ 0x7d4d, 0x1264, 0x7d51, 0x1258, 0x7d54, 0x124c, 0x7d58, 0x1240,
+ 0x7d5b, 0x1234, 0x7d5f, 0x1228, 0x7d63, 0x121c, 0x7d66, 0x1210,
+ 0x7d6a, 0x1204, 0x7d6d, 0x11f7, 0x7d71, 0x11eb, 0x7d74, 0x11df,
+ 0x7d78, 0x11d3, 0x7d7b, 0x11c7, 0x7d7f, 0x11bb, 0x7d82, 0x11af,
+ 0x7d86, 0x11a3, 0x7d89, 0x1197, 0x7d8d, 0x118b, 0x7d90, 0x117f,
+ 0x7d93, 0x1173, 0x7d97, 0x1167, 0x7d9a, 0x115a, 0x7d9e, 0x114e,
+ 0x7da1, 0x1142, 0x7da4, 0x1136, 0x7da8, 0x112a, 0x7dab, 0x111e,
+ 0x7daf, 0x1112, 0x7db2, 0x1106, 0x7db5, 0x10fa, 0x7db9, 0x10ed,
+ 0x7dbc, 0x10e1, 0x7dbf, 0x10d5, 0x7dc2, 0x10c9, 0x7dc6, 0x10bd,
+ 0x7dc9, 0x10b1, 0x7dcc, 0x10a5, 0x7dd0, 0x1099, 0x7dd3, 0x108c,
+ 0x7dd6, 0x1080, 0x7dd9, 0x1074, 0x7ddd, 0x1068, 0x7de0, 0x105c,
+ 0x7de3, 0x1050, 0x7de6, 0x1044, 0x7de9, 0x1037, 0x7ded, 0x102b,
+ 0x7df0, 0x101f, 0x7df3, 0x1013, 0x7df6, 0x1007, 0x7df9, 0xffb,
+ 0x7dfc, 0xfee, 0x7dff, 0xfe2, 0x7e03, 0xfd6, 0x7e06, 0xfca,
+ 0x7e09, 0xfbe, 0x7e0c, 0xfb2, 0x7e0f, 0xfa5, 0x7e12, 0xf99,
+ 0x7e15, 0xf8d, 0x7e18, 0xf81, 0x7e1b, 0xf75, 0x7e1e, 0xf68,
+ 0x7e21, 0xf5c, 0x7e24, 0xf50, 0x7e27, 0xf44, 0x7e2a, 0xf38,
+ 0x7e2d, 0xf2b, 0x7e30, 0xf1f, 0x7e33, 0xf13, 0x7e36, 0xf07,
+ 0x7e39, 0xefb, 0x7e3c, 0xeee, 0x7e3f, 0xee2, 0x7e42, 0xed6,
+ 0x7e45, 0xeca, 0x7e48, 0xebd, 0x7e4a, 0xeb1, 0x7e4d, 0xea5,
+ 0x7e50, 0xe99, 0x7e53, 0xe8c, 0x7e56, 0xe80, 0x7e59, 0xe74,
+ 0x7e5c, 0xe68, 0x7e5e, 0xe5c, 0x7e61, 0xe4f, 0x7e64, 0xe43,
+ 0x7e67, 0xe37, 0x7e6a, 0xe2b, 0x7e6c, 0xe1e, 0x7e6f, 0xe12,
+ 0x7e72, 0xe06, 0x7e75, 0xdf9, 0x7e77, 0xded, 0x7e7a, 0xde1,
+ 0x7e7d, 0xdd5, 0x7e80, 0xdc8, 0x7e82, 0xdbc, 0x7e85, 0xdb0,
+ 0x7e88, 0xda4, 0x7e8a, 0xd97, 0x7e8d, 0xd8b, 0x7e90, 0xd7f,
+ 0x7e92, 0xd72, 0x7e95, 0xd66, 0x7e98, 0xd5a, 0x7e9a, 0xd4e,
+ 0x7e9d, 0xd41, 0x7e9f, 0xd35, 0x7ea2, 0xd29, 0x7ea5, 0xd1c,
+ 0x7ea7, 0xd10, 0x7eaa, 0xd04, 0x7eac, 0xcf8, 0x7eaf, 0xceb,
+ 0x7eb1, 0xcdf, 0x7eb4, 0xcd3, 0x7eb6, 0xcc6, 0x7eb9, 0xcba,
+ 0x7ebb, 0xcae, 0x7ebe, 0xca1, 0x7ec0, 0xc95, 0x7ec3, 0xc89,
+ 0x7ec5, 0xc7c, 0x7ec8, 0xc70, 0x7eca, 0xc64, 0x7ecc, 0xc57,
+ 0x7ecf, 0xc4b, 0x7ed1, 0xc3f, 0x7ed4, 0xc32, 0x7ed6, 0xc26,
+ 0x7ed8, 0xc1a, 0x7edb, 0xc0d, 0x7edd, 0xc01, 0x7ee0, 0xbf5,
+ 0x7ee2, 0xbe8, 0x7ee4, 0xbdc, 0x7ee7, 0xbd0, 0x7ee9, 0xbc3,
+ 0x7eeb, 0xbb7, 0x7eed, 0xbab, 0x7ef0, 0xb9e, 0x7ef2, 0xb92,
+ 0x7ef4, 0xb85, 0x7ef7, 0xb79, 0x7ef9, 0xb6d, 0x7efb, 0xb60,
+ 0x7efd, 0xb54, 0x7f00, 0xb48, 0x7f02, 0xb3b, 0x7f04, 0xb2f,
+ 0x7f06, 0xb23, 0x7f08, 0xb16, 0x7f0a, 0xb0a, 0x7f0d, 0xafd,
+ 0x7f0f, 0xaf1, 0x7f11, 0xae5, 0x7f13, 0xad8, 0x7f15, 0xacc,
+ 0x7f17, 0xac0, 0x7f19, 0xab3, 0x7f1c, 0xaa7, 0x7f1e, 0xa9a,
+ 0x7f20, 0xa8e, 0x7f22, 0xa82, 0x7f24, 0xa75, 0x7f26, 0xa69,
+ 0x7f28, 0xa5c, 0x7f2a, 0xa50, 0x7f2c, 0xa44, 0x7f2e, 0xa37,
+ 0x7f30, 0xa2b, 0x7f32, 0xa1e, 0x7f34, 0xa12, 0x7f36, 0xa06,
+ 0x7f38, 0x9f9, 0x7f3a, 0x9ed, 0x7f3c, 0x9e0, 0x7f3e, 0x9d4,
+ 0x7f40, 0x9c7, 0x7f42, 0x9bb, 0x7f43, 0x9af, 0x7f45, 0x9a2,
+ 0x7f47, 0x996, 0x7f49, 0x989, 0x7f4b, 0x97d, 0x7f4d, 0x970,
+ 0x7f4f, 0x964, 0x7f51, 0x958, 0x7f52, 0x94b, 0x7f54, 0x93f,
+ 0x7f56, 0x932, 0x7f58, 0x926, 0x7f5a, 0x919, 0x7f5b, 0x90d,
+ 0x7f5d, 0x901, 0x7f5f, 0x8f4, 0x7f61, 0x8e8, 0x7f62, 0x8db,
+ 0x7f64, 0x8cf, 0x7f66, 0x8c2, 0x7f68, 0x8b6, 0x7f69, 0x8a9,
+ 0x7f6b, 0x89d, 0x7f6d, 0x891, 0x7f6e, 0x884, 0x7f70, 0x878,
+ 0x7f72, 0x86b, 0x7f73, 0x85f, 0x7f75, 0x852, 0x7f77, 0x846,
+ 0x7f78, 0x839, 0x7f7a, 0x82d, 0x7f7b, 0x820, 0x7f7d, 0x814,
+ 0x7f7f, 0x807, 0x7f80, 0x7fb, 0x7f82, 0x7ef, 0x7f83, 0x7e2,
+ 0x7f85, 0x7d6, 0x7f86, 0x7c9, 0x7f88, 0x7bd, 0x7f89, 0x7b0,
+ 0x7f8b, 0x7a4, 0x7f8c, 0x797, 0x7f8e, 0x78b, 0x7f8f, 0x77e,
+ 0x7f91, 0x772, 0x7f92, 0x765, 0x7f94, 0x759, 0x7f95, 0x74c,
+ 0x7f97, 0x740, 0x7f98, 0x733, 0x7f99, 0x727, 0x7f9b, 0x71a,
+ 0x7f9c, 0x70e, 0x7f9e, 0x701, 0x7f9f, 0x6f5, 0x7fa0, 0x6e8,
+ 0x7fa2, 0x6dc, 0x7fa3, 0x6cf, 0x7fa4, 0x6c3, 0x7fa6, 0x6b6,
+ 0x7fa7, 0x6aa, 0x7fa8, 0x69d, 0x7faa, 0x691, 0x7fab, 0x684,
+ 0x7fac, 0x678, 0x7fad, 0x66b, 0x7faf, 0x65f, 0x7fb0, 0x652,
+ 0x7fb1, 0x646, 0x7fb2, 0x639, 0x7fb4, 0x62d, 0x7fb5, 0x620,
+ 0x7fb6, 0x614, 0x7fb7, 0x607, 0x7fb8, 0x5fb, 0x7fb9, 0x5ee,
+ 0x7fbb, 0x5e2, 0x7fbc, 0x5d5, 0x7fbd, 0x5c9, 0x7fbe, 0x5bc,
+ 0x7fbf, 0x5b0, 0x7fc0, 0x5a3, 0x7fc1, 0x597, 0x7fc3, 0x58a,
+ 0x7fc4, 0x57e, 0x7fc5, 0x571, 0x7fc6, 0x565, 0x7fc7, 0x558,
+ 0x7fc8, 0x54c, 0x7fc9, 0x53f, 0x7fca, 0x533, 0x7fcb, 0x526,
+ 0x7fcc, 0x51a, 0x7fcd, 0x50d, 0x7fce, 0x500, 0x7fcf, 0x4f4,
+ 0x7fd0, 0x4e7, 0x7fd1, 0x4db, 0x7fd2, 0x4ce, 0x7fd3, 0x4c2,
+ 0x7fd4, 0x4b5, 0x7fd5, 0x4a9, 0x7fd5, 0x49c, 0x7fd6, 0x490,
+ 0x7fd7, 0x483, 0x7fd8, 0x477, 0x7fd9, 0x46a, 0x7fda, 0x45e,
+ 0x7fdb, 0x451, 0x7fdc, 0x444, 0x7fdc, 0x438, 0x7fdd, 0x42b,
+ 0x7fde, 0x41f, 0x7fdf, 0x412, 0x7fe0, 0x406, 0x7fe0, 0x3f9,
+ 0x7fe1, 0x3ed, 0x7fe2, 0x3e0, 0x7fe3, 0x3d4, 0x7fe3, 0x3c7,
+ 0x7fe4, 0x3bb, 0x7fe5, 0x3ae, 0x7fe6, 0x3a1, 0x7fe6, 0x395,
+ 0x7fe7, 0x388, 0x7fe8, 0x37c, 0x7fe8, 0x36f, 0x7fe9, 0x363,
+ 0x7fea, 0x356, 0x7fea, 0x34a, 0x7feb, 0x33d, 0x7fec, 0x330,
+ 0x7fec, 0x324, 0x7fed, 0x317, 0x7fed, 0x30b, 0x7fee, 0x2fe,
+ 0x7fef, 0x2f2, 0x7fef, 0x2e5, 0x7ff0, 0x2d9, 0x7ff0, 0x2cc,
+ 0x7ff1, 0x2c0, 0x7ff1, 0x2b3, 0x7ff2, 0x2a6, 0x7ff2, 0x29a,
+ 0x7ff3, 0x28d, 0x7ff3, 0x281, 0x7ff4, 0x274, 0x7ff4, 0x268,
+ 0x7ff5, 0x25b, 0x7ff5, 0x24e, 0x7ff6, 0x242, 0x7ff6, 0x235,
+ 0x7ff7, 0x229, 0x7ff7, 0x21c, 0x7ff7, 0x210, 0x7ff8, 0x203,
+ 0x7ff8, 0x1f7, 0x7ff9, 0x1ea, 0x7ff9, 0x1dd, 0x7ff9, 0x1d1,
+ 0x7ffa, 0x1c4, 0x7ffa, 0x1b8, 0x7ffa, 0x1ab, 0x7ffb, 0x19f,
+ 0x7ffb, 0x192, 0x7ffb, 0x186, 0x7ffc, 0x179, 0x7ffc, 0x16c,
+ 0x7ffc, 0x160, 0x7ffc, 0x153, 0x7ffd, 0x147, 0x7ffd, 0x13a,
+ 0x7ffd, 0x12e, 0x7ffd, 0x121, 0x7ffe, 0x114, 0x7ffe, 0x108,
+ 0x7ffe, 0xfb, 0x7ffe, 0xef, 0x7ffe, 0xe2, 0x7fff, 0xd6,
+ 0x7fff, 0xc9, 0x7fff, 0xbc, 0x7fff, 0xb0, 0x7fff, 0xa3,
+ 0x7fff, 0x97, 0x7fff, 0x8a, 0x7fff, 0x7e, 0x7fff, 0x71,
+ 0x7fff, 0x65, 0x7fff, 0x58, 0x7fff, 0x4b, 0x7fff, 0x3f,
+ 0x7fff, 0x32, 0x7fff, 0x26, 0x7fff, 0x19, 0x7fff, 0xd,
+ 0x7fff, 0x0, 0x7fff, 0xfff3, 0x7fff, 0xffe7, 0x7fff, 0xffda,
+ 0x7fff, 0xffce, 0x7fff, 0xffc1, 0x7fff, 0xffb5, 0x7fff, 0xffa8,
+ 0x7fff, 0xff9b, 0x7fff, 0xff8f, 0x7fff, 0xff82, 0x7fff, 0xff76,
+ 0x7fff, 0xff69, 0x7fff, 0xff5d, 0x7fff, 0xff50, 0x7fff, 0xff44,
+ 0x7fff, 0xff37, 0x7fff, 0xff2a, 0x7ffe, 0xff1e, 0x7ffe, 0xff11,
+ 0x7ffe, 0xff05, 0x7ffe, 0xfef8, 0x7ffe, 0xfeec, 0x7ffd, 0xfedf,
+ 0x7ffd, 0xfed2, 0x7ffd, 0xfec6, 0x7ffd, 0xfeb9, 0x7ffc, 0xfead,
+ 0x7ffc, 0xfea0, 0x7ffc, 0xfe94, 0x7ffc, 0xfe87, 0x7ffb, 0xfe7a,
+ 0x7ffb, 0xfe6e, 0x7ffb, 0xfe61, 0x7ffa, 0xfe55, 0x7ffa, 0xfe48,
+ 0x7ffa, 0xfe3c, 0x7ff9, 0xfe2f, 0x7ff9, 0xfe23, 0x7ff9, 0xfe16,
+ 0x7ff8, 0xfe09, 0x7ff8, 0xfdfd, 0x7ff7, 0xfdf0, 0x7ff7, 0xfde4,
+ 0x7ff7, 0xfdd7, 0x7ff6, 0xfdcb, 0x7ff6, 0xfdbe, 0x7ff5, 0xfdb2,
+ 0x7ff5, 0xfda5, 0x7ff4, 0xfd98, 0x7ff4, 0xfd8c, 0x7ff3, 0xfd7f,
+ 0x7ff3, 0xfd73, 0x7ff2, 0xfd66, 0x7ff2, 0xfd5a, 0x7ff1, 0xfd4d,
+ 0x7ff1, 0xfd40, 0x7ff0, 0xfd34, 0x7ff0, 0xfd27, 0x7fef, 0xfd1b,
+ 0x7fef, 0xfd0e, 0x7fee, 0xfd02, 0x7fed, 0xfcf5, 0x7fed, 0xfce9,
+ 0x7fec, 0xfcdc, 0x7fec, 0xfcd0, 0x7feb, 0xfcc3, 0x7fea, 0xfcb6,
+ 0x7fea, 0xfcaa, 0x7fe9, 0xfc9d, 0x7fe8, 0xfc91, 0x7fe8, 0xfc84,
+ 0x7fe7, 0xfc78, 0x7fe6, 0xfc6b, 0x7fe6, 0xfc5f, 0x7fe5, 0xfc52,
+ 0x7fe4, 0xfc45, 0x7fe3, 0xfc39, 0x7fe3, 0xfc2c, 0x7fe2, 0xfc20,
+ 0x7fe1, 0xfc13, 0x7fe0, 0xfc07, 0x7fe0, 0xfbfa, 0x7fdf, 0xfbee,
+ 0x7fde, 0xfbe1, 0x7fdd, 0xfbd5, 0x7fdc, 0xfbc8, 0x7fdc, 0xfbbc,
+ 0x7fdb, 0xfbaf, 0x7fda, 0xfba2, 0x7fd9, 0xfb96, 0x7fd8, 0xfb89,
+ 0x7fd7, 0xfb7d, 0x7fd6, 0xfb70, 0x7fd5, 0xfb64, 0x7fd5, 0xfb57,
+ 0x7fd4, 0xfb4b, 0x7fd3, 0xfb3e, 0x7fd2, 0xfb32, 0x7fd1, 0xfb25,
+ 0x7fd0, 0xfb19, 0x7fcf, 0xfb0c, 0x7fce, 0xfb00, 0x7fcd, 0xfaf3,
+ 0x7fcc, 0xfae6, 0x7fcb, 0xfada, 0x7fca, 0xfacd, 0x7fc9, 0xfac1,
+ 0x7fc8, 0xfab4, 0x7fc7, 0xfaa8, 0x7fc6, 0xfa9b, 0x7fc5, 0xfa8f,
+ 0x7fc4, 0xfa82, 0x7fc3, 0xfa76, 0x7fc1, 0xfa69, 0x7fc0, 0xfa5d,
+ 0x7fbf, 0xfa50, 0x7fbe, 0xfa44, 0x7fbd, 0xfa37, 0x7fbc, 0xfa2b,
+ 0x7fbb, 0xfa1e, 0x7fb9, 0xfa12, 0x7fb8, 0xfa05, 0x7fb7, 0xf9f9,
+ 0x7fb6, 0xf9ec, 0x7fb5, 0xf9e0, 0x7fb4, 0xf9d3, 0x7fb2, 0xf9c7,
+ 0x7fb1, 0xf9ba, 0x7fb0, 0xf9ae, 0x7faf, 0xf9a1, 0x7fad, 0xf995,
+ 0x7fac, 0xf988, 0x7fab, 0xf97c, 0x7faa, 0xf96f, 0x7fa8, 0xf963,
+ 0x7fa7, 0xf956, 0x7fa6, 0xf94a, 0x7fa4, 0xf93d, 0x7fa3, 0xf931,
+ 0x7fa2, 0xf924, 0x7fa0, 0xf918, 0x7f9f, 0xf90b, 0x7f9e, 0xf8ff,
+ 0x7f9c, 0xf8f2, 0x7f9b, 0xf8e6, 0x7f99, 0xf8d9, 0x7f98, 0xf8cd,
+ 0x7f97, 0xf8c0, 0x7f95, 0xf8b4, 0x7f94, 0xf8a7, 0x7f92, 0xf89b,
+ 0x7f91, 0xf88e, 0x7f8f, 0xf882, 0x7f8e, 0xf875, 0x7f8c, 0xf869,
+ 0x7f8b, 0xf85c, 0x7f89, 0xf850, 0x7f88, 0xf843, 0x7f86, 0xf837,
+ 0x7f85, 0xf82a, 0x7f83, 0xf81e, 0x7f82, 0xf811, 0x7f80, 0xf805,
+ 0x7f7f, 0xf7f9, 0x7f7d, 0xf7ec, 0x7f7b, 0xf7e0, 0x7f7a, 0xf7d3,
+ 0x7f78, 0xf7c7, 0x7f77, 0xf7ba, 0x7f75, 0xf7ae, 0x7f73, 0xf7a1,
+ 0x7f72, 0xf795, 0x7f70, 0xf788, 0x7f6e, 0xf77c, 0x7f6d, 0xf76f,
+ 0x7f6b, 0xf763, 0x7f69, 0xf757, 0x7f68, 0xf74a, 0x7f66, 0xf73e,
+ 0x7f64, 0xf731, 0x7f62, 0xf725, 0x7f61, 0xf718, 0x7f5f, 0xf70c,
+ 0x7f5d, 0xf6ff, 0x7f5b, 0xf6f3, 0x7f5a, 0xf6e7, 0x7f58, 0xf6da,
+ 0x7f56, 0xf6ce, 0x7f54, 0xf6c1, 0x7f52, 0xf6b5, 0x7f51, 0xf6a8,
+ 0x7f4f, 0xf69c, 0x7f4d, 0xf690, 0x7f4b, 0xf683, 0x7f49, 0xf677,
+ 0x7f47, 0xf66a, 0x7f45, 0xf65e, 0x7f43, 0xf651, 0x7f42, 0xf645,
+ 0x7f40, 0xf639, 0x7f3e, 0xf62c, 0x7f3c, 0xf620, 0x7f3a, 0xf613,
+ 0x7f38, 0xf607, 0x7f36, 0xf5fa, 0x7f34, 0xf5ee, 0x7f32, 0xf5e2,
+ 0x7f30, 0xf5d5, 0x7f2e, 0xf5c9, 0x7f2c, 0xf5bc, 0x7f2a, 0xf5b0,
+ 0x7f28, 0xf5a4, 0x7f26, 0xf597, 0x7f24, 0xf58b, 0x7f22, 0xf57e,
+ 0x7f20, 0xf572, 0x7f1e, 0xf566, 0x7f1c, 0xf559, 0x7f19, 0xf54d,
+ 0x7f17, 0xf540, 0x7f15, 0xf534, 0x7f13, 0xf528, 0x7f11, 0xf51b,
+ 0x7f0f, 0xf50f, 0x7f0d, 0xf503, 0x7f0a, 0xf4f6, 0x7f08, 0xf4ea,
+ 0x7f06, 0xf4dd, 0x7f04, 0xf4d1, 0x7f02, 0xf4c5, 0x7f00, 0xf4b8,
+ 0x7efd, 0xf4ac, 0x7efb, 0xf4a0, 0x7ef9, 0xf493, 0x7ef7, 0xf487,
+ 0x7ef4, 0xf47b, 0x7ef2, 0xf46e, 0x7ef0, 0xf462, 0x7eed, 0xf455,
+ 0x7eeb, 0xf449, 0x7ee9, 0xf43d, 0x7ee7, 0xf430, 0x7ee4, 0xf424,
+ 0x7ee2, 0xf418, 0x7ee0, 0xf40b, 0x7edd, 0xf3ff, 0x7edb, 0xf3f3,
+ 0x7ed8, 0xf3e6, 0x7ed6, 0xf3da, 0x7ed4, 0xf3ce, 0x7ed1, 0xf3c1,
+ 0x7ecf, 0xf3b5, 0x7ecc, 0xf3a9, 0x7eca, 0xf39c, 0x7ec8, 0xf390,
+ 0x7ec5, 0xf384, 0x7ec3, 0xf377, 0x7ec0, 0xf36b, 0x7ebe, 0xf35f,
+ 0x7ebb, 0xf352, 0x7eb9, 0xf346, 0x7eb6, 0xf33a, 0x7eb4, 0xf32d,
+ 0x7eb1, 0xf321, 0x7eaf, 0xf315, 0x7eac, 0xf308, 0x7eaa, 0xf2fc,
+ 0x7ea7, 0xf2f0, 0x7ea5, 0xf2e4, 0x7ea2, 0xf2d7, 0x7e9f, 0xf2cb,
+ 0x7e9d, 0xf2bf, 0x7e9a, 0xf2b2, 0x7e98, 0xf2a6, 0x7e95, 0xf29a,
+ 0x7e92, 0xf28e, 0x7e90, 0xf281, 0x7e8d, 0xf275, 0x7e8a, 0xf269,
+ 0x7e88, 0xf25c, 0x7e85, 0xf250, 0x7e82, 0xf244, 0x7e80, 0xf238,
+ 0x7e7d, 0xf22b, 0x7e7a, 0xf21f, 0x7e77, 0xf213, 0x7e75, 0xf207,
+ 0x7e72, 0xf1fa, 0x7e6f, 0xf1ee, 0x7e6c, 0xf1e2, 0x7e6a, 0xf1d5,
+ 0x7e67, 0xf1c9, 0x7e64, 0xf1bd, 0x7e61, 0xf1b1, 0x7e5e, 0xf1a4,
+ 0x7e5c, 0xf198, 0x7e59, 0xf18c, 0x7e56, 0xf180, 0x7e53, 0xf174,
+ 0x7e50, 0xf167, 0x7e4d, 0xf15b, 0x7e4a, 0xf14f, 0x7e48, 0xf143,
+ 0x7e45, 0xf136, 0x7e42, 0xf12a, 0x7e3f, 0xf11e, 0x7e3c, 0xf112,
+ 0x7e39, 0xf105, 0x7e36, 0xf0f9, 0x7e33, 0xf0ed, 0x7e30, 0xf0e1,
+ 0x7e2d, 0xf0d5, 0x7e2a, 0xf0c8, 0x7e27, 0xf0bc, 0x7e24, 0xf0b0,
+ 0x7e21, 0xf0a4, 0x7e1e, 0xf098, 0x7e1b, 0xf08b, 0x7e18, 0xf07f,
+ 0x7e15, 0xf073, 0x7e12, 0xf067, 0x7e0f, 0xf05b, 0x7e0c, 0xf04e,
+ 0x7e09, 0xf042, 0x7e06, 0xf036, 0x7e03, 0xf02a, 0x7dff, 0xf01e,
+ 0x7dfc, 0xf012, 0x7df9, 0xf005, 0x7df6, 0xeff9, 0x7df3, 0xefed,
+ 0x7df0, 0xefe1, 0x7ded, 0xefd5, 0x7de9, 0xefc9, 0x7de6, 0xefbc,
+ 0x7de3, 0xefb0, 0x7de0, 0xefa4, 0x7ddd, 0xef98, 0x7dd9, 0xef8c,
+ 0x7dd6, 0xef80, 0x7dd3, 0xef74, 0x7dd0, 0xef67, 0x7dcc, 0xef5b,
+ 0x7dc9, 0xef4f, 0x7dc6, 0xef43, 0x7dc2, 0xef37, 0x7dbf, 0xef2b,
+ 0x7dbc, 0xef1f, 0x7db9, 0xef13, 0x7db5, 0xef06, 0x7db2, 0xeefa,
+ 0x7daf, 0xeeee, 0x7dab, 0xeee2, 0x7da8, 0xeed6, 0x7da4, 0xeeca,
+ 0x7da1, 0xeebe, 0x7d9e, 0xeeb2, 0x7d9a, 0xeea6, 0x7d97, 0xee99,
+ 0x7d93, 0xee8d, 0x7d90, 0xee81, 0x7d8d, 0xee75, 0x7d89, 0xee69,
+ 0x7d86, 0xee5d, 0x7d82, 0xee51, 0x7d7f, 0xee45, 0x7d7b, 0xee39,
+ 0x7d78, 0xee2d, 0x7d74, 0xee21, 0x7d71, 0xee15, 0x7d6d, 0xee09,
+ 0x7d6a, 0xedfc, 0x7d66, 0xedf0, 0x7d63, 0xede4, 0x7d5f, 0xedd8,
+ 0x7d5b, 0xedcc, 0x7d58, 0xedc0, 0x7d54, 0xedb4, 0x7d51, 0xeda8,
+ 0x7d4d, 0xed9c, 0x7d49, 0xed90, 0x7d46, 0xed84, 0x7d42, 0xed78,
+ 0x7d3f, 0xed6c, 0x7d3b, 0xed60, 0x7d37, 0xed54, 0x7d34, 0xed48,
+ 0x7d30, 0xed3c, 0x7d2c, 0xed30, 0x7d28, 0xed24, 0x7d25, 0xed18,
+ 0x7d21, 0xed0c, 0x7d1d, 0xed00, 0x7d1a, 0xecf4, 0x7d16, 0xece8,
+ 0x7d12, 0xecdc, 0x7d0e, 0xecd0, 0x7d0b, 0xecc4, 0x7d07, 0xecb8,
+ 0x7d03, 0xecac, 0x7cff, 0xeca0, 0x7cfb, 0xec94, 0x7cf8, 0xec88,
+ 0x7cf4, 0xec7c, 0x7cf0, 0xec70, 0x7cec, 0xec64, 0x7ce8, 0xec58,
+ 0x7ce4, 0xec4c, 0x7ce0, 0xec40, 0x7cdd, 0xec34, 0x7cd9, 0xec28,
+ 0x7cd5, 0xec1c, 0x7cd1, 0xec10, 0x7ccd, 0xec05, 0x7cc9, 0xebf9,
+ 0x7cc5, 0xebed, 0x7cc1, 0xebe1, 0x7cbd, 0xebd5, 0x7cb9, 0xebc9,
+ 0x7cb5, 0xebbd, 0x7cb1, 0xebb1, 0x7cad, 0xeba5, 0x7ca9, 0xeb99,
+ 0x7ca5, 0xeb8d, 0x7ca1, 0xeb81, 0x7c9d, 0xeb75, 0x7c99, 0xeb6a,
+ 0x7c95, 0xeb5e, 0x7c91, 0xeb52, 0x7c8d, 0xeb46, 0x7c89, 0xeb3a,
+ 0x7c85, 0xeb2e, 0x7c81, 0xeb22, 0x7c7d, 0xeb16, 0x7c79, 0xeb0a,
+ 0x7c74, 0xeaff, 0x7c70, 0xeaf3, 0x7c6c, 0xeae7, 0x7c68, 0xeadb,
+ 0x7c64, 0xeacf, 0x7c60, 0xeac3, 0x7c5b, 0xeab7, 0x7c57, 0xeaac,
+ 0x7c53, 0xeaa0, 0x7c4f, 0xea94, 0x7c4b, 0xea88, 0x7c46, 0xea7c,
+ 0x7c42, 0xea70, 0x7c3e, 0xea65, 0x7c3a, 0xea59, 0x7c36, 0xea4d,
+ 0x7c31, 0xea41, 0x7c2d, 0xea35, 0x7c29, 0xea29, 0x7c24, 0xea1e,
+ 0x7c20, 0xea12, 0x7c1c, 0xea06, 0x7c17, 0xe9fa, 0x7c13, 0xe9ee,
+ 0x7c0f, 0xe9e3, 0x7c0a, 0xe9d7, 0x7c06, 0xe9cb, 0x7c02, 0xe9bf,
+ 0x7bfd, 0xe9b4, 0x7bf9, 0xe9a8, 0x7bf5, 0xe99c, 0x7bf0, 0xe990,
+ 0x7bec, 0xe984, 0x7be7, 0xe979, 0x7be3, 0xe96d, 0x7bde, 0xe961,
+ 0x7bda, 0xe955, 0x7bd6, 0xe94a, 0x7bd1, 0xe93e, 0x7bcd, 0xe932,
+ 0x7bc8, 0xe926, 0x7bc4, 0xe91b, 0x7bbf, 0xe90f, 0x7bbb, 0xe903,
+ 0x7bb6, 0xe8f7, 0x7bb2, 0xe8ec, 0x7bad, 0xe8e0, 0x7ba9, 0xe8d4,
+ 0x7ba4, 0xe8c9, 0x7b9f, 0xe8bd, 0x7b9b, 0xe8b1, 0x7b96, 0xe8a5,
+ 0x7b92, 0xe89a, 0x7b8d, 0xe88e, 0x7b88, 0xe882, 0x7b84, 0xe877,
+ 0x7b7f, 0xe86b, 0x7b7b, 0xe85f, 0x7b76, 0xe854, 0x7b71, 0xe848,
+ 0x7b6d, 0xe83c, 0x7b68, 0xe831, 0x7b63, 0xe825, 0x7b5f, 0xe819,
+ 0x7b5a, 0xe80e, 0x7b55, 0xe802, 0x7b50, 0xe7f6, 0x7b4c, 0xe7eb,
+ 0x7b47, 0xe7df, 0x7b42, 0xe7d3, 0x7b3e, 0xe7c8, 0x7b39, 0xe7bc,
+ 0x7b34, 0xe7b1, 0x7b2f, 0xe7a5, 0x7b2a, 0xe799, 0x7b26, 0xe78e,
+ 0x7b21, 0xe782, 0x7b1c, 0xe777, 0x7b17, 0xe76b, 0x7b12, 0xe75f,
+ 0x7b0e, 0xe754, 0x7b09, 0xe748, 0x7b04, 0xe73d, 0x7aff, 0xe731,
+ 0x7afa, 0xe725, 0x7af5, 0xe71a, 0x7af0, 0xe70e, 0x7aeb, 0xe703,
+ 0x7ae6, 0xe6f7, 0x7ae2, 0xe6ec, 0x7add, 0xe6e0, 0x7ad8, 0xe6d4,
+ 0x7ad3, 0xe6c9, 0x7ace, 0xe6bd, 0x7ac9, 0xe6b2, 0x7ac4, 0xe6a6,
+ 0x7abf, 0xe69b, 0x7aba, 0xe68f, 0x7ab5, 0xe684, 0x7ab0, 0xe678,
+ 0x7aab, 0xe66d, 0x7aa6, 0xe661, 0x7aa1, 0xe656, 0x7a9c, 0xe64a,
+ 0x7a97, 0xe63f, 0x7a92, 0xe633, 0x7a8d, 0xe628, 0x7a88, 0xe61c,
+ 0x7a82, 0xe611, 0x7a7d, 0xe605, 0x7a78, 0xe5fa, 0x7a73, 0xe5ee,
+ 0x7a6e, 0xe5e3, 0x7a69, 0xe5d7, 0x7a64, 0xe5cc, 0x7a5f, 0xe5c0,
+ 0x7a59, 0xe5b5, 0x7a54, 0xe5a9, 0x7a4f, 0xe59e, 0x7a4a, 0xe592,
+ 0x7a45, 0xe587, 0x7a3f, 0xe57c, 0x7a3a, 0xe570, 0x7a35, 0xe565,
+ 0x7a30, 0xe559, 0x7a2b, 0xe54e, 0x7a25, 0xe542, 0x7a20, 0xe537,
+ 0x7a1b, 0xe52c, 0x7a16, 0xe520, 0x7a10, 0xe515, 0x7a0b, 0xe509,
+ 0x7a06, 0xe4fe, 0x7a00, 0xe4f3, 0x79fb, 0xe4e7, 0x79f6, 0xe4dc,
+ 0x79f0, 0xe4d0, 0x79eb, 0xe4c5, 0x79e6, 0xe4ba, 0x79e0, 0xe4ae,
+ 0x79db, 0xe4a3, 0x79d6, 0xe498, 0x79d0, 0xe48c, 0x79cb, 0xe481,
+ 0x79c5, 0xe476, 0x79c0, 0xe46a, 0x79bb, 0xe45f, 0x79b5, 0xe454,
+ 0x79b0, 0xe448, 0x79aa, 0xe43d, 0x79a5, 0xe432, 0x799f, 0xe426,
+ 0x799a, 0xe41b, 0x7994, 0xe410, 0x798f, 0xe404, 0x7989, 0xe3f9,
+ 0x7984, 0xe3ee, 0x797e, 0xe3e2, 0x7979, 0xe3d7, 0x7973, 0xe3cc,
+ 0x796e, 0xe3c1, 0x7968, 0xe3b5, 0x7963, 0xe3aa, 0x795d, 0xe39f,
+ 0x7958, 0xe394, 0x7952, 0xe388, 0x794c, 0xe37d, 0x7947, 0xe372,
+ 0x7941, 0xe367, 0x793b, 0xe35b, 0x7936, 0xe350, 0x7930, 0xe345,
+ 0x792b, 0xe33a, 0x7925, 0xe32e, 0x791f, 0xe323, 0x791a, 0xe318,
+ 0x7914, 0xe30d, 0x790e, 0xe301, 0x7909, 0xe2f6, 0x7903, 0xe2eb,
+ 0x78fd, 0xe2e0, 0x78f7, 0xe2d5, 0x78f2, 0xe2ca, 0x78ec, 0xe2be,
+ 0x78e6, 0xe2b3, 0x78e0, 0xe2a8, 0x78db, 0xe29d, 0x78d5, 0xe292,
+ 0x78cf, 0xe287, 0x78c9, 0xe27b, 0x78c3, 0xe270, 0x78be, 0xe265,
+ 0x78b8, 0xe25a, 0x78b2, 0xe24f, 0x78ac, 0xe244, 0x78a6, 0xe239,
+ 0x78a1, 0xe22d, 0x789b, 0xe222, 0x7895, 0xe217, 0x788f, 0xe20c,
+ 0x7889, 0xe201, 0x7883, 0xe1f6, 0x787d, 0xe1eb, 0x7877, 0xe1e0,
+ 0x7871, 0xe1d5, 0x786b, 0xe1ca, 0x7866, 0xe1be, 0x7860, 0xe1b3,
+ 0x785a, 0xe1a8, 0x7854, 0xe19d, 0x784e, 0xe192, 0x7848, 0xe187,
+ 0x7842, 0xe17c, 0x783c, 0xe171, 0x7836, 0xe166, 0x7830, 0xe15b,
+ 0x782a, 0xe150, 0x7824, 0xe145, 0x781e, 0xe13a, 0x7818, 0xe12f,
+ 0x7812, 0xe124, 0x780b, 0xe119, 0x7805, 0xe10e, 0x77ff, 0xe103,
+ 0x77f9, 0xe0f8, 0x77f3, 0xe0ed, 0x77ed, 0xe0e2, 0x77e7, 0xe0d7,
+ 0x77e1, 0xe0cc, 0x77db, 0xe0c1, 0x77d5, 0xe0b6, 0x77ce, 0xe0ab,
+ 0x77c8, 0xe0a0, 0x77c2, 0xe095, 0x77bc, 0xe08a, 0x77b6, 0xe07f,
+ 0x77b0, 0xe074, 0x77a9, 0xe069, 0x77a3, 0xe05e, 0x779d, 0xe054,
+ 0x7797, 0xe049, 0x7790, 0xe03e, 0x778a, 0xe033, 0x7784, 0xe028,
+ 0x777e, 0xe01d, 0x7777, 0xe012, 0x7771, 0xe007, 0x776b, 0xdffc,
+ 0x7765, 0xdff1, 0x775e, 0xdfe7, 0x7758, 0xdfdc, 0x7752, 0xdfd1,
+ 0x774b, 0xdfc6, 0x7745, 0xdfbb, 0x773f, 0xdfb0, 0x7738, 0xdfa5,
+ 0x7732, 0xdf9b, 0x772c, 0xdf90, 0x7725, 0xdf85, 0x771f, 0xdf7a,
+ 0x7718, 0xdf6f, 0x7712, 0xdf65, 0x770c, 0xdf5a, 0x7705, 0xdf4f,
+ 0x76ff, 0xdf44, 0x76f8, 0xdf39, 0x76f2, 0xdf2f, 0x76eb, 0xdf24,
+ 0x76e5, 0xdf19, 0x76df, 0xdf0e, 0x76d8, 0xdf03, 0x76d2, 0xdef9,
+ 0x76cb, 0xdeee, 0x76c5, 0xdee3, 0x76be, 0xded8, 0x76b8, 0xdece,
+ 0x76b1, 0xdec3, 0x76ab, 0xdeb8, 0x76a4, 0xdead, 0x769d, 0xdea3,
+ 0x7697, 0xde98, 0x7690, 0xde8d, 0x768a, 0xde83, 0x7683, 0xde78,
+ 0x767d, 0xde6d, 0x7676, 0xde62, 0x766f, 0xde58, 0x7669, 0xde4d,
+ 0x7662, 0xde42, 0x765c, 0xde38, 0x7655, 0xde2d, 0x764e, 0xde22,
+ 0x7648, 0xde18, 0x7641, 0xde0d, 0x763a, 0xde02, 0x7634, 0xddf8,
+ 0x762d, 0xdded, 0x7626, 0xdde2, 0x7620, 0xddd8, 0x7619, 0xddcd,
+ 0x7612, 0xddc3, 0x760b, 0xddb8, 0x7605, 0xddad, 0x75fe, 0xdda3,
+ 0x75f7, 0xdd98, 0x75f0, 0xdd8e, 0x75ea, 0xdd83, 0x75e3, 0xdd78,
+ 0x75dc, 0xdd6e, 0x75d5, 0xdd63, 0x75ce, 0xdd59, 0x75c8, 0xdd4e,
+ 0x75c1, 0xdd44, 0x75ba, 0xdd39, 0x75b3, 0xdd2e, 0x75ac, 0xdd24,
+ 0x75a5, 0xdd19, 0x759f, 0xdd0f, 0x7598, 0xdd04, 0x7591, 0xdcfa,
+ 0x758a, 0xdcef, 0x7583, 0xdce5, 0x757c, 0xdcda, 0x7575, 0xdcd0,
+ 0x756e, 0xdcc5, 0x7567, 0xdcbb, 0x7561, 0xdcb0, 0x755a, 0xdca6,
+ 0x7553, 0xdc9b, 0x754c, 0xdc91, 0x7545, 0xdc86, 0x753e, 0xdc7c,
+ 0x7537, 0xdc72, 0x7530, 0xdc67, 0x7529, 0xdc5d, 0x7522, 0xdc52,
+ 0x751b, 0xdc48, 0x7514, 0xdc3d, 0x750d, 0xdc33, 0x7506, 0xdc29,
+ 0x74ff, 0xdc1e, 0x74f8, 0xdc14, 0x74f1, 0xdc09, 0x74ea, 0xdbff,
+ 0x74e2, 0xdbf5, 0x74db, 0xdbea, 0x74d4, 0xdbe0, 0x74cd, 0xdbd5,
+ 0x74c6, 0xdbcb, 0x74bf, 0xdbc1, 0x74b8, 0xdbb6, 0x74b1, 0xdbac,
+ 0x74aa, 0xdba2, 0x74a2, 0xdb97, 0x749b, 0xdb8d, 0x7494, 0xdb83,
+ 0x748d, 0xdb78, 0x7486, 0xdb6e, 0x747f, 0xdb64, 0x7477, 0xdb59,
+ 0x7470, 0xdb4f, 0x7469, 0xdb45, 0x7462, 0xdb3b, 0x745b, 0xdb30,
+ 0x7453, 0xdb26, 0x744c, 0xdb1c, 0x7445, 0xdb11, 0x743e, 0xdb07,
+ 0x7436, 0xdafd, 0x742f, 0xdaf3, 0x7428, 0xdae8, 0x7420, 0xdade,
+ 0x7419, 0xdad4, 0x7412, 0xdaca, 0x740b, 0xdabf, 0x7403, 0xdab5,
+ 0x73fc, 0xdaab, 0x73f5, 0xdaa1, 0x73ed, 0xda97, 0x73e6, 0xda8c,
+ 0x73df, 0xda82, 0x73d7, 0xda78, 0x73d0, 0xda6e, 0x73c8, 0xda64,
+ 0x73c1, 0xda5a, 0x73ba, 0xda4f, 0x73b2, 0xda45, 0x73ab, 0xda3b,
+ 0x73a3, 0xda31, 0x739c, 0xda27, 0x7395, 0xda1d, 0x738d, 0xda13,
+ 0x7386, 0xda08, 0x737e, 0xd9fe, 0x7377, 0xd9f4, 0x736f, 0xd9ea,
+ 0x7368, 0xd9e0, 0x7360, 0xd9d6, 0x7359, 0xd9cc, 0x7351, 0xd9c2,
+ 0x734a, 0xd9b8, 0x7342, 0xd9ae, 0x733b, 0xd9a4, 0x7333, 0xd99a,
+ 0x732c, 0xd98f, 0x7324, 0xd985, 0x731d, 0xd97b, 0x7315, 0xd971,
+ 0x730d, 0xd967, 0x7306, 0xd95d, 0x72fe, 0xd953, 0x72f7, 0xd949,
+ 0x72ef, 0xd93f, 0x72e7, 0xd935, 0x72e0, 0xd92b, 0x72d8, 0xd921,
+ 0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
+ 0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
+ 0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
+ 0x7274, 0xd8a0, 0x726d, 0xd896, 0x7265, 0xd88c, 0x725d, 0xd882,
+ 0x7255, 0xd878, 0x724e, 0xd86f, 0x7246, 0xd865, 0x723e, 0xd85b,
+ 0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
+ 0x7217, 0xd82a, 0x720f, 0xd820, 0x7207, 0xd816, 0x71ff, 0xd80c,
+ 0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
+ 0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
+ 0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
+ 0x7199, 0xd78d, 0x7191, 0xd783, 0x7189, 0xd77a, 0x7181, 0xd770,
+ 0x7179, 0xd766, 0x7171, 0xd75c, 0x7169, 0xd753, 0x7161, 0xd749,
+ 0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
+ 0x7139, 0xd719, 0x7131, 0xd70f, 0x7129, 0xd705, 0x7121, 0xd6fc,
+ 0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
+ 0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
+ 0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
+ 0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
+ 0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
+ 0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
+ 0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
+ 0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
+ 0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
+ 0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
+ 0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
+ 0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
+ 0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
+ 0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
+ 0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
+ 0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
+ 0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
+ 0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
+ 0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
+ 0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
+ 0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
+ 0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
+ 0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
+ 0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
+ 0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
+ 0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
+ 0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
+ 0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
+ 0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
+ 0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
+ 0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
+ 0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
+ 0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
+ 0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
+ 0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
+ 0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
+ 0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
+ 0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
+ 0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
+ 0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
+ 0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
+ 0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
+ 0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
+ 0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
+ 0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
+ 0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
+ 0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
+ 0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
+ 0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
+ 0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
+ 0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
+ 0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
+ 0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
+ 0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
+ 0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
+ 0x6981, 0xcf48, 0x6978, 0xcf40, 0x696e, 0xcf38, 0x6965, 0xcf30,
+ 0x695b, 0xcf28, 0x6951, 0xcf20, 0x6948, 0xcf18, 0x693e, 0xcf10,
+ 0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
+ 0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
+ 0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
+ 0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
+ 0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
+ 0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
+ 0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
+ 0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
+ 0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
+ 0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
+ 0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
+ 0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
+ 0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
+ 0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
+ 0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
+ 0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
+ 0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
+ 0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
+ 0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
+ 0x6648, 0xccb6, 0x663e, 0xccaf, 0x6634, 0xcca7, 0x662a, 0xcca0,
+ 0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
+ 0x65f8, 0xcc7a, 0x65ed, 0xcc73, 0x65e3, 0xcc6b, 0x65d9, 0xcc64,
+ 0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
+ 0x65a6, 0xcc3f, 0x659c, 0xcc38, 0x6592, 0xcc30, 0x6588, 0xcc29,
+ 0x657e, 0xcc21, 0x6574, 0xcc1a, 0x6569, 0xcc13, 0x655f, 0xcc0b,
+ 0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
+ 0x652c, 0xcbe7, 0x6522, 0xcbe0, 0x6518, 0xcbd8, 0x650d, 0xcbd1,
+ 0x6503, 0xcbca, 0x64f9, 0xcbc2, 0x64ef, 0xcbbb, 0x64e4, 0xcbb4,
+ 0x64da, 0xcbad, 0x64d0, 0xcba5, 0x64c5, 0xcb9e, 0x64bb, 0xcb97,
+ 0x64b1, 0xcb90, 0x64a7, 0xcb89, 0x649c, 0xcb81, 0x6492, 0xcb7a,
+ 0x6488, 0xcb73, 0x647d, 0xcb6c, 0x6473, 0xcb65, 0x6469, 0xcb5e,
+ 0x645e, 0xcb56, 0x6454, 0xcb4f, 0x644a, 0xcb48, 0x643f, 0xcb41,
+ 0x6435, 0xcb3a, 0x642b, 0xcb33, 0x6420, 0xcb2c, 0x6416, 0xcb25,
+ 0x640b, 0xcb1e, 0x6401, 0xcb16, 0x63f7, 0xcb0f, 0x63ec, 0xcb08,
+ 0x63e2, 0xcb01, 0x63d7, 0xcafa, 0x63cd, 0xcaf3, 0x63c3, 0xcaec,
+ 0x63b8, 0xcae5, 0x63ae, 0xcade, 0x63a3, 0xcad7, 0x6399, 0xcad0,
+ 0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
+ 0x6365, 0xcaad, 0x635a, 0xcaa6, 0x6350, 0xca9f, 0x6345, 0xca99,
+ 0x633b, 0xca92, 0x6330, 0xca8b, 0x6326, 0xca84, 0x631b, 0xca7d,
+ 0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
+ 0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
+ 0x62bc, 0xca3f, 0x62b2, 0xca38, 0x62a7, 0xca32, 0x629d, 0xca2b,
+ 0x6292, 0xca24, 0x6288, 0xca1d, 0x627d, 0xca16, 0x6272, 0xca10,
+ 0x6268, 0xca09, 0x625d, 0xca02, 0x6253, 0xc9fb, 0x6248, 0xc9f5,
+ 0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
+ 0x6213, 0xc9d3, 0x6208, 0xc9cc, 0x61fe, 0xc9c6, 0x61f3, 0xc9bf,
+ 0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
+ 0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
+ 0x6193, 0xc983, 0x6188, 0xc97d, 0x617d, 0xc976, 0x6173, 0xc970,
+ 0x6168, 0xc969, 0x615d, 0xc963, 0x6153, 0xc95c, 0x6148, 0xc955,
+ 0x613d, 0xc94f, 0x6132, 0xc948, 0x6128, 0xc942, 0x611d, 0xc93b,
+ 0x6112, 0xc935, 0x6107, 0xc92e, 0x60fd, 0xc928, 0x60f2, 0xc921,
+ 0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
+ 0x60bc, 0xc901, 0x60b1, 0xc8fb, 0x60a6, 0xc8f4, 0x609b, 0xc8ee,
+ 0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
+ 0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
+ 0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
+ 0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
+ 0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
+ 0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
+ 0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
+ 0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
+ 0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
+ 0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
+ 0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
+ 0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
+ 0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
+ 0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
+ 0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
+ 0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
+ 0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
+ 0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
+ 0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
+ 0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
+ 0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
+ 0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
+ 0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
+ 0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
+ 0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
+ 0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
+ 0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
+ 0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
+ 0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
+ 0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
+ 0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
+ 0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
+ 0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
+ 0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
+ 0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
+ 0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
+ 0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
+ 0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
+ 0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
+ 0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
+ 0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
+ 0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
+ 0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
+ 0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
+ 0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
+ 0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
+ 0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
+ 0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
+ 0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
+ 0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
+ 0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
+ 0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
+ 0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
+ 0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
+ 0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
+ 0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
+ 0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
+ 0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
+ 0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
+ 0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
+ 0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
+ 0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
+ 0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
+ 0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
+ 0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
+ 0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
+ 0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
+ 0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
+ 0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
+ 0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
+ 0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
+ 0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
+ 0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
+ 0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
+ 0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
+ 0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
+ 0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
+ 0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
+ 0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
+ 0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
+ 0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
+ 0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
+ 0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
+ 0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
+ 0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
+ 0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
+ 0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
+ 0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
+ 0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
+ 0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
+ 0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
+ 0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
+ 0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
+ 0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
+ 0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
+ 0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
+ 0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
+ 0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
+ 0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
+ 0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
+ 0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
+ 0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
+ 0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
+ 0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
+ 0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
+ 0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
+ 0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
+ 0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
+ 0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
+ 0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
+ 0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
+ 0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
+ 0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
+ 0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
+ 0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
+ 0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
+ 0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
+ 0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
+ 0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
+ 0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
+ 0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
+ 0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
+ 0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
+ 0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
+ 0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
+ 0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
+ 0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
+ 0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
+ 0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
+ 0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
+ 0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
+ 0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
+ 0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
+ 0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
+ 0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
+ 0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
+ 0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
+ 0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
+ 0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
+ 0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
+ 0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
+ 0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
+ 0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
+ 0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
+ 0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
+ 0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
+ 0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
+ 0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
+ 0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
+ 0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
+ 0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
+ 0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
+ 0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
+ 0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
+ 0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
+ 0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
+ 0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
+ 0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
+ 0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
+ 0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
+ 0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
+ 0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
+ 0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
+ 0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
+ 0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
+ 0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
+ 0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
+ 0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
+ 0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
+ 0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
+ 0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
+ 0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
+ 0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
+ 0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
+};
+
+/**
+* @brief Initialization function for the Q15 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 000000000..da815cff0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4279 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q31.c
+*
+* Description: RFFT & RIFFT Q31 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* \par
+* Generation floating point realCoefAQ31 array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }</pre>
+* \par
+* Convert to fixed point Q31 format
+* round(pATable[i] * pow(2, 31))
+*/
+
+
+static const q31_t realCoefAQ31[8192] = {
+ 0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
+ 0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
+ 0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
+ 0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
+ 0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
+ 0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
+ 0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
+ 0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
+ 0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
+ 0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
+ 0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
+ 0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
+ 0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
+ 0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
+ 0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
+ 0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
+ 0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
+ 0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
+ 0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
+ 0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
+ 0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
+ 0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
+ 0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
+ 0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
+ 0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
+ 0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
+ 0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
+ 0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
+ 0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
+ 0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
+ 0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
+ 0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
+ 0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
+ 0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
+ 0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
+ 0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
+ 0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
+ 0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
+ 0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
+ 0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
+ 0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
+ 0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
+ 0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
+ 0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
+ 0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
+ 0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
+ 0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
+ 0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
+ 0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
+ 0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
+ 0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
+ 0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
+ 0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
+ 0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
+ 0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
+ 0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
+ 0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
+ 0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
+ 0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
+ 0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
+ 0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
+ 0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
+ 0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
+ 0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
+ 0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
+ 0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
+ 0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
+ 0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
+ 0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
+ 0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
+ 0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
+ 0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
+ 0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
+ 0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
+ 0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
+ 0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
+ 0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
+ 0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
+ 0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
+ 0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
+ 0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
+ 0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
+ 0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
+ 0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
+ 0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
+ 0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
+ 0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
+ 0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
+ 0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
+ 0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
+ 0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
+ 0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
+ 0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
+ 0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
+ 0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
+ 0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
+ 0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
+ 0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
+ 0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
+ 0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
+ 0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
+ 0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
+ 0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
+ 0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
+ 0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
+ 0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
+ 0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
+ 0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
+ 0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
+ 0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
+ 0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
+ 0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
+ 0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
+ 0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
+ 0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
+ 0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
+ 0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
+ 0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
+ 0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
+ 0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
+ 0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
+ 0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
+ 0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
+ 0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
+ 0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
+ 0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
+ 0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
+ 0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
+ 0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
+ 0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
+ 0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
+ 0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
+ 0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
+ 0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
+ 0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
+ 0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
+ 0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
+ 0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
+ 0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
+ 0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
+ 0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
+ 0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
+ 0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
+ 0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
+ 0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
+ 0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
+ 0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
+ 0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
+ 0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
+ 0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
+ 0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
+ 0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
+ 0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
+ 0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
+ 0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
+ 0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
+ 0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
+ 0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
+ 0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
+ 0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
+ 0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
+ 0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
+ 0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
+ 0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
+ 0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
+ 0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
+ 0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
+ 0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
+ 0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
+ 0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
+ 0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
+ 0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
+ 0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
+ 0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
+ 0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
+ 0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
+ 0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
+ 0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
+ 0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
+ 0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
+ 0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
+ 0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
+ 0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
+ 0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
+ 0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
+ 0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
+ 0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
+ 0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
+ 0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
+ 0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
+ 0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
+ 0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
+ 0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
+ 0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
+ 0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
+ 0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
+ 0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
+ 0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
+ 0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
+ 0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
+ 0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
+ 0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
+ 0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
+ 0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
+ 0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
+ 0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
+ 0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
+ 0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
+ 0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
+ 0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
+ 0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
+ 0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
+ 0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
+ 0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
+ 0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
+ 0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
+ 0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
+ 0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
+ 0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
+ 0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
+ 0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
+ 0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
+ 0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
+ 0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
+ 0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
+ 0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
+ 0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
+ 0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
+ 0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
+ 0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
+ 0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
+ 0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
+ 0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
+ 0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
+ 0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
+ 0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
+ 0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
+ 0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
+ 0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
+ 0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
+ 0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
+ 0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
+ 0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
+ 0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
+ 0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
+ 0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
+ 0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
+ 0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
+ 0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
+ 0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
+ 0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
+ 0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
+ 0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
+ 0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
+ 0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
+ 0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
+ 0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
+ 0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
+ 0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
+ 0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
+ 0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
+ 0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
+ 0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
+ 0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
+ 0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
+ 0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
+ 0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
+ 0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
+ 0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
+ 0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
+ 0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
+ 0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
+ 0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
+ 0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
+ 0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
+ 0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
+ 0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
+ 0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
+ 0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
+ 0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
+ 0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
+ 0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
+ 0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
+ 0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
+ 0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
+ 0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
+ 0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
+ 0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
+ 0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
+ 0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
+ 0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
+ 0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
+ 0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
+ 0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
+ 0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
+ 0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
+ 0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
+ 0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
+ 0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
+ 0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
+ 0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
+ 0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
+ 0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
+ 0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
+ 0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
+ 0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
+ 0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
+ 0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
+ 0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
+ 0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
+ 0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
+ 0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
+ 0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
+ 0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
+ 0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
+ 0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
+ 0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
+ 0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
+ 0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
+ 0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
+ 0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
+ 0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
+ 0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
+ 0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
+ 0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
+ 0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
+ 0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
+ 0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
+ 0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
+ 0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
+ 0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
+ 0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
+ 0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
+ 0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
+ 0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
+ 0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
+ 0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
+ 0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
+ 0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
+ 0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
+ 0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
+ 0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
+ 0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
+ 0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
+ 0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
+ 0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
+ 0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
+ 0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
+ 0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
+ 0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
+ 0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
+ 0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
+ 0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
+ 0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
+ 0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
+ 0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
+ 0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
+ 0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
+ 0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
+ 0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
+ 0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
+ 0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
+ 0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
+ 0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
+ 0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
+ 0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
+ 0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
+ 0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
+ 0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
+ 0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
+ 0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
+ 0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
+ 0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
+ 0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
+ 0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
+ 0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
+ 0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
+ 0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
+ 0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
+ 0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
+ 0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
+ 0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
+ 0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
+ 0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
+ 0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
+ 0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
+ 0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
+ 0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
+ 0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
+ 0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
+ 0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
+ 0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
+ 0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
+ 0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
+ 0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
+ 0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
+ 0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
+ 0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
+ 0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
+ 0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
+ 0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
+ 0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
+ 0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
+ 0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
+ 0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
+ 0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
+ 0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
+ 0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
+ 0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
+ 0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
+ 0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
+ 0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
+ 0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
+ 0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
+ 0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
+ 0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
+ 0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
+ 0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
+ 0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
+ 0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
+ 0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
+ 0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
+ 0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
+ 0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
+ 0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
+ 0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
+ 0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
+ 0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
+ 0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
+ 0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
+ 0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
+ 0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
+ 0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
+ 0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
+ 0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
+ 0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
+ 0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
+ 0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
+ 0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
+ 0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
+ 0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
+ 0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
+ 0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
+ 0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
+ 0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
+ 0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
+ 0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
+ 0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
+ 0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
+ 0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
+ 0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
+ 0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
+ 0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
+ 0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
+ 0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
+ 0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
+ 0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
+ 0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
+ 0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
+ 0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
+ 0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
+ 0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
+ 0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
+ 0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
+ 0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
+ 0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
+ 0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
+ 0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
+ 0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
+ 0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
+ 0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
+ 0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
+ 0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
+ 0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
+ 0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
+ 0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
+ 0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
+ 0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
+ 0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
+ 0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
+ 0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
+ 0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
+ 0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
+ 0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
+ 0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
+ 0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
+ 0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
+ 0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
+ 0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
+ 0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
+ 0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
+ 0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
+ 0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
+ 0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
+ 0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
+ 0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
+ 0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
+ 0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
+ 0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
+ 0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
+ 0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
+ 0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
+ 0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
+ 0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
+ 0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
+ 0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
+ 0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
+ 0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
+ 0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
+ 0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
+ 0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
+ 0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
+ 0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
+ 0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
+ 0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
+ 0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
+ 0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
+ 0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
+ 0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
+ 0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
+ 0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
+ 0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
+ 0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
+ 0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
+ 0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
+ 0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
+ 0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
+ 0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
+ 0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
+ 0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
+ 0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
+ 0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
+ 0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
+ 0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
+ 0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
+ 0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
+ 0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
+ 0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
+ 0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
+ 0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
+ 0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
+ 0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
+ 0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
+ 0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
+ 0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
+ 0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
+ 0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
+ 0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
+ 0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
+ 0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
+ 0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
+ 0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
+ 0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
+ 0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
+ 0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
+ 0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
+ 0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
+ 0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
+ 0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
+ 0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
+ 0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
+ 0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
+ 0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
+ 0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
+ 0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
+ 0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
+ 0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
+ 0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
+ 0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
+ 0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
+ 0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
+ 0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
+ 0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
+ 0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
+ 0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
+ 0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
+ 0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
+ 0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
+ 0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
+ 0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
+ 0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
+ 0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
+ 0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
+ 0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
+ 0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
+ 0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
+ 0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
+ 0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
+ 0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
+ 0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
+ 0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
+ 0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
+ 0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
+ 0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
+ 0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
+ 0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
+ 0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
+ 0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
+ 0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
+ 0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
+ 0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
+ 0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
+ 0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
+ 0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
+ 0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
+ 0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
+ 0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
+ 0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
+ 0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
+ 0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
+ 0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
+ 0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
+ 0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
+ 0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
+ 0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
+ 0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
+ 0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
+ 0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
+ 0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
+ 0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
+ 0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
+ 0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
+ 0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
+ 0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
+ 0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
+ 0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
+ 0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
+ 0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
+ 0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
+ 0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
+ 0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
+ 0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
+ 0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
+ 0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
+ 0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
+ 0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
+ 0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
+ 0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
+ 0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
+ 0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
+ 0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
+ 0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
+ 0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
+ 0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
+ 0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
+ 0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
+ 0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
+ 0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
+ 0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
+ 0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
+ 0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
+ 0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
+ 0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
+ 0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
+ 0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
+ 0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
+ 0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
+ 0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
+ 0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
+ 0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
+ 0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
+ 0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
+ 0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
+ 0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
+ 0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
+ 0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
+ 0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
+ 0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
+ 0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
+ 0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
+ 0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
+ 0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
+ 0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
+ 0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
+ 0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
+ 0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
+ 0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
+ 0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
+ 0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
+ 0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
+ 0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
+ 0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
+ 0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
+ 0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
+ 0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
+ 0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
+ 0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
+ 0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
+ 0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
+ 0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
+ 0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
+ 0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
+ 0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
+ 0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
+ 0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
+ 0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
+ 0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
+ 0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
+ 0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
+ 0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
+ 0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
+ 0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
+ 0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
+ 0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
+ 0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
+ 0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
+ 0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
+ 0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
+ 0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
+ 0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
+ 0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
+ 0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
+ 0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
+ 0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
+ 0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
+ 0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
+ 0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
+ 0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
+ 0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
+ 0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
+ 0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
+ 0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
+ 0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
+ 0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
+ 0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
+ 0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
+ 0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
+ 0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
+ 0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
+ 0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
+ 0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
+ 0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
+ 0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
+ 0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
+ 0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
+ 0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
+ 0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
+ 0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
+ 0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
+ 0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
+ 0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
+ 0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
+ 0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
+ 0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
+ 0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
+ 0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
+ 0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
+ 0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
+ 0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
+ 0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
+ 0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
+ 0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
+ 0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
+ 0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
+ 0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
+ 0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
+ 0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
+ 0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
+ 0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
+ 0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
+ 0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
+ 0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
+ 0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
+ 0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
+ 0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
+ 0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
+ 0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
+ 0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
+ 0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
+ 0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
+ 0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
+ 0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
+ 0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
+ 0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
+ 0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
+ 0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
+ 0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
+ 0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
+ 0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
+ 0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
+ 0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
+ 0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
+ 0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
+ 0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
+ 0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
+ 0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
+ 0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
+ 0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
+ 0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
+ 0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
+ 0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
+ 0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
+ 0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
+ 0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
+ 0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
+ 0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
+ 0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
+ 0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
+ 0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
+ 0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
+ 0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
+ 0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
+ 0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
+ 0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
+ 0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
+ 0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
+ 0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
+ 0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
+ 0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
+ 0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
+ 0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
+ 0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
+ 0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
+ 0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
+ 0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
+ 0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
+ 0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
+ 0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
+ 0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
+ 0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
+ 0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
+ 0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
+ 0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
+ 0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
+ 0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
+ 0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
+ 0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
+ 0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
+ 0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
+ 0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
+ 0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
+ 0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
+ 0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
+ 0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
+ 0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
+ 0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
+ 0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
+ 0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
+ 0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
+ 0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
+ 0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
+ 0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
+ 0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
+ 0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
+ 0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
+ 0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
+ 0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
+ 0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
+ 0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
+ 0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
+ 0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
+ 0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
+ 0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
+ 0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
+ 0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
+ 0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
+ 0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
+ 0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
+ 0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
+ 0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
+ 0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
+ 0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
+ 0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
+ 0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
+ 0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
+ 0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
+ 0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
+ 0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
+ 0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
+ 0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
+ 0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
+ 0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
+ 0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
+ 0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
+ 0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
+ 0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
+ 0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
+ 0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
+ 0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
+ 0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
+ 0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
+ 0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
+ 0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
+ 0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
+ 0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
+ 0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
+ 0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
+ 0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
+ 0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
+ 0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
+ 0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
+ 0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
+ 0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
+ 0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
+ 0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
+ 0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
+ 0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
+ 0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
+ 0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
+ 0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
+ 0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
+ 0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
+ 0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
+ 0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
+ 0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
+ 0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
+ 0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
+ 0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
+ 0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
+ 0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
+ 0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
+ 0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
+ 0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
+ 0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
+ 0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
+ 0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
+ 0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
+ 0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
+ 0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
+ 0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
+ 0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
+ 0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
+ 0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
+ 0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
+ 0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
+ 0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
+ 0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
+ 0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
+ 0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
+ 0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
+ 0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
+ 0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
+ 0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
+ 0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
+ 0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
+ 0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
+ 0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
+ 0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
+ 0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
+ 0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
+ 0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
+ 0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
+ 0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
+ 0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
+ 0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
+ 0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
+ 0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
+ 0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
+ 0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
+ 0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
+ 0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
+ 0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
+ 0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
+ 0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
+ 0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
+ 0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
+ 0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
+ 0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
+ 0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
+ 0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
+ 0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
+ 0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
+ 0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
+ 0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
+ 0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
+ 0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
+ 0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
+ 0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
+ 0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
+ 0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
+ 0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
+ 0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
+ 0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
+ 0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
+ 0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
+ 0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
+ 0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
+ 0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
+ 0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
+ 0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
+ 0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
+ 0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
+ 0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
+ 0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
+ 0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
+ 0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
+ 0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
+ 0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
+ 0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
+ 0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
+ 0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
+ 0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
+ 0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
+ 0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
+ 0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
+ 0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
+ 0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
+ 0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
+ 0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
+ 0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
+ 0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
+ 0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
+ 0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
+ 0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
+ 0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
+ 0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
+ 0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
+ 0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
+ 0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
+ 0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
+ 0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
+ 0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
+ 0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
+ 0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
+ 0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
+ 0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
+ 0x13bd3, 0xff36f170, 0x11594, 0xff438234,
+ 0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
+ 0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
+ 0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
+ 0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
+ 0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
+ 0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
+ 0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
+ 0x0, 0x0, 0x13c, 0xc90fe,
+ 0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
+ 0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
+ 0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
+ 0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
+ 0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
+ 0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
+ 0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
+ 0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
+ 0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
+ 0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
+ 0x25519, 0x1147271, 0x28c9c, 0x12102f4,
+ 0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
+ 0x341f4, 0x146b438, 0x38356, 0x153448c,
+ 0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
+ 0x45648, 0x178f536, 0x4a188, 0x1858552,
+ 0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
+ 0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
+ 0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
+ 0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
+ 0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
+ 0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
+ 0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
+ 0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
+ 0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
+ 0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
+ 0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
+ 0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
+ 0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
+ 0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
+ 0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
+ 0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
+ 0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
+ 0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
+ 0x164757, 0x3562038, 0x16f047, 0x362acc5,
+ 0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
+ 0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
+ 0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
+ 0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
+ 0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
+ 0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
+ 0x2064ab, 0x405c361, 0x213018, 0x4124dee,
+ 0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
+ 0x23a124, 0x437eca4, 0x24766a, 0x444768d,
+ 0x254e27, 0x451004d, 0x262859, 0x45d89e2,
+ 0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
+ 0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
+ 0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
+ 0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
+ 0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
+ 0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
+ 0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
+ 0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
+ 0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
+ 0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
+ 0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
+ 0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
+ 0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
+ 0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
+ 0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
+ 0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
+ 0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
+ 0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
+ 0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
+ 0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
+ 0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
+ 0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
+ 0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
+ 0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
+ 0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
+ 0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
+ 0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
+ 0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
+ 0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
+ 0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
+ 0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
+ 0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
+ 0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
+ 0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
+ 0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
+ 0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
+ 0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
+ 0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
+ 0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
+ 0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
+ 0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
+ 0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
+ 0x91b01d, 0x884104b, 0x935d64, 0x8908483,
+ 0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
+ 0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
+ 0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
+ 0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
+ 0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
+ 0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
+ 0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
+ 0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
+ 0xb15502, 0x9640837, 0xb32e42, 0x9707635,
+ 0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
+ 0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
+ 0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
+ 0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
+ 0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
+ 0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
+ 0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
+ 0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
+ 0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
+ 0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
+ 0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
+ 0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
+ 0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
+ 0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
+ 0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
+ 0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
+ 0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
+ 0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
+ 0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
+ 0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
+ 0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
+ 0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
+ 0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
+ 0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
+ 0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
+ 0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
+ 0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
+ 0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
+ 0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
+ 0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
+ 0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
+ 0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
+ 0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
+ 0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
+ 0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
+ 0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
+ 0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
+ 0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
+ 0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
+ 0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
+ 0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
+ 0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
+ 0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
+ 0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
+ 0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
+ 0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
+ 0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
+ 0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
+ 0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
+ 0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
+ 0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
+ 0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
+ 0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
+ 0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
+ 0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
+ 0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
+ 0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
+ 0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
+ 0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
+ 0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
+ 0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
+ 0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
+ 0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
+ 0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
+ 0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
+ 0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
+ 0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
+ 0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
+ 0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
+ 0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
+ 0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
+ 0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
+ 0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
+ 0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
+ 0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
+ 0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
+ 0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
+ 0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
+ 0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
+ 0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
+ 0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
+ 0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
+ 0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
+ 0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
+ 0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
+ 0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
+ 0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
+ 0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
+ 0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
+ 0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
+ 0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
+ 0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
+ 0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
+ 0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
+ 0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
+ 0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
+ 0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
+ 0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
+ 0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
+ 0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
+ 0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
+ 0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
+ 0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
+ 0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
+ 0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
+ 0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
+ 0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
+ 0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
+ 0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
+ 0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
+ 0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
+ 0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
+ 0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
+ 0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
+ 0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
+ 0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
+ 0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
+ 0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
+ 0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
+ 0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
+ 0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
+ 0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
+ 0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
+ 0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
+ 0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
+ 0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
+ 0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
+ 0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
+ 0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
+ 0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
+ 0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
+ 0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
+ 0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
+ 0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
+ 0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
+ 0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
+ 0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
+ 0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
+ 0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
+ 0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
+ 0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
+ 0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
+ 0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
+ 0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
+ 0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
+ 0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
+ 0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
+ 0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
+ 0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
+ 0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
+ 0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
+ 0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
+ 0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
+ 0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
+ 0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
+ 0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
+ 0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
+ 0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
+ 0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
+ 0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
+ 0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
+ 0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
+ 0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
+ 0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
+ 0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
+ 0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
+ 0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
+ 0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
+ 0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
+ 0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
+ 0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
+ 0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
+ 0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
+ 0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
+ 0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
+ 0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
+ 0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
+ 0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
+ 0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
+ 0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
+ 0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
+ 0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
+ 0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
+ 0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
+ 0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
+ 0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
+ 0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
+ 0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
+ 0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
+ 0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
+ 0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
+ 0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
+ 0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
+ 0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
+ 0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
+ 0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
+ 0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
+ 0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
+ 0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
+ 0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
+ 0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
+ 0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
+ 0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
+ 0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
+ 0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
+ 0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
+ 0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
+ 0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
+ 0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
+ 0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
+ 0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
+ 0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
+ 0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
+ 0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
+ 0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
+ 0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
+ 0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
+ 0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
+ 0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
+ 0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
+ 0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
+ 0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
+ 0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
+ 0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
+ 0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
+ 0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
+ 0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
+ 0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
+ 0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
+ 0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
+ 0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
+ 0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
+ 0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
+ 0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
+ 0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
+ 0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
+ 0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
+ 0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
+ 0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
+ 0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
+ 0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
+ 0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
+ 0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
+ 0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
+ 0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
+ 0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
+ 0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
+ 0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
+ 0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
+ 0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
+ 0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
+ 0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
+ 0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
+ 0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
+ 0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
+ 0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
+ 0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
+ 0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
+ 0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
+ 0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
+ 0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
+ 0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
+ 0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
+ 0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
+ 0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
+ 0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
+ 0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
+ 0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
+ 0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
+ 0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
+ 0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
+ 0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
+ 0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
+ 0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
+ 0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
+ 0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
+ 0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
+ 0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
+ 0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
+ 0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
+ 0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
+ 0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
+ 0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
+ 0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
+ 0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
+ 0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
+ 0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
+ 0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
+ 0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
+ 0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
+ 0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
+ 0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
+ 0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
+ 0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
+ 0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
+ 0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
+ 0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
+ 0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
+ 0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
+ 0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
+ 0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
+ 0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
+ 0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
+ 0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
+ 0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
+ 0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
+ 0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
+ 0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
+ 0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
+ 0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
+ 0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
+ 0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
+ 0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
+ 0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
+ 0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
+ 0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
+ 0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
+ 0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
+ 0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
+ 0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
+ 0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
+ 0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
+ 0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
+ 0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
+ 0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
+ 0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
+ 0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
+ 0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
+ 0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
+ 0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
+ 0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
+ 0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
+ 0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
+ 0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
+ 0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
+ 0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
+ 0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
+ 0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
+ 0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
+ 0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
+ 0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
+ 0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
+ 0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
+ 0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
+ 0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
+ 0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
+ 0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
+ 0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
+ 0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
+ 0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
+ 0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
+ 0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
+ 0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
+ 0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
+ 0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
+ 0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
+ 0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
+ 0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
+ 0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
+ 0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
+ 0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
+ 0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
+ 0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
+ 0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
+ 0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
+ 0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
+ 0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
+ 0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
+ 0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
+ 0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
+ 0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
+ 0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
+ 0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
+ 0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
+ 0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
+ 0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
+ 0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
+ 0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
+ 0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
+ 0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
+ 0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
+ 0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
+ 0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
+ 0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
+ 0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
+ 0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
+ 0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
+ 0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
+ 0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
+ 0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
+ 0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
+ 0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
+ 0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
+ 0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
+ 0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
+ 0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
+ 0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
+ 0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
+ 0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
+ 0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
+ 0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
+ 0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
+ 0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
+ 0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
+ 0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
+ 0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
+ 0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
+ 0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
+ 0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
+ 0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
+ 0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
+ 0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
+ 0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
+ 0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
+ 0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
+ 0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
+ 0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
+ 0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
+ 0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
+ 0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
+ 0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
+ 0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
+ 0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
+ 0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
+ 0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
+ 0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
+ 0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
+ 0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
+ 0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
+ 0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
+ 0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
+ 0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
+ 0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
+ 0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
+ 0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
+ 0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
+ 0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
+ 0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
+ 0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
+ 0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
+ 0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
+ 0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
+ 0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
+ 0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
+ 0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
+ 0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
+ 0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
+ 0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
+ 0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
+ 0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
+ 0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
+ 0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
+ 0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
+ 0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
+ 0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
+ 0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
+ 0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
+ 0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
+ 0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
+ 0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
+ 0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
+ 0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
+ 0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
+ 0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
+ 0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
+ 0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
+ 0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
+ 0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
+ 0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
+ 0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
+ 0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
+ 0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
+ 0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
+ 0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
+ 0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
+ 0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
+ 0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
+ 0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
+ 0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
+ 0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
+ 0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
+ 0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
+ 0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
+ 0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
+ 0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
+ 0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
+ 0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
+ 0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
+ 0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
+ 0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
+ 0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
+ 0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
+ 0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
+ 0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
+ 0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
+ 0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
+ 0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
+ 0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
+ 0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
+ 0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
+ 0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
+ 0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
+ 0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
+ 0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
+ 0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
+ 0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
+ 0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
+ 0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
+ 0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
+ 0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
+ 0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
+ 0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
+ 0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
+ 0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
+ 0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
+ 0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
+ 0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
+ 0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
+ 0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
+ 0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
+ 0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
+ 0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
+ 0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
+ 0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
+ 0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
+ 0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
+ 0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
+ 0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
+ 0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
+ 0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
+ 0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
+ 0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
+ 0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
+ 0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
+ 0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
+ 0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
+ 0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
+ 0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
+ 0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
+ 0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
+ 0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
+ 0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
+ 0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
+ 0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
+ 0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
+ 0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
+ 0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
+ 0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
+ 0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
+ 0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
+ 0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
+ 0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
+ 0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
+ 0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
+ 0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
+ 0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
+ 0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
+ 0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
+ 0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
+ 0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
+ 0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
+ 0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
+ 0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
+ 0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
+ 0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
+ 0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
+ 0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
+ 0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
+ 0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
+ 0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
+ 0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
+ 0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
+ 0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
+ 0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
+ 0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
+ 0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
+ 0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
+ 0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
+ 0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
+ 0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
+ 0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
+ 0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
+ 0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
+ 0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
+ 0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
+ 0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
+ 0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
+ 0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
+ 0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
+ 0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
+ 0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
+ 0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
+ 0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
+ 0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
+ 0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
+ 0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
+ 0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
+ 0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
+ 0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
+ 0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
+ 0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
+ 0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
+ 0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
+ 0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
+ 0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
+ 0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
+ 0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
+ 0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
+ 0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
+ 0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
+ 0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
+ 0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
+ 0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
+ 0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
+ 0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
+ 0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
+ 0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
+ 0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
+ 0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
+ 0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
+ 0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
+ 0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
+ 0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
+ 0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
+ 0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
+ 0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
+ 0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
+ 0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
+ 0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
+ 0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
+ 0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
+ 0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
+ 0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
+ 0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
+ 0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
+ 0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
+ 0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
+ 0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
+ 0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
+ 0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
+ 0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
+ 0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
+ 0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
+ 0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
+ 0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
+ 0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
+ 0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
+ 0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
+ 0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
+ 0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
+ 0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
+ 0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
+ 0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
+ 0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
+ 0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
+ 0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
+ 0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
+ 0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
+ 0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
+ 0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
+ 0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
+ 0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
+ 0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
+ 0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
+ 0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
+ 0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
+ 0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
+ 0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
+ 0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
+ 0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
+ 0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
+ 0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
+ 0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
+ 0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
+ 0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
+ 0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
+ 0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
+ 0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
+ 0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
+ 0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
+ 0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
+ 0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
+ 0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
+ 0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
+ 0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
+ 0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
+ 0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
+ 0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
+ 0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
+ 0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
+ 0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
+ 0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
+ 0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
+ 0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
+ 0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
+ 0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
+ 0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
+ 0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
+ 0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
+ 0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
+ 0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
+ 0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
+ 0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
+ 0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
+ 0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
+ 0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
+ 0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
+ 0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
+ 0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
+ 0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
+ 0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
+ 0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
+ 0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
+ 0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
+ 0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
+ 0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
+ 0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
+ 0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
+ 0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
+ 0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
+ 0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
+ 0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
+ 0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
+ 0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
+ 0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
+ 0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
+ 0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
+ 0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
+ 0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
+ 0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
+ 0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
+ 0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
+ 0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
+ 0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
+ 0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
+ 0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
+ 0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
+ 0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
+ 0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
+ 0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
+ 0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
+ 0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
+ 0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
+ 0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
+ 0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
+ 0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
+ 0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
+ 0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
+ 0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
+ 0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
+ 0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
+ 0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
+ 0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
+ 0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
+ 0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
+ 0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
+ 0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
+ 0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
+ 0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
+ 0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
+ 0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
+ 0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
+ 0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
+ 0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
+ 0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
+ 0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
+ 0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
+ 0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
+ 0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
+ 0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
+ 0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
+ 0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
+ 0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
+ 0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
+ 0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
+ 0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
+ 0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
+ 0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
+ 0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
+ 0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
+ 0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
+ 0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
+ 0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
+ 0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
+ 0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
+ 0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
+ 0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
+ 0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
+ 0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
+ 0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
+ 0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
+ 0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
+ 0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
+ 0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
+ 0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
+ 0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
+ 0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
+ 0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
+ 0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
+ 0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
+ 0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
+ 0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
+ 0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
+ 0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
+ 0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
+ 0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
+ 0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
+ 0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
+ 0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
+ 0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
+ 0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
+ 0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
+ 0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
+ 0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
+ 0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
+ 0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
+ 0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
+ 0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
+ 0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
+ 0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
+ 0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
+ 0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
+ 0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
+ 0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
+ 0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
+ 0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
+ 0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
+ 0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
+ 0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
+ 0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
+ 0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
+ 0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
+ 0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
+ 0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
+ 0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
+ 0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
+ 0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
+ 0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
+ 0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
+ 0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
+ 0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
+ 0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
+ 0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
+ 0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
+ 0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
+ 0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
+ 0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
+ 0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
+ 0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
+ 0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
+ 0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
+ 0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
+ 0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
+ 0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
+ 0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
+ 0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
+ 0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
+ 0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
+ 0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
+ 0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
+ 0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
+ 0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
+ 0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
+ 0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
+ 0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
+ 0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
+ 0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
+ 0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
+ 0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
+ 0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
+ 0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
+ 0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
+ 0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
+ 0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
+ 0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
+ 0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
+ 0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
+ 0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
+ 0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
+ 0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
+ 0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
+ 0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
+ 0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
+ 0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
+ 0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
+ 0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
+ 0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
+ 0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
+ 0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
+ 0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
+ 0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
+ 0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
+ 0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
+ 0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
+ 0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
+ 0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
+ 0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
+ 0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
+ 0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
+ 0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
+ 0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
+ 0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
+ 0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
+ 0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
+ 0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
+ 0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
+ 0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
+ 0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
+ 0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
+ 0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
+ 0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
+ 0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
+ 0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
+ 0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
+ 0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
+ 0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
+ 0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
+ 0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
+ 0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
+ 0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
+ 0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
+ 0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
+ 0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
+ 0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
+ 0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
+ 0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
+ 0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
+};
+
+
+/**
+* \par
+* Generation of realCoefBQ31 array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q31 format
+* round(pBTable[i] * pow(2, 31))
+*
+*/
+
+static const q31_t realCoefBQ31[8192] = {
+ 0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
+ 0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
+ 0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
+ 0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
+ 0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
+ 0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
+ 0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
+ 0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
+ 0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
+ 0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
+ 0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
+ 0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
+ 0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
+ 0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
+ 0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
+ 0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
+ 0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
+ 0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
+ 0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
+ 0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
+ 0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
+ 0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
+ 0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
+ 0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
+ 0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
+ 0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
+ 0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
+ 0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
+ 0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
+ 0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
+ 0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
+ 0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
+ 0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
+ 0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
+ 0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
+ 0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
+ 0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
+ 0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
+ 0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
+ 0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
+ 0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
+ 0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
+ 0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
+ 0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
+ 0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
+ 0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
+ 0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
+ 0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
+ 0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
+ 0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
+ 0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
+ 0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
+ 0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
+ 0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
+ 0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
+ 0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
+ 0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
+ 0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
+ 0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
+ 0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
+ 0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
+ 0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
+ 0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
+ 0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
+ 0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
+ 0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
+ 0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
+ 0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
+ 0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
+ 0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
+ 0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
+ 0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
+ 0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
+ 0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
+ 0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
+ 0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
+ 0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
+ 0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
+ 0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
+ 0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
+ 0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
+ 0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
+ 0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
+ 0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
+ 0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
+ 0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
+ 0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
+ 0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
+ 0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
+ 0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
+ 0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
+ 0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
+ 0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
+ 0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
+ 0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
+ 0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
+ 0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
+ 0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
+ 0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
+ 0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
+ 0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
+ 0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
+ 0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
+ 0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
+ 0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
+ 0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
+ 0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
+ 0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
+ 0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
+ 0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
+ 0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
+ 0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
+ 0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
+ 0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
+ 0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
+ 0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
+ 0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
+ 0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
+ 0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
+ 0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
+ 0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
+ 0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
+ 0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
+ 0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
+ 0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
+ 0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
+ 0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
+ 0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
+ 0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
+ 0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
+ 0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
+ 0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
+ 0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
+ 0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
+ 0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
+ 0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
+ 0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
+ 0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
+ 0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
+ 0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
+ 0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
+ 0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
+ 0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
+ 0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
+ 0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
+ 0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
+ 0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
+ 0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
+ 0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
+ 0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
+ 0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
+ 0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
+ 0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
+ 0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
+ 0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
+ 0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
+ 0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
+ 0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
+ 0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
+ 0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
+ 0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
+ 0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
+ 0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
+ 0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
+ 0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
+ 0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
+ 0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
+ 0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
+ 0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
+ 0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
+ 0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
+ 0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
+ 0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
+ 0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
+ 0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
+ 0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
+ 0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
+ 0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
+ 0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
+ 0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
+ 0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
+ 0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
+ 0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
+ 0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
+ 0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
+ 0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
+ 0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
+ 0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
+ 0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
+ 0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
+ 0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
+ 0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
+ 0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
+ 0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
+ 0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
+ 0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
+ 0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
+ 0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
+ 0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
+ 0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
+ 0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
+ 0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
+ 0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
+ 0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
+ 0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
+ 0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
+ 0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
+ 0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
+ 0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
+ 0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
+ 0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
+ 0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
+ 0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
+ 0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
+ 0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
+ 0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
+ 0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
+ 0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
+ 0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
+ 0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
+ 0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
+ 0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
+ 0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
+ 0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
+ 0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
+ 0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
+ 0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
+ 0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
+ 0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
+ 0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
+ 0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
+ 0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
+ 0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
+ 0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
+ 0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
+ 0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
+ 0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
+ 0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
+ 0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
+ 0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
+ 0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
+ 0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
+ 0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
+ 0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
+ 0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
+ 0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
+ 0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
+ 0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
+ 0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
+ 0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
+ 0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
+ 0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
+ 0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
+ 0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
+ 0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
+ 0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
+ 0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
+ 0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
+ 0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
+ 0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
+ 0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
+ 0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
+ 0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
+ 0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
+ 0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
+ 0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
+ 0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
+ 0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
+ 0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
+ 0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
+ 0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
+ 0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
+ 0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
+ 0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
+ 0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
+ 0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
+ 0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
+ 0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
+ 0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
+ 0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
+ 0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
+ 0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
+ 0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
+ 0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
+ 0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
+ 0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
+ 0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
+ 0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
+ 0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
+ 0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
+ 0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
+ 0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
+ 0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
+ 0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
+ 0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
+ 0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
+ 0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
+ 0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
+ 0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
+ 0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
+ 0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
+ 0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
+ 0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
+ 0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
+ 0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
+ 0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
+ 0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
+ 0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
+ 0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
+ 0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
+ 0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
+ 0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
+ 0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
+ 0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
+ 0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
+ 0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
+ 0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
+ 0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
+ 0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
+ 0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
+ 0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
+ 0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
+ 0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
+ 0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
+ 0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
+ 0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
+ 0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
+ 0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
+ 0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
+ 0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
+ 0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
+ 0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
+ 0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
+ 0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
+ 0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
+ 0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
+ 0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
+ 0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
+ 0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
+ 0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
+ 0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
+ 0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
+ 0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
+ 0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
+ 0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
+ 0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
+ 0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
+ 0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
+ 0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
+ 0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
+ 0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
+ 0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
+ 0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
+ 0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
+ 0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
+ 0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
+ 0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
+ 0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
+ 0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
+ 0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
+ 0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
+ 0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
+ 0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
+ 0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
+ 0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
+ 0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
+ 0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
+ 0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
+ 0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
+ 0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
+ 0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
+ 0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
+ 0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
+ 0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
+ 0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
+ 0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
+ 0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
+ 0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
+ 0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
+ 0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
+ 0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
+ 0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
+ 0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
+ 0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
+ 0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
+ 0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
+ 0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
+ 0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
+ 0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
+ 0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
+ 0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
+ 0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
+ 0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
+ 0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
+ 0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
+ 0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
+ 0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
+ 0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
+ 0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
+ 0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
+ 0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
+ 0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
+ 0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
+ 0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
+ 0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
+ 0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
+ 0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
+ 0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
+ 0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
+ 0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
+ 0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
+ 0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
+ 0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
+ 0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
+ 0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
+ 0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
+ 0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
+ 0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
+ 0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
+ 0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
+ 0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
+ 0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
+ 0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
+ 0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
+ 0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
+ 0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
+ 0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
+ 0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
+ 0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
+ 0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
+ 0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
+ 0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
+ 0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
+ 0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
+ 0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
+ 0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
+ 0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
+ 0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
+ 0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
+ 0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
+ 0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
+ 0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
+ 0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
+ 0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
+ 0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
+ 0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
+ 0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
+ 0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
+ 0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
+ 0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
+ 0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
+ 0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
+ 0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
+ 0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
+ 0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
+ 0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
+ 0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
+ 0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
+ 0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
+ 0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
+ 0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
+ 0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
+ 0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
+ 0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
+ 0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
+ 0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
+ 0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
+ 0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
+ 0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
+ 0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
+ 0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
+ 0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
+ 0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
+ 0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
+ 0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
+ 0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
+ 0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
+ 0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
+ 0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
+ 0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
+ 0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
+ 0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
+ 0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
+ 0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
+ 0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
+ 0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
+ 0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
+ 0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
+ 0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
+ 0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
+ 0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
+ 0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
+ 0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
+ 0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
+ 0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
+ 0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
+ 0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
+ 0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
+ 0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
+ 0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
+ 0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
+ 0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
+ 0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
+ 0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
+ 0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
+ 0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
+ 0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
+ 0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
+ 0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
+ 0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
+ 0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
+ 0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
+ 0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
+ 0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
+ 0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
+ 0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
+ 0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
+ 0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
+ 0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
+ 0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
+ 0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
+ 0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
+ 0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
+ 0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
+ 0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
+ 0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
+ 0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
+ 0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
+ 0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
+ 0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
+ 0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
+ 0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
+ 0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
+ 0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
+ 0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
+ 0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
+ 0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
+ 0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
+ 0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
+ 0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
+ 0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
+ 0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
+ 0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
+ 0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
+ 0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
+ 0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
+ 0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
+ 0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
+ 0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
+ 0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
+ 0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
+ 0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
+ 0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
+ 0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
+ 0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
+ 0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
+ 0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
+ 0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
+ 0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
+ 0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
+ 0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
+ 0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
+ 0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
+ 0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
+ 0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
+ 0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
+ 0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
+ 0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
+ 0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
+ 0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
+ 0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
+ 0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
+ 0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
+ 0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
+ 0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
+ 0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
+ 0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
+ 0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
+ 0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
+ 0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
+ 0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
+ 0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
+ 0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
+ 0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
+ 0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
+ 0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
+ 0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
+ 0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
+ 0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
+ 0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
+ 0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
+ 0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
+ 0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
+ 0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
+ 0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
+ 0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
+ 0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
+ 0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
+ 0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
+ 0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
+ 0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
+ 0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
+ 0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
+ 0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
+ 0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
+ 0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
+ 0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
+ 0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
+ 0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
+ 0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
+ 0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
+ 0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
+ 0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
+ 0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
+ 0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
+ 0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
+ 0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
+ 0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
+ 0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
+ 0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
+ 0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
+ 0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
+ 0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
+ 0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
+ 0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
+ 0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
+ 0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
+ 0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
+ 0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
+ 0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
+ 0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
+ 0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
+ 0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
+ 0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
+ 0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
+ 0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
+ 0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
+ 0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
+ 0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
+ 0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
+ 0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
+ 0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
+ 0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
+ 0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
+ 0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
+ 0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
+ 0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
+ 0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
+ 0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
+ 0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
+ 0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
+ 0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
+ 0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
+ 0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
+ 0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
+ 0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
+ 0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
+ 0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
+ 0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
+ 0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
+ 0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
+ 0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
+ 0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
+ 0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
+ 0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
+ 0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
+ 0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
+ 0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
+ 0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
+ 0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
+ 0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
+ 0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
+ 0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
+ 0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
+ 0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
+ 0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
+ 0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
+ 0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
+ 0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
+ 0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
+ 0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
+ 0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
+ 0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
+ 0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
+ 0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
+ 0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
+ 0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
+ 0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
+ 0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
+ 0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
+ 0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
+ 0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
+ 0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
+ 0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
+ 0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
+ 0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
+ 0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
+ 0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
+ 0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
+ 0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
+ 0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
+ 0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
+ 0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
+ 0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
+ 0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
+ 0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
+ 0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
+ 0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
+ 0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
+ 0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
+ 0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
+ 0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
+ 0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
+ 0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
+ 0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
+ 0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
+ 0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
+ 0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
+ 0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
+ 0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
+ 0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
+ 0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
+ 0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
+ 0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
+ 0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
+ 0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
+ 0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
+ 0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
+ 0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
+ 0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
+ 0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
+ 0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
+ 0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
+ 0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
+ 0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
+ 0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
+ 0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
+ 0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
+ 0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
+ 0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
+ 0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
+ 0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
+ 0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
+ 0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
+ 0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
+ 0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
+ 0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
+ 0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
+ 0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
+ 0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
+ 0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
+ 0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
+ 0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
+ 0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
+ 0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
+ 0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
+ 0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
+ 0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
+ 0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
+ 0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
+ 0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
+ 0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
+ 0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
+ 0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
+ 0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
+ 0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
+ 0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
+ 0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
+ 0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
+ 0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
+ 0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
+ 0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
+ 0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
+ 0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
+ 0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
+ 0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
+ 0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
+ 0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
+ 0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
+ 0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
+ 0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
+ 0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
+ 0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
+ 0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
+ 0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
+ 0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
+ 0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
+ 0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
+ 0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
+ 0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
+ 0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
+ 0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
+ 0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
+ 0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
+ 0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
+ 0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
+ 0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
+ 0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
+ 0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
+ 0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
+ 0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
+ 0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
+ 0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
+ 0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
+ 0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
+ 0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
+ 0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
+ 0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
+ 0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
+ 0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
+ 0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
+ 0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
+ 0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
+ 0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
+ 0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
+ 0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
+ 0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
+ 0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
+ 0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
+ 0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
+ 0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
+ 0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
+ 0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
+ 0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
+ 0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
+ 0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
+ 0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
+ 0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
+ 0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
+ 0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
+ 0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
+ 0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
+ 0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
+ 0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
+ 0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
+ 0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
+ 0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
+ 0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
+ 0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
+ 0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
+ 0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
+ 0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
+ 0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
+ 0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
+ 0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
+ 0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
+ 0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
+ 0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
+ 0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
+ 0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
+ 0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
+ 0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
+ 0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
+ 0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
+ 0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
+ 0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
+ 0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
+ 0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
+ 0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
+ 0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
+ 0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
+ 0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
+ 0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
+ 0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
+ 0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
+ 0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
+ 0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
+ 0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
+ 0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
+ 0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
+ 0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
+ 0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
+ 0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
+ 0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
+ 0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
+ 0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
+ 0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
+ 0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
+ 0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
+ 0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
+ 0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
+ 0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
+ 0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
+ 0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
+ 0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
+ 0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
+ 0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
+ 0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
+ 0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
+ 0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
+ 0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
+ 0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
+ 0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
+ 0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
+ 0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
+ 0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
+ 0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
+ 0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
+ 0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
+ 0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
+ 0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
+ 0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
+ 0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
+ 0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
+ 0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
+ 0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
+ 0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
+ 0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
+ 0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
+ 0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
+ 0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
+ 0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
+ 0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
+ 0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
+ 0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
+ 0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
+ 0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
+ 0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
+ 0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
+ 0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
+ 0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
+ 0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
+ 0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
+ 0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
+ 0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
+ 0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
+ 0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
+ 0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
+ 0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
+ 0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
+ 0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
+ 0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
+ 0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
+ 0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
+ 0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
+ 0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
+ 0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
+ 0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
+ 0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
+ 0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
+ 0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
+ 0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
+ 0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
+ 0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
+ 0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
+ 0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
+ 0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
+ 0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
+ 0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
+ 0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
+ 0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
+ 0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
+ 0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
+ 0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
+ 0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
+ 0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
+ 0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
+ 0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
+ 0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
+ 0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
+ 0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
+ 0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
+ 0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
+ 0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
+ 0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
+ 0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
+ 0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
+ 0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
+ 0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
+ 0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
+ 0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
+ 0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
+ 0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
+ 0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
+ 0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
+ 0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
+ 0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
+ 0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
+ 0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
+ 0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
+ 0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
+ 0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
+ 0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
+ 0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
+ 0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
+ 0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
+ 0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
+ 0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
+ 0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
+ 0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
+ 0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
+ 0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
+ 0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
+ 0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
+ 0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
+ 0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
+ 0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
+ 0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
+ 0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
+ 0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
+ 0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
+ 0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
+ 0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
+ 0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
+ 0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
+ 0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
+ 0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
+ 0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
+ 0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
+ 0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
+ 0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
+ 0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
+ 0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
+ 0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
+ 0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
+ 0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
+ 0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
+ 0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
+ 0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
+ 0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
+ 0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
+ 0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
+ 0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
+ 0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
+ 0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
+ 0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
+ 0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
+ 0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
+ 0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
+ 0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
+ 0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
+ 0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
+ 0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
+ 0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
+ 0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
+ 0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
+ 0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
+ 0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
+ 0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
+ 0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
+ 0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
+ 0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
+ 0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
+ 0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
+ 0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
+ 0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
+ 0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
+ 0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
+ 0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
+ 0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
+ 0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
+ 0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
+ 0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
+ 0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
+ 0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
+ 0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
+ 0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
+ 0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
+ 0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
+ 0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
+ 0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
+ 0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
+ 0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
+ 0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
+ 0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
+ 0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
+ 0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
+ 0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
+ 0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
+ 0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
+ 0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
+ 0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
+ 0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
+ 0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
+ 0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
+ 0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
+ 0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
+ 0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
+ 0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
+ 0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
+ 0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
+ 0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
+ 0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
+ 0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
+ 0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
+ 0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
+ 0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
+ 0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
+ 0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
+ 0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
+ 0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
+ 0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
+ 0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
+ 0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
+ 0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
+ 0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
+ 0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
+ 0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
+ 0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
+ 0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
+ 0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
+ 0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
+ 0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
+ 0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
+ 0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
+ 0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
+ 0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
+ 0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
+ 0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
+ 0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
+ 0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
+ 0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
+ 0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
+ 0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
+ 0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
+ 0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
+ 0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
+ 0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
+ 0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
+ 0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
+ 0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
+ 0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
+ 0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
+ 0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
+ 0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
+ 0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
+ 0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
+ 0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
+ 0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
+ 0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
+ 0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
+ 0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
+ 0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
+ 0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
+ 0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
+ 0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
+ 0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
+ 0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
+ 0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
+ 0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
+ 0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
+ 0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
+ 0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
+ 0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
+ 0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
+ 0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
+ 0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
+ 0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
+ 0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
+ 0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
+ 0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
+ 0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
+ 0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
+ 0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
+ 0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
+ 0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
+ 0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
+ 0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
+ 0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
+ 0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
+ 0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
+ 0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
+ 0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
+ 0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
+ 0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
+ 0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
+ 0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
+ 0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
+ 0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
+ 0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
+ 0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
+ 0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
+ 0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
+ 0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
+ 0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
+ 0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
+ 0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
+ 0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
+ 0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
+ 0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
+ 0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
+ 0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
+ 0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
+ 0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
+ 0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
+ 0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
+ 0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
+ 0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
+ 0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
+ 0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
+ 0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
+ 0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
+ 0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
+ 0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
+ 0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
+ 0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
+ 0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
+ 0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
+ 0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
+ 0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
+ 0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
+ 0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
+ 0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
+ 0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
+ 0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
+ 0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
+ 0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
+ 0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
+ 0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
+ 0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
+ 0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
+ 0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
+ 0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
+ 0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
+ 0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
+ 0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
+ 0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
+ 0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
+ 0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
+ 0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
+ 0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
+ 0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
+ 0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
+ 0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
+ 0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
+ 0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
+ 0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
+ 0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
+ 0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
+ 0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
+ 0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
+ 0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
+ 0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
+ 0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
+ 0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
+ 0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
+ 0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
+ 0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
+ 0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
+ 0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
+ 0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
+ 0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
+ 0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
+ 0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
+ 0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
+ 0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
+ 0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
+ 0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
+ 0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
+ 0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
+ 0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
+ 0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
+ 0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
+ 0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
+ 0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
+ 0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
+ 0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
+ 0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
+ 0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
+ 0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
+ 0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
+ 0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
+ 0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
+ 0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
+ 0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
+ 0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
+ 0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
+ 0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
+ 0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
+ 0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
+ 0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
+ 0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
+ 0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
+ 0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
+ 0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
+ 0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
+ 0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
+ 0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
+ 0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
+ 0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
+ 0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
+ 0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
+ 0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
+ 0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
+ 0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
+ 0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
+ 0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
+ 0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
+ 0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
+ 0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
+ 0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
+ 0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
+ 0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
+ 0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
+ 0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
+ 0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
+ 0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
+ 0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
+ 0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
+ 0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
+ 0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
+ 0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
+ 0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
+ 0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
+ 0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
+ 0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
+ 0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
+ 0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
+ 0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
+ 0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
+ 0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
+ 0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
+ 0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
+ 0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
+ 0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
+ 0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
+ 0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
+ 0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
+ 0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
+ 0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
+ 0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
+ 0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
+ 0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
+ 0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
+ 0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
+ 0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
+ 0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
+ 0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
+ 0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
+ 0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
+ 0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
+ 0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
+ 0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
+ 0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
+ 0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
+ 0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
+ 0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
+ 0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
+ 0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
+ 0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
+ 0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
+ 0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
+ 0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
+ 0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
+ 0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
+ 0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
+ 0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
+ 0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
+ 0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
+ 0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
+ 0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
+ 0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
+ 0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
+ 0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
+ 0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
+ 0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
+ 0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
+ 0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
+ 0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
+ 0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
+ 0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
+ 0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
+ 0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
+ 0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
+ 0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
+ 0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
+ 0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
+ 0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
+ 0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
+ 0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
+ 0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
+ 0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
+ 0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
+ 0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
+ 0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
+ 0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
+ 0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
+ 0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
+ 0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
+ 0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
+ 0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
+ 0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
+ 0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
+ 0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
+ 0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
+ 0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
+ 0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
+ 0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
+ 0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
+ 0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
+ 0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
+ 0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
+ 0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
+ 0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
+ 0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
+ 0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
+ 0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
+ 0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
+ 0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
+ 0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
+ 0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
+ 0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
+ 0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
+ 0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
+ 0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
+ 0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
+ 0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
+ 0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
+ 0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
+ 0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
+ 0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
+ 0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
+ 0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
+ 0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
+ 0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
+ 0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
+ 0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
+ 0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
+ 0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
+ 0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
+ 0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
+ 0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
+ 0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
+ 0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
+ 0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
+ 0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
+ 0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
+ 0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
+ 0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
+ 0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
+ 0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
+ 0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
+ 0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
+ 0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
+ 0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
+ 0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
+ 0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
+ 0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
+ 0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
+ 0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
+ 0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
+ 0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
+ 0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
+ 0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
+ 0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
+ 0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
+ 0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
+ 0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
+ 0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
+ 0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
+ 0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
+ 0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
+ 0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
+ 0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
+ 0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
+ 0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
+ 0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
+ 0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
+ 0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
+ 0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
+ 0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
+ 0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
+ 0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
+ 0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
+ 0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
+ 0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
+ 0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
+ 0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
+ 0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
+ 0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
+ 0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
+ 0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
+ 0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
+ 0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
+ 0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
+ 0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
+ 0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
+ 0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
+ 0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
+ 0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
+ 0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
+ 0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
+ 0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
+ 0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
+ 0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
+ 0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
+ 0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
+ 0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
+ 0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
+ 0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
+ 0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
+ 0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
+ 0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
+ 0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
+ 0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
+ 0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
+ 0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
+ 0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
+ 0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
+ 0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
+ 0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
+ 0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
+ 0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
+ 0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
+ 0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
+ 0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
+ 0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
+ 0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
+ 0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
+ 0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
+ 0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
+ 0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
+ 0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
+ 0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
+ 0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
+ 0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
+ 0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
+ 0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
+ 0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
+ 0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
+ 0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
+ 0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
+ 0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
+ 0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
+ 0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
+ 0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
+ 0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
+ 0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
+ 0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
+ 0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
+ 0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
+ 0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
+ 0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
+ 0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
+ 0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
+ 0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
+ 0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
+ 0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
+ 0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
+ 0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
+ 0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
+ 0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
+ 0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
+ 0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
+ 0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
+ 0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
+ 0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
+ 0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
+ 0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
+ 0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
+ 0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
+ 0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
+ 0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
+ 0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
+ 0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
+ 0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
+ 0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
+ 0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
+ 0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
+ 0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
+ 0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
+ 0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
+ 0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
+ 0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
+ 0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
+ 0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
+ 0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
+ 0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
+ 0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
+ 0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
+ 0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
+ 0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
+ 0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
+ 0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
+ 0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
+ 0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
+ 0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
+ 0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
+ 0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
+ 0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
+ 0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
+ 0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
+ 0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
+ 0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
+ 0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
+ 0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
+ 0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
+ 0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
+ 0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
+ 0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
+ 0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
+ 0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
+ 0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
+ 0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
+ 0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
+ 0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
+ 0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
+ 0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
+ 0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
+ 0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
+ 0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
+ 0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
+ 0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
+ 0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
+ 0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
+ 0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
+ 0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
+ 0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
+ 0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
+ 0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
+ 0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
+ 0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
+ 0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
+ 0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
+ 0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
+ 0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
+ 0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
+ 0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
+ 0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
+ 0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
+ 0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
+ 0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
+ 0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
+ 0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
+ 0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
+ 0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
+ 0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
+ 0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
+ 0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
+ 0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
+ 0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
+ 0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
+ 0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
+ 0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
+ 0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
+ 0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
+ 0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
+ 0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
+ 0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
+ 0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
+ 0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
+ 0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
+ 0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
+ 0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
+ 0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
+ 0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
+ 0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
+ 0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
+ 0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
+ 0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
+ 0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
+ 0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
+ 0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
+ 0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
+ 0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
+ 0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
+ 0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
+ 0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
+ 0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
+ 0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
+ 0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
+ 0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
+ 0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
+ 0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
+ 0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
+ 0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
+ 0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
+ 0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
+ 0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
+ 0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
+ 0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
+ 0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
+ 0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
+ 0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
+ 0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
+ 0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
+ 0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
+ 0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
+ 0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
+ 0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
+ 0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
+ 0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
+ 0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
+ 0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
+ 0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
+ 0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
+ 0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
+ 0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
+ 0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
+ 0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
+ 0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
+ 0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
+ 0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
+ 0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
+ 0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
+ 0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
+ 0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
+ 0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
+ 0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
+ 0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
+ 0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
+ 0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
+ 0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
+ 0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
+ 0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
+ 0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
+ 0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
+ 0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
+ 0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
+ 0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
+ 0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
+ 0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
+ 0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
+ 0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
+ 0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
+ 0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
+ 0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
+ 0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
+ 0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
+ 0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
+ 0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
+ 0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
+ 0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
+ 0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
+ 0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
+ 0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
+ 0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
+ 0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
+ 0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
+ 0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
+ 0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
+ 0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
+ 0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
+ 0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
+ 0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
+ 0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
+ 0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
+ 0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
+ 0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
+ 0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
+ 0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
+ 0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
+ 0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
+ 0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
+ 0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
+ 0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
+ 0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
+ 0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
+ 0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
+ 0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
+ 0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
+ 0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
+ 0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
+ 0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
+ 0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
+ 0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
+ 0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
+ 0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
+ 0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
+ 0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
+ 0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
+ 0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
+ 0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
+ 0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
+ 0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
+ 0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
+ 0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
+ 0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
+ 0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
+ 0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
+ 0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
+ 0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
+ 0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
+ 0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
+ 0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
+ 0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
+ 0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
+ 0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
+ 0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
+ 0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
+ 0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
+ 0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
+ 0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
+ 0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
+ 0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
+ 0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
+ 0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
+ 0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
+ 0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
+ 0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
+ 0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
+ 0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
+ 0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
+ 0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
+ 0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
+ 0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
+ 0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
+ 0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
+ 0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
+ 0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
+ 0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
+ 0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
+ 0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
+ 0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
+ 0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
+ 0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
+ 0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
+ 0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
+ 0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
+ 0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
+ 0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
+ 0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
+ 0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
+ 0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
+ 0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
+ 0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
+ 0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
+ 0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
+ 0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
+ 0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
+ 0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
+ 0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
+ 0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
+ 0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
+ 0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
+ 0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
+ 0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
+ 0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
+ 0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
+ 0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
+ 0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
+ 0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
+ 0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
+ 0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
+ 0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
+ 0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
+ 0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
+ 0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
+ 0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
+ 0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
+ 0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
+ 0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
+ 0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
+ 0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
+ 0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
+ 0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
+ 0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
+ 0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
+ 0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
+ 0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
+ 0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
+ 0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
+ 0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
+ 0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
+ 0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
+ 0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
+ 0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
+ 0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
+ 0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
+ 0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
+ 0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
+ 0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
+ 0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
+ 0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
+ 0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
+ 0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
+ 0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
+ 0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
+ 0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
+ 0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
+ 0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
+ 0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
+ 0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
+ 0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
+ 0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
+ 0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
+ 0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
+ 0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
+ 0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
+ 0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
+ 0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
+ 0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
+ 0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
+ 0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
+ 0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
+ 0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
+ 0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
+ 0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
+ 0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
+ 0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
+ 0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
+ 0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
+ 0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
+ 0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
+ 0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
+ 0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
+ 0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
+ 0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
+ 0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
+ 0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
+ 0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
+ 0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
+ 0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
+ 0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
+ 0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
+ 0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
+ 0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
+ 0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
+ 0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
+ 0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
+ 0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
+ 0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
+ 0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
+ 0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
+ 0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
+ 0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
+ 0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
+ 0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
+ 0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
+ 0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
+ 0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
+ 0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
+ 0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
+ 0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
+ 0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
+ 0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
+ 0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
+ 0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
+ 0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
+ 0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
+ 0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
+ 0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
+ 0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
+ 0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
+ 0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
+ 0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
+ 0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
+ 0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
+ 0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
+ 0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
+ 0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
+ 0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
+ 0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
+ 0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
+ 0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
+ 0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
+ 0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
+ 0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
+ 0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
+ 0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
+ 0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
+ 0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
+ 0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
+ 0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
+ 0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
+ 0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
+ 0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
+ 0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
+ 0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
+ 0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
+ 0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
+ 0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
+ 0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
+ 0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
+ 0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
+ 0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
+ 0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
+ 0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
+ 0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
+ 0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
+ 0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
+ 0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
+ 0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
+ 0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
+ 0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
+ 0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
+ 0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
+ 0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
+ 0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
+ 0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
+ 0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
+ 0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
+ 0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
+ 0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
+ 0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
+ 0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
+ 0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
+ 0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
+ 0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
+ 0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
+ 0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
+ 0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
+ 0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
+ 0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
+ 0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
+ 0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
+ 0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
+ 0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
+ 0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
+ 0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
+ 0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
+ 0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
+ 0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
+ 0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
+ 0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
+ 0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
+ 0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
+ 0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
+ 0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
+ 0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
+ 0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
+ 0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
+ 0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
+ 0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
+ 0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
+ 0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
+ 0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
+ 0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
+ 0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
+ 0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
+ 0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
+ 0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
+ 0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
+ 0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
+ 0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
+ 0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
+ 0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
+ 0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
+ 0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
+ 0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
+ 0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
+ 0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
+ 0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
+ 0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
+ 0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
+ 0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
+ 0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
+ 0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
+ 0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
+ 0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
+ 0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
+ 0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
+ 0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
+ 0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
+ 0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
+ 0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
+ 0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
+ 0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
+};
+
+/**
+* @brief Initialization function for the Q31 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 000000000..0b6613cde
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,482 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q15.c
+*
+* Description: RFFT & RIFFT Q15 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different RFFT sizes.
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+ * \par
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
+ * \par
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
+ */
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst)
+{
+ const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex readix-4 IFFT process */
+ arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex readix-4 FFT process */
+ arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+ arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param *pSrc points to the input buffer.
+ * @param fftLen length of FFT.
+ * @param *pATable points to the A twiddle Coef buffer.
+ * @param *pBTable points to the B twiddle Coef buffer.
+ * @param *pDst points to the output buffer.
+ * @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ * The function implements a Real FFT
+ */
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+
+
+// pSrc[2u * fftLen] = pSrc[0];
+// pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ pSrc1 = &pSrc[2];
+ pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ i = 1u;
+
+ while(i < fftLen)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+ /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+ outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+ outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+ outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+ /* write output */
+ pDst[2u * i] = (q15_t) outR;
+ pDst[(2u * i) + 1u] = outI >> 15u;
+
+ /* write complex conjugate output */
+ pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+ pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i++;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ i = 1u;
+
+ while(i < fftLen)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc1 * *pCoefA;
+ outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+ outR = outR + (*pSrc2 * *pCoefB);
+ outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *pSrc2 * *(pCoefB + 1);
+ outI = outI - (*(pSrc2 + 1) * *pCoefB);
+ outI = outI + (*(pSrc1 + 1) * *pCoefA);
+ outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ pDst[2u * i] = (q15_t) outR;
+ pDst[(2u * i) + 1u] = outI >> 15u;
+
+ /* write complex conjugate output */
+ pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+ pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i++;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ * The function implements a Real IFFT
+ */
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+ q15_t *pDst1 = &pDst[0];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ pSrc1 = &pSrc[0];
+ pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ i = fftLen;
+
+ while(i > 0u)
+ {
+
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+ /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+ outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+ /*
+ -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+ /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+ outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+ *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ i = fftLen;
+
+ while(i > 0u)
+ {
+
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc2 * *pCoefB;
+ outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+ outR = outR + (*pSrc1 * *pCoefA);
+ outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+ /*
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *(pSrc1 + 1) * *pCoefA;
+ outI = outI - (*pSrc1 * *(pCoefA + 1));
+ outI = outI - (*pSrc2 * *(pCoefB + 1));
+ outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ *pDst1++ = (q15_t) outR;
+ *pDst1++ = (q15_t) (outI >> 15);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 000000000..488cbd9a5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,349 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q31.c
+*
+* Description: RFFT & RIFFT Q31 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different RFFT sizes.
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+ * \par
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"
+ *
+ * \par
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"
+ */
+
+void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst)
+{
+ const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex readix-4 IFFT process */
+ arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier);
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex readix-4 FFT process */
+ arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+ /* Real FFT core process */
+ arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+
+ /**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+ q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * pATable[2 * i] */
+ outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+ /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+ outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+ /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+ /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+ /* write output */
+ *pOut1++ = (outR << 1u);
+ *pOut1++ = (outI << 1u);
+
+ /* write complex conjugate output */
+ *pOut2-- = -(outI << 1u);
+ *pOut2-- = (outR << 1u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pIn[2 * i] * pATable[2 * i] */
+ outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+ /* - pIn[2 * i] * pATable[2 * i + 1] */
+ outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+ /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+ /* pIn[2 * i + 1] * pATable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+ /* write output */
+ *pDst++ = (outR << 1u);
+ *pDst++ = (outI << 1u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+
+ }
+
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h
new file mode 100644
index 000000000..7a59b5923
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h
new file mode 100644
index 000000000..0b7c6902b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h
@@ -0,0 +1,7304 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * <b>Using the Library</b>
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * <b>Examples</b>
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * <b>Toolchain Support</b>
+ *
+ * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * <b>Building the Library</b>
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * <b>Pre-processor Macros</b>
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+#define __CLZ __clz
+#elif defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+#if defined ( __CC_ARM ) //Keil
+//SMMLAR
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+ #define LOW_OPTIMIZATION_EXIT
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h
new file mode 100644
index 000000000..749f00d43
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h b/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h
new file mode 100644
index 000000000..bbb9f927f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef FIR_F32_H
+#define FIR_F32_H
+
+#include <stdint.h>
+#include "arm_math.h"
+
+namespace dsp {
+
+template<uint16_t num_taps, uint32_t block_size=32>
+class FIR_f32 {
+public:
+ FIR_f32(const float32_t *coeff) {
+ arm_fir_init_f32(&fir, num_taps, (float32_t*)coeff, fir_state, block_size);
+ }
+
+ void process(float32_t *sgn_in, float32_t *sgn_out) {
+ arm_fir_f32(&fir, sgn_in, sgn_out, block_size);
+ }
+
+ void reset(void) {
+ memset(fir_state, 0, sizeof(fir_state));
+ }
+
+private:
+ arm_fir_instance_f32 fir;
+ float32_t fir_state[block_size + num_taps - 1];
+};
+
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp b/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp
new file mode 100644
index 000000000..63163c858
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Sine_f32.h"
+#include "math_helper.h"
+
+#define RAD_2PI (2. * PI)
+
+namespace dsp {
+
+Sine_f32::Sine_f32(uint32_t frequency, uint32_t sample_rate, float32_t amplitude, float32_t phase, uint32_t block_size) {
+ _dx = RAD_2PI * ((float32_t)frequency / (float32_t)sample_rate);
+ _amplitude = amplitude;
+ _x = phase;
+ _block_size = block_size;
+}
+
+void Sine_f32::process(float32_t *sgn_in, float32_t *sgn_out) {
+ for (uint32_t i=0; i<_block_size; i++) {
+ *sgn_out = *sgn_in + (_amplitude * arm_sin_f32(_x));
+ sgn_in++; sgn_out++;
+ _x += _dx;
+ }
+}
+
+void Sine_f32::generate(float32_t *sgn) {
+ for (uint32_t i=0; i<_block_size; i++) {
+ *sgn = (_amplitude * arm_sin_f32(_x));
+ sgn++;
+ _x += _dx;
+ }
+}
+
+void Sine_f32::reset(void) {
+ _x = 0.0f;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h b/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h
new file mode 100644
index 000000000..798778572
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef SINE_F32_H
+#define SINE_F32_H
+
+#include <stdint.h>
+#include "arm_math.h"
+
+namespace dsp {
+
+class Sine_f32 {
+public:
+ Sine_f32(uint32_t frequency, uint32_t sample_rate=48000, float32_t amplitude=1.f, float32_t phase=0.0, uint32_t block_size=32);
+
+ void process(float32_t *sgn_in, float32_t *sgn_out);
+
+ void generate(float32_t *sgn);
+
+ void reset(void);
+
+private:
+ float32_t _dx;
+ float32_t _amplitude;
+ float32_t _x;
+ uint32_t _block_size;
+};
+
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h b/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h
new file mode 100644
index 000000000..0ac5e8e0f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef DSP_H
+#define DSP_H
+
+#include "math_helper.h"
+#include "arm_math.h"
+
+#include "FIR_f32.h"
+#include "Sine_f32.h"
+
+using namespace dsp;
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp
new file mode 100644
index 000000000..01d94428c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp
@@ -0,0 +1,540 @@
+/*------------------------------------------------------------------------*/
+/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */
+/* (SBCS code pages) */
+/*------------------------------------------------------------------------*/
+/* 437 U.S. (OEM)
+/ 720 Arabic (OEM)
+/ 1256 Arabic (Windows)
+/ 737 Greek (OEM)
+/ 1253 Greek (Windows)
+/ 1250 Central Europe (Windows)
+/ 775 Baltic (OEM)
+/ 1257 Baltic (Windows)
+/ 850 Multilingual Latin 1 (OEM)
+/ 852 Latin 2 (OEM)
+/ 1252 Latin 1 (Windows)
+/ 855 Cyrillic (OEM)
+/ 1251 Cyrillic (Windows)
+/ 866 Russian (OEM)
+/ 857 Turkish (OEM)
+/ 1254 Turkish (Windows)
+/ 858 Multilingual Latin 1 + Euro (OEM)
+/ 862 Hebrew (OEM)
+/ 1255 Hebrew (Windows)
+/ 874 Thai (OEM, Windows)
+/ 1258 Vietnam (OEM, Windows)
+*/
+
+#include "ff.h"
+
+
+#if _CODE_PAGE == 437
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+ 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 720
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */
+ 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
+ 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+ 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+ 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
+ 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+ 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 737
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */
+ 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
+ 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+ 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
+ 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+ 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
+ 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
+ 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+ 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 775
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */
+ 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
+ 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
+ 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+ 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
+ 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
+ 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+ 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
+ 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
+ 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+ 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
+ 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 850
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+ 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 852
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
+ 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+ 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
+ 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
+ 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
+ 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
+ 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
+ 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+ 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 855
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */
+ 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
+ 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+ 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
+ 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+ 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
+ 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
+ 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
+ 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+ 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
+ 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+ 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
+ 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 857
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
+ 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 858
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+ 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 862
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */
+ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+ 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+ 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+ 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 866
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+ 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+ 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+ 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+ 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+ 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 874
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
+ 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
+ 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
+ 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
+ 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
+ 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
+ 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
+ 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
+ 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
+ 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
+ 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
+ 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+#elif _CODE_PAGE == 1250
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
+ 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
+ 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
+ 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
+ 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
+ 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
+ 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
+ 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
+ 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
+ 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
+ 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
+};
+
+#elif _CODE_PAGE == 1251
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */
+ 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
+ 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
+ 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
+ 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
+ 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
+ 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+ 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+ 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+ 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+ 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
+};
+
+#elif _CODE_PAGE == 1252
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+ 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+ 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
+};
+
+#elif _CODE_PAGE == 1253
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
+ 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
+ 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
+ 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
+ 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
+ 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
+ 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
+ 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
+ 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
+ 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
+};
+
+#elif _CODE_PAGE == 1254
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+ 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+ 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
+};
+
+#elif _CODE_PAGE == 1255
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
+ 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
+ 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
+ 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+ 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+ 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
+};
+
+#elif _CODE_PAGE == 1256
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
+ 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
+ 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
+ 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
+ 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+ 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
+ 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
+ 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
+ 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
+ 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
+}
+
+#elif _CODE_PAGE == 1257
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
+ 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
+ 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
+ 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
+ 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
+ 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
+ 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
+ 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
+ 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
+ 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
+ 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
+};
+
+#elif _CODE_PAGE == 1258
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
+ 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
+ 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
+};
+
+#endif
+
+
+#if !_TBLDEF || !_USE_LFN
+#error This file is not needed in current configuration. Remove from the project.
+#endif
+
+
+WCHAR ff_convert ( /* Converted character, Returns zero on error */
+ WCHAR src, /* Character code to be converted */
+ UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
+)
+{
+ WCHAR c;
+
+
+ if (src < 0x80) { /* ASCII */
+ c = src;
+
+ } else {
+ if (dir) { /* OEMCP to Unicode */
+ c = (src >= 0x100) ? 0 : Tbl[src - 0x80];
+
+ } else { /* Unicode to OEMCP */
+ for (c = 0; c < 0x80; c++) {
+ if (src == Tbl[c]) break;
+ }
+ c = (c + 0x80) & 0xFF;
+ }
+ }
+
+ return c;
+}
+
+
+WCHAR ff_wtoupper ( /* Upper converted character */
+ WCHAR chr /* Input character */
+)
+{
+ static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 };
+ static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
+ int i;
+
+
+ for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
+
+ return tbl_lower[i] ? tbl_upper[i] : chr;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp
new file mode 100644
index 000000000..1f719725e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */
+/*-----------------------------------------------------------------------*/
+/* This is a stub disk I/O module that acts as front end of the existing */
+/* disk I/O modules and attach it to FatFs module with common interface. */
+/*-----------------------------------------------------------------------*/
+#include "ffconf.h"
+#include "diskio.h"
+
+#include "mbed_debug.h"
+#include "FATFileSystem.h"
+
+using namespace mbed;
+
+DSTATUS disk_initialize (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ debug_if(FFS_DBG, "disk_initialize on drv [%d]\n", drv);
+ return (DSTATUS)FATFileSystem::_ffs[drv]->disk_initialize();
+}
+
+DSTATUS disk_status (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ debug_if(FFS_DBG, "disk_status on drv [%d]\n", drv);
+ return (DSTATUS)FATFileSystem::_ffs[drv]->disk_status();
+}
+
+DRESULT disk_read (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to read (1..255) */
+)
+{
+ debug_if(FFS_DBG, "disk_read(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+ if (FATFileSystem::_ffs[drv]->disk_read((uint8_t*)buff, sector, count))
+ return RES_PARERR;
+ else
+ return RES_OK;
+}
+
+#if _READONLY == 0
+DRESULT disk_write (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to write (1..255) */
+)
+{
+ debug_if(FFS_DBG, "disk_write(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+ if (FATFileSystem::_ffs[drv]->disk_write((uint8_t*)buff, sector, count))
+ return RES_PARERR;
+ else
+ return RES_OK;
+}
+#endif /* _READONLY */
+
+DRESULT disk_ioctl (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE ctrl, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ debug_if(FFS_DBG, "disk_ioctl(%d)\n", ctrl);
+ switch(ctrl) {
+ case CTRL_SYNC:
+ if(FATFileSystem::_ffs[drv] == NULL) {
+ return RES_NOTRDY;
+ } else if(FATFileSystem::_ffs[drv]->disk_sync()) {
+ return RES_ERROR;
+ }
+ return RES_OK;
+ case GET_SECTOR_COUNT:
+ if(FATFileSystem::_ffs[drv] == NULL) {
+ return RES_NOTRDY;
+ } else {
+ DWORD res = FATFileSystem::_ffs[drv]->disk_sectors();
+ if(res > 0) {
+ *((DWORD*)buff) = res; // minimum allowed
+ return RES_OK;
+ } else {
+ return RES_ERROR;
+ }
+ }
+ case GET_BLOCK_SIZE:
+ *((DWORD*)buff) = 1; // default when not known
+ return RES_OK;
+
+ }
+ return RES_PARERR;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h
new file mode 100644
index 000000000..a469ebb85
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h
@@ -0,0 +1,76 @@
+//-----------------------------------------------------------------------
+// Low level disk interface modlue include file
+//-----------------------------------------------------------------------
+
+#ifndef _DISKIO
+
+#define _READONLY 0 // 1: Remove write functions
+#define _USE_IOCTL 1 // 1: Use disk_ioctl fucntion
+
+#include "integer.h"
+
+
+// Status of Disk Functions
+typedef BYTE DSTATUS;
+
+// Results of Disk Functions
+typedef enum {
+ RES_OK = 0, // 0: Successful
+ RES_ERROR, // 1: R/W Error
+ RES_WRPRT, // 2: Write Protected
+ RES_NOTRDY, // 3: Not Ready
+ RES_PARERR // 4: Invalid Parameter
+} DRESULT;
+
+
+// Prototypes for disk control functions
+
+int assign_drives (int, int);
+DSTATUS disk_initialize (BYTE);
+DSTATUS disk_status (BYTE);
+DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
+#if _READONLY == 0
+DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
+#endif
+DRESULT disk_ioctl (BYTE, BYTE, void*);
+
+
+
+// Disk Status Bits (DSTATUS)
+#define STA_NOINIT 0x01 // Drive not initialized
+#define STA_NODISK 0x02 // No medium in the drive
+#define STA_PROTECT 0x04 // Write protected
+
+
+// Command code for disk_ioctrl fucntion
+
+// Generic command (defined for FatFs)
+#define CTRL_SYNC 0 // Flush disk cache (for write functions)
+#define GET_SECTOR_COUNT 1 // Get media size (for only f_mkfs())
+#define GET_SECTOR_SIZE 2 // Get sector size (for multiple sector size (_MAX_SS >= 1024))
+#define GET_BLOCK_SIZE 3 // Get erase block size (for only f_mkfs())
+#define CTRL_ERASE_SECTOR 4 // Force erased a block of sectors (for only _USE_ERASE)
+
+// Generic command
+#define CTRL_POWER 5 // Get/Set power status
+#define CTRL_LOCK 6 // Lock/Unlock media removal
+#define CTRL_EJECT 7 // Eject media
+
+// MMC/SDC specific ioctl command
+#define MMC_GET_TYPE 10 // Get card type
+#define MMC_GET_CSD 11 // Get CSD
+#define MMC_GET_CID 12 // Get CID
+#define MMC_GET_OCR 13 // Get OCR
+#define MMC_GET_SDSTAT 14 // Get SD status
+
+// ATA/CF specific ioctl command
+#define ATA_GET_REV 20 // Get F/W revision
+#define ATA_GET_MODEL 21 // Get model name
+#define ATA_GET_SN 22 // Get serial number
+
+// NAND specific ioctl command
+#define NAND_FORMAT 30 // Create physical format
+
+
+#define _DISKIO
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp
new file mode 100644
index 000000000..fe786a747
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp
@@ -0,0 +1,4153 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - FAT file system module R0.09a (C)ChaN, 2012
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/ Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Feb 26,'06 R0.00 Prototype.
+/
+/ Apr 29,'06 R0.01 First stable version.
+/
+/ Jun 01,'06 R0.02 Added FAT12 support.
+/ Removed unbuffered mode.
+/ Fixed a problem on small (<32M) partition.
+/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
+/
+/ Sep 22,'06 R0.03 Added f_rename().
+/ Changed option _FS_MINIMUM to _FS_MINIMIZE.
+/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
+/ Fixed f_mkdir() creates incorrect directory on FAT32.
+/
+/ Feb 04,'07 R0.04 Supported multiple drive system.
+/ Changed some interfaces for multiple drive system.
+/ Changed f_mountdrv() to f_mount().
+/ Added f_mkfs().
+/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
+/ Added a capability of extending file size to f_lseek().
+/ Added minimization level 3.
+/ Fixed an endian sensitive code in f_mkfs().
+/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
+/ Added FSInfo support.
+/ Fixed DBCS name can result FR_INVALID_NAME.
+/ Fixed short seek (<= csize) collapses the file object.
+/
+/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs().
+/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
+/ Fixed f_mkdir() on FAT32 creates incorrect directory.
+/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
+/ Fixed off by one error at FAT sub-type determination.
+/ Fixed btr in f_read() can be mistruncated.
+/ Fixed cached sector is not flushed when create and close without write.
+/
+/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets().
+/ Improved performance of f_lseek() on moving to the same or following cluster.
+/
+/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+/ Added long file name feature.
+/ Added multiple code page feature.
+/ Added re-entrancy for multitask operation.
+/ Added auto cluster size selection to f_mkfs().
+/ Added rewind option to f_readdir().
+/ Changed result code of critical errors.
+/ Renamed string functions to avoid name collision.
+/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
+/ Added multiple sector size feature.
+/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
+/ Fixed wrong cache control in f_lseek().
+/ Added relative path feature.
+/ Added f_chdir() and f_chdrive().
+/ Added proper case conversion to extended char.
+/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
+/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
+/ Fixed name matching error on the 13 char boundary.
+/ Added a configuration option, _LFN_UNICODE.
+/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+/
+/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3)
+/ Added file lock feature. (_FS_SHARE)
+/ Added fast seek feature. (_USE_FASTSEEK)
+/ Changed some types on the API, XCHAR->TCHAR.
+/ Changed fname member in the FILINFO structure on Unicode cfg.
+/ String functions support UTF-8 encoding files on Unicode cfg.
+/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
+/ Added sector erase feature. (_USE_ERASE)
+/ Moved file lock semaphore table from fs object to the bss.
+/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
+/ Fixed f_mkfs() creates wrong FAT32 volume.
+/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
+/ f_lseek() reports required table size on creating CLMP.
+/ Extended format syntax of f_printf function.
+/ Ignores duplicated directory separators in given path name.
+/
+/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature.
+/ Added f_fdisk(). (_MULTI_PARTITION = 2)
+/ Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+/ Changed f_open() and f_opendir reject null object pointer to avoid crash.
+/ Changed option name _FS_SHARE to _FS_LOCK.
+/---------------------------------------------------------------------------*/
+
+#include "ff.h" /* FatFs configurations and declarations */
+#include "diskio.h" /* Declarations of low level disk I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 4004 /* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Definitions on sector size */
+#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
+#error Wrong sector size.
+#endif
+#if _MAX_SS != 512
+#define SS(fs) ((fs)->ssize) /* Variable sector size */
+#else
+#define SS(fs) 512U /* Fixed sector size */
+#endif
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area must not be used in re-entrant configuration.
+#endif
+#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
+#else
+#define ENTER_FF(fs)
+#define LEAVE_FF(fs, res) return res
+#endif
+
+#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
+
+
+/* File access control feature */
+#if _FS_LOCK
+#if _FS_READONLY
+#error _FS_LOCK must be 0 on read-only cfg.
+#endif
+typedef struct {
+ FATFS *fs; /* File ID 1, volume (NULL:blank entry) */
+ DWORD clu; /* File ID 2, directory */
+ WORD idx; /* File ID 3, directory index */
+ WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
+#define _DF1S 0x81 /* DBC 1st byte range 1 start */
+#define _DF1E 0x9F /* DBC 1st byte range 1 end */
+#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
+#define _DF2E 0xFC /* DBC 1st byte range 2 end */
+#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
+#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
+#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
+#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0x80
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 949 /* Korean */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x41
+#define _DS1E 0x5A
+#define _DS2S 0x61
+#define _DS2E 0x7A
+#define _DS3S 0x81
+#define _DS3E 0xFE
+
+#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0xA1
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 437 /* U.S. (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720 /* Arabic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737 /* Greek (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775 /* Baltic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857 /* Turkish (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866 /* Russian (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+ 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S 0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
+#define IsLower(c) (((c)>='a')&&((c)<='z'))
+#define IsDigit(c) (((c)>='0')&&((c)<='9'))
+
+#if _DF1S /* Code page is DBCS */
+
+#ifdef _DF2S /* Two 1st byte areas */
+#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else /* One 1st byte area */
+#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S /* Three 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else /* Two 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else /* Code page is SBCS */
+
+#define IsDBCS1(c) 0
+#define IsDBCS2(c) 0
+
+#endif /* _DF1S */
+
+
+/* Name status flags */
+#define NS 11 /* Index of name status byte in fn[] */
+#define NS_LOSS 0x01 /* Out of 8.3 format */
+#define NS_LFN 0x02 /* Force to create LFN entry */
+#define NS_LAST 0x04 /* Last segment */
+#define NS_BODY 0x08 /* Lower case flag (body) */
+#define NS_EXT 0x10 /* Lower case flag (ext) */
+#define NS_DOT 0x20 /* Dot entry */
+
+
+/* FAT sub-type boundaries */
+/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
+#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
+#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
+
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure member because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot 0 /* Jump instruction (3) */
+#define BS_OEMName 3 /* OEM name (8) */
+#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */
+#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */
+#define BPB_NumFATs 16 /* Number of FAT copies (1) */
+#define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */
+#define BPB_TotSec16 19 /* Volume size [sector] (2) */
+#define BPB_Media 21 /* Media descriptor (1) */
+#define BPB_FATSz16 22 /* FAT size [sector] (2) */
+#define BPB_SecPerTrk 24 /* Track size [sector] (2) */
+#define BPB_NumHeads 26 /* Number of heads (2) */
+#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */
+#define BPB_TotSec32 32 /* Volume size [sector] (4) */
+#define BS_DrvNum 36 /* Physical drive number (2) */
+#define BS_BootSig 38 /* Extended boot signature (1) */
+#define BS_VolID 39 /* Volume serial number (4) */
+#define BS_VolLab 43 /* Volume label (8) */
+#define BS_FilSysType 54 /* File system type (1) */
+#define BPB_FATSz32 36 /* FAT size [sector] (4) */
+#define BPB_ExtFlags 40 /* Extended flags (2) */
+#define BPB_FSVer 42 /* File system version (2) */
+#define BPB_RootClus 44 /* Root dir first cluster (4) */
+#define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */
+#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */
+#define BS_DrvNum32 64 /* Physical drive number (2) */
+#define BS_BootSig32 66 /* Extended boot signature (1) */
+#define BS_VolID32 67 /* Volume serial number (4) */
+#define BS_VolLab32 71 /* Volume label (8) */
+#define BS_FilSysType32 82 /* File system type (1) */
+#define FSI_LeadSig 0 /* FSI: Leading signature (4) */
+#define FSI_StrucSig 484 /* FSI: Structure signature (4) */
+#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */
+#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */
+#define MBR_Table 446 /* MBR: Partition table offset (2) */
+#define SZ_PTE 16 /* MBR: Size of a partition table entry */
+#define BS_55AA 510 /* Boot sector signature (2) */
+
+#define DIR_Name 0 /* Short file name (11) */
+#define DIR_Attr 11 /* Attribute (1) */
+#define DIR_NTres 12 /* NT flag (1) */
+#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */
+#define DIR_CrtTime 14 /* Created time (2) */
+#define DIR_CrtDate 16 /* Created date (2) */
+#define DIR_LstAccDate 18 /* Last accessed date (2) */
+#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */
+#define DIR_WrtTime 22 /* Modified time (2) */
+#define DIR_WrtDate 24 /* Modified date (2) */
+#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */
+#define DIR_FileSize 28 /* File size (4) */
+#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */
+#define LDIR_Attr 11 /* LFN attribute (1) */
+#define LDIR_Type 12 /* LFN type (1) */
+#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */
+#define LDIR_FstClusLO 26 /* Filled by zero (0) */
+#define SZ_DIR 32 /* Size of a directory entry */
+#define LLE 0x40 /* Last long entry flag in LDIR_Ord */
+#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */
+#define NDDE 0x05 /* Replacement of the character collides with DDE */
+
+
+/*------------------------------------------------------------*/
+/* Module private work area */
+/*------------------------------------------------------------*/
+/* Note that uninitialized variables with static duration are
+/ zeroed/nulled at start-up. If not, the compiler or start-up
+/ routine is out of ANSI-C standard.
+*/
+
+#if _VOLUMES
+static
+FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
+#else
+#error Number of volumes must not be 0.
+#endif
+
+static
+WORD Fsid; /* File system mount ID */
+
+#if _FS_RPATH
+static
+BYTE CurrVol; /* Current drive */
+#endif
+
+#if _FS_LOCK
+static
+FILESEM Files[_FS_LOCK]; /* File lock semaphores */
+#endif
+
+#if _USE_LFN == 0 /* No LFN feature */
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) (dobj).fn = sfn
+#define FREE_BUF()
+
+#elif _USE_LFN == 1 /* LFN feature with static working buffer */
+static WCHAR LfnBuf[_MAX_LFN+1];
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
+ if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
+ (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define FREE_BUF() ff_memfree(lfn)
+
+#else
+#error Wrong LFN configuration.
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+ const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int); s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+#endif
+ while (cnt--)
+ *d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+
+ while (cnt--)
+ *d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {
+ const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+ int r = 0;
+
+ while (cnt-- && (r = *d++ - *s++) == 0) ;
+ return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {
+ while (*str && *str != chr) str++;
+ return *str;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+
+static
+int lock_fs (
+ FATFS *fs /* File system object */
+)
+{
+ return ff_req_grant(fs->sobj);
+}
+
+
+static
+void unlock_fs (
+ FATFS *fs, /* File system object */
+ FRESULT res /* Result code to be returned */
+)
+{
+ if (fs &&
+ res != FR_NOT_ENABLED &&
+ res != FR_INVALID_DRIVE &&
+ res != FR_INVALID_OBJECT &&
+ res != FR_TIMEOUT) {
+ ff_rel_grant(fs->sobj);
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* File lock control functions */
+/*-----------------------------------------------------------------------*/
+#if _FS_LOCK
+
+static
+FRESULT chk_lock ( /* Check if the file can be accessed */
+ DIR* dj, /* Directory object pointing the file to be checked */
+ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+ UINT i, be;
+
+ /* Search file semaphore table */
+ for (i = be = 0; i < _FS_LOCK; i++) {
+ if (Files[i].fs) { /* Existing entry */
+ if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ } else { /* Blank entry */
+ be++;
+ }
+ }
+ if (i == _FS_LOCK) /* The file is not opened */
+ return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */
+
+ /* The file has been opened. Reject any open against writing file and all write mode open */
+ return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void) /* Check if an entry is available for a new file */
+{
+ UINT i;
+
+ for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
+ DIR* dj, /* Directory object pointing the file to register or increment */
+ int acc /* Desired access mode (0:Read, !0:Write) */
+)
+{
+ UINT i;
+
+
+ for (i = 0; i < _FS_LOCK; i++) { /* Find the file */
+ if (Files[i].fs == dj->fs &&
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ }
+
+ if (i == _FS_LOCK) { /* Not opened. Register it as new. */
+ for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ if (i == _FS_LOCK) return 0; /* No space to register (int err) */
+ Files[i].fs = dj->fs;
+ Files[i].clu = dj->sclust;
+ Files[i].idx = dj->index;
+ Files[i].ctr = 0;
+ }
+
+ if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
+
+ Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
+
+ return i + 1;
+}
+
+
+static
+FRESULT dec_lock ( /* Decrement file open counter */
+ UINT i /* Semaphore index */
+)
+{
+ WORD n;
+ FRESULT res;
+
+
+ if (--i < _FS_LOCK) {
+ n = Files[i].ctr;
+ if (n == 0x100) n = 0;
+ if (n) n--;
+ Files[i].ctr = n;
+ if (!n) Files[i].fs = 0;
+ res = FR_OK;
+ } else {
+ res = FR_INT_ERR;
+ }
+ return res;
+}
+
+
+static
+void clear_lock ( /* Clear lock entries of the volume */
+ FATFS *fs
+)
+{
+ UINT i;
+
+ for (i = 0; i < _FS_LOCK; i++) {
+ if (Files[i].fs == fs) Files[i].fs = 0;
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change window offset */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT move_window (
+ FATFS *fs, /* File system object */
+ DWORD sector /* Sector number to make appearance in the fs->win[] */
+) /* Move to zero only writes back dirty window */
+{
+ DWORD wsect;
+
+
+ wsect = fs->winsect;
+ if (wsect != sector) { /* Changed current window */
+#if !_FS_READONLY
+ if (fs->wflag) { /* Write back dirty window if needed */
+ if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->wflag = 0;
+ if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */
+ BYTE nf;
+ for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */
+ wsect += fs->fsize;
+ disk_write(fs->drv, fs->win, wsect, 1);
+ }
+ }
+ }
+#endif
+ if (sector) {
+ if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->winsect = sector;
+ }
+ }
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Clean-up cached data */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */
+ FATFS *fs /* File system object */
+)
+{
+ FRESULT res;
+
+
+ res = move_window(fs, 0);
+ if (res == FR_OK) {
+ /* Update FSInfo sector if needed */
+ if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
+ fs->winsect = 0;
+ /* Create FSInfo structure */
+ mem_set(fs->win, 0, 512);
+ ST_WORD(fs->win+BS_55AA, 0xAA55);
+ ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
+ ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
+ ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
+ ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
+ /* Write it into the FSInfo sector */
+ disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
+ fs->fsi_flag = 0;
+ }
+ /* Make sure that no pending write process in the physical drive */
+ if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
+ res = FR_DISK_ERR;
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster# */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to be converted */
+)
+{
+ clst -= 2;
+ if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
+ return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to get the link information */
+)
+{
+ UINT wc, bc;
+ BYTE *p;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) /* Check range */
+ return 1;
+
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc = fs->win[bc % SS(fs)]; bc++;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc |= fs->win[bc % SS(fs)] << 8;
+ return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+
+ case FS_FAT16 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ return LD_WORD(p);
+
+ case FS_FAT32 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ return LD_DWORD(p) & 0x0FFFFFFF;
+ }
+
+ return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+
+FRESULT put_fat (
+ FATFS *fs, /* File system object */
+ DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
+ DWORD val /* New value to mark the cluster */
+)
+{
+ UINT bc;
+ BYTE *p;
+ FRESULT res;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ bc++;
+ fs->wflag = 1;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ break;
+
+ case FS_FAT16 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ ST_WORD(p, (WORD)val);
+ break;
+
+ case FS_FAT32 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ val |= LD_DWORD(p) & 0xF0000000;
+ ST_DWORD(p, val);
+ break;
+
+ default :
+ res = FR_INT_ERR;
+ }
+ fs->wflag = 1;
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to remove a chain from */
+)
+{
+ FRESULT res;
+ DWORD nxt;
+#if _USE_ERASE
+ DWORD scl = clst, ecl = clst, rt[2];
+#endif
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ res = FR_OK;
+ while (clst < fs->n_fatent) { /* Not a last link? */
+ nxt = get_fat(fs, clst); /* Get cluster status */
+ if (nxt == 0) break; /* Empty cluster? */
+ if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */
+ if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */
+ res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */
+ if (res != FR_OK) break;
+ if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
+ fs->free_clust++;
+ fs->fsi_flag = 1;
+ }
+#if _USE_ERASE
+ if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
+ ecl = nxt;
+ } else { /* End of contiguous clusters */
+ rt[0] = clust2sect(fs, scl); /* Start sector */
+ rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
+ disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */
+ scl = ecl = nxt;
+ }
+#endif
+ clst = nxt; /* Next cluster */
+ }
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to stretch. 0 means create a new chain. */
+)
+{
+ DWORD cs, ncl, scl;
+ FRESULT res;
+
+
+ if (clst == 0) { /* Create a new chain */
+ scl = fs->last_clust; /* Get suggested start point */
+ if (!scl || scl >= fs->n_fatent) scl = 1;
+ }
+ else { /* Stretch the current chain */
+ cs = get_fat(fs, clst); /* Check the cluster status */
+ if (cs < 2) return 1; /* It is an invalid cluster */
+ if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
+ scl = clst;
+ }
+
+ ncl = scl; /* Start cluster */
+ for (;;) {
+ ncl++; /* Next cluster */
+ if (ncl >= fs->n_fatent) { /* Wrap around */
+ ncl = 2;
+ if (ncl > scl) return 0; /* No free cluster */
+ }
+ cs = get_fat(fs, ncl); /* Get the cluster status */
+ if (cs == 0) break; /* Found a free cluster */
+ if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+ return cs;
+ if (ncl == scl) return 0; /* No free cluster */
+ }
+
+ res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
+ if (res == FR_OK && clst != 0) {
+ res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */
+ }
+ if (res == FR_OK) {
+ fs->last_clust = ncl; /* Update FSINFO */
+ if (fs->free_clust != 0xFFFFFFFF) {
+ fs->free_clust--;
+ fs->fsi_flag = 1;
+ }
+ } else {
+ ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+ }
+
+ return ncl; /* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
+ FIL* fp, /* Pointer to the file object */
+ DWORD ofs /* File offset to be converted to cluster# */
+)
+{
+ DWORD cl, ncl, *tbl;
+
+
+ tbl = fp->cltbl + 1; /* Top of CLMT */
+ cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */
+ for (;;) {
+ ncl = *tbl++; /* Number of cluters in the fragment */
+ if (!ncl) return 0; /* End of table? (error) */
+ if (cl < ncl) break; /* In this fragment? */
+ cl -= ncl; tbl++; /* Next fragment */
+ }
+ return cl + *tbl; /* Return the cluster number */
+}
+#endif /* _USE_FASTSEEK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (
+ FATFS_DIR *dj, /* Pointer to directory object */
+ WORD idx /* Index of directory table */
+)
+{
+ DWORD clst;
+ WORD ic;
+
+
+ dj->index = idx;
+ clst = dj->sclust;
+ if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */
+ return FR_INT_ERR;
+ if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */
+ clst = dj->fs->dirbase;
+
+ if (clst == 0) { /* Static table (root-dir in FAT12/16) */
+ dj->clust = clst;
+ if (idx >= dj->fs->n_rootdir) /* Index is out of range */
+ return FR_INT_ERR;
+ dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+ else { /* Dynamic table (sub-dirs or root-dir in FAT32) */
+ ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */
+ while (idx >= ic) { /* Follow cluster chain */
+ clst = get_fat(dj->fs, clst); /* Get next cluster */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */
+ return FR_INT_ERR;
+ idx -= ic;
+ }
+ dj->clust = clst;
+ dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+
+ dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */
+
+ return FR_OK; /* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
+ FATFS_DIR *dj, /* Pointer to directory object */
+ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+ DWORD clst;
+ WORD i;
+
+
+ stretch = stretch; /* To suppress warning on read-only cfg. */
+ i = dj->index + 1;
+ if (!i || !dj->sect) /* Report EOT when index has reached 65535 */
+ return FR_NO_FILE;
+
+ if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */
+ dj->sect++; /* Next sector */
+
+ if (dj->clust == 0) { /* Static table */
+ if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
+ return FR_NO_FILE;
+ }
+ else { /* Dynamic table */
+ if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
+ clst = get_fat(dj->fs, dj->clust); /* Get next cluster */
+ if (clst <= 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */
+#if !_FS_READONLY
+ BYTE c;
+ if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */
+ clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */
+ if (clst == 0) return FR_DENIED; /* No free cluster */
+ if (clst == 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ /* Clean-up stretched table */
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
+ mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */
+ dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
+ for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */
+ dj->fs->wflag = 1;
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR;
+ dj->fs->winsect++;
+ }
+ dj->fs->winsect -= c; /* Rewind window address */
+#else
+ return FR_NO_FILE; /* Report EOT */
+#endif
+ }
+ dj->clust = clst; /* Initialize data for new cluster */
+ dj->sect = clust2sect(dj->fs, clst);
+ }
+ }
+ }
+
+ dj->index = i;
+ dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Load/Store start cluster number */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (
+ FATFS *fs, /* Pointer to the fs object */
+ BYTE *dir /* Pointer to the directory entry */
+)
+{
+ DWORD cl;
+
+ cl = LD_WORD(dir+DIR_FstClusLO);
+ if (fs->fs_type == FS_FAT32)
+ cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16;
+
+ return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+ BYTE *dir, /* Pointer to the directory entry */
+ DWORD cl /* Value to be set */
+)
+{
+ ST_WORD(dir+DIR_FstClusLO, cl);
+ ST_WORD(dir+DIR_FstClusHI, cl >> 16);
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */
+
+
+static
+int cmp_lfn ( /* 1:Matched, 0:Not matched */
+ WCHAR *lfnbuf, /* Pointer to the LFN to be compared */
+ BYTE *dir /* Pointer to the directory entry containing a part of LFN */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ wc = ff_wtoupper(uc); /* Convert it to upper case */
+ if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */
+ return 0; /* Not matched */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Repeat until all chars in the entry are checked */
+
+ if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */
+ return 0;
+
+ return 1; /* The part of LFN matched */
+}
+
+
+
+static
+int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */
+ WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */
+ BYTE *dir /* Pointer to the directory entry */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
+
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i++] = wc = uc; /* Store it */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Read all character in the entry */
+
+ if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i] = 0;
+ }
+
+ return 1;
+}
+
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+ const WCHAR *lfnbuf, /* Pointer to the LFN buffer */
+ BYTE *dir, /* Pointer to the directory entry */
+ BYTE ord, /* LFN order (1-20) */
+ BYTE sum /* SFN sum */
+)
+{
+ UINT i, s;
+ WCHAR wc;
+
+
+ dir[LDIR_Chksum] = sum; /* Set check sum */
+ dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
+ dir[LDIR_Type] = 0;
+ ST_WORD(dir+LDIR_FstClusLO, 0);
+
+ i = (ord - 1) * 13; /* Get offset in the LFN buffer */
+ s = wc = 0;
+ do {
+ if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
+ ST_WORD(dir+LfnOfs[s], wc); /* Put it */
+ if (!wc) wc = 0xFFFF; /* Padding chars following last char */
+ } while (++s < 13);
+ if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */
+ dir[LDIR_Ord] = ord; /* Set the LFN order */
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+void gen_numname (
+ BYTE *dst, /* Pointer to generated SFN */
+ const BYTE *src, /* Pointer to source SFN to be modified */
+ const WCHAR *lfn, /* Pointer to LFN */
+ WORD seq /* Sequence number */
+)
+{
+ BYTE ns[8], c;
+ UINT i, j;
+
+
+ mem_cpy(dst, src, 11);
+
+ if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */
+ do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
+ }
+
+ /* itoa (hexdecimal) */
+ i = 7;
+ do {
+ c = (seq % 16) + '0';
+ if (c > '9') c += 7;
+ ns[i--] = c;
+ seq /= 16;
+ } while (seq);
+ ns[i] = '~';
+
+ /* Append the number */
+ for (j = 0; j < i && dst[j] != ' '; j++) {
+ if (IsDBCS1(dst[j])) {
+ if (j == i - 1) break;
+ j++;
+ }
+ }
+ do {
+ dst[j++] = (i < 8) ? ns[i++] : ' ';
+ } while (j < 8);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Calculate sum of an SFN */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+ const BYTE *dir /* Ptr to directory entry */
+)
+{
+ BYTE sum = 0;
+ UINT n = 11;
+
+ do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
+ return sum;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+ FATFS_DIR *dj /* Pointer to the directory object linked to the file name */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord, sum;
+#endif
+
+ res = dir_sdi(dj, 0); /* Rewind directory object */
+ if (res != FR_OK) return res;
+
+#if _USE_LFN
+ ord = sum = 0xFF;
+#endif
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (dj->lfn) {
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c; /* LFN start order */
+ dj->lfn_idx = dj->index;
+ }
+ /* Check validity of the LFN entry and compare it with given name */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ }
+ } else { /* An SFN entry is found */
+ if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
+ ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */
+ if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */
+ }
+ }
+#else /* Non LFN configuration */
+ if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+FRESULT dir_read (
+ FATFS_DIR *dj /* Pointer to the directory object that pointing the entry to be read */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord = 0xFF, sum = 0xFF;
+#endif
+
+ res = FR_NO_FILE;
+ while (dj->sect) {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c;
+ dj->lfn_idx = dj->index;
+ }
+ /* Check LFN validity and capture it */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ } else { /* An SFN entry is found */
+ if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
+ dj->lfn_idx = 0xFFFF; /* It has no LFN. */
+ break;
+ }
+ }
+#else /* Non LFN configuration */
+ if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ if (res != FR_OK) break;
+ }
+
+ if (res != FR_OK) dj->sect = 0;
+
+ return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
+ FATFS_DIR *dj /* Target directory with object name to be created */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN /* LFN configuration */
+ WORD n, ne, is;
+ BYTE sn[12], *fn, sum;
+ WCHAR *lfn;
+
+
+ fn = dj->fn; lfn = dj->lfn;
+ mem_cpy(sn, fn, 12);
+
+ if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
+ return FR_INVALID_NAME;
+
+ if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
+ fn[NS] = 0; dj->lfn = 0; /* Find only SFN */
+ for (n = 1; n < 100; n++) {
+ gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
+ res = dir_find(dj); /* Check if the name collides with existing SFN */
+ if (res != FR_OK) break;
+ }
+ if (n == 100) return FR_DENIED; /* Abort if too many collisions */
+ if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
+ fn[NS] = sn[NS]; dj->lfn = lfn;
+ }
+
+ if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */
+ for (ne = 0; lfn[ne]; ne++) ;
+ ne = (ne + 25) / 13;
+ } else { /* Otherwise reserve only an SFN entry. */
+ ne = 1;
+ }
+
+ /* Reserve contiguous entries */
+ res = dir_sdi(dj, 0);
+ if (res != FR_OK) return res;
+ n = is = 0;
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir; /* Check the entry status */
+ if (c == DDE || c == 0) { /* Is it a blank entry? */
+ if (n == 0) is = dj->index; /* First index of the contiguous entry */
+ if (++n == ne) break; /* A contiguous entry that required count is found */
+ } else {
+ n = 0; /* Not a blank entry. Restart to search */
+ }
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+
+ if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */
+ res = dir_sdi(dj, is);
+ if (res == FR_OK) {
+ sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */
+ ne--;
+ do { /* Store LFN entries in bottom first */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
+ dj->fs->wflag = 1;
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK && --ne);
+ }
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, 0);
+ if (res == FR_OK) {
+ do { /* Find a blank entry for the SFN */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir;
+ if (c == DDE || c == 0) break; /* Is it a blank entry? */
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+ }
+#endif
+
+ if (res == FR_OK) { /* Initialize the SFN entry */
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ dir = dj->dir;
+ mem_set(dir, 0, SZ_DIR); /* Clean the entry */
+ mem_cpy(dir, dj->fn, 11); /* Put SFN */
+#if _USE_LFN
+ dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
+#endif
+ dj->fs->wflag = 1;
+ }
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */
+ FATFS_DIR *dj /* Directory object pointing the entry to be removed */
+)
+{
+ FRESULT res;
+#if _USE_LFN /* LFN configuration */
+ WORD i;
+
+ i = dj->index; /* SFN index */
+ res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */
+ if (res == FR_OK) {
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, dj->index);
+ if (res == FR_OK) {
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ }
+ }
+#endif
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (
+ FATFS_DIR *dj, /* Pointer to the directory object */
+ const TCHAR **path /* Pointer to pointer to the segment in the path string */
+)
+{
+#ifdef _EXCVT
+ static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
+#endif
+
+#if _USE_LFN /* LFN configuration */
+ BYTE b, cf;
+ WCHAR w, *lfn;
+ UINT i, ni, si, di;
+ const TCHAR *p;
+
+ /* Create LFN in Unicode */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ lfn = dj->lfn;
+ si = di = 0;
+ for (;;) {
+ w = p[si++]; /* Get a character */
+ if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */
+ if (di >= _MAX_LFN) /* Reject too long name */
+ return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+ w &= 0xFF;
+ if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ b = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(b))
+ return FR_INVALID_NAME; /* Reject invalid sequence */
+ w = (w << 8) + b; /* Create a DBC */
+ }
+ w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
+ if (!w) return FR_INVALID_NAME; /* Reject invalid code */
+#endif
+ if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
+ return FR_INVALID_NAME;
+ lfn[di++] = w; /* Store the Unicode char */
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+#if _FS_RPATH
+ if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
+ (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
+ lfn[di] = 0;
+ for (i = 0; i < 11; i++)
+ dj->fn[i] = (i < di) ? '.' : ' ';
+ dj->fn[i] = cf | NS_DOT; /* This is a dot entry */
+ return FR_OK;
+ }
+#endif
+ while (di) { /* Strip trailing spaces and dots */
+ w = lfn[di-1];
+ if (w != ' ' && w != '.') break;
+ di--;
+ }
+ if (!di) return FR_INVALID_NAME; /* Reject nul string */
+
+ lfn[di] = 0; /* LFN is created */
+
+ /* Create SFN in directory form */
+ mem_set(dj->fn, ' ', 11);
+ for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
+ if (si) cf |= NS_LOSS | NS_LFN;
+ while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
+
+ b = i = 0; ni = 8;
+ for (;;) {
+ w = lfn[si++]; /* Get an LFN char */
+ if (!w) break; /* Break on end of the LFN */
+ if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
+ cf |= NS_LOSS | NS_LFN; continue;
+ }
+
+ if (i >= ni || si == di) { /* Extension or end of SFN */
+ if (ni == 11) { /* Long extension */
+ cf |= NS_LOSS | NS_LFN; break;
+ }
+ if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
+ if (si > di) break; /* No extension */
+ si = di; i = 8; ni = 11; /* Enter extension section */
+ b <<= 2; continue;
+ }
+
+ if (w >= 0x80) { /* Non ASCII char */
+#ifdef _EXCVT
+ w = ff_convert(w, 0); /* Unicode -> OEM code */
+ if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
+#else
+ w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
+#endif
+ cf |= NS_LFN; /* Force create LFN entry */
+ }
+
+ if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */
+ if (i >= ni - 1) {
+ cf |= NS_LOSS | NS_LFN; i = ni; continue;
+ }
+ dj->fn[i++] = (BYTE)(w >> 8);
+ } else { /* Single byte char */
+ if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */
+ w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+ } else {
+ if (IsUpper(w)) { /* ASCII large capital */
+ b |= 2;
+ } else {
+ if (IsLower(w)) { /* ASCII small capital */
+ b |= 1; w -= 0x20;
+ }
+ }
+ }
+ }
+ dj->fn[i++] = (BYTE)w;
+ }
+
+ if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */
+ cf |= NS_LFN;
+ if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */
+ if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
+ if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
+ }
+
+ dj->fn[NS] = cf; /* SFN is created */
+
+ return FR_OK;
+
+
+#else /* Non-LFN configuration */
+ BYTE b, c, d, *sfn;
+ UINT ni, si, i;
+ const char *p;
+
+ /* Create file name in directory form */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ sfn = dj->fn;
+ mem_set(sfn, ' ', 11);
+ si = i = b = 0; ni = 8;
+#if _FS_RPATH
+ if (p[si] == '.') { /* Is this a dot entry? */
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c != '.' || si >= 3) break;
+ sfn[i++] = c;
+ }
+ if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+ *path = &p[si]; /* Return pointer to the next segment */
+ sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
+ return FR_OK;
+ }
+#endif
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */
+ if (c == '.' || i >= ni) {
+ if (ni != 8 || c != '.') return FR_INVALID_NAME;
+ i = 8; ni = 11;
+ b <<= 2; continue;
+ }
+ if (c >= 0x80) { /* Extended char? */
+ b |= 3; /* Eliminate NT flag */
+#ifdef _EXCVT
+ c = excvt[c - 0x80]; /* Upper conversion (SBCS) */
+#else
+#if !_DF1S /* ASCII only cfg */
+ return FR_INVALID_NAME;
+#endif
+#endif
+ }
+ if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ d = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
+ return FR_INVALID_NAME;
+ sfn[i++] = c;
+ sfn[i++] = d;
+ } else { /* Single byte code */
+ if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */
+ return FR_INVALID_NAME;
+ if (IsUpper(c)) { /* ASCII large capital? */
+ b |= 2;
+ } else {
+ if (IsLower(c)) { /* ASCII small capital? */
+ b |= 1; c -= 0x20;
+ }
+ }
+ sfn[i++] = c;
+ }
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+
+ if (!i) return FR_INVALID_NAME; /* Reject nul string */
+ if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
+ if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
+
+ sfn[NS] = c; /* Store NT flag, File name is created */
+
+ return FR_OK;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+void get_fileinfo ( /* No return code */
+ FATFS_DIR *dj, /* Pointer to the directory object */
+ FILINFO *fno /* Pointer to the file information to be filled */
+)
+{
+ UINT i;
+ BYTE nt, *dir;
+ TCHAR *p, c;
+
+
+ p = fno->fname;
+ if (dj->sect) {
+ dir = dj->dir;
+ nt = dir[DIR_NTres]; /* NT flag */
+ for (i = 0; i < 8; i++) { /* Copy name body */
+ c = dir[i];
+ if (c == ' ') break;
+ if (c == NDDE) c = (TCHAR)DDE;
+ if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ if (dir[8] != ' ') { /* Copy name extension */
+ *p++ = '.';
+ for (i = 8; i < 11; i++) {
+ c = dir[i];
+ if (c == ' ') break;
+ if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ }
+ fno->fattrib = dir[DIR_Attr]; /* Attribute */
+ fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */
+ fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */
+ fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */
+ }
+ *p = 0; /* Terminate SFN str by a \0 */
+
+#if _USE_LFN
+ if (fno->lfname && fno->lfsize) {
+ TCHAR *tp = fno->lfname;
+ WCHAR w, *lfn;
+
+ i = 0;
+ if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
+ lfn = dj->lfn;
+ while ((w = *lfn++) != 0) { /* Get an LFN char */
+#if !_LFN_UNICODE
+ w = ff_convert(w, 0); /* Unicode -> OEM conversion */
+ if (!w) { i = 0; break; } /* Could not convert, no LFN */
+ if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+ tp[i++] = (TCHAR)(w >> 8);
+#endif
+ if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */
+ tp[i++] = (TCHAR)w;
+ }
+ }
+ tp[i] = 0; /* Terminate the LFN str by a \0 */
+ }
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
+ FATFS_DIR *dj, /* Directory object to return last directory and found object */
+ const TCHAR *path /* Full-path string to find a file or directory */
+)
+{
+ FRESULT res;
+ BYTE *dir, ns;
+
+
+#if _FS_RPATH
+ if (*path == '/' || *path == '\\') { /* There is a heading separator */
+ path++; dj->sclust = 0; /* Strip it and start from the root dir */
+ } else { /* No heading separator */
+ dj->sclust = dj->fs->cdir; /* Start from the current dir */
+ }
+#else
+ if (*path == '/' || *path == '\\') /* Strip heading separator if exist */
+ path++;
+ dj->sclust = 0; /* Start from the root dir */
+#endif
+
+ if ((UINT)*path < ' ') { /* Nul path means the start directory itself */
+ res = dir_sdi(dj, 0);
+ dj->dir = 0;
+ } else { /* Follow path */
+ for (;;) {
+ res = create_name(dj, &path); /* Get a segment */
+ if (res != FR_OK) break;
+ res = dir_find(dj); /* Find it */
+ ns = *(dj->fn+NS);
+ if (res != FR_OK) { /* Failed to find the object */
+ if (res != FR_NO_FILE) break; /* Abort if any hard error occurred */
+ /* Object not found */
+ if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */
+ dj->sclust = 0; dj->dir = 0; /* It is the root dir */
+ res = FR_OK;
+ if (!(ns & NS_LAST)) continue;
+ } else { /* Could not find the object */
+ if (!(ns & NS_LAST)) res = FR_NO_PATH;
+ }
+ break;
+ }
+ if (ns & NS_LAST) break; /* Last segment match. Function completed. */
+ dir = dj->dir; /* There is next segment. Follow the sub directory */
+ if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+ res = FR_NO_PATH; break;
+ }
+ dj->sclust = ld_clust(dj->fs, dir);
+ }
+ }
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT Volume Boot Record */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs ( /* 0:FAT-VBR, 1:Any BR but not FAT, 2:Not a BR, 3:Disk error */
+ FATFS *fs, /* File system object */
+ DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+ if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */
+ return 3;
+ if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */
+ return 2;
+
+ if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
+ return 0;
+ if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
+ return 0;
+
+ return 1;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file system object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
+ const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
+ FATFS **rfs, /* Pointer to pointer to the found file system object */
+ BYTE wmode /* !=0: Check write protection for write access */
+)
+{
+ BYTE fmt, b, pi, *tbl;
+ UINT vol;
+ DSTATUS stat;
+ DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
+ WORD nrsv;
+ const TCHAR *p = *path;
+ FATFS *fs;
+
+
+ /* Get logical drive number from the path name */
+ vol = p[0] - '0'; /* Is there a drive number? */
+ if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */
+ p += 2; *path = p; /* Return pointer to the path name */
+ } else { /* No drive number is given */
+#if _FS_RPATH
+ vol = CurrVol; /* Use current drive */
+#else
+ vol = 0; /* Use drive 0 */
+#endif
+ }
+
+ /* Check if the file system object is valid or not */
+ *rfs = 0;
+ if (vol >= _VOLUMES) /* Is the drive number valid? */
+ return FR_INVALID_DRIVE;
+ fs = FatFs[vol]; /* Get corresponding file system object */
+ if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
+
+ ENTER_FF(fs); /* Lock file system */
+
+ *rfs = fs; /* Return pointer to the corresponding file system object */
+ if (fs->fs_type) { /* If the volume has been mounted */
+ stat = disk_status(fs->drv);
+ if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */
+ if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */
+ return FR_WRITE_PROTECTED;
+ return FR_OK; /* The file system object is valid */
+ }
+ }
+
+ /* The file system object is not valid. */
+ /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+ fs->fs_type = 0; /* Clear the file system object */
+ fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */
+ stat = disk_initialize(fs->drv); /* Initialize the physical drive */
+ if (stat & STA_NOINIT) /* Check if the initialization succeeded */
+ return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */
+ if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */
+ return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */
+ if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
+ return FR_DISK_ERR;
+#endif
+ /* Search FAT partition on the drive. Supports only generic partitions, FDISK and SFD. */
+ fmt = check_fs(fs, bsect = 0); /* Load sector 0 and check if it is an FAT-VBR (in SFD) */
+ if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */
+ if (fmt == 1) { /* Not an FAT-VBR, the physical drive can be partitioned */
+ /* Check the partition listed in the partition table */
+ pi = LD2PT(vol);
+ if (pi) pi--;
+ tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */
+ if (tbl[4]) { /* Is the partition existing? */
+ bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */
+ fmt = check_fs(fs, bsect); /* Check the partition */
+ }
+ }
+ if (fmt == 3) return FR_DISK_ERR;
+ if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */
+
+ /* An FAT volume is found. Following code initializes the file system object */
+
+ if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */
+ return FR_NO_FILESYSTEM;
+
+ fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */
+ if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
+ fs->fsize = fasize;
+
+ fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */
+ if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
+ fasize *= b; /* Number of sectors for FAT area */
+
+ fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */
+ if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
+
+ fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */
+ if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
+
+ tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */
+ if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
+
+ nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */
+ if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */
+
+ /* Determine the FAT sub type */
+ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */
+ if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
+ if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ fmt = FS_FAT12;
+ if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+ if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Boundaries and Limits */
+ fs->n_fatent = nclst + 2; /* Number of FAT entries */
+ fs->database = bsect + sysect; /* Data start sector */
+ fs->fatbase = bsect + nrsv; /* FAT start sector */
+ if (fmt == FS_FAT32) {
+ if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
+ fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */
+ szbfat = fs->n_fatent * 4; /* (Required FAT size) */
+ } else {
+ if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
+ fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
+ szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */
+ fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+ }
+ if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */
+ return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+ /* Initialize cluster allocation information */
+ fs->free_clust = 0xFFFFFFFF;
+ fs->last_clust = 0;
+
+ /* Get fsinfo if available */
+ if (fmt == FS_FAT32) {
+ fs->fsi_flag = 0;
+ fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
+ if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
+ LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
+ LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
+ LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
+ fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
+ fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
+ }
+ }
+#endif
+ fs->fs_type = fmt; /* FAT sub-type */
+ fs->id = ++Fsid; /* File system mount ID */
+ fs->winsect = 0; /* Invalidate sector cache */
+ fs->wflag = 0;
+#if _FS_RPATH
+ fs->cdir = 0; /* Current directory (root dir) */
+#endif
+#if _FS_LOCK /* Clear file lock semaphores */
+ clear_lock(fs);
+#endif
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/dir object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */
+ void* obj /* Pointer to the object FIL/DIR to check validity */
+)
+{
+ FIL *fil;
+
+
+ fil = (FIL*)obj; /* Assuming offset of fs and id in the FIL/DIR is identical */
+ if (!fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id)
+ return FR_INVALID_OBJECT;
+
+ ENTER_FF(fil->fs); /* Lock file system */
+
+ if (disk_status(fil->fs->drv) & STA_NOINIT)
+ return FR_NOT_READY;
+
+ return FR_OK;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+ BYTE vol, /* Logical drive number to be mounted/unmounted */
+ FATFS *fs /* Pointer to new file system object (NULL for unmount)*/
+)
+{
+ FATFS *rfs;
+
+
+ if (vol >= _VOLUMES) /* Check if the drive number is valid */
+ return FR_INVALID_DRIVE;
+ rfs = FatFs[vol]; /* Get current fs object */
+
+ if (rfs) {
+#if _FS_LOCK
+ clear_lock(rfs);
+#endif
+#if _FS_REENTRANT /* Discard sync object of the current volume */
+ if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
+#endif
+ rfs->fs_type = 0; /* Clear old fs object */
+ }
+
+ if (fs) {
+ fs->fs_type = 0; /* Clear new fs object */
+#if _FS_REENTRANT /* Create sync object for the new volume */
+ if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+ }
+ FatFs[vol] = fs; /* Register new fs object */
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+ FIL *fp, /* Pointer to the blank file object */
+ const TCHAR *path, /* Pointer to the file name */
+ BYTE mode /* Access mode and file open mode flags */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ if (!fp) return FR_INVALID_OBJECT;
+ fp->fs = 0; /* Clear file object */
+
+#if !_FS_READONLY
+ mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+ res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
+#else
+ mode &= FA_READ;
+ res = chk_mounted(&path, &dj.fs, 0);
+#endif
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ dir = dj.dir;
+#if !_FS_READONLY /* R/W configuration */
+ if (res == FR_OK) {
+ if (!dir) /* Current dir itself */
+ res = FR_INVALID_NAME;
+#if _FS_LOCK
+ else
+ res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+ }
+ /* Create or Open a file */
+ if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+ DWORD dw, cl;
+
+ if (res != FR_OK) { /* No file, create new */
+ if (res == FR_NO_FILE) /* There is no file to open, create a new entry */
+#if _FS_LOCK
+ res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+ res = dir_register(&dj);
+#endif
+ mode |= FA_CREATE_ALWAYS; /* File is created */
+ dir = dj.dir; /* New entry */
+ }
+ else { /* Any object is already existing */
+ if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
+ res = FR_DENIED;
+ } else {
+ if (mode & FA_CREATE_NEW) /* Cannot create as new file */
+ res = FR_EXIST;
+ }
+ }
+ if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
+ dw = get_fattime(); /* Created time */
+ ST_DWORD(dir+DIR_CrtTime, dw);
+ dir[DIR_Attr] = 0; /* Reset attribute */
+ ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
+ cl = ld_clust(dj.fs, dir); /* Get start cluster */
+ st_clust(dir, 0); /* cluster = 0 */
+ dj.fs->wflag = 1;
+ if (cl) { /* Remove the cluster chain if exist */
+ dw = dj.fs->winsect;
+ res = remove_chain(dj.fs, cl);
+ if (res == FR_OK) {
+ dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
+ res = move_window(dj.fs, dw);
+ }
+ }
+ }
+ }
+ else { /* Open an existing file */
+ if (res == FR_OK) { /* Follow succeeded */
+ if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */
+ res = FR_NO_FILE;
+ } else {
+ if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+ res = FR_DENIED;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
+ mode |= FA__WRITTEN;
+ fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */
+ fp->dir_ptr = dir;
+#if _FS_LOCK
+ fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+ if (!fp->lockid) res = FR_INT_ERR;
+#endif
+ }
+
+#else /* R/O configuration */
+ if (res == FR_OK) { /* Follow succeeded */
+ dir = dj.dir;
+ if (!dir) { /* Current dir itself */
+ res = FR_INVALID_NAME;
+ } else {
+ if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
+ res = FR_NO_FILE;
+ }
+ }
+#endif
+ FREE_BUF();
+
+ if (res == FR_OK) {
+ fp->flag = mode; /* File access mode */
+ fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */
+ fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
+ fp->fptr = 0; /* File pointer */
+ fp->dsect = 0;
+#if _USE_FASTSEEK
+ fp->cltbl = 0; /* Normal seek mode */
+#endif
+ fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+ FIL *fp, /* Pointer to the file object */
+ void *buff, /* Pointer to data buffer */
+ UINT btr, /* Number of bytes to read */
+ UINT *br /* Pointer to number of bytes read */
+)
+{
+ FRESULT res;
+ DWORD clst, sect, remain;
+ UINT rcnt, cc;
+ BYTE csect, *rbuff = (BYTE *)buff;
+
+
+ *br = 0; /* Clear read byte counter */
+
+ res = validate(fp); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr; /* Repeat until all data read */
+ rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */
+ }
+ if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Read maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+ if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+ mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
+#else
+ if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+ mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
+#endif
+#endif
+ rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if !_FS_TINY
+ if (fp->dsect != sect) { /* Load data sector if not in cache */
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
+ if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#else
+ mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#endif
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+ FIL *fp, /* Pointer to the file object */
+ const void *buff, /* Pointer to the data to be written */
+ UINT btw, /* Number of bytes to write */
+ UINT *bw /* Pointer to number of bytes written */
+)
+{
+ FRESULT res;
+ DWORD clst, sect;
+ UINT wcnt, cc;
+ const BYTE *wbuff = (const BYTE *)buff;
+ BYTE csect;
+ bool need_sync = false;
+
+ *bw = 0; /* Clear write byte counter */
+
+ res = validate(fp); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */
+
+ for ( ; btw; /* Repeat until all data written */
+ wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ if (clst == 0) /* When no cluster is allocated, */
+ fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */
+ }
+ if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+
+#ifdef FLUSH_ON_NEW_CLUSTER
+ // We do not need to flush for the first cluster
+ if (fp->fptr != 0) {
+ need_sync = true;
+ }
+#endif
+ }
+#if _FS_TINY
+ if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#else
+ if (fp->flag & FA__DIRTY) { /* Write-back sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Write maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_TINY
+ if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->fs->wflag = 0;
+ }
+#else
+ if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+#ifdef FLUSH_ON_NEW_SECTOR
+ need_sync = true;
+#endif
+ continue;
+ }
+#if _FS_TINY
+ if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */
+ if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
+ fp->fs->winsect = sect;
+ }
+#else
+ if (fp->dsect != sect) { /* Fill sector cache with file data */
+ if (fp->fptr < fp->fsize &&
+ disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+ if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->fs->wflag = 1;
+#else
+ mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->flag |= FA__DIRTY;
+#endif
+ }
+
+ if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
+ fp->flag |= FA__WRITTEN; /* Set file change flag */
+
+ if (need_sync) {
+ f_sync (fp);
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD tim;
+ BYTE *dir;
+
+
+ res = validate(fp); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__WRITTEN) { /* Has the file been written? */
+#if !_FS_TINY /* Write-back dirty buffer */
+ if (fp->flag & FA__DIRTY) {
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ LEAVE_FF(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ /* Update the directory entry */
+ res = move_window(fp->fs, fp->dir_sect);
+ if (res == FR_OK) {
+ dir = fp->dir_ptr;
+ dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
+ ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
+ st_clust(dir, fp->sclust); /* Update start cluster */
+ tim = get_fattime(); /* Update updated time */
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ ST_WORD(dir+DIR_LstAccDate, 0);
+ fp->flag &= ~FA__WRITTEN;
+ fp->fs->wflag = 1;
+ res = sync(fp->fs);
+ }
+ }
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+ FIL *fp /* Pointer to the file object to be closed */
+)
+{
+ FRESULT res;
+
+
+#if _FS_READONLY
+ res = validate(fp);
+ {
+#if _FS_REENTRANT
+ FATFS *fs = fp->fs;
+#endif
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ LEAVE_FF(fs, res);
+ }
+#else
+ res = f_sync(fp); /* Flush cached data */
+#if _FS_LOCK
+ if (res == FR_OK) { /* Decrement open counter */
+#if _FS_REENTRANT
+ FATFS *fs = fp->fs;;
+ res = validate(fp);
+ if (res == FR_OK) {
+ res = dec_lock(fp->lockid);
+ unlock_fs(fs, FR_OK);
+ }
+#else
+ res = dec_lock(fp->lockid);
+#endif
+ }
+#endif
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ return res;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Current Drive/Directory Handlings */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+
+FRESULT f_chdrive (
+ BYTE drv /* Drive number */
+)
+{
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+
+ CurrVol = drv;
+
+ return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the path */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (!dj.dir) {
+ dj.fs->cdir = dj.sclust; /* Start directory itself */
+ } else {
+ if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */
+ dj.fs->cdir = ld_clust(dj.fs, dj.dir);
+ else
+ res = FR_NO_PATH; /* Reached but a file */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+ TCHAR *path, /* Pointer to the directory path */
+ UINT sz_path /* Size of path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ UINT i, n;
+ DWORD ccl;
+ TCHAR *tp;
+ FILINFO fno;
+ DEF_NAMEBUF;
+
+
+ *path = 0;
+ res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ i = sz_path; /* Bottom of buffer (dir stack base) */
+ dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */
+ while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */
+ res = dir_sdi(&dj, 1); /* Get parent dir */
+ if (res != FR_OK) break;
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent dir */
+ res = dir_sdi(&dj, 0);
+ if (res != FR_OK) break;
+ do { /* Find the entry links to the child dir */
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */
+ res = dir_next(&dj, 0);
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+ if (res != FR_OK) break;
+#if _USE_LFN
+ fno.lfname = path;
+ fno.lfsize = i;
+#endif
+ get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */
+ tp = fno.fname;
+ if (_USE_LFN && *path) tp = path;
+ for (n = 0; tp[n]; n++) ;
+ if (i < n + 3) {
+ res = FR_NOT_ENOUGH_CORE; break;
+ }
+ while (n) path[--i] = tp[--n];
+ path[--i] = '/';
+ }
+ tp = path;
+ if (res == FR_OK) {
+ *tp++ = '0' + CurrVol; /* Put drive number */
+ *tp++ = ':';
+ if (i == sz_path) { /* Root-dir */
+ *tp++ = '/';
+ } else { /* Sub-dir */
+ do /* Add stacked path str */
+ *tp++ = path[i++];
+ while (i < sz_path);
+ }
+ }
+ *tp = 0;
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+ FIL *fp, /* Pointer to the file object */
+ DWORD ofs /* File pointer from top of file */
+)
+{
+ FRESULT res;
+
+
+ res = validate(fp); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check abort flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+
+#if _USE_FASTSEEK
+ if (fp->cltbl) { /* Fast seek */
+ DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+
+ if (ofs == CREATE_LINKMAP) { /* Create CLMT */
+ tbl = fp->cltbl;
+ tlen = *tbl++; ulen = 2; /* Given table size and required table size */
+ cl = fp->sclust; /* Top of the chain */
+ if (cl) {
+ do {
+ /* Get a fragment */
+ tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */
+ do {
+ pcl = cl; ncl++;
+ cl = get_fat(fp->fs, cl);
+ if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ } while (cl == pcl + 1);
+ if (ulen <= tlen) { /* Store the length and top of the fragment */
+ *tbl++ = ncl; *tbl++ = tcl;
+ }
+ } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */
+ }
+ *fp->cltbl = ulen; /* Number of items used */
+ if (ulen <= tlen)
+ *tbl = 0; /* Terminate table */
+ else
+ res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */
+
+ } else { /* Fast seek */
+ if (ofs > fp->fsize) /* Clip offset at the file size */
+ ofs = fp->fsize;
+ fp->fptr = ofs; /* Set file pointer */
+ if (ofs) {
+ fp->clust = clmt_clust(fp, ofs - 1);
+ dsc = clust2sect(fp->fs, fp->clust);
+ if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+ dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+ if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = dsc;
+ }
+ }
+ }
+ } else
+#endif
+
+ /* Normal Seek */
+ {
+ DWORD clst, bcs, nsect, ifptr;
+
+ if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+ && !(fp->flag & FA_WRITE)
+#endif
+ ) ofs = fp->fsize;
+
+ ifptr = fp->fptr;
+ fp->fptr = nsect = 0;
+ if (ofs) {
+ bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */
+ if (ifptr > 0 &&
+ (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
+ fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */
+ ofs -= fp->fptr;
+ clst = fp->clust;
+ } else { /* When seek to back cluster, */
+ clst = fp->sclust; /* start from the first cluster */
+#if !_FS_READONLY
+ if (clst == 0) { /* If no cluster chain, create a new chain */
+ clst = create_chain(fp->fs, 0);
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->sclust = clst;
+ }
+#endif
+ fp->clust = clst;
+ }
+ if (clst != 0) {
+ while (ofs > bcs) { /* Cluster following loop */
+#if !_FS_READONLY
+ if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
+ clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */
+ if (clst == 0) { /* When disk gets full, clip file size */
+ ofs = bcs; break;
+ }
+ } else
+#endif
+ clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+ fp->clust = clst;
+ fp->fptr += bcs;
+ ofs -= bcs;
+ }
+ fp->fptr += ofs;
+ if (ofs % SS(fp->fs)) {
+ nsect = clust2sect(fp->fs, clst); /* Current sector */
+ if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+ nsect += ofs / SS(fp->fs);
+ }
+ }
+ }
+ if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = nsect;
+ }
+#if !_FS_READONLY
+ if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */
+ fp->fsize = fp->fptr;
+ fp->flag |= FA__WRITTEN;
+ }
+#endif
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+ FATFS_DIR *dj, /* Pointer to directory object to create */
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ FATFS *fs;
+ DEF_NAMEBUF;
+
+
+ if (!dj) return FR_INVALID_OBJECT;
+
+ res = chk_mounted(&path, &dj->fs, 0);
+ fs = dj->fs;
+ if (res == FR_OK) {
+ INIT_BUF(*dj);
+ res = follow_path(dj, path); /* Follow the path to the directory */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (dj->dir) { /* It is not the root dir */
+ if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */
+ dj->sclust = ld_clust(fs, dj->dir);
+ } else { /* The object is not a directory */
+ res = FR_NO_PATH;
+ }
+ }
+ if (res == FR_OK) {
+ dj->id = fs->id;
+ res = dir_sdi(dj, 0); /* Rewind dir */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ if (res != FR_OK) dj->fs = 0; /* Invalidate the dir object if function faild */
+ } else {
+ dj->fs = 0;
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequence */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+ FATFS_DIR *dj, /* Pointer to the open directory object */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ DEF_NAMEBUF;
+
+
+ res = validate(dj); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (!fno) {
+ res = dir_sdi(dj, 0); /* Rewind the directory object */
+ } else {
+ INIT_BUF(*dj);
+ res = dir_read(dj); /* Read an directory item */
+ if (res == FR_NO_FILE) { /* Reached end of dir */
+ dj->sect = 0;
+ res = FR_OK;
+ }
+ if (res == FR_OK) { /* A valid entry is found */
+ get_fileinfo(dj, fno); /* Get the object information */
+ res = dir_next(dj, 0); /* Increment index for next */
+ if (res == FR_NO_FILE) {
+ dj->sect = 0;
+ res = FR_OK;
+ }
+ }
+ FREE_BUF();
+ }
+ }
+
+ LEAVE_FF(dj->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+ const TCHAR *path, /* Pointer to the file path */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) { /* Follow completed */
+ if (dj.dir) /* Found an object */
+ get_fileinfo(&dj, fno);
+ else /* It is root dir */
+ res = FR_INVALID_NAME;
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+ const TCHAR *path, /* Pointer to the logical drive number (root dir) */
+ DWORD *nclst, /* Pointer to the variable to return number of free clusters */
+ FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */
+)
+{
+ FRESULT res;
+ FATFS *fs;
+ DWORD n, clst, sect, stat;
+ UINT i;
+ BYTE fat, *p;
+
+
+ /* Get drive number */
+ res = chk_mounted(&path, fatfs, 0);
+ fs = *fatfs;
+ if (res == FR_OK) {
+ /* If free_clust is valid, return it without full cluster scan */
+ if (fs->free_clust <= fs->n_fatent - 2) {
+ *nclst = fs->free_clust;
+ } else {
+ /* Get number of free clusters */
+ fat = fs->fs_type;
+ n = 0;
+ if (fat == FS_FAT12) {
+ clst = 2;
+ do {
+ stat = get_fat(fs, clst);
+ if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ if (stat == 1) { res = FR_INT_ERR; break; }
+ if (stat == 0) n++;
+ } while (++clst < fs->n_fatent);
+ } else {
+ clst = fs->n_fatent;
+ sect = fs->fatbase;
+ i = 0; p = 0;
+ do {
+ if (!i) {
+ res = move_window(fs, sect++);
+ if (res != FR_OK) break;
+ p = fs->win;
+ i = SS(fs);
+ }
+ if (fat == FS_FAT16) {
+ if (LD_WORD(p) == 0) n++;
+ p += 2; i -= 2;
+ } else {
+ if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
+ p += 4; i -= 4;
+ }
+ } while (--clst);
+ }
+ fs->free_clust = n;
+ if (fat == FS_FAT32) fs->fsi_flag = 1;
+ *nclst = n;
+ }
+ }
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD ncl;
+
+
+ if (!fp) return FR_INVALID_OBJECT;
+
+ res = validate(fp); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__ERROR) { /* Check abort flag */
+ res = FR_INT_ERR;
+ } else {
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ res = FR_DENIED;
+ }
+ }
+ if (res == FR_OK) {
+ if (fp->fsize > fp->fptr) {
+ fp->fsize = fp->fptr; /* Set file size to current R/W point */
+ fp->flag |= FA__WRITTEN;
+ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
+ res = remove_chain(fp->fs, fp->sclust);
+ fp->sclust = 0;
+ } else { /* When truncate a part of the file, remove remaining clusters */
+ ncl = get_fat(fp->fs, fp->clust);
+ res = FR_OK;
+ if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (ncl == 1) res = FR_INT_ERR;
+ if (res == FR_OK && ncl < fp->fs->n_fatent) {
+ res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+ if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+ }
+ }
+ }
+ if (res != FR_OK) fp->flag |= FA__ERROR;
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+ const TCHAR *path /* Pointer to the file or directory path */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj, sdj;
+ BYTE *dir;
+ DWORD dclst;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME; /* Cannot remove dot entry */
+#if _FS_LOCK
+ if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
+#endif
+ if (res == FR_OK) { /* The object is accessible */
+ dir = dj.dir;
+ if (!dir) {
+ res = FR_INVALID_NAME; /* Cannot remove the start directory */
+ } else {
+ if (dir[DIR_Attr] & AM_RDO)
+ res = FR_DENIED; /* Cannot remove R/O object */
+ }
+ dclst = ld_clust(dj.fs, dir);
+ if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
+ if (dclst < 2) {
+ res = FR_INT_ERR;
+ } else {
+ mem_cpy(&sdj, &dj, sizeof (FATFS_DIR)); /* Check if the sub-dir is empty or not */
+ sdj.sclust = dclst;
+ res = dir_sdi(&sdj, 2); /* Exclude dot entries */
+ if (res == FR_OK) {
+ res = dir_read(&sdj);
+ if (res == FR_OK /* Not empty dir */
+#if _FS_RPATH
+ || dclst == dj.fs->cdir /* Current dir */
+#endif
+ ) res = FR_DENIED;
+ if (res == FR_NO_FILE) res = FR_OK; /* Empty */
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&dj); /* Remove the directory entry */
+ if (res == FR_OK) {
+ if (dclst) /* Remove the cluster chain if exist */
+ res = remove_chain(dj.fs, dclst);
+ if (res == FR_OK) res = sync(dj.fs);
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir, n;
+ DWORD dsc, dcl, pcl, tim = get_fattime();
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
+ if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_NO_FILE) { /* Can create a new directory */
+ dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
+ res = FR_OK;
+ if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
+ if (dcl == 1) res = FR_INT_ERR;
+ if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (res == FR_OK) /* Flush FAT */
+ res = move_window(dj.fs, 0);
+ if (res == FR_OK) { /* Initialize the new directory table */
+ dsc = clust2sect(dj.fs, dcl);
+ dir = dj.fs->win;
+ mem_set(dir, 0, SS(dj.fs));
+ mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */
+ dir[DIR_Name] = '.';
+ dir[DIR_Attr] = AM_DIR;
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ st_clust(dir, dcl);
+ mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */
+ dir[33] = '.'; pcl = dj.sclust;
+ if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+ pcl = 0;
+ st_clust(dir+SZ_DIR, pcl);
+ for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */
+ dj.fs->winsect = dsc++;
+ dj.fs->wflag = 1;
+ res = move_window(dj.fs, 0);
+ if (res != FR_OK) break;
+ mem_set(dir, 0, SS(dj.fs));
+ }
+ }
+ if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */
+ if (res != FR_OK) {
+ remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */
+ } else {
+ dir = dj.dir;
+ dir[DIR_Attr] = AM_DIR; /* Attribute */
+ ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */
+ st_clust(dir, dcl); /* Table start cluster */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+ const TCHAR *path, /* Pointer to the file path */
+ BYTE value, /* Attribute bits */
+ BYTE mask /* Attribute mask to change */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Is it a root directory? */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub directory */
+ mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
+ dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+ const TCHAR *path, /* Pointer to the file/directory name */
+ const FILINFO *fno /* Pointer to the time stamp to be set */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Root directory */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub-directory */
+ ST_WORD(dir+DIR_WrtTime, fno->ftime);
+ ST_WORD(dir+DIR_WrtDate, fno->fdate);
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+ const TCHAR *path_old, /* Pointer to the old name */
+ const TCHAR *path_new /* Pointer to the new name */
+)
+{
+ FRESULT res;
+ FATFS_DIR djo, djn;
+ BYTE buf[21], *dir;
+ DWORD dw;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path_old, &djo.fs, 1);
+ if (res == FR_OK) {
+ djn.fs = djo.fs;
+ INIT_BUF(djo);
+ res = follow_path(&djo, path_old); /* Check old object */
+ if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+#if _FS_LOCK
+ if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+ if (res == FR_OK) { /* Old object is found */
+ if (!djo.dir) { /* Is root dir? */
+ res = FR_NO_FILE;
+ } else {
+ mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */
+ mem_cpy(&djn, &djo, sizeof (FATFS_DIR)); /* Check new object */
+ res = follow_path(&djn, path_new);
+ if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
+ if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
+/* Start critical section that an interruption or error can cause cross-link */
+ res = dir_register(&djn); /* Register the new entry */
+ if (res == FR_OK) {
+ dir = djn.dir; /* Copy object information except for name */
+ mem_cpy(dir+13, buf+2, 19);
+ dir[DIR_Attr] = buf[0] | AM_ARC;
+ djo.fs->wflag = 1;
+ if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
+ dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
+ if (!dw) {
+ res = FR_INT_ERR;
+ } else {
+ res = move_window(djo.fs, dw);
+ dir = djo.fs->win+SZ_DIR; /* .. entry */
+ if (res == FR_OK && dir[1] == '.') {
+ dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust;
+ st_clust(dir, dw);
+ djo.fs->wflag = 1;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&djo); /* Remove old entry */
+ if (res == FR_OK)
+ res = sync(djo.fs);
+ }
+ }
+/* End critical section */
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(djo.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg) */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+ FIL *fp, /* Pointer to the file object */
+ UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
+ UINT btr, /* Number of bytes to forward */
+ UINT *bf /* Pointer to number of bytes forwarded */
+)
+{
+ FRESULT res;
+ DWORD remain, clst, sect;
+ UINT rcnt;
+ BYTE csect;
+
+
+ *bf = 0; /* Clear transfer byte counter */
+
+ if (!fp) return FR_INVALID_OBJECT;
+
+ res = validate(fp); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check error flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */
+ fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ if (!csect) { /* On the cluster boundary? */
+ clst = (fp->fptr == 0) ? /* On the top of the file? */
+ fp->sclust : get_fat(fp->fs, fp->clust);
+ if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ if (move_window(fp->fs, sect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->dsect = sect;
+ rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
+ if (rcnt > btr) rcnt = btr;
+ rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+ if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create File System on the Drive */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */
+#define N_FATS 1 /* Number of FAT copies (1 or 2) */
+
+
+FRESULT f_mkfs (
+ BYTE drv, /* Logical drive number */
+ BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
+ UINT au /* Allocation unit size [bytes] */
+)
+{
+ static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
+ static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+ BYTE fmt, md, sys, *tbl, pdrv, part;
+ DWORD n_clst, vs, n, wsect;
+ UINT i;
+ DWORD b_vol, b_fat, b_dir, b_data; /* LBA */
+ DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */
+ FATFS *fs;
+ DSTATUS stat;
+
+
+ /* Check mounted drive and clear work area */
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+ if (sfd > 1) return FR_INVALID_PARAMETER;
+ if (au & (au - 1)) return FR_INVALID_PARAMETER;
+ fs = FatFs[drv];
+ if (!fs) return FR_NOT_ENABLED;
+ fs->fs_type = 0;
+ pdrv = LD2PD(drv); /* Physical drive */
+ part = LD2PT(drv); /* Partition (0:auto detect, 1-4:get from partition table)*/
+
+ /* Get disk statics */
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512 /* Get disk sector size */
+ if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS)
+ return FR_DISK_ERR;
+#endif
+ if (_MULTI_PARTITION && part) {
+ /* Get partition information from partition table in the MBR */
+ if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+ if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
+ tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+ if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */
+ b_vol = LD_DWORD(tbl+8); /* Volume start sector */
+ n_vol = LD_DWORD(tbl+12); /* Volume size */
+ } else {
+ /* Create a partition in this function */
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+ return FR_DISK_ERR;
+ b_vol = (sfd) ? 0 : 63; /* Volume start sector */
+ n_vol -= b_vol; /* Volume size */
+ }
+
+ if (!au) { /* AU auto selection */
+ vs = n_vol / (2000 / (SS(fs) / 512));
+ for (i = 0; vs < vst[i]; i++) ;
+ au = cst[i];
+ }
+ au /= SS(fs); /* Number of sectors per cluster */
+ if (au == 0) au = 1;
+ if (au > 128) au = 128;
+
+ /* Pre-compute number of clusters and FAT sub-type */
+ n_clst = n_vol / au;
+ fmt = FS_FAT12;
+ if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+ if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Determine offset and size of FAT structure */
+ if (fmt == FS_FAT32) {
+ n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+ n_rsv = 32;
+ n_dir = 0;
+ } else {
+ n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+ n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+ n_rsv = 1;
+ n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs);
+ }
+ b_fat = b_vol + n_rsv; /* FAT area start sector */
+ b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */
+ b_data = b_dir + n_dir; /* Data area start sector */
+ if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */
+
+ /* Align data start sector to erase block boundary (for flash memory media) */
+ if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+ n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */
+ n = (n - b_data) / N_FATS;
+ if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */
+ n_rsv += n;
+ b_fat += n;
+ } else { /* FAT12/16: Expand FAT size */
+ n_fat += n;
+ }
+
+ /* Determine number of clusters and final check of validity of the FAT sub-type */
+ n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+ if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+ || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+ return FR_MKFS_ABORTED;
+
+ switch (fmt) { /* Determine system ID for partition table */
+ case FS_FAT12: sys = 0x01; break;
+ case FS_FAT16: sys = (n_vol < 0x10000) ? 0x04 : 0x06; break;
+ default: sys = 0x0C;
+ }
+
+ if (_MULTI_PARTITION && part) {
+ /* Update system ID in the partition table */
+ tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+ tbl[4] = sys;
+ if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+ md = 0xF8;
+ } else {
+ if (sfd) { /* No partition table (SFD) */
+ md = 0xF0;
+ } else { /* Create partition table (FDISK) */
+ mem_set(fs->win, 0, SS(fs));
+ tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */
+ tbl[1] = 1; /* Partition start head */
+ tbl[2] = 1; /* Partition start sector */
+ tbl[3] = 0; /* Partition start cylinder */
+ tbl[4] = sys; /* System type */
+ tbl[5] = 254; /* Partition end head */
+ n = (b_vol + n_vol) / 63 / 255;
+ tbl[6] = (BYTE)((n >> 2) | 63); /* Partition end sector */
+ tbl[7] = (BYTE)n; /* End cylinder */
+ ST_DWORD(tbl+8, 63); /* Partition start in LBA */
+ ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
+ ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */
+ if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR sector */
+ return FR_DISK_ERR;
+ md = 0xF8;
+ }
+ }
+
+ /* Create BPB in the VBR */
+ tbl = fs->win; /* Clear sector */
+ mem_set(tbl, 0, SS(fs));
+ mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+ i = SS(fs); /* Sector size */
+ ST_WORD(tbl+BPB_BytsPerSec, i);
+ tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */
+ ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */
+ tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */
+ i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */
+ ST_WORD(tbl+BPB_RootEntCnt, i);
+ if (n_vol < 0x10000) { /* Number of total sectors */
+ ST_WORD(tbl+BPB_TotSec16, n_vol);
+ } else {
+ ST_DWORD(tbl+BPB_TotSec32, n_vol);
+ }
+ tbl[BPB_Media] = md; /* Media descriptor */
+ ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
+ ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
+ ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
+ n = get_fattime(); /* Use current time as VSN */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+BS_VolID32, n); /* VSN */
+ ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
+ ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */
+ ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */
+ ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */
+ tbl[BS_DrvNum32] = 0x80; /* Drive number */
+ tbl[BS_BootSig32] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
+ } else {
+ ST_DWORD(tbl+BS_VolID, n); /* VSN */
+ ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */
+ tbl[BS_DrvNum] = 0x80; /* Drive number */
+ tbl[BS_BootSig] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
+ }
+ ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
+ if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */
+ return FR_DISK_ERR;
+ if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */
+ disk_write(pdrv, tbl, b_vol + 6, 1);
+
+ /* Initialize FAT area */
+ wsect = b_fat;
+ for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */
+ mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */
+ n = md; /* Media descriptor byte */
+ if (fmt != FS_FAT32) {
+ n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */
+ } else {
+ n |= 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */
+ ST_DWORD(tbl+4, 0xFFFFFFFF);
+ ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */
+ }
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
+ for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ }
+ }
+
+ /* Initialize root directory */
+ i = (fmt == FS_FAT32) ? au : n_dir;
+ do {
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ } while (--i);
+
+#if _USE_ERASE /* Erase data area if needed */
+ {
+ DWORD eb[2];
+
+ eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+ disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb);
+ }
+#endif
+
+ /* Create FSInfo if needed */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
+ ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
+ ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */
+ ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */
+ ST_WORD(tbl+BS_55AA, 0xAA55);
+ disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */
+ disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */
+ }
+
+ return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+
+#if _MULTI_PARTITION == 2
+/*-----------------------------------------------------------------------*/
+/* Divide Physical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+ BYTE pdrv, /* Physical drive number */
+ const DWORD szt[], /* Pointer to the size table for each partitions */
+ void* work /* Pointer to the working buffer */
+)
+{
+ UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+ BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+ DSTATUS stat;
+ DWORD sz_disk, sz_part, s_part;
+
+
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+ /* Determine CHS in the table regardless of the drive geometry */
+ for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+ if (n == 256) n--;
+ e_hd = n - 1;
+ sz_cyl = 63 * n;
+ tot_cyl = sz_disk / sz_cyl;
+
+ /* Create partition table */
+ mem_set(buf, 0, _MAX_SS);
+ p = buf + MBR_Table; b_cyl = 0;
+ for (i = 0; i < 4; i++, p += SZ_PTE) {
+ p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
+ if (!p_cyl) continue;
+ s_part = (DWORD)sz_cyl * b_cyl;
+ sz_part = (DWORD)sz_cyl * p_cyl;
+ if (i == 0) { /* Exclude first track of cylinder 0 */
+ s_hd = 1;
+ s_part += 63; sz_part -= 63;
+ } else {
+ s_hd = 0;
+ }
+ e_cyl = b_cyl + p_cyl - 1;
+ if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+ /* Set partition table */
+ p[1] = s_hd; /* Start head */
+ p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */
+ p[3] = (BYTE)b_cyl; /* Start cylinder */
+ p[4] = 0x06; /* System type (temporary setting) */
+ p[5] = e_hd; /* End head */
+ p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */
+ p[7] = (BYTE)e_cyl; /* End cylinder */
+ ST_DWORD(p + 8, s_part); /* Start sector in LBA */
+ ST_DWORD(p + 12, sz_part); /* Partition size */
+
+ /* Next partition */
+ b_cyl += p_cyl;
+ }
+ ST_WORD(p, 0xAA55);
+
+ /* Write it to the MBR */
+ return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK;
+}
+
+
+#endif /* _MULTI_PARTITION == 2 */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file */
+/*-----------------------------------------------------------------------*/
+TCHAR* f_gets (
+ TCHAR* buff, /* Pointer to the string buffer to read */
+ int len, /* Size of string buffer (characters) */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n = 0;
+ TCHAR c, *p = buff;
+ BYTE s[2];
+ UINT rc;
+
+
+ while (n < len - 1) { /* Read bytes until buffer gets filled */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break; /* Break on EOF or error */
+ c = s[0];
+#if _LFN_UNICODE /* Read a character in UTF-8 encoding */
+ if (c >= 0x80) {
+ if (c < 0xC0) continue; /* Skip stray trailer */
+ if (c < 0xE0) { /* Two-byte sequence */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break;
+ c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
+ if (c < 0x80) c = '?';
+ } else {
+ if (c < 0xF0) { /* Three-byte sequence */
+ f_read(fil, s, 2, &rc);
+ if (rc != 2) break;
+ c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
+ if (c < 0x800) c = '?';
+ } else { /* Reject four-byte sequence */
+ c = '?';
+ }
+ }
+ }
+#endif
+#if _USE_STRFUNC >= 2
+ if (c == '\r') continue; /* Strip '\r' */
+#endif
+ *p++ = c;
+ n++;
+ if (c == '\n') break; /* Break on EOL */
+ }
+ *p = 0;
+ return n ? buff : 0; /* When no data read (eof or error), return with error. */
+}
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file */
+/*-----------------------------------------------------------------------*/
+int f_putc (
+ TCHAR c, /* A character to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ UINT bw, btw;
+ BYTE s[3];
+
+
+#if _USE_STRFUNC >= 2
+ if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */
+#endif
+
+#if _LFN_UNICODE /* Write the character in UTF-8 encoding */
+ if (c < 0x80) { /* 7-bit */
+ s[0] = (BYTE)c;
+ btw = 1;
+ } else {
+ if (c < 0x800) { /* 11-bit */
+ s[0] = (BYTE)(0xC0 | (c >> 6));
+ s[1] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 2;
+ } else { /* 16-bit */
+ s[0] = (BYTE)(0xE0 | (c >> 12));
+ s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
+ s[2] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 3;
+ }
+ }
+#else /* Write the character without conversion */
+ s[0] = (BYTE)c;
+ btw = 1;
+#endif
+ f_write(fil, s, btw, &bw); /* Write the char to the file */
+ return (bw == btw) ? 1 : EOF; /* Return the result */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file */
+/*-----------------------------------------------------------------------*/
+int f_puts (
+ const TCHAR* str, /* Pointer to the string to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n;
+
+
+ for (n = 0; *str; str++, n++) {
+ if (f_putc(*str, fil) == EOF) return EOF;
+ }
+ return n;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file */
+/*-----------------------------------------------------------------------*/
+int f_printf (
+ FIL* fil, /* Pointer to the file object */
+ const TCHAR* str, /* Pointer to the format string */
+ ... /* Optional arguments... */
+)
+{
+ va_list arp;
+ BYTE f, r;
+ UINT i, j, w;
+ ULONG v;
+ TCHAR c, d, s[16], *p;
+ int res, chc, cc;
+
+
+ va_start(arp, str);
+
+ for (cc = res = 0; cc != EOF; res += cc) {
+ c = *str++;
+ if (c == 0) break; /* End of string */
+ if (c != '%') { /* Non escape character */
+ cc = f_putc(c, fil);
+ if (cc != EOF) cc = 1;
+ continue;
+ }
+ w = f = 0;
+ c = *str++;
+ if (c == '0') { /* Flag: '0' padding */
+ f = 1; c = *str++;
+ } else {
+ if (c == '-') { /* Flag: left justified */
+ f = 2; c = *str++;
+ }
+ }
+ while (IsDigit(c)) { /* Precision */
+ w = w * 10 + c - '0';
+ c = *str++;
+ }
+ if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
+ f |= 4; c = *str++;
+ }
+ if (!c) break;
+ d = c;
+ if (IsLower(d)) d -= 0x20;
+ switch (d) { /* Type is... */
+ case 'S' : /* String */
+ p = va_arg(arp, TCHAR*);
+ for (j = 0; p[j]; j++) ;
+ chc = 0;
+ if (!(f & 2)) {
+ while (j++ < w) chc += (cc = f_putc(' ', fil));
+ }
+ chc += (cc = f_puts(p, fil));
+ while (j++ < w) chc += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = chc;
+ continue;
+ case 'C' : /* Character */
+ cc = f_putc((TCHAR)va_arg(arp, int), fil); continue;
+ case 'B' : /* Binary */
+ r = 2; break;
+ case 'O' : /* Octal */
+ r = 8; break;
+ case 'D' : /* Signed decimal */
+ case 'U' : /* Unsigned decimal */
+ r = 10; break;
+ case 'X' : /* Hexdecimal */
+ r = 16; break;
+ default: /* Unknown type (pass-through) */
+ cc = f_putc(c, fil); continue;
+ }
+
+ /* Get an argument and put it in numeral */
+ v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int));
+ if (d == 'D' && (v & 0x80000000)) {
+ v = 0 - v;
+ f |= 8;
+ }
+ i = 0;
+ do {
+ d = (TCHAR)(v % r); v /= r;
+ if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ s[i++] = d + '0';
+ } while (v && i < sizeof s / sizeof s[0]);
+ if (f & 8) s[i++] = '-';
+ j = i; d = (f & 1) ? '0' : ' ';
+ res = 0;
+ while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil));
+ do res += (cc = f_putc(s[--i], fil)); while(i);
+ while (j++ < w) res += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = res;
+ }
+
+ va_end(arp);
+ return (cc == EOF) ? cc : res;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h
new file mode 100644
index 000000000..610ad0a68
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h
@@ -0,0 +1,337 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module include file R0.09a (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/ Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#ifndef _FATFS
+#define _FATFS 4004 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h" /* Basic integer types */
+#include "ffconf.h" /* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION /* Multiple partition configuration */
+typedef struct {
+ BYTE pd; /* Physical drive number */
+ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
+#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
+#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
+
+#else /* Single partition configuration */
+#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */
+
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE /* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 in non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else /* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* FAT sub-type (0:Not mounted) */
+ BYTE drv; /* Physical drive number */
+ BYTE csize; /* Sectors per cluster (1,2,4...128) */
+ BYTE n_fats; /* Number of FAT copies (1,2) */
+ BYTE wflag; /* win[] dirty flag (1:must be written back) */
+ BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
+ WORD id; /* File system mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != 512
+ WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
+#endif
+#if _FS_REENTRANT
+ _SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+ DWORD last_clust; /* Last allocated cluster */
+ DWORD free_clust; /* Number of free clusters */
+ DWORD fsi_sector; /* fsinfo sector (FAT32) */
+#endif
+#if _FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#endif
+ DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
+ DWORD fsize; /* Sectors per FAT */
+ DWORD fatbase; /* FAT start sector */
+ DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
+ DWORD database; /* Data start sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+ BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
+} FATFS;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the related file system object */
+ WORD id; /* File system mount ID of the related file system object */
+ BYTE flag; /* File status flags */
+ BYTE pad1;
+ DWORD fptr; /* File read/write pointer (0ed on file open) */
+ DWORD fsize; /* File size */
+ DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
+ DWORD clust; /* Current cluster of fpter */
+ DWORD dsect; /* Current data sector of fpter */
+#if !_FS_READONLY
+ DWORD dir_sect; /* Sector containing the directory entry */
+ BYTE* dir_ptr; /* Pointer to the directory entry in the window */
+#endif
+#if _USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
+#endif
+#if _FS_LOCK
+ UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
+#endif
+#if !_FS_TINY
+ BYTE buf[_MAX_SS]; /* File data read/write buffer */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the owner file system object */
+ WORD id; /* Owner file system mount ID */
+ WORD index; /* Current read/write index number */
+ DWORD sclust; /* Table start cluster (0:Root dir) */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector */
+ BYTE* dir; /* Pointer to the current SFN entry in the win[] */
+ BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+ WCHAR* lfn; /* Pointer to the LFN working buffer */
+ WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+} FATFS_DIR;
+
+
+
+/* File status structure (FILINFO) */
+
+typedef struct {
+ DWORD fsize; /* File size */
+ WORD fdate; /* Last modified date */
+ WORD ftime; /* Last modified time */
+ BYTE fattrib; /* Attribute */
+ TCHAR fname[13]; /* Short file name (8.3 format) */
+#if _USE_LFN
+ TCHAR* lfname; /* Pointer to the LFN buffer */
+ UINT lfsize; /* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Access denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
+ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
+FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
+FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
+FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
+FRESULT f_close (FIL*); /* Close an open file object */
+FRESULT f_opendir (FATFS_DIR*, const TCHAR*); /* Open an existing directory */
+FRESULT f_readdir (FATFS_DIR*, FILINFO*); /* Read a directory item */
+FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
+FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
+FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
+FRESULT f_truncate (FIL*); /* Truncate file */
+FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
+FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
+FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
+FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attribute of the file/dir */
+FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change times-tamp of the file/dir */
+FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
+FRESULT f_chdrive (BYTE); /* Change current drive */
+FRESULT f_chdir (const TCHAR*); /* Change current directory */
+FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
+FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
+FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
+FRESULT f_fdisk (BYTE, const DWORD[], void*); /* Divide a physical drive into some partitions */
+int f_putc (TCHAR, FIL*); /* Put a character to the file */
+int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
+int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
+
+#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
+#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !_FS_READONLY
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN /* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
+#if _USE_LFN == 3 /* Memory functions */
+void* ff_memalloc (UINT); /* Allocate memory block */
+void ff_memfree (void*); /* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
+int ff_req_grant (_SYNC_t); /* Lock sync object */
+void ff_rel_grant (_SYNC_t); /* Unlock sync object */
+int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access control and file status flags (FIL.flag) */
+
+#define FA_READ 0x01
+#define FA_OPEN_EXISTING 0x00
+#define FA__ERROR 0x80
+
+#if !_FS_READONLY
+#define FA_WRITE 0x02
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA__WRITTEN 0x20
+#define FA__DIRTY 0x40
+#endif
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+
+
+/* File attribute bits for directory entry */
+
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_VOL 0x08 /* Volume label */
+#define AM_LFN 0x0F /* LFN entry */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+#define AM_MASK 0x3F /* Mask of defined bits */
+
+
+/* Fast seek feature */
+#define CREATE_LINKMAP 0xFFFFFFFF
+
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros */
+
+#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else /* Use byte-by-byte access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h
new file mode 100644
index 000000000..959f98468
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h
@@ -0,0 +1,198 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module configuration file R0.09a (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FFCONF
+#define _FFCONF 4004 /* Revision ID */
+
+#define FFS_DBG 0
+
+/*---------------------------------------------------------------------------/
+/ Functions and Buffer Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
+/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
+/ object instead of the sector buffer in the individual file object for file
+/ data transfer. This reduces memory consumption 512 bytes each file object. */
+
+
+#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
+/* Setting _FS_READONLY to 1 defines read only configuration. This removes
+/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
+/ f_truncate and useless f_getfree. */
+
+
+#define _FS_MINIMIZE 0 /* 0 to 3 */
+/* The _FS_MINIMIZE option defines minimization level to remove some functions.
+/
+/ 0: Full function.
+/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
+/ are removed.
+/ 2: f_opendir and f_readdir are removed in addition to 1.
+/ 3: f_lseek is removed in addition to 2. */
+
+
+#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */
+/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
+
+
+#define _USE_MKFS 1 /* 0:Disable or 1:Enable */
+/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
+
+
+#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
+/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
+
+
+#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
+/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE 858
+/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
+/ Incorrect setting of the code page can cause a file open failure.
+/
+/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
+/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
+/ 949 - Korean (DBCS, OEM, Windows)
+/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/ 1250 - Central Europe (Windows)
+/ 1251 - Cyrillic (Windows)
+/ 1252 - Latin 1 (Windows)
+/ 1253 - Greek (Windows)
+/ 1254 - Turkish (Windows)
+/ 1255 - Hebrew (Windows)
+/ 1256 - Arabic (Windows)
+/ 1257 - Baltic (Windows)
+/ 1258 - Vietnam (OEM, Windows)
+/ 437 - U.S. (OEM)
+/ 720 - Arabic (OEM)
+/ 737 - Greek (OEM)
+/ 775 - Baltic (OEM)
+/ 850 - Multilingual Latin 1 (OEM)
+/ 858 - Multilingual Latin 1 + Euro (OEM)
+/ 852 - Latin 2 (OEM)
+/ 855 - Cyrillic (OEM)
+/ 866 - Russian (OEM)
+/ 857 - Turkish (OEM)
+/ 862 - Hebrew (OEM)
+/ 874 - Thai (OEM, Windows)
+/ 1 - ASCII only (Valid for non LFN cfg.)
+*/
+
+
+#define _USE_LFN 1 /* 0 to 3 */
+#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN option switches the LFN support.
+/
+/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
+/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
+/ to the project. When enable to use heap, memory control functions
+/ ff_memalloc() and ff_memfree() must be added to the project. */
+
+
+#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
+/* To switch the character code set on FatFs API to Unicode,
+/ enable LFN feature and set _LFN_UNICODE to 1. */
+
+
+#define _FS_RPATH 0 /* 0 to 2 */
+/* The _FS_RPATH option configures relative path feature.
+/
+/ 0: Disable relative path feature and remove related functions.
+/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
+/ 2: f_getcwd() is available in addition to 1.
+/
+/ Note that output of the f_readdir fnction is affected by this option. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Physical Drive Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES 1
+/* Number of volumes (logical drives) to be used. */
+
+
+#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
+/* Maximum sector size to be handled.
+/ Always set 512 for memory card and hard disk but a larger value may be
+/ required for on-board flash memory, floppy disk and optical disk.
+/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
+/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
+
+
+#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */
+/* When set to 0, each volume is bound to the same physical drive number and
+/ it can mount only first primaly partition. When it is set to 1, each volume
+/ is tied to the partitions listed in VolToPart[]. */
+
+
+#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
+/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
+/ should be added to the disk_ioctl functio. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _WORD_ACCESS 0 /* 0 or 1 */
+/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
+/ option defines which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access.
+/ 1: Word access. Do not choose this unless following condition is met.
+/
+/ When the byte order on the memory is big-endian or address miss-aligned word
+/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/ If it is not the case, the value can also be set to 1 to improve the
+/ performance and code size.
+*/
+
+
+/* A header file that defines sync object types on the O/S, such as
+/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
+
+#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
+
+/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
+/
+/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
+/ 1: Enable reentrancy. Also user provided synchronization handlers,
+/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
+/ function must be added to the project. */
+
+
+#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
+/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
+ The value defines how many files can be opened simultaneously. */
+
+#define FLUSH_ON_NEW_CLUSTER 0 /* Sync the file on every new cluster */
+#define FLUSH_ON_NEW_SECTOR 1 /* Sync the file on every new sector */
+/* Only one of these two defines needs to be set to 1. If both are set to 0
+ the file is only sync when closed.
+ Clusters are group of sectors (eg: 8 sectors). Flushing on new cluster means
+ it would be less often than flushing on new sector. Sectors are generally
+ 512 Bytes long. */
+
+#endif /* _FFCONFIG */
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h
new file mode 100644
index 000000000..1b99b37f6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else /* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int INT;
+typedef unsigned int UINT;
+
+/* These types must be 8-bit integer */
+typedef char CHAR;
+typedef unsigned char UCHAR;
+typedef unsigned char BYTE;
+
+/* These types must be 16-bit integer */
+typedef short SHORT;
+typedef unsigned short USHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long LONG;
+typedef unsigned long ULONG;
+typedef unsigned long DWORD;
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp
new file mode 100644
index 000000000..60a4e7b2b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include <string.h>
+#include "ff.h"
+#include "FATDirHandle.h"
+
+using namespace mbed;
+
+FATDirHandle::FATDirHandle(const FATFS_DIR &the_dir) {
+ dir = the_dir;
+}
+
+int FATDirHandle::closedir() {
+ delete this;
+ return 0;
+}
+
+struct dirent *FATDirHandle::readdir() {
+ FILINFO finfo;
+
+#if _USE_LFN
+ finfo.lfname = cur_entry.d_name;
+ finfo.lfsize = sizeof(cur_entry.d_name);
+#endif // _USE_LFN
+
+ FRESULT res = f_readdir(&dir, &finfo);
+
+#if _USE_LFN
+ if(res != 0 || finfo.fname[0]==0) {
+ return NULL;
+ } else {
+ if(cur_entry.d_name[0]==0) {
+ // No long filename so use short filename.
+ memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+ }
+ return &cur_entry;
+ }
+#else
+ if(res != 0 || finfo.fname[0]==0) {
+ return NULL;
+ } else {
+ memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+ return &cur_entry;
+ }
+#endif /* _USE_LFN */
+}
+
+void FATDirHandle::rewinddir() {
+ dir.index = 0;
+}
+
+off_t FATDirHandle::telldir() {
+ return dir.index;
+}
+
+void FATDirHandle::seekdir(off_t location) {
+ dir.index = location;
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h b/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h
new file mode 100644
index 000000000..25ececacf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATDIRHANDLE_H
+#define MBED_FATDIRHANDLE_H
+
+#include "DirHandle.h"
+
+using namespace mbed;
+
+class FATDirHandle : public DirHandle {
+
+ public:
+ FATDirHandle(const FATFS_DIR &the_dir);
+ virtual int closedir();
+ virtual struct dirent *readdir();
+ virtual void rewinddir();
+ virtual off_t telldir();
+ virtual void seekdir(off_t location);
+
+ private:
+ FATFS_DIR dir;
+ struct dirent cur_entry;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp
new file mode 100644
index 000000000..8c2bf881e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "ff.h"
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileHandle.h"
+
+FATFileHandle::FATFileHandle(FIL fh) {
+ _fh = fh;
+}
+
+int FATFileHandle::close() {
+ int retval = f_close(&_fh);
+ delete this;
+ return retval;
+}
+
+ssize_t FATFileHandle::write(const void* buffer, size_t length) {
+ UINT n;
+ FRESULT res = f_write(&_fh, buffer, length, &n);
+ if (res) {
+ debug_if(FFS_DBG, "f_write() failed: %d", res);
+ return -1;
+ }
+ return n;
+}
+
+ssize_t FATFileHandle::read(void* buffer, size_t length) {
+ debug_if(FFS_DBG, "read(%d)\n", length);
+ UINT n;
+ FRESULT res = f_read(&_fh, buffer, length, &n);
+ if (res) {
+ debug_if(FFS_DBG, "f_read() failed: %d\n", res);
+ return -1;
+ }
+ return n;
+}
+
+int FATFileHandle::isatty() {
+ return 0;
+}
+
+off_t FATFileHandle::lseek(off_t position, int whence) {
+ if (whence == SEEK_END) {
+ position += _fh.fsize;
+ } else if(whence==SEEK_CUR) {
+ position += _fh.fptr;
+ }
+ FRESULT res = f_lseek(&_fh, position);
+ if (res) {
+ debug_if(FFS_DBG, "lseek failed: %d\n", res);
+ return -1;
+ } else {
+ debug_if(FFS_DBG, "lseek OK, returning %i\n", _fh.fptr);
+ return _fh.fptr;
+ }
+}
+
+int FATFileHandle::fsync() {
+ FRESULT res = f_sync(&_fh);
+ if (res) {
+ debug_if(FFS_DBG, "f_sync() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+off_t FATFileHandle::flen() {
+ return _fh.fsize;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h
new file mode 100644
index 000000000..d41592f9c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILEHANDLE_H
+#define MBED_FATFILEHANDLE_H
+
+#include "FileHandle.h"
+
+using namespace mbed;
+
+class FATFileHandle : public FileHandle {
+public:
+
+ FATFileHandle(FIL fh);
+ virtual int close();
+ virtual ssize_t write(const void* buffer, size_t length);
+ virtual ssize_t read(void* buffer, size_t length);
+ virtual int isatty();
+ virtual off_t lseek(off_t position, int whence);
+ virtual int fsync();
+ virtual off_t flen();
+
+protected:
+
+ FIL _fh;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp
new file mode 100644
index 000000000..da7e8e086
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp
@@ -0,0 +1,153 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "mbed.h"
+
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileSystem.h"
+#include "FATFileHandle.h"
+#include "FATDirHandle.h"
+
+DWORD get_fattime(void) {
+ time_t rawtime;
+ time(&rawtime);
+ struct tm *ptm = localtime(&rawtime);
+ return (DWORD)(ptm->tm_year - 80) << 25
+ | (DWORD)(ptm->tm_mon + 1 ) << 21
+ | (DWORD)(ptm->tm_mday ) << 16
+ | (DWORD)(ptm->tm_hour ) << 11
+ | (DWORD)(ptm->tm_min ) << 5
+ | (DWORD)(ptm->tm_sec/2 );
+}
+
+FATFileSystem *FATFileSystem::_ffs[_VOLUMES] = {0};
+
+FATFileSystem::FATFileSystem(const char* n) : FileSystemLike(n) {
+ debug_if(FFS_DBG, "FATFileSystem(%s)\n", n);
+ for(int i=0; i<_VOLUMES; i++) {
+ if(_ffs[i] == 0) {
+ _ffs[i] = this;
+ _fsid = i;
+ debug_if(FFS_DBG, "Mounting [%s] on ffs drive [%d]\n", _name, _fsid);
+ f_mount(i, &_fs);
+ return;
+ }
+ }
+ error("Couldn't create %s in FATFileSystem::FATFileSystem\n", n);
+}
+
+FATFileSystem::~FATFileSystem() {
+ for (int i=0; i<_VOLUMES; i++) {
+ if (_ffs[i] == this) {
+ _ffs[i] = 0;
+ f_mount(i, NULL);
+ }
+ }
+}
+
+FileHandle *FATFileSystem::open(const char* name, int flags) {
+ debug_if(FFS_DBG, "open(%s) on filesystem [%s], drv [%d]\n", name, _name, _fsid);
+ char n[64];
+ sprintf(n, "%d:/%s", _fsid, name);
+
+ /* POSIX flags -> FatFS open mode */
+ BYTE openmode;
+ if (flags & O_RDWR) {
+ openmode = FA_READ|FA_WRITE;
+ } else if(flags & O_WRONLY) {
+ openmode = FA_WRITE;
+ } else {
+ openmode = FA_READ;
+ }
+ if(flags & O_CREAT) {
+ if(flags & O_TRUNC) {
+ openmode |= FA_CREATE_ALWAYS;
+ } else {
+ openmode |= FA_OPEN_ALWAYS;
+ }
+ }
+
+ FIL fh;
+ FRESULT res = f_open(&fh, n, openmode);
+ if (res) {
+ debug_if(FFS_DBG, "f_open('w') failed: %d\n", res);
+ return NULL;
+ }
+ if (flags & O_APPEND) {
+ f_lseek(&fh, fh.fsize);
+ }
+ return new FATFileHandle(fh);
+}
+
+int FATFileSystem::remove(const char *filename) {
+ FRESULT res = f_unlink(filename);
+ if (res) {
+ debug_if(FFS_DBG, "f_unlink() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+int FATFileSystem::rename(const char *oldname, const char *newname) {
+ FRESULT res = f_rename(oldname, newname);
+ if (res) {
+ debug_if(FFS_DBG, "f_rename() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+int FATFileSystem::format() {
+ FRESULT res = f_mkfs(_fsid, 0, 512); // Logical drive number, Partitioning rule, Allocation unit size (bytes per cluster)
+ if (res) {
+ debug_if(FFS_DBG, "f_mkfs() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+DirHandle *FATFileSystem::opendir(const char *name) {
+ FATFS_DIR dir;
+ FRESULT res = f_opendir(&dir, name);
+ if (res != 0) {
+ return NULL;
+ }
+ return new FATDirHandle(dir);
+}
+
+int FATFileSystem::mkdir(const char *name, mode_t mode) {
+ FRESULT res = f_mkdir(name);
+ return res == 0 ? 0 : -1;
+}
+
+int FATFileSystem::mount() {
+ FRESULT res = f_mount(_fsid, &_fs);
+ return res == 0 ? 0 : -1;
+}
+
+int FATFileSystem::unmount() {
+ if (disk_sync())
+ return -1;
+ FRESULT res = f_mount(_fsid, NULL);
+ return res == 0 ? 0 : -1;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h
new file mode 100644
index 000000000..ff137fed9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILESYSTEM_H
+#define MBED_FATFILESYSTEM_H
+
+#include "FileSystemLike.h"
+#include "FileHandle.h"
+#include "ff.h"
+#include <stdint.h>
+
+using namespace mbed;
+
+/**
+ * FATFileSystem based on ChaN's Fat Filesystem library v0.8
+ */
+class FATFileSystem : public FileSystemLike {
+public:
+
+ FATFileSystem(const char* n);
+ virtual ~FATFileSystem();
+
+ static FATFileSystem * _ffs[_VOLUMES]; // FATFileSystem objects, as parallel to FatFs drives array
+ FATFS _fs; // Work area (file system object) for logical drive
+ int _fsid;
+
+ /**
+ * Opens a file on the filesystem
+ */
+ virtual FileHandle *open(const char* name, int flags);
+
+ /**
+ * Removes a file path
+ */
+ virtual int remove(const char *filename);
+
+ /**
+ * Renames a file
+ */
+ virtual int rename(const char *oldname, const char *newname);
+
+ /**
+ * Formats a logical drive, FDISK artitioning rule, 512 bytes per cluster
+ */
+ virtual int format();
+
+ /**
+ * Opens a directory on the filesystem
+ */
+ virtual DirHandle *opendir(const char *name);
+
+ /**
+ * Creates a directory path
+ */
+ virtual int mkdir(const char *name, mode_t mode);
+
+ /**
+ * Mounts the filesystem
+ */
+ virtual int mount();
+
+ /**
+ * Unmounts the filesystem
+ */
+ virtual int unmount();
+
+ virtual int disk_initialize() { return 0; }
+ virtual int disk_status() { return 0; }
+ virtual int disk_read(uint8_t * buffer, uint64_t sector, uint8_t count) = 0;
+ virtual int disk_write(const uint8_t * buffer, uint64_t sector, uint8_t count) = 0;
+ virtual int disk_sync() { return 0; }
+ virtual uint64_t disk_sectors() = 0;
+
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h b/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h
new file mode 100644
index 000000000..0bb415ebc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library - MemFileSystem
+ * Copyright (c) 2008, sford
+ */
+
+
+#ifndef MBED_MEMFILESYSTEM_H
+#define MBED_MEMFILESYSTEM_H
+
+#include "FATFileSystem.h"
+
+namespace mbed
+{
+
+ class MemFileSystem : public FATFileSystem
+ {
+ public:
+
+ // 2000 sectors, each 512 bytes (malloced as required)
+ char *sectors[2000];
+
+ MemFileSystem(const char* name) : FATFileSystem(name) {
+ memset(sectors, 0, sizeof(sectors));
+ }
+
+ virtual ~MemFileSystem() {
+ for(int i = 0; i < 2000; i++) {
+ if(sectors[i]) {
+ free(sectors[i]);
+ }
+ }
+ }
+
+ // read a sector in to the buffer, return 0 if ok
+ virtual int disk_read(char *buffer, int sector) {
+ if(sectors[sector] == 0) {
+ // nothing allocated means sector is empty
+ memset(buffer, 0, 512);
+ } else {
+ memcpy(buffer, sectors[sector], 512);
+ }
+ return 0;
+ }
+
+ // write a sector from the buffer, return 0 if ok
+ virtual int disk_write(const char *buffer, int sector) {
+ // if buffer is zero deallocate sector
+ char zero[512];
+ memset(zero, 0, 512);
+ if(memcmp(zero, buffer, 512)==0) {
+ if(sectors[sector] != 0) {
+ free(sectors[sector]);
+ sectors[sector] = 0;
+ }
+ return 0;
+ }
+ // else allocate a sector if needed, and write
+ if(sectors[sector] == 0) {
+ char *sec = (char*)malloc(512);
+ if(sec==0) {
+ return 1; // out of memory
+ }
+ sectors[sector] = sec;
+ }
+ memcpy(sectors[sector], buffer, 512);
+ return 0;
+ }
+
+ // return the number of sectors
+ virtual int disk_sectors() {
+ return sizeof(sectors)/sizeof(sectors[0]);
+ }
+
+ };
+
+}
+
+#endif \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp b/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp
new file mode 100644
index 000000000..054035553
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp
@@ -0,0 +1,498 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+/* Introduction
+ * ------------
+ * SD and MMC cards support a number of interfaces, but common to them all
+ * is one based on SPI. This is the one I'm implmenting because it means
+ * it is much more portable even though not so performant, and we already
+ * have the mbed SPI Interface!
+ *
+ * The main reference I'm using is Chapter 7, "SPI Mode" of:
+ * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
+ *
+ * SPI Startup
+ * -----------
+ * The SD card powers up in SD mode. The SPI interface mode is selected by
+ * asserting CS low and sending the reset command (CMD0). The card will
+ * respond with a (R1) response.
+ *
+ * CMD8 is optionally sent to determine the voltage range supported, and
+ * indirectly determine whether it is a version 1.x SD/non-SD card or
+ * version 2.x. I'll just ignore this for now.
+ *
+ * ACMD41 is repeatedly issued to initialise the card, until "in idle"
+ * (bit 0) of the R1 response goes to '0', indicating it is initialised.
+ *
+ * You should also indicate whether the host supports High Capicity cards,
+ * and check whether the card is high capacity - i'll also ignore this
+ *
+ * SPI Protocol
+ * ------------
+ * The SD SPI protocol is based on transactions made up of 8-bit words, with
+ * the host starting every bus transaction by asserting the CS signal low. The
+ * card always responds to commands, data blocks and errors.
+ *
+ * The protocol supports a CRC, but by default it is off (except for the
+ * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
+ * I'll leave the CRC off I think!
+ *
+ * Standard capacity cards have variable data block sizes, whereas High
+ * Capacity cards fix the size of data block to 512 bytes. I'll therefore
+ * just always use the Standard Capacity cards with a block size of 512 bytes.
+ * This is set with CMD16.
+ *
+ * You can read and write single blocks (CMD17, CMD25) or multiple blocks
+ * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
+ * the card gets a read command, it responds with a response token, and then
+ * a data token or an error.
+ *
+ * SPI Command Format
+ * ------------------
+ * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
+ *
+ * +---------------+------------+------------+-----------+----------+--------------+
+ * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
+ * +---------------+------------+------------+-----------+----------+--------------+
+ *
+ * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
+ *
+ * All Application Specific commands shall be preceded with APP_CMD (CMD55).
+ *
+ * SPI Response Format
+ * -------------------
+ * The main response format (R1) is a status byte (normally zero). Key flags:
+ * idle - 1 if the card is in an idle state/initialising
+ * cmd - 1 if an illegal command code was detected
+ *
+ * +-------------------------------------------------+
+ * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
+ * +-------------------------------------------------+
+ *
+ * R1b is the same, except it is followed by a busy signal (zeros) until
+ * the first non-zero byte when it is ready again.
+ *
+ * Data Response Token
+ * -------------------
+ * Every data block written to the card is acknowledged by a byte
+ * response token
+ *
+ * +----------------------+
+ * | xxx | 0 | status | 1 |
+ * +----------------------+
+ * 010 - OK!
+ * 101 - CRC Error
+ * 110 - Write Error
+ *
+ * Single Block Read and Write
+ * ---------------------------
+ *
+ * Block transfers have a byte header, followed by the data, followed
+ * by a 16-bit CRC. In our case, the data will always be 512 bytes.
+ *
+ * +------+---------+---------+- - - -+---------+-----------+----------+
+ * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
+ * +------+---------+---------+- - - -+---------+-----------+----------+
+ */
+#include "SDFileSystem.h"
+#include "mbed_debug.h"
+
+#define SD_COMMAND_TIMEOUT 5000
+
+#define SD_DBG 0
+
+SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
+ FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) {
+ _cs = 1;
+
+ // Set default to 100kHz for initialisation and 1MHz for data transfer
+ _init_sck = 100000;
+ _transfer_sck = 1000000;
+}
+
+#define R1_IDLE_STATE (1 << 0)
+#define R1_ERASE_RESET (1 << 1)
+#define R1_ILLEGAL_COMMAND (1 << 2)
+#define R1_COM_CRC_ERROR (1 << 3)
+#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
+#define R1_ADDRESS_ERROR (1 << 5)
+#define R1_PARAMETER_ERROR (1 << 6)
+
+// Types
+// - v1.x Standard Capacity
+// - v2.x Standard Capacity
+// - v2.x High Capacity
+// - Not recognised as an SD Card
+#define SDCARD_FAIL 0
+#define SDCARD_V1 1
+#define SDCARD_V2 2
+#define SDCARD_V2HC 3
+
+int SDFileSystem::initialise_card() {
+ // Set to SCK for initialisation, and clock card with cs = 1
+ _spi.frequency(_init_sck);
+ _cs = 1;
+ for (int i = 0; i < 16; i++) {
+ _spi.write(0xFF);
+ }
+
+ // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
+ if (_cmd(0, 0) != R1_IDLE_STATE) {
+ debug("No disk, or could not put SD card in to SPI idle state\n");
+ return SDCARD_FAIL;
+ }
+
+ // send CMD8 to determine whther it is ver 2.x
+ int r = _cmd8();
+ if (r == R1_IDLE_STATE) {
+ return initialise_card_v2();
+ } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
+ return initialise_card_v1();
+ } else {
+ debug("Not in idle state after sending CMD8 (not an SD card?)\n");
+ return SDCARD_FAIL;
+ }
+}
+
+int SDFileSystem::initialise_card_v1() {
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ _cmd(55, 0);
+ if (_cmd(41, 0) == 0) {
+ cdv = 512;
+ debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
+ return SDCARD_V1;
+ }
+ }
+
+ debug("Timeout waiting for v1.x card\n");
+ return SDCARD_FAIL;
+}
+
+int SDFileSystem::initialise_card_v2() {
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ wait_ms(50);
+ _cmd58();
+ _cmd(55, 0);
+ if (_cmd(41, 0x40000000) == 0) {
+ _cmd58();
+ debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
+ cdv = 1;
+ return SDCARD_V2;
+ }
+ }
+
+ debug("Timeout waiting for v2.x card\n");
+ return SDCARD_FAIL;
+}
+
+int SDFileSystem::disk_initialize() {
+ _is_initialized = initialise_card();
+ if (_is_initialized == 0) {
+ debug("Fail to initialize card\n");
+ return 1;
+ }
+ debug_if(SD_DBG, "init card = %d\n", _is_initialized);
+ _sectors = _sd_sectors();
+
+ // Set block length to 512 (CMD16)
+ if (_cmd(16, 512) != 0) {
+ debug("Set 512-byte block timed out\n");
+ return 1;
+ }
+
+ // Set SCK for data transfer
+ _spi.frequency(_transfer_sck);
+ return 0;
+}
+
+int SDFileSystem::disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ if (!_is_initialized) {
+ return -1;
+ }
+
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ // set write address for single block (CMD24)
+ if (_cmd(24, b * cdv) != 0) {
+ return 1;
+ }
+
+ // send the data block
+ _write(buffer, 512);
+ buffer += 512;
+ }
+
+ return 0;
+}
+
+int SDFileSystem::disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ if (!_is_initialized) {
+ return -1;
+ }
+
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ // set read address for single block (CMD17)
+ if (_cmd(17, b * cdv) != 0) {
+ return 1;
+ }
+
+ // receive the data
+ _read(buffer, 512);
+ buffer += 512;
+ }
+
+ return 0;
+}
+
+int SDFileSystem::disk_status() {
+ // FATFileSystem::disk_status() returns 0 when initialized
+ if (_is_initialized) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+int SDFileSystem::disk_sync() { return 0; }
+uint64_t SDFileSystem::disk_sectors() { return _sectors; }
+
+
+// PRIVATE FUNCTIONS
+int SDFileSystem::_cmd(int cmd, int arg) {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | cmd);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ _cs = 1;
+ _spi.write(0xFF);
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+int SDFileSystem::_cmdx(int cmd, int arg) {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | cmd);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+
+int SDFileSystem::_cmd58() {
+ _cs = 0;
+ int arg = 0;
+
+ // send a command
+ _spi.write(0x40 | 58);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ int ocr = _spi.write(0xFF) << 24;
+ ocr |= _spi.write(0xFF) << 16;
+ ocr |= _spi.write(0xFF) << 8;
+ ocr |= _spi.write(0xFF) << 0;
+ _cs = 1;
+ _spi.write(0xFF);
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+int SDFileSystem::_cmd8() {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | 8); // CMD8
+ _spi.write(0x00); // reserved
+ _spi.write(0x00); // reserved
+ _spi.write(0x01); // 3.3v
+ _spi.write(0xAA); // check pattern
+ _spi.write(0x87); // crc
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
+ char response[5];
+ response[0] = _spi.write(0xFF);
+ if (!(response[0] & 0x80)) {
+ for (int j = 1; j < 5; j++) {
+ response[i] = _spi.write(0xFF);
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return response[0];
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
+ _cs = 0;
+
+ // read until start byte (0xFF)
+ while (_spi.write(0xFF) != 0xFE);
+
+ // read data
+ for (uint32_t i = 0; i < length; i++) {
+ buffer[i] = _spi.write(0xFF);
+ }
+ _spi.write(0xFF); // checksum
+ _spi.write(0xFF);
+
+ _cs = 1;
+ _spi.write(0xFF);
+ return 0;
+}
+
+int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
+ _cs = 0;
+
+ // indicate start of block
+ _spi.write(0xFE);
+
+ // write the data
+ for (uint32_t i = 0; i < length; i++) {
+ _spi.write(buffer[i]);
+ }
+
+ // write the checksum
+ _spi.write(0xFF);
+ _spi.write(0xFF);
+
+ // check the response token
+ if ((_spi.write(0xFF) & 0x1F) != 0x05) {
+ _cs = 1;
+ _spi.write(0xFF);
+ return 1;
+ }
+
+ // wait for write to finish
+ while (_spi.write(0xFF) == 0);
+
+ _cs = 1;
+ _spi.write(0xFF);
+ return 0;
+}
+
+static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
+ uint32_t bits = 0;
+ uint32_t size = 1 + msb - lsb;
+ for (uint32_t i = 0; i < size; i++) {
+ uint32_t position = lsb + i;
+ uint32_t byte = 15 - (position >> 3);
+ uint32_t bit = position & 0x7;
+ uint32_t value = (data[byte] >> bit) & 1;
+ bits |= value << i;
+ }
+ return bits;
+}
+
+uint64_t SDFileSystem::_sd_sectors() {
+ uint32_t c_size, c_size_mult, read_bl_len;
+ uint32_t block_len, mult, blocknr, capacity;
+ uint32_t hc_c_size;
+ uint64_t blocks;
+
+ // CMD9, Response R2 (R1 byte + 16-byte block read)
+ if (_cmdx(9, 0) != 0) {
+ debug("Didn't get a response from the disk\n");
+ return 0;
+ }
+
+ uint8_t csd[16];
+ if (_read(csd, 16) != 0) {
+ debug("Couldn't read csd response from disk\n");
+ return 0;
+ }
+
+ // csd_structure : csd[127:126]
+ // c_size : csd[73:62]
+ // c_size_mult : csd[49:47]
+ // read_bl_len : csd[83:80] - the *maximum* read block length
+
+ int csd_structure = ext_bits(csd, 127, 126);
+
+ switch (csd_structure) {
+ case 0:
+ cdv = 512;
+ c_size = ext_bits(csd, 73, 62);
+ c_size_mult = ext_bits(csd, 49, 47);
+ read_bl_len = ext_bits(csd, 83, 80);
+
+ block_len = 1 << read_bl_len;
+ mult = 1 << (c_size_mult + 2);
+ blocknr = (c_size + 1) * mult;
+ capacity = blocknr * block_len;
+ blocks = capacity / 512;
+ debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
+ break;
+
+ case 1:
+ cdv = 1;
+ hc_c_size = ext_bits(csd, 63, 48);
+ blocks = (hc_c_size+1)*1024;
+ debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
+ break;
+
+ default:
+ debug("CSD struct unsupported\r\n");
+ return 0;
+ };
+ return blocks;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h b/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h
new file mode 100644
index 000000000..73aba494d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_SDFILESYSTEM_H
+#define MBED_SDFILESYSTEM_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+#include <stdint.h>
+
+/** Access the filesystem on an SD Card using SPI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDFileSystem.h"
+ *
+ * SDFileSystem sd(p5, p6, p7, p12, "sd"); // mosi, miso, sclk, cs
+ *
+ * int main() {
+ * FILE *fp = fopen("/sd/myfile.txt", "w");
+ * fprintf(fp, "Hello World!\n");
+ * fclose(fp);
+ * }
+ */
+class SDFileSystem : public FATFileSystem {
+public:
+
+ /** Create the File System for accessing an SD Card using SPI
+ *
+ * @param mosi SPI mosi pin connected to SD Card
+ * @param miso SPI miso pin conencted to SD Card
+ * @param sclk SPI sclk pin connected to SD Card
+ * @param cs DigitalOut pin used as SD Card chip select
+ * @param name The name used to access the virtual filesystem
+ */
+ SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
+ virtual int disk_initialize();
+ virtual int disk_status();
+ virtual int disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count);
+ virtual int disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count);
+ virtual int disk_sync();
+ virtual uint64_t disk_sectors();
+
+protected:
+
+ int _cmd(int cmd, int arg);
+ int _cmdx(int cmd, int arg);
+ int _cmd8();
+ int _cmd58();
+ int initialise_card();
+ int initialise_card_v1();
+ int initialise_card_v2();
+
+ int _read(uint8_t * buffer, uint32_t length);
+ int _write(const uint8_t *buffer, uint32_t length);
+ uint64_t _sd_sectors();
+ uint64_t _sectors;
+
+ void set_init_sck(uint32_t sck) { _init_sck = sck; }
+ // Note: The highest SPI clock rate is 20 MHz for MMC and 25 MHz for SD
+ void set_transfer_sck(uint32_t sck) { _transfer_sck = sck; }
+ uint32_t _init_sck;
+ uint32_t _transfer_sck;
+
+ SPI _spi;
+ DigitalOut _cs;
+ int cdv;
+ int _is_initialized;
+};
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h b/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
new file mode 100644
index 000000000..09437a256
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ * while(1) {
+ * if(temperature > 0.5) {
+ * printf("Too hot! (%f)", temperature.read());
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ AnalogIn(PinName pin) {
+ analogin_init(&_adc, pin);
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns A floating-point value representing the current input voltage, measured as a percentage
+ */
+ float read() {
+ return analogin_read(&_adc);
+ }
+
+ /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @returns
+ * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+ */
+ unsigned short read_u16() {
+ return analogin_read_u16(&_adc);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for read()
+ *
+ * The float() operator can be used as a shorthand for read() to simplify common code sequences
+ *
+ * Example:
+ * @code
+ * float x = volume.read();
+ * float x = volume;
+ *
+ * if(volume.read() > 0.25) { ... }
+ * if(volume > 0.25) { ... }
+ * @endcode
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ analogin_t _adc;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
new file mode 100644
index 000000000..0b879a72b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ * while(1) {
+ * tri = tri + 0.01;
+ * wait_us(1);
+ * if(tri == 1) {
+ * tri = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+ /** Create an AnalogOut connected to the specified pin
+ *
+ * @param AnalogOut pin to connect to (18)
+ */
+ AnalogOut(PinName pin) {
+ analogout_init(&_dac, pin);
+ }
+
+ /** Set the output voltage, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output voltage,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ analogout_write(&_dac, value);
+ }
+
+ /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @param value 16-bit unsigned short representing the output voltage,
+ * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+ */
+ void write_u16(unsigned short value) {
+ analogout_write_u16(&_dac, value);
+ }
+
+ /** Return the current output voltage setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current voltage being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read() {
+ return analogout_read(&_dac);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for write()
+ */
+ AnalogOut& operator= (float percent) {
+ write(percent);
+ return *this;
+ }
+
+ AnalogOut& operator= (AnalogOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ dac_t _dac;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h b/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
new file mode 100644
index 000000000..d1c9a9cd4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ */
+class BusIn {
+
+public:
+ /* Group: Configuration Methods */
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusIn(PinName pins[16]);
+
+ virtual ~BusIn();
+
+ /** Read the value of the input bus
+ *
+ * @returns
+ * An integer with each bit corresponding to the value read from the associated DigitalIn pin
+ */
+ int read();
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for read()
+ */
+ operator int();
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalIn & operator[] (int index);
+#endif
+
+protected:
+ DigitalIn* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusIn(const BusIn&);
+ BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
new file mode 100644
index 000000000..54328fb02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ */
+class BusInOut {
+
+public:
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusInOut(PinName pins[16]);
+
+ virtual ~BusInOut();
+
+ /* Group: Access Methods */
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalInOut pin setting
+ */
+ int read();
+
+ /** Set as an output
+ */
+ void output();
+
+ /** Set as an input
+ */
+ void input();
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ BusInOut& operator= (int v);
+ BusInOut& operator= (BusInOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalInOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+#endif
+
+protected:
+ DigitalInOut* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusInOut(const BusInOut&);
+ BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
new file mode 100644
index 000000000..1c55be07e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusOut(PinName pins[16]);
+
+ virtual ~BusOut();
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalOut pin setting
+ */
+ int read();
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ BusOut& operator= (int v);
+ BusOut& operator= (BusOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+#endif
+
+protected:
+ DigitalOut* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusOut(const BusOut&);
+ BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h b/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
new file mode 100644
index 000000000..db613f661
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() : CAN_Message() {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard) {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ * @param handle message filter handle (0 for any message)
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg, int handle = 0);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Filter out incomming messages
+ *
+ * @param id the id to filter on
+ * @param mask the mask applied to the id
+ * @param format format to filter on (Default CANAny)
+ * @param handle message filter handle (Optional)
+ *
+ * @returns
+ * 0 if filter change failed or unsupported,
+ * new filter handle if successful
+ */
+ int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+ /** Returns number of read errors to detect read overflow errors.
+ */
+ unsigned char rderror();
+
+ /** Returns number of write errors to detect write overflow errors.
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ }
+ else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ can_t _can;
+ FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h b/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
new file mode 100644
index 000000000..ebb796a3c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+ /** Create an empty chain
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ CallChain(int size = 4);
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add(void (*function)(void));
+
+ /** Add a function at the end of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+ return common_add(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_front(void (*function)(void));
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+ return common_add_front(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Get the number of functions in the chain
+ */
+ int size() const;
+
+ /** Get a function object from the chain
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ */
+ void clear();
+
+ /** Remove a function object from the chain
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ */
+ void call();
+
+#ifdef MBED_OPERATORS
+ void operator ()(void) {
+ call();
+ }
+ pFunctionPointer_t operator [](int i) const {
+ return get(i);
+ }
+#endif
+
+private:
+ void _check_size();
+ pFunctionPointer_t common_add(pFunctionPointer_t pf);
+ pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+ pFunctionPointer_t* _chain;
+ int _size;
+ int _elements;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ CallChain(const CallChain&);
+ CallChain & operator = (const CallChain&);
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
new file mode 100644
index 000000000..b089de9fa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * if(enable) {
+ * led = !led;
+ * }
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ */
+ DigitalIn(PinName pin) : gpio() {
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ * @param mode the initial mode of the pin
+ */
+ DigitalIn(PinName pin, PinMode mode) : gpio() {
+ gpio_init_in_ex(&gpio, pin, mode);
+ }
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
new file mode 100644
index 000000000..e30be0e63
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ */
+class DigitalInOut {
+
+public:
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ */
+ DigitalInOut(PinName pin) : gpio() {
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ * @param direction the initial direction of the pin
+ * @param mode the initial mode of the pin
+ * @param value the initial value of the pin if is an output
+ */
+ DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+ gpio_init_inout(&gpio, pin, direction, mode, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin if it is an output,
+ * or read the input if set as an input
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ gpio_dir(&gpio, PIN_OUTPUT);
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ gpio_dir(&gpio, PIN_INPUT);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ DigitalInOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ DigitalInOut& operator= (DigitalInOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
new file mode 100644
index 000000000..0d66f907b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ */
+ DigitalOut(PinName pin) : gpio() {
+ gpio_init_out(&gpio, pin);
+ }
+
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ * @param value the initial pin value
+ */
+ DigitalOut(PinName pin, int value) : gpio() {
+ gpio_init_out_ex(&gpio, pin, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ DigitalOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ DigitalOut& operator= (DigitalOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h b/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
new file mode 100644
index 000000000..329f4d1c7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+# define NAME_MAX 255
+typedef int mode_t;
+
+#else
+# include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+ char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ * by a FileSystemLike's opendir method. Implementations must define
+ * at least closedir, readdir and rewinddir.
+ *
+ * If a FileSystemLike class defines the opendir method, then the
+ * directories of an object of that type can be accessed by
+ * DIR *d = opendir("/example/directory") (or opendir("/example")
+ * to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ * The root directory is considered to contain all FileLike and
+ * FileSystemLike objects, so the DIR* returned by opendir("/") will
+ * reflect this.
+ */
+class DirHandle {
+
+public:
+ /** Closes the directory.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on error.
+ */
+ virtual int closedir()=0;
+
+ /** Return the directory entry at the current position, and
+ * advances the position to the next entry.
+ *
+ * @returns
+ * A pointer to a dirent structure representing the
+ * directory entry at the current position, or NULL on reaching
+ * end of directory or error.
+ */
+ virtual struct dirent *readdir()=0;
+
+ /** Resets the position to the beginning of the directory.
+ */
+ virtual void rewinddir()=0;
+
+ /** Returns the current position of the DirHandle.
+ *
+ * @returns
+ * the current position,
+ * -1 on error.
+ */
+ virtual off_t telldir() { return -1; }
+
+ /** Sets the position of the DirHandle.
+ *
+ * @param location The location to seek to. Must be a value returned by telldir.
+ */
+ virtual void seekdir(off_t location) { }
+
+ virtual ~DirHandle() {}
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+ DIR *opendir(const char*);
+ struct dirent *readdir(DIR *);
+ int closedir(DIR*);
+ void rewinddir(DIR*);
+ long telldir(DIR*);
+ void seekdir(DIR*, long);
+ int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
new file mode 100644
index 000000000..d0e59a5cf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * char buf[0x600];
+ *
+ * while(1) {
+ * int size = eth.receive();
+ * if(size > 0) {
+ * eth.read(buf, size);
+ * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ * }
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+ /** Initialise the ethernet interface.
+ */
+ Ethernet();
+
+ /** Powers the hardware down.
+ */
+ virtual ~Ethernet();
+
+ enum Mode {
+ AutoNegotiate,
+ HalfDuplex10,
+ FullDuplex10,
+ HalfDuplex100,
+ FullDuplex100
+ };
+
+ /** Writes into an outgoing ethernet packet.
+ *
+ * It will append size bytes of data to the previously written bytes.
+ *
+ * @param data An array to write.
+ * @param size The size of data.
+ *
+ * @returns
+ * The number of written bytes.
+ */
+ int write(const char *data, int size);
+
+ /** Send an outgoing ethernet packet.
+ *
+ * After filling in the data in an ethernet packet it must be send.
+ * Send will provide a new packet to write to.
+ *
+ * @returns
+ * 0 if the sending was failed,
+ * or the size of the packet successfully sent.
+ */
+ int send();
+
+ /** Recevies an arrived ethernet packet.
+ *
+ * Receiving an ethernet packet will drop the last received ethernet packet
+ * and make a new ethernet packet ready to read.
+ * If no ethernet packet is arrived it will return 0.
+ *
+ * @returns
+ * 0 if no ethernet packet is arrived,
+ * or the size of the arrived packet.
+ */
+ int receive();
+
+ /** Read from an recevied ethernet packet.
+ *
+ * After receive returnd a number bigger than 0it is
+ * possible to read bytes from this packet.
+ * Read will write up to size bytes into data.
+ *
+ * It is possible to use read multible times.
+ * Each time read will start reading after the last read byte before.
+ *
+ * @returns
+ * The number of byte read.
+ */
+ int read(char *data, int size);
+
+ /** Gives the ethernet address of the mbed.
+ *
+ * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+ */
+ void address(char *mac);
+
+ /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+ *
+ * @returns
+ * 0 if no ethernet link is pressent,
+ * 1 if an ethernet link is pressent.
+ *
+ * Example:
+ * @code
+ * // Using the Ethernet link function
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * wait(1); // Needed after startup.
+ * if (eth.link()) {
+ * printf("online\n");
+ * } else {
+ * printf("offline\n");
+ * }
+ * }
+ * @endcode
+ */
+ int link();
+
+ /** Sets the speed and duplex parameters of an ethernet link
+ *
+ * - AutoNegotiate Auto negotiate speed and duplex
+ * - HalfDuplex10 10 Mbit, half duplex
+ * - FullDuplex10 10 Mbit, full duplex
+ * - HalfDuplex100 100 Mbit, half duplex
+ * - FullDuplex100 100 Mbit, full duplex
+ *
+ * @param mode the speed and duplex mode to set the link to:
+ */
+ void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
new file mode 100644
index 000000000..88f87842c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+# define O_RDONLY 0
+# define O_WRONLY 1
+# define O_RDWR 2
+# define O_CREAT 0x0200
+# define O_TRUNC 0x0400
+# define O_APPEND 0x0008
+
+# define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+# include <sys/fcntl.h>
+# include <sys/types.h>
+# include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+
+namespace mbed {
+
+typedef enum {
+ FilePathType,
+ FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+ FileBase(const char *name, PathType t);
+
+ virtual ~FileBase();
+
+ const char* getName(void);
+ PathType getPathType(void);
+
+ static FileBase *lookup(const char *name, unsigned int len);
+
+ static FileBase *get(int n);
+
+protected:
+ static FileBase *_head;
+
+ FileBase *_next;
+ const char *_name;
+ PathType _path_type;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ FileBase(const FileBase&);
+ FileBase & operator = (const FileBase&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
new file mode 100644
index 000000000..0a98a827c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+# include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ * and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ * sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ * created by FileSystem, and wrapped up by stdio.
+ */
+class FileHandle {
+
+public:
+ /** Write the contents of a buffer to the file
+ *
+ * @param buffer the buffer to write from
+ * @param length the number of characters to write
+ *
+ * @returns
+ * The number of characters written (possibly 0) on success, -1 on error.
+ */
+ virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+ /** Close the file
+ *
+ * @returns
+ * Zero on success, -1 on error.
+ */
+ virtual int close() = 0;
+
+ /** Function read
+ * Reads the contents of the file into a buffer
+ *
+ * @param buffer the buffer to read in to
+ * @param length the number of characters to read
+ *
+ * @returns
+ * The number of characters read (zero at end of file) on success, -1 on error.
+ */
+ virtual ssize_t read(void* buffer, size_t length) = 0;
+
+ /** Check if the handle is for a interactive terminal device.
+ * If so, line buffered behaviour is used by default
+ *
+ * @returns
+ * 1 if it is a terminal,
+ * 0 otherwise
+ */
+ virtual int isatty() = 0;
+
+ /** Move the file position to a given offset from a given location.
+ *
+ * @param offset The offset from whence to move to
+ * @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+ * current file position, or SEEK_END for the end of the file.
+ *
+ * @returns
+ * new file position on success,
+ * -1 on failure or unsupported
+ */
+ virtual off_t lseek(off_t offset, int whence) = 0;
+
+ /** Flush any buffers associated with the FileHandle, ensuring it
+ * is up to date on disk
+ *
+ * @returns
+ * 0 on success or un-needed,
+ * -1 on error
+ */
+ virtual int fsync() = 0;
+
+ virtual off_t flen() {
+ /* remember our current position */
+ off_t pos = lseek(0, SEEK_CUR);
+ if(pos == -1) return -1;
+ /* seek to the end to get the file length */
+ off_t res = lseek(0, SEEK_END);
+ /* return to our old position */
+ lseek(pos, SEEK_SET);
+ return res;
+ }
+
+ virtual ~FileHandle();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
new file mode 100644
index 000000000..666575c90
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ * A file-like object is one that can be opened with fopen by
+ * fopen("/name", mode). It is intersection of the classes Base and
+ * FileHandle.
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+ /* Constructor FileLike
+ *
+ * Variables
+ * name - The name to use to open the file.
+ */
+ FileLike(const char *name);
+
+ virtual ~FileLike();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
new file mode 100644
index 000000000..3de120504
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+ FilePath(const char* file_path);
+
+ const char* fileName(void);
+
+ bool isFileSystem(void);
+ FileSystemLike* fileSystem(void);
+
+ bool isFile(void);
+ FileLike* file(void);
+ bool exists(void);
+
+private:
+ const char* file_name;
+ FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
new file mode 100644
index 000000000..6680c4cb0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ * though it by fopen("/name/filename", mode)
+ *
+ * Implementations must define at least open (the default definitions
+ * of the rest of the functions just return error values).
+ */
+class FileSystemLike : public FileBase {
+
+public:
+ /** FileSystemLike constructor
+ *
+ * @param name The name to use for the filesystem.
+ */
+ FileSystemLike(const char *name);
+
+ virtual ~FileSystemLike();
+
+ static DirHandle *opendir();
+ friend class BaseDirHandle;
+
+ /** Opens a file from the filesystem
+ *
+ * @param filename The name of the file to open.
+ * @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+ * zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+ *
+ * @returns
+ * A pointer to a FileHandle object representing the
+ * file on success, or NULL on failure.
+ */
+ virtual FileHandle *open(const char *filename, int flags) = 0;
+
+ /** Remove a file from the filesystem.
+ *
+ * @param filename the name of the file to remove.
+ * @param returns 0 on success, -1 on failure.
+ */
+ virtual int remove(const char *filename) { return -1; };
+
+ /** Rename a file in the filesystem.
+ *
+ * @param oldname the name of the file to rename.
+ * @param newname the name to rename it to.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on failure.
+ */
+ virtual int rename(const char *oldname, const char *newname) { return -1; };
+
+ /** Opens a directory in the filesystem and returns a DirHandle
+ * representing the directory stream.
+ *
+ * @param name The name of the directory to open.
+ *
+ * @returns
+ * A DirHandle representing the directory stream, or
+ * NULL on failure.
+ */
+ virtual DirHandle *opendir(const char *name) { return NULL; };
+
+ /** Creates a directory in the filesystem.
+ *
+ * @param name The name of the directory to create.
+ * @param mode The permissions to create the directory with.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on failure.
+ */
+ virtual int mkdir(const char *name, mode_t mode) { return -1; }
+
+ // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h b/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
new file mode 100644
index 000000000..1ae492283
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include <string.h>
+
+namespace mbed {
+
+typedef void (*pvoidf_t)(void);
+
+/** A class for storing and calling a pointer to a static or member void function
+ */
+class FunctionPointer {
+public:
+
+ /** Create a FunctionPointer, attaching a static function
+ *
+ * @param function The void static function to attach (default is none)
+ */
+ FunctionPointer(void (*function)(void) = 0);
+
+ /** Create a FunctionPointer, attaching a member function
+ *
+ * @param object The object pointer to invoke the member function on (i.e. the this pointer)
+ * @param function The address of the void member function to attach
+ */
+ template<typename T>
+ FunctionPointer(T *object, void (T::*member)(void)) {
+ attach(object, member);
+ }
+
+ /** Attach a static function
+ *
+ * @param function The void static function to attach (default is none)
+ */
+ void attach(void (*function)(void) = 0);
+
+ /** Attach a member function
+ *
+ * @param object The object pointer to invoke the member function on (i.e. the this pointer)
+ * @param function The address of the void member function to attach
+ */
+ template<typename T>
+ void attach(T *object, void (T::*member)(void)) {
+ _object = static_cast<void*>(object);
+ memcpy(_member, (char*)&member, sizeof(member));
+ _membercaller = &FunctionPointer::membercaller<T>;
+ _function = 0;
+ }
+
+ /** Call the attached static or member function
+ */
+ void call();
+
+ pvoidf_t get_function() const {
+ return (pvoidf_t)_function;
+ }
+
+#ifdef MBED_OPERATORS
+ void operator ()(void);
+#endif
+
+private:
+ template<typename T>
+ static void membercaller(void *object, char *member) {
+ T* o = static_cast<T*>(object);
+ void (T::*m)(void);
+ memcpy((char*)&m, member, sizeof(m));
+ (o->*m)();
+ }
+
+ void (*_function)(void); // static function pointer - 0 if none attached
+ void *_object; // object this pointer - 0 if none attached
+ char _member[16]; // raw member function pointer storage - converted back by registered _membercaller
+ void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h b/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
new file mode 100644
index 000000000..bd7cf1223
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ * int address = 0x62;
+ * char data[2];
+ * i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+ enum RxStatus {
+ NoData,
+ MasterGeneralCall,
+ MasterWrite,
+ MasterRead
+ };
+
+ enum Acknowledge {
+ NoACK = 0,
+ ACK = 1
+ };
+
+ /** Create an I2C Master interface, connected to the specified pins
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2C(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Read from an I2C slave
+ *
+ * Performs a complete read transaction. The bottom bit of
+ * the address is forced to 1 to indicate a read.
+ *
+ * @param address 8-bit I2C slave address [ addr | 1 ]
+ * @param data Pointer to the byte-array to read data in to
+ * @param length Number of bytes to read
+ * @param repeated Repeated start, true - don't send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int read(int address, char *data, int length, bool repeated = false);
+
+ /** Read a single byte from the I2C bus
+ *
+ * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+ *
+ * @returns
+ * the byte read
+ */
+ int read(int ack);
+
+ /** Write to an I2C slave
+ *
+ * Performs a complete write transaction. The bottom bit of
+ * the address is forced to 0 to indicate a write.
+ *
+ * @param address 8-bit I2C slave address [ addr | 0 ]
+ * @param data Pointer to the byte-array data to send
+ * @param length Number of bytes to send
+ * @param repeated Repeated start, true - do not send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int write(int address, const char *data, int length, bool repeated = false);
+
+ /** Write single byte out on the I2C bus
+ *
+ * @param data data to write out on bus
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Creates a start condition on the I2C bus
+ */
+
+ void start(void);
+
+ /** Creates a stop condition on the I2C bus
+ */
+ void stop(void);
+
+protected:
+ void aquire();
+
+ i2c_t _i2c;
+ static I2C *_owner;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h b/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
new file mode 100644
index 000000000..738faea27
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ * char buf[10];
+ * char msg[] = "Slave!";
+ *
+ * slave.address(0xA0);
+ * while (1) {
+ * int i = slave.receive();
+ * switch (i) {
+ * case I2CSlave::ReadAddressed:
+ * slave.write(msg, strlen(msg) + 1); // Includes null char
+ * break;
+ * case I2CSlave::WriteGeneral:
+ * slave.read(buf, 10);
+ * printf("Read G: %s\n", buf);
+ * break;
+ * case I2CSlave::WriteAddressed:
+ * slave.read(buf, 10);
+ * printf("Read A: %s\n", buf);
+ * break;
+ * }
+ * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
+ * }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+ enum RxStatus {
+ NoData = 0,
+ ReadAddressed = 1,
+ WriteGeneral = 2,
+ WriteAddressed = 3
+ };
+
+ /** Create an I2C Slave interface, connected to the specified pins.
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2CSlave(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Checks to see if this I2C Slave has been addressed.
+ *
+ * @returns
+ * A status indicating if the device has been addressed, and how
+ * - NoData - the slave has not been addressed
+ * - ReadAddressed - the master has requested a read from this slave
+ * - WriteAddressed - the master is writing to this slave
+ * - WriteGeneral - the master is writing to all slave
+ */
+ int receive(void);
+
+ /** Read from an I2C master.
+ *
+ * @param data pointer to the byte array to read data in to
+ * @param length maximum number of bytes to read
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int read(char *data, int length);
+
+ /** Read a single byte from an I2C master.
+ *
+ * @returns
+ * the byte read
+ */
+ int read(void);
+
+ /** Write to an I2C master.
+ *
+ * @param data pointer to the byte array to be transmitted
+ * @param length the number of bytes to transmite
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int write(const char *data, int length);
+
+ /** Write a single byte to an I2C master.
+ *
+ * @data the byte to write
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Sets the I2C slave address.
+ *
+ * @param address The address to set for the slave (ignoring the least
+ * signifcant bit). If set to 0, the slave will only respond to the
+ * general call address.
+ */
+ void address(int address);
+
+ /** Reset the I2C slave back into the known ready receiving state.
+ */
+ void stop(void);
+
+protected:
+ i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h b/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
new file mode 100644
index 000000000..88bc4308e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ * printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ * event.rise(&trigger);
+ * while(1) {
+ * led = !led;
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+ /** Create an InterruptIn connected to the specified pin
+ *
+ * @param pin InterruptIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ InterruptIn(PinName pin);
+ virtual ~InterruptIn();
+
+ int read();
+#ifdef MBED_OPERATORS
+ operator int();
+
+#endif
+
+ /** Attach a function to call when a rising edge occurs on the input
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ */
+ void rise(void (*fptr)(void));
+
+ /** Attach a member function to call when a rising edge occurs on the input
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void rise(T* tptr, void (T::*mptr)(void)) {
+ _rise.attach(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ }
+
+ /** Attach a function to call when a falling edge occurs on the input
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ */
+ void fall(void (*fptr)(void));
+
+ /** Attach a member function to call when a falling edge occurs on the input
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void fall(T* tptr, void (T::*mptr)(void)) {
+ _fall.attach(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Enable IRQ. This method depends on hw implementation, might enable one
+ * port interrupts. For further information, check gpio_irq_enable().
+ */
+ void enable_irq();
+
+ /** Disable IRQ. This method depends on hw implementation, might disable one
+ * port interrupts. For further information, check gpio_irq_disable().
+ */
+ void disable_irq();
+
+ static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+ gpio_t gpio;
+ gpio_irq_t gpio_irq;
+
+ FunctionPointer _rise;
+ FunctionPointer _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h b/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
new file mode 100644
index 000000000..4959a6469
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
@@ -0,0 +1,143 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+ /** Return the only instance of this class
+ */
+ static InterruptManager* get();
+
+ /** Destroy the current instance of the interrupt manager
+ */
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ // We declare the copy contructor and the assignment operator, but we don't
+ // implement them. This way, if someone tries to copy/assign our instance,
+ // he will get an error at compile time.
+ InterruptManager(const InterruptManager&);
+ InterruptManager& operator =(const InterruptManager&);
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+ static void static_irq_helper();
+
+ CallChain* _chains[NVIC_NUM_VECTORS];
+ static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h b/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
new file mode 100644
index 000000000..9eb61a4b9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+ LocalFileHandle(FILEHANDLE fh);
+
+ virtual int close();
+
+ virtual ssize_t write(const void *buffer, size_t length);
+
+ virtual ssize_t read(void *buffer, size_t length);
+
+ virtual int isatty();
+
+ virtual off_t lseek(off_t position, int whence);
+
+ virtual int fsync();
+
+ virtual off_t flen();
+
+protected:
+ FILEHANDLE _fh;
+ int pos;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ * This allows programs to read and write files on the same disk drive that is used to program the
+ * mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ * read and write files.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local"); // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing
+ * fprintf(fp, "Hello World!");
+ * fclose(fp);
+ * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system
+ *
+ * DIR *d = opendir("/local"); // Opens the root directory of the local file system
+ * struct dirent *p;
+ * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system
+ * printf("%s\n", p->d_name); // to stdout.
+ * }
+ * closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ * If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ * on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ * The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+
+public:
+ LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+ }
+
+ virtual FileHandle *open(const char* name, int flags);
+ virtual int remove(const char *filename);
+ virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h b/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
new file mode 100644
index 000000000..44686325c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ * Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn p(Port2, 0x0000003F); // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ * while(1) {
+ * int pins = p.read();
+ * if(pins) {
+ * ind = 1;
+ * } else {
+ * ind = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+ /** Create an PortIn, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortIn(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_INPUT);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ port_mode(&_port, mode);
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
new file mode 100644
index 000000000..cca755126
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ */
+class PortInOut {
+public:
+
+ /** Create an PortInOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_INPUT);
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding port pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ port_dir(&_port, PIN_OUTPUT);
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ port_dir(&_port, PIN_INPUT);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ port_mode(&_port, mode);
+ }
+
+ /** A shorthand for write()
+ */
+ PortInOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortInOut& operator= (PortInOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
new file mode 100644
index 000000000..bab5fe0c6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ * while(1) {
+ * ledport = LED_MASK;
+ * wait(1);
+ * ledport = 0;
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+ /** Create an PortOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortOut(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_OUTPUT);
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding PortOut pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated PortOut pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** A shorthand for write()
+ */
+ PortOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortOut& operator= (PortOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h b/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
new file mode 100644
index 000000000..9e8c0bdf2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = led + 0.01;
+ * wait(0.2);
+ * if(led == 1.0) {
+ * led = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ *
+ * @note
+ * On the LPC1768 and LPC2368, the PWMs all share the same
+ * period - if you change the period for one, you change it for all.
+ * Although routines that change the period maintain the duty cycle
+ * for its PWM, all other PWMs will require their duty cycle to be
+ * refreshed.
+ */
+class PwmOut {
+
+public:
+
+ /** Create a PwmOut connected to the specified pin
+ *
+ * @param pin PwmOut pin to connect to
+ */
+ PwmOut(PinName pin) {
+ pwmout_init(&_pwm, pin);
+ }
+
+ /** Set the ouput duty-cycle, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output duty-cycle,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ pwmout_write(&_pwm, value);
+ }
+
+ /** Return the current output duty-cycle setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current duty-cycle being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous <write>.
+ */
+ float read() {
+ return pwmout_read(&_pwm);
+ }
+
+ /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+ *
+ * @note
+ * The resolution is currently in microseconds; periods smaller than this
+ * will be set to zero.
+ */
+ void period(float seconds) {
+ pwmout_period(&_pwm, seconds);
+ }
+
+ /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+ */
+ void period_ms(int ms) {
+ pwmout_period_ms(&_pwm, ms);
+ }
+
+ /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+ */
+ void period_us(int us) {
+ pwmout_period_us(&_pwm, us);
+ }
+
+ /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+ */
+ void pulsewidth(float seconds) {
+ pwmout_pulsewidth(&_pwm, seconds);
+ }
+
+ /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+ */
+ void pulsewidth_ms(int ms) {
+ pwmout_pulsewidth_ms(&_pwm, ms);
+ }
+
+ /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+ */
+ void pulsewidth_us(int us) {
+ pwmout_pulsewidth_us(&_pwm, us);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A operator shorthand for write()
+ */
+ PwmOut& operator= (float value) {
+ write(value);
+ return *this;
+ }
+
+ PwmOut& operator= (PwmOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h b/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
new file mode 100644
index 000000000..a5182bb64
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+ /** Create a RawSerial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ RawSerial(PinName tx, PinName rx);
+
+ /** Write a char to the serial port
+ *
+ * @param c The char to write
+ *
+ * @returns The written char or -1 if an error occured
+ */
+ int putc(int c);
+
+ /** Read a char from the serial port
+ *
+ * @returns The char read from the serial port
+ */
+ int getc();
+
+ /** Write a string to the serial port
+ *
+ * @param str The string to write
+ *
+ * @returns 0 if the write succeeds, EOF for error
+ */
+ int puts(const char *str);
+
+ int printf(const char *format, ...);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h b/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
new file mode 100644
index 000000000..7fa1a6be8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ *
+ * int main() {
+ * int response = device.write(0xFF);
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+ /** Create a SPI master connected to the specified pins
+ *
+ * Pin Options:
+ * (5, 6, 7) or (11, 12, 13)
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ */
+ SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Write to the SPI Slave and return the response
+ *
+ * @param value Data to be sent to the SPI slave
+ *
+ * @returns
+ * Response from the SPI slave
+ */
+ virtual int write(int value);
+
+public:
+ virtual ~SPI() {
+ }
+
+protected:
+ spi_t _spi;
+
+ void aquire(void);
+ static SPI *_owner;
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h b/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
new file mode 100644
index 000000000..d06c7e1b4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ * device.reply(0x00); // Prime SPI with first reply
+ * while(1) {
+ * if(device.receive()) {
+ * int v = device.read(); // Read byte from master
+ * v = (v + 1) % 0x100; // Add one to it, modulo 256
+ * device.reply(v); // Make this the next reply
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+ /** Create a SPI slave connected to the specified pins
+ *
+ * Pin Options:
+ * (5, 6, 7i, 8) or (11, 12, 13, 14)
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ * @param name (optional) A string to identify the object
+ */
+ SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Polls the SPI to see if data has been received
+ *
+ * @returns
+ * 0 if no data,
+ * 1 otherwise
+ */
+ int receive(void);
+
+ /** Retrieve data from receive buffer as slave
+ *
+ * @returns
+ * the data in the receive buffer
+ */
+ int read(void);
+
+ /** Fill the transmission buffer with the value to be written out
+ * as slave on the next received message from the master.
+ *
+ * @param value the data to be transmitted next
+ */
+ void reply(int value);
+
+protected:
+ spi_t _spi;
+
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
new file mode 100644
index 000000000..edd762d01
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+ /** Create a Serial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, const char *name=NULL);
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h b/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
new file mode 100644
index 000000000..07bc4b463
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ */
+class SerialBase {
+
+public:
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate);
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Forced1,
+ Forced0
+ };
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq
+ };
+
+ enum Flow {
+ Disabled = 0,
+ RTS,
+ CTS,
+ RTSCTS
+ };
+
+ /** Set the transmission format used by the serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+ * @param stop The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable();
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable();
+
+ /** Attach a function to call whenever a serial interrupt is generated
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ }
+ }
+
+ /** Generate a break condition on the serial line
+ */
+ void send_break();
+
+#if DEVICE_SERIAL_FC
+ /** Set the flow control type on the serial port
+ *
+ * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+ * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+ * @param flow2 the second flow control pin (CTS for RTSCTS)
+ */
+ void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+ static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+protected:
+ SerialBase(PinName tx, PinName rx);
+ virtual ~SerialBase() {
+ }
+
+ int _base_getc();
+ int _base_putc(int c);
+
+ serial_t _serial;
+ FunctionPointer _irq[2];
+ int _baud;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
new file mode 100644
index 000000000..a57053e67
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+extern void mbed_set_unbuffered_stream(FILE *_file);
+extern int mbed_getc(FILE *_file);
+extern char* mbed_gets(char *s, int size, FILE *_file);
+
+class Stream : public FileLike {
+
+public:
+ Stream(const char *name=NULL);
+ virtual ~Stream();
+
+ int putc(int c);
+ int puts(const char *s);
+ int getc();
+ char *gets(char *s, int size);
+ int printf(const char* format, ...);
+ int scanf(const char* format, ...);
+
+ operator std::FILE*() {return _file;}
+
+protected:
+ virtual int close();
+ virtual ssize_t write(const void* buffer, size_t length);
+ virtual ssize_t read(void* buffer, size_t length);
+ virtual off_t lseek(off_t offset, int whence);
+ virtual int isatty();
+ virtual int fsync();
+ virtual off_t flen();
+
+ virtual int _putc(int c) = 0;
+ virtual int _getc() = 0;
+
+ std::FILE *_file;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ Stream(const Stream&);
+ Stream & operator = (const Stream&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
new file mode 100644
index 000000000..43b70cbfc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ * You can use as many seperate Ticker objects as you require.
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ * flip = !flip;
+ * }
+ *
+ * int main() {
+ * timer.attach(&attime, 5);
+ * while(1) {
+ * if(flip == 0) {
+ * led1 = !led1;
+ * } else {
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param fptr pointer to the function to be called
+ * @param t the time between calls in seconds
+ */
+ void attach(void (*fptr)(void), float t) {
+ attach_us(fptr, t * 1000000.0f);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param t the time between calls in seconds
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), float t) {
+ attach_us(tptr, mptr, t * 1000000.0f);
+ }
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param fptr pointer to the function to be called
+ * @param t the time between calls in micro-seconds
+ */
+ void attach_us(void (*fptr)(void), timestamp_t t) {
+ _function.attach(fptr);
+ setup(t);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param t the time between calls in micro-seconds
+ */
+ template<typename T>
+ void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
+ _function.attach(tptr, mptr);
+ setup(t);
+ }
+
+ virtual ~Ticker() {
+ detach();
+ }
+
+ /** Detach the function
+ */
+ void detach();
+
+protected:
+ void setup(timestamp_t t);
+ virtual void handler();
+
+protected:
+ timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ FunctionPointer _function; /**< Callback. */
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
new file mode 100644
index 000000000..e145d9a77
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ * on = 0;
+ * }
+ *
+ * int main() {
+ * timeout.attach(&attimeout, 5);
+ * while(on) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+ virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h b/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
new file mode 100644
index 000000000..aedf0377e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ * timer.start();
+ * begin = timer.read_us();
+ * led = !led;
+ * end = timer.read_us();
+ * printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+ Timer();
+
+ /** Start the timer
+ */
+ void start();
+
+ /** Stop the timer
+ */
+ void stop();
+
+ /** Reset the timer to 0.
+ *
+ * If it was already counting, it will continue
+ */
+ void reset();
+
+ /** Get the time passed in seconds
+ */
+ float read();
+
+ /** Get the time passed in mili-seconds
+ */
+ int read_ms();
+
+ /** Get the time passed in micro-seconds
+ */
+ int read_us();
+
+#ifdef MBED_OPERATORS
+ operator float();
+#endif
+
+protected:
+ int slicetime();
+ int _running; // whether the timer is running
+ unsigned int _start; // the start time of the latest slice
+ int _time; // any accumulated time from previous slices
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h b/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
new file mode 100644
index 000000000..4ec7056a7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+*/
+class TimerEvent {
+public:
+ TimerEvent();
+
+ /** The handler registered with the underlying timer interrupt
+ */
+ static void irq(uint32_t id);
+
+ /** Destruction removes it...
+ */
+ virtual ~TimerEvent();
+
+protected:
+ // The handler called to service the timer event of the derived class
+ virtual void handler() = 0;
+
+ // insert in to linked list
+ void insert(timestamp_t timestamp);
+
+ // remove from linked list, if in it
+ void remove();
+
+ ticker_event_t event;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h b/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
new file mode 100644
index 000000000..e427250e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+ CANStandard = 0,
+ CANExtended = 1,
+ CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+ CANData = 0,
+ CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+ unsigned int id; // 29 bit identifier
+ unsigned char data[8]; // Data field
+ unsigned char len; // Length of data field in bytes
+ CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+ CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
new file mode 100644
index 000000000..51b044d11
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 97
+
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "mbed_error.h"
+#include "mbed_interface.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+#include "RawSerial.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
new file mode 100644
index 000000000..1bcfb092b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ * This function is active only if NDEBUG is not defined prior to including this
+ * assert header file.
+ * In case of MBED_ASSERT failing condition, the assertation message is printed
+ * to stderr and mbed_die() is called.
+ * @param expr Expresion to be checked.
+ * @param file File where assertation failed.
+ * @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr) \
+do { \
+ if (!(expr)) { \
+ mbed_assert_internal(#expr, __FILE__, __LINE__); \
+ } \
+} while (0)
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
new file mode 100644
index 000000000..2c8a34673
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+ if (condition == 1) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+ }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
new file mode 100644
index 000000000..3a403586d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ * #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ * error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
new file mode 100644
index 000000000..a93a4d33d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ * @returns
+ * 1 if interface is connected,
+ * 0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ * This is a weak function that can be overwritten if required
+ *
+ * @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ * @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h b/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
new file mode 100644
index 000000000..85e44e57b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#define MBED_OPERATORS 1
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h b/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
new file mode 100644
index 000000000..565897366
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ * while(1) {
+ * time_t seconds = time(NULL);
+ *
+ * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ * printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ * char buffer[32];
+ * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ * printf("Time as a custom formatted string = %s", buffer);
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * Do not call this function from an interrupt while an RTC read/write operation may be occurring
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h b/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
new file mode 100644
index 000000000..279f67160
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+inline int __semihost(int reason, const void *arg) {
+ return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+# define AngelSWI 0xAB
+# define AngelSWIInsn "bkpt"
+# define AngelSWIAsm bkpt
+#else
+# define AngelSWI 0x123456
+# define AngelSWIInsn "swi"
+# define AngelSWIAsm swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+ int value;
+
+ asm volatile (
+ "mov r0, %1" "\n\t"
+ "mov r1, %2" "\n\t"
+ AngelSWIInsn " %a3" "\n\t"
+ "mov %0, r0"
+ : "=r" (value) /* output operands */
+ : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
+ );
+
+ return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h b/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
new file mode 100644
index 000000000..b140643b3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+#if defined (__ICCARM__)
+# define WEAK __weak
+# define PACKED __packed
+#else
+# define WEAK __attribute__((weak))
+# define PACKED __attribute__((packed))
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h b/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
new file mode 100644
index 000000000..03c27141e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ * while (1) {
+ * heartbeat = 1;
+ * wait(0.5);
+ * heartbeat = 0;
+ * wait(0.5);
+ * }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ * the accuracy of single precision floating point).
+ *
+ * @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ * @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ * @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
new file mode 100644
index 000000000..ea67cbcb8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::~BusIn() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+int BusIn::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+void BusIn::mode(PinMode pull) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+}
+
+#ifdef MBED_OPERATORS
+BusIn::operator int() {
+ return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+#endif
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
new file mode 100644
index 000000000..5575f90d4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::~BusInOut() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusInOut::write(int value) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+}
+
+int BusInOut::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+void BusInOut::output() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->output();
+ }
+ }
+}
+
+void BusInOut::input() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->input();
+ }
+ }
+}
+
+void BusInOut::mode(PinMode pull) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+}
+
+#ifdef MBED_OPERATORS
+BusInOut& BusInOut::operator= (int v) {
+ write(v);
+ return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+ write(rhs.read());
+ return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusInOut::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
new file mode 100644
index 000000000..4277c5727
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::~BusOut() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusOut::write(int value) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+}
+
+int BusOut::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+#ifdef MBED_OPERATORS
+BusOut& BusOut::operator= (int v) {
+ write(v);
+ return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+ write(rhs.read());
+ return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusOut::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
new file mode 100644
index 000000000..407e00bf1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+ can_init(&_can, rd, td);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+ can_irq_free(&_can);
+ can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+ return can_frequency(&_can, f);
+}
+
+int CAN::write(CANMessage msg) {
+ return can_write(&_can, msg, 0);
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+ return can_read(&_can, &msg, handle);
+}
+
+void CAN::reset() {
+ can_reset(&_can);
+}
+
+unsigned char CAN::rderror() {
+ return can_rderror(&_can);
+}
+
+unsigned char CAN::tderror() {
+ return can_tderror(&_can);
+}
+
+void CAN::monitor(bool silent) {
+ can_monitor(&_can, (silent) ? 1 : 0);
+}
+
+int CAN::mode(Mode mode) {
+ return can_mode(&_can, (CanMode)mode);
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+ return can_filter(&_can, id, mask, format, handle);
+}
+
+void CAN::attach(void (*fptr)(void), IrqType type) {
+ if (fptr) {
+ _irq[(CanIrqType)type].attach(fptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ } else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+ CAN *handler = (CAN*)id;
+ handler->_irq[type].call();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
new file mode 100644
index 000000000..e95090305
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
@@ -0,0 +1,90 @@
+#include "CallChain.h"
+#include "cmsis.h"
+
+namespace mbed {
+
+CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
+ _chain = new pFunctionPointer_t[size]();
+}
+
+CallChain::~CallChain() {
+ clear();
+ delete _chain;
+}
+
+pFunctionPointer_t CallChain::add(void (*function)(void)) {
+ return common_add(new FunctionPointer(function));
+}
+
+pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
+ return common_add_front(new FunctionPointer(function));
+}
+
+int CallChain::size() const {
+ return _elements;
+}
+
+pFunctionPointer_t CallChain::get(int i) const {
+ if (i < 0 || i >= _elements)
+ return NULL;
+ return _chain[i];
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+ for (int i = 0; i < _elements; i++)
+ if (f == _chain[i])
+ return i;
+ return -1;
+}
+
+void CallChain::clear() {
+ for(int i = 0; i < _elements; i ++) {
+ delete _chain[i];
+ _chain[i] = NULL;
+ }
+ _elements = 0;
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+ int i;
+
+ if ((i = find(f)) == -1)
+ return false;
+ if (i != _elements - 1)
+ memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
+ delete f;
+ _elements --;
+ return true;
+}
+
+void CallChain::call() {
+ for(int i = 0; i < _elements; i++)
+ _chain[i]->call();
+}
+
+void CallChain::_check_size() {
+ if (_elements < _size)
+ return;
+ _size = (_size < 4) ? 4 : _size + 4;
+ pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
+ memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
+ delete _chain;
+ _chain = new_chain;
+}
+
+pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
+ _check_size();
+ _chain[_elements] = pf;
+ _elements ++;
+ return pf;
+}
+
+pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
+ _check_size();
+ memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
+ _chain[0] = pf;
+ _elements ++;
+ return pf;
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
new file mode 100644
index 000000000..279a88b8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+ ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+ ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+ return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+ return ethernet_send();
+}
+
+int Ethernet::receive() {
+ return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+ return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+ return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+ return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+ int speed = -1;
+ int duplex = 0;
+
+ switch(mode) {
+ case AutoNegotiate : speed = -1; duplex = 0; break;
+ case HalfDuplex10 : speed = 0; duplex = 0; break;
+ case FullDuplex10 : speed = 0; duplex = 1; break;
+ case HalfDuplex100 : speed = 1; duplex = 0; break;
+ case FullDuplex100 : speed = 1; duplex = 1; break;
+ }
+
+ ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
new file mode 100644
index 000000000..fce113d88
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+ _name(name),
+ _path_type(t) {
+ if (name != NULL) {
+ // put this object at head of the list
+ _next = _head;
+ _head = this;
+ } else {
+ _next = NULL;
+ }
+}
+
+FileBase::~FileBase() {
+ if (_name != NULL) {
+ // remove this object from the list
+ if (_head == this) { // first in the list, so just drop me
+ _head = _next;
+ } else { // find the object before me, then drop me
+ FileBase *p = _head;
+ while (p->_next != this) {
+ p = p->_next;
+ }
+ p->_next = _next;
+ }
+ }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+ FileBase *p = _head;
+ while (p != NULL) {
+ /* Check that p->_name matches name and is the correct length */
+ if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+ return p;
+ }
+ p = p->_next;
+ }
+ return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+ FileBase *p = _head;
+ int m = 0;
+ while (p != NULL) {
+ if (m == n) return p;
+
+ m++;
+ p = p->_next;
+ }
+ return NULL;
+}
+
+const char* FileBase::getName(void) {
+ return _name;
+}
+
+PathType FileBase::getPathType(void) {
+ return _path_type;
+}
+
+} // namespace mbed
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
new file mode 100644
index 000000000..da13ead14
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
new file mode 100644
index 000000000..09147a269
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+ if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+ const char* file_system = &file_path[1];
+ file_name = file_system;
+ int len = 0;
+ while (true) {
+ char c = *file_name;
+ if (c == '/') { // end of object name
+ file_name++; // point to one char after the '/'
+ break;
+ }
+ if (c == 0) { // end of object name, with no filename
+ break;
+ }
+ len++;
+ file_name++;
+ }
+
+ fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+ return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+ if (NULL == fb)
+ return false;
+ return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+ if (isFileSystem()) {
+ return (FileSystemLike*)fb;
+ }
+ return NULL;
+}
+
+bool FilePath::isFile(void) {
+ if (NULL == fb)
+ return false;
+ return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+ if (isFile()) {
+ return (FileLike*)fb;
+ }
+ return NULL;
+}
+
+bool FilePath::exists(void) {
+ return fb != NULL;
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
new file mode 100644
index 000000000..df5d86da8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+ /*
+ We keep track of our current location as the n'th object in the
+ FileSystemLike list. Using a Base* instead would cause problems if that
+ object were to be destroyed between readdirs.
+ Using this method does mean though that destroying/creating objects can
+ give unusual results from readdir.
+ */
+ off_t n;
+ struct dirent cur_entry;
+
+ BaseDirHandle() : n(0), cur_entry() {
+ }
+
+ virtual int closedir() {
+ delete this;
+ return 0;
+ }
+
+ virtual struct dirent *readdir() {
+ FileBase *ptr = FileBase::get(n);
+ if (ptr == NULL) return NULL;
+
+ /* Increment n, so next readdir gets the next item */
+ n++;
+
+ /* Setup cur entry and return a pointer to it */
+ std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+ return &cur_entry;
+ }
+
+ virtual off_t telldir() {
+ return n;
+ }
+
+ virtual void seekdir(off_t offset) {
+ n = offset;
+ }
+
+ virtual void rewinddir() {
+ n = 0;
+ }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+ return new BaseDirHandle();
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
new file mode 100644
index 000000000..7c43916c7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+FunctionPointer::FunctionPointer(void (*function)(void)): _function(),
+ _object(),
+ _membercaller() {
+ attach(function);
+}
+
+void FunctionPointer::attach(void (*function)(void)) {
+ _function = function;
+ _object = 0;
+}
+
+void FunctionPointer::call(void) {
+ if (_function) {
+ _function();
+ } else if (_object) {
+ _membercaller(_object, _member);
+ }
+}
+
+#ifdef MBED_OPERATORS
+void FunctionPointer::operator ()(void) {
+ call();
+}
+#endif
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
new file mode 100644
index 000000000..fb1d03048
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+
+I2C::I2C(PinName sda, PinName scl) : _i2c(), _hz(100000) {
+ // The init function also set the frequency to 100000
+ i2c_init(&_i2c, sda, scl);
+
+ // Used to avoid unnecessary frequency updates
+ _owner = this;
+}
+
+void I2C::frequency(int hz) {
+ _hz = hz;
+
+ // We want to update the frequency even if we are already the bus owners
+ i2c_frequency(&_i2c, _hz);
+
+ // Updating the frequency of the bus we become the owners of it
+ _owner = this;
+}
+
+void I2C::aquire() {
+ if (_owner != this) {
+ i2c_frequency(&_i2c, _hz);
+ _owner = this;
+ }
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int written = i2c_write(&_i2c, address, data, length, stop);
+
+ return length != written;
+}
+
+int I2C::write(int data) {
+ return i2c_byte_write(&_i2c, data);
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int read = i2c_read(&_i2c, address, data, length, stop);
+
+ return length != read;
+}
+
+int I2C::read(int ack) {
+ if (ack) {
+ return i2c_byte_read(&_i2c, 0);
+ } else {
+ return i2c_byte_read(&_i2c, 1);
+ }
+}
+
+void I2C::start(void) {
+ i2c_start(&_i2c);
+}
+
+void I2C::stop(void) {
+ i2c_stop(&_i2c);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
new file mode 100644
index 000000000..43940939c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+ i2c_init(&_i2c, sda, scl);
+ i2c_frequency(&_i2c, 100000);
+ i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+ i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+ int addr = (address & 0xFF) | 1;
+ i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+ return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+ return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+ return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+ return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+ return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+ i2c_stop(&_i2c);
+}
+
+}
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
new file mode 100644
index 000000000..8692124c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+ gpio_irq(),
+ _rise(),
+ _fall() {
+ gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+ gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+ gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+ return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+}
+
+void InterruptIn::rise(void (*fptr)(void)) {
+ if (fptr) {
+ _rise.attach(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ } else {
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+ }
+}
+
+void InterruptIn::fall(void (*fptr)(void)) {
+ if (fptr) {
+ _fall.attach(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ } else {
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+ }
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+ InterruptIn *handler = (InterruptIn*)id;
+ switch (event) {
+ case IRQ_RISE: handler->_rise.call(); break;
+ case IRQ_FALL: handler->_fall.call(); break;
+ case IRQ_NONE: break;
+ }
+}
+
+void InterruptIn::enable_irq() {
+ gpio_irq_enable(&gpio_irq);
+}
+
+void InterruptIn::disable_irq() {
+ gpio_irq_disable(&gpio_irq);
+}
+
+#ifdef MBED_OPERATORS
+InterruptIn::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
new file mode 100644
index 000000000..e92fb68d4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
@@ -0,0 +1,93 @@
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "InterruptManager.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE 4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+ if (NULL == _instance)
+ _instance = new InterruptManager();
+ return _instance;
+}
+
+InterruptManager::InterruptManager() {
+ memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+ // Not a good idea to call this unless NO interrupt at all
+ // is under the control of the handler; otherwise, a system crash
+ // is very likely to occur
+ if (NULL != _instance) {
+ delete _instance;
+ _instance = (InterruptManager*)NULL;
+ }
+}
+
+InterruptManager::~InterruptManager() {
+ for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+ if (NULL != _chains[i])
+ delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos]) {
+ _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+ _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+ return true;
+ }
+ return false;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos])
+ return false;
+ if (!_chains[irq_pos]->remove(handler))
+ return false;
+ // If there's a single function left in the chain, swith the interrupt vector
+ // to call that function directly. This way we save both time and space.
+ if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
+ NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
+ delete _chains[irq_pos];
+ _chains[irq_pos] = (CallChain*) NULL;
+ }
+ return true;
+}
+
+void InterruptManager::irq_helper() {
+ _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+ return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+ InterruptManager::get()->irq_helper();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
new file mode 100644
index 000000000..9505d91a9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+ unsigned char hr; /* Hours [0..23] */
+ unsigned char min; /* Minutes [0..59] */
+ unsigned char sec; /* Seconds [0..59] */
+ unsigned char day; /* Day [1..31] */
+ unsigned char mon; /* Month [1..12] */
+ unsigned short year; /* Year [1980..2107] */
+} FTIME;
+
+typedef struct { /* File Search info record */
+ char name[32]; /* File name */
+ long size; /* File size in bytes */
+ int fileID; /* System File Identification */
+ FTIME create_time; /* Date & time file was created */
+ FTIME write_time; /* Date & time of last write */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+ unsigned param[4];
+
+ param[0] = (unsigned long)pattern;
+ param[1] = (unsigned long)strlen(pattern);
+ param[2] = (unsigned long)info;
+ param[3] = (unsigned long)sizeof(XFINFO);
+
+ return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R 0
+#define OPEN_B 1
+#define OPEN_PLUS 2
+#define OPEN_W 4
+#define OPEN_A 8
+#define OPEN_INVALID -1
+
+int posix_to_semihost_open_flags(int flags) {
+ /* POSIX flags -> semihosting open mode */
+ int openmode;
+ if (flags & O_RDWR) {
+ /* a plus mode */
+ openmode = OPEN_PLUS;
+ if (flags & O_APPEND) {
+ openmode |= OPEN_A;
+ } else if (flags & O_TRUNC) {
+ openmode |= OPEN_W;
+ } else {
+ openmode |= OPEN_R;
+ }
+ } else if (flags & O_WRONLY) {
+ /* write or append */
+ if (flags & O_APPEND) {
+ openmode = OPEN_A;
+ } else {
+ openmode = OPEN_W;
+ }
+ } else if (flags == O_RDONLY) {
+ /* read mode */
+ openmode = OPEN_R;
+ } else {
+ /* invalid flags */
+ openmode = OPEN_INVALID;
+ }
+
+ return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return (FILEHANDLE)NULL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return (FILEHANDLE)NULL;
+ }
+
+ return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+}
+
+int LocalFileHandle::close() {
+ int retval = semihost_close(_fh);
+ delete this;
+ return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+ ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+ n = length - n; // number of characters written
+ pos += n;
+ return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+ ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+ n = length - n; // number of characters read
+ pos += n;
+ return n;
+}
+
+int LocalFileHandle::isatty() {
+ return semihost_istty(_fh);
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+ if (whence == SEEK_CUR) {
+ position += pos;
+ } else if (whence == SEEK_END) {
+ position += semihost_flen(_fh);
+ } /* otherwise SEEK_SET, so position is fine */
+
+ /* Always seems to return -1, so just ignore for now. */
+ semihost_seek(_fh, position);
+ pos = position;
+ return position;
+}
+
+int LocalFileHandle::fsync() {
+ return semihost_ensure(_fh);
+}
+
+off_t LocalFileHandle::flen() {
+ return semihost_flen(_fh);
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+ struct dirent cur_entry;
+ XFINFO info;
+
+ LocalDirHandle() : cur_entry(), info() {
+ }
+
+ virtual int closedir() {
+ delete this;
+ return 0;
+ }
+
+ virtual struct dirent *readdir() {
+ if (xffind("*", &info)!=0) {
+ return NULL;
+ }
+ memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+ return &cur_entry;
+ }
+
+ virtual void rewinddir() {
+ info.fileID = 0;
+ }
+
+ virtual off_t telldir() {
+ return info.fileID;
+ }
+
+ virtual void seekdir(off_t offset) {
+ info.fileID = offset;
+ }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+ /* reject filenames with / in them */
+ for (const char *tmp = name; *tmp; tmp++) {
+ if (*tmp == '/') {
+ return NULL;
+ }
+ }
+
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return NULL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return NULL;
+ }
+ return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+ return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+ return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
new file mode 100644
index 000000000..dc5db7a3f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RawSerial.h"
+#include "wait_api.h"
+#include <cstdarg>
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT 120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
+}
+
+int RawSerial::getc() {
+ return _base_getc();
+}
+
+int RawSerial::putc(int c) {
+ return _base_putc(c);
+}
+
+int RawSerial::puts(const char *str) {
+ while (*str)
+ putc(*str ++);
+ return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ int len = vsnprintf(NULL, 0, format, arg);
+ if (len < STRING_STACK_LIMIT) {
+ char temp[STRING_STACK_LIMIT];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ } else {
+ char *temp = new char[len + 1];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ delete[] temp;
+ }
+ va_end(arg);
+ return len;
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
new file mode 100644
index 000000000..4bca2b69c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000) {
+ spi_init(&_spi, mosi, miso, sclk, NC);
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPI::format(int bits, int mode) {
+ _bits = bits;
+ _mode = mode;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+}
+
+void SPI::frequency(int hz) {
+ _hz = hz;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+}
+
+SPI* SPI::_owner = NULL;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+ if (_owner != this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+ _owner = this;
+ }
+}
+
+int SPI::write(int value) {
+ aquire();
+ return spi_master_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
new file mode 100644
index 000000000..5e503165b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000)
+ {
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ spi_format(&_spi, _bits, _mode, 1);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+ _bits = bits;
+ _mode = mode;
+ spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+ _hz = hz;
+ spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+ return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+ return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+ spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
new file mode 100644
index 000000000..602c87a0a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
+}
+
+int Serial::_getc() {
+ return _base_getc();
+}
+
+int Serial::_putc(int c) {
+ return _base_putc(c);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
new file mode 100644
index 000000000..68cf7c381
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SerialBase.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx) : _serial(), _baud(9600) {
+ serial_init(&_serial, tx, rx);
+ serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+ serial_baud(&_serial, baudrate);
+ _baud = baudrate;
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+ serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+}
+
+int SerialBase::readable() {
+ return serial_readable(&_serial);
+}
+
+
+int SerialBase::writeable() {
+ return serial_writable(&_serial);
+}
+
+void SerialBase::attach(void (*fptr)(void), IrqType type) {
+ if (fptr) {
+ _irq[type].attach(fptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ } else {
+ serial_irq_set(&_serial, (SerialIrq)type, 0);
+ }
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+ SerialBase *handler = (SerialBase*)id;
+ handler->_irq[irq_type].call();
+}
+
+int SerialBase::_base_getc() {
+ return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+ serial_putc(&_serial, c);
+ return c;
+}
+
+void SerialBase::send_break() {
+ // Wait for 1.5 frames before clearing the break condition
+ // This will have different effects on our platforms, but should
+ // ensure that we keep the break active for at least one frame.
+ // We consider a full frame (1 start bit + 8 data bits bits +
+ // 1 parity bit + 2 stop bits = 12 bits) for computation.
+ // One bit time (in us) = 1000000/_baud
+ // Twelve bits: 12000000/baud delay
+ // 1.5 frames: 18000000/baud delay
+ serial_break_set(&_serial);
+ wait_us(18000000/_baud);
+ serial_break_clear(&_serial);
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+ FlowControl flow_type = (FlowControl)type;
+ switch(type) {
+ case RTS:
+ serial_set_flow_control(&_serial, flow_type, flow1, NC);
+ break;
+
+ case CTS:
+ serial_set_flow_control(&_serial, flow_type, NC, flow1);
+ break;
+
+ case RTSCTS:
+ case Disabled:
+ serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+ break;
+
+ default:
+ break;
+ }
+}
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
new file mode 100644
index 000000000..6d3a33526
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+#include <cstdarg>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+ /* open ourselves */
+ char buf[12]; /* :0x12345678 + null byte */
+ std::sprintf(buf, ":%p", this);
+ _file = std::fopen(buf, "w+");
+ mbed_set_unbuffered_stream(_file);
+}
+
+Stream::~Stream() {
+ fclose(_file);
+}
+
+int Stream::putc(int c) {
+ fflush(_file);
+ return std::fputc(c, _file);
+}
+int Stream::puts(const char *s) {
+ fflush(_file);
+ return std::fputs(s, _file);
+}
+int Stream::getc() {
+ fflush(_file);
+ return mbed_getc(_file);
+}
+char* Stream::gets(char *s, int size) {
+ fflush(_file);
+ return mbed_gets(s,size,_file);
+}
+
+int Stream::close() {
+ return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+ const char* ptr = (const char*)buffer;
+ const char* end = ptr + length;
+ while (ptr != end) {
+ if (_putc(*ptr++) == EOF) {
+ break;
+ }
+ }
+ return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+ char* ptr = (char*)buffer;
+ char* end = ptr + length;
+ while (ptr != end) {
+ int c = _getc();
+ if (c==EOF) break;
+ *ptr++ = c;
+ }
+ return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+ return 0;
+}
+
+int Stream::isatty() {
+ return 0;
+}
+
+int Stream::fsync() {
+ return 0;
+}
+
+off_t Stream::flen() {
+ return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfprintf(_file, format, arg);
+ va_end(arg);
+ return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfscanf(_file, format, arg);
+ va_end(arg);
+ return r;
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
new file mode 100644
index 000000000..577950b85
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+ remove();
+ _function.attach(0);
+}
+
+void Ticker::setup(timestamp_t t) {
+ remove();
+ _delay = t;
+ insert(_delay + us_ticker_read());
+}
+
+void Ticker::handler() {
+ insert(event.timestamp + _delay);
+ _function.call();
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
new file mode 100644
index 000000000..ed7950212
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+ _function.call();
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
new file mode 100644
index 000000000..e00eaaf54
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time() {
+ reset();
+}
+
+void Timer::start() {
+ if (!_running) {
+ _start = us_ticker_read();
+ _running = 1;
+ }
+}
+
+void Timer::stop() {
+ _time += slicetime();
+ _running = 0;
+}
+
+int Timer::read_us() {
+ return _time + slicetime();
+}
+
+float Timer::read() {
+ return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+ return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+ if (_running) {
+ return us_ticker_read() - _start;
+ } else {
+ return 0;
+ }
+}
+
+void Timer::reset() {
+ _start = us_ticker_read();
+ _time = 0;
+}
+
+#ifdef MBED_OPERATORS
+Timer::operator float() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
new file mode 100644
index 000000000..272adf51f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event() {
+ us_ticker_set_handler((&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+ TimerEvent *timer_event = (TimerEvent*)id;
+ timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+ remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+ us_ticker_insert_event(&event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+ us_ticker_remove_event(&event);
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c b/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
new file mode 100644
index 000000000..51394707b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+#include <stdlib.h>
+#include "mbed_interface.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+#if DEVICE_STDIO_MESSAGES
+ fprintf(stderr, "mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+#endif
+ mbed_die();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/board.c b/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
new file mode 100644
index 000000000..910323645
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "toolchain.h"
+#include "mbed_interface.h"
+
+WEAK void mbed_die(void) {
+#ifndef NRF51_H
+ __disable_irq(); // dont allow interrupts to disturb the flash pattern
+#endif
+#if (DEVICE_ERROR_RED == 1)
+ gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_t led_1; gpio_init_out(&led_1, LED1);
+ gpio_t led_2; gpio_init_out(&led_2, LED2);
+ gpio_t led_3; gpio_init_out(&led_3, LED3);
+ gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+ while (1) {
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 1);
+ gpio_write(&led_2, 0);
+ gpio_write(&led_3, 0);
+ gpio_write(&led_4, 1);
+#endif
+
+ wait_ms(150);
+
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 0);
+ gpio_write(&led_2, 1);
+ gpio_write(&led_3, 1);
+ gpio_write(&led_4, 0);
+#endif
+
+ wait_ms(150);
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/error.c b/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
new file mode 100644
index 000000000..b307d8756
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+WEAK void error(const char* format, ...) {
+#if DEVICE_STDIO_MESSAGES
+ va_list arg;
+ va_start(arg, format);
+ vfprintf(stderr, format, arg);
+ va_end(arg);
+#endif
+ exit(1);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c b/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
new file mode 100644
index 000000000..3839e8bb2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_dir(gpio, PIN_INPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_write(gpio, value);
+ gpio_dir(gpio, PIN_OUTPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+ gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+ _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+ gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+ _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+ if (direction == PIN_INPUT) {
+ _gpio_init_in(gpio, pin, mode);
+ if (pin != NC)
+ gpio_write(gpio, value); // we prepare the value in case it is switched later
+ } else {
+ _gpio_init_out(gpio, pin, mode, value);
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c b/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
new file mode 100644
index 000000000..5b27b3087
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "mbed_error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+ return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+ if (mbed_interface_connected()) {
+ semihost_reset();
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+ if (mbed_interface_connected()) {
+ return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+ } else {
+ uid[0] = 0;
+ return -1;
+ }
+}
+
+int mbed_interface_disconnect(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_disabledebug()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+int mbed_interface_powerdown(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_powerdown()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+ mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+ return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+ char uid[DEVICE_ID_LENGTH + 1];
+ int i;
+
+ // if we have a UID, extract the MAC
+ if (mbed_interface_uid(uid) == 0) {
+ char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+ p += DEVICE_MAC_OFFSET;
+#endif
+ for (i=0; i<6; i++) {
+ int byte;
+ sscanf(p, "%2x", &byte);
+ mac[i] = byte;
+ p += 2;
+ }
+ mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+ } else { // else return a default MAC
+#endif
+ mac[0] = 0x00;
+ mac[1] = 0x02;
+ mac[2] = 0xF7;
+ mac[3] = 0xF0;
+ mac[4] = 0x00;
+ mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+ }
+#endif
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c b/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
new file mode 100644
index 000000000..5aab0e617
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+ if (pin == NC)
+ return;
+
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ pin_function(pin, map->function);
+
+ pin_mode(pin, PullNone);
+ return;
+ }
+ map++;
+ }
+ error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+ // both are the same (inc both NC)
+ if (a == b)
+ return a;
+
+ // one (or both) is not connected
+ if (a == (uint32_t)NC)
+ return b;
+ if (b == (uint32_t)NC)
+ return a;
+
+ // mis-match error case
+ error("pinmap mis-match");
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->peripheral;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+ uint32_t peripheral = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ peripheral = pinmap_find_peripheral(pin, map);
+ if ((uint32_t)NC == peripheral) // no mapping available
+ error("pinmap not found for peripheral");
+ return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->function;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+ uint32_t function = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ function = pinmap_find_function(pin, map);
+ if ((uint32_t)NC == function) // no mapping available
+ error("pinmap not found for function");
+ return function;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp b/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
new file mode 100644
index 000000000..82411abd2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
@@ -0,0 +1,569 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+# include <rt_sys.h>
+# define PREFIX(x) _sys##x
+# define OPEN_MAX _SYS_OPEN
+# ifdef __MICROLIB
+# pragma import(__use_full_stdio)
+# endif
+
+#elif defined(__ICCARM__)
+# include <yfuns.h>
+# define PREFIX(x) _##x
+# define OPEN_MAX 16
+
+# define STDIN_FILENO 0
+# define STDOUT_FILENO 1
+# define STDERR_FILENO 2
+
+#else
+# include <sys/stat.h>
+# include <sys/unistd.h>
+# include <sys/syslimits.h>
+# define PREFIX(x) x
+#endif
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[] = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[] = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+
+FileHandle::~FileHandle() {
+ /* Remove all open filehandles for this */
+ for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == this) {
+ filehandles[fh_i] = NULL;
+ }
+ }
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+ if (stdio_uart_inited) return;
+ serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+ int posix = openmode;
+#ifdef __ARMCC_VERSION
+ if (openmode & OPEN_PLUS) {
+ posix = O_RDWR;
+ } else if(openmode & OPEN_W) {
+ posix = O_WRONLY;
+ } else if(openmode & OPEN_A) {
+ posix = O_WRONLY|O_APPEND;
+ } else {
+ posix = O_RDONLY;
+ }
+ /* a, w, a+, w+ all create if file does not already exist */
+ if (openmode & (OPEN_A|OPEN_W)) {
+ posix |= O_CREAT;
+ }
+ /* w and w+ truncate */
+ if (openmode & OPEN_W) {
+ posix |= O_TRUNC;
+ }
+#elif defined(__ICCARM__)
+ switch (openmode & _LLIO_RDWRMASK) {
+ case _LLIO_RDONLY: posix = O_RDONLY; break;
+ case _LLIO_WRONLY: posix = O_WRONLY; break;
+ case _LLIO_RDWR : posix = O_RDWR ; break;
+ }
+ if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+ if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+ if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#endif
+ return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+ #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+ // Before version 5.03, we were using a patched version of microlib with proper names
+ // This is the workaround that the microlib author suggested us
+ static int n = 0;
+ if (!std::strcmp(name, ":tt")) return n++;
+
+ #else
+ /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+ */
+ if (std::strcmp(name, __stdin_name) == 0) {
+ init_serial();
+ return 0;
+ } else if (std::strcmp(name, __stdout_name) == 0) {
+ init_serial();
+ return 1;
+ } else if (std::strcmp(name, __stderr_name) == 0) {
+ init_serial();
+ return 2;
+ }
+ #endif
+
+ // find the first empty slot in filehandles
+ unsigned int fh_i;
+ for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == NULL) break;
+ }
+ if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+ return -1;
+ }
+
+ FileHandle *res;
+
+ /* FILENAME: ":0x12345678" describes a FileLike* */
+ if (name[0] == ':') {
+ void *p;
+ sscanf(name, ":%p", &p);
+ res = (FileHandle*)p;
+
+ /* FILENAME: "/file_system/file_name" */
+ } else {
+ FilePath path(name);
+
+ if (!path.exists())
+ return -1;
+ else if (path.isFile()) {
+ res = path.file();
+ } else {
+ FileSystemLike *fs = path.fileSystem();
+ if (fs == NULL) return -1;
+ int posix_mode = openmode_to_posix(openmode);
+ res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+ }
+ }
+
+ if (res == NULL) return -1;
+ filehandles[fh_i] = res;
+
+ return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ filehandles[fh-3] = NULL;
+ if (fhc == NULL) return -1;
+
+ return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __write (int fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes written
+ if (fh < 3) {
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+ for (unsigned int i = 0; i < length; i++) {
+ serial_putc(&stdio_uart, buffer[i]);
+ }
+#endif
+ n = length;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ n = fhc->write(buffer, length);
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes read
+ if (fh < 3) {
+ // only read a character at a time from stdin
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+ *buffer = serial_getc(&stdio_uart);
+#endif
+ n = 1;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ n = fhc->read(buffer, length);
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+ /* stdin, stdout and stderr should be tty */
+ if (fh < 3) return 1;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+ return fhc->lseek(position, SEEK_SET);
+#else
+ return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+ if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+ st->st_mode = S_IFCHR;
+ return 0;
+ }
+
+ errno = EBADF;
+ return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+ FilePath fp(path);
+ FileSystemLike *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+ FilePath fpOld(oldname);
+ FilePath fpNew(newname);
+ FileSystemLike *fsOld = fpOld.fileSystem();
+ FileSystemLike *fsNew = fpNew.fileSystem();
+
+ /* rename only if both files are on the same FS */
+ if (fsOld != fsNew || fsOld == NULL) return -1;
+
+ return fsOld->rename(fpOld.fileName(), fpNew.fileName());
+}
+
+extern "C" char *tmpnam(char *s) {
+ return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+ return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+ return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+ /* root dir is FileSystemLike */
+ if (path[0] == '/' && path[1] == 0) {
+ return FileSystemLike::opendir();
+ }
+
+ FilePath fp(path);
+ FileSystemLike* fs = fp.fileSystem();
+ if (fs == NULL) return NULL;
+
+ return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+ return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+ return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+ dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+ return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+ dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+ FilePath fp(path);
+ FileSystemLike *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+ void __verbose_terminate_handler() {
+ error("Exception");
+ }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+ exit(1);
+}
+
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+// mbed_sdk_init() is also a function that is called before main(), but unlike
+// mbed_main(), it is not meant for user code, but for the SDK itself to perform
+// initializations before main() is called.
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+extern "C" WEAK void mbed_sdk_init(void);
+extern "C" WEAK void mbed_sdk_init(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+ mbed_sdk_init();
+ mbed_main();
+ return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+ mbed_sdk_init();
+ mbed_main();
+ return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+ mbed_sdk_init();
+ mbed_main();
+}
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP. This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM)
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" int __end__;
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// For ARM7 only
+register unsigned char * stack_ptr __asm ("sp");
+
+// Dynamic memory allocation related syscall.
+extern "C" caddr_t _sbrk(int incr) {
+ static unsigned char* heap = (unsigned char*)&__end__;
+ unsigned char* prev_heap = heap;
+ unsigned char* new_heap = heap + incr;
+
+#if defined(TARGET_ARM7)
+ if (new_heap >= stack_ptr) {
+#elif defined(TARGET_CORTEX_A)
+ if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
+#else
+ if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+ errno = ENOMEM;
+ return (caddr_t)-1;
+ }
+
+ heap = new_heap;
+ return (caddr_t) prev_heap;
+}
+#endif
+
+
+#ifdef TOOLCHAIN_GCC_CW
+// TODO: Ideally, we would like to define directly "_ExitProcess"
+extern "C" void mbed_exit(int return_code) {
+#elif defined TOOLCHAIN_GCC_ARM
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+ fflush(stdout);
+ fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+ if (mbed_interface_connected()) {
+ semihost_exit();
+ }
+#endif
+ if (return_code) {
+ mbed_die();
+ }
+
+ while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
+} //namespace std
+#endif
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(FILE *_file) {
+#if defined (__ICCARM__)
+ char buf[2];
+ std::setvbuf(_file,buf,_IONBF,NULL);
+#else
+ setbuf(_file, NULL);
+#endif
+}
+
+int mbed_getc(FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ int res = std::fgetc(_file);
+ if (res>=0){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return res;
+#else
+ return std::fgetc(_file);
+#endif
+}
+
+char* mbed_gets(char*s, int size, FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ char *str = fgets(s,size,_file);
+ if (str!=NULL){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return str;
+#else
+ return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c b/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
new file mode 100644
index 000000000..982279746
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+ if (_rtc_isenabled != NULL) {
+ if (!(_rtc_isenabled())) {
+ set_time(0);
+ }
+ }
+
+ time_t t = 0;
+ if (_rtc_read != NULL) {
+ t = _rtc_read();
+ }
+
+ if (timer != NULL) {
+ *timer = t;
+ }
+ return t;
+}
+
+void set_time(time_t t) {
+ if (_rtc_init != NULL) {
+ _rtc_init();
+ }
+ if (_rtc_write != NULL) {
+ _rtc_write(t);
+ }
+}
+
+clock_t clock() {
+ clock_t t = us_ticker_read();
+ t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+ return t;
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+ __disable_irq();
+ _rtc_read = read_rtc;
+ _rtc_write = write_rtc;
+ _rtc_init = init_rtc;
+ _rtc_isenabled = isenabled_rtc;
+ __enable_irq();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c b/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
new file mode 100644
index 000000000..e4e136eca
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
@@ -0,0 +1,162 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN (0x1)
+#define SYS_CLOSE (0x2)
+#define SYS_WRITE (0x5)
+#define SYS_READ (0x6)
+#define SYS_ISTTY (0x9)
+#define SYS_SEEK (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)openmode;
+ args[2] = (uint32_t)strlen(name);
+ return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+ return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+ if (length == 0) return 0;
+
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+ return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+ uint32_t args[2];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)position;
+ return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+ return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+ return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+ uint32_t args[2];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)strlen(name);
+ return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+ uint32_t args[4];
+ args[0] = (uint32_t)old_name;
+ args[1] = (uint32_t)strlen(old_name);
+ args[0] = (uint32_t)new_name;
+ args[1] = (uint32_t)strlen(new_name);
+ return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+ uint32_t args[4];
+ return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+ uint32_t args[2];
+ args[0] = (uint32_t)uid;
+ args[1] = DEVICE_ID_LENGTH + 1;
+ return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+ // Does not normally return, however if used with older firmware versions
+ // that do not support this call it will return -1.
+ return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+ return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+ return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+ return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+ return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+#if !(DEVICE_DEBUG_AWARENESS)
+ is_debugger_attached = 0;
+#endif
+ return __semihost(USR_DISABLEDEBUG, NULL);
+}
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c b/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
new file mode 100644
index 000000000..659a04f48
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
@@ -0,0 +1,134 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "cmsis.h"
+
+static ticker_event_handler event_handler;
+static ticker_event_t *head = NULL;
+
+void us_ticker_set_handler(ticker_event_handler handler) {
+ us_ticker_init();
+
+ event_handler = handler;
+}
+
+void us_ticker_irq_handler(void) {
+ us_ticker_clear_interrupt();
+
+ /* Go through all the pending TimerEvents */
+ while (1) {
+ if (head == NULL) {
+ // There are no more TimerEvents left, so disable matches.
+ us_ticker_disable_interrupt();
+ return;
+ }
+
+ if ((int)(head->timestamp - us_ticker_read()) <= 0) {
+ // This event was in the past:
+ // point to the following one and execute its handler
+ ticker_event_t *p = head;
+ head = head->next;
+ if (event_handler != NULL) {
+ event_handler(p->id); // NOTE: the handler can set new events
+ }
+ /* Note: We continue back to examining the head because calling the
+ * event handler may have altered the chain of pending events. */
+ } else {
+ // This event and the following ones in the list are in the future:
+ // set it as next interrupt and return
+ us_ticker_set_interrupt(head->timestamp);
+ return;
+ }
+ }
+}
+
+void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
+ /* disable interrupts for the duration of the function */
+ __disable_irq();
+
+ // initialise our data
+ obj->timestamp = timestamp;
+ obj->id = id;
+
+ /* Go through the list until we either reach the end, or find
+ an element this should come before (which is possibly the
+ head). */
+ ticker_event_t *prev = NULL, *p = head;
+ while (p != NULL) {
+ /* check if we come before p */
+ if ((int)(timestamp - p->timestamp) < 0) {
+ break;
+ }
+ /* go to the next element */
+ prev = p;
+ p = p->next;
+ }
+
+ /* if we're at the end p will be NULL, which is correct */
+ obj->next = p;
+
+ /* if prev is NULL we're at the head */
+ if (prev == NULL) {
+ head = obj;
+ us_ticker_set_interrupt(timestamp);
+ } else {
+ prev->next = obj;
+ }
+
+ __enable_irq();
+}
+
+void us_ticker_remove_event(ticker_event_t *obj) {
+ __disable_irq();
+
+ // remove this object from the list
+ if (head == obj) {
+ // first in the list, so just drop me
+ head = obj->next;
+ if (head == NULL) {
+ us_ticker_disable_interrupt();
+ } else {
+ us_ticker_set_interrupt(head->timestamp);
+ }
+ } else {
+ // find the object before me, then drop me
+ ticker_event_t* p = head;
+ while (p != NULL) {
+ if (p->next == obj) {
+ p->next = obj->next;
+ break;
+ }
+ p = p->next;
+ }
+ }
+
+ __enable_irq();
+}
+
+int us_ticker_get_next_timestamp(timestamp_t *timestamp) {
+ int ret = 0;
+
+ /* if head is NULL, there are no pending events */
+ __disable_irq();
+ if (head != NULL) {
+ *timestamp = head->timestamp;
+ ret = 1;
+ }
+ __enable_irq();
+
+ return ret;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c b/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
new file mode 100644
index 000000000..b276614ca
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+ uint32_t start = us_ticker_read();
+ while ((us_ticker_read() - start) < (uint32_t)us);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
new file mode 100644
index 000000000..98d02c1b8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct analogin_s analogin_t;
+
+void analogin_init (analogin_t *obj, PinName pin);
+float analogin_read (analogin_t *obj);
+uint16_t analogin_read_u16(analogin_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
new file mode 100644
index 000000000..97a201376
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dac_s dac_t;
+
+void analogout_init (dac_t *obj, PinName pin);
+void analogout_free (dac_t *obj);
+void analogout_write (dac_t *obj, float value);
+void analogout_write_u16(dac_t *obj, uint16_t value);
+float analogout_read (dac_t *obj);
+uint16_t analogout_read_u16 (dac_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
new file mode 100644
index 000000000..48bc10469
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_LOCAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void can_init (can_t *obj, PinName rd, PinName td);
+void can_free (can_t *obj);
+int can_frequency(can_t *obj, int hz);
+
+void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free (can_t *obj);
+void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int can_write (can_t *obj, CAN_Message, int cc);
+int can_read (can_t *obj, CAN_Message *msg, int handle);
+int can_mode (can_t *obj, CanMode mode);
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void can_reset (can_t *obj);
+unsigned char can_rderror (can_t *obj);
+unsigned char can_tderror (can_t *obj);
+void can_monitor (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // MBED_CAN_API_H
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
new file mode 100644
index 000000000..4cae77e13
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
new file mode 100644
index 000000000..872b547ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/* GPIO object */
+void gpio_init(gpio_t *obj, PinName pin);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int gpio_read (gpio_t *obj);
+
+// the following set of functions are generic and are implemented in the common gpio.c file
+void gpio_init_in(gpio_t* gpio, PinName pin);
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+void gpio_init_out(gpio_t* gpio, PinName pin);
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
new file mode 100644
index 000000000..76c7e927e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_NONE,
+ IRQ_RISE,
+ IRQ_FALL
+} gpio_irq_event;
+
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+void gpio_irq_free(gpio_irq_t *obj);
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+void gpio_irq_enable(gpio_irq_t *obj);
+void gpio_irq_disable(gpio_irq_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
new file mode 100644
index 000000000..c4da824e7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+
+#if DEVICE_I2C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct i2c_s i2c_t;
+
+enum {
+ I2C_ERROR_NO_SLAVE = -1,
+ I2C_ERROR_BUS_BUSY = -2
+};
+
+void i2c_init (i2c_t *obj, PinName sda, PinName scl);
+void i2c_frequency (i2c_t *obj, int hz);
+int i2c_start (i2c_t *obj);
+int i2c_stop (i2c_t *obj);
+int i2c_read (i2c_t *obj, int address, char *data, int length, int stop);
+int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop);
+void i2c_reset (i2c_t *obj);
+int i2c_byte_read (i2c_t *obj, int last);
+int i2c_byte_write (i2c_t *obj, int data);
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode (i2c_t *obj, int enable_slave);
+int i2c_slave_receive(i2c_t *obj);
+int i2c_slave_read (i2c_t *obj, char *data, int length);
+int i2c_slave_write (i2c_t *obj, const char *data, int length);
+int i2c_slave_byte_read(i2c_t *obj, int last);
+int i2c_slave_byte_write(i2c_t *obj, int data);
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
new file mode 100644
index 000000000..a9cc92186
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ int peripheral;
+ int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge (uint32_t a, uint32_t b);
+void pinmap_pinout (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
new file mode 100644
index 000000000..f687cfe89
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct port_s port_t;
+
+PinName port_pin(PortName port, int pin_n);
+
+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
+void port_mode (port_t *obj, PinMode mode);
+void port_dir (port_t *obj, PinDirection dir);
+void port_write(port_t *obj, int value);
+int port_read (port_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
new file mode 100644
index 000000000..6557fcdc4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct pwmout_s pwmout_t;
+
+void pwmout_init (pwmout_t* obj, PinName pin);
+void pwmout_free (pwmout_t* obj);
+
+void pwmout_write (pwmout_t* obj, float percent);
+float pwmout_read (pwmout_t* obj);
+
+void pwmout_period (pwmout_t* obj, float seconds);
+void pwmout_period_ms (pwmout_t* obj, int ms);
+void pwmout_period_us (pwmout_t* obj, int us);
+
+void pwmout_pulsewidth (pwmout_t* obj, float seconds);
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
+void pwmout_pulsewidth_us(pwmout_t* obj, int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
new file mode 100644
index 000000000..663f8884f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtc_init(void);
+void rtc_free(void);
+int rtc_isenabled(void);
+
+time_t rtc_read(void);
+void rtc_write(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
new file mode 100644
index 000000000..2b0f0c4ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+
+#if DEVICE_SERIAL
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ParityNone = 0,
+ ParityOdd = 1,
+ ParityEven = 2,
+ ParityForced1 = 3,
+ ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+ RxIrq,
+ TxIrq
+} SerialIrq;
+
+typedef enum {
+ FlowControlNone,
+ FlowControlRTS,
+ FlowControlCTS,
+ FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+typedef struct serial_s serial_t;
+
+void serial_init (serial_t *obj, PinName tx, PinName rx);
+void serial_free (serial_t *obj);
+void serial_baud (serial_t *obj, int baudrate);
+void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable);
+
+int serial_getc (serial_t *obj);
+void serial_putc (serial_t *obj, int c);
+int serial_readable (serial_t *obj);
+int serial_writable (serial_t *obj);
+void serial_clear (serial_t *obj);
+
+void serial_break_set (serial_t *obj);
+void serial_break_clear(serial_t *obj);
+
+void serial_pinout_tx(PinName tx);
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
new file mode 100644
index 000000000..c8cf3b6f8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
new file mode 100644
index 000000000..7553dc1e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+
+#if DEVICE_SPI
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct spi_s spi_t;
+
+void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+void spi_free (spi_t *obj);
+void spi_format (spi_t *obj, int bits, int mode, int slave);
+void spi_frequency (spi_t *obj, int hz);
+int spi_master_write (spi_t *obj, int value);
+int spi_slave_receive(spi_t *obj);
+int spi_slave_read (spi_t *obj);
+void spi_slave_write (spi_t *obj, int value);
+int spi_busy (spi_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h b/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
new file mode 100644
index 000000000..1fa93170e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t timestamp_t;
+
+uint32_t us_ticker_read(void);
+
+typedef void (*ticker_event_handler)(uint32_t id);
+void us_ticker_set_handler(ticker_event_handler handler);
+
+typedef struct ticker_event_s {
+ timestamp_t timestamp;
+ uint32_t id;
+ struct ticker_event_s *next;
+} ticker_event_t;
+
+void us_ticker_init(void);
+void us_ticker_set_interrupt(timestamp_t timestamp);
+void us_ticker_disable_interrupt(void);
+void us_ticker_clear_interrupt(void);
+void us_ticker_irq_handler(void);
+
+void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+void us_ticker_remove_event(ticker_event_t *obj);
+int us_ticker_get_next_timestamp(timestamp_t *timestamp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
new file mode 100644
index 000000000..b979eb7db
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
@@ -0,0 +1,5836 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK20D5
+**
+** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5.h
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief CMSIS Peripheral Access Layer for MK20D5
+ *
+ * CMSIS Peripheral Access Layer for MK20D5
+ */
+
+#if !defined(MK20D5_H_)
+#define MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ DMA_Error_IRQn = 4, /**< DMA error interrupt */
+ Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
+ FTFL_IRQn = 6, /**< FTFL interrupt */
+ Read_Collision_IRQn = 7, /**< Read collision interrupt */
+ LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 9, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 10, /**< WDOG interrupt */
+ I2C0_IRQn = 11, /**< I2C0 interrupt */
+ SPI0_IRQn = 12, /**< SPI0 interrupt */
+ I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
+ UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
+ UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
+ UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
+ UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
+ UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
+ ADC0_IRQn = 22, /**< ADC0 interrupt */
+ CMP0_IRQn = 23, /**< CMP0 interrupt */
+ CMP1_IRQn = 24, /**< CMP1 interrupt */
+ FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
+ CMT_IRQn = 27, /**< CMT interrupt */
+ RTC_IRQn = 28, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
+ PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 34, /**< PDB0 interrupt */
+ USB0_IRQn = 35, /**< USB0 interrupt */
+ USBDCD_IRQn = 36, /**< USBDCD interrupt */
+ TSI0_IRQn = 37, /**< TSI0 interrupt */
+ MCG_IRQn = 38, /**< MCG interrupt */
+ LPTimer_IRQn = 39, /**< LPTimer interrupt */
+ PORTA_IRQn = 40, /**< Port A interrupt */
+ PORTB_IRQn = 41, /**< Port B interrupt */
+ PORTC_IRQn = 42, /**< Port C interrupt */
+ PORTD_IRQn = 43, /**< Port D interrupt */
+ PORTE_IRQn = 44, /**< Port E interrupt */
+ SWI_IRQn = 45 /**< Software interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK20D5.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+
+/**
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
+ __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
+ __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
+ __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
+ __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK 0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT 0
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
+/* CRCH Bit Fields */
+#define CRC_CRCH_CRCH_MASK 0xFFFFu
+#define CRC_CRCH_CRCH_SHIFT 0
+#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
+/* CRC Bit Fields */
+#define CRC_CRC_LL_MASK 0xFFu
+#define CRC_CRC_LL_SHIFT 0
+#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK 0xFF00u
+#define CRC_CRC_LU_SHIFT 8
+#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK 0xFF0000u
+#define CRC_CRC_HL_SHIFT 16
+#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK 0xFF000000u
+#define CRC_CRC_HU_SHIFT 24
+#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
+/* CRCLL Bit Fields */
+#define CRC_CRCLL_CRCLL_MASK 0xFFu
+#define CRC_CRCLL_CRCLL_SHIFT 0
+#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
+/* CRCLU Bit Fields */
+#define CRC_CRCLU_CRCLU_MASK 0xFFu
+#define CRC_CRCLU_CRCLU_SHIFT 0
+#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
+/* CRCHL Bit Fields */
+#define CRC_CRCHL_CRCHL_MASK 0xFFu
+#define CRC_CRCHL_CRCHL_SHIFT 0
+#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
+/* CRCHU Bit Fields */
+#define CRC_CRCHU_CRCHU_MASK 0xFFu
+#define CRC_CRCHU_CRCHU_SHIFT 0
+#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/**
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+
+/**
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ uint8_t RESERVED_6[3836];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/**
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+
+/**
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } TAG_WAY[4];
+ uint8_t RESERVED_1[132];
+ struct { /* offset: 0x204, array step: 0x8 */
+ __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW0S[2];
+ uint8_t RESERVED_2[48];
+ struct { /* offset: 0x244, array step: 0x8 */
+ __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW1S[2];
+ uint8_t RESERVED_3[48];
+ struct { /* offset: 0x284, array step: 0x8 */
+ __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW2S[2];
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x2C4, array step: 0x8 */
+ __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW3S[2];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* TAGVD Bit Fields */
+#define FMC_TAGVD_valid_MASK 0x1u
+#define FMC_TAGVD_valid_SHIFT 0
+#define FMC_TAGVD_tag_MASK 0x7FFC0u
+#define FMC_TAGVD_tag_SHIFT 6
+#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
+/* DATAW0S Bit Fields */
+#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW0S_data_SHIFT 0
+#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
+/* DATAW1S Bit Fields */
+#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW1S_data_SHIFT 0
+#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
+/* DATAW2S Bit Fields */
+#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW2S_data_SHIFT 0
+#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
+/* DATAW3S Bit Fields */
+#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW3S_data_SHIFT 0
+#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
+
+/**
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+
+/**
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
+ * @{
+ */
+
+/** FTFL - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Register_Masks FTFL Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFL_FSTAT_MGSTAT0_SHIFT 0
+#define FTFL_FSTAT_FPVIOL_MASK 0x10u
+#define FTFL_FSTAT_FPVIOL_SHIFT 4
+#define FTFL_FSTAT_ACCERR_MASK 0x20u
+#define FTFL_FSTAT_ACCERR_SHIFT 5
+#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFL_FSTAT_RDCOLERR_SHIFT 6
+#define FTFL_FSTAT_CCIF_MASK 0x80u
+#define FTFL_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFL_FCNFG_EEERDY_MASK 0x1u
+#define FTFL_FCNFG_EEERDY_SHIFT 0
+#define FTFL_FCNFG_RAMRDY_MASK 0x2u
+#define FTFL_FCNFG_RAMRDY_SHIFT 1
+#define FTFL_FCNFG_PFLSH_MASK 0x4u
+#define FTFL_FCNFG_PFLSH_SHIFT 2
+#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFL_FCNFG_ERSSUSP_SHIFT 4
+#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFL_FCNFG_ERSAREQ_SHIFT 5
+#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFL_FCNFG_CCIE_MASK 0x80u
+#define FTFL_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFL_FSEC_SEC_MASK 0x3u
+#define FTFL_FSEC_SEC_SHIFT 0
+#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK 0xCu
+#define FTFL_FSEC_FSLACC_SHIFT 2
+#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK 0x30u
+#define FTFL_FSEC_MEEN_SHIFT 4
+#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK 0xC0u
+#define FTFL_FSEC_KEYEN_SHIFT 6
+#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFL_FOPT_OPT_MASK 0xFFu
+#define FTFL_FOPT_OPT_SHIFT 0
+#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB3_CCOBn_SHIFT 0
+#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB2_CCOBn_SHIFT 0
+#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB1_CCOBn_SHIFT 0
+#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB0_CCOBn_SHIFT 0
+#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB7_CCOBn_SHIFT 0
+#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB6_CCOBn_SHIFT 0
+#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB5_CCOBn_SHIFT 0
+#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB4_CCOBn_SHIFT 0
+#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBB_CCOBn_SHIFT 0
+#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBA_CCOBn_SHIFT 0
+#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB9_CCOBn_SHIFT 0
+#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB8_CCOBn_SHIFT 0
+#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFL_FPROT3_PROT_MASK 0xFFu
+#define FTFL_FPROT3_PROT_SHIFT 0
+#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFL_FPROT2_PROT_MASK 0xFFu
+#define FTFL_FPROT2_PROT_SHIFT 0
+#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFL_FPROT1_PROT_MASK 0xFFu
+#define FTFL_FPROT1_PROT_SHIFT 0
+#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFL_FPROT0_PROT_MASK 0xFFu
+#define FTFL_FPROT0_PROT_SHIFT 0
+#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFL_FEPROT_EPROT_MASK 0xFFu
+#define FTFL_FEPROT_EPROT_SHIFT 0
+#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFL_FDPROT_DPROT_MASK 0xFFu
+#define FTFL_FDPROT_DPROT_SHIFT 0
+#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/** Peripheral FTFL base address */
+#define FTFL_BASE (0x40020000u)
+/** Peripheral FTFL base pointer */
+#define FTFL ((FTFL_Type *)FTFL_BASE)
+
+/**
+ * @}
+ */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/**
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+
+/**
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x1u
+#define MCG_C7_OSCSEL_SHIFT 0
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE (0x400u)
+/** Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x10 */
+ __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
+ __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
+ } CH[1];
+ uint8_t RESERVED_0[368];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/**
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+
+/**
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTIMER_MASK 0x1u
+#define SIM_SCGC5_LPTIMER_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTFL_MASK 0x1u
+#define SIM_SCGC6_FTFL_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK 0x1u
+#define TSI_GENCS_STPE_SHIFT 0
+#define TSI_GENCS_STM_MASK 0x2u
+#define TSI_GENCS_STM_SHIFT 1
+#define TSI_GENCS_ESOR_MASK 0x10u
+#define TSI_GENCS_ESOR_SHIFT 4
+#define TSI_GENCS_ERIE_MASK 0x20u
+#define TSI_GENCS_ERIE_SHIFT 5
+#define TSI_GENCS_TSIIE_MASK 0x40u
+#define TSI_GENCS_TSIIE_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_SWTS_MASK 0x100u
+#define TSI_GENCS_SWTS_SHIFT 8
+#define TSI_GENCS_SCNIP_MASK 0x200u
+#define TSI_GENCS_SCNIP_SHIFT 9
+#define TSI_GENCS_OVRF_MASK 0x1000u
+#define TSI_GENCS_OVRF_SHIFT 12
+#define TSI_GENCS_EXTERF_MASK 0x2000u
+#define TSI_GENCS_EXTERF_SHIFT 13
+#define TSI_GENCS_OUTRGF_MASK 0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT 14
+#define TSI_GENCS_EOSF_MASK 0x8000u
+#define TSI_GENCS_EOSF_SHIFT 15
+#define TSI_GENCS_PS_MASK 0x70000u
+#define TSI_GENCS_PS_SHIFT 16
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK 0xF80000u
+#define TSI_GENCS_NSCN_SHIFT 19
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
+#define TSI_GENCS_LPSCNITV_SHIFT 24
+#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK 0x10000000u
+#define TSI_GENCS_LPCLKS_SHIFT 28
+/* SCANC Bit Fields */
+#define TSI_SCANC_AMPSC_MASK 0x7u
+#define TSI_SCANC_AMPSC_SHIFT 0
+#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK 0x18u
+#define TSI_SCANC_AMCLKS_SHIFT 3
+#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK 0xFF00u
+#define TSI_SCANC_SMOD_SHIFT 8
+#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
+#define TSI_SCANC_EXTCHRG_SHIFT 16
+#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK 0xF000000u
+#define TSI_SCANC_REFCHRG_SHIFT 24
+#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
+/* PEN Bit Fields */
+#define TSI_PEN_PEN0_MASK 0x1u
+#define TSI_PEN_PEN0_SHIFT 0
+#define TSI_PEN_PEN1_MASK 0x2u
+#define TSI_PEN_PEN1_SHIFT 1
+#define TSI_PEN_PEN2_MASK 0x4u
+#define TSI_PEN_PEN2_SHIFT 2
+#define TSI_PEN_PEN3_MASK 0x8u
+#define TSI_PEN_PEN3_SHIFT 3
+#define TSI_PEN_PEN4_MASK 0x10u
+#define TSI_PEN_PEN4_SHIFT 4
+#define TSI_PEN_PEN5_MASK 0x20u
+#define TSI_PEN_PEN5_SHIFT 5
+#define TSI_PEN_PEN6_MASK 0x40u
+#define TSI_PEN_PEN6_SHIFT 6
+#define TSI_PEN_PEN7_MASK 0x80u
+#define TSI_PEN_PEN7_SHIFT 7
+#define TSI_PEN_PEN8_MASK 0x100u
+#define TSI_PEN_PEN8_SHIFT 8
+#define TSI_PEN_PEN9_MASK 0x200u
+#define TSI_PEN_PEN9_SHIFT 9
+#define TSI_PEN_PEN10_MASK 0x400u
+#define TSI_PEN_PEN10_SHIFT 10
+#define TSI_PEN_PEN11_MASK 0x800u
+#define TSI_PEN_PEN11_SHIFT 11
+#define TSI_PEN_PEN12_MASK 0x1000u
+#define TSI_PEN_PEN12_SHIFT 12
+#define TSI_PEN_PEN13_MASK 0x2000u
+#define TSI_PEN_PEN13_SHIFT 13
+#define TSI_PEN_PEN14_MASK 0x4000u
+#define TSI_PEN_PEN14_SHIFT 14
+#define TSI_PEN_PEN15_MASK 0x8000u
+#define TSI_PEN_PEN15_SHIFT 15
+#define TSI_PEN_LPSP_MASK 0xF0000u
+#define TSI_PEN_LPSP_SHIFT 16
+#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
+/* WUCNTR Bit Fields */
+#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
+#define TSI_WUCNTR_WUCNT_SHIFT 0
+#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
+/* CNTR1 Bit Fields */
+#define TSI_CNTR1_CTN1_MASK 0xFFFFu
+#define TSI_CNTR1_CTN1_SHIFT 0
+#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR1_CTN_SHIFT 16
+#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
+/* CNTR3 Bit Fields */
+#define TSI_CNTR3_CTN1_MASK 0xFFFFu
+#define TSI_CNTR3_CTN1_SHIFT 0
+#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR3_CTN_SHIFT 16
+#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
+/* CNTR5 Bit Fields */
+#define TSI_CNTR5_CTN1_MASK 0xFFFFu
+#define TSI_CNTR5_CTN1_SHIFT 0
+#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR5_CTN_SHIFT 16
+#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
+/* CNTR7 Bit Fields */
+#define TSI_CNTR7_CTN1_MASK 0xFFFFu
+#define TSI_CNTR7_CTN1_SHIFT 0
+#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR7_CTN_SHIFT 16
+#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
+/* CNTR9 Bit Fields */
+#define TSI_CNTR9_CTN1_MASK 0xFFFFu
+#define TSI_CNTR9_CTN1_SHIFT 0
+#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR9_CTN_SHIFT 16
+#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
+/* CNTR11 Bit Fields */
+#define TSI_CNTR11_CTN1_MASK 0xFFFFu
+#define TSI_CNTR11_CTN1_SHIFT 0
+#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR11_CTN_SHIFT 16
+#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
+/* CNTR13 Bit Fields */
+#define TSI_CNTR13_CTN1_MASK 0xFFFFu
+#define TSI_CNTR13_CTN1_SHIFT 0
+#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR13_CTN_SHIFT 16
+#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
+/* CNTR15 Bit Fields */
+#define TSI_CNTR15_CTN1_MASK 0xFFFFu
+#define TSI_CNTR15_CTN1_SHIFT 0
+#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR15_CTN_SHIFT 16
+#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
+/* THRESHOLD Bit Fields */
+#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
+#define TSI_THRESHOLD_HTHH_SHIFT 0
+#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
+#define TSI_THRESHOLD_LTHH_SHIFT 16
+#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
+ __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
+ __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
+ __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
+ __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
+ __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
+ __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
+ __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
+ __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
+ __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
+ __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
+ __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
+ __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
+ __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
+ __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
+ __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
+ __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT 0
+#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
+#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
+#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* C6 Bit Fields */
+#define UART_C6_CP_MASK 0x10u
+#define UART_C6_CP_SHIFT 4
+#define UART_C6_CE_MASK 0x20u
+#define UART_C6_CE_SHIFT 5
+#define UART_C6_TX709_MASK 0x40u
+#define UART_C6_TX709_SHIFT 6
+#define UART_C6_EN709_MASK 0x80u
+#define UART_C6_EN709_SHIFT 7
+/* PCTH Bit Fields */
+#define UART_PCTH_PCTH_MASK 0xFFu
+#define UART_PCTH_PCTH_SHIFT 0
+#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
+/* PCTL Bit Fields */
+#define UART_PCTL_PCTL_MASK 0xFFu
+#define UART_PCTL_PCTL_SHIFT 0
+#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
+/* B1T Bit Fields */
+#define UART_B1T_B1T_MASK 0xFFu
+#define UART_B1T_B1T_SHIFT 0
+#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
+/* SDTH Bit Fields */
+#define UART_SDTH_SDTH_MASK 0xFFu
+#define UART_SDTH_SDTH_SHIFT 0
+#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
+/* SDTL Bit Fields */
+#define UART_SDTL_SDTL_MASK 0xFFu
+#define UART_SDTL_SDTL_SHIFT 0
+#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
+/* PRE Bit Fields */
+#define UART_PRE_PREAMBLE_MASK 0xFFu
+#define UART_PRE_PREAMBLE_SHIFT 0
+#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
+/* TPL Bit Fields */
+#define UART_TPL_TPL_MASK 0xFFu
+#define UART_TPL_TPL_SHIFT 0
+#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
+/* IE Bit Fields */
+#define UART_IE_TXFIE_MASK 0x1u
+#define UART_IE_TXFIE_SHIFT 0
+#define UART_IE_PSIE_MASK 0x2u
+#define UART_IE_PSIE_SHIFT 1
+#define UART_IE_PCTEIE_MASK 0x4u
+#define UART_IE_PCTEIE_SHIFT 2
+#define UART_IE_PTXIE_MASK 0x8u
+#define UART_IE_PTXIE_SHIFT 3
+#define UART_IE_PRXIE_MASK 0x10u
+#define UART_IE_PRXIE_SHIFT 4
+#define UART_IE_ISDIE_MASK 0x20u
+#define UART_IE_ISDIE_SHIFT 5
+#define UART_IE_WBEIE_MASK 0x40u
+#define UART_IE_WBEIE_SHIFT 6
+/* WB Bit Fields */
+#define UART_WB_WBASE_MASK 0xFFu
+#define UART_WB_WBASE_SHIFT 0
+#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
+/* S3 Bit Fields */
+#define UART_S3_TXFF_MASK 0x1u
+#define UART_S3_TXFF_SHIFT 0
+#define UART_S3_PSF_MASK 0x2u
+#define UART_S3_PSF_SHIFT 1
+#define UART_S3_PCTEF_MASK 0x4u
+#define UART_S3_PCTEF_SHIFT 2
+#define UART_S3_PTXF_MASK 0x8u
+#define UART_S3_PTXF_SHIFT 3
+#define UART_S3_PRXF_MASK 0x10u
+#define UART_S3_PRXF_SHIFT 4
+#define UART_S3_ISD_MASK 0x20u
+#define UART_S3_ISD_SHIFT 5
+#define UART_S3_WBEF_MASK 0x40u
+#define UART_S3_WBEF_SHIFT 6
+#define UART_S3_PEF_MASK 0x80u
+#define UART_S3_PEF_SHIFT 7
+/* S4 Bit Fields */
+#define UART_S4_FE_MASK 0x1u
+#define UART_S4_FE_SHIFT 0
+#define UART_S4_ILCV_MASK 0x2u
+#define UART_S4_ILCV_SHIFT 1
+#define UART_S4_CDET_MASK 0xCu
+#define UART_S4_CDET_SHIFT 2
+#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK 0x10u
+#define UART_S4_INITF_SHIFT 4
+/* RPL Bit Fields */
+#define UART_RPL_RPL_MASK 0xFFu
+#define UART_RPL_RPL_SHIFT 0
+#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
+/* RPREL Bit Fields */
+#define UART_RPREL_RPREL_MASK 0xFFu
+#define UART_RPREL_RPREL_SHIFT 0
+#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
+/* CPW Bit Fields */
+#define UART_CPW_CPW_MASK 0xFFu
+#define UART_CPW_CPW_SHIFT 0
+#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
+/* RIDT Bit Fields */
+#define UART_RIDT_RIDT_MASK 0xFFu
+#define UART_RIDT_RIDT_SHIFT 0
+#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
+/* TIDT Bit Fields */
+#define UART_TIDT_TIDT_MASK 0xFFu
+#define UART_TIDT_TIDT_SHIFT 0
+#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status Register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< , offset: 0x14 */
+ __IO uint32_t TIMER2; /**< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2 Bit Fields */
+#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+
+/**
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/**
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+
+/**
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MK20D5_H_) */
+
+/* MK20D5.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
new file mode 100644
index 000000000..9a661627b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
+ ; 0x4000 - 0xF8 = 0x3F08
+ RW_IRAM1 0x1FFFE0F8 0x3F08 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
new file mode 100644
index 000000000..24de2c250
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
@@ -0,0 +1,412 @@
+;/*****************************************************************************
+; * @file: startup_MK20D5.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK20D5
+; * @version: 1.0
+; * @date: 2011-12-15
+; *
+; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20002000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD DMA_Error_IRQHandler ; DMA error interrupt
+ DCD Reserved21_IRQHandler ; Reserved interrupt 21
+ DCD FTFL_IRQHandler ; FTFL interrupt
+ DCD Read_Collision_IRQHandler ; Read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT Reserved21_IRQHandler [WEAK]
+ EXPORT FTFL_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA_Error_IRQHandler
+Reserved21_IRQHandler
+FTFL_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..3296df192
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
new file mode 100644
index 000000000..600751ca0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
@@ -0,0 +1,163 @@
+/*
+ * K20 ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
new file mode 100644
index 000000000..ffa33181f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
@@ -0,0 +1,259 @@
+/* File: startup_MK20D5.s
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 08 Feb 2012
+ *
+ * Copyright (c) 2015, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0xC00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* 0: Watchdog Timer */
+ .long DMA1_IRQHandler /* 1: Real Time Clock */
+ .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
+ .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
+ .long DMA_Error_IRQHandler /* 4: MCIa */
+ .long 0 /* 5: MCIb */
+ .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long LLW_IRQHandler /* 9: UART4 - not connected */
+ .long Watchdog_IRQHandler /* 10: AACI / AC97 */
+ .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long SPI0_IRQHandler /* 12: Ethernet */
+ .long I2S0_Tx_IRQHandler /* 13: USB Device */
+ .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
+ .long UART0_LON_IRQHandler /* 15: Character LCD */
+ .long UART0_RX_TX_IRQHandler /* 16: Flexray */
+ .long UART0_ERR_IRQHandler /* 17: CAN */
+ .long UART1_RX_TX_IRQHandler /* 18: LIN */
+ .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
+ .long UART2_RX_TX_IRQHandler /* 20: Reserved */
+ .long UART2_ERR_IRQHandler /* 21: Reserved */
+ .long ADC0_IRQHandler /* 22: Reserved */
+ .long CMP0_IRQHandler /* 23: Reserved */
+ .long CMP1_IRQHandler /* 24: Reserved */
+ .long FTM0_IRQHandler /* 25: Reserved */
+ .long FTM1_IRQHandler /* 26: Reserved */
+ .long CMT_IRQHandler /* 27: Reserved */
+ .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
+ .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ .long PIT2_IRQHandler
+ .long PIT3_IRQHandler
+ .long PDB0_IRQHandler
+ .long USB0_IRQHandler
+ .long USBDCD_IRQHandler
+ .long TSI0_IRQHandler
+ .long MCG_IRQHandler
+ .long LPTimer_IRQHandler
+ .long PORTA_IRQHandler
+ .long PORTB_IRQHandler
+ .long PORTC_IRQHandler
+ .long PORTD_IRQHandler
+ .long PORTE_IRQHandler
+ .long SWI_IRQHandler
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler FTFL_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler UART0_LON_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler CMT_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USBDCD_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
new file mode 100644
index 000000000..e73c38a0c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
@@ -0,0 +1,52 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x600;
+define symbol __ICFEDIT_size_heap__ = 0xC00;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20001fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define symbol __region_FlexNVM_start__ = 0x10000000;
+define symbol __region_FlexNVM_end__ = 0x10007fff;
+
+define symbol __region_FlexRAM_start__ = 0x14000000;
+define symbol __region_FlexRAM_end__ = 0x140007ff;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
+
+place in FlexRAM_region { section .flex_ram };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
new file mode 100644
index 000000000..cee394eaf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
@@ -0,0 +1,271 @@
+/**************************************************
+ *
+ * Copyright 2010 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete
+ DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15
+ DCD 0 ; 5: Reserved
+ DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete
+ DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision
+ DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning
+ DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup
+ DCD WDOG_IRQHandler ;10: WDOG interrupt
+ DCD I2C0_IRQHandler ;11: I2C0 interrupt
+ DCD SPI0_IRQHandler ;12: SPI 0 interrupt
+ DCD I2S0_IRQHandler ;13: I2S 0 interrupt
+ DCD I2S1_IRQHandler ;14: I2S 1 interrupt
+ DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt
+ DCD UART0_IRQHandler ;16: UART 0 intertrupt
+ DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt
+ DCD UART1_IRQHandler ;18: UART 1 intertrupt
+ DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt
+ DCD UART2_IRQHandler ;20: UART 2 intertrupt
+ DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt
+ DCD ADC0_IRQHandler ;22: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt
+ DCD CMP1_IRQHandler ;24: CMP 1 interrupt
+ DCD FTM0_IRQHandler ;25: FTM 0 interrupt
+ DCD FTM1_IRQHandler ;26: FTM 1 interrupt
+ DCD CMT_IRQHandler ;27: CMT intrrupt
+ DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt
+ DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt
+ DCD PIT0_IRQHandler ;30: PIT 0 interrupt
+ DCD PIT1_IRQHandler ;31: PIT 1 interrupt
+ DCD PIT2_IRQHandler ;32: PIT 2 interrupt
+ DCD PIT3_IRQHandler ;33: PIT 3 interrupt
+ DCD PDB_IRQHandler ;34: PDB interrupt
+ DCD USB_OTG_IRQHandler ;35: USB OTG interrupt
+ DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt
+ DCD TSI_IRQHandler ;37: TSI interrupt
+ DCD MCG_IRQHandler ;38: MCG interrupt
+ DCD LPT_IRQHandler ;39: LPT interrupt
+ DCD PORTA_IRQHandler ;40: PORT A interrupt
+ DCD PORTB_IRQHandler ;41: PORT B interrupt
+ DCD PORTC_IRQHandler ;42: PORT C interrupt
+ DCD PORTD_IRQHandler ;43: PORT D interrupt
+ DCD PORTE_IRQHandler ;44: PORT E interrupt
+ DCD SW_IRQHandler ;45: Software initiated interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT^0xFF
+
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK DMA_ERR_IRQHandler
+ PUBWEAK FLASH_CC_IRQHandler
+ PUBWEAK FLASH_RC_IRQHandler
+ PUBWEAK VLD_IRQHandler
+ PUBWEAK LLWU_IRQHandler
+ PUBWEAK WDOG_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK I2S1_IRQHandler
+ PUBWEAK UART0_LON_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART0_ERR_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART1_ERR_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART2_ERR_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK FTM0_IRQHandler
+ PUBWEAK FTM1_IRQHandler
+ PUBWEAK CMT_IRQHandler
+ PUBWEAK RTC_ALRM_IRQHandler
+ PUBWEAK RTC_SEC_IRQHandler
+ PUBWEAK PIT0_IRQHandler
+ PUBWEAK PIT1_IRQHandler
+ PUBWEAK PIT2_IRQHandler
+ PUBWEAK PIT3_IRQHandler
+ PUBWEAK PDB_IRQHandler
+ PUBWEAK USB_OTG_IRQHandler
+ PUBWEAK USB_CD_IRQHandler
+ PUBWEAK TSI_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPT_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+ PUBWEAK PORTC_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+ PUBWEAK PORTE_IRQHandler
+ PUBWEAK SW_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA_ERR_IRQHandler
+FLASH_CC_IRQHandler
+FLASH_RC_IRQHandler
+VLD_IRQHandler
+LLWU_IRQHandler
+WDOG_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+UART0_LON_IRQHandler
+UART0_IRQHandler
+UART0_ERR_IRQHandler
+UART1_IRQHandler
+UART1_ERR_IRQHandler
+UART2_IRQHandler
+UART2_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+CMT_IRQHandler
+RTC_ALRM_IRQHandler
+RTC_SEC_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB_IRQHandler
+USB_OTG_IRQHandler
+USB_CD_IRQHandler
+TSI_IRQHandler
+MCG_IRQHandler
+LPT_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SW_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
new file mode 100644
index 000000000..099017c7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK20D5.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
new file mode 100644
index 000000000..16d1b1f7e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
new file mode 100644
index 000000000..04cf15b21
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
new file mode 100644
index 000000000..9cd3c16b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
@@ -0,0 +1,278 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 1.0, 2011-12-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 1.0
+ * @date 2011-12-15
+ * @brief Device specific configuration file for MK20D5 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK20D5.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 41.94MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 48MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
+ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
+ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06u;
+ /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00u;
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40u;
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1Au;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
new file mode 100644
index 000000000..738791790
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
@@ -0,0 +1,87 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief Device specific configuration file for MK20D5 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK20D5_H_
+#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK20D5_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
new file mode 100644
index 000000000..041f99782
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
@@ -0,0 +1,6032 @@
+/*
+** ###################################################################
+** Processors: MK20DX64VLH7
+** MK20DX128VLH7
+** MK20DX256VLH7
+** MK20DX64VLK7
+** MK20DX128VLK7
+** MK20DX256VLK7
+** MK20DX128VLL7
+** MK20DX256VLL7
+** MK20DX64VMB7
+** MK20DX128VMB7
+** MK20DX256VMB7
+** MK20DX128VML7
+** MK20DX256VML7
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
+** Version: rev. 1.0, 2012-01-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-01-15)
+** Initial public version.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256.h
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief CMSIS Peripheral Access Layer for MK20DX256
+ *
+ * CMSIS Peripheral Access Layer for MK20DX256
+ */
+
+#if !defined(MK20DX256_H_)
+#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */
+#define MCU_MK20DX256
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ DMA4_IRQn = 4,
+ DMA5_IRQn = 5,
+ DMA6_IRQn = 6,
+ DMA7_IRQn = 7,
+ DMA8_IRQn = 8,
+ DMA9_IRQn = 9,
+ DMA10_IRQn = 10,
+ DMA11_IRQn = 11,
+ DMA12_IRQn = 12,
+ DMA13_IRQn = 13,
+ DMA14_IRQn = 14,
+ DMA15_IRQn = 15,
+ DMA_Error_IRQn = 16, /**< DMA error interrupt */
+ Reserved33_IRQn = 17,
+ FTFL_IRQn = 18, /**< FTFL interrupt */
+ Read_Collision_IRQn = 19, /**< Read collision interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG interrupt */
+ Reserved39_IRQn = 23,
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25,
+ SPI0_IRQn = 26, /**< SPI0 interrupt */
+ SPI1_IRQn = 27,
+ Reserved44_IRQn = 28,
+ CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
+ I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
+ Reserved53_IRQn = 37,
+ Reserved54_IRQn = 38,
+ Reserved55_IRQn = 39,
+ Reserved56_IRQn = 40,
+ Reserved57_IRQn = 41,
+ Reserved58_IRQn = 42,
+ Reserved59_IRQn = 43,
+ UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
+ UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
+ UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
+ UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
+ UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
+ UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
+ Reserved67_IRQn = 51,
+ Reserved68_IRQn = 52,
+ Reserved69_IRQn = 53,
+ Reserved70_IRQn = 54,
+ Reserved71_IRQn = 55,
+ Reserved72_IRQn = 56,
+ ADC0_IRQn = 57, /**< ADC0 interrupt */
+ ADC1_IRQn = 58,
+ CMP0_IRQn = 59, /**< CMP0 interrupt */
+ CMP1_IRQn = 60, /**< CMP1 interrupt */
+ CMP2_IRQn = 61,
+ FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 64,
+ CMT_IRQn = 65, /**< CMT interrupt */
+ RTC_IRQn = 66, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
+ PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 72, /**< PDB0 interrupt */
+ USB0_IRQn = 73, /**< USB0 interrupt */
+ USBDCD_IRQn = 74, /**< USBDCD interrupt */
+ Reserved91_IRQn = 75,
+ Reserved92_IRQn = 76,
+ Reserved93_IRQn = 77,
+ Reserved94_IRQn = 78,
+ Reserved95_IRQn = 79,
+ Reserved96_IRQn = 80,
+ DAC0_IRQn = 81,
+ Reserved98_IRQn = 82,
+ TSI0_IRQn = 83, /**< TSI0 interrupt */
+ MCG_IRQn = 84, /**< MCG interrupt */
+ LPTimer_IRQn = 85, /**< LPTimer interrupt */
+ Reserved102_IRQn = 86,
+ PORTA_IRQn = 87, /**< Port A interrupt */
+ PORTB_IRQn = 88, /**< Port B interrupt */
+ PORTC_IRQn = 89, /**< Port C interrupt */
+ PORTD_IRQn = 90, /**< Port D interrupt */
+ PORTE_IRQn = 91, /**< Port E interrupt */
+ Reserved108_IRQn = 92,
+ Reserved109_IRQn = 93,
+ SWI_IRQn = 94 /**< Software interrupt */
+
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK20DX256.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+
+/**
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
+ __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
+ __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
+ __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
+ __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK 0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT 0
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
+/* CRCH Bit Fields */
+#define CRC_CRCH_CRCH_MASK 0xFFFFu
+#define CRC_CRCH_CRCH_SHIFT 0
+#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
+/* CRC Bit Fields */
+#define CRC_CRC_LL_MASK 0xFFu
+#define CRC_CRC_LL_SHIFT 0
+#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK 0xFF00u
+#define CRC_CRC_LU_SHIFT 8
+#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK 0xFF0000u
+#define CRC_CRC_HL_SHIFT 16
+#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK 0xFF000000u
+#define CRC_CRC_HU_SHIFT 24
+#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
+/* CRCLL Bit Fields */
+#define CRC_CRCLL_CRCLL_MASK 0xFFu
+#define CRC_CRCLL_CRCLL_SHIFT 0
+#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
+/* CRCLU Bit Fields */
+#define CRC_CRCLU_CRCLU_MASK 0xFFu
+#define CRC_CRCLU_CRCLU_SHIFT 0
+#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
+/* CRCHL Bit Fields */
+#define CRC_CRCHL_CRCHL_MASK 0xFFu
+#define CRC_CRCHL_CRCHL_SHIFT 0
+#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
+/* CRCHU Bit Fields */
+#define CRC_CRCHU_CRCHU_MASK 0xFFu
+#define CRC_CRCHU_CRCHU_SHIFT 0
+#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/**
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+
+/**
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ uint8_t RESERVED_6[3836];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/**
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+
+/**
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } TAG_WAY[4];
+ uint8_t RESERVED_1[132];
+ struct { /* offset: 0x204, array step: 0x8 */
+ __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW0S[2];
+ uint8_t RESERVED_2[48];
+ struct { /* offset: 0x244, array step: 0x8 */
+ __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW1S[2];
+ uint8_t RESERVED_3[48];
+ struct { /* offset: 0x284, array step: 0x8 */
+ __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW2S[2];
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x2C4, array step: 0x8 */
+ __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW3S[2];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* TAGVD Bit Fields */
+#define FMC_TAGVD_valid_MASK 0x1u
+#define FMC_TAGVD_valid_SHIFT 0
+#define FMC_TAGVD_tag_MASK 0x7FFC0u
+#define FMC_TAGVD_tag_SHIFT 6
+#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
+/* DATAW0S Bit Fields */
+#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW0S_data_SHIFT 0
+#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
+/* DATAW1S Bit Fields */
+#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW1S_data_SHIFT 0
+#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
+/* DATAW2S Bit Fields */
+#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW2S_data_SHIFT 0
+#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
+/* DATAW3S Bit Fields */
+#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW3S_data_SHIFT 0
+#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
+
+/**
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+
+/**
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
+ * @{
+ */
+
+/** FTFL - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Register_Masks FTFL Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFL_FSTAT_MGSTAT0_SHIFT 0
+#define FTFL_FSTAT_FPVIOL_MASK 0x10u
+#define FTFL_FSTAT_FPVIOL_SHIFT 4
+#define FTFL_FSTAT_ACCERR_MASK 0x20u
+#define FTFL_FSTAT_ACCERR_SHIFT 5
+#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFL_FSTAT_RDCOLERR_SHIFT 6
+#define FTFL_FSTAT_CCIF_MASK 0x80u
+#define FTFL_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFL_FCNFG_EEERDY_MASK 0x1u
+#define FTFL_FCNFG_EEERDY_SHIFT 0
+#define FTFL_FCNFG_RAMRDY_MASK 0x2u
+#define FTFL_FCNFG_RAMRDY_SHIFT 1
+#define FTFL_FCNFG_PFLSH_MASK 0x4u
+#define FTFL_FCNFG_PFLSH_SHIFT 2
+#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFL_FCNFG_ERSSUSP_SHIFT 4
+#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFL_FCNFG_ERSAREQ_SHIFT 5
+#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFL_FCNFG_CCIE_MASK 0x80u
+#define FTFL_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFL_FSEC_SEC_MASK 0x3u
+#define FTFL_FSEC_SEC_SHIFT 0
+#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK 0xCu
+#define FTFL_FSEC_FSLACC_SHIFT 2
+#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK 0x30u
+#define FTFL_FSEC_MEEN_SHIFT 4
+#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK 0xC0u
+#define FTFL_FSEC_KEYEN_SHIFT 6
+#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFL_FOPT_OPT_MASK 0xFFu
+#define FTFL_FOPT_OPT_SHIFT 0
+#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB3_CCOBn_SHIFT 0
+#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB2_CCOBn_SHIFT 0
+#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB1_CCOBn_SHIFT 0
+#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB0_CCOBn_SHIFT 0
+#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB7_CCOBn_SHIFT 0
+#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB6_CCOBn_SHIFT 0
+#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB5_CCOBn_SHIFT 0
+#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB4_CCOBn_SHIFT 0
+#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBB_CCOBn_SHIFT 0
+#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBA_CCOBn_SHIFT 0
+#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB9_CCOBn_SHIFT 0
+#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB8_CCOBn_SHIFT 0
+#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFL_FPROT3_PROT_MASK 0xFFu
+#define FTFL_FPROT3_PROT_SHIFT 0
+#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFL_FPROT2_PROT_MASK 0xFFu
+#define FTFL_FPROT2_PROT_SHIFT 0
+#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFL_FPROT1_PROT_MASK 0xFFu
+#define FTFL_FPROT1_PROT_SHIFT 0
+#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFL_FPROT0_PROT_MASK 0xFFu
+#define FTFL_FPROT0_PROT_SHIFT 0
+#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFL_FEPROT_EPROT_MASK 0xFFu
+#define FTFL_FEPROT_EPROT_SHIFT 0
+#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFL_FDPROT_DPROT_MASK 0xFFu
+#define FTFL_FDPROT_DPROT_SHIFT 0
+#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/** Peripheral FTFL base address */
+#define FTFL_BASE (0x40020000u)
+/** Peripheral FTFL base pointer */
+#define FTFL ((FTFL_Type *)FTFL_BASE)
+
+/**
+ * @}
+ */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/**
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+
+/**
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x1u
+#define MCG_C7_OSCSEL_SHIFT 0
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE (0x400u)
+/** Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x10 */
+ __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
+ __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
+ } CH[1];
+ uint8_t RESERVED_0[368];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/**
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+
+/**
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
+ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
+ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT 2
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_DAC0_MASK 0x1000u
+#define SIM_SCGC2_DAC0_SHIFT 12
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_FTM2_MASK 0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT 24
+#define SIM_SCGC3_ADC1_MASK 0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT 27
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTIMER_MASK 0x1u
+#define SIM_SCGC5_LPTIMER_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTFL_MASK 0x1u
+#define SIM_SCGC6_FTFL_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT 4
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK 0x1u
+#define TSI_GENCS_STPE_SHIFT 0
+#define TSI_GENCS_STM_MASK 0x2u
+#define TSI_GENCS_STM_SHIFT 1
+#define TSI_GENCS_ESOR_MASK 0x10u
+#define TSI_GENCS_ESOR_SHIFT 4
+#define TSI_GENCS_ERIE_MASK 0x20u
+#define TSI_GENCS_ERIE_SHIFT 5
+#define TSI_GENCS_TSIIE_MASK 0x40u
+#define TSI_GENCS_TSIIE_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_SWTS_MASK 0x100u
+#define TSI_GENCS_SWTS_SHIFT 8
+#define TSI_GENCS_SCNIP_MASK 0x200u
+#define TSI_GENCS_SCNIP_SHIFT 9
+#define TSI_GENCS_OVRF_MASK 0x1000u
+#define TSI_GENCS_OVRF_SHIFT 12
+#define TSI_GENCS_EXTERF_MASK 0x2000u
+#define TSI_GENCS_EXTERF_SHIFT 13
+#define TSI_GENCS_OUTRGF_MASK 0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT 14
+#define TSI_GENCS_EOSF_MASK 0x8000u
+#define TSI_GENCS_EOSF_SHIFT 15
+#define TSI_GENCS_PS_MASK 0x70000u
+#define TSI_GENCS_PS_SHIFT 16
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK 0xF80000u
+#define TSI_GENCS_NSCN_SHIFT 19
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
+#define TSI_GENCS_LPSCNITV_SHIFT 24
+#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK 0x10000000u
+#define TSI_GENCS_LPCLKS_SHIFT 28
+/* SCANC Bit Fields */
+#define TSI_SCANC_AMPSC_MASK 0x7u
+#define TSI_SCANC_AMPSC_SHIFT 0
+#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK 0x18u
+#define TSI_SCANC_AMCLKS_SHIFT 3
+#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK 0xFF00u
+#define TSI_SCANC_SMOD_SHIFT 8
+#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
+#define TSI_SCANC_EXTCHRG_SHIFT 16
+#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK 0xF000000u
+#define TSI_SCANC_REFCHRG_SHIFT 24
+#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
+/* PEN Bit Fields */
+#define TSI_PEN_PEN0_MASK 0x1u
+#define TSI_PEN_PEN0_SHIFT 0
+#define TSI_PEN_PEN1_MASK 0x2u
+#define TSI_PEN_PEN1_SHIFT 1
+#define TSI_PEN_PEN2_MASK 0x4u
+#define TSI_PEN_PEN2_SHIFT 2
+#define TSI_PEN_PEN3_MASK 0x8u
+#define TSI_PEN_PEN3_SHIFT 3
+#define TSI_PEN_PEN4_MASK 0x10u
+#define TSI_PEN_PEN4_SHIFT 4
+#define TSI_PEN_PEN5_MASK 0x20u
+#define TSI_PEN_PEN5_SHIFT 5
+#define TSI_PEN_PEN6_MASK 0x40u
+#define TSI_PEN_PEN6_SHIFT 6
+#define TSI_PEN_PEN7_MASK 0x80u
+#define TSI_PEN_PEN7_SHIFT 7
+#define TSI_PEN_PEN8_MASK 0x100u
+#define TSI_PEN_PEN8_SHIFT 8
+#define TSI_PEN_PEN9_MASK 0x200u
+#define TSI_PEN_PEN9_SHIFT 9
+#define TSI_PEN_PEN10_MASK 0x400u
+#define TSI_PEN_PEN10_SHIFT 10
+#define TSI_PEN_PEN11_MASK 0x800u
+#define TSI_PEN_PEN11_SHIFT 11
+#define TSI_PEN_PEN12_MASK 0x1000u
+#define TSI_PEN_PEN12_SHIFT 12
+#define TSI_PEN_PEN13_MASK 0x2000u
+#define TSI_PEN_PEN13_SHIFT 13
+#define TSI_PEN_PEN14_MASK 0x4000u
+#define TSI_PEN_PEN14_SHIFT 14
+#define TSI_PEN_PEN15_MASK 0x8000u
+#define TSI_PEN_PEN15_SHIFT 15
+#define TSI_PEN_LPSP_MASK 0xF0000u
+#define TSI_PEN_LPSP_SHIFT 16
+#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
+/* WUCNTR Bit Fields */
+#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
+#define TSI_WUCNTR_WUCNT_SHIFT 0
+#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
+/* CNTR1 Bit Fields */
+#define TSI_CNTR1_CTN1_MASK 0xFFFFu
+#define TSI_CNTR1_CTN1_SHIFT 0
+#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR1_CTN_SHIFT 16
+#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
+/* CNTR3 Bit Fields */
+#define TSI_CNTR3_CTN1_MASK 0xFFFFu
+#define TSI_CNTR3_CTN1_SHIFT 0
+#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR3_CTN_SHIFT 16
+#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
+/* CNTR5 Bit Fields */
+#define TSI_CNTR5_CTN1_MASK 0xFFFFu
+#define TSI_CNTR5_CTN1_SHIFT 0
+#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR5_CTN_SHIFT 16
+#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
+/* CNTR7 Bit Fields */
+#define TSI_CNTR7_CTN1_MASK 0xFFFFu
+#define TSI_CNTR7_CTN1_SHIFT 0
+#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR7_CTN_SHIFT 16
+#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
+/* CNTR9 Bit Fields */
+#define TSI_CNTR9_CTN1_MASK 0xFFFFu
+#define TSI_CNTR9_CTN1_SHIFT 0
+#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR9_CTN_SHIFT 16
+#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
+/* CNTR11 Bit Fields */
+#define TSI_CNTR11_CTN1_MASK 0xFFFFu
+#define TSI_CNTR11_CTN1_SHIFT 0
+#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR11_CTN_SHIFT 16
+#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
+/* CNTR13 Bit Fields */
+#define TSI_CNTR13_CTN1_MASK 0xFFFFu
+#define TSI_CNTR13_CTN1_SHIFT 0
+#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR13_CTN_SHIFT 16
+#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
+/* CNTR15 Bit Fields */
+#define TSI_CNTR15_CTN1_MASK 0xFFFFu
+#define TSI_CNTR15_CTN1_SHIFT 0
+#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR15_CTN_SHIFT 16
+#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
+/* THRESHOLD Bit Fields */
+#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
+#define TSI_THRESHOLD_HTHH_SHIFT 0
+#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
+#define TSI_THRESHOLD_LTHH_SHIFT 16
+#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
+ __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
+ __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
+ __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
+ __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
+ __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
+ __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
+ __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
+ __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
+ __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
+ __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
+ __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
+ __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
+ __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
+ __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
+ __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
+ __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT 0
+#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
+#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
+#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* C6 Bit Fields */
+#define UART_C6_CP_MASK 0x10u
+#define UART_C6_CP_SHIFT 4
+#define UART_C6_CE_MASK 0x20u
+#define UART_C6_CE_SHIFT 5
+#define UART_C6_TX709_MASK 0x40u
+#define UART_C6_TX709_SHIFT 6
+#define UART_C6_EN709_MASK 0x80u
+#define UART_C6_EN709_SHIFT 7
+/* PCTH Bit Fields */
+#define UART_PCTH_PCTH_MASK 0xFFu
+#define UART_PCTH_PCTH_SHIFT 0
+#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
+/* PCTL Bit Fields */
+#define UART_PCTL_PCTL_MASK 0xFFu
+#define UART_PCTL_PCTL_SHIFT 0
+#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
+/* B1T Bit Fields */
+#define UART_B1T_B1T_MASK 0xFFu
+#define UART_B1T_B1T_SHIFT 0
+#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
+/* SDTH Bit Fields */
+#define UART_SDTH_SDTH_MASK 0xFFu
+#define UART_SDTH_SDTH_SHIFT 0
+#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
+/* SDTL Bit Fields */
+#define UART_SDTL_SDTL_MASK 0xFFu
+#define UART_SDTL_SDTL_SHIFT 0
+#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
+/* PRE Bit Fields */
+#define UART_PRE_PREAMBLE_MASK 0xFFu
+#define UART_PRE_PREAMBLE_SHIFT 0
+#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
+/* TPL Bit Fields */
+#define UART_TPL_TPL_MASK 0xFFu
+#define UART_TPL_TPL_SHIFT 0
+#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
+/* IE Bit Fields */
+#define UART_IE_TXFIE_MASK 0x1u
+#define UART_IE_TXFIE_SHIFT 0
+#define UART_IE_PSIE_MASK 0x2u
+#define UART_IE_PSIE_SHIFT 1
+#define UART_IE_PCTEIE_MASK 0x4u
+#define UART_IE_PCTEIE_SHIFT 2
+#define UART_IE_PTXIE_MASK 0x8u
+#define UART_IE_PTXIE_SHIFT 3
+#define UART_IE_PRXIE_MASK 0x10u
+#define UART_IE_PRXIE_SHIFT 4
+#define UART_IE_ISDIE_MASK 0x20u
+#define UART_IE_ISDIE_SHIFT 5
+#define UART_IE_WBEIE_MASK 0x40u
+#define UART_IE_WBEIE_SHIFT 6
+/* WB Bit Fields */
+#define UART_WB_WBASE_MASK 0xFFu
+#define UART_WB_WBASE_SHIFT 0
+#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
+/* S3 Bit Fields */
+#define UART_S3_TXFF_MASK 0x1u
+#define UART_S3_TXFF_SHIFT 0
+#define UART_S3_PSF_MASK 0x2u
+#define UART_S3_PSF_SHIFT 1
+#define UART_S3_PCTEF_MASK 0x4u
+#define UART_S3_PCTEF_SHIFT 2
+#define UART_S3_PTXF_MASK 0x8u
+#define UART_S3_PTXF_SHIFT 3
+#define UART_S3_PRXF_MASK 0x10u
+#define UART_S3_PRXF_SHIFT 4
+#define UART_S3_ISD_MASK 0x20u
+#define UART_S3_ISD_SHIFT 5
+#define UART_S3_WBEF_MASK 0x40u
+#define UART_S3_WBEF_SHIFT 6
+#define UART_S3_PEF_MASK 0x80u
+#define UART_S3_PEF_SHIFT 7
+/* S4 Bit Fields */
+#define UART_S4_FE_MASK 0x1u
+#define UART_S4_FE_SHIFT 0
+#define UART_S4_ILCV_MASK 0x2u
+#define UART_S4_ILCV_SHIFT 1
+#define UART_S4_CDET_MASK 0xCu
+#define UART_S4_CDET_SHIFT 2
+#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK 0x10u
+#define UART_S4_INITF_SHIFT 4
+/* RPL Bit Fields */
+#define UART_RPL_RPL_MASK 0xFFu
+#define UART_RPL_RPL_SHIFT 0
+#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
+/* RPREL Bit Fields */
+#define UART_RPREL_RPREL_MASK 0xFFu
+#define UART_RPREL_RPREL_SHIFT 0
+#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
+/* CPW Bit Fields */
+#define UART_CPW_CPW_MASK 0xFFu
+#define UART_CPW_CPW_SHIFT 0
+#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
+/* RIDT Bit Fields */
+#define UART_RIDT_RIDT_MASK 0xFFu
+#define UART_RIDT_RIDT_SHIFT 0
+#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
+/* TIDT Bit Fields */
+#define UART_TIDT_TIDT_MASK 0xFFu
+#define UART_TIDT_TIDT_SHIFT 0
+#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status Register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< , offset: 0x14 */
+ __IO uint32_t TIMER2; /**< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2 Bit Fields */
+#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+
+/**
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/**
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+
+/**
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MK20D5_H_) */
+
+/* MK20D5.h, eof. */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
new file mode 100644
index 000000000..8e8908c28
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(112 vect * 4 bytes) = 8_byte_aligned(0x1C0) = 0x1C0
+ ; 0x10000 - 0x1C0 = 0xFE40
+ RW_IRAM1 0x1FFF81C0 0xFE40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
new file mode 100644
index 000000000..cbbc94aaa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
@@ -0,0 +1,559 @@
+;/*****************************************************************************
+; * @file: startup_MK20DX256.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK20DX256
+; * @version: 1.0
+; * @date: 2011-12-15
+; *
+; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20008000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt
+ DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt
+ DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt
+ DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt
+ DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt
+ DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt
+ DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt
+ DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt
+ DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt
+ DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt
+ DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt
+ DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt
+ DCD DMA_Error_IRQHandler ; DMA error interrupt
+ DCD Reserved33_IRQHandler ; Reserved interrupt 33
+ DCD FTFL_IRQHandler ; FTFL interrupt
+ DCD Read_Collision_IRQHandler ; Read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD Reserved44_IRQHandler ; Reserved interrupt 44
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD Reserved53_IRQHandler ; Reserved interrupt 53
+ DCD Reserved54_IRQHandler ; Reserved interrupt 54
+ DCD Reserved55_IRQHandler ; Reserved interrupt 55
+ DCD Reserved56_IRQHandler ; Reserved interrupt 56
+ DCD Reserved57_IRQHandler ; Reserved interrupt 57
+ DCD Reserved58_IRQHandler ; Reserved interrupt 58
+ DCD Reserved59_IRQHandler ; Reserved interrupt 59
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 error interrupt
+ DCD Reserved67_IRQHandler ; Reserved interrupt 67
+ DCD Reserved68_IRQHandler ; Reserved interrupt 68
+ DCD Reserved69_IRQHandler ; Reserved interrupt 69
+ DCD Reserved70_IRQHandler ; Reserved interrupt 70
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD Reserved72_IRQHandler ; Reserved interrupt 72
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD interrupt
+ DCD Reserved91_IRQHandler ; Reserved interrupt 91
+ DCD Reserved92_IRQHandler ; Reserved interrupt 92
+ DCD Reserved93_IRQHandler ; Reserved interrupt 93
+ DCD Reserved94_IRQHandler ; Reserved interrupt 94
+ DCD Reserved95_IRQHandler ; Reserved interrupt 95
+ DCD Reserved96_IRQHandler ; Reserved interrupt 96
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD Reserved98_IRQHandler ; Reserved interrupt 98
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved102_IRQHandler ; Reserved interrupt 102
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD Reserved108_IRQHandler ; Reserved interrupt 108
+ DCD Reserved109_IRQHandler ; Reserved interrupt 109
+ DCD SWI_IRQHandler ; Software interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA4_IRQHandler [WEAK]
+ EXPORT DMA5_IRQHandler [WEAK]
+ EXPORT DMA6_IRQHandler [WEAK]
+ EXPORT DMA7_IRQHandler [WEAK]
+ EXPORT DMA8_IRQHandler [WEAK]
+ EXPORT DMA9_IRQHandler [WEAK]
+ EXPORT DMA10_IRQHandler [WEAK]
+ EXPORT DMA11_IRQHandler [WEAK]
+ EXPORT DMA12_IRQHandler [WEAK]
+ EXPORT DMA13_IRQHandler [WEAK]
+ EXPORT DMA14_IRQHandler [WEAK]
+ EXPORT DMA15_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT Reserved33_IRQHandler [WEAK]
+ EXPORT FTFL_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT Reserved44_IRQHandler [WEAK]
+ EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
+ EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
+ EXPORT CAN0_Error_IRQHandler [WEAK]
+ EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT Reserved53_IRQHandler [WEAK]
+ EXPORT Reserved54_IRQHandler [WEAK]
+ EXPORT Reserved55_IRQHandler [WEAK]
+ EXPORT Reserved56_IRQHandler [WEAK]
+ EXPORT Reserved57_IRQHandler [WEAK]
+ EXPORT Reserved58_IRQHandler [WEAK]
+ EXPORT Reserved59_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT Reserved67_IRQHandler [WEAK]
+ EXPORT Reserved68_IRQHandler [WEAK]
+ EXPORT Reserved69_IRQHandler [WEAK]
+ EXPORT Reserved70_IRQHandler [WEAK]
+ EXPORT Reserved71_IRQHandler [WEAK]
+ EXPORT Reserved72_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT FTM2_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT Reserved91_IRQHandler [WEAK]
+ EXPORT Reserved92_IRQHandler [WEAK]
+ EXPORT Reserved93_IRQHandler [WEAK]
+ EXPORT Reserved94_IRQHandler [WEAK]
+ EXPORT Reserved95_IRQHandler [WEAK]
+ EXPORT Reserved96_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT Reserved98_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved102_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT Reserved108_IRQHandler [WEAK]
+ EXPORT Reserved109_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+Reserved33_IRQHandler
+FTFL_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+Reserved39_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+Reserved44_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+Reserved53_IRQHandler
+Reserved54_IRQHandler
+Reserved55_IRQHandler
+Reserved56_IRQHandler
+Reserved57_IRQHandler
+Reserved58_IRQHandler
+Reserved59_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+Reserved72_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved91_IRQHandler
+Reserved92_IRQHandler
+Reserved93_IRQHandler
+Reserved94_IRQHandler
+Reserved95_IRQHandler
+Reserved96_IRQHandler
+DAC0_IRQHandler
+Reserved98_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved102_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+Reserved108_IRQHandler
+Reserved109_IRQHandler
+SWI_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..3296df192
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
new file mode 100644
index 000000000..3a40be864
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
@@ -0,0 +1,164 @@
+/*
+ * K20DX256 ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ . = 0;
+ __isr_vector = .;
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
new file mode 100644
index 000000000..e54559a4d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
@@ -0,0 +1,366 @@
+/* File: startup_MK20DX256.s
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 08 Feb 2012
+ *
+ * Copyright (c) 2015, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0xC00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA_Error_IRQHandler // DMA error interrupt
+ .long Reserved33_IRQHandler // Reserved interrupt 33
+ .long FTFL_IRQHandler // FTFL interrupt
+ .long Read_Collision_IRQHandler // Read collision interrupt
+ .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning
+ .long LLW_IRQHandler // Low Leakage Wakeup
+ .long Watchdog_IRQHandler // WDOG interrupt
+ .long Reserved39_IRQHandler // Reserved interrupt 39
+ .long I2C0_IRQHandler // I2C0 interrupt
+ .long I2C1_IRQHandler // I2C1 interrupt
+ .long SPI0_IRQHandler // SPI0 interrupt
+ .long SPI1_IRQHandler // SPI1 interrupt
+ .long Reserved44_IRQHandler // Reserved interrupt 44
+ .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt
+ .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt
+ .long CAN0_Error_IRQHandler // CAN0 error interrupt
+ .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt
+ .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt
+ .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt
+ .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt
+ .long I2S0_Rx_IRQHandler // I2S0 receive interrupt
+ .long Reserved53_IRQHandler // Reserved interrupt 53
+ .long Reserved54_IRQHandler // Reserved interrupt 54
+ .long Reserved55_IRQHandler // Reserved interrupt 55
+ .long Reserved56_IRQHandler // Reserved interrupt 56
+ .long Reserved57_IRQHandler // Reserved interrupt 57
+ .long Reserved58_IRQHandler // Reserved interrupt 58
+ .long Reserved59_IRQHandler // Reserved interrupt 59
+ .long UART0_LON_IRQHandler // UART0 LON interrupt
+ .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt
+ .long UART0_ERR_IRQHandler // UART0 error interrupt
+ .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt
+ .long UART1_ERR_IRQHandler // UART1 error interrupt
+ .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt
+ .long UART2_ERR_IRQHandler // UART2 error interrupt
+ .long Reserved67_IRQHandler // Reserved interrupt 67
+ .long Reserved68_IRQHandler // Reserved interrupt 68
+ .long Reserved69_IRQHandler // Reserved interrupt 69
+ .long Reserved70_IRQHandler // Reserved interrupt 70
+ .long Reserved71_IRQHandler // Reserved interrupt 71
+ .long Reserved72_IRQHandler // Reserved interrupt 72
+ .long ADC0_IRQHandler // ADC0 interrupt
+ .long ADC1_IRQHandler // ADC1 interrupt
+ .long CMP0_IRQHandler // CMP0 interrupt
+ .long CMP1_IRQHandler // CMP1 interrupt
+ .long CMP2_IRQHandler // CMP2 interrupt
+ .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt
+ .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt
+ .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt
+ .long CMT_IRQHandler // CMT interrupt
+ .long RTC_IRQHandler // RTC interrupt
+ .long RTC_Seconds_IRQHandler // RTC seconds interrupt
+ .long PIT0_IRQHandler // PIT timer channel 0 interrupt
+ .long PIT1_IRQHandler // PIT timer channel 1 interrupt
+ .long PIT2_IRQHandler // PIT timer channel 2 interrupt
+ .long PIT3_IRQHandler // PIT timer channel 3 interrupt
+ .long PDB0_IRQHandler // PDB0 interrupt
+ .long USB0_IRQHandler // USB0 interrupt
+ .long USBDCD_IRQHandler // USBDCD interrupt
+ .long Reserved91_IRQHandler // Reserved interrupt 91
+ .long Reserved92_IRQHandler // Reserved interrupt 92
+ .long Reserved93_IRQHandler // Reserved interrupt 93
+ .long Reserved94_IRQHandler // Reserved interrupt 94
+ .long Reserved95_IRQHandler // Reserved interrupt 95
+ .long Reserved96_IRQHandler // Reserved interrupt 96
+ .long DAC0_IRQHandler // DAC0 interrupt
+ .long Reserved98_IRQHandler // Reserved interrupt 98
+ .long TSI0_IRQHandler // TSI0 interrupt
+ .long MCG_IRQHandler // MCG interrupt
+ .long LPTimer_IRQHandler // LPTimer interrupt
+ .long Reserved102_IRQHandler // Reserved interrupt 102
+ .long PORTA_IRQHandler // Port A interrupt
+ .long PORTB_IRQHandler // Port B interrupt
+ .long PORTC_IRQHandler // Port C interrupt
+ .long PORTD_IRQHandler // Port D interrupt
+ .long PORTE_IRQHandler // Port E interrupt
+ .long Reserved108_IRQHandler // Reserved interrupt 108
+ .long Reserved109_IRQHandler // Reserved interrupt 109
+ .long SWI_IRQHandler // Software interrupt
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/*
+ * Call SystemInit before loading the .data section to prevent the watchdog
+ * from resetting the board.
+ */
+ ldr r0, =SystemInit
+ blx r0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA4_IRQHandler
+ def_irq_default_handler DMA5_IRQHandler
+ def_irq_default_handler DMA6_IRQHandler
+ def_irq_default_handler DMA7_IRQHandler
+ def_irq_default_handler DMA8_IRQHandler
+ def_irq_default_handler DMA9_IRQHandler
+ def_irq_default_handler DMA10_IRQHandler
+ def_irq_default_handler DMA11_IRQHandler
+ def_irq_default_handler DMA12_IRQHandler
+ def_irq_default_handler DMA13_IRQHandler
+ def_irq_default_handler DMA14_IRQHandler
+ def_irq_default_handler DMA15_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler Reserved33_IRQHandler
+ def_irq_default_handler FTFL_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler Reserved39_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler Reserved44_IRQHandler
+ def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
+ def_irq_default_handler CAN0_Bus_Off_IRQHandler
+ def_irq_default_handler CAN0_Error_IRQHandler
+ def_irq_default_handler CAN0_Tx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Rx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Wake_Up_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler Reserved53_IRQHandler
+ def_irq_default_handler Reserved54_IRQHandler
+ def_irq_default_handler Reserved55_IRQHandler
+ def_irq_default_handler Reserved56_IRQHandler
+ def_irq_default_handler Reserved57_IRQHandler
+ def_irq_default_handler Reserved58_IRQHandler
+ def_irq_default_handler Reserved59_IRQHandler
+ def_irq_default_handler UART0_LON_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler Reserved67_IRQHandler
+ def_irq_default_handler Reserved68_IRQHandler
+ def_irq_default_handler Reserved69_IRQHandler
+ def_irq_default_handler Reserved70_IRQHandler
+ def_irq_default_handler Reserved71_IRQHandler
+ def_irq_default_handler Reserved72_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler CMP2_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler FTM2_IRQHandler
+ def_irq_default_handler CMT_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USBDCD_IRQHandler
+ def_irq_default_handler Reserved91_IRQHandler
+ def_irq_default_handler Reserved92_IRQHandler
+ def_irq_default_handler Reserved93_IRQHandler
+ def_irq_default_handler Reserved94_IRQHandler
+ def_irq_default_handler Reserved95_IRQHandler
+ def_irq_default_handler Reserved96_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler Reserved98_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler Reserved102_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler Reserved108_IRQHandler
+ def_irq_default_handler Reserved109_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler DefaultISR
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
new file mode 100644
index 000000000..86440692b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK20DX256.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
new file mode 100644
index 000000000..8148ba87f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2012 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
new file mode 100644
index 000000000..ce9de13c9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
new file mode 100644
index 000000000..4f34cc76c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
@@ -0,0 +1,309 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+**
+**
+** Version: rev. 1.0, 2011-12-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256
+ * @version 1.0
+ * @date 2011-12-15
+ * @brief Device specific configuration file for MK20DX256 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK20DX256.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 3
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 41.94MHz
+ This works on Teensy3.1
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 48MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+ 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 16MHz
+ Core clock = 72MHz, BusClock = 48MHz
+ This is the default Teensy3.1 72Mhz set up
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 3)
+ #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+void SystemInit (void) {
+ /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
+
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
+ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
+ /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00u;
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
+ while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
+
+#elif (CLOCK_SETUP == 1)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2);
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = MCG_C5_PRDIV0(3);
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to PBE Mode */
+ /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = MCG_C5_PRDIV0(3);
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
+ MCG->C6 = MCG_C6_PLLS_MASK;
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+
+#elif (CLOCK_SETUP == 2)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to BLPE Mode */
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+
+#elif (CLOCK_SETUP == 3)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
+ OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
+ /* Switch to FBE Mode */
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+ //MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
+ MCG->C5 = MCG_C5_PRDIV0(7);
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to PBE Mode */
+ /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
+ MCG->C5 = MCG_C5_PRDIV0(5);
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
+ MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+#endif /* (CLOCK_SETUP) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
new file mode 100644
index 000000000..3c916d038
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
@@ -0,0 +1,85 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+**
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief Device specific configuration file for MK20DX256 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK20DX256_H_
+#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK20DX256_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
new file mode 100644
index 000000000..fd48b0f8c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
@@ -0,0 +1,10137 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140604
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK22F51212
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212.h
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief CMSIS Peripheral Access Layer for MK22F51212
+ *
+ * CMSIS Peripheral Access Layer for MK22F51212
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */
+#define MK22F51212_H_
+#define MCU_MK22F51212
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
+ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
+ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
+ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
+ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
+ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
+ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
+ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
+ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
+ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
+ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
+ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
+ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
+ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
+ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
+ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTF_IRQn = 18, /**< FTFA Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
+ Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTimer_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
+ Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
+ Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
+ Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
+ Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
+ Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
+ Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
+ Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
+ Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
+ Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
+ Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
+ Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
+ Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
+ Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
+ Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
+ Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
+ Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK22F51212.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x40027000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
+#define ADC1_RA ADC_R_REG(ADC1,0)
+#define ADC1_RB ADC_R_REG(ADC1,1)
+#define ADC1_CV1 ADC_CV1_REG(ADC1)
+#define ADC1_CV2 ADC_CV2_REG(ADC1)
+#define ADC1_SC2 ADC_SC2_REG(ADC1)
+#define ADC1_SC3 ADC_SC3_REG(ADC1)
+#define ADC1_OFS ADC_OFS_REG(ADC1)
+#define ADC1_PG ADC_PG_REG(ADC1)
+#define ADC1_MG ADC_MG_REG(ADC1)
+#define ADC1_CLPD ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+#define ADC1_R(index) ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR (CMP1)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0, CMP1 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0 CMP_CR0_REG(CMP1)
+#define CMP1_CR1 CMP_CR1_REG(CMP1)
+#define CMP1_FPR CMP_FPR_REG(CMP1)
+#define CMP1_SCR CMP_SCR_REG(CMP1)
+#define CMP1_DACCR CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base) ((base)->DATA)
+#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base) ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base) ((base)->CTRL)
+#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK 0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT 0
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK 0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT 0
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK 0xFFu
+#define CRC_DATA_LL_SHIFT 0
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK 0xFF00u
+#define CRC_DATA_LU_SHIFT 8
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK 0xFF0000u
+#define CRC_DATA_HL_SHIFT 16
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK 0xFF000000u
+#define CRC_DATA_HU_SHIFT 24
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK 0xFFu
+#define CRC_DATALL_DATALL_SHIFT 0
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK 0xFFu
+#define CRC_DATALU_DATALU_SHIFT 0
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK 0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT 0
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK 0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT 0
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC0 }
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA CRC_DATA_REG(CRC0)
+#define CRC_DATAL CRC_DATAL_REG(CRC0)
+#define CRC_DATALL CRC_DATALL_REG(CRC0)
+#define CRC_DATALU CRC_DATALU_REG(CRC0)
+#define CRC_DATAH CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE (0x40028000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1 ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
+#define DAC1_SR DAC_SR_REG(DAC1)
+#define DAC1_C0 DAC_C0_REG(DAC1)
+#define DAC1_C1 DAC_C1_REG(DAC1)
+#define DAC1_C2 DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+ uint8_t RESERVED_6[184];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
+ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
+ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
+ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
+ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
+ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
+ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
+ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
+ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
+ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
+ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
+ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
+ uint8_t RESERVED_7[3824];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base) ((base)->CR)
+#define DMA_ES_REG(base) ((base)->ES)
+#define DMA_ERQ_REG(base) ((base)->ERQ)
+#define DMA_EEI_REG(base) ((base)->EEI)
+#define DMA_CEEI_REG(base) ((base)->CEEI)
+#define DMA_SEEI_REG(base) ((base)->SEEI)
+#define DMA_CERQ_REG(base) ((base)->CERQ)
+#define DMA_SERQ_REG(base) ((base)->SERQ)
+#define DMA_CDNE_REG(base) ((base)->CDNE)
+#define DMA_SSRT_REG(base) ((base)->SSRT)
+#define DMA_CERR_REG(base) ((base)->CERR)
+#define DMA_CINT_REG(base) ((base)->CINT)
+#define DMA_INT_REG(base) ((base)->INT)
+#define DMA_ERR_REG(base) ((base)->ERR)
+#define DMA_HRS_REG(base) ((base)->HRS)
+#define DMA_EARS_REG(base) ((base)->EARS)
+#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+#define DMA_ERQ_ERQ4_MASK 0x10u
+#define DMA_ERQ_ERQ4_SHIFT 4
+#define DMA_ERQ_ERQ5_MASK 0x20u
+#define DMA_ERQ_ERQ5_SHIFT 5
+#define DMA_ERQ_ERQ6_MASK 0x40u
+#define DMA_ERQ_ERQ6_SHIFT 6
+#define DMA_ERQ_ERQ7_MASK 0x80u
+#define DMA_ERQ_ERQ7_SHIFT 7
+#define DMA_ERQ_ERQ8_MASK 0x100u
+#define DMA_ERQ_ERQ8_SHIFT 8
+#define DMA_ERQ_ERQ9_MASK 0x200u
+#define DMA_ERQ_ERQ9_SHIFT 9
+#define DMA_ERQ_ERQ10_MASK 0x400u
+#define DMA_ERQ_ERQ10_SHIFT 10
+#define DMA_ERQ_ERQ11_MASK 0x800u
+#define DMA_ERQ_ERQ11_SHIFT 11
+#define DMA_ERQ_ERQ12_MASK 0x1000u
+#define DMA_ERQ_ERQ12_SHIFT 12
+#define DMA_ERQ_ERQ13_MASK 0x2000u
+#define DMA_ERQ_ERQ13_SHIFT 13
+#define DMA_ERQ_ERQ14_MASK 0x4000u
+#define DMA_ERQ_ERQ14_SHIFT 14
+#define DMA_ERQ_ERQ15_MASK 0x8000u
+#define DMA_ERQ_ERQ15_SHIFT 15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+#define DMA_EEI_EEI4_MASK 0x10u
+#define DMA_EEI_EEI4_SHIFT 4
+#define DMA_EEI_EEI5_MASK 0x20u
+#define DMA_EEI_EEI5_SHIFT 5
+#define DMA_EEI_EEI6_MASK 0x40u
+#define DMA_EEI_EEI6_SHIFT 6
+#define DMA_EEI_EEI7_MASK 0x80u
+#define DMA_EEI_EEI7_SHIFT 7
+#define DMA_EEI_EEI8_MASK 0x100u
+#define DMA_EEI_EEI8_SHIFT 8
+#define DMA_EEI_EEI9_MASK 0x200u
+#define DMA_EEI_EEI9_SHIFT 9
+#define DMA_EEI_EEI10_MASK 0x400u
+#define DMA_EEI_EEI10_SHIFT 10
+#define DMA_EEI_EEI11_MASK 0x800u
+#define DMA_EEI_EEI11_SHIFT 11
+#define DMA_EEI_EEI12_MASK 0x1000u
+#define DMA_EEI_EEI12_SHIFT 12
+#define DMA_EEI_EEI13_MASK 0x2000u
+#define DMA_EEI_EEI13_SHIFT 13
+#define DMA_EEI_EEI14_MASK 0x4000u
+#define DMA_EEI_EEI14_SHIFT 14
+#define DMA_EEI_EEI15_MASK 0x8000u
+#define DMA_EEI_EEI15_SHIFT 15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+#define DMA_INT_INT4_MASK 0x10u
+#define DMA_INT_INT4_SHIFT 4
+#define DMA_INT_INT5_MASK 0x20u
+#define DMA_INT_INT5_SHIFT 5
+#define DMA_INT_INT6_MASK 0x40u
+#define DMA_INT_INT6_SHIFT 6
+#define DMA_INT_INT7_MASK 0x80u
+#define DMA_INT_INT7_SHIFT 7
+#define DMA_INT_INT8_MASK 0x100u
+#define DMA_INT_INT8_SHIFT 8
+#define DMA_INT_INT9_MASK 0x200u
+#define DMA_INT_INT9_SHIFT 9
+#define DMA_INT_INT10_MASK 0x400u
+#define DMA_INT_INT10_SHIFT 10
+#define DMA_INT_INT11_MASK 0x800u
+#define DMA_INT_INT11_SHIFT 11
+#define DMA_INT_INT12_MASK 0x1000u
+#define DMA_INT_INT12_SHIFT 12
+#define DMA_INT_INT13_MASK 0x2000u
+#define DMA_INT_INT13_SHIFT 13
+#define DMA_INT_INT14_MASK 0x4000u
+#define DMA_INT_INT14_SHIFT 14
+#define DMA_INT_INT15_MASK 0x8000u
+#define DMA_INT_INT15_SHIFT 15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+#define DMA_ERR_ERR4_MASK 0x10u
+#define DMA_ERR_ERR4_SHIFT 4
+#define DMA_ERR_ERR5_MASK 0x20u
+#define DMA_ERR_ERR5_SHIFT 5
+#define DMA_ERR_ERR6_MASK 0x40u
+#define DMA_ERR_ERR6_SHIFT 6
+#define DMA_ERR_ERR7_MASK 0x80u
+#define DMA_ERR_ERR7_SHIFT 7
+#define DMA_ERR_ERR8_MASK 0x100u
+#define DMA_ERR_ERR8_SHIFT 8
+#define DMA_ERR_ERR9_MASK 0x200u
+#define DMA_ERR_ERR9_SHIFT 9
+#define DMA_ERR_ERR10_MASK 0x400u
+#define DMA_ERR_ERR10_SHIFT 10
+#define DMA_ERR_ERR11_MASK 0x800u
+#define DMA_ERR_ERR11_SHIFT 11
+#define DMA_ERR_ERR12_MASK 0x1000u
+#define DMA_ERR_ERR12_SHIFT 12
+#define DMA_ERR_ERR13_MASK 0x2000u
+#define DMA_ERR_ERR13_SHIFT 13
+#define DMA_ERR_ERR14_MASK 0x4000u
+#define DMA_ERR_ERR14_SHIFT 14
+#define DMA_ERR_ERR15_MASK 0x8000u
+#define DMA_ERR_ERR15_SHIFT 15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+#define DMA_HRS_HRS4_MASK 0x10u
+#define DMA_HRS_HRS4_SHIFT 4
+#define DMA_HRS_HRS5_MASK 0x20u
+#define DMA_HRS_HRS5_SHIFT 5
+#define DMA_HRS_HRS6_MASK 0x40u
+#define DMA_HRS_HRS6_SHIFT 6
+#define DMA_HRS_HRS7_MASK 0x80u
+#define DMA_HRS_HRS7_SHIFT 7
+#define DMA_HRS_HRS8_MASK 0x100u
+#define DMA_HRS_HRS8_SHIFT 8
+#define DMA_HRS_HRS9_MASK 0x200u
+#define DMA_HRS_HRS9_SHIFT 9
+#define DMA_HRS_HRS10_MASK 0x400u
+#define DMA_HRS_HRS10_SHIFT 10
+#define DMA_HRS_HRS11_MASK 0x800u
+#define DMA_HRS_HRS11_SHIFT 11
+#define DMA_HRS_HRS12_MASK 0x1000u
+#define DMA_HRS_HRS12_SHIFT 12
+#define DMA_HRS_HRS13_MASK 0x2000u
+#define DMA_HRS_HRS13_SHIFT 13
+#define DMA_HRS_HRS14_MASK 0x4000u
+#define DMA_HRS_HRS14_SHIFT 14
+#define DMA_HRS_HRS15_MASK 0x8000u
+#define DMA_HRS_HRS15_SHIFT 15
+/* EARS Bit Fields */
+#define DMA_EARS_EDREQ_0_MASK 0x1u
+#define DMA_EARS_EDREQ_0_SHIFT 0
+#define DMA_EARS_EDREQ_1_MASK 0x2u
+#define DMA_EARS_EDREQ_1_SHIFT 1
+#define DMA_EARS_EDREQ_2_MASK 0x4u
+#define DMA_EARS_EDREQ_2_SHIFT 2
+#define DMA_EARS_EDREQ_3_MASK 0x8u
+#define DMA_EARS_EDREQ_3_SHIFT 3
+#define DMA_EARS_EDREQ_4_MASK 0x10u
+#define DMA_EARS_EDREQ_4_SHIFT 4
+#define DMA_EARS_EDREQ_5_MASK 0x20u
+#define DMA_EARS_EDREQ_5_SHIFT 5
+#define DMA_EARS_EDREQ_6_MASK 0x40u
+#define DMA_EARS_EDREQ_6_SHIFT 6
+#define DMA_EARS_EDREQ_7_MASK 0x80u
+#define DMA_EARS_EDREQ_7_SHIFT 7
+#define DMA_EARS_EDREQ_8_MASK 0x100u
+#define DMA_EARS_EDREQ_8_SHIFT 8
+#define DMA_EARS_EDREQ_9_MASK 0x200u
+#define DMA_EARS_EDREQ_9_SHIFT 9
+#define DMA_EARS_EDREQ_10_MASK 0x400u
+#define DMA_EARS_EDREQ_10_SHIFT 10
+#define DMA_EARS_EDREQ_11_MASK 0x800u
+#define DMA_EARS_EDREQ_11_SHIFT 11
+#define DMA_EARS_EDREQ_12_MASK 0x1000u
+#define DMA_EARS_EDREQ_12_SHIFT 12
+#define DMA_EARS_EDREQ_13_MASK 0x2000u
+#define DMA_EARS_EDREQ_13_SHIFT 13
+#define DMA_EARS_EDREQ_14_MASK 0x4000u
+#define DMA_EARS_EDREQ_14_SHIFT 14
+#define DMA_EARS_EDREQ_15_MASK 0x8000u
+#define DMA_EARS_EDREQ_15_SHIFT 15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK 0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT 0
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK 0x40u
+#define DMA_DCHPRI7_DPA_SHIFT 6
+#define DMA_DCHPRI7_ECP_MASK 0x80u
+#define DMA_DCHPRI7_ECP_SHIFT 7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK 0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT 0
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK 0x40u
+#define DMA_DCHPRI6_DPA_SHIFT 6
+#define DMA_DCHPRI6_ECP_MASK 0x80u
+#define DMA_DCHPRI6_ECP_SHIFT 7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK 0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT 0
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK 0x40u
+#define DMA_DCHPRI5_DPA_SHIFT 6
+#define DMA_DCHPRI5_ECP_MASK 0x80u
+#define DMA_DCHPRI5_ECP_SHIFT 7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK 0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT 0
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK 0x40u
+#define DMA_DCHPRI4_DPA_SHIFT 6
+#define DMA_DCHPRI4_ECP_MASK 0x80u
+#define DMA_DCHPRI4_ECP_SHIFT 7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK 0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT 0
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK 0x40u
+#define DMA_DCHPRI11_DPA_SHIFT 6
+#define DMA_DCHPRI11_ECP_MASK 0x80u
+#define DMA_DCHPRI11_ECP_SHIFT 7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK 0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT 0
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK 0x40u
+#define DMA_DCHPRI10_DPA_SHIFT 6
+#define DMA_DCHPRI10_ECP_MASK 0x80u
+#define DMA_DCHPRI10_ECP_SHIFT 7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK 0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT 0
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK 0x40u
+#define DMA_DCHPRI9_DPA_SHIFT 6
+#define DMA_DCHPRI9_ECP_MASK 0x80u
+#define DMA_DCHPRI9_ECP_SHIFT 7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK 0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT 0
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK 0x40u
+#define DMA_DCHPRI8_DPA_SHIFT 6
+#define DMA_DCHPRI8_ECP_MASK 0x80u
+#define DMA_DCHPRI8_ECP_SHIFT 7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK 0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT 0
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK 0x40u
+#define DMA_DCHPRI15_DPA_SHIFT 6
+#define DMA_DCHPRI15_ECP_MASK 0x80u
+#define DMA_DCHPRI15_ECP_SHIFT 7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK 0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT 0
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK 0x40u
+#define DMA_DCHPRI14_DPA_SHIFT 6
+#define DMA_DCHPRI14_ECP_MASK 0x80u
+#define DMA_DCHPRI14_ECP_SHIFT 7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK 0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT 0
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK 0x40u
+#define DMA_DCHPRI13_DPA_SHIFT 6
+#define DMA_DCHPRI13_ECP_MASK 0x80u
+#define DMA_DCHPRI13_ECP_SHIFT 7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK 0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT 0
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK 0x40u
+#define DMA_DCHPRI12_DPA_SHIFT 6
+#define DMA_DCHPRI12_ECP_MASK 0x80u
+#define DMA_DCHPRI12_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR DMA_CR_REG(DMA0)
+#define DMA_ES DMA_ES_REG(DMA0)
+#define DMA_ERQ DMA_ERQ_REG(DMA0)
+#define DMA_EEI DMA_EEI_REG(DMA0)
+#define DMA_CEEI DMA_CEEI_REG(DMA0)
+#define DMA_SEEI DMA_SEEI_REG(DMA0)
+#define DMA_CERQ DMA_CERQ_REG(DMA0)
+#define DMA_SERQ DMA_SERQ_REG(DMA0)
+#define DMA_CDNE DMA_CDNE_REG(DMA0)
+#define DMA_SSRT DMA_SSRT_REG(DMA0)
+#define DMA_CERR DMA_CERR_REG(DMA0)
+#define DMA_CINT DMA_CINT_REG(DMA0)
+#define DMA_INT DMA_INT_REG(DMA0)
+#define DMA_ERR DMA_ERR_REG(DMA0)
+#define DMA_HRS DMA_HRS_REG(DMA0)
+#define DMA_EARS DMA_EARS_REG(DMA0)
+#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base) ((base)->CTRL)
+#define EWM_SERV_REG(base) ((base)->SERV)
+#define EWM_CMPL_REG(base) ((base)->CMPL)
+#define EWM_CMPH_REG(base) ((base)->CMPH)
+#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+/* CLKPRESCALER Bit Fields */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
+#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL EWM_CTRL_REG(EWM)
+#define EWM_SERV EWM_SERV_REG(EWM)
+#define EWM_CMPL EWM_CMPL_REG(EWM)
+#define EWM_CMPH EWM_CMPH_REG(EWM)
+#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0xC */
+ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+ } CS[6];
+ uint8_t RESERVED_0[24];
+ __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
+#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK 0xFFFF0000u
+#define FB_CSAR_BA_SHIFT 16
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK 0x1u
+#define FB_CSMR_V_SHIFT 0
+#define FB_CSMR_WP_MASK 0x100u
+#define FB_CSMR_WP_SHIFT 8
+#define FB_CSMR_BAM_MASK 0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT 16
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK 0x8u
+#define FB_CSCR_BSTW_SHIFT 3
+#define FB_CSCR_BSTR_MASK 0x10u
+#define FB_CSCR_BSTR_SHIFT 4
+#define FB_CSCR_BEM_MASK 0x20u
+#define FB_CSCR_BEM_SHIFT 5
+#define FB_CSCR_PS_MASK 0xC0u
+#define FB_CSCR_PS_SHIFT 6
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK 0x100u
+#define FB_CSCR_AA_SHIFT 8
+#define FB_CSCR_BLS_MASK 0x200u
+#define FB_CSCR_BLS_SHIFT 9
+#define FB_CSCR_WS_MASK 0xFC00u
+#define FB_CSCR_WS_SHIFT 10
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK 0x30000u
+#define FB_CSCR_WRAH_SHIFT 16
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK 0xC0000u
+#define FB_CSCR_RDAH_SHIFT 18
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK 0x300000u
+#define FB_CSCR_ASET_SHIFT 20
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK 0x400000u
+#define FB_CSCR_EXTS_SHIFT 22
+#define FB_CSCR_SWSEN_MASK 0x800000u
+#define FB_CSCR_SWSEN_SHIFT 23
+#define FB_CSCR_SWS_MASK 0xFC000000u
+#define FB_CSCR_SWS_SHIFT 26
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK 0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT 12
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK 0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT 16
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK 0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT 20
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK 0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT 24
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT 28
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS { FB }
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0 FB_CSAR_REG(FB,0)
+#define FB_CSMR0 FB_CSMR_REG(FB,0)
+#define FB_CSCR0 FB_CSCR_REG(FB,0)
+#define FB_CSAR1 FB_CSAR_REG(FB,1)
+#define FB_CSMR1 FB_CSMR_REG(FB,1)
+#define FB_CSCR1 FB_CSCR_REG(FB,1)
+#define FB_CSAR2 FB_CSAR_REG(FB,2)
+#define FB_CSMR2 FB_CSMR_REG(FB,2)
+#define FB_CSCR2 FB_CSCR_REG(FB,2)
+#define FB_CSAR3 FB_CSAR_REG(FB,3)
+#define FB_CSMR3 FB_CSMR_REG(FB,3)
+#define FB_CSCR3 FB_CSCR_REG(FB,3)
+#define FB_CSAR4 FB_CSAR_REG(FB,4)
+#define FB_CSMR4 FB_CSMR_REG(FB,4)
+#define FB_CSCR4 FB_CSCR_REG(FB,4)
+#define FB_CSAR5 FB_CSAR_REG(FB,5)
+#define FB_CSMR5 FB_CSMR_REG(FB,5)
+#define FB_CSCR5 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index) FB_CSAR_REG(FB,index)
+#define FB_CSMR(index) FB_CSMR_REG(FB,index)
+#define FB_CSCR(index) FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
+ __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[244];
+ __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+ __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
+ __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
+ uint8_t RESERVED_1[128];
+ struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
+ __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
+ __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
+ } SET[4][8];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base) ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
+#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK 0x300u
+#define FMC_PFAPR_M4AP_SHIFT 8
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK 0xC00u
+#define FMC_PFAPR_M5AP_SHIFT 10
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK 0x3000u
+#define FMC_PFAPR_M6AP_SHIFT 12
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK 0xC000u
+#define FMC_PFAPR_M7AP_SHIFT 14
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+#define FMC_PFAPR_M4PFD_MASK 0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT 20
+#define FMC_PFAPR_M5PFD_MASK 0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT 21
+#define FMC_PFAPR_M6PFD_MASK 0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT 22
+#define FMC_PFAPR_M7PFD_MASK 0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT 23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK 0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT 0
+#define FMC_PFB1CR_B1IPE_MASK 0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT 1
+#define FMC_PFB1CR_B1DPE_MASK 0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT 2
+#define FMC_PFB1CR_B1ICE_MASK 0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT 3
+#define FMC_PFB1CR_B1DCE_MASK 0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT 4
+#define FMC_PFB1CR_B1MW_MASK 0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT 17
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT 28
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK 0x1u
+#define FMC_TAGVDW0S_valid_SHIFT 0
+#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT 5
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK 0x1u
+#define FMC_TAGVDW1S_valid_SHIFT 0
+#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT 5
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK 0x1u
+#define FMC_TAGVDW2S_valid_SHIFT 0
+#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT 5
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK 0x1u
+#define FMC_TAGVDW3S_valid_SHIFT 0
+#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT 5
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT 0
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT 0
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
+#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
+#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
+#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
+#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
+#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
+#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
+#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
+#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
+#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
+#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
+#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
+#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
+#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
+#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
+#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
+#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
+#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
+#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
+#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
+#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
+#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
+#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
+#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
+#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
+#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
+#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
+#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
+#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
+#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
+#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
+#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
+#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
+#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
+#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
+#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
+#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
+#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
+#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
+#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
+#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
+#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
+#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
+#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
+#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
+#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
+#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
+#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
+#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[4];
+ __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
+ __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
+ __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
+ __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
+ __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
+ __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
+ __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
+ __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
+ __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
+ __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
+ __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
+ __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
+ __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
+ __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
+ __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
+ __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
+ __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
+ uint8_t RESERVED_1[2];
+ __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
+} FTFA_Type, *FTFA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register accessors */
+#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFA_FSEC_REG(base) ((base)->FSEC)
+#define FTFA_FOPT_REG(base) ((base)->FOPT)
+#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
+#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
+#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
+#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
+#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
+#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
+#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
+#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
+#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
+#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
+#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
+#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
+#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
+#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
+#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
+#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
+#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
+#define FTFA_FACSS_REG(base) ((base)->FACSS)
+#define FTFA_FACSN_REG(base) ((base)->FACSN)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+/* XACCH3 Bit Fields */
+#define FTFA_XACCH3_XA_MASK 0xFFu
+#define FTFA_XACCH3_XA_SHIFT 0
+#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
+/* XACCH2 Bit Fields */
+#define FTFA_XACCH2_XA_MASK 0xFFu
+#define FTFA_XACCH2_XA_SHIFT 0
+#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
+/* XACCH1 Bit Fields */
+#define FTFA_XACCH1_XA_MASK 0xFFu
+#define FTFA_XACCH1_XA_SHIFT 0
+#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
+/* XACCH0 Bit Fields */
+#define FTFA_XACCH0_XA_MASK 0xFFu
+#define FTFA_XACCH0_XA_SHIFT 0
+#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
+/* XACCL3 Bit Fields */
+#define FTFA_XACCL3_XA_MASK 0xFFu
+#define FTFA_XACCL3_XA_SHIFT 0
+#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
+/* XACCL2 Bit Fields */
+#define FTFA_XACCL2_XA_MASK 0xFFu
+#define FTFA_XACCL2_XA_SHIFT 0
+#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
+/* XACCL1 Bit Fields */
+#define FTFA_XACCL1_XA_MASK 0xFFu
+#define FTFA_XACCL1_XA_SHIFT 0
+#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
+/* XACCL0 Bit Fields */
+#define FTFA_XACCL0_XA_MASK 0xFFu
+#define FTFA_XACCL0_XA_SHIFT 0
+#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
+/* SACCH3 Bit Fields */
+#define FTFA_SACCH3_SA_MASK 0xFFu
+#define FTFA_SACCH3_SA_SHIFT 0
+#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
+/* SACCH2 Bit Fields */
+#define FTFA_SACCH2_SA_MASK 0xFFu
+#define FTFA_SACCH2_SA_SHIFT 0
+#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
+/* SACCH1 Bit Fields */
+#define FTFA_SACCH1_SA_MASK 0xFFu
+#define FTFA_SACCH1_SA_SHIFT 0
+#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
+/* SACCH0 Bit Fields */
+#define FTFA_SACCH0_SA_MASK 0xFFu
+#define FTFA_SACCH0_SA_SHIFT 0
+#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
+/* SACCL3 Bit Fields */
+#define FTFA_SACCL3_SA_MASK 0xFFu
+#define FTFA_SACCL3_SA_SHIFT 0
+#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
+/* SACCL2 Bit Fields */
+#define FTFA_SACCL2_SA_MASK 0xFFu
+#define FTFA_SACCL2_SA_SHIFT 0
+#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
+/* SACCL1 Bit Fields */
+#define FTFA_SACCL1_SA_MASK 0xFFu
+#define FTFA_SACCL1_SA_SHIFT 0
+#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
+/* SACCL0 Bit Fields */
+#define FTFA_SACCL0_SA_MASK 0xFFu
+#define FTFA_SACCL0_SA_SHIFT 0
+#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
+/* FACSS Bit Fields */
+#define FTFA_FACSS_SGSIZE_MASK 0xFFu
+#define FTFA_FACSS_SGSIZE_SHIFT 0
+#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
+/* FACSN Bit Fields */
+#define FTFA_FACSN_NUMSG_MASK 0xFFu
+#define FTFA_FACSN_NUMSG_SHIFT 0
+#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+#define FTFA_BASE_PTR (FTFA)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
+#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register instance definitions */
+/* FTFA */
+#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
+#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
+#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
+#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
+#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
+#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
+#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
+#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
+#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
+#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
+#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
+#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
+#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
+#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
+#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
+#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
+#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
+#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
+#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
+#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
+#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
+#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
+#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
+#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
+#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
+#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
+#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
+#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
+#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
+#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
+#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
+#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
+#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
+#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
+#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
+#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
+#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
+#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base) ((base)->SC)
+#define FTM_CNT_REG(base) ((base)->CNT)
+#define FTM_MOD_REG(base) ((base)->MOD)
+#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base) ((base)->CNTIN)
+#define FTM_STATUS_REG(base) ((base)->STATUS)
+#define FTM_MODE_REG(base) ((base)->MODE)
+#define FTM_SYNC_REG(base) ((base)->SYNC)
+#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base) ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
+#define FTM_POL_REG(base) ((base)->POL)
+#define FTM_FMS_REG(base) ((base)->FMS)
+#define FTM_FILTER_REG(base) ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
+#define FTM_CONF_REG(base) ((base)->CONF)
+#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ICRST_MASK 0x2u
+#define FTM_CnSC_ICRST_SHIFT 1
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x40026000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC FTM_SC_REG(FTM0)
+#define FTM0_CNT FTM_CNT_REG(FTM0)
+#define FTM0_MOD FTM_MOD_REG(FTM0)
+#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS FTM_STATUS_REG(FTM0)
+#define FTM0_MODE FTM_MODE_REG(FTM0)
+#define FTM0_SYNC FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL FTM_POL_REG(FTM0)
+#define FTM0_FMS FTM_FMS_REG(FTM0)
+#define FTM0_FILTER FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC FTM_SC_REG(FTM1)
+#define FTM1_CNT FTM_CNT_REG(FTM1)
+#define FTM1_MOD FTM_MOD_REG(FTM1)
+#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS FTM_STATUS_REG(FTM1)
+#define FTM1_MODE FTM_MODE_REG(FTM1)
+#define FTM1_SYNC FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL FTM_POL_REG(FTM1)
+#define FTM1_FMS FTM_FMS_REG(FTM1)
+#define FTM1_FILTER FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC FTM_SC_REG(FTM2)
+#define FTM2_CNT FTM_CNT_REG(FTM2)
+#define FTM2_MOD FTM_MOD_REG(FTM2)
+#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS FTM_STATUS_REG(FTM2)
+#define FTM2_MODE FTM_MODE_REG(FTM2)
+#define FTM2_SYNC FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL FTM_POL_REG(FTM2)
+#define FTM2_FMS FTM_FMS_REG(FTM2)
+#define FTM2_FILTER FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC FTM_SC_REG(FTM3)
+#define FTM3_CNT FTM_CNT_REG(FTM3)
+#define FTM3_MOD FTM_MOD_REG(FTM3)
+#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS FTM_STATUS_REG(FTM3)
+#define FTM3_MODE FTM_MODE_REG(FTM3)
+#define FTM3_SYNC FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL FTM_POL_REG(FTM3)
+#define FTM3_FMS FTM_FMS_REG(FTM3)
+#define FTM3_FILTER FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[28];
+ __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[28];
+ __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR1_REG(base) ((base)->TCR1)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TFR_REG(base,index) ((base)->TFR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR1_REG(base) ((base)->RCR1)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RFR_REG(base,index) ((base)->RFR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+#define I2S_MDR_REG(base) ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0xFu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_ONDEM_MASK 0x4u
+#define I2S_TCR4_ONDEM_SHIFT 2
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0xF0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK 0x3000000u
+#define I2S_TCR4_FPACK_SHIFT 24
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK 0x10000000u
+#define I2S_TCR4_FCONT_SHIFT 28
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0xFu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_ONDEM_MASK 0x4u
+#define I2S_RCR4_ONDEM_SHIFT 2
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0xF0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK 0x3000000u
+#define I2S_RCR4_FPACK_SHIFT 24
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK 0x10000000u
+#define I2S_RCR4_FCONT_SHIFT 28
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+#define I2S0_MDR I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTimer_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
+ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register accessors */
+#define LPUART_BAUD_REG(base) ((base)->BAUD)
+#define LPUART_STAT_REG(base) ((base)->STAT)
+#define LPUART_CTRL_REG(base) ((base)->CTRL)
+#define LPUART_DATA_REG(base) ((base)->DATA)
+#define LPUART_MATCH_REG(base) ((base)->MATCH)
+#define LPUART_MODIR_REG(base) ((base)->MODIR)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK 0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT 0
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK 0x2000u
+#define LPUART_BAUD_SBNS_SHIFT 13
+#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT 14
+#define LPUART_BAUD_LBKDIE_MASK 0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT 15
+#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT 16
+#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT 17
+#define LPUART_BAUD_MATCFG_MASK 0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT 18
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK 0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT 21
+#define LPUART_BAUD_TDMAE_MASK 0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT 23
+#define LPUART_BAUD_OSR_MASK 0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT 24
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK 0x20000000u
+#define LPUART_BAUD_M10_SHIFT 29
+#define LPUART_BAUD_MAEN2_MASK 0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT 30
+#define LPUART_BAUD_MAEN1_MASK 0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT 31
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK 0x4000u
+#define LPUART_STAT_MA2F_SHIFT 14
+#define LPUART_STAT_MA1F_MASK 0x8000u
+#define LPUART_STAT_MA1F_SHIFT 15
+#define LPUART_STAT_PF_MASK 0x10000u
+#define LPUART_STAT_PF_SHIFT 16
+#define LPUART_STAT_FE_MASK 0x20000u
+#define LPUART_STAT_FE_SHIFT 17
+#define LPUART_STAT_NF_MASK 0x40000u
+#define LPUART_STAT_NF_SHIFT 18
+#define LPUART_STAT_OR_MASK 0x80000u
+#define LPUART_STAT_OR_SHIFT 19
+#define LPUART_STAT_IDLE_MASK 0x100000u
+#define LPUART_STAT_IDLE_SHIFT 20
+#define LPUART_STAT_RDRF_MASK 0x200000u
+#define LPUART_STAT_RDRF_SHIFT 21
+#define LPUART_STAT_TC_MASK 0x400000u
+#define LPUART_STAT_TC_SHIFT 22
+#define LPUART_STAT_TDRE_MASK 0x800000u
+#define LPUART_STAT_TDRE_SHIFT 23
+#define LPUART_STAT_RAF_MASK 0x1000000u
+#define LPUART_STAT_RAF_SHIFT 24
+#define LPUART_STAT_LBKDE_MASK 0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT 25
+#define LPUART_STAT_BRK13_MASK 0x4000000u
+#define LPUART_STAT_BRK13_SHIFT 26
+#define LPUART_STAT_RWUID_MASK 0x8000000u
+#define LPUART_STAT_RWUID_SHIFT 27
+#define LPUART_STAT_RXINV_MASK 0x10000000u
+#define LPUART_STAT_RXINV_SHIFT 28
+#define LPUART_STAT_MSBF_MASK 0x20000000u
+#define LPUART_STAT_MSBF_SHIFT 29
+#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
+#define LPUART_STAT_RXEDGIF_SHIFT 30
+#define LPUART_STAT_LBKDIF_MASK 0x80000000u
+#define LPUART_STAT_LBKDIF_SHIFT 31
+/* CTRL Bit Fields */
+#define LPUART_CTRL_PT_MASK 0x1u
+#define LPUART_CTRL_PT_SHIFT 0
+#define LPUART_CTRL_PE_MASK 0x2u
+#define LPUART_CTRL_PE_SHIFT 1
+#define LPUART_CTRL_ILT_MASK 0x4u
+#define LPUART_CTRL_ILT_SHIFT 2
+#define LPUART_CTRL_WAKE_MASK 0x8u
+#define LPUART_CTRL_WAKE_SHIFT 3
+#define LPUART_CTRL_M_MASK 0x10u
+#define LPUART_CTRL_M_SHIFT 4
+#define LPUART_CTRL_RSRC_MASK 0x20u
+#define LPUART_CTRL_RSRC_SHIFT 5
+#define LPUART_CTRL_DOZEEN_MASK 0x40u
+#define LPUART_CTRL_DOZEEN_SHIFT 6
+#define LPUART_CTRL_LOOPS_MASK 0x80u
+#define LPUART_CTRL_LOOPS_SHIFT 7
+#define LPUART_CTRL_IDLECFG_MASK 0x700u
+#define LPUART_CTRL_IDLECFG_SHIFT 8
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK 0x4000u
+#define LPUART_CTRL_MA2IE_SHIFT 14
+#define LPUART_CTRL_MA1IE_MASK 0x8000u
+#define LPUART_CTRL_MA1IE_SHIFT 15
+#define LPUART_CTRL_SBK_MASK 0x10000u
+#define LPUART_CTRL_SBK_SHIFT 16
+#define LPUART_CTRL_RWU_MASK 0x20000u
+#define LPUART_CTRL_RWU_SHIFT 17
+#define LPUART_CTRL_RE_MASK 0x40000u
+#define LPUART_CTRL_RE_SHIFT 18
+#define LPUART_CTRL_TE_MASK 0x80000u
+#define LPUART_CTRL_TE_SHIFT 19
+#define LPUART_CTRL_ILIE_MASK 0x100000u
+#define LPUART_CTRL_ILIE_SHIFT 20
+#define LPUART_CTRL_RIE_MASK 0x200000u
+#define LPUART_CTRL_RIE_SHIFT 21
+#define LPUART_CTRL_TCIE_MASK 0x400000u
+#define LPUART_CTRL_TCIE_SHIFT 22
+#define LPUART_CTRL_TIE_MASK 0x800000u
+#define LPUART_CTRL_TIE_SHIFT 23
+#define LPUART_CTRL_PEIE_MASK 0x1000000u
+#define LPUART_CTRL_PEIE_SHIFT 24
+#define LPUART_CTRL_FEIE_MASK 0x2000000u
+#define LPUART_CTRL_FEIE_SHIFT 25
+#define LPUART_CTRL_NEIE_MASK 0x4000000u
+#define LPUART_CTRL_NEIE_SHIFT 26
+#define LPUART_CTRL_ORIE_MASK 0x8000000u
+#define LPUART_CTRL_ORIE_SHIFT 27
+#define LPUART_CTRL_TXINV_MASK 0x10000000u
+#define LPUART_CTRL_TXINV_SHIFT 28
+#define LPUART_CTRL_TXDIR_MASK 0x20000000u
+#define LPUART_CTRL_TXDIR_SHIFT 29
+#define LPUART_CTRL_R9T8_MASK 0x40000000u
+#define LPUART_CTRL_R9T8_SHIFT 30
+#define LPUART_CTRL_R8T9_MASK 0x80000000u
+#define LPUART_CTRL_R8T9_SHIFT 31
+/* DATA Bit Fields */
+#define LPUART_DATA_R0T0_MASK 0x1u
+#define LPUART_DATA_R0T0_SHIFT 0
+#define LPUART_DATA_R1T1_MASK 0x2u
+#define LPUART_DATA_R1T1_SHIFT 1
+#define LPUART_DATA_R2T2_MASK 0x4u
+#define LPUART_DATA_R2T2_SHIFT 2
+#define LPUART_DATA_R3T3_MASK 0x8u
+#define LPUART_DATA_R3T3_SHIFT 3
+#define LPUART_DATA_R4T4_MASK 0x10u
+#define LPUART_DATA_R4T4_SHIFT 4
+#define LPUART_DATA_R5T5_MASK 0x20u
+#define LPUART_DATA_R5T5_SHIFT 5
+#define LPUART_DATA_R6T6_MASK 0x40u
+#define LPUART_DATA_R6T6_SHIFT 6
+#define LPUART_DATA_R7T7_MASK 0x80u
+#define LPUART_DATA_R7T7_SHIFT 7
+#define LPUART_DATA_R8T8_MASK 0x100u
+#define LPUART_DATA_R8T8_SHIFT 8
+#define LPUART_DATA_R9T9_MASK 0x200u
+#define LPUART_DATA_R9T9_SHIFT 9
+#define LPUART_DATA_IDLINE_MASK 0x800u
+#define LPUART_DATA_IDLINE_SHIFT 11
+#define LPUART_DATA_RXEMPT_MASK 0x1000u
+#define LPUART_DATA_RXEMPT_SHIFT 12
+#define LPUART_DATA_FRETSC_MASK 0x2000u
+#define LPUART_DATA_FRETSC_SHIFT 13
+#define LPUART_DATA_PARITYE_MASK 0x4000u
+#define LPUART_DATA_PARITYE_SHIFT 14
+#define LPUART_DATA_NOISY_MASK 0x8000u
+#define LPUART_DATA_NOISY_SHIFT 15
+/* MATCH Bit Fields */
+#define LPUART_MATCH_MA1_MASK 0x3FFu
+#define LPUART_MATCH_MA1_SHIFT 0
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK 0x3FF0000u
+#define LPUART_MATCH_MA2_SHIFT 16
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
+/* MODIR Bit Fields */
+#define LPUART_MODIR_TXCTSE_MASK 0x1u
+#define LPUART_MODIR_TXCTSE_SHIFT 0
+#define LPUART_MODIR_TXRTSE_MASK 0x2u
+#define LPUART_MODIR_TXRTSE_SHIFT 1
+#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
+#define LPUART_MODIR_TXRTSPOL_SHIFT 2
+#define LPUART_MODIR_RXRTSE_MASK 0x8u
+#define LPUART_MODIR_RXRTSE_SHIFT 3
+#define LPUART_MODIR_TXCTSC_MASK 0x10u
+#define LPUART_MODIR_TXCTSC_SHIFT 4
+#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
+#define LPUART_MODIR_TXCTSSRC_SHIFT 5
+#define LPUART_MODIR_TNP_MASK 0x30000u
+#define LPUART_MODIR_TNP_SHIFT 16
+#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK 0x40000u
+#define LPUART_MODIR_IREN_SHIFT 18
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x4002A000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0_BASE_PTR (LPUART0)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
+#define LPUART_ERR_IRQS { LPUART0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register instance definitions */
+/* LPUART0 */
+#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
+#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
+#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
+#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
+#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
+#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_C3_REG(base) ((base)->C3)
+#define MCG_C4_REG(base) ((base)->C4)
+#define MCG_C5_REG(base) ((base)->C5)
+#define MCG_C6_REG(base) ((base)->C6)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_ATCVH_REG(base) ((base)->ATCVH)
+#define MCG_ATCVL_REG(base) ((base)->ATCVL)
+#define MCG_C7_REG(base) ((base)->C7)
+#define MCG_C8_REG(base) ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS_MASK 0x4u
+#define MCG_C2_EREFS_SHIFT 2
+#define MCG_C2_HGO_MASK 0x8u
+#define MCG_C2_HGO_SHIFT 3
+#define MCG_C2_RANGE_MASK 0x30u
+#define MCG_C2_RANGE_SHIFT 4
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x3u
+#define MCG_C7_OSCSEL_SHIFT 0
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_C3 MCG_C3_REG(MCG)
+#define MCG_C4 MCG_C4_REG(MCG)
+#define MCG_C5 MCG_C5_REG(MCG)
+#define MCG_C6 MCG_C6_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_ATCVH MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL MCG_ATCVL_REG(MCG)
+#define MCG_C7 MCG_C7_REG(MCG)
+#define MCG_C8 MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
+ __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
+ uint8_t RESERVED_1[44];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_PLACR_REG(base) ((base)->PLACR)
+#define MCM_ISCR_REG(base) ((base)->ISCR)
+#define MCM_CPO_REG(base) ((base)->CPO)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+/* ISCR Bit Fields */
+#define MCM_ISCR_FIOC_MASK 0x100u
+#define MCM_ISCR_FIOC_SHIFT 8
+#define MCM_ISCR_FDZC_MASK 0x200u
+#define MCM_ISCR_FDZC_SHIFT 9
+#define MCM_ISCR_FOFC_MASK 0x400u
+#define MCM_ISCR_FOFC_SHIFT 10
+#define MCM_ISCR_FUFC_MASK 0x800u
+#define MCM_ISCR_FUFC_SHIFT 11
+#define MCM_ISCR_FIXC_MASK 0x1000u
+#define MCM_ISCR_FIXC_SHIFT 12
+#define MCM_ISCR_FIDC_MASK 0x8000u
+#define MCM_ISCR_FIDC_SHIFT 15
+#define MCM_ISCR_FIOCE_MASK 0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT 24
+#define MCM_ISCR_FDZCE_MASK 0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT 25
+#define MCM_ISCR_FOFCE_MASK 0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT 26
+#define MCM_ISCR_FUFCE_MASK 0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT 27
+#define MCM_ISCR_FIXCE_MASK 0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT 28
+#define MCM_ISCR_FIDCE_MASK 0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT 31
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_PLACR MCM_PLACR_REG(MCM)
+#define MCM_ISCR MCM_ISCR_REG(MCM)
+#define MCM_CPO MCM_CPO_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFA_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+#define OSC_DIV_REG(base) ((base)->DIV)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+/* DIV Bit Fields */
+#define OSC_DIV_ERPS_MASK 0xC0u
+#define OSC_DIV_ERPS_SHIFT 6
+#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR OSC_CR_REG(OSC)
+#define OSC_DIV OSC_DIV_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[2];
+ uint8_t RESERVED_0[240];
+ struct { /* offset: 0x150, array step: 0x8 */
+ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base) ((base)->SC)
+#define PDB_MOD_REG(base) ((base)->MOD)
+#define PDB_CNT_REG(base) ((base)->CNT)
+#define PDB_IDLY_REG(base) ((base)->IDLY)
+#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
+#define PDB_S_REG(base,index) ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base) ((base)->POEN)
+#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK 0x1u
+#define PDB_INTC_TOE_SHIFT 0
+#define PDB_INTC_EXT_MASK 0x2u
+#define PDB_INTC_EXT_SHIFT 1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK 0xFFFFu
+#define PDB_INT_INT_SHIFT 0
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC PDB_SC_REG(PDB0)
+#define PDB0_MOD PDB_MOD_REG(PDB0)
+#define PDB0_CNT PDB_CNT_REG(PDB0)
+#define PDB0_IDLY PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
+#define PDB0_POEN PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
+#define PDB0_S(index) PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+#define PORT_DFER_REG(base) ((base)->DFER)
+#define PORT_DFCR_REG(base) ((base)->DFCR)
+#define PORT_DFWR_REG(base) ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+#define PORTD_DFER PORT_DFER_REG(PORTD)
+#define PORTD_DFCR PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
+ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_MR_REG(base) ((base)->MR)
+#define RCM_SSRS0_REG(base) ((base)->SSRS0)
+#define RCM_SSRS1_REG(base) ((base)->SSRS1)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+/* SSRS0 Bit Fields */
+#define RCM_SSRS0_SWAKEUP_MASK 0x1u
+#define RCM_SSRS0_SWAKEUP_SHIFT 0
+#define RCM_SSRS0_SLVD_MASK 0x2u
+#define RCM_SSRS0_SLVD_SHIFT 1
+#define RCM_SSRS0_SLOC_MASK 0x4u
+#define RCM_SSRS0_SLOC_SHIFT 2
+#define RCM_SSRS0_SLOL_MASK 0x8u
+#define RCM_SSRS0_SLOL_SHIFT 3
+#define RCM_SSRS0_SWDOG_MASK 0x20u
+#define RCM_SSRS0_SWDOG_SHIFT 5
+#define RCM_SSRS0_SPIN_MASK 0x40u
+#define RCM_SSRS0_SPIN_SHIFT 6
+#define RCM_SSRS0_SPOR_MASK 0x80u
+#define RCM_SSRS0_SPOR_SHIFT 7
+/* SSRS1 Bit Fields */
+#define RCM_SSRS1_SJTAG_MASK 0x1u
+#define RCM_SSRS1_SJTAG_SHIFT 0
+#define RCM_SSRS1_SLOCKUP_MASK 0x2u
+#define RCM_SSRS1_SLOCKUP_SHIFT 1
+#define RCM_SSRS1_SSW_MASK 0x4u
+#define RCM_SSRS1_SSW_SHIFT 2
+#define RCM_SSRS1_SMDM_AP_MASK 0x8u
+#define RCM_SSRS1_SMDM_AP_SHIFT 3
+#define RCM_SSRS1_SEZPT_MASK 0x10u
+#define RCM_SSRS1_SEZPT_SHIFT 4
+#define RCM_SSRS1_SSACKERR_MASK 0x20u
+#define RCM_SSRS1_SSACKERR_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
+#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
+ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
+ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base) ((base)->CR)
+#define RNG_SR_REG(base) ((base)->SR)
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_OR_REG(base) ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK 0x1u
+#define RNG_CR_GO_SHIFT 0
+#define RNG_CR_HA_MASK 0x2u
+#define RNG_CR_HA_SHIFT 1
+#define RNG_CR_INTM_MASK 0x4u
+#define RNG_CR_INTM_SHIFT 2
+#define RNG_CR_CLRI_MASK 0x8u
+#define RNG_CR_CLRI_SHIFT 3
+#define RNG_CR_SLP_MASK 0x10u
+#define RNG_CR_SLP_SHIFT 4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK 0x1u
+#define RNG_SR_SECV_SHIFT 0
+#define RNG_SR_LRS_MASK 0x2u
+#define RNG_SR_LRS_SHIFT 1
+#define RNG_SR_ORU_MASK 0x4u
+#define RNG_SR_ORU_SHIFT 2
+#define RNG_SR_ERRI_MASK 0x8u
+#define RNG_SR_ERRI_SHIFT 3
+#define RNG_SR_SLP_MASK 0x10u
+#define RNG_SR_SLP_SHIFT 4
+#define RNG_SR_OREG_LVL_MASK 0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT 8
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT 16
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT 0
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT 0
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR RNG_CR_REG(RNG)
+#define RNG_SR RNG_SR_REG(RNG)
+#define RNG_ER RNG_ER_REG(RNG)
+#define RNG_OR RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+#define RTC_WAR_REG(base) ((base)->WAR)
+#define RTC_RAR_REG(base) ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+#define RTC_WAR RTC_WAR_REG(RTC)
+#define RTC_RAR RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
+ uint8_t RESERVED_3[4];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SOPT8_REG(base) ((base)->SOPT8)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDH_REG(base) ((base)->UIDH)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
+#define SIM_SOPT1_OSC32KOUT_SHIFT 16
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK 0x300u
+#define SIM_SOPT2_FBSL_SHIFT 8
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
+#define SIM_SOPT2_LPUARTSRC_SHIFT 26
+#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT 12
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
+#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
+#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SOPT8 Bit Fields */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
+#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
+#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
+#define SIM_SOPT8_FTM3SYNCBIT_MASK 0x8u
+#define SIM_SOPT8_FTM3SYNCBIT_SHIFT 3
+#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
+#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
+#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
+#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
+#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
+#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
+#define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
+#define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
+#define SIM_SOPT8_FTM3OCH0SRC_MASK 0x1000000u
+#define SIM_SOPT8_FTM3OCH0SRC_SHIFT 24
+#define SIM_SOPT8_FTM3OCH1SRC_MASK 0x2000000u
+#define SIM_SOPT8_FTM3OCH1SRC_SHIFT 25
+#define SIM_SOPT8_FTM3OCH2SRC_MASK 0x4000000u
+#define SIM_SOPT8_FTM3OCH2SRC_SHIFT 26
+#define SIM_SOPT8_FTM3OCH3SRC_MASK 0x8000000u
+#define SIM_SOPT8_FTM3OCH3SRC_SHIFT 27
+#define SIM_SOPT8_FTM3OCH4SRC_MASK 0x10000000u
+#define SIM_SOPT8_FTM3OCH4SRC_SHIFT 28
+#define SIM_SOPT8_FTM3OCH5SRC_MASK 0x20000000u
+#define SIM_SOPT8_FTM3OCH5SRC_SHIFT 29
+#define SIM_SOPT8_FTM3OCH6SRC_MASK 0x40000000u
+#define SIM_SOPT8_FTM3OCH6SRC_SHIFT 30
+#define SIM_SOPT8_FTM3OCH7SRC_MASK 0x80000000u
+#define SIM_SOPT8_FTM3OCH7SRC_SHIFT 31
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK 0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT 28
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FTM3_MASK 0x40u
+#define SIM_SCGC6_FTM3_SHIFT 6
+#define SIM_SCGC6_ADC1_MASK 0x80u
+#define SIM_SCGC6_ADC1_SHIFT 7
+#define SIM_SCGC6_DAC1_MASK 0x100u
+#define SIM_SCGC6_DAC1_SHIFT 8
+#define SIM_SCGC6_RNGA_MASK 0x200u
+#define SIM_SCGC6_RNGA_SHIFT 9
+#define SIM_SCGC6_LPUART0_MASK 0x400u
+#define SIM_SCGC6_LPUART0_SHIFT 10
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_FTM2_MASK 0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK 0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT 0
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SOPT8 SIM_SOPT8_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDH SIM_UIDH_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+#define SMC_PMPROT_AHSRUN_MASK 0x80u
+#define SMC_PMPROT_AHSRUN_SHIFT 7
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_LLSM_MASK 0x7u
+#define SMC_STOPCTRL_LLSM_SHIFT 0
+#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base) ((base)->MCR)
+#define SPI_TCR_REG(base) ((base)->TCR)
+#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base) ((base)->SR)
+#define SPI_RSER_REG(base) ((base)->RSER)
+#define SPI_PUSHR_REG(base) ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base) ((base)->POPR)
+#define SPI_TXFR0_REG(base) ((base)->TXFR0)
+#define SPI_TXFR1_REG(base) ((base)->TXFR1)
+#define SPI_TXFR2_REG(base) ((base)->TXFR2)
+#define SPI_TXFR3_REG(base) ((base)->TXFR3)
+#define SPI_RXFR0_REG(base) ((base)->RXFR0)
+#define SPI_RXFR1_REG(base) ((base)->RXFR1)
+#define SPI_RXFR2_REG(base) ((base)->RXFR2)
+#define SPI_RXFR3_REG(base) ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR SPI_MCR_REG(SPI0)
+#define SPI0_TCR SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR SPI_SR_REG(SPI0)
+#define SPI0_RSER SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR SPI_MCR_REG(SPI1)
+#define SPI1_TCR SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR SPI_SR_REG(SPI1)
+#define SPI1_RSER SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
+#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[26];
+ __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+ union { /* offset: 0x3C */
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE0;
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE1;
+ };
+ __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_ED_REG(base) ((base)->ED)
+#define UART_MODEM_REG(base) ((base)->MODEM)
+#define UART_IR_REG(base) ((base)->IR)
+#define UART_PFIFO_REG(base) ((base)->PFIFO)
+#define UART_CFIFO_REG(base) ((base)->CFIFO)
+#define UART_SFIFO_REG(base) ((base)->SFIFO)
+#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816_REG(base) ((base)->WP7816)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
+#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
+#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
+#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
+#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
+#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
+#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
+#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXOFE_MASK 0x4u
+#define UART_CFIFO_RXOFE_SHIFT 2
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXOF_MASK 0x4u
+#define UART_SFIFO_RXOF_SHIFT 2
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_ADTE_MASK 0x8u
+#define UART_IE7816_ADTE_SHIFT 3
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_ADT_MASK 0x8u
+#define UART_IS7816_ADT_SHIFT 3
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816 Bit Fields */
+#define UART_WP7816_WTX_MASK 0xFFu
+#define UART_WP7816_WTX_SHIFT 0
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* AP7816A_T0 Bit Fields */
+#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
+#define UART_AP7816A_T0_ADTI_H_SHIFT 0
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
+/* AP7816B_T0 Bit Fields */
+#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
+#define UART_AP7816B_T0_ADTI_L_SHIFT 0
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
+/* WP7816A_T0 Bit Fields */
+#define UART_WP7816A_T0_WI_H_MASK 0xFFu
+#define UART_WP7816A_T0_WI_H_SHIFT 0
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
+/* WP7816B_T0 Bit Fields */
+#define UART_WP7816B_T0_WI_L_MASK 0xFFu
+#define UART_WP7816B_T0_WI_L_SHIFT 0
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
+/* WP7816A_T1 Bit Fields */
+#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
+#define UART_WP7816A_T1_BWI_H_SHIFT 0
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
+/* WP7816B_T1 Bit Fields */
+#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
+#define UART_WP7816B_T1_BWI_L_SHIFT 0
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
+/* WGP7816_T1 Bit Fields */
+#define UART_WGP7816_T1_BGI_MASK 0xFu
+#define UART_WGP7816_T1_BGI_SHIFT 0
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK 0xF0u
+#define UART_WGP7816_T1_CWI1_SHIFT 4
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
+/* WP7816C_T1 Bit Fields */
+#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
+#define UART_WP7816C_T1_CWI2_SHIFT 0
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
+#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH UART_BDH_REG(UART0)
+#define UART0_BDL UART_BDL_REG(UART0)
+#define UART0_C1 UART_C1_REG(UART0)
+#define UART0_C2 UART_C2_REG(UART0)
+#define UART0_S1 UART_S1_REG(UART0)
+#define UART0_S2 UART_S2_REG(UART0)
+#define UART0_C3 UART_C3_REG(UART0)
+#define UART0_D UART_D_REG(UART0)
+#define UART0_MA1 UART_MA1_REG(UART0)
+#define UART0_MA2 UART_MA2_REG(UART0)
+#define UART0_C4 UART_C4_REG(UART0)
+#define UART0_C5 UART_C5_REG(UART0)
+#define UART0_ED UART_ED_REG(UART0)
+#define UART0_MODEM UART_MODEM_REG(UART0)
+#define UART0_IR UART_IR_REG(UART0)
+#define UART0_PFIFO UART_PFIFO_REG(UART0)
+#define UART0_CFIFO UART_CFIFO_REG(UART0)
+#define UART0_SFIFO UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
+#define UART0_C7816 UART_C7816_REG(UART0)
+#define UART0_IE7816 UART_IE7816_REG(UART0)
+#define UART0_IS7816 UART_IS7816_REG(UART0)
+#define UART0_WP7816 UART_WP7816_REG(UART0)
+#define UART0_WN7816 UART_WN7816_REG(UART0)
+#define UART0_WF7816 UART_WF7816_REG(UART0)
+#define UART0_ET7816 UART_ET7816_REG(UART0)
+#define UART0_TL7816 UART_TL7816_REG(UART0)
+#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
+#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
+#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
+#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
+#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
+#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
+#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
+#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
+/* UART1 */
+#define UART1_BDH UART_BDH_REG(UART1)
+#define UART1_BDL UART_BDL_REG(UART1)
+#define UART1_C1 UART_C1_REG(UART1)
+#define UART1_C2 UART_C2_REG(UART1)
+#define UART1_S1 UART_S1_REG(UART1)
+#define UART1_S2 UART_S2_REG(UART1)
+#define UART1_C3 UART_C3_REG(UART1)
+#define UART1_D UART_D_REG(UART1)
+#define UART1_MA1 UART_MA1_REG(UART1)
+#define UART1_MA2 UART_MA2_REG(UART1)
+#define UART1_C4 UART_C4_REG(UART1)
+#define UART1_C5 UART_C5_REG(UART1)
+#define UART1_ED UART_ED_REG(UART1)
+#define UART1_MODEM UART_MODEM_REG(UART1)
+#define UART1_IR UART_IR_REG(UART1)
+#define UART1_PFIFO UART_PFIFO_REG(UART1)
+#define UART1_CFIFO UART_CFIFO_REG(UART1)
+#define UART1_SFIFO UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_ED UART_ED_REG(UART2)
+#define UART2_MODEM UART_MODEM_REG(UART2)
+#define UART2_IR UART_IR_REG(UART2)
+#define UART2_PFIFO UART_PFIFO_REG(UART2)
+#define UART2_CFIFO UART_CFIFO_REG(UART2)
+#define UART2_SFIFO UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_26[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_27[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_28[23];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base) ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base) ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
+#define WDOG_WINH_REG(base) ((base)->WINH)
+#define WDOG_WINL_REG(base) ((base)->WINL)
+#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base) ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH WDOG_WINH_REG(WDOG)
+#define WDOG_WINL WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
+#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK22F51212_H_) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0200u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif /* #if !defined(MK22F51212_H_) */
+
+/* MK22F51212.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
new file mode 100644
index 000000000..710144bf3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k)
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
+ ; 0x20000 - 0x198 = 0x1FE68
+ RW_IRAM1 0x1FFF0198 0x1FE68 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
new file mode 100644
index 000000000..5c53006d0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
@@ -0,0 +1,679 @@
+;/*****************************************************************************
+; * @file: startup_MK22F12.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK22F12
+; * @version: 1.5
+; * @date: 2013-5-16
+; *
+; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20010000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD Reserved39_IRQHandler ; Reserved Interrupt 39
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD DefaultISR ; 98
+ DCD DefaultISR ; 99
+ DCD DefaultISR ; 100
+ DCD DefaultISR ; 101
+ DCD DefaultISR ; 102
+ DCD DefaultISR ; 103
+ DCD DefaultISR ; 104
+ DCD DefaultISR ; 105
+ DCD DefaultISR ; 106
+ DCD DefaultISR ; 107
+ DCD DefaultISR ; 108
+ DCD DefaultISR ; 109
+ DCD DefaultISR ; 110
+ DCD DefaultISR ; 111
+ DCD DefaultISR ; 112
+ DCD DefaultISR ; 113
+ DCD DefaultISR ; 114
+ DCD DefaultISR ; 115
+ DCD DefaultISR ; 116
+ DCD DefaultISR ; 117
+ DCD DefaultISR ; 118
+ DCD DefaultISR ; 119
+ DCD DefaultISR ; 120
+ DCD DefaultISR ; 121
+ DCD DefaultISR ; 122
+ DCD DefaultISR ; 123
+ DCD DefaultISR ; 124
+ DCD DefaultISR ; 125
+ DCD DefaultISR ; 126
+ DCD DefaultISR ; 127
+ DCD DefaultISR ; 128
+ DCD DefaultISR ; 129
+ DCD DefaultISR ; 130
+ DCD DefaultISR ; 131
+ DCD DefaultISR ; 132
+ DCD DefaultISR ; 133
+ DCD DefaultISR ; 134
+ DCD DefaultISR ; 135
+ DCD DefaultISR ; 136
+ DCD DefaultISR ; 137
+ DCD DefaultISR ; 138
+ DCD DefaultISR ; 139
+ DCD DefaultISR ; 140
+ DCD DefaultISR ; 141
+ DCD DefaultISR ; 142
+ DCD DefaultISR ; 143
+ DCD DefaultISR ; 144
+ DCD DefaultISR ; 145
+ DCD DefaultISR ; 146
+ DCD DefaultISR ; 147
+ DCD DefaultISR ; 148
+ DCD DefaultISR ; 149
+ DCD DefaultISR ; 150
+ DCD DefaultISR ; 151
+ DCD DefaultISR ; 152
+ DCD DefaultISR ; 153
+ DCD DefaultISR ; 154
+ DCD DefaultISR ; 155
+ DCD DefaultISR ; 156
+ DCD DefaultISR ; 157
+ DCD DefaultISR ; 158
+ DCD DefaultISR ; 159
+ DCD DefaultISR ; 160
+ DCD DefaultISR ; 161
+ DCD DefaultISR ; 162
+ DCD DefaultISR ; 163
+ DCD DefaultISR ; 164
+ DCD DefaultISR ; 165
+ DCD DefaultISR ; 166
+ DCD DefaultISR ; 167
+ DCD DefaultISR ; 168
+ DCD DefaultISR ; 169
+ DCD DefaultISR ; 170
+ DCD DefaultISR ; 171
+ DCD DefaultISR ; 172
+ DCD DefaultISR ; 173
+ DCD DefaultISR ; 174
+ DCD DefaultISR ; 175
+ DCD DefaultISR ; 176
+ DCD DefaultISR ; 177
+ DCD DefaultISR ; 178
+ DCD DefaultISR ; 179
+ DCD DefaultISR ; 180
+ DCD DefaultISR ; 181
+ DCD DefaultISR ; 182
+ DCD DefaultISR ; 183
+ DCD DefaultISR ; 184
+ DCD DefaultISR ; 185
+ DCD DefaultISR ; 186
+ DCD DefaultISR ; 187
+ DCD DefaultISR ; 188
+ DCD DefaultISR ; 189
+ DCD DefaultISR ; 190
+ DCD DefaultISR ; 191
+ DCD DefaultISR ; 192
+ DCD DefaultISR ; 193
+ DCD DefaultISR ; 194
+ DCD DefaultISR ; 195
+ DCD DefaultISR ; 196
+ DCD DefaultISR ; 197
+ DCD DefaultISR ; 198
+ DCD DefaultISR ; 199
+ DCD DefaultISR ; 200
+ DCD DefaultISR ; 201
+ DCD DefaultISR ; 202
+ DCD DefaultISR ; 203
+ DCD DefaultISR ; 204
+ DCD DefaultISR ; 205
+ DCD DefaultISR ; 206
+ DCD DefaultISR ; 207
+ DCD DefaultISR ; 208
+ DCD DefaultISR ; 209
+ DCD DefaultISR ; 210
+ DCD DefaultISR ; 211
+ DCD DefaultISR ; 212
+ DCD DefaultISR ; 213
+ DCD DefaultISR ; 214
+ DCD DefaultISR ; 215
+ DCD DefaultISR ; 216
+ DCD DefaultISR ; 217
+ DCD DefaultISR ; 218
+ DCD DefaultISR ; 219
+ DCD DefaultISR ; 220
+ DCD DefaultISR ; 221
+ DCD DefaultISR ; 222
+ DCD DefaultISR ; 223
+ DCD DefaultISR ; 224
+ DCD DefaultISR ; 225
+ DCD DefaultISR ; 226
+ DCD DefaultISR ; 227
+ DCD DefaultISR ; 228
+ DCD DefaultISR ; 229
+ DCD DefaultISR ; 230
+ DCD DefaultISR ; 231
+ DCD DefaultISR ; 232
+ DCD DefaultISR ; 233
+ DCD DefaultISR ; 234
+ DCD DefaultISR ; 235
+ DCD DefaultISR ; 236
+ DCD DefaultISR ; 237
+ DCD DefaultISR ; 238
+ DCD DefaultISR ; 239
+ DCD DefaultISR ; 240
+ DCD DefaultISR ; 241
+ DCD DefaultISR ; 242
+ DCD DefaultISR ; 243
+ DCD DefaultISR ; 244
+ DCD DefaultISR ; 245
+ DCD DefaultISR ; 246
+ DCD DefaultISR ; 247
+ DCD DefaultISR ; 248
+ DCD DefaultISR ; 249
+ DCD DefaultISR ; 250
+ DCD DefaultISR ; 251
+ DCD DefaultISR ; 252
+ DCD DefaultISR ; 253
+ DCD DefaultISR ; 254
+ DCD DefaultISR ; 255
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA4_IRQHandler [WEAK]
+ EXPORT DMA5_IRQHandler [WEAK]
+ EXPORT DMA6_IRQHandler [WEAK]
+ EXPORT DMA7_IRQHandler [WEAK]
+ EXPORT DMA8_IRQHandler [WEAK]
+ EXPORT DMA9_IRQHandler [WEAK]
+ EXPORT DMA10_IRQHandler [WEAK]
+ EXPORT DMA11_IRQHandler [WEAK]
+ EXPORT DMA12_IRQHandler [WEAK]
+ EXPORT DMA13_IRQHandler [WEAK]
+ EXPORT DMA14_IRQHandler [WEAK]
+ EXPORT DMA15_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT MCM_IRQHandler [WEAK]
+ EXPORT FTFE_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT UART3_RX_TX_IRQHandler [WEAK]
+ EXPORT UART3_ERR_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT FTM2_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT Reserved71_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART4_RX_TX_IRQHandler [WEAK]
+ EXPORT UART4_ERR_IRQHandler [WEAK]
+ EXPORT UART5_RX_TX_IRQHandler [WEAK]
+ EXPORT UART5_ERR_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT FTM3_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
+ EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
+ EXPORT CAN0_Error_IRQHandler [WEAK]
+ EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
+ EXPORT SDHC_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+Reserved39_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved71_IRQHandler
+DAC0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+SPI2_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+CMP2_IRQHandler
+FTM3_IRQHandler
+DAC1_IRQHandler
+ADC1_IRQHandler
+I2C2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+SDHC_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..b129b2c2a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
new file mode 100644
index 000000000..b7b3fe61c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
@@ -0,0 +1,164 @@
+/*
+ * K64F ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x000080000 - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFF0400, LENGTH = 0x000020000 - 0x00000400
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
new file mode 100644
index 000000000..2b5675164
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
@@ -0,0 +1,369 @@
+/* K64F startup ARM GCC
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xC00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
+ .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
+ .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
+ .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
+ .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
+ .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
+ .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
+ .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
+ .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
+ .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
+ .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
+ .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
+ .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
+ .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
+ .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
+ .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
+ .long DMA_Error_IRQHandler /* DMA Error Interrupt*/
+ .long MCM_IRQHandler /* Normal Interrupt*/
+ .long FTF_IRQHandler /* FTFA Command complete interrupt*/
+ .long Read_Collision_IRQHandler /* Read Collision Interrupt*/
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
+ .long LLW_IRQHandler /* Low Leakage Wakeup*/
+ .long Watchdog_IRQHandler /* WDOG Interrupt*/
+ .long RNG_IRQHandler /* RNG Interrupt*/
+ .long I2C0_IRQHandler /* I2C0 interrupt*/
+ .long I2C1_IRQHandler /* I2C1 interrupt*/
+ .long SPI0_IRQHandler /* SPI0 Interrupt*/
+ .long SPI1_IRQHandler /* SPI1 Interrupt*/
+ .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
+ .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
+ .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
+ .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
+ .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
+ .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
+ .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
+ .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
+ .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
+ .long Reserved53_IRQHandler /* Reserved interrupt 53*/
+ .long Reserved54_IRQHandler /* Reserved interrupt 54*/
+ .long ADC0_IRQHandler /* ADC0 interrupt*/
+ .long CMP0_IRQHandler /* CMP0 interrupt*/
+ .long CMP1_IRQHandler /* CMP1 interrupt*/
+ .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
+ .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
+ .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
+ .long Reserved61_IRQHandler /* Reserved interrupt 61*/
+ .long RTC_IRQHandler /* RTC interrupt*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
+ .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
+ .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
+ .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
+ .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
+ .long PDB0_IRQHandler /* PDB0 Interrupt*/
+ .long USB0_IRQHandler /* USB0 interrupt*/
+ .long Reserved70_IRQHandler /* Reserved interrupt 70*/
+ .long Reserved71_IRQHandler /* Reserved interrupt 71*/
+ .long DAC0_IRQHandler /* DAC0 interrupt*/
+ .long MCG_IRQHandler /* MCG Interrupt*/
+ .long LPTimer_IRQHandler /* LPTimer interrupt*/
+ .long PORTA_IRQHandler /* Port A interrupt*/
+ .long PORTB_IRQHandler /* Port B interrupt*/
+ .long PORTC_IRQHandler /* Port C interrupt*/
+ .long PORTD_IRQHandler /* Port D interrupt*/
+ .long PORTE_IRQHandler /* Port E interrupt*/
+ .long SWI_IRQHandler /* Software interrupt*/
+ .long Reserved81_IRQHandler /* Reserved interrupt 81*/
+ .long Reserved82_IRQHandler /* Reserved interrupt 82*/
+ .long Reserved83_IRQHandler /* Reserved interrupt 83*/
+ .long Reserved84_IRQHandler /* Reserved interrupt 84*/
+ .long Reserved85_IRQHandler /* Reserved interrupt 85*/
+ .long Reserved86_IRQHandler /* Reserved interrupt 86*/
+ .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
+ .long DAC1_IRQHandler /* DAC1 interrupt*/
+ .long ADC1_IRQHandler /* ADC1 interrupt*/
+ .long Reserved90_IRQHandler /* Reserved Interrupt 90*/
+ .long Reserved91_IRQHandler /* Reserved Interrupt 91*/
+ .long Reserved92_IRQHandler /* Reserved Interrupt 92*/
+ .long Reserved93_IRQHandler /* Reserved Interrupt 93*/
+ .long Reserved94_IRQHandler /* Reserved Interrupt 94*/
+ .long Reserved95_IRQHandler /* Reserved Interrupt 95*/
+ .long Reserved96_IRQHandler /* Reserved Interrupt 96*/
+ .long Reserved97_IRQHandler /* Reserved Interrupt 97*/
+ .long Reserved98_IRQHandler /* Reserved Interrupt 98*/
+ .long Reserved99_IRQHandler /* Reserved Interrupt 99*/
+ .long Reserved100_IRQHandler /* Reserved Interrupt 100*/
+ .long Reserved101_IRQHandler /* Reserved Interrupt 101*/
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+disable_watchdog:
+ /* unlock */
+ ldr r1, =0x4005200e
+ ldr r0, =0xc520
+ strh r0, [r1]
+ ldr r0, =0xd928
+ strh r0, [r1]
+ /* disable */
+ ldr r1, =0x40052000
+ ldr r0, =0x01d2
+ strh r0, [r1]
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+/* Exception Handlers */
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+/* IRQ Handlers */
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA4_IRQHandler
+ def_irq_default_handler DMA5_IRQHandler
+ def_irq_default_handler DMA6_IRQHandler
+ def_irq_default_handler DMA7_IRQHandler
+ def_irq_default_handler DMA8_IRQHandler
+ def_irq_default_handler DMA9_IRQHandler
+ def_irq_default_handler DMA10_IRQHandler
+ def_irq_default_handler DMA11_IRQHandler
+ def_irq_default_handler DMA12_IRQHandler
+ def_irq_default_handler DMA13_IRQHandler
+ def_irq_default_handler DMA14_IRQHandler
+ def_irq_default_handler DMA15_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler MCM_IRQHandler
+ def_irq_default_handler FTF_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler RNG_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler LPUART0_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler Reserved53_IRQHandler
+ def_irq_default_handler Reserved54_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler FTM2_IRQHandler
+ def_irq_default_handler Reserved61_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler Reserved70_IRQHandler
+ def_irq_default_handler Reserved71_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler Reserved81_IRQHandler
+ def_irq_default_handler Reserved82_IRQHandler
+ def_irq_default_handler Reserved83_IRQHandler
+ def_irq_default_handler Reserved84_IRQHandler
+ def_irq_default_handler Reserved85_IRQHandler
+ def_irq_default_handler Reserved86_IRQHandler
+ def_irq_default_handler FTM3_IRQHandler
+ def_irq_default_handler DAC1_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler Reserved90_IRQHandler
+ def_irq_default_handler Reserved91_IRQHandler
+ def_irq_default_handler Reserved92_IRQHandler
+ def_irq_default_handler Reserved93_IRQHandler
+ def_irq_default_handler Reserved94_IRQHandler
+ def_irq_default_handler Reserved95_IRQHandler
+ def_irq_default_handler Reserved96_IRQHandler
+ def_irq_default_handler Reserved97_IRQHandler
+ def_irq_default_handler Reserved98_IRQHandler
+ def_irq_default_handler Reserved99_IRQHandler
+ def_irq_default_handler Reserved100_IRQHandler
+ def_irq_default_handler Reserved101_IRQHandler
+ def_irq_default_handler DefaultISR
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
new file mode 100644
index 000000000..4955517c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff03ff;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0400;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x4000;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x2000ffff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
new file mode 100644
index 000000000..90ee34879
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
@@ -0,0 +1,535 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD 0 ; Reserved
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD 0 ; Reserved
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD Default_Handler ; 98
+ DCD Default_Handler ; 99
+ DCD Default_Handler ; 100
+ DCD Default_Handler ; 101
+ DCD Default_Handler ; 102
+ DCD Default_Handler ; 103
+ DCD Default_Handler ; 104
+ DCD Default_Handler ; 105
+ DCD Default_Handler ; 106
+ DCD Default_Handler ; 107
+ DCD Default_Handler ; 108
+ DCD Default_Handler ; 109
+ DCD Default_Handler ; 110
+ DCD Default_Handler ; 111
+ DCD Default_Handler ; 112
+ DCD Default_Handler ; 113
+ DCD Default_Handler ; 114
+ DCD Default_Handler ; 115
+ DCD Default_Handler ; 116
+ DCD Default_Handler ; 117
+ DCD Default_Handler ; 118
+ DCD Default_Handler ; 119
+ DCD Default_Handler ; 120
+ DCD Default_Handler ; 121
+ DCD Default_Handler ; 122
+ DCD Default_Handler ; 123
+ DCD Default_Handler ; 124
+ DCD Default_Handler ; 125
+ DCD Default_Handler ; 126
+ DCD Default_Handler ; 127
+ DCD Default_Handler ; 128
+ DCD Default_Handler ; 129
+ DCD Default_Handler ; 130
+ DCD Default_Handler ; 131
+ DCD Default_Handler ; 132
+ DCD Default_Handler ; 133
+ DCD Default_Handler ; 134
+ DCD Default_Handler ; 135
+ DCD Default_Handler ; 136
+ DCD Default_Handler ; 137
+ DCD Default_Handler ; 138
+ DCD Default_Handler ; 139
+ DCD Default_Handler ; 140
+ DCD Default_Handler ; 141
+ DCD Default_Handler ; 142
+ DCD Default_Handler ; 143
+ DCD Default_Handler ; 144
+ DCD Default_Handler ; 145
+ DCD Default_Handler ; 146
+ DCD Default_Handler ; 147
+ DCD Default_Handler ; 148
+ DCD Default_Handler ; 149
+ DCD Default_Handler ; 150
+ DCD Default_Handler ; 151
+ DCD Default_Handler ; 152
+ DCD Default_Handler ; 153
+ DCD Default_Handler ; 154
+ DCD Default_Handler ; 155
+ DCD Default_Handler ; 156
+ DCD Default_Handler ; 157
+ DCD Default_Handler ; 158
+ DCD Default_Handler ; 159
+ DCD Default_Handler ; 160
+ DCD Default_Handler ; 161
+ DCD Default_Handler ; 162
+ DCD Default_Handler ; 163
+ DCD Default_Handler ; 164
+ DCD Default_Handler ; 165
+ DCD Default_Handler ; 166
+ DCD Default_Handler ; 167
+ DCD Default_Handler ; 168
+ DCD Default_Handler ; 169
+ DCD Default_Handler ; 170
+ DCD Default_Handler ; 171
+ DCD Default_Handler ; 172
+ DCD Default_Handler ; 173
+ DCD Default_Handler ; 174
+ DCD Default_Handler ; 175
+ DCD Default_Handler ; 176
+ DCD Default_Handler ; 177
+ DCD Default_Handler ; 178
+ DCD Default_Handler ; 179
+ DCD Default_Handler ; 180
+ DCD Default_Handler ; 181
+ DCD Default_Handler ; 182
+ DCD Default_Handler ; 183
+ DCD Default_Handler ; 184
+ DCD Default_Handler ; 185
+ DCD Default_Handler ; 186
+ DCD Default_Handler ; 187
+ DCD Default_Handler ; 188
+ DCD Default_Handler ; 189
+ DCD Default_Handler ; 190
+ DCD Default_Handler ; 191
+ DCD Default_Handler ; 192
+ DCD Default_Handler ; 193
+ DCD Default_Handler ; 194
+ DCD Default_Handler ; 195
+ DCD Default_Handler ; 196
+ DCD Default_Handler ; 197
+ DCD Default_Handler ; 198
+ DCD Default_Handler ; 199
+ DCD Default_Handler ; 200
+ DCD Default_Handler ; 201
+ DCD Default_Handler ; 202
+ DCD Default_Handler ; 203
+ DCD Default_Handler ; 204
+ DCD Default_Handler ; 205
+ DCD Default_Handler ; 206
+ DCD Default_Handler ; 207
+ DCD Default_Handler ; 208
+ DCD Default_Handler ; 209
+ DCD Default_Handler ; 210
+ DCD Default_Handler ; 211
+ DCD Default_Handler ; 212
+ DCD Default_Handler ; 213
+ DCD Default_Handler ; 214
+ DCD Default_Handler ; 215
+ DCD Default_Handler ; 216
+ DCD Default_Handler ; 217
+ DCD Default_Handler ; 218
+ DCD Default_Handler ; 219
+ DCD Default_Handler ; 220
+ DCD Default_Handler ; 221
+ DCD Default_Handler ; 222
+ DCD Default_Handler ; 223
+ DCD Default_Handler ; 224
+ DCD Default_Handler ; 225
+ DCD Default_Handler ; 226
+ DCD Default_Handler ; 227
+ DCD Default_Handler ; 228
+ DCD Default_Handler ; 229
+ DCD Default_Handler ; 230
+ DCD Default_Handler ; 231
+ DCD Default_Handler ; 232
+ DCD Default_Handler ; 233
+ DCD Default_Handler ; 234
+ DCD Default_Handler ; 235
+ DCD Default_Handler ; 236
+ DCD Default_Handler ; 237
+ DCD Default_Handler ; 238
+ DCD Default_Handler ; 239
+ DCD Default_Handler ; 240
+ DCD Default_Handler ; 241
+ DCD Default_Handler ; 242
+ DCD Default_Handler ; 243
+ DCD Default_Handler ; 244
+ DCD Default_Handler ; 245
+ DCD Default_Handler ; 246
+ DCD Default_Handler ; 247
+ DCD Default_Handler ; 248
+ DCD Default_Handler ; 249
+ DCD Default_Handler ; 250
+ DCD Default_Handler ; 251
+ DCD Default_Handler ; 252
+ DCD Default_Handler ; 253
+ DCD Default_Handler ; 254
+ DCD Default_Handler ; 255
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT^0xFF
+
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK DMA4_IRQHandler
+ PUBWEAK DMA5_IRQHandler
+ PUBWEAK DMA6_IRQHandler
+ PUBWEAK DMA7_IRQHandler
+ PUBWEAK DMA8_IRQHandler
+ PUBWEAK DMA9_IRQHandler
+ PUBWEAK DMA10_IRQHandler
+ PUBWEAK DMA11_IRQHandler
+ PUBWEAK DMA12_IRQHandler
+ PUBWEAK DMA13_IRQHandler
+ PUBWEAK DMA14_IRQHandler
+ PUBWEAK DMA15_IRQHandler
+ PUBWEAK DMA_Error_IRQHandler
+ PUBWEAK MCM_IRQHandler
+ PUBWEAK FTFE_IRQHandler
+ PUBWEAK Read_Collision_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK Watchdog_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK I2S0_Tx_IRQHandler
+ PUBWEAK I2S0_Rx_IRQHandler
+ PUBWEAK UART0_LON_IRQHandler
+ PUBWEAK UART0_RX_TX_IRQHandler
+ PUBWEAK UART0_ERR_IRQHandler
+ PUBWEAK UART1_RX_TX_IRQHandler
+ PUBWEAK UART1_ERR_IRQHandler
+ PUBWEAK UART2_RX_TX_IRQHandler
+ PUBWEAK UART2_ERR_IRQHandler
+ PUBWEAK UART3_RX_TX_IRQHandler
+ PUBWEAK UART3_ERR_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK FTM0_IRQHandler
+ PUBWEAK FTM1_IRQHandler
+ PUBWEAK FTM2_IRQHandler
+ PUBWEAK CMT_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT0_IRQHandler
+ PUBWEAK PIT1_IRQHandler
+ PUBWEAK PIT2_IRQHandler
+ PUBWEAK PIT3_IRQHandler
+ PUBWEAK PDB0_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USBDCD_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+ PUBWEAK PORTC_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+ PUBWEAK PORTE_IRQHandler
+ PUBWEAK SWI_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ PUBWEAK UART4_RX_TX_IRQHandler
+ PUBWEAK UART4_ERR_IRQHandler
+ PUBWEAK UART5_RX_TX_IRQHandler
+ PUBWEAK UART5_ERR_IRQHandler
+ PUBWEAK CMP2_IRQHandler
+ PUBWEAK FTM3_IRQHandler
+ PUBWEAK DAC1_IRQHandler
+ PUBWEAK ADC1_IRQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
+ PUBWEAK CAN0_Bus_Off_IRQHandler
+ PUBWEAK CAN0_Error_IRQHandler
+ PUBWEAK CAN0_Tx_Warning_IRQHandler
+ PUBWEAK CAN0_Rx_Warning_IRQHandler
+ PUBWEAK CAN0_Wake_Up_IRQHandler
+ PUBWEAK SDHC_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+DAC0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+SPI2_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+CMP2_IRQHandler
+FTM3_IRQHandler
+DAC1_IRQHandler
+ADC1_IRQHandler
+I2C2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+SDHC_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
new file mode 100644
index 000000000..ff19283b7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK22F51212.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
new file mode 100644
index 000000000..fc13c884f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
new file mode 100644
index 000000000..206b64543
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
new file mode 100644
index 000000000..bc387c16c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
@@ -0,0 +1,395 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief Device specific configuration file for MK22F51212 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "cmsis.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+ /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+ WDOG_STCTRLH_WAITEN_MASK |
+ WDOG_STCTRLH_STOPEN_MASK |
+ WDOG_STCTRLH_ALLOWUPDATE_MASK |
+ WDOG_STCTRLH_CLKSRC_MASK |
+ 0x0100U;
+#endif /* (DISABLE_WDOG) */
+ if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+ {
+ if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+ {
+ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
+ }
+ } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+ if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+ RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+ RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+ RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+ }
+#endif
+ }
+
+ /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+ SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+ /* High speed run mode enable */
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
+ SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
+ while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
+ }
+#endif
+ /* System clock initialization */
+ /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+ if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
+ MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+ #if defined(SLOW_FINE_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+ #endif
+ #if defined(FAST_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+ #endif
+ #if defined(FAST_FINE_TRIM_ADDRESS)
+ MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+ #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+ }
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+ /* Set system prescalers and clock sources */
+ SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+ SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+ SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ /* Set MCG and OSC */
+#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_BLPI)
+ /* BLPI specific */
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+ #endif
+
+#else /* MCG_MODE */
+ /* Set MCG and OSC */
+#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+ #else
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ #endif
+ if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+ }
+ }
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+ /* Common for all MCG modes */
+
+ /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+ MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+ MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+ MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
+ }
+ /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+ MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+ }
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+ #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#elif (MCG_MODE == MCG_MODE_PEE)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+ SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+ while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
+ }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+ SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+ /* PLL loss of lock interrupt request initialization */
+ if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+ NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+ switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+ case 0x38U:
+ Divider = 1536U;
+ break;
+ case 0x30U:
+ Divider = 1280U;
+ break;
+ default:
+ Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ break;
+ }
+ } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+ Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ }
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x00U:
+ MCGOUTClock *= 640U;
+ break;
+ case 0x20U:
+ MCGOUTClock *= 1280U;
+ break;
+ case 0x40U:
+ MCGOUTClock *= 1920U;
+ break;
+ case 0x60U:
+ MCGOUTClock *= 2560U;
+ break;
+ case 0x80U:
+ MCGOUTClock *= 732U;
+ break;
+ case 0xA0U:
+ MCGOUTClock *= 1464U;
+ break;
+ case 0xC0U:
+ MCGOUTClock *= 2197U;
+ break;
+ case 0xE0U:
+ MCGOUTClock *= 2929U;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ /* PLL is selected */
+ Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
new file mode 100644
index 000000000..bdeed9c5a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
@@ -0,0 +1,367 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief Device specific configuration file for MK22F51212 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK22F51212_H_
+#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#define DISABLE_WDOG 1
+
+#ifndef CLOCK_SETUP
+ #define CLOCK_SETUP 4
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+ 0 ... Default part configuration
+ Multipurpose Clock Generator (MCG) in FEI mode.
+ Reference clock source for MCG module: Slow internal reference clock
+ Core clock = 20.97152MHz
+ Bus clock = 20.97152MHz
+ 1 ... Maximum achievable clock frequency configuration
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPI mode.
+ Reference clock source for MCG module: Fast internal reference clock
+ Core clock = 4MHz
+ Bus clock = 4MHz
+ 3 ... Chip externally clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 4MHz
+ Bus clock = 4MHz
+ 4 ... USB clock setup
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ 5 ... Maximum achievable clock frequency configuration in RUN mode
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 80MHz
+ Bus clock = 40MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#if (CLOCK_SETUP == 0)
+ #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
+ #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
+ /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
+ /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
+ #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+ #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 5)
+ #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
+ #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
+ #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK22F51212_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
new file mode 100644
index 000000000..cc046d06e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
@@ -0,0 +1,3613 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.3, 2012-10-04
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL05Z4
+**
+** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL05Z4.h
+ * @version 1.3
+ * @date 2012-10-04
+ * @brief CMSIS Peripheral Access Layer for MKL05Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL05Z4
+ */
+
+#if !defined(MKL05Z4_H_)
+#define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0003u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
+ Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
+ Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTB_IRQn = 31 /**< Port B interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL05Z4.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C6 Bit Fields */
+#define MCG_C6_CME_MASK 0x20u
+#define MCG_C6_CME_SHIFT 5
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
+ __I uint8_t S; /**< SPI status register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t D; /**< SPI data register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t M; /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK 0xFFu
+#define SPI_D_Bits_SHIFT 0
+#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK 0xFFu
+#define SPI_M_Bits_SHIFT 0
+#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART0_BDH_SBR_MASK 0x1Fu
+#define UART0_BDH_SBR_SHIFT 0
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK 0x20u
+#define UART0_BDH_SBNS_SHIFT 5
+#define UART0_BDH_RXEDGIE_MASK 0x40u
+#define UART0_BDH_RXEDGIE_SHIFT 6
+#define UART0_BDH_LBKDIE_MASK 0x80u
+#define UART0_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART0_BDL_SBR_MASK 0xFFu
+#define UART0_BDL_SBR_SHIFT 0
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART0_C1_PT_MASK 0x1u
+#define UART0_C1_PT_SHIFT 0
+#define UART0_C1_PE_MASK 0x2u
+#define UART0_C1_PE_SHIFT 1
+#define UART0_C1_ILT_MASK 0x4u
+#define UART0_C1_ILT_SHIFT 2
+#define UART0_C1_WAKE_MASK 0x8u
+#define UART0_C1_WAKE_SHIFT 3
+#define UART0_C1_M_MASK 0x10u
+#define UART0_C1_M_SHIFT 4
+#define UART0_C1_RSRC_MASK 0x20u
+#define UART0_C1_RSRC_SHIFT 5
+#define UART0_C1_DOZEEN_MASK 0x40u
+#define UART0_C1_DOZEEN_SHIFT 6
+#define UART0_C1_LOOPS_MASK 0x80u
+#define UART0_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART0_C2_SBK_MASK 0x1u
+#define UART0_C2_SBK_SHIFT 0
+#define UART0_C2_RWU_MASK 0x2u
+#define UART0_C2_RWU_SHIFT 1
+#define UART0_C2_RE_MASK 0x4u
+#define UART0_C2_RE_SHIFT 2
+#define UART0_C2_TE_MASK 0x8u
+#define UART0_C2_TE_SHIFT 3
+#define UART0_C2_ILIE_MASK 0x10u
+#define UART0_C2_ILIE_SHIFT 4
+#define UART0_C2_RIE_MASK 0x20u
+#define UART0_C2_RIE_SHIFT 5
+#define UART0_C2_TCIE_MASK 0x40u
+#define UART0_C2_TCIE_SHIFT 6
+#define UART0_C2_TIE_MASK 0x80u
+#define UART0_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART0_S1_PF_MASK 0x1u
+#define UART0_S1_PF_SHIFT 0
+#define UART0_S1_FE_MASK 0x2u
+#define UART0_S1_FE_SHIFT 1
+#define UART0_S1_NF_MASK 0x4u
+#define UART0_S1_NF_SHIFT 2
+#define UART0_S1_OR_MASK 0x8u
+#define UART0_S1_OR_SHIFT 3
+#define UART0_S1_IDLE_MASK 0x10u
+#define UART0_S1_IDLE_SHIFT 4
+#define UART0_S1_RDRF_MASK 0x20u
+#define UART0_S1_RDRF_SHIFT 5
+#define UART0_S1_TC_MASK 0x40u
+#define UART0_S1_TC_SHIFT 6
+#define UART0_S1_TDRE_MASK 0x80u
+#define UART0_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART0_S2_RAF_MASK 0x1u
+#define UART0_S2_RAF_SHIFT 0
+#define UART0_S2_LBKDE_MASK 0x2u
+#define UART0_S2_LBKDE_SHIFT 1
+#define UART0_S2_BRK13_MASK 0x4u
+#define UART0_S2_BRK13_SHIFT 2
+#define UART0_S2_RWUID_MASK 0x8u
+#define UART0_S2_RWUID_SHIFT 3
+#define UART0_S2_RXINV_MASK 0x10u
+#define UART0_S2_RXINV_SHIFT 4
+#define UART0_S2_MSBF_MASK 0x20u
+#define UART0_S2_MSBF_SHIFT 5
+#define UART0_S2_RXEDGIF_MASK 0x40u
+#define UART0_S2_RXEDGIF_SHIFT 6
+#define UART0_S2_LBKDIF_MASK 0x80u
+#define UART0_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART0_C3_PEIE_MASK 0x1u
+#define UART0_C3_PEIE_SHIFT 0
+#define UART0_C3_FEIE_MASK 0x2u
+#define UART0_C3_FEIE_SHIFT 1
+#define UART0_C3_NEIE_MASK 0x4u
+#define UART0_C3_NEIE_SHIFT 2
+#define UART0_C3_ORIE_MASK 0x8u
+#define UART0_C3_ORIE_SHIFT 3
+#define UART0_C3_TXINV_MASK 0x10u
+#define UART0_C3_TXINV_SHIFT 4
+#define UART0_C3_TXDIR_MASK 0x20u
+#define UART0_C3_TXDIR_SHIFT 5
+#define UART0_C3_R9T8_MASK 0x40u
+#define UART0_C3_R9T8_SHIFT 6
+#define UART0_C3_R8T9_MASK 0x80u
+#define UART0_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UART0_D_R0T0_MASK 0x1u
+#define UART0_D_R0T0_SHIFT 0
+#define UART0_D_R1T1_MASK 0x2u
+#define UART0_D_R1T1_SHIFT 1
+#define UART0_D_R2T2_MASK 0x4u
+#define UART0_D_R2T2_SHIFT 2
+#define UART0_D_R3T3_MASK 0x8u
+#define UART0_D_R3T3_SHIFT 3
+#define UART0_D_R4T4_MASK 0x10u
+#define UART0_D_R4T4_SHIFT 4
+#define UART0_D_R5T5_MASK 0x20u
+#define UART0_D_R5T5_SHIFT 5
+#define UART0_D_R6T6_MASK 0x40u
+#define UART0_D_R6T6_SHIFT 6
+#define UART0_D_R7T7_MASK 0x80u
+#define UART0_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UART0_MA1_MA_MASK 0xFFu
+#define UART0_MA1_MA_SHIFT 0
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART0_MA2_MA_MASK 0xFFu
+#define UART0_MA2_MA_SHIFT 0
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART0_C4_OSR_MASK 0x1Fu
+#define UART0_C4_OSR_SHIFT 0
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK 0x20u
+#define UART0_C4_M10_SHIFT 5
+#define UART0_C4_MAEN2_MASK 0x40u
+#define UART0_C4_MAEN2_SHIFT 6
+#define UART0_C4_MAEN1_MASK 0x80u
+#define UART0_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART0_C5_RESYNCDIS_MASK 0x1u
+#define UART0_C5_RESYNCDIS_SHIFT 0
+#define UART0_C5_BOTHEDGE_MASK 0x2u
+#define UART0_C5_BOTHEDGE_SHIFT 1
+#define UART0_C5_RDMAE_MASK 0x20u
+#define UART0_C5_RDMAE_SHIFT 5
+#define UART0_C5_TDMAE_MASK 0x80u
+#define UART0_C5_TDMAE_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASES { UART0 }
+
+/**
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
+#define DMA_REQC0 This_symbol_has_been_deprecated
+#define DMA_REQC1 This_symbol_has_been_deprecated
+#define DMA_REQC2 This_symbol_has_been_deprecated
+#define DMA_REQC3 This_symbol_has_been_deprecated
+#define MCG_C6_CME0_MASK MCG_C6_CME_MASK
+#define MCG_C6_CME0_SHIFT MCG_C6_CME_SHIFT
+#define MCM_MATCR_ATC0_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC0_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC0(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO0_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO0_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO1_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO1_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO2_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO2_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO3_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO3_SHIFT This_symbol_has_been_deprecated
+#define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
+#define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
+#define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
+#define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
+#define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
+#define UARTLP_Type UART0_Type
+#define UARTLP_BDH_REG UART0_BDH_REG
+#define UARTLP_BDL_REG UART0_BDL_REG
+#define UARTLP_C1_REG UART0_C1_REG
+#define UARTLP_C2_REG UART0_C2_REG
+#define UARTLP_S1_REG UART0_S1_REG
+#define UARTLP_S2_REG UART0_S2_REG
+#define UARTLP_C3_REG UART0_C3_REG
+#define UARTLP_D_REG UART0_D_REG
+#define UARTLP_MA1_REG UART0_MA1_REG
+#define UARTLP_MA2_REG UART0_MA2_REG
+#define UARTLP_C4_REG UART0_C4_REG
+#define UARTLP_C5_REG UART0_C5_REG
+#define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
+#define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
+#define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
+#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
+#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
+#define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
+#define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
+#define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
+#define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
+#define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
+#define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
+#define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
+#define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
+#define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
+#define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
+#define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
+#define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
+#define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
+#define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
+#define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
+#define UARTLP_C1_M_MASK UART0_C1_M_MASK
+#define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
+#define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
+#define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
+#define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
+#define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
+#define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
+#define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
+#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
+#define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
+#define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
+#define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
+#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
+#define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
+#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
+#define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
+#define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
+#define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
+#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
+#define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
+#define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
+#define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
+#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
+#define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
+#define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
+#define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
+#define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
+#define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
+#define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
+#define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
+#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
+#define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
+#define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
+#define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
+#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
+#define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
+#define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
+#define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
+#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
+#define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
+#define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
+#define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
+#define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
+#define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
+#define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
+#define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
+#define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
+#define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
+#define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
+#define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
+#define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
+#define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
+#define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
+#define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
+#define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
+#define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
+#define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
+#define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
+#define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
+#define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
+#define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
+#define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
+#define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
+#define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
+#define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
+#define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
+#define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
+#define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
+#define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
+#define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
+#define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
+#define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
+#define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
+#define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
+#define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
+#define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
+#define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
+#define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
+#define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
+#define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
+#define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
+#define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
+#define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
+#define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
+#define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
+#define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
+#define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
+#define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
+#define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
+#define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
+#define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
+#define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
+#define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
+#define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
+#define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
+#define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
+#define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
+#define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
+#define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
+#define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
+#define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
+#define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
+#define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
+#define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
+#define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
+#define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
+#define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
+#define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
+#define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
+#define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
+#define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
+#define UARTLP_BASES UARTLP_BASES
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL05Z4_H_) */
+
+/* MKL05Z4.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct
new file mode 100644
index 000000000..1afd9a9dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct
@@ -0,0 +1,12 @@
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x1000 - 0xC0 = 0xF40
+ RW_IRAM1 0x1FFFFCC0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s
new file mode 100644
index 000000000..0e8a17c57
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s
@@ -0,0 +1,348 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL05Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20000C00 ; Top of RAM
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD Reserved_25_IRQHandler ; Reserved interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD Reserved_27_IRQHandler ; Reserved interrupt 27
+ DCD UART0_IRQHandler ; UART0 status and error interrupt
+ DCD Reserved_29_IRQHandler ; Reserved interrupt 29
+ DCD Reserved_30_IRQHandler ; Reserved interrupt 30
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD Reserved_35_IRQHandler ; Reserved interrupt 35
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
+ DCD Reserved_39_IRQHandler ; Reserved interrupt 39
+ DCD Reserved_40_IRQHandler ; Reserved interrupt 40
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved_45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT Reserved_25_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT Reserved_27_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT Reserved_29_IRQHandler [WEAK]
+ EXPORT Reserved_30_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT Reserved_35_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved_39_IRQHandler [WEAK]
+ EXPORT Reserved_40_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved_45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+Reserved_25_IRQHandler
+SPI0_IRQHandler
+Reserved_27_IRQHandler
+UART0_IRQHandler
+Reserved_29_IRQHandler
+Reserved_30_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+Reserved_35_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved_39_IRQHandler
+Reserved_40_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved_45_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct
new file mode 100644
index 000000000..1afd9a9dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct
@@ -0,0 +1,12 @@
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x1000 - 0xC0 = 0xF40
+ RW_IRAM1 0x1FFFFCC0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s
new file mode 100644
index 000000000..2fbfad033
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL05Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20000C00 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD Reserved_25_IRQHandler ; Reserved interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD Reserved_27_IRQHandler ; Reserved interrupt 27
+ DCD UART0_IRQHandler ; UART0 status and error interrupt
+ DCD Reserved_29_IRQHandler ; Reserved interrupt 29
+ DCD Reserved_30_IRQHandler ; Reserved interrupt 30
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD Reserved_35_IRQHandler ; Reserved interrupt 35
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
+ DCD Reserved_39_IRQHandler ; Reserved interrupt 39
+ DCD Reserved_40_IRQHandler ; Reserved interrupt 40
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved_45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT Reserved_25_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT Reserved_27_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT Reserved_29_IRQHandler [WEAK]
+ EXPORT Reserved_30_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT Reserved_35_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved_39_IRQHandler [WEAK]
+ EXPORT Reserved_40_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved_45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+Reserved_25_IRQHandler
+SPI0_IRQHandler
+Reserved_27_IRQHandler
+UART0_IRQHandler
+Reserved_29_IRQHandler
+Reserved_30_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+Reserved_35_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved_39_IRQHandler
+Reserved_40_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved_45_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld
new file mode 100644
index 000000000..65eba85be
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld
@@ -0,0 +1,154 @@
+/*
+ * KL05Z ARM GCC linker script file, Martin Kojtal (0xc0170)
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000410
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 32K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFFCC0, LENGTH = 4K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ . = ALIGN(4);
+ } > VECTORS
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s
new file mode 100644
index 000000000..384c489e2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s
@@ -0,0 +1,225 @@
+/* KL05Z startup ARM GCC, Martin Kojtal (0xc0170)
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long Default_Handler /* Reserved interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long Default_Handler /* Reserved interrupt 27 */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long Default_Handler /* Reserved interrupt 29 */
+ .long Default_Handler /* Reserved interrupt 30 */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long Default_Handler /* Reserved interrupt 35 */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Default_Handler /* Reserved interrupt 39 */
+ .long Default_Handler /* Reserved interrupt 40 */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Default_Handler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTB_IRQHandler /* Port B interrupt */
+
+ .size __isr_vector, . - __isr_vector
+ .org 0x400, 0xff
+
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .flash_to_ram_loop_end
+
+ movs r4, 0
+.flash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ def_default_handler DMA0_IRQHandler
+ def_default_handler DMA1_IRQHandler
+ def_default_handler DMA2_IRQHandler
+ def_default_handler DMA3_IRQHandler
+ def_default_handler FTFA_IRQHandler
+ def_default_handler LVD_LVW_IRQHandler
+ def_default_handler LLW_IRQHandler
+ def_default_handler I2C0_IRQHandler
+ def_default_handler SPI0_IRQHandler
+ def_default_handler UART0_IRQHandler
+ def_default_handler ADC0_IRQHandler
+ def_default_handler CMP0_IRQHandler
+ def_default_handler TPM0_IRQHandler
+ def_default_handler TPM1_IRQHandler
+ def_default_handler RTC_IRQHandler
+ def_default_handler RTC_Seconds_IRQHandler
+ def_default_handler PIT_IRQHandler
+ def_default_handler DAC0_IRQHandler
+ def_default_handler TSI0_IRQHandler
+ def_default_handler MCG_IRQHandler
+ def_default_handler LPTimer_IRQHandler
+ def_default_handler PORTA_IRQHandler
+ def_default_handler PORTB_IRQHandler
+
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf
new file mode 100644
index 000000000..4bfab3fc1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007fff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffffc00;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffffcbf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1ffffcc0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20000bff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s
new file mode 100644
index 000000000..34b906e4f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s
@@ -0,0 +1,199 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
+ DCD 0 ; 4: Reserved
+ DCD FTFA_IRQHandler ; 5: FTFA
+ DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
+ DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
+ DCD 0 ; 9: Reserved
+ DCD SPI0_IRQHandler ;10: SPI0 intertrupt
+ DCD 0 ;11: Reserved
+ DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
+ DCD 0 ;13: Reserved
+ DCD 0 ;14: Reserved
+ DCD ADC0_IRQHandler ;15: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;16: CMP 0 interrupt
+ DCD TPM0_IRQHandler ;17: TPM 0 interrupt
+ DCD TPM1_IRQHandler ;18: TPM 1 interrupt
+ DCD 0 ;19: Reserved
+ DCD RTC_IRQHandler ;20: RTC interrupt
+ DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
+ DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
+ DCD 0 ;23: Reserved
+ DCD 0 ;24: Reserved
+ DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
+ DCD TSI0_IRQHandler ;26: TSI 0 interrupt
+ DCD MCG_IRQHandler ;27: MCG intertrupt
+ DCD LPTimer_IRQHandler ;28: LPTimer interrupt
+ DCD 0 ;29: Reserved
+ DCD PORTA_IRQHandler ;30: PORT A interrupt
+ DCD PORTB_IRQHandler ;31: PORT B interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+UART0_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h
new file mode 100644
index 000000000..6df5d3792
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in KL05Z specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL05Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c
new file mode 100644
index 000000000..cce960bdf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFFC00) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h
new file mode 100644
index 000000000..324e79704
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
new file mode 100644
index 000000000..012d472a7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
@@ -0,0 +1,256 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.6, 2013-04-11
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+** - rev. 1.4 (2012-11-22)
+** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
+** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
+** - rev. 1.5 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.6 (2013-04-11)
+** SystemInit methods updated with predefined initialization sequence.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL05Z4
+ * @version 1.6
+ * @date 2013-04-11
+ * @brief Device specific configuration file for MKL05Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL05Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 20.97MHz
+ 1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
+ Reference clock source for MCG module is an external crystal 32.768kHz
+ Core clock = 47.97MHz, BusClock = 23.98MHz
+ 2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
+ Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
+ Core clock = 4MHz, BusClock = 4MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(0x00) |
+ MCG_C1_FRDIV(0x00) |
+ MCG_C1_IREFS_MASK |
+ MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(0x00);
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
+ MCG_C4_DMX32_MASK |
+ MCG_C4_DRST_DRS(0x02)
+ )) | (uint8_t)(
+ MCG_C4_DRST_DRS(0x01)
+ ));
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
+ /* PORTA->PCR[3]: ISF=0,MUX=0 */
+ PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ /* PORTA->PCR[4]: ISF=0,MUX=0 */
+ PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ /* Switch to FEE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC4P_MASK;
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
+ /* MCG->C4: DMX32=1,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
+ MCG_C4_DRST_DRS(0x02)
+ )) | (uint8_t)(
+ MCG_C4_DMX32_MASK |
+ MCG_C4_DRST_DRS(0x01)
+ ));
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
+ /* MCG->SC: FCRDIV=0 */
+ MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
+ /* Switch to FBI Mode */
+ /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(0x01) |
+ MCG_C1_FRDIV(0x00) |
+ MCG_C1_IREFS_MASK |
+ MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+ }
+ /* Switch to BLPI Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
new file mode 100644
index 000000000..0fd05f2ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
@@ -0,0 +1,99 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.6, 2013-04-11
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+** - rev. 1.4 (2012-11-22)
+** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
+** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
+** - rev. 1.5 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.6 (2013-04-11)
+** SystemInit methods updated with predefined initialization sequence.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL05Z4
+ * @version 1.6
+ * @date 2013-04-11
+ * @brief Device specific configuration file for MKL05Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL05Z4_H_
+#define SYSTEM_MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL05Z4_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h
new file mode 100644
index 000000000..c54be80e8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h
@@ -0,0 +1,4155 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL25Z4
+**
+** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4.h
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief CMSIS Peripheral Access Layer for MKL25Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL25Z4
+ */
+
+#if !defined(MKL25Z4_H_)
+#define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ SPI1_IRQn = 11, /**< SPI1 interrupt */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ UART1_IRQn = 13, /**< UART1 status/error interrupt */
+ UART2_IRQn = 14, /**< UART2 status/error interrupt */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTD_IRQn = 31 /**< Port D interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL25Z4.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x40u
+#define CMP_MUXCR_PSTM_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
+ };
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* REQC_ARR Bit Fields */
+#define DMA_REQC_ARR_DMAC_MASK 0xFu
+#define DMA_REQC_ARR_DMAC_SHIFT 0
+#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
+#define DMA_REQC_ARR_CFSM_MASK 0x80u
+#define DMA_REQC_ARR_CFSM_SHIFT 7
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS_MASK 0x80u
+#define MCG_S_LOLS_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+#define SIM_SOPT5_UART1ODE_MASK 0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR_SHIFT 24
+#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
+ __I uint8_t S; /**< SPI status register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t D; /**< SPI data register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t M; /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPLPIE_MASK 0x40u
+#define SPI_C2_SPLPIE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK 0xFFu
+#define SPI_D_Bits_SHIFT 0
+#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK 0xFFu
+#define SPI_M_Bits_SHIFT 0
+#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1, TPM2 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK 0x1u
+#define UART_D_R0T0_SHIFT 0
+#define UART_D_R1T1_MASK 0x2u
+#define UART_D_R1T1_SHIFT 1
+#define UART_D_R2T2_MASK 0x4u
+#define UART_D_R2T2_SHIFT 2
+#define UART_D_R3T3_MASK 0x8u
+#define UART_D_R3T3_SHIFT 3
+#define UART_D_R4T4_MASK 0x10u
+#define UART_D_R4T4_SHIFT 4
+#define UART_D_R5T5_MASK 0x20u
+#define UART_D_R5T5_SHIFT 5
+#define UART_D_R6T6_MASK 0x40u
+#define UART_D_R6T6_SHIFT 6
+#define UART_D_R7T7_MASK 0x80u
+#define UART_D_R7T7_SHIFT 7
+/* C4 Bit Fields */
+#define UART_C4_LBKDDMAS_MASK 0x8u
+#define UART_C4_LBKDDMAS_SHIFT 3
+#define UART_C4_ILDMAS_MASK 0x10u
+#define UART_C4_ILDMAS_SHIFT 4
+#define UART_C4_RDMAS_MASK 0x20u
+#define UART_C4_RDMAS_SHIFT 5
+#define UART_C4_TCDMAS_MASK 0x40u
+#define UART_C4_TCDMAS_SHIFT 6
+#define UART_C4_TDMAS_MASK 0x80u
+#define UART_C4_TDMAS_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART1, UART2 }
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
+ * @{
+ */
+
+/** UARTLP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UARTLP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UARTLP_BDH_SBR_MASK 0x1Fu
+#define UARTLP_BDH_SBR_SHIFT 0
+#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
+#define UARTLP_BDH_SBNS_MASK 0x20u
+#define UARTLP_BDH_SBNS_SHIFT 5
+#define UARTLP_BDH_RXEDGIE_MASK 0x40u
+#define UARTLP_BDH_RXEDGIE_SHIFT 6
+#define UARTLP_BDH_LBKDIE_MASK 0x80u
+#define UARTLP_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UARTLP_BDL_SBR_MASK 0xFFu
+#define UARTLP_BDL_SBR_SHIFT 0
+#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UARTLP_C1_PT_MASK 0x1u
+#define UARTLP_C1_PT_SHIFT 0
+#define UARTLP_C1_PE_MASK 0x2u
+#define UARTLP_C1_PE_SHIFT 1
+#define UARTLP_C1_ILT_MASK 0x4u
+#define UARTLP_C1_ILT_SHIFT 2
+#define UARTLP_C1_WAKE_MASK 0x8u
+#define UARTLP_C1_WAKE_SHIFT 3
+#define UARTLP_C1_M_MASK 0x10u
+#define UARTLP_C1_M_SHIFT 4
+#define UARTLP_C1_RSRC_MASK 0x20u
+#define UARTLP_C1_RSRC_SHIFT 5
+#define UARTLP_C1_DOZEEN_MASK 0x40u
+#define UARTLP_C1_DOZEEN_SHIFT 6
+#define UARTLP_C1_LOOPS_MASK 0x80u
+#define UARTLP_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UARTLP_C2_SBK_MASK 0x1u
+#define UARTLP_C2_SBK_SHIFT 0
+#define UARTLP_C2_RWU_MASK 0x2u
+#define UARTLP_C2_RWU_SHIFT 1
+#define UARTLP_C2_RE_MASK 0x4u
+#define UARTLP_C2_RE_SHIFT 2
+#define UARTLP_C2_TE_MASK 0x8u
+#define UARTLP_C2_TE_SHIFT 3
+#define UARTLP_C2_ILIE_MASK 0x10u
+#define UARTLP_C2_ILIE_SHIFT 4
+#define UARTLP_C2_RIE_MASK 0x20u
+#define UARTLP_C2_RIE_SHIFT 5
+#define UARTLP_C2_TCIE_MASK 0x40u
+#define UARTLP_C2_TCIE_SHIFT 6
+#define UARTLP_C2_TIE_MASK 0x80u
+#define UARTLP_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UARTLP_S1_PF_MASK 0x1u
+#define UARTLP_S1_PF_SHIFT 0
+#define UARTLP_S1_FE_MASK 0x2u
+#define UARTLP_S1_FE_SHIFT 1
+#define UARTLP_S1_NF_MASK 0x4u
+#define UARTLP_S1_NF_SHIFT 2
+#define UARTLP_S1_OR_MASK 0x8u
+#define UARTLP_S1_OR_SHIFT 3
+#define UARTLP_S1_IDLE_MASK 0x10u
+#define UARTLP_S1_IDLE_SHIFT 4
+#define UARTLP_S1_RDRF_MASK 0x20u
+#define UARTLP_S1_RDRF_SHIFT 5
+#define UARTLP_S1_TC_MASK 0x40u
+#define UARTLP_S1_TC_SHIFT 6
+#define UARTLP_S1_TDRE_MASK 0x80u
+#define UARTLP_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UARTLP_S2_RAF_MASK 0x1u
+#define UARTLP_S2_RAF_SHIFT 0
+#define UARTLP_S2_LBKDE_MASK 0x2u
+#define UARTLP_S2_LBKDE_SHIFT 1
+#define UARTLP_S2_BRK13_MASK 0x4u
+#define UARTLP_S2_BRK13_SHIFT 2
+#define UARTLP_S2_RWUID_MASK 0x8u
+#define UARTLP_S2_RWUID_SHIFT 3
+#define UARTLP_S2_RXINV_MASK 0x10u
+#define UARTLP_S2_RXINV_SHIFT 4
+#define UARTLP_S2_MSBF_MASK 0x20u
+#define UARTLP_S2_MSBF_SHIFT 5
+#define UARTLP_S2_RXEDGIF_MASK 0x40u
+#define UARTLP_S2_RXEDGIF_SHIFT 6
+#define UARTLP_S2_LBKDIF_MASK 0x80u
+#define UARTLP_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UARTLP_C3_PEIE_MASK 0x1u
+#define UARTLP_C3_PEIE_SHIFT 0
+#define UARTLP_C3_FEIE_MASK 0x2u
+#define UARTLP_C3_FEIE_SHIFT 1
+#define UARTLP_C3_NEIE_MASK 0x4u
+#define UARTLP_C3_NEIE_SHIFT 2
+#define UARTLP_C3_ORIE_MASK 0x8u
+#define UARTLP_C3_ORIE_SHIFT 3
+#define UARTLP_C3_TXINV_MASK 0x10u
+#define UARTLP_C3_TXINV_SHIFT 4
+#define UARTLP_C3_TXDIR_MASK 0x20u
+#define UARTLP_C3_TXDIR_SHIFT 5
+#define UARTLP_C3_R9T8_MASK 0x40u
+#define UARTLP_C3_R9T8_SHIFT 6
+#define UARTLP_C3_R8T9_MASK 0x80u
+#define UARTLP_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UARTLP_D_R0T0_MASK 0x1u
+#define UARTLP_D_R0T0_SHIFT 0
+#define UARTLP_D_R1T1_MASK 0x2u
+#define UARTLP_D_R1T1_SHIFT 1
+#define UARTLP_D_R2T2_MASK 0x4u
+#define UARTLP_D_R2T2_SHIFT 2
+#define UARTLP_D_R3T3_MASK 0x8u
+#define UARTLP_D_R3T3_SHIFT 3
+#define UARTLP_D_R4T4_MASK 0x10u
+#define UARTLP_D_R4T4_SHIFT 4
+#define UARTLP_D_R5T5_MASK 0x20u
+#define UARTLP_D_R5T5_SHIFT 5
+#define UARTLP_D_R6T6_MASK 0x40u
+#define UARTLP_D_R6T6_SHIFT 6
+#define UARTLP_D_R7T7_MASK 0x80u
+#define UARTLP_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UARTLP_MA1_MA_MASK 0xFFu
+#define UARTLP_MA1_MA_SHIFT 0
+#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UARTLP_MA2_MA_MASK 0xFFu
+#define UARTLP_MA2_MA_SHIFT 0
+#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UARTLP_C4_OSR_MASK 0x1Fu
+#define UARTLP_C4_OSR_SHIFT 0
+#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
+#define UARTLP_C4_M10_MASK 0x20u
+#define UARTLP_C4_M10_SHIFT 5
+#define UARTLP_C4_MAEN2_MASK 0x40u
+#define UARTLP_C4_MAEN2_SHIFT 6
+#define UARTLP_C4_MAEN1_MASK 0x80u
+#define UARTLP_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UARTLP_C5_RESYNCDIS_MASK 0x1u
+#define UARTLP_C5_RESYNCDIS_SHIFT 0
+#define UARTLP_C5_BOTHEDGE_MASK 0x2u
+#define UARTLP_C5_BOTHEDGE_SHIFT 1
+#define UARTLP_C5_RDMAE_MASK 0x20u
+#define UARTLP_C5_RDMAE_SHIFT 5
+#define UARTLP_C5_TDMAE_MASK 0x80u
+#define UARTLP_C5_TDMAE_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UARTLP_Register_Masks */
+
+
+/* UARTLP - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UARTLP_Type *)UART0_BASE)
+/** Array initializer of UARTLP peripheral base pointers */
+#define UARTLP_BASES { UART0 }
+
+/**
+ * @}
+ */ /* end of group UARTLP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL25Z4_H_) */
+
+/* MKL25Z4.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
new file mode 100644
index 000000000..101606842
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s
new file mode 100644
index 000000000..e83f4fcbd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s
@@ -0,0 +1,353 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL25Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20003000 ; Top of RAM
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct
new file mode 100644
index 000000000..101606842
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s
new file mode 100644
index 000000000..19bec0a7c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL25Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20003000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld
new file mode 100644
index 000000000..6c8da015b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL25Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
new file mode 100644
index 000000000..d1a47ceaf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
@@ -0,0 +1,239 @@
+/* KL25Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Default_Handler /* Reserved interrupt 39 */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Default_Handler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
new file mode 100644
index 000000000..dc26b23e4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
@@ -0,0 +1,197 @@
+/*
+*****************************************************************************
+**
+** File : KL25Z128M4_flash.ld
+**
+** Default linker command file for Flash targets
+**
+*****************************************************************************
+*/
+/* Entry Point */
+ENTRY(__thumb_startup)
+
+/* Highest address of the user mode stack */
+_estack = 0x20003000; /* end of SRAM */
+__SP_INIT = _estack;
+
+/* Generate a link error if heap and stack don't fit into RAM */
+__heap_size = 0x400; /* required amount of heap */
+__stack_size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0xC0
+ m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10
+ m_text (rx) : ORIGIN = 0x00000800, LENGTH = 128K - 0x800
+ m_data (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K /* SRAM */
+}
+
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into Flash */
+ .interrupts :
+ {
+ __vector_table = .;
+ . = ALIGN(4);
+ KEEP(*(.vectortable)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .cfmprotect :
+ {
+ . = ALIGN(4);
+ KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */
+ . = ALIGN(4);
+ } > m_cfmprotrom
+
+ /* The program code and other data goes into Flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } > m_text
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ ___ROM_AT = .;
+ } > m_text
+
+ /* reserve MTB memory at the beginning of m_data */
+ .mtb : /* MTB buffer address as defined by the hardware */
+ {
+ . = ALIGN(8);
+ _mtb_start = .;
+ KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+ . = ALIGN(8);
+ _mtb_end = .;
+ } > m_data
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data : AT(___ROM_AT)
+ {
+ . = ALIGN(4);
+ __sinit__ = .;
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } > m_data
+
+ ___data_size = _edata - _sdata;
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ __START_BSS = .;
+ PROVIDE ( __bss_start__ = __START_BSS );
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ __END_BSS = .;
+ PROVIDE ( __bss_end__ = __END_BSS );
+ } > m_data
+
+ _romp_at = ___ROM_AT + SIZEOF(.data);
+ .romp : AT(_romp_at)
+ {
+ __S_romp = _romp_at;
+ LONG(___ROM_AT);
+ LONG(_sdata);
+ LONG(___data_size);
+ LONG(0);
+ LONG(0);
+ LONG(0);
+ } > m_data
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ __heap_addr = .;
+ . = . + __heap_size;
+ . = . + __stack_size;
+ . = ALIGN(4);
+ } > m_data
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
new file mode 100644
index 000000000..49a3a3735
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
@@ -0,0 +1,147 @@
+#include <string.h>
+#include <stdlib.h>
+
+#include "cmsis.h"
+
+// Linker Script
+extern unsigned long _estack;
+extern char __S_romp[];
+
+extern char __START_BSS[];
+extern char __END_BSS[];
+
+// CRT0
+extern void __init_registers();
+extern void __copy_rom_sections_to_ram(void);
+extern void __call_static_initializers(void);
+extern void __init_user();
+
+// User/mbed Defined
+extern int main();
+extern void mbed_exit(int return_code);
+
+void _ExitProcess(int return_code) {
+ mbed_exit(return_code);
+}
+
+void __thumb_startup(void) {
+ // Setup registers
+ __init_registers();
+
+ // Disable the Watchdog because it may reset the core before entering main().
+ SIM->COPC = 0x0;
+
+ // zero-fill the .bss section
+ memset(__START_BSS, 0, (__END_BSS - __START_BSS));
+
+ if (__S_romp != 0L)
+ __copy_rom_sections_to_ram();
+
+ // call C++ static initializers
+ __call_static_initializers();
+
+ // initializations before main, user specific
+ __init_user();
+
+ exit(main());
+
+ // should never get here
+ while (1);
+}
+
+void Default_Handler() {
+ __asm("bkpt");
+}
+
+/* Weak definitions of handlers point to Default_Handler if not implemented */
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void DMA0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA3_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTFL_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PMC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LLW_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void CMP0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Seconds_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PIT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USBOTG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void TSI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LPTimer_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTA_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTD_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+/* The Interrupt Vector Table */
+void (* const InterruptVector[])() __attribute__ ((section(".vectortable"))) = {
+ /* Processor exceptions */
+ (void(*)(void)) &_estack,
+ __thumb_startup,
+ NMI_Handler,
+ HardFault_Handler,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ SVC_Handler,
+ 0,
+ 0,
+ PendSV_Handler,
+ SysTick_Handler,
+
+ /* Interrupts */
+ DMA0_IRQHandler, /* DMA Channel 0 Transfer Complete and Error */
+ DMA1_IRQHandler, /* DMA Channel 1 Transfer Complete and Error */
+ DMA2_IRQHandler, /* DMA Channel 2 Transfer Complete and Error */
+ DMA3_IRQHandler, /* DMA Channel 3 Transfer Complete and Error */
+ MCM_IRQHandler, /* Normal Interrupt */
+ FTFL_IRQHandler, /* FTFL Interrupt */
+ PMC_IRQHandler, /* PMC Interrupt */
+ LLW_IRQHandler, /* Low Leakage Wake-up */
+ I2C0_IRQHandler, /* I2C0 interrupt */
+ I2C1_IRQHandler, /* I2C1 interrupt */
+ SPI0_IRQHandler, /* SPI0 Interrupt */
+ SPI1_IRQHandler, /* SPI1 Interrupt */
+ UART0_IRQHandler, /* UART0 Status and Error interrupt */
+ UART1_IRQHandler, /* UART1 Status and Error interrupt */
+ UART2_IRQHandler, /* UART2 Status and Error interrupt */
+ ADC0_IRQHandler, /* ADC0 interrupt */
+ CMP0_IRQHandler, /* CMP0 interrupt */
+ FTM0_IRQHandler, /* FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQHandler, /* FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQHandler, /* FTM2 fault, overflow and channels interrupt */
+ RTC_Alarm_IRQHandler, /* RTC Alarm interrupt */
+ RTC_Seconds_IRQHandler, /* RTC Seconds interrupt */
+ PIT_IRQHandler, /* PIT timer all channels interrupt */
+ Default_Handler, /* Reserved interrupt 39/23 */
+ USBOTG_IRQHandler, /* USB interrupt */
+ DAC0_IRQHandler, /* DAC0 interrupt */
+ TSI0_IRQHandler, /* TSI0 Interrupt */
+ MCG_IRQHandler, /* MCG Interrupt */
+ LPTimer_IRQHandler, /* LPTimer interrupt */
+ Default_Handler, /* Reserved interrupt 45/29 */
+ PORTA_IRQHandler, /* Port A interrupt */
+ PORTD_IRQHandler /* Port D interrupt */
+};
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
new file mode 100644
index 000000000..3ea44c046
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
@@ -0,0 +1,153 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 0x3F40
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s
new file mode 100644
index 000000000..84bfb6b68
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s
@@ -0,0 +1,226 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Reserved20_IRQHandler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Reserved39_IRQHandler /* Reserved interrupt 39 */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Reserved45_IRQHandler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .flash_to_ram_loop_end
+
+ movs r4, 0
+.flash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler DMA0_IRQHandler
+ def_default_handler DMA1_IRQHandler
+ def_default_handler DMA2_IRQHandler
+ def_default_handler DMA3_IRQHandler
+ def_default_handler Reserved20_IRQHandler
+ def_default_handler FTFA_IRQHandler
+ def_default_handler LVD_LVW_IRQHandler
+ def_default_handler LLW_IRQHandler
+ def_default_handler I2C0_IRQHandler
+ def_default_handler I2C1_IRQHandler
+ def_default_handler SPI0_IRQHandler
+ def_default_handler SPI1_IRQHandler
+ def_default_handler UART0_IRQHandler
+ def_default_handler UART1_IRQHandler
+ def_default_handler UART2_IRQHandler
+ def_default_handler ADC0_IRQHandler
+ def_default_handler CMP0_IRQHandler
+ def_default_handler TPM0_IRQHandler
+ def_default_handler TPM1_IRQHandler
+ def_default_handler TPM2_IRQHandler
+ def_default_handler RTC_IRQHandler
+ def_default_handler RTC_Seconds_IRQHandler
+ def_default_handler PIT_IRQHandler
+ def_default_handler Reserved39_IRQHandler
+ def_default_handler USB0_IRQHandler
+ def_default_handler DAC0_IRQHandler
+ def_default_handler TSI0_IRQHandler
+ def_default_handler MCG_IRQHandler
+ def_default_handler LPTimer_IRQHandler
+ def_default_handler Reserved45_IRQHandler
+ def_default_handler PORTA_IRQHandler
+ def_default_handler PORTD_IRQHandler
+
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf
new file mode 100644
index 000000000..55caa8084
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffff000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20002fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s
new file mode 100644
index 000000000..88a8a876e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s
@@ -0,0 +1,213 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
+ DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
+ DCD FTFA_IRQHandler ; 5: FTFA
+ DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
+ DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
+ DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
+ DCD SPI0_IRQHandler ;10: SPI0 intertrupt
+ DCD SPI1_IRQHandler ;11: SPI1 intertrupt
+ DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
+ DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
+ DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
+ DCD ADC0_IRQHandler ;15: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;16: CMP 0 interrupt
+ DCD TPM0_IRQHandler ;17: TPM 0 interrupt
+ DCD TPM1_IRQHandler ;18: TPM 1 interrupt
+ DCD TPM2_IRQHandler ;19: TPM 2 interrupt
+ DCD RTC_IRQHandler ;20: RTC Alarm interrupt
+ DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
+ DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
+ DCD 0 ;23: Reserved
+ DCD USB0_IRQHandler ;24: USB OTG intertrupt
+ DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
+ DCD TSI0_IRQHandler ;26: TSI 0 interrupt
+ DCD MCG_IRQHandler ;27: MCG intertrupt
+ DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
+ DCD 0 ;29: Reserved
+ DCD PORTA_IRQHandler ;30: PORT A interrupt
+ DCD PORTD_IRQHandler ;31: PORT D interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK TPM2_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h
new file mode 100644
index 000000000..82dab2b69
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL25Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c
new file mode 100644
index 000000000..cb17abc0d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c
new file mode 100644
index 000000000..92255f236
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c
@@ -0,0 +1,263 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL25Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 13.98MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 24MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06U;
+ /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00U;
+ /* MCG->C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+ OSC0->CR = (uint8_t)0x89U;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ MCG->C5 = (uint8_t)0x01U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1AU;
+ while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+ OSC0->CR = (uint8_t)0x89U;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+ MCG->C2 = (uint8_t)0x26U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h
new file mode 100644
index 000000000..69ed7b04e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL25Z4_H_
+#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
new file mode 100644
index 000000000..96162e2a8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
@@ -0,0 +1,8856 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.5, 2014-09-05
+** Build: b140905
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL43Z4
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+** - rev. 1.5 (2014-09-05)
+** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4.h
+ * @version 1.5
+ * @date 2014-09-05
+ * @brief CMSIS Peripheral Access Layer for MKL43Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL43Z4
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
+#define MKL43Z4_H_
+#define MCU_MKL43Z4
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
+ Reserved20_IRQn = 4, /**< Reserved interrupt */
+ FTFA_IRQn = 5, /**< Command complete and read collision */
+ PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
+ LLWU_IRQn = 7, /**< Low leakage wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C1 interrupt */
+ SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
+ SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
+ LPUART0_IRQn = 12, /**< LPUART0 status and error */
+ LPUART1_IRQn = 13, /**< LPUART1 status and error */
+ UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
+ TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
+ TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
+ RTC_IRQn = 20, /**< RTC alarm */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds */
+ PIT_IRQn = 22, /**< PIT interrupt */
+ I2S0_IRQn = 23, /**< I2S0 interrupt */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ Reserved42_IRQn = 26, /**< Reserved interrupt */
+ Reserved43_IRQn = 27, /**< Reserved interrupt */
+ LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
+ LCD_IRQn = 29, /**< LCD interrupt */
+ PORTA_IRQn = 30, /**< PORTA Pin detect */
+ PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL43Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
+#define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
+#define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
+#define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
+#define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_SAR0 DMA_SAR_REG(DMA0,0)
+#define DMA_DAR0 DMA_DAR_REG(DMA0,0)
+#define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
+#define DMA_DSR0 DMA_DSR_REG(DMA0,0)
+#define DMA_DCR0 DMA_DCR_REG(DMA0,0)
+#define DMA_SAR1 DMA_SAR_REG(DMA0,1)
+#define DMA_DAR1 DMA_DAR_REG(DMA0,1)
+#define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
+#define DMA_DSR1 DMA_DSR_REG(DMA0,1)
+#define DMA_DCR1 DMA_DCR_REG(DMA0,1)
+#define DMA_SAR2 DMA_SAR_REG(DMA0,2)
+#define DMA_DAR2 DMA_DAR_REG(DMA0,2)
+#define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
+#define DMA_DSR2 DMA_DSR_REG(DMA0,2)
+#define DMA_DCR2 DMA_DCR_REG(DMA0,2)
+#define DMA_SAR3 DMA_SAR_REG(DMA0,3)
+#define DMA_DAR3 DMA_DAR_REG(DMA0,3)
+#define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
+#define DMA_DSR3 DMA_DSR_REG(DMA0,3)
+#define DMA_DCR3 DMA_DCR_REG(DMA0,3)
+
+/* DMA - Register array accessors */
+#define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
+#define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
+#define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
+#define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
+#define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+#define DMAMUX0_BASE_PTR (DMAMUX0)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX0 }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX0 */
+#define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
+#define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
+#define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
+#define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
+ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
+ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
+ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
+ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
+ uint8_t RESERVED_3[76];
+ __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_4[112];
+ __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_5[240];
+ __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_6[112];
+ __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
+ uint8_t RESERVED_7[112];
+ __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_8[112];
+ __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
+ uint8_t RESERVED_9[112];
+ __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_10[112];
+ __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+ uint8_t RESERVED_11[112];
+ __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+} FLEXIO_Type, *FLEXIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register accessors */
+#define FLEXIO_VERID_REG(base) ((base)->VERID)
+#define FLEXIO_PARAM_REG(base) ((base)->PARAM)
+#define FLEXIO_CTRL_REG(base) ((base)->CTRL)
+#define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
+#define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
+#define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
+#define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
+#define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
+#define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
+#define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
+#define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
+#define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
+#define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
+#define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
+#define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
+#define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
+#define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
+#define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
+#define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
+#define FLEXIO_VERID_FEATURE_SHIFT 0
+#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK 0xFF0000u
+#define FLEXIO_VERID_MINOR_SHIFT 16
+#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
+#define FLEXIO_VERID_MAJOR_SHIFT 24
+#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
+#define FLEXIO_PARAM_SHIFTER_SHIFT 0
+#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK 0xFF00u
+#define FLEXIO_PARAM_TIMER_SHIFT 8
+#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK 0xFF0000u
+#define FLEXIO_PARAM_PIN_SHIFT 16
+#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
+#define FLEXIO_PARAM_TRIGGER_SHIFT 24
+#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
+/* CTRL Bit Fields */
+#define FLEXIO_CTRL_FLEXEN_MASK 0x1u
+#define FLEXIO_CTRL_FLEXEN_SHIFT 0
+#define FLEXIO_CTRL_SWRST_MASK 0x2u
+#define FLEXIO_CTRL_SWRST_SHIFT 1
+#define FLEXIO_CTRL_FASTACC_MASK 0x4u
+#define FLEXIO_CTRL_FASTACC_SHIFT 2
+#define FLEXIO_CTRL_DBGE_MASK 0x40000000u
+#define FLEXIO_CTRL_DBGE_SHIFT 30
+#define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
+#define FLEXIO_CTRL_DOZEN_SHIFT 31
+/* SHIFTSTAT Bit Fields */
+#define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
+#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
+/* SHIFTERR Bit Fields */
+#define FLEXIO_SHIFTERR_SEF_MASK 0xFu
+#define FLEXIO_SHIFTERR_SEF_SHIFT 0
+#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
+/* TIMSTAT Bit Fields */
+#define FLEXIO_TIMSTAT_TSF_MASK 0xFu
+#define FLEXIO_TIMSTAT_TSF_SHIFT 0
+#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
+/* SHIFTSIEN Bit Fields */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
+#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
+/* SHIFTEIEN Bit Fields */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
+#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
+/* TIMIEN Bit Fields */
+#define FLEXIO_TIMIEN_TEIE_MASK 0xFu
+#define FLEXIO_TIMIEN_TEIE_SHIFT 0
+#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
+/* SHIFTSDEN Bit Fields */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
+#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
+/* SHIFTCTL Bit Fields */
+#define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
+#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
+#define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
+#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
+#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
+#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/* SHIFTCFG Bit Fields */
+#define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
+#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
+#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
+/* SHIFTBUF Bit Fields */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/* SHIFTBUFBBS Bit Fields */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/* SHIFTBUFBYS Bit Fields */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/* SHIFTBUFBIS Bit Fields */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/* TIMCTL Bit Fields */
+#define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
+#define FLEXIO_TIMCTL_TIMOD_SHIFT 0
+#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
+#define FLEXIO_TIMCTL_PINPOL_SHIFT 7
+#define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
+#define FLEXIO_TIMCTL_PINSEL_SHIFT 8
+#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_TIMCTL_PINCFG_SHIFT 16
+#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
+#define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
+#define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
+#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
+/* TIMCFG Bit Fields */
+#define FLEXIO_TIMCFG_TSTART_MASK 0x2u
+#define FLEXIO_TIMCFG_TSTART_SHIFT 1
+#define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
+#define FLEXIO_TIMCFG_TSTOP_SHIFT 4
+#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
+#define FLEXIO_TIMCFG_TIMENA_SHIFT 8
+#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
+#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
+#define FLEXIO_TIMCFG_TIMRST_SHIFT 16
+#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
+#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
+#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
+/* TIMCMP Bit Fields */
+#define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
+#define FLEXIO_TIMCMP_CMP_SHIFT 0
+#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO base address */
+#define FLEXIO_BASE (0x4005F000u)
+/** Peripheral FLEXIO base pointer */
+#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
+#define FLEXIO_BASE_PTR (FLEXIO)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS { FLEXIO }
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register instance definitions */
+/* FLEXIO */
+#define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
+#define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
+#define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
+#define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
+#define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
+#define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
+#define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
+#define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
+#define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
+#define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
+#define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
+#define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
+#define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
+#define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
+#define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
+#define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
+#define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
+#define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
+#define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
+#define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
+
+/* FLEXIO - Register array accessors */
+#define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
+#define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
+#define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
+#define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
+#define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type, *FTFA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register accessors */
+#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFA_FSEC_REG(base) ((base)->FSEC)
+#define FTFA_FOPT_REG(base) ((base)->FOPT)
+#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+#define FTFA_BASE_PTR (FTFA)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register instance definitions */
+/* FTFA */
+#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
+#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
+#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
+#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
+#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
+#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
+#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
+#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
+#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
+#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
+#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
+#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
+#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
+#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
+#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
+#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
+#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
+#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
+#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
+#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+#define GPIOA_BASE_PTR (GPIOA)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+#define GPIOB_BASE_PTR (GPIOB)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+#define GPIOC_BASE_PTR (GPIOC)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+#define GPIOD_BASE_PTR (GPIOD)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
+#define GPIOE_BASE_PTR (GPIOE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* GPIOA */
+#define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
+#define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
+#define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
+#define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
+#define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
+#define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
+/* GPIOB */
+#define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
+#define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
+#define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
+#define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
+#define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
+#define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
+/* GPIOC */
+#define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
+#define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
+#define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
+#define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
+#define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
+#define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
+/* GPIOD */
+#define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
+#define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
+#define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
+#define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
+#define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
+#define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
+/* GPIOE */
+#define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
+#define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
+#define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
+#define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
+#define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
+#define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+ __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+#define I2C_S2_REG(base) ((base)->S2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/* S2 Bit Fields */
+#define I2C_S2_EMPTY_MASK 0x1u
+#define I2C_S2_EMPTY_SHIFT 0
+#define I2C_S2_ERROR_MASK 0x2u
+#define I2C_S2_ERROR_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+#define I2C0_S2 I2C_S2_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+#define I2C1_S2 I2C_S2_REG(I2C1)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1u
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_ONDEM_MASK 0x4u
+#define I2S_TCR4_ONDEM_SHIFT 2
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x10000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FPACK_MASK 0x3000000u
+#define I2S_TCR4_FPACK_SHIFT 24
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK 0x10000000u
+#define I2S_TCR4_FCONT_SHIFT 28
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0x3u
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1u
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_ONDEM_MASK 0x4u
+#define I2S_RCR4_ONDEM_SHIFT 2
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x10000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FPACK_MASK 0x3000000u
+#define I2S_RCR4_FPACK_SHIFT 24
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK 0x10000000u
+#define I2S_RCR4_FCONT_SHIFT 28
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0x3u
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_IRQn }
+#define I2S_TX_IRQS { I2S0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
+ __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
+ __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
+ __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
+ __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+ union { /* offset: 0x20 */
+ __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+ __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+ };
+} LCD_Type, *LCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
+ * @{
+ */
+
+
+/* LCD - Register accessors */
+#define LCD_GCR_REG(base) ((base)->GCR)
+#define LCD_AR_REG(base) ((base)->AR)
+#define LCD_FDCR_REG(base) ((base)->FDCR)
+#define LCD_FDSR_REG(base) ((base)->FDSR)
+#define LCD_PEN_REG(base,index) ((base)->PEN[index])
+#define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
+#define LCD_WF_REG(base,index2) ((base)->WF[index2])
+#define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK 0x7u
+#define LCD_GCR_DUTY_SHIFT 0
+#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK 0x38u
+#define LCD_GCR_LCLK_SHIFT 3
+#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK 0x40u
+#define LCD_GCR_SOURCE_SHIFT 6
+#define LCD_GCR_LCDEN_MASK 0x80u
+#define LCD_GCR_LCDEN_SHIFT 7
+#define LCD_GCR_LCDSTP_MASK 0x100u
+#define LCD_GCR_LCDSTP_SHIFT 8
+#define LCD_GCR_LCDDOZE_MASK 0x200u
+#define LCD_GCR_LCDDOZE_SHIFT 9
+#define LCD_GCR_FFR_MASK 0x400u
+#define LCD_GCR_FFR_SHIFT 10
+#define LCD_GCR_ALTSOURCE_MASK 0x800u
+#define LCD_GCR_ALTSOURCE_SHIFT 11
+#define LCD_GCR_ALTDIV_MASK 0x3000u
+#define LCD_GCR_ALTDIV_SHIFT 12
+#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK 0x4000u
+#define LCD_GCR_FDCIEN_SHIFT 14
+#define LCD_GCR_PADSAFE_MASK 0x8000u
+#define LCD_GCR_PADSAFE_SHIFT 15
+#define LCD_GCR_VSUPPLY_MASK 0x20000u
+#define LCD_GCR_VSUPPLY_SHIFT 17
+#define LCD_GCR_LADJ_MASK 0x300000u
+#define LCD_GCR_LADJ_SHIFT 20
+#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_CPSEL_MASK 0x800000u
+#define LCD_GCR_CPSEL_SHIFT 23
+#define LCD_GCR_RVTRIM_MASK 0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT 24
+#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK 0x80000000u
+#define LCD_GCR_RVEN_SHIFT 31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK 0x7u
+#define LCD_AR_BRATE_SHIFT 0
+#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK 0x8u
+#define LCD_AR_BMODE_SHIFT 3
+#define LCD_AR_BLANK_MASK 0x20u
+#define LCD_AR_BLANK_SHIFT 5
+#define LCD_AR_ALT_MASK 0x40u
+#define LCD_AR_ALT_SHIFT 6
+#define LCD_AR_BLINK_MASK 0x80u
+#define LCD_AR_BLINK_SHIFT 7
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK 0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT 0
+#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK 0x40u
+#define LCD_FDCR_FDBPEN_SHIFT 6
+#define LCD_FDCR_FDEN_MASK 0x80u
+#define LCD_FDCR_FDEN_SHIFT 7
+#define LCD_FDCR_FDSWW_MASK 0xE00u
+#define LCD_FDCR_FDSWW_SHIFT 9
+#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK 0x7000u
+#define LCD_FDCR_FDPRS_SHIFT 12
+#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK 0xFFu
+#define LCD_FDSR_FDCNT_SHIFT 0
+#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK 0x8000u
+#define LCD_FDSR_FDCF_SHIFT 15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT 0
+#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT 0
+#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK 0xFFu
+#define LCD_WF_WF0_SHIFT 0
+#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK 0xFFu
+#define LCD_WF_WF60_SHIFT 0
+#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK 0xFFu
+#define LCD_WF_WF56_SHIFT 0
+#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK 0xFFu
+#define LCD_WF_WF52_SHIFT 0
+#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK 0xFFu
+#define LCD_WF_WF4_SHIFT 0
+#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK 0xFFu
+#define LCD_WF_WF48_SHIFT 0
+#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK 0xFFu
+#define LCD_WF_WF44_SHIFT 0
+#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK 0xFFu
+#define LCD_WF_WF40_SHIFT 0
+#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK 0xFFu
+#define LCD_WF_WF8_SHIFT 0
+#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK 0xFFu
+#define LCD_WF_WF36_SHIFT 0
+#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK 0xFFu
+#define LCD_WF_WF32_SHIFT 0
+#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK 0xFFu
+#define LCD_WF_WF28_SHIFT 0
+#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK 0xFFu
+#define LCD_WF_WF12_SHIFT 0
+#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK 0xFFu
+#define LCD_WF_WF24_SHIFT 0
+#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK 0xFFu
+#define LCD_WF_WF20_SHIFT 0
+#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK 0xFFu
+#define LCD_WF_WF16_SHIFT 0
+#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK 0xFF00u
+#define LCD_WF_WF5_SHIFT 8
+#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK 0xFF00u
+#define LCD_WF_WF49_SHIFT 8
+#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK 0xFF00u
+#define LCD_WF_WF45_SHIFT 8
+#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK 0xFF00u
+#define LCD_WF_WF61_SHIFT 8
+#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK 0xFF00u
+#define LCD_WF_WF25_SHIFT 8
+#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK 0xFF00u
+#define LCD_WF_WF17_SHIFT 8
+#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK 0xFF00u
+#define LCD_WF_WF41_SHIFT 8
+#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK 0xFF00u
+#define LCD_WF_WF13_SHIFT 8
+#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK 0xFF00u
+#define LCD_WF_WF57_SHIFT 8
+#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK 0xFF00u
+#define LCD_WF_WF53_SHIFT 8
+#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK 0xFF00u
+#define LCD_WF_WF37_SHIFT 8
+#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK 0xFF00u
+#define LCD_WF_WF9_SHIFT 8
+#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK 0xFF00u
+#define LCD_WF_WF1_SHIFT 8
+#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK 0xFF00u
+#define LCD_WF_WF29_SHIFT 8
+#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK 0xFF00u
+#define LCD_WF_WF33_SHIFT 8
+#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK 0xFF00u
+#define LCD_WF_WF21_SHIFT 8
+#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK 0xFF0000u
+#define LCD_WF_WF26_SHIFT 16
+#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK 0xFF0000u
+#define LCD_WF_WF46_SHIFT 16
+#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK 0xFF0000u
+#define LCD_WF_WF6_SHIFT 16
+#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK 0xFF0000u
+#define LCD_WF_WF42_SHIFT 16
+#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK 0xFF0000u
+#define LCD_WF_WF18_SHIFT 16
+#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK 0xFF0000u
+#define LCD_WF_WF38_SHIFT 16
+#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK 0xFF0000u
+#define LCD_WF_WF22_SHIFT 16
+#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK 0xFF0000u
+#define LCD_WF_WF34_SHIFT 16
+#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK 0xFF0000u
+#define LCD_WF_WF50_SHIFT 16
+#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK 0xFF0000u
+#define LCD_WF_WF14_SHIFT 16
+#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK 0xFF0000u
+#define LCD_WF_WF54_SHIFT 16
+#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK 0xFF0000u
+#define LCD_WF_WF2_SHIFT 16
+#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK 0xFF0000u
+#define LCD_WF_WF58_SHIFT 16
+#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK 0xFF0000u
+#define LCD_WF_WF30_SHIFT 16
+#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK 0xFF0000u
+#define LCD_WF_WF62_SHIFT 16
+#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK 0xFF0000u
+#define LCD_WF_WF10_SHIFT 16
+#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK 0xFF000000u
+#define LCD_WF_WF63_SHIFT 24
+#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK 0xFF000000u
+#define LCD_WF_WF59_SHIFT 24
+#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK 0xFF000000u
+#define LCD_WF_WF55_SHIFT 24
+#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK 0xFF000000u
+#define LCD_WF_WF3_SHIFT 24
+#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK 0xFF000000u
+#define LCD_WF_WF51_SHIFT 24
+#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK 0xFF000000u
+#define LCD_WF_WF47_SHIFT 24
+#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK 0xFF000000u
+#define LCD_WF_WF43_SHIFT 24
+#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK 0xFF000000u
+#define LCD_WF_WF7_SHIFT 24
+#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK 0xFF000000u
+#define LCD_WF_WF39_SHIFT 24
+#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK 0xFF000000u
+#define LCD_WF_WF35_SHIFT 24
+#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK 0xFF000000u
+#define LCD_WF_WF31_SHIFT 24
+#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK 0xFF000000u
+#define LCD_WF_WF11_SHIFT 24
+#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK 0xFF000000u
+#define LCD_WF_WF27_SHIFT 24
+#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK 0xFF000000u
+#define LCD_WF_WF23_SHIFT 24
+#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK 0xFF000000u
+#define LCD_WF_WF19_SHIFT 24
+#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK 0xFF000000u
+#define LCD_WF_WF15_SHIFT 24
+#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK 0x1u
+#define LCD_WF8B_BPALCD0_SHIFT 0
+#define LCD_WF8B_BPALCD63_MASK 0x1u
+#define LCD_WF8B_BPALCD63_SHIFT 0
+#define LCD_WF8B_BPALCD62_MASK 0x1u
+#define LCD_WF8B_BPALCD62_SHIFT 0
+#define LCD_WF8B_BPALCD61_MASK 0x1u
+#define LCD_WF8B_BPALCD61_SHIFT 0
+#define LCD_WF8B_BPALCD60_MASK 0x1u
+#define LCD_WF8B_BPALCD60_SHIFT 0
+#define LCD_WF8B_BPALCD59_MASK 0x1u
+#define LCD_WF8B_BPALCD59_SHIFT 0
+#define LCD_WF8B_BPALCD58_MASK 0x1u
+#define LCD_WF8B_BPALCD58_SHIFT 0
+#define LCD_WF8B_BPALCD57_MASK 0x1u
+#define LCD_WF8B_BPALCD57_SHIFT 0
+#define LCD_WF8B_BPALCD1_MASK 0x1u
+#define LCD_WF8B_BPALCD1_SHIFT 0
+#define LCD_WF8B_BPALCD56_MASK 0x1u
+#define LCD_WF8B_BPALCD56_SHIFT 0
+#define LCD_WF8B_BPALCD55_MASK 0x1u
+#define LCD_WF8B_BPALCD55_SHIFT 0
+#define LCD_WF8B_BPALCD54_MASK 0x1u
+#define LCD_WF8B_BPALCD54_SHIFT 0
+#define LCD_WF8B_BPALCD53_MASK 0x1u
+#define LCD_WF8B_BPALCD53_SHIFT 0
+#define LCD_WF8B_BPALCD52_MASK 0x1u
+#define LCD_WF8B_BPALCD52_SHIFT 0
+#define LCD_WF8B_BPALCD51_MASK 0x1u
+#define LCD_WF8B_BPALCD51_SHIFT 0
+#define LCD_WF8B_BPALCD50_MASK 0x1u
+#define LCD_WF8B_BPALCD50_SHIFT 0
+#define LCD_WF8B_BPALCD2_MASK 0x1u
+#define LCD_WF8B_BPALCD2_SHIFT 0
+#define LCD_WF8B_BPALCD49_MASK 0x1u
+#define LCD_WF8B_BPALCD49_SHIFT 0
+#define LCD_WF8B_BPALCD48_MASK 0x1u
+#define LCD_WF8B_BPALCD48_SHIFT 0
+#define LCD_WF8B_BPALCD47_MASK 0x1u
+#define LCD_WF8B_BPALCD47_SHIFT 0
+#define LCD_WF8B_BPALCD46_MASK 0x1u
+#define LCD_WF8B_BPALCD46_SHIFT 0
+#define LCD_WF8B_BPALCD45_MASK 0x1u
+#define LCD_WF8B_BPALCD45_SHIFT 0
+#define LCD_WF8B_BPALCD44_MASK 0x1u
+#define LCD_WF8B_BPALCD44_SHIFT 0
+#define LCD_WF8B_BPALCD43_MASK 0x1u
+#define LCD_WF8B_BPALCD43_SHIFT 0
+#define LCD_WF8B_BPALCD3_MASK 0x1u
+#define LCD_WF8B_BPALCD3_SHIFT 0
+#define LCD_WF8B_BPALCD42_MASK 0x1u
+#define LCD_WF8B_BPALCD42_SHIFT 0
+#define LCD_WF8B_BPALCD41_MASK 0x1u
+#define LCD_WF8B_BPALCD41_SHIFT 0
+#define LCD_WF8B_BPALCD40_MASK 0x1u
+#define LCD_WF8B_BPALCD40_SHIFT 0
+#define LCD_WF8B_BPALCD39_MASK 0x1u
+#define LCD_WF8B_BPALCD39_SHIFT 0
+#define LCD_WF8B_BPALCD38_MASK 0x1u
+#define LCD_WF8B_BPALCD38_SHIFT 0
+#define LCD_WF8B_BPALCD37_MASK 0x1u
+#define LCD_WF8B_BPALCD37_SHIFT 0
+#define LCD_WF8B_BPALCD36_MASK 0x1u
+#define LCD_WF8B_BPALCD36_SHIFT 0
+#define LCD_WF8B_BPALCD4_MASK 0x1u
+#define LCD_WF8B_BPALCD4_SHIFT 0
+#define LCD_WF8B_BPALCD35_MASK 0x1u
+#define LCD_WF8B_BPALCD35_SHIFT 0
+#define LCD_WF8B_BPALCD34_MASK 0x1u
+#define LCD_WF8B_BPALCD34_SHIFT 0
+#define LCD_WF8B_BPALCD33_MASK 0x1u
+#define LCD_WF8B_BPALCD33_SHIFT 0
+#define LCD_WF8B_BPALCD32_MASK 0x1u
+#define LCD_WF8B_BPALCD32_SHIFT 0
+#define LCD_WF8B_BPALCD31_MASK 0x1u
+#define LCD_WF8B_BPALCD31_SHIFT 0
+#define LCD_WF8B_BPALCD30_MASK 0x1u
+#define LCD_WF8B_BPALCD30_SHIFT 0
+#define LCD_WF8B_BPALCD29_MASK 0x1u
+#define LCD_WF8B_BPALCD29_SHIFT 0
+#define LCD_WF8B_BPALCD5_MASK 0x1u
+#define LCD_WF8B_BPALCD5_SHIFT 0
+#define LCD_WF8B_BPALCD28_MASK 0x1u
+#define LCD_WF8B_BPALCD28_SHIFT 0
+#define LCD_WF8B_BPALCD27_MASK 0x1u
+#define LCD_WF8B_BPALCD27_SHIFT 0
+#define LCD_WF8B_BPALCD26_MASK 0x1u
+#define LCD_WF8B_BPALCD26_SHIFT 0
+#define LCD_WF8B_BPALCD25_MASK 0x1u
+#define LCD_WF8B_BPALCD25_SHIFT 0
+#define LCD_WF8B_BPALCD24_MASK 0x1u
+#define LCD_WF8B_BPALCD24_SHIFT 0
+#define LCD_WF8B_BPALCD23_MASK 0x1u
+#define LCD_WF8B_BPALCD23_SHIFT 0
+#define LCD_WF8B_BPALCD22_MASK 0x1u
+#define LCD_WF8B_BPALCD22_SHIFT 0
+#define LCD_WF8B_BPALCD6_MASK 0x1u
+#define LCD_WF8B_BPALCD6_SHIFT 0
+#define LCD_WF8B_BPALCD21_MASK 0x1u
+#define LCD_WF8B_BPALCD21_SHIFT 0
+#define LCD_WF8B_BPALCD20_MASK 0x1u
+#define LCD_WF8B_BPALCD20_SHIFT 0
+#define LCD_WF8B_BPALCD19_MASK 0x1u
+#define LCD_WF8B_BPALCD19_SHIFT 0
+#define LCD_WF8B_BPALCD18_MASK 0x1u
+#define LCD_WF8B_BPALCD18_SHIFT 0
+#define LCD_WF8B_BPALCD17_MASK 0x1u
+#define LCD_WF8B_BPALCD17_SHIFT 0
+#define LCD_WF8B_BPALCD16_MASK 0x1u
+#define LCD_WF8B_BPALCD16_SHIFT 0
+#define LCD_WF8B_BPALCD15_MASK 0x1u
+#define LCD_WF8B_BPALCD15_SHIFT 0
+#define LCD_WF8B_BPALCD7_MASK 0x1u
+#define LCD_WF8B_BPALCD7_SHIFT 0
+#define LCD_WF8B_BPALCD14_MASK 0x1u
+#define LCD_WF8B_BPALCD14_SHIFT 0
+#define LCD_WF8B_BPALCD13_MASK 0x1u
+#define LCD_WF8B_BPALCD13_SHIFT 0
+#define LCD_WF8B_BPALCD12_MASK 0x1u
+#define LCD_WF8B_BPALCD12_SHIFT 0
+#define LCD_WF8B_BPALCD11_MASK 0x1u
+#define LCD_WF8B_BPALCD11_SHIFT 0
+#define LCD_WF8B_BPALCD10_MASK 0x1u
+#define LCD_WF8B_BPALCD10_SHIFT 0
+#define LCD_WF8B_BPALCD9_MASK 0x1u
+#define LCD_WF8B_BPALCD9_SHIFT 0
+#define LCD_WF8B_BPALCD8_MASK 0x1u
+#define LCD_WF8B_BPALCD8_SHIFT 0
+#define LCD_WF8B_BPBLCD1_MASK 0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT 1
+#define LCD_WF8B_BPBLCD32_MASK 0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT 1
+#define LCD_WF8B_BPBLCD30_MASK 0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT 1
+#define LCD_WF8B_BPBLCD60_MASK 0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT 1
+#define LCD_WF8B_BPBLCD24_MASK 0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT 1
+#define LCD_WF8B_BPBLCD28_MASK 0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT 1
+#define LCD_WF8B_BPBLCD23_MASK 0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT 1
+#define LCD_WF8B_BPBLCD48_MASK 0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT 1
+#define LCD_WF8B_BPBLCD10_MASK 0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT 1
+#define LCD_WF8B_BPBLCD15_MASK 0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT 1
+#define LCD_WF8B_BPBLCD36_MASK 0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT 1
+#define LCD_WF8B_BPBLCD44_MASK 0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT 1
+#define LCD_WF8B_BPBLCD62_MASK 0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT 1
+#define LCD_WF8B_BPBLCD53_MASK 0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT 1
+#define LCD_WF8B_BPBLCD22_MASK 0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT 1
+#define LCD_WF8B_BPBLCD47_MASK 0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT 1
+#define LCD_WF8B_BPBLCD33_MASK 0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT 1
+#define LCD_WF8B_BPBLCD2_MASK 0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT 1
+#define LCD_WF8B_BPBLCD49_MASK 0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT 1
+#define LCD_WF8B_BPBLCD0_MASK 0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT 1
+#define LCD_WF8B_BPBLCD55_MASK 0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT 1
+#define LCD_WF8B_BPBLCD56_MASK 0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT 1
+#define LCD_WF8B_BPBLCD21_MASK 0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT 1
+#define LCD_WF8B_BPBLCD6_MASK 0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT 1
+#define LCD_WF8B_BPBLCD29_MASK 0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT 1
+#define LCD_WF8B_BPBLCD25_MASK 0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT 1
+#define LCD_WF8B_BPBLCD8_MASK 0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT 1
+#define LCD_WF8B_BPBLCD54_MASK 0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT 1
+#define LCD_WF8B_BPBLCD38_MASK 0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT 1
+#define LCD_WF8B_BPBLCD43_MASK 0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT 1
+#define LCD_WF8B_BPBLCD20_MASK 0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT 1
+#define LCD_WF8B_BPBLCD9_MASK 0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT 1
+#define LCD_WF8B_BPBLCD7_MASK 0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT 1
+#define LCD_WF8B_BPBLCD50_MASK 0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT 1
+#define LCD_WF8B_BPBLCD40_MASK 0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT 1
+#define LCD_WF8B_BPBLCD63_MASK 0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT 1
+#define LCD_WF8B_BPBLCD26_MASK 0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT 1
+#define LCD_WF8B_BPBLCD12_MASK 0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT 1
+#define LCD_WF8B_BPBLCD19_MASK 0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT 1
+#define LCD_WF8B_BPBLCD34_MASK 0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT 1
+#define LCD_WF8B_BPBLCD39_MASK 0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT 1
+#define LCD_WF8B_BPBLCD59_MASK 0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT 1
+#define LCD_WF8B_BPBLCD61_MASK 0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT 1
+#define LCD_WF8B_BPBLCD37_MASK 0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT 1
+#define LCD_WF8B_BPBLCD31_MASK 0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT 1
+#define LCD_WF8B_BPBLCD58_MASK 0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT 1
+#define LCD_WF8B_BPBLCD18_MASK 0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT 1
+#define LCD_WF8B_BPBLCD45_MASK 0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT 1
+#define LCD_WF8B_BPBLCD27_MASK 0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT 1
+#define LCD_WF8B_BPBLCD14_MASK 0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT 1
+#define LCD_WF8B_BPBLCD51_MASK 0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT 1
+#define LCD_WF8B_BPBLCD52_MASK 0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT 1
+#define LCD_WF8B_BPBLCD4_MASK 0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT 1
+#define LCD_WF8B_BPBLCD35_MASK 0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT 1
+#define LCD_WF8B_BPBLCD17_MASK 0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT 1
+#define LCD_WF8B_BPBLCD41_MASK 0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT 1
+#define LCD_WF8B_BPBLCD11_MASK 0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT 1
+#define LCD_WF8B_BPBLCD46_MASK 0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT 1
+#define LCD_WF8B_BPBLCD57_MASK 0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT 1
+#define LCD_WF8B_BPBLCD42_MASK 0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT 1
+#define LCD_WF8B_BPBLCD5_MASK 0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT 1
+#define LCD_WF8B_BPBLCD3_MASK 0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT 1
+#define LCD_WF8B_BPBLCD16_MASK 0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT 1
+#define LCD_WF8B_BPBLCD13_MASK 0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT 1
+#define LCD_WF8B_BPCLCD10_MASK 0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT 2
+#define LCD_WF8B_BPCLCD55_MASK 0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT 2
+#define LCD_WF8B_BPCLCD2_MASK 0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT 2
+#define LCD_WF8B_BPCLCD23_MASK 0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT 2
+#define LCD_WF8B_BPCLCD48_MASK 0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT 2
+#define LCD_WF8B_BPCLCD24_MASK 0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT 2
+#define LCD_WF8B_BPCLCD60_MASK 0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT 2
+#define LCD_WF8B_BPCLCD47_MASK 0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT 2
+#define LCD_WF8B_BPCLCD22_MASK 0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT 2
+#define LCD_WF8B_BPCLCD8_MASK 0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT 2
+#define LCD_WF8B_BPCLCD21_MASK 0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT 2
+#define LCD_WF8B_BPCLCD49_MASK 0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT 2
+#define LCD_WF8B_BPCLCD25_MASK 0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT 2
+#define LCD_WF8B_BPCLCD1_MASK 0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT 2
+#define LCD_WF8B_BPCLCD20_MASK 0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT 2
+#define LCD_WF8B_BPCLCD50_MASK 0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT 2
+#define LCD_WF8B_BPCLCD19_MASK 0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT 2
+#define LCD_WF8B_BPCLCD26_MASK 0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT 2
+#define LCD_WF8B_BPCLCD59_MASK 0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT 2
+#define LCD_WF8B_BPCLCD61_MASK 0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT 2
+#define LCD_WF8B_BPCLCD46_MASK 0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT 2
+#define LCD_WF8B_BPCLCD18_MASK 0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT 2
+#define LCD_WF8B_BPCLCD5_MASK 0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT 2
+#define LCD_WF8B_BPCLCD63_MASK 0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT 2
+#define LCD_WF8B_BPCLCD27_MASK 0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT 2
+#define LCD_WF8B_BPCLCD17_MASK 0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT 2
+#define LCD_WF8B_BPCLCD51_MASK 0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT 2
+#define LCD_WF8B_BPCLCD9_MASK 0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT 2
+#define LCD_WF8B_BPCLCD54_MASK 0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT 2
+#define LCD_WF8B_BPCLCD15_MASK 0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT 2
+#define LCD_WF8B_BPCLCD16_MASK 0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT 2
+#define LCD_WF8B_BPCLCD14_MASK 0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT 2
+#define LCD_WF8B_BPCLCD32_MASK 0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT 2
+#define LCD_WF8B_BPCLCD28_MASK 0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT 2
+#define LCD_WF8B_BPCLCD53_MASK 0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT 2
+#define LCD_WF8B_BPCLCD33_MASK 0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT 2
+#define LCD_WF8B_BPCLCD0_MASK 0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT 2
+#define LCD_WF8B_BPCLCD43_MASK 0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT 2
+#define LCD_WF8B_BPCLCD7_MASK 0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT 2
+#define LCD_WF8B_BPCLCD4_MASK 0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT 2
+#define LCD_WF8B_BPCLCD34_MASK 0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT 2
+#define LCD_WF8B_BPCLCD29_MASK 0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT 2
+#define LCD_WF8B_BPCLCD45_MASK 0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT 2
+#define LCD_WF8B_BPCLCD57_MASK 0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT 2
+#define LCD_WF8B_BPCLCD42_MASK 0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT 2
+#define LCD_WF8B_BPCLCD35_MASK 0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT 2
+#define LCD_WF8B_BPCLCD13_MASK 0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT 2
+#define LCD_WF8B_BPCLCD36_MASK 0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT 2
+#define LCD_WF8B_BPCLCD30_MASK 0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT 2
+#define LCD_WF8B_BPCLCD52_MASK 0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT 2
+#define LCD_WF8B_BPCLCD58_MASK 0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT 2
+#define LCD_WF8B_BPCLCD41_MASK 0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT 2
+#define LCD_WF8B_BPCLCD37_MASK 0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT 2
+#define LCD_WF8B_BPCLCD3_MASK 0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT 2
+#define LCD_WF8B_BPCLCD12_MASK 0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT 2
+#define LCD_WF8B_BPCLCD11_MASK 0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT 2
+#define LCD_WF8B_BPCLCD38_MASK 0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT 2
+#define LCD_WF8B_BPCLCD44_MASK 0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT 2
+#define LCD_WF8B_BPCLCD31_MASK 0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT 2
+#define LCD_WF8B_BPCLCD40_MASK 0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT 2
+#define LCD_WF8B_BPCLCD62_MASK 0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT 2
+#define LCD_WF8B_BPCLCD56_MASK 0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT 2
+#define LCD_WF8B_BPCLCD39_MASK 0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT 2
+#define LCD_WF8B_BPCLCD6_MASK 0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT 2
+#define LCD_WF8B_BPDLCD47_MASK 0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT 3
+#define LCD_WF8B_BPDLCD23_MASK 0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT 3
+#define LCD_WF8B_BPDLCD48_MASK 0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT 3
+#define LCD_WF8B_BPDLCD24_MASK 0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT 3
+#define LCD_WF8B_BPDLCD15_MASK 0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT 3
+#define LCD_WF8B_BPDLCD22_MASK 0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT 3
+#define LCD_WF8B_BPDLCD60_MASK 0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT 3
+#define LCD_WF8B_BPDLCD10_MASK 0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT 3
+#define LCD_WF8B_BPDLCD21_MASK 0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT 3
+#define LCD_WF8B_BPDLCD49_MASK 0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT 3
+#define LCD_WF8B_BPDLCD1_MASK 0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT 3
+#define LCD_WF8B_BPDLCD25_MASK 0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT 3
+#define LCD_WF8B_BPDLCD20_MASK 0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT 3
+#define LCD_WF8B_BPDLCD2_MASK 0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT 3
+#define LCD_WF8B_BPDLCD55_MASK 0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT 3
+#define LCD_WF8B_BPDLCD59_MASK 0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT 3
+#define LCD_WF8B_BPDLCD5_MASK 0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT 3
+#define LCD_WF8B_BPDLCD19_MASK 0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT 3
+#define LCD_WF8B_BPDLCD6_MASK 0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT 3
+#define LCD_WF8B_BPDLCD26_MASK 0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT 3
+#define LCD_WF8B_BPDLCD0_MASK 0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT 3
+#define LCD_WF8B_BPDLCD50_MASK 0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT 3
+#define LCD_WF8B_BPDLCD46_MASK 0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT 3
+#define LCD_WF8B_BPDLCD18_MASK 0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT 3
+#define LCD_WF8B_BPDLCD61_MASK 0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT 3
+#define LCD_WF8B_BPDLCD9_MASK 0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT 3
+#define LCD_WF8B_BPDLCD17_MASK 0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT 3
+#define LCD_WF8B_BPDLCD27_MASK 0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT 3
+#define LCD_WF8B_BPDLCD53_MASK 0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT 3
+#define LCD_WF8B_BPDLCD51_MASK 0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT 3
+#define LCD_WF8B_BPDLCD54_MASK 0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT 3
+#define LCD_WF8B_BPDLCD13_MASK 0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT 3
+#define LCD_WF8B_BPDLCD16_MASK 0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT 3
+#define LCD_WF8B_BPDLCD32_MASK 0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT 3
+#define LCD_WF8B_BPDLCD14_MASK 0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT 3
+#define LCD_WF8B_BPDLCD28_MASK 0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT 3
+#define LCD_WF8B_BPDLCD43_MASK 0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT 3
+#define LCD_WF8B_BPDLCD4_MASK 0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT 3
+#define LCD_WF8B_BPDLCD45_MASK 0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT 3
+#define LCD_WF8B_BPDLCD8_MASK 0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT 3
+#define LCD_WF8B_BPDLCD62_MASK 0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT 3
+#define LCD_WF8B_BPDLCD33_MASK 0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT 3
+#define LCD_WF8B_BPDLCD34_MASK 0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT 3
+#define LCD_WF8B_BPDLCD29_MASK 0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT 3
+#define LCD_WF8B_BPDLCD58_MASK 0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT 3
+#define LCD_WF8B_BPDLCD57_MASK 0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT 3
+#define LCD_WF8B_BPDLCD42_MASK 0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT 3
+#define LCD_WF8B_BPDLCD35_MASK 0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT 3
+#define LCD_WF8B_BPDLCD52_MASK 0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT 3
+#define LCD_WF8B_BPDLCD7_MASK 0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT 3
+#define LCD_WF8B_BPDLCD36_MASK 0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT 3
+#define LCD_WF8B_BPDLCD30_MASK 0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT 3
+#define LCD_WF8B_BPDLCD41_MASK 0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT 3
+#define LCD_WF8B_BPDLCD37_MASK 0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT 3
+#define LCD_WF8B_BPDLCD44_MASK 0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT 3
+#define LCD_WF8B_BPDLCD63_MASK 0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT 3
+#define LCD_WF8B_BPDLCD38_MASK 0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT 3
+#define LCD_WF8B_BPDLCD56_MASK 0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT 3
+#define LCD_WF8B_BPDLCD40_MASK 0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT 3
+#define LCD_WF8B_BPDLCD31_MASK 0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT 3
+#define LCD_WF8B_BPDLCD12_MASK 0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT 3
+#define LCD_WF8B_BPDLCD39_MASK 0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT 3
+#define LCD_WF8B_BPDLCD3_MASK 0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT 3
+#define LCD_WF8B_BPDLCD11_MASK 0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT 3
+#define LCD_WF8B_BPELCD12_MASK 0x10u
+#define LCD_WF8B_BPELCD12_SHIFT 4
+#define LCD_WF8B_BPELCD39_MASK 0x10u
+#define LCD_WF8B_BPELCD39_SHIFT 4
+#define LCD_WF8B_BPELCD3_MASK 0x10u
+#define LCD_WF8B_BPELCD3_SHIFT 4
+#define LCD_WF8B_BPELCD38_MASK 0x10u
+#define LCD_WF8B_BPELCD38_SHIFT 4
+#define LCD_WF8B_BPELCD40_MASK 0x10u
+#define LCD_WF8B_BPELCD40_SHIFT 4
+#define LCD_WF8B_BPELCD37_MASK 0x10u
+#define LCD_WF8B_BPELCD37_SHIFT 4
+#define LCD_WF8B_BPELCD41_MASK 0x10u
+#define LCD_WF8B_BPELCD41_SHIFT 4
+#define LCD_WF8B_BPELCD36_MASK 0x10u
+#define LCD_WF8B_BPELCD36_SHIFT 4
+#define LCD_WF8B_BPELCD8_MASK 0x10u
+#define LCD_WF8B_BPELCD8_SHIFT 4
+#define LCD_WF8B_BPELCD35_MASK 0x10u
+#define LCD_WF8B_BPELCD35_SHIFT 4
+#define LCD_WF8B_BPELCD42_MASK 0x10u
+#define LCD_WF8B_BPELCD42_SHIFT 4
+#define LCD_WF8B_BPELCD34_MASK 0x10u
+#define LCD_WF8B_BPELCD34_SHIFT 4
+#define LCD_WF8B_BPELCD33_MASK 0x10u
+#define LCD_WF8B_BPELCD33_SHIFT 4
+#define LCD_WF8B_BPELCD11_MASK 0x10u
+#define LCD_WF8B_BPELCD11_SHIFT 4
+#define LCD_WF8B_BPELCD43_MASK 0x10u
+#define LCD_WF8B_BPELCD43_SHIFT 4
+#define LCD_WF8B_BPELCD32_MASK 0x10u
+#define LCD_WF8B_BPELCD32_SHIFT 4
+#define LCD_WF8B_BPELCD31_MASK 0x10u
+#define LCD_WF8B_BPELCD31_SHIFT 4
+#define LCD_WF8B_BPELCD44_MASK 0x10u
+#define LCD_WF8B_BPELCD44_SHIFT 4
+#define LCD_WF8B_BPELCD30_MASK 0x10u
+#define LCD_WF8B_BPELCD30_SHIFT 4
+#define LCD_WF8B_BPELCD29_MASK 0x10u
+#define LCD_WF8B_BPELCD29_SHIFT 4
+#define LCD_WF8B_BPELCD7_MASK 0x10u
+#define LCD_WF8B_BPELCD7_SHIFT 4
+#define LCD_WF8B_BPELCD45_MASK 0x10u
+#define LCD_WF8B_BPELCD45_SHIFT 4
+#define LCD_WF8B_BPELCD28_MASK 0x10u
+#define LCD_WF8B_BPELCD28_SHIFT 4
+#define LCD_WF8B_BPELCD2_MASK 0x10u
+#define LCD_WF8B_BPELCD2_SHIFT 4
+#define LCD_WF8B_BPELCD27_MASK 0x10u
+#define LCD_WF8B_BPELCD27_SHIFT 4
+#define LCD_WF8B_BPELCD46_MASK 0x10u
+#define LCD_WF8B_BPELCD46_SHIFT 4
+#define LCD_WF8B_BPELCD26_MASK 0x10u
+#define LCD_WF8B_BPELCD26_SHIFT 4
+#define LCD_WF8B_BPELCD10_MASK 0x10u
+#define LCD_WF8B_BPELCD10_SHIFT 4
+#define LCD_WF8B_BPELCD13_MASK 0x10u
+#define LCD_WF8B_BPELCD13_SHIFT 4
+#define LCD_WF8B_BPELCD25_MASK 0x10u
+#define LCD_WF8B_BPELCD25_SHIFT 4
+#define LCD_WF8B_BPELCD5_MASK 0x10u
+#define LCD_WF8B_BPELCD5_SHIFT 4
+#define LCD_WF8B_BPELCD24_MASK 0x10u
+#define LCD_WF8B_BPELCD24_SHIFT 4
+#define LCD_WF8B_BPELCD47_MASK 0x10u
+#define LCD_WF8B_BPELCD47_SHIFT 4
+#define LCD_WF8B_BPELCD23_MASK 0x10u
+#define LCD_WF8B_BPELCD23_SHIFT 4
+#define LCD_WF8B_BPELCD22_MASK 0x10u
+#define LCD_WF8B_BPELCD22_SHIFT 4
+#define LCD_WF8B_BPELCD48_MASK 0x10u
+#define LCD_WF8B_BPELCD48_SHIFT 4
+#define LCD_WF8B_BPELCD21_MASK 0x10u
+#define LCD_WF8B_BPELCD21_SHIFT 4
+#define LCD_WF8B_BPELCD49_MASK 0x10u
+#define LCD_WF8B_BPELCD49_SHIFT 4
+#define LCD_WF8B_BPELCD20_MASK 0x10u
+#define LCD_WF8B_BPELCD20_SHIFT 4
+#define LCD_WF8B_BPELCD19_MASK 0x10u
+#define LCD_WF8B_BPELCD19_SHIFT 4
+#define LCD_WF8B_BPELCD9_MASK 0x10u
+#define LCD_WF8B_BPELCD9_SHIFT 4
+#define LCD_WF8B_BPELCD50_MASK 0x10u
+#define LCD_WF8B_BPELCD50_SHIFT 4
+#define LCD_WF8B_BPELCD18_MASK 0x10u
+#define LCD_WF8B_BPELCD18_SHIFT 4
+#define LCD_WF8B_BPELCD6_MASK 0x10u
+#define LCD_WF8B_BPELCD6_SHIFT 4
+#define LCD_WF8B_BPELCD17_MASK 0x10u
+#define LCD_WF8B_BPELCD17_SHIFT 4
+#define LCD_WF8B_BPELCD51_MASK 0x10u
+#define LCD_WF8B_BPELCD51_SHIFT 4
+#define LCD_WF8B_BPELCD16_MASK 0x10u
+#define LCD_WF8B_BPELCD16_SHIFT 4
+#define LCD_WF8B_BPELCD56_MASK 0x10u
+#define LCD_WF8B_BPELCD56_SHIFT 4
+#define LCD_WF8B_BPELCD57_MASK 0x10u
+#define LCD_WF8B_BPELCD57_SHIFT 4
+#define LCD_WF8B_BPELCD52_MASK 0x10u
+#define LCD_WF8B_BPELCD52_SHIFT 4
+#define LCD_WF8B_BPELCD1_MASK 0x10u
+#define LCD_WF8B_BPELCD1_SHIFT 4
+#define LCD_WF8B_BPELCD58_MASK 0x10u
+#define LCD_WF8B_BPELCD58_SHIFT 4
+#define LCD_WF8B_BPELCD59_MASK 0x10u
+#define LCD_WF8B_BPELCD59_SHIFT 4
+#define LCD_WF8B_BPELCD53_MASK 0x10u
+#define LCD_WF8B_BPELCD53_SHIFT 4
+#define LCD_WF8B_BPELCD14_MASK 0x10u
+#define LCD_WF8B_BPELCD14_SHIFT 4
+#define LCD_WF8B_BPELCD0_MASK 0x10u
+#define LCD_WF8B_BPELCD0_SHIFT 4
+#define LCD_WF8B_BPELCD60_MASK 0x10u
+#define LCD_WF8B_BPELCD60_SHIFT 4
+#define LCD_WF8B_BPELCD15_MASK 0x10u
+#define LCD_WF8B_BPELCD15_SHIFT 4
+#define LCD_WF8B_BPELCD61_MASK 0x10u
+#define LCD_WF8B_BPELCD61_SHIFT 4
+#define LCD_WF8B_BPELCD54_MASK 0x10u
+#define LCD_WF8B_BPELCD54_SHIFT 4
+#define LCD_WF8B_BPELCD62_MASK 0x10u
+#define LCD_WF8B_BPELCD62_SHIFT 4
+#define LCD_WF8B_BPELCD63_MASK 0x10u
+#define LCD_WF8B_BPELCD63_SHIFT 4
+#define LCD_WF8B_BPELCD55_MASK 0x10u
+#define LCD_WF8B_BPELCD55_SHIFT 4
+#define LCD_WF8B_BPELCD4_MASK 0x10u
+#define LCD_WF8B_BPELCD4_SHIFT 4
+#define LCD_WF8B_BPFLCD13_MASK 0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT 5
+#define LCD_WF8B_BPFLCD39_MASK 0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT 5
+#define LCD_WF8B_BPFLCD55_MASK 0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT 5
+#define LCD_WF8B_BPFLCD47_MASK 0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT 5
+#define LCD_WF8B_BPFLCD63_MASK 0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT 5
+#define LCD_WF8B_BPFLCD43_MASK 0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT 5
+#define LCD_WF8B_BPFLCD5_MASK 0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT 5
+#define LCD_WF8B_BPFLCD62_MASK 0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT 5
+#define LCD_WF8B_BPFLCD14_MASK 0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT 5
+#define LCD_WF8B_BPFLCD24_MASK 0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT 5
+#define LCD_WF8B_BPFLCD54_MASK 0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT 5
+#define LCD_WF8B_BPFLCD15_MASK 0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT 5
+#define LCD_WF8B_BPFLCD32_MASK 0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT 5
+#define LCD_WF8B_BPFLCD61_MASK 0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT 5
+#define LCD_WF8B_BPFLCD25_MASK 0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT 5
+#define LCD_WF8B_BPFLCD60_MASK 0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT 5
+#define LCD_WF8B_BPFLCD41_MASK 0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT 5
+#define LCD_WF8B_BPFLCD33_MASK 0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT 5
+#define LCD_WF8B_BPFLCD53_MASK 0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT 5
+#define LCD_WF8B_BPFLCD59_MASK 0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT 5
+#define LCD_WF8B_BPFLCD0_MASK 0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT 5
+#define LCD_WF8B_BPFLCD46_MASK 0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT 5
+#define LCD_WF8B_BPFLCD58_MASK 0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT 5
+#define LCD_WF8B_BPFLCD26_MASK 0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT 5
+#define LCD_WF8B_BPFLCD36_MASK 0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT 5
+#define LCD_WF8B_BPFLCD10_MASK 0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT 5
+#define LCD_WF8B_BPFLCD52_MASK 0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT 5
+#define LCD_WF8B_BPFLCD57_MASK 0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT 5
+#define LCD_WF8B_BPFLCD27_MASK 0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT 5
+#define LCD_WF8B_BPFLCD11_MASK 0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT 5
+#define LCD_WF8B_BPFLCD56_MASK 0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT 5
+#define LCD_WF8B_BPFLCD1_MASK 0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT 5
+#define LCD_WF8B_BPFLCD8_MASK 0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT 5
+#define LCD_WF8B_BPFLCD40_MASK 0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT 5
+#define LCD_WF8B_BPFLCD51_MASK 0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT 5
+#define LCD_WF8B_BPFLCD16_MASK 0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT 5
+#define LCD_WF8B_BPFLCD45_MASK 0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT 5
+#define LCD_WF8B_BPFLCD6_MASK 0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT 5
+#define LCD_WF8B_BPFLCD17_MASK 0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT 5
+#define LCD_WF8B_BPFLCD28_MASK 0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT 5
+#define LCD_WF8B_BPFLCD42_MASK 0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT 5
+#define LCD_WF8B_BPFLCD29_MASK 0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT 5
+#define LCD_WF8B_BPFLCD50_MASK 0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT 5
+#define LCD_WF8B_BPFLCD18_MASK 0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT 5
+#define LCD_WF8B_BPFLCD34_MASK 0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT 5
+#define LCD_WF8B_BPFLCD19_MASK 0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT 5
+#define LCD_WF8B_BPFLCD2_MASK 0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT 5
+#define LCD_WF8B_BPFLCD9_MASK 0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT 5
+#define LCD_WF8B_BPFLCD3_MASK 0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT 5
+#define LCD_WF8B_BPFLCD37_MASK 0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT 5
+#define LCD_WF8B_BPFLCD49_MASK 0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT 5
+#define LCD_WF8B_BPFLCD20_MASK 0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT 5
+#define LCD_WF8B_BPFLCD44_MASK 0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT 5
+#define LCD_WF8B_BPFLCD30_MASK 0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT 5
+#define LCD_WF8B_BPFLCD21_MASK 0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT 5
+#define LCD_WF8B_BPFLCD35_MASK 0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT 5
+#define LCD_WF8B_BPFLCD4_MASK 0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT 5
+#define LCD_WF8B_BPFLCD31_MASK 0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT 5
+#define LCD_WF8B_BPFLCD48_MASK 0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT 5
+#define LCD_WF8B_BPFLCD7_MASK 0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT 5
+#define LCD_WF8B_BPFLCD22_MASK 0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT 5
+#define LCD_WF8B_BPFLCD38_MASK 0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT 5
+#define LCD_WF8B_BPFLCD12_MASK 0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT 5
+#define LCD_WF8B_BPFLCD23_MASK 0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT 5
+#define LCD_WF8B_BPGLCD14_MASK 0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT 6
+#define LCD_WF8B_BPGLCD55_MASK 0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT 6
+#define LCD_WF8B_BPGLCD63_MASK 0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT 6
+#define LCD_WF8B_BPGLCD15_MASK 0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT 6
+#define LCD_WF8B_BPGLCD62_MASK 0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT 6
+#define LCD_WF8B_BPGLCD54_MASK 0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT 6
+#define LCD_WF8B_BPGLCD61_MASK 0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT 6
+#define LCD_WF8B_BPGLCD60_MASK 0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT 6
+#define LCD_WF8B_BPGLCD59_MASK 0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT 6
+#define LCD_WF8B_BPGLCD53_MASK 0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT 6
+#define LCD_WF8B_BPGLCD58_MASK 0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT 6
+#define LCD_WF8B_BPGLCD0_MASK 0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT 6
+#define LCD_WF8B_BPGLCD57_MASK 0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT 6
+#define LCD_WF8B_BPGLCD52_MASK 0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT 6
+#define LCD_WF8B_BPGLCD7_MASK 0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT 6
+#define LCD_WF8B_BPGLCD56_MASK 0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT 6
+#define LCD_WF8B_BPGLCD6_MASK 0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT 6
+#define LCD_WF8B_BPGLCD51_MASK 0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT 6
+#define LCD_WF8B_BPGLCD16_MASK 0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT 6
+#define LCD_WF8B_BPGLCD1_MASK 0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT 6
+#define LCD_WF8B_BPGLCD17_MASK 0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT 6
+#define LCD_WF8B_BPGLCD50_MASK 0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT 6
+#define LCD_WF8B_BPGLCD18_MASK 0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT 6
+#define LCD_WF8B_BPGLCD19_MASK 0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT 6
+#define LCD_WF8B_BPGLCD8_MASK 0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT 6
+#define LCD_WF8B_BPGLCD49_MASK 0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT 6
+#define LCD_WF8B_BPGLCD20_MASK 0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT 6
+#define LCD_WF8B_BPGLCD9_MASK 0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT 6
+#define LCD_WF8B_BPGLCD21_MASK 0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT 6
+#define LCD_WF8B_BPGLCD13_MASK 0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT 6
+#define LCD_WF8B_BPGLCD48_MASK 0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT 6
+#define LCD_WF8B_BPGLCD22_MASK 0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT 6
+#define LCD_WF8B_BPGLCD5_MASK 0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT 6
+#define LCD_WF8B_BPGLCD47_MASK 0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT 6
+#define LCD_WF8B_BPGLCD23_MASK 0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT 6
+#define LCD_WF8B_BPGLCD24_MASK 0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT 6
+#define LCD_WF8B_BPGLCD25_MASK 0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT 6
+#define LCD_WF8B_BPGLCD46_MASK 0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT 6
+#define LCD_WF8B_BPGLCD26_MASK 0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT 6
+#define LCD_WF8B_BPGLCD27_MASK 0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT 6
+#define LCD_WF8B_BPGLCD10_MASK 0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT 6
+#define LCD_WF8B_BPGLCD45_MASK 0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT 6
+#define LCD_WF8B_BPGLCD28_MASK 0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT 6
+#define LCD_WF8B_BPGLCD29_MASK 0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT 6
+#define LCD_WF8B_BPGLCD4_MASK 0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT 6
+#define LCD_WF8B_BPGLCD44_MASK 0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT 6
+#define LCD_WF8B_BPGLCD30_MASK 0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT 6
+#define LCD_WF8B_BPGLCD2_MASK 0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT 6
+#define LCD_WF8B_BPGLCD31_MASK 0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT 6
+#define LCD_WF8B_BPGLCD43_MASK 0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT 6
+#define LCD_WF8B_BPGLCD32_MASK 0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT 6
+#define LCD_WF8B_BPGLCD33_MASK 0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT 6
+#define LCD_WF8B_BPGLCD42_MASK 0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT 6
+#define LCD_WF8B_BPGLCD34_MASK 0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT 6
+#define LCD_WF8B_BPGLCD11_MASK 0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT 6
+#define LCD_WF8B_BPGLCD35_MASK 0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT 6
+#define LCD_WF8B_BPGLCD12_MASK 0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT 6
+#define LCD_WF8B_BPGLCD41_MASK 0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT 6
+#define LCD_WF8B_BPGLCD36_MASK 0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT 6
+#define LCD_WF8B_BPGLCD3_MASK 0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT 6
+#define LCD_WF8B_BPGLCD37_MASK 0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT 6
+#define LCD_WF8B_BPGLCD40_MASK 0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT 6
+#define LCD_WF8B_BPGLCD38_MASK 0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT 6
+#define LCD_WF8B_BPGLCD39_MASK 0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT 6
+#define LCD_WF8B_BPHLCD63_MASK 0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT 7
+#define LCD_WF8B_BPHLCD62_MASK 0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT 7
+#define LCD_WF8B_BPHLCD61_MASK 0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT 7
+#define LCD_WF8B_BPHLCD60_MASK 0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT 7
+#define LCD_WF8B_BPHLCD59_MASK 0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT 7
+#define LCD_WF8B_BPHLCD58_MASK 0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT 7
+#define LCD_WF8B_BPHLCD57_MASK 0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT 7
+#define LCD_WF8B_BPHLCD0_MASK 0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT 7
+#define LCD_WF8B_BPHLCD56_MASK 0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT 7
+#define LCD_WF8B_BPHLCD55_MASK 0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT 7
+#define LCD_WF8B_BPHLCD54_MASK 0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT 7
+#define LCD_WF8B_BPHLCD53_MASK 0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT 7
+#define LCD_WF8B_BPHLCD52_MASK 0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT 7
+#define LCD_WF8B_BPHLCD51_MASK 0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT 7
+#define LCD_WF8B_BPHLCD50_MASK 0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT 7
+#define LCD_WF8B_BPHLCD1_MASK 0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT 7
+#define LCD_WF8B_BPHLCD49_MASK 0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT 7
+#define LCD_WF8B_BPHLCD48_MASK 0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT 7
+#define LCD_WF8B_BPHLCD47_MASK 0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT 7
+#define LCD_WF8B_BPHLCD46_MASK 0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT 7
+#define LCD_WF8B_BPHLCD45_MASK 0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT 7
+#define LCD_WF8B_BPHLCD44_MASK 0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT 7
+#define LCD_WF8B_BPHLCD43_MASK 0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT 7
+#define LCD_WF8B_BPHLCD2_MASK 0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT 7
+#define LCD_WF8B_BPHLCD42_MASK 0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT 7
+#define LCD_WF8B_BPHLCD41_MASK 0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT 7
+#define LCD_WF8B_BPHLCD40_MASK 0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT 7
+#define LCD_WF8B_BPHLCD39_MASK 0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT 7
+#define LCD_WF8B_BPHLCD38_MASK 0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT 7
+#define LCD_WF8B_BPHLCD37_MASK 0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT 7
+#define LCD_WF8B_BPHLCD36_MASK 0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT 7
+#define LCD_WF8B_BPHLCD3_MASK 0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT 7
+#define LCD_WF8B_BPHLCD35_MASK 0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT 7
+#define LCD_WF8B_BPHLCD34_MASK 0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT 7
+#define LCD_WF8B_BPHLCD33_MASK 0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT 7
+#define LCD_WF8B_BPHLCD32_MASK 0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT 7
+#define LCD_WF8B_BPHLCD31_MASK 0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT 7
+#define LCD_WF8B_BPHLCD30_MASK 0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT 7
+#define LCD_WF8B_BPHLCD29_MASK 0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT 7
+#define LCD_WF8B_BPHLCD4_MASK 0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT 7
+#define LCD_WF8B_BPHLCD28_MASK 0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT 7
+#define LCD_WF8B_BPHLCD27_MASK 0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT 7
+#define LCD_WF8B_BPHLCD26_MASK 0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT 7
+#define LCD_WF8B_BPHLCD25_MASK 0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT 7
+#define LCD_WF8B_BPHLCD24_MASK 0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT 7
+#define LCD_WF8B_BPHLCD23_MASK 0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT 7
+#define LCD_WF8B_BPHLCD22_MASK 0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT 7
+#define LCD_WF8B_BPHLCD5_MASK 0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT 7
+#define LCD_WF8B_BPHLCD21_MASK 0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT 7
+#define LCD_WF8B_BPHLCD20_MASK 0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT 7
+#define LCD_WF8B_BPHLCD19_MASK 0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT 7
+#define LCD_WF8B_BPHLCD18_MASK 0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT 7
+#define LCD_WF8B_BPHLCD17_MASK 0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT 7
+#define LCD_WF8B_BPHLCD16_MASK 0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT 7
+#define LCD_WF8B_BPHLCD15_MASK 0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT 7
+#define LCD_WF8B_BPHLCD6_MASK 0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT 7
+#define LCD_WF8B_BPHLCD14_MASK 0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT 7
+#define LCD_WF8B_BPHLCD13_MASK 0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT 7
+#define LCD_WF8B_BPHLCD12_MASK 0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT 7
+#define LCD_WF8B_BPHLCD11_MASK 0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT 7
+#define LCD_WF8B_BPHLCD10_MASK 0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT 7
+#define LCD_WF8B_BPHLCD9_MASK 0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT 7
+#define LCD_WF8B_BPHLCD8_MASK 0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT 7
+#define LCD_WF8B_BPHLCD7_MASK 0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+#define LCD_BASE_PTR (LCD)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_LCD_IRQS { LCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
+ * @{
+ */
+
+
+/* LCD - Register instance definitions */
+/* LCD */
+#define LCD_GCR LCD_GCR_REG(LCD)
+#define LCD_AR LCD_AR_REG(LCD)
+#define LCD_FDCR LCD_FDCR_REG(LCD)
+#define LCD_FDSR LCD_FDSR_REG(LCD)
+#define LCD_PENL LCD_PEN_REG(LCD,0)
+#define LCD_PENH LCD_PEN_REG(LCD,1)
+#define LCD_BPENL LCD_BPEN_REG(LCD,0)
+#define LCD_BPENH LCD_BPEN_REG(LCD,1)
+#define LCD_WF0 LCD_WF8B_REG(LCD,0)
+#define LCD_WF3TO0 LCD_WF_REG(LCD,0)
+#define LCD_WF1 LCD_WF8B_REG(LCD,1)
+#define LCD_WF2 LCD_WF8B_REG(LCD,2)
+#define LCD_WF3 LCD_WF8B_REG(LCD,3)
+#define LCD_WF4 LCD_WF8B_REG(LCD,4)
+#define LCD_WF7TO4 LCD_WF_REG(LCD,1)
+#define LCD_WF5 LCD_WF8B_REG(LCD,5)
+#define LCD_WF6 LCD_WF8B_REG(LCD,6)
+#define LCD_WF7 LCD_WF8B_REG(LCD,7)
+#define LCD_WF11TO8 LCD_WF_REG(LCD,2)
+#define LCD_WF8 LCD_WF8B_REG(LCD,8)
+#define LCD_WF9 LCD_WF8B_REG(LCD,9)
+#define LCD_WF10 LCD_WF8B_REG(LCD,10)
+#define LCD_WF11 LCD_WF8B_REG(LCD,11)
+#define LCD_WF12 LCD_WF8B_REG(LCD,12)
+#define LCD_WF15TO12 LCD_WF_REG(LCD,3)
+#define LCD_WF13 LCD_WF8B_REG(LCD,13)
+#define LCD_WF14 LCD_WF8B_REG(LCD,14)
+#define LCD_WF15 LCD_WF8B_REG(LCD,15)
+#define LCD_WF16 LCD_WF8B_REG(LCD,16)
+#define LCD_WF19TO16 LCD_WF_REG(LCD,4)
+#define LCD_WF17 LCD_WF8B_REG(LCD,17)
+#define LCD_WF18 LCD_WF8B_REG(LCD,18)
+#define LCD_WF19 LCD_WF8B_REG(LCD,19)
+#define LCD_WF20 LCD_WF8B_REG(LCD,20)
+#define LCD_WF23TO20 LCD_WF_REG(LCD,5)
+#define LCD_WF21 LCD_WF8B_REG(LCD,21)
+#define LCD_WF22 LCD_WF8B_REG(LCD,22)
+#define LCD_WF23 LCD_WF8B_REG(LCD,23)
+#define LCD_WF24 LCD_WF8B_REG(LCD,24)
+#define LCD_WF27TO24 LCD_WF_REG(LCD,6)
+#define LCD_WF25 LCD_WF8B_REG(LCD,25)
+#define LCD_WF26 LCD_WF8B_REG(LCD,26)
+#define LCD_WF27 LCD_WF8B_REG(LCD,27)
+#define LCD_WF28 LCD_WF8B_REG(LCD,28)
+#define LCD_WF31TO28 LCD_WF_REG(LCD,7)
+#define LCD_WF29 LCD_WF8B_REG(LCD,29)
+#define LCD_WF30 LCD_WF8B_REG(LCD,30)
+#define LCD_WF31 LCD_WF8B_REG(LCD,31)
+#define LCD_WF32 LCD_WF8B_REG(LCD,32)
+#define LCD_WF35TO32 LCD_WF_REG(LCD,8)
+#define LCD_WF33 LCD_WF8B_REG(LCD,33)
+#define LCD_WF34 LCD_WF8B_REG(LCD,34)
+#define LCD_WF35 LCD_WF8B_REG(LCD,35)
+#define LCD_WF36 LCD_WF8B_REG(LCD,36)
+#define LCD_WF39TO36 LCD_WF_REG(LCD,9)
+#define LCD_WF37 LCD_WF8B_REG(LCD,37)
+#define LCD_WF38 LCD_WF8B_REG(LCD,38)
+#define LCD_WF39 LCD_WF8B_REG(LCD,39)
+#define LCD_WF40 LCD_WF8B_REG(LCD,40)
+#define LCD_WF43TO40 LCD_WF_REG(LCD,10)
+#define LCD_WF41 LCD_WF8B_REG(LCD,41)
+#define LCD_WF42 LCD_WF8B_REG(LCD,42)
+#define LCD_WF43 LCD_WF8B_REG(LCD,43)
+#define LCD_WF44 LCD_WF8B_REG(LCD,44)
+#define LCD_WF47TO44 LCD_WF_REG(LCD,11)
+#define LCD_WF45 LCD_WF8B_REG(LCD,45)
+#define LCD_WF46 LCD_WF8B_REG(LCD,46)
+#define LCD_WF47 LCD_WF8B_REG(LCD,47)
+#define LCD_WF48 LCD_WF8B_REG(LCD,48)
+#define LCD_WF51TO48 LCD_WF_REG(LCD,12)
+#define LCD_WF49 LCD_WF8B_REG(LCD,49)
+#define LCD_WF50 LCD_WF8B_REG(LCD,50)
+#define LCD_WF51 LCD_WF8B_REG(LCD,51)
+#define LCD_WF52 LCD_WF8B_REG(LCD,52)
+#define LCD_WF55TO52 LCD_WF_REG(LCD,13)
+#define LCD_WF53 LCD_WF8B_REG(LCD,53)
+#define LCD_WF54 LCD_WF8B_REG(LCD,54)
+#define LCD_WF55 LCD_WF8B_REG(LCD,55)
+#define LCD_WF56 LCD_WF8B_REG(LCD,56)
+#define LCD_WF59TO56 LCD_WF_REG(LCD,14)
+#define LCD_WF57 LCD_WF8B_REG(LCD,57)
+#define LCD_WF58 LCD_WF8B_REG(LCD,58)
+#define LCD_WF59 LCD_WF8B_REG(LCD,59)
+#define LCD_WF60 LCD_WF8B_REG(LCD,60)
+#define LCD_WF63TO60 LCD_WF_REG(LCD,15)
+#define LCD_WF61 LCD_WF8B_REG(LCD,61)
+#define LCD_WF62 LCD_WF8B_REG(LCD,62)
+#define LCD_WF63 LCD_WF8B_REG(LCD,63)
+
+/* LCD - Register array accessors */
+#define LCD_PEN(index) LCD_PEN_REG(LCD,index)
+#define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
+#define LCD_WF(index2) LCD_WF_REG(LCD,index2)
+#define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register accessors */
+#define LPUART_BAUD_REG(base) ((base)->BAUD)
+#define LPUART_STAT_REG(base) ((base)->STAT)
+#define LPUART_CTRL_REG(base) ((base)->CTRL)
+#define LPUART_DATA_REG(base) ((base)->DATA)
+#define LPUART_MATCH_REG(base) ((base)->MATCH)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK 0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT 0
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK 0x2000u
+#define LPUART_BAUD_SBNS_SHIFT 13
+#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT 14
+#define LPUART_BAUD_LBKDIE_MASK 0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT 15
+#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT 16
+#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT 17
+#define LPUART_BAUD_MATCFG_MASK 0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT 18
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK 0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT 21
+#define LPUART_BAUD_TDMAE_MASK 0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT 23
+#define LPUART_BAUD_OSR_MASK 0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT 24
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK 0x20000000u
+#define LPUART_BAUD_M10_SHIFT 29
+#define LPUART_BAUD_MAEN2_MASK 0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT 30
+#define LPUART_BAUD_MAEN1_MASK 0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT 31
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK 0x4000u
+#define LPUART_STAT_MA2F_SHIFT 14
+#define LPUART_STAT_MA1F_MASK 0x8000u
+#define LPUART_STAT_MA1F_SHIFT 15
+#define LPUART_STAT_PF_MASK 0x10000u
+#define LPUART_STAT_PF_SHIFT 16
+#define LPUART_STAT_FE_MASK 0x20000u
+#define LPUART_STAT_FE_SHIFT 17
+#define LPUART_STAT_NF_MASK 0x40000u
+#define LPUART_STAT_NF_SHIFT 18
+#define LPUART_STAT_OR_MASK 0x80000u
+#define LPUART_STAT_OR_SHIFT 19
+#define LPUART_STAT_IDLE_MASK 0x100000u
+#define LPUART_STAT_IDLE_SHIFT 20
+#define LPUART_STAT_RDRF_MASK 0x200000u
+#define LPUART_STAT_RDRF_SHIFT 21
+#define LPUART_STAT_TC_MASK 0x400000u
+#define LPUART_STAT_TC_SHIFT 22
+#define LPUART_STAT_TDRE_MASK 0x800000u
+#define LPUART_STAT_TDRE_SHIFT 23
+#define LPUART_STAT_RAF_MASK 0x1000000u
+#define LPUART_STAT_RAF_SHIFT 24
+#define LPUART_STAT_LBKDE_MASK 0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT 25
+#define LPUART_STAT_BRK13_MASK 0x4000000u
+#define LPUART_STAT_BRK13_SHIFT 26
+#define LPUART_STAT_RWUID_MASK 0x8000000u
+#define LPUART_STAT_RWUID_SHIFT 27
+#define LPUART_STAT_RXINV_MASK 0x10000000u
+#define LPUART_STAT_RXINV_SHIFT 28
+#define LPUART_STAT_MSBF_MASK 0x20000000u
+#define LPUART_STAT_MSBF_SHIFT 29
+#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
+#define LPUART_STAT_RXEDGIF_SHIFT 30
+#define LPUART_STAT_LBKDIF_MASK 0x80000000u
+#define LPUART_STAT_LBKDIF_SHIFT 31
+/* CTRL Bit Fields */
+#define LPUART_CTRL_PT_MASK 0x1u
+#define LPUART_CTRL_PT_SHIFT 0
+#define LPUART_CTRL_PE_MASK 0x2u
+#define LPUART_CTRL_PE_SHIFT 1
+#define LPUART_CTRL_ILT_MASK 0x4u
+#define LPUART_CTRL_ILT_SHIFT 2
+#define LPUART_CTRL_WAKE_MASK 0x8u
+#define LPUART_CTRL_WAKE_SHIFT 3
+#define LPUART_CTRL_M_MASK 0x10u
+#define LPUART_CTRL_M_SHIFT 4
+#define LPUART_CTRL_RSRC_MASK 0x20u
+#define LPUART_CTRL_RSRC_SHIFT 5
+#define LPUART_CTRL_DOZEEN_MASK 0x40u
+#define LPUART_CTRL_DOZEEN_SHIFT 6
+#define LPUART_CTRL_LOOPS_MASK 0x80u
+#define LPUART_CTRL_LOOPS_SHIFT 7
+#define LPUART_CTRL_IDLECFG_MASK 0x700u
+#define LPUART_CTRL_IDLECFG_SHIFT 8
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK 0x4000u
+#define LPUART_CTRL_MA2IE_SHIFT 14
+#define LPUART_CTRL_MA1IE_MASK 0x8000u
+#define LPUART_CTRL_MA1IE_SHIFT 15
+#define LPUART_CTRL_SBK_MASK 0x10000u
+#define LPUART_CTRL_SBK_SHIFT 16
+#define LPUART_CTRL_RWU_MASK 0x20000u
+#define LPUART_CTRL_RWU_SHIFT 17
+#define LPUART_CTRL_RE_MASK 0x40000u
+#define LPUART_CTRL_RE_SHIFT 18
+#define LPUART_CTRL_TE_MASK 0x80000u
+#define LPUART_CTRL_TE_SHIFT 19
+#define LPUART_CTRL_ILIE_MASK 0x100000u
+#define LPUART_CTRL_ILIE_SHIFT 20
+#define LPUART_CTRL_RIE_MASK 0x200000u
+#define LPUART_CTRL_RIE_SHIFT 21
+#define LPUART_CTRL_TCIE_MASK 0x400000u
+#define LPUART_CTRL_TCIE_SHIFT 22
+#define LPUART_CTRL_TIE_MASK 0x800000u
+#define LPUART_CTRL_TIE_SHIFT 23
+#define LPUART_CTRL_PEIE_MASK 0x1000000u
+#define LPUART_CTRL_PEIE_SHIFT 24
+#define LPUART_CTRL_FEIE_MASK 0x2000000u
+#define LPUART_CTRL_FEIE_SHIFT 25
+#define LPUART_CTRL_NEIE_MASK 0x4000000u
+#define LPUART_CTRL_NEIE_SHIFT 26
+#define LPUART_CTRL_ORIE_MASK 0x8000000u
+#define LPUART_CTRL_ORIE_SHIFT 27
+#define LPUART_CTRL_TXINV_MASK 0x10000000u
+#define LPUART_CTRL_TXINV_SHIFT 28
+#define LPUART_CTRL_TXDIR_MASK 0x20000000u
+#define LPUART_CTRL_TXDIR_SHIFT 29
+#define LPUART_CTRL_R9T8_MASK 0x40000000u
+#define LPUART_CTRL_R9T8_SHIFT 30
+#define LPUART_CTRL_R8T9_MASK 0x80000000u
+#define LPUART_CTRL_R8T9_SHIFT 31
+/* DATA Bit Fields */
+#define LPUART_DATA_R0T0_MASK 0x1u
+#define LPUART_DATA_R0T0_SHIFT 0
+#define LPUART_DATA_R1T1_MASK 0x2u
+#define LPUART_DATA_R1T1_SHIFT 1
+#define LPUART_DATA_R2T2_MASK 0x4u
+#define LPUART_DATA_R2T2_SHIFT 2
+#define LPUART_DATA_R3T3_MASK 0x8u
+#define LPUART_DATA_R3T3_SHIFT 3
+#define LPUART_DATA_R4T4_MASK 0x10u
+#define LPUART_DATA_R4T4_SHIFT 4
+#define LPUART_DATA_R5T5_MASK 0x20u
+#define LPUART_DATA_R5T5_SHIFT 5
+#define LPUART_DATA_R6T6_MASK 0x40u
+#define LPUART_DATA_R6T6_SHIFT 6
+#define LPUART_DATA_R7T7_MASK 0x80u
+#define LPUART_DATA_R7T7_SHIFT 7
+#define LPUART_DATA_R8T8_MASK 0x100u
+#define LPUART_DATA_R8T8_SHIFT 8
+#define LPUART_DATA_R9T9_MASK 0x200u
+#define LPUART_DATA_R9T9_SHIFT 9
+#define LPUART_DATA_IDLINE_MASK 0x800u
+#define LPUART_DATA_IDLINE_SHIFT 11
+#define LPUART_DATA_RXEMPT_MASK 0x1000u
+#define LPUART_DATA_RXEMPT_SHIFT 12
+#define LPUART_DATA_FRETSC_MASK 0x2000u
+#define LPUART_DATA_FRETSC_SHIFT 13
+#define LPUART_DATA_PARITYE_MASK 0x4000u
+#define LPUART_DATA_PARITYE_SHIFT 14
+#define LPUART_DATA_NOISY_MASK 0x8000u
+#define LPUART_DATA_NOISY_SHIFT 15
+/* MATCH Bit Fields */
+#define LPUART_MATCH_MA1_MASK 0x3FFu
+#define LPUART_MATCH_MA1_SHIFT 0
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK 0x3FF0000u
+#define LPUART_MATCH_MA2_SHIFT 16
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x40054000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0_BASE_PTR (LPUART0)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE (0x40055000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
+#define LPUART1_BASE_PTR (LPUART1)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0, LPUART1 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
+#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register instance definitions */
+/* LPUART0 */
+#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
+#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
+#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
+#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
+#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
+/* LPUART1 */
+#define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
+#define LPUART1_STAT LPUART_STAT_REG(LPUART1)
+#define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
+#define LPUART1_DATA LPUART_DATA_REG(LPUART1)
+#define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
+ uint8_t RESERVED_0[4];
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_2[11];
+ __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
+ __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
+ __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
+ uint8_t RESERVED_3[1];
+ __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
+ __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
+ __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
+ __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
+#define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
+#define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
+#define MCG_MC_REG(base) ((base)->MC)
+#define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
+#define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
+#define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+/* S Bit Fields */
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+/* SC Bit Fields */
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+/* HCTRIM Bit Fields */
+#define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
+#define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
+#define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
+/* HTTRIM Bit Fields */
+#define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
+#define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
+#define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
+/* HFTRIM Bit Fields */
+#define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
+#define MCG_HFTRIM_FINE_TRIM_SHIFT 0
+#define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
+/* MC Bit Fields */
+#define MCG_MC_LIRC_DIV2_MASK 0x7u
+#define MCG_MC_LIRC_DIV2_SHIFT 0
+#define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
+#define MCG_MC_HIRCEN_MASK 0x80u
+#define MCG_MC_HIRCEN_SHIFT 7
+/* LTRIMRNG Bit Fields */
+#define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
+#define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
+#define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
+#define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
+#define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
+#define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
+/* LFTRIM Bit Fields */
+#define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
+#define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
+#define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
+/* LSTRIM Bit Fields */
+#define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
+#define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
+#define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
+#define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
+#define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
+#define MCG_MC MCG_MC_REG(MCG)
+#define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
+#define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
+#define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_PLACR_REG(base) ((base)->PLACR)
+#define MCM_CPO_REG(base) ((base)->CPO)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_PLACR MCM_PLACR_REG(MCM)
+#define MCM_CPO MCM_CPO_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type, *MTB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MTB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register accessors */
+#define MTB_POSITION_REG(base) ((base)->POSITION)
+#define MTB_MASTER_REG(base) ((base)->MASTER)
+#define MTB_FLOW_REG(base) ((base)->FLOW)
+#define MTB_BASE_REG(base) ((base)->BASE)
+#define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
+#define MTB_TAGSET_REG(base) ((base)->TAGSET)
+#define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
+#define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
+#define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
+#define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
+#define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
+#define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
+#define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
+#define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
+#define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+#define MTB_BASE_PTR (MTB)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS { MTB }
+
+/* ----------------------------------------------------------------------------
+ -- MTB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register instance definitions */
+/* MTB */
+#define MTB_POSITION MTB_POSITION_REG(MTB)
+#define MTB_MASTER MTB_MASTER_REG(MTB)
+#define MTB_FLOW MTB_FLOW_REG(MTB)
+#define MTB_BASEr MTB_BASE_REG(MTB)
+#define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
+#define MTB_TAGSET MTB_TAGSET_REG(MTB)
+#define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
+#define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
+#define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
+#define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
+#define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
+#define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
+#define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
+#define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
+#define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
+#define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
+#define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
+#define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
+#define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
+#define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
+#define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
+#define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
+#define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
+#define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
+#define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
+
+/* MTB - Register array accessors */
+#define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
+#define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type, *MTBDWT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register accessors */
+#define MTBDWT_CTRL_REG(base) ((base)->CTRL)
+#define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
+#define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
+#define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
+#define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
+#define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
+#define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
+#define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
+#define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+#define MTBDWT_BASE_PTR (MTBDWT)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS { MTBDWT }
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register instance definitions */
+/* MTBDWT */
+#define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
+#define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
+#define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
+#define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
+#define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
+#define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
+#define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
+#define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
+#define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
+#define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
+#define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
+#define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
+#define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
+#define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
+#define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
+#define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
+#define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
+#define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
+#define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
+#define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
+#define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
+#define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
+
+/* MTBDWT - Register array accessors */
+#define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
+#define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
+#define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
+#define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
+#define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
+#define NV_FOPT_BOOTPIN_OPT_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+#define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
+#define NV_FOPT_BOOTSRC_SEL_SHIFT 6
+#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFA_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+#define OSC0_BASE_PTR (OSC0)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0 }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC0 */
+#define OSC0_CR OSC_CR_REG(OSC0)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
+#define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT_IRQn, PIT_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
+#define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { PMC_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
+ __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
+ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
+ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_FM_REG(base) ((base)->FM)
+#define RCM_MR_REG(base) ((base)->MR)
+#define RCM_SSRS0_REG(base) ((base)->SSRS0)
+#define RCM_SSRS1_REG(base) ((base)->SSRS1)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* FM Bit Fields */
+#define RCM_FM_FORCEROM_MASK 0x6u
+#define RCM_FM_FORCEROM_SHIFT 1
+#define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
+/* MR Bit Fields */
+#define RCM_MR_BOOTROM_MASK 0x6u
+#define RCM_MR_BOOTROM_SHIFT 1
+#define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
+/* SSRS0 Bit Fields */
+#define RCM_SSRS0_SWAKEUP_MASK 0x1u
+#define RCM_SSRS0_SWAKEUP_SHIFT 0
+#define RCM_SSRS0_SLVD_MASK 0x2u
+#define RCM_SSRS0_SLVD_SHIFT 1
+#define RCM_SSRS0_SWDOG_MASK 0x20u
+#define RCM_SSRS0_SWDOG_SHIFT 5
+#define RCM_SSRS0_SPIN_MASK 0x40u
+#define RCM_SSRS0_SPIN_SHIFT 6
+#define RCM_SSRS0_SPOR_MASK 0x80u
+#define RCM_SSRS0_SPOR_SHIFT 7
+/* SSRS1 Bit Fields */
+#define RCM_SSRS1_SLOCKUP_MASK 0x2u
+#define RCM_SSRS1_SLOCKUP_SHIFT 1
+#define RCM_SSRS1_SSW_MASK 0x4u
+#define RCM_SSRS1_SSW_SHIFT 2
+#define RCM_SSRS1_SMDM_AP_MASK 0x8u
+#define RCM_SSRS1_SMDM_AP_SHIFT 3
+#define RCM_SSRS1_SSACKERR_MASK 0x20u
+#define RCM_SSRS1_SSACKERR_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_FM RCM_FM_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
+#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type, *ROM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ROM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register accessors */
+#define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
+#define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
+#define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
+#define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
+#define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
+#define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
+#define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
+#define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
+#define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
+#define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
+#define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
+#define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+#define ROM_BASE_PTR (ROM)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS { ROM }
+
+/* ----------------------------------------------------------------------------
+ -- ROM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register instance definitions */
+/* ROM */
+#define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
+#define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
+#define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
+#define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
+#define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
+#define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
+#define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
+#define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
+#define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
+#define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
+#define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
+#define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
+#define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
+#define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
+#define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
+#define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
+#define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
+
+/* ROM - Register array accessors */
+#define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
+#define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+#define SIM_COPC_REG(base) ((base)->COPC)
+#define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
+#define SIM_SOPT1_OSC32KOUT_SHIFT 16
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
+#define SIM_SOPT2_FLEXIOSRC_SHIFT 22
+#define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_LPUART0SRC_SHIFT 26
+#define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
+#define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
+#define SIM_SOPT2_LPUART1SRC_SHIFT 28
+#define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
+#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
+#define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
+#define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
+#define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
+#define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
+#define SIM_SOPT5_LPUART0ODE_SHIFT 16
+#define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
+#define SIM_SOPT5_LPUART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBFS_MASK 0x40000u
+#define SIM_SCGC4_USBFS_SHIFT 18
+#define SIM_SCGC4_CMP0_MASK 0x80000u
+#define SIM_SCGC4_CMP0_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+#define SIM_SCGC5_SLCD_MASK 0x80000u
+#define SIM_SCGC5_SLCD_SHIFT 19
+#define SIM_SCGC5_LPUART0_MASK 0x100000u
+#define SIM_SCGC5_LPUART0_SHIFT 20
+#define SIM_SCGC5_LPUART1_MASK 0x200000u
+#define SIM_SCGC5_LPUART1_SHIFT 21
+#define SIM_SCGC5_FLEXIO_MASK 0x80000000u
+#define SIM_SCGC5_FLEXIO_SHIFT 31
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+#define SIM_COPC_COPSTPEN_MASK 0x10u
+#define SIM_COPC_COPSTPEN_SHIFT 4
+#define SIM_COPC_COPDBGEN_MASK 0x20u
+#define SIM_COPC_COPDBGEN_SHIFT 5
+#define SIM_COPC_COPCLKSEL_MASK 0xC0u
+#define SIM_COPC_COPCLKSEL_SHIFT 6
+#define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+#define SIM_COPC SIM_COPC_REG(SIM)
+#define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_S_REG(base) ((base)->S)
+#define SPI_BR_REG(base) ((base)->BR)
+#define SPI_C2_REG(base) ((base)->C2)
+#define SPI_C1_REG(base) ((base)->C1)
+#define SPI_ML_REG(base) ((base)->ML)
+#define SPI_MH_REG(base) ((base)->MH)
+#define SPI_DL_REG(base) ((base)->DL)
+#define SPI_DH_REG(base) ((base)->DH)
+#define SPI_CI_REG(base) ((base)->CI)
+#define SPI_C3_REG(base) ((base)->C3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK 0x1u
+#define SPI_S_RFIFOEF_SHIFT 0
+#define SPI_S_TXFULLF_MASK 0x2u
+#define SPI_S_TXFULLF_SHIFT 1
+#define SPI_S_TNEAREF_MASK 0x4u
+#define SPI_S_TNEAREF_SHIFT 2
+#define SPI_S_RNFULLF_MASK 0x8u
+#define SPI_S_RNFULLF_SHIFT 3
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPIMODE_MASK 0x40u
+#define SPI_C2_SPIMODE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK 0xFFu
+#define SPI_ML_Bits_SHIFT 0
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK 0xFFu
+#define SPI_MH_Bits_SHIFT 0
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK 0xFFu
+#define SPI_DL_Bits_SHIFT 0
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK 0xFFu
+#define SPI_DH_Bits_SHIFT 0
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK 0x1u
+#define SPI_CI_SPRFCI_SHIFT 0
+#define SPI_CI_SPTEFCI_MASK 0x2u
+#define SPI_CI_SPTEFCI_SHIFT 1
+#define SPI_CI_RNFULLFCI_MASK 0x4u
+#define SPI_CI_RNFULLFCI_SHIFT 2
+#define SPI_CI_TNEAREFCI_MASK 0x8u
+#define SPI_CI_TNEAREFCI_SHIFT 3
+#define SPI_CI_RXFOF_MASK 0x10u
+#define SPI_CI_RXFOF_SHIFT 4
+#define SPI_CI_TXFOF_MASK 0x20u
+#define SPI_CI_TXFOF_SHIFT 5
+#define SPI_CI_RXFERR_MASK 0x40u
+#define SPI_CI_RXFERR_SHIFT 6
+#define SPI_CI_TXFERR_MASK 0x80u
+#define SPI_CI_TXFERR_SHIFT 7
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK 0x1u
+#define SPI_C3_FIFOMODE_SHIFT 0
+#define SPI_C3_RNFULLIEN_MASK 0x2u
+#define SPI_C3_RNFULLIEN_SHIFT 1
+#define SPI_C3_TNEARIEN_MASK 0x4u
+#define SPI_C3_TNEARIEN_SHIFT 2
+#define SPI_C3_INTCLR_MASK 0x8u
+#define SPI_C3_INTCLR_SHIFT 3
+#define SPI_C3_RNFULLF_MARK_MASK 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT 4
+#define SPI_C3_TNEAREF_MARK_MASK 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_S SPI_S_REG(SPI0)
+#define SPI0_BR SPI_BR_REG(SPI0)
+#define SPI0_C2 SPI_C2_REG(SPI0)
+#define SPI0_C1 SPI_C1_REG(SPI0)
+#define SPI0_ML SPI_ML_REG(SPI0)
+#define SPI0_MH SPI_MH_REG(SPI0)
+#define SPI0_DL SPI_DL_REG(SPI0)
+#define SPI0_DH SPI_DH_REG(SPI0)
+/* SPI1 */
+#define SPI1_S SPI_S_REG(SPI1)
+#define SPI1_BR SPI_BR_REG(SPI1)
+#define SPI1_C2 SPI_C2_REG(SPI1)
+#define SPI1_C1 SPI_C1_REG(SPI1)
+#define SPI1_ML SPI_ML_REG(SPI1)
+#define SPI1_MH SPI_MH_REG(SPI1)
+#define SPI1_DL SPI_DL_REG(SPI1)
+#define SPI1_DH SPI_DH_REG(SPI1)
+#define SPI1_CI SPI_CI_REG(SPI1)
+#define SPI1_C3 SPI_C3_REG(SPI1)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type, *TPM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- TPM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register accessors */
+#define TPM_SC_REG(base) ((base)->SC)
+#define TPM_CNT_REG(base) ((base)->CNT)
+#define TPM_MOD_REG(base) ((base)->MOD)
+#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define TPM_STATUS_REG(base) ((base)->STATUS)
+#define TPM_POL_REG(base) ((base)->POL)
+#define TPM_CONF_REG(base) ((base)->CONF)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* POL Bit Fields */
+#define TPM_POL_POL0_MASK 0x1u
+#define TPM_POL_POL0_SHIFT 0
+#define TPM_POL_POL1_MASK 0x2u
+#define TPM_POL_POL1_SHIFT 1
+#define TPM_POL_POL2_MASK 0x4u
+#define TPM_POL_POL2_SHIFT 2
+#define TPM_POL_POL3_MASK 0x8u
+#define TPM_POL_POL3_SHIFT 3
+#define TPM_POL_POL4_MASK 0x10u
+#define TPM_POL_POL4_SHIFT 4
+#define TPM_POL_POL5_MASK 0x20u
+#define TPM_POL_POL5_SHIFT 5
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK 0x100u
+#define TPM_CONF_GTBSYNC_SHIFT 8
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_CPOT_MASK 0x80000u
+#define TPM_CONF_CPOT_SHIFT 19
+#define TPM_CONF_TRGPOL_MASK 0x400000u
+#define TPM_CONF_TRGPOL_SHIFT 22
+#define TPM_CONF_TRGSRC_MASK 0x800000u
+#define TPM_CONF_TRGSRC_SHIFT 23
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+#define TPM0_BASE_PTR (TPM0)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+#define TPM1_BASE_PTR (TPM1)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+#define TPM2_BASE_PTR (TPM2)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- TPM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register instance definitions */
+/* TPM0 */
+#define TPM0_SC TPM_SC_REG(TPM0)
+#define TPM0_CNT TPM_CNT_REG(TPM0)
+#define TPM0_MOD TPM_MOD_REG(TPM0)
+#define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
+#define TPM0_C0V TPM_CnV_REG(TPM0,0)
+#define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
+#define TPM0_C1V TPM_CnV_REG(TPM0,1)
+#define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
+#define TPM0_C2V TPM_CnV_REG(TPM0,2)
+#define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
+#define TPM0_C3V TPM_CnV_REG(TPM0,3)
+#define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
+#define TPM0_C4V TPM_CnV_REG(TPM0,4)
+#define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
+#define TPM0_C5V TPM_CnV_REG(TPM0,5)
+#define TPM0_STATUS TPM_STATUS_REG(TPM0)
+#define TPM0_POL TPM_POL_REG(TPM0)
+#define TPM0_CONF TPM_CONF_REG(TPM0)
+/* TPM1 */
+#define TPM1_SC TPM_SC_REG(TPM1)
+#define TPM1_CNT TPM_CNT_REG(TPM1)
+#define TPM1_MOD TPM_MOD_REG(TPM1)
+#define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
+#define TPM1_C0V TPM_CnV_REG(TPM1,0)
+#define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
+#define TPM1_C1V TPM_CnV_REG(TPM1,1)
+#define TPM1_STATUS TPM_STATUS_REG(TPM1)
+#define TPM1_POL TPM_POL_REG(TPM1)
+#define TPM1_CONF TPM_CONF_REG(TPM1)
+/* TPM2 */
+#define TPM2_SC TPM_SC_REG(TPM2)
+#define TPM2_CNT TPM_CNT_REG(TPM2)
+#define TPM2_MOD TPM_MOD_REG(TPM2)
+#define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
+#define TPM2_C0V TPM_CnV_REG(TPM2,0)
+#define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
+#define TPM2_C1V TPM_CnV_REG(TPM2,1)
+#define TPM2_STATUS TPM_STATUS_REG(TPM2)
+#define TPM2_POL TPM_POL_REG(TPM2)
+#define TPM2_CONF TPM_CONF_REG(TPM2)
+
+/* TPM - Register array accessors */
+#define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
+#define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
+#define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
+#define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
+#define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
+#define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ uint8_t RESERVED_0[12];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_1[26];
+ __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+ union { /* offset: 0x3C */
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE0;
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE1;
+ };
+ __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816_REG(base) ((base)->WP7816)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
+#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
+#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
+#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
+#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
+#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
+#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
+#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_ADTE_MASK 0x8u
+#define UART_IE7816_ADTE_SHIFT 3
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_ADT_MASK 0x8u
+#define UART_IS7816_ADT_SHIFT 3
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816 Bit Fields */
+#define UART_WP7816_WTX_MASK 0xFFu
+#define UART_WP7816_WTX_SHIFT 0
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* AP7816A_T0 Bit Fields */
+#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
+#define UART_AP7816A_T0_ADTI_H_SHIFT 0
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
+/* AP7816B_T0 Bit Fields */
+#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
+#define UART_AP7816B_T0_ADTI_L_SHIFT 0
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
+/* WP7816A_T0 Bit Fields */
+#define UART_WP7816A_T0_WI_H_MASK 0xFFu
+#define UART_WP7816A_T0_WI_H_SHIFT 0
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
+/* WP7816B_T0 Bit Fields */
+#define UART_WP7816B_T0_WI_L_MASK 0xFFu
+#define UART_WP7816B_T0_WI_L_SHIFT 0
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
+/* WP7816A_T1 Bit Fields */
+#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
+#define UART_WP7816A_T1_BWI_H_SHIFT 0
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
+/* WP7816B_T1 Bit Fields */
+#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
+#define UART_WP7816B_T1_BWI_L_SHIFT 0
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
+/* WGP7816_T1 Bit Fields */
+#define UART_WGP7816_T1_BGI_MASK 0xFu
+#define UART_WGP7816_T1_BGI_SHIFT 0
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK 0xF0u
+#define UART_WGP7816_T1_CWI1_SHIFT 4
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
+/* WP7816C_T1 Bit Fields */
+#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
+#define UART_WP7816C_T1_CWI2_SHIFT 0
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
+#define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_C7816 UART_C7816_REG(UART2)
+#define UART2_IE7816 UART_IE7816_REG(UART2)
+#define UART2_IS7816 UART_IS7816_REG(UART2)
+#define UART2_WP7816 UART_WP7816_REG(UART2)
+#define UART2_WN7816 UART_WN7816_REG(UART2)
+#define UART2_WF7816 UART_WF7816_REG(UART2)
+#define UART2_ET7816 UART_ET7816_REG(UART2)
+#define UART2_TL7816 UART_TL7816_REG(UART2)
+#define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
+#define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
+#define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
+#define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
+#define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
+#define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
+#define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
+#define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[15];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_4[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_7[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_8[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_11[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_14[11];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_16[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_17[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_20[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_21[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_22[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_23[15];
+ __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
+ uint8_t RESERVED_24[7];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5_MASK 0x2u
+#define USB_ERRSTAT_CRC5_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_EN Bit Fields */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
+#define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
+#define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
+#define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
+#define I2C_S1_SRW_MASK I2C_S_SRW_MASK
+#define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
+#define I2C_S1_RAM_MASK I2C_S_RAM_MASK
+#define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
+#define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
+#define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
+#define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
+#define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
+#define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
+#define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
+#define I2C_S1_TCF_MASK I2C_S_TCF_MASK
+#define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
+#define I2C_S1_REG(base) I2C_S_REG(base)
+#define I2C0_S1 I2C0_S
+#define I2C1_S1 I2C1_S
+#define ADC_BASES ADC_BASE_PTRS
+#define CMP_BASES CMP_BASE_PTRS
+#define DAC_BASES DAC_BASE_PTRS
+#define DMA_BASES DMA_BASE_PTRS
+#define DMAMUX_BASES DMAMUX_BASE_PTRS
+#define FLEXIO_BASES FLEXIO_BASE_PTRS
+#define FTFA_BASES FTFA_BASE_PTRS
+#define GPIO_BASES GPIO_BASE_PTRS
+#define I2C_BASES I2C_BASE_PTRS
+#define I2S_BASES I2S_BASE_PTRS
+#define LCD_BASES LCD_BASE_PTRS
+#define LLWU_BASES LLWU_BASE_PTRS
+#define LPTMR_BASES LPTMR_BASE_PTRS
+#define LPUART_BASES LPUART_BASE_PTRS
+#define MCG_BASES MCG_BASE_PTRS
+#define MCM_BASES MCM_BASE_PTRS
+#define MTB_BASES MTB_BASE_PTRS
+#define MTBDWT_BASES MTBDWT_BASE_PTRS
+#define NV_BASES NV_BASE_PTRS
+#define OSC_BASES OSC_BASE_PTRS
+#define PIT_BASES PIT_BASE_PTRS
+#define PMC_BASES PMC_BASE_PTRS
+#define PORT_BASES PORT_BASE_PTRS
+#define RCM_BASES RCM_BASE_PTRS
+#define ROM_BASES ROM_BASE_PTRS
+#define RTC_BASES RTC_BASE_PTRS
+#define SIM_BASES SIM_BASE_PTRS
+#define SMC_BASES SMC_BASE_PTRS
+#define SPI_BASES SPI_BASE_PTRS
+#define TPM_BASES TPM_BASE_PTRS
+#define UART_BASES UART_BASE_PTRS
+#define USB_BASES USB_BASE_PTRS
+#define VREF_BASES VREF_BASE_PTRS
+#define PTA_BASE_PTR GPIOA_BASE_PTR
+#define PTB_BASE_PTR GPIOB_BASE_PTR
+#define PTC_BASE_PTR GPIOC_BASE_PTR
+#define PTD_BASE_PTR GPIOD_BASE_PTR
+#define PTE_BASE_PTR GPIOE_BASE_PTR
+#define PTA_BASE GPIOA_BASE
+#define PTB_BASE GPIOB_BASE
+#define PTC_BASE GPIOC_BASE
+#define PTD_BASE GPIOD_BASE
+#define PTE_BASE GPIOE_BASE
+#define PTA GPIOA
+#define PTB GPIOB
+#define PTC GPIOC
+#define PTD GPIOD
+#define PTE GPIOE
+#define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
+#define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
+#define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
+#define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
+#define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
+#define UART0_BASE UART2_BASE
+#define UART0 UART2
+#define UART0_BASE_PTR UART2_BASE_PTR
+#define UART0_BDH UART2_BDH
+#define UART0_BDL UART2_BDL
+#define UART0_C1 UART2_C1
+#define UART0_C2 UART2_C2
+#define UART0_S1 UART2_S1
+#define UART0_S2 UART2_S2
+#define UART0_C3 UART2_C3
+#define UART0_D UART2_D
+#define UART0_MA1 UART2_MA1
+#define UART0_MA2 UART2_MA2
+#define UART0_C4 UART2_C4
+#define UART0_C5 UART2_C5
+#define UART0_ED UART2_ED
+#define UART0_MODEM UART2_MODEM
+#define UART0_IR UART2_IR
+#define UART0_PFIFO UART2_PFIFO
+#define UART0_CFIFO UART2_CFIFO
+#define UART0_SFIFO UART2_SFIFO
+#define UART0_TWFIFO UART2_TWFIFO
+#define UART0_TCFIFO UART2_TCFIFO
+#define UART0_RWFIFO UART2_RWFIFO
+#define UART0_RCFIFO UART2_RCFIFO
+#define UART0_C7816 UART2_C7816
+#define UART0_IE7816 UART2_IE7816
+#define UART0_IS7816 UART2_IS7816
+#define UART0_WP7816 UART2_WP7816
+#define UART0_WN7816 UART2_WN7816
+#define UART0_WF7816 UART2_WF7816
+#define UART0_ET7816 UART2_ET7816
+#define UART0_TL7816 UART2_TL7816
+#define UART0_AP7816A_T0 UART2_AP7816A_T0
+#define UART0_AP7816B_T0 UART2_AP7816B_T0
+#define UART0_WP7816A_T0 UART2_WP7816A_T0
+#define UART0_WP7816A_T1 UART2_WP7816A_T1
+#define UART0_WP7816B_T0 UART2_WP7816B_T0
+#define UART0_WP7816B_T1 UART2_WP7816B_T1
+#define UART0_WGP7816_T1 UART2_WGP7816_T1
+#define UART0_WP7816C_T1 UART2_WP7816C_T1
+#define I2S0_MDR This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
+#define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
+#define I2S_MDR_REG(base) This_symb_has_been_deprecated
+#define CTL0 OTGCTL
+#define USB0_CTL0 USB0_OTGCTL
+#define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
+#define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
+#define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
+#define CTL1 CTL
+#define USB0_CTL1 USB0_CTL
+#define USB_CTL1_REG(base) USB_CTL_REG(base)
+#define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
+#define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
+#define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
+#define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
+#define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
+#define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
+#define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
+#define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
+#define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
+#define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
+#define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
+#define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MKL43Z4_H_) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0100u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
+#endif /* #if !defined(MKL43Z4_H_) */
+
+/* MKL43Z4.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct
new file mode 100644
index 000000000..82ddfb878
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x8000 - 0xC0 = 0x7F40
+ RW_IRAM1 0x1FFFE0C0 0x7F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s
new file mode 100644
index 000000000..58abd545d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s
@@ -0,0 +1,362 @@
+; * ---------------------------------------------------------------------------------------
+; * @file: startup_MKL43Z4.s
+; * @purpose: CMSIS Cortex-M0P Core Device Startup File
+; * MKL43Z4
+; * @version: 1.3
+; * @date: 2014-8-21
+; * @build: b140821
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; * of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; * list of conditions and the following disclaimer in the documentation and/or
+; * other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; * contributors may be used to endorse or promote products derived from this
+; * software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20006000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ;NMI Handler
+ DCD HardFault_Handler ;Hard Fault Handler
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD SVC_Handler ;SVCall Handler
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD PendSV_Handler ;PendSV Handler
+ DCD SysTick_Handler ;SysTick Handler
+
+ ;External Interrupts
+ DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
+ DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
+ DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
+ DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
+ DCD Reserved20_IRQHandler ;Reserved interrupt
+ DCD FTFA_IRQHandler ;Command complete and read collision
+ DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
+ DCD LLWU_IRQHandler ;Low leakage wakeup
+ DCD I2C0_IRQHandler ;I2C0 interrupt
+ DCD I2C1_IRQHandler ;I2C1 interrupt
+ DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
+ DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
+ DCD LPUART0_IRQHandler ;LPUART0 status and error
+ DCD LPUART1_IRQHandler ;LPUART1 status and error
+ DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
+ DCD ADC0_IRQHandler ;ADC0 interrupt
+ DCD CMP0_IRQHandler ;CMP0 interrupt
+ DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
+ DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
+ DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
+ DCD RTC_IRQHandler ;RTC alarm
+ DCD RTC_Seconds_IRQHandler ;RTC seconds
+ DCD PIT_IRQHandler ;PIT interrupt
+ DCD I2S0_IRQHandler ;I2S0 interrupt
+ DCD USB0_IRQHandler ;USB0 interrupt
+ DCD DAC0_IRQHandler ;DAC0 interrupt
+ DCD Reserved42_IRQHandler ;Reserved interrupt
+ DCD Reserved43_IRQHandler ;Reserved interrupt
+ DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
+ DCD LCD_IRQHandler ;LCD interrupt
+ DCD PORTA_IRQHandler ;PORTA Pin detect
+ DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict access to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
+; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
+; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
+; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
+; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
+; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
+; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
+; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program Flash Region Protect Register 0
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
+; <o.1> BOOTPIN_OPT
+; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI_b pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
+; <1=> RESET_b pin is dedicated
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
+; <o.5> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+; <o.6..7> BOOTSRC_SEL
+; <0=> Boot from Flash
+; <2=> Boot from ROM
+; <3=> Boot from ROM
+; <i> Boot source selection
+FOPT EQU 0x3F
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor Key Security Enable
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, DATA, READONLY
+__FlashConfig
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
+ DCB FSEC , FOPT , 0xFF , 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler\
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Default_Handler\
+ PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT PMC_IRQHandler [WEAK]
+ EXPORT LLWU_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT LPUART0_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT UART2_FLEXIO_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT Reserved42_IRQHandler [WEAK]
+ EXPORT Reserved43_IRQHandler [WEAK]
+ EXPORT LPTMR0_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTCD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+PMC_IRQHandler
+LLWU_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+UART2_FLEXIO_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+Reserved42_IRQHandler
+Reserved43_IRQHandler
+LPTMR0_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTCD_IRQHandler
+DefaultISR
+ B .
+ ENDP
+ ALIGN
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld
new file mode 100644
index 000000000..80cc231e5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL43Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S
new file mode 100644
index 000000000..7f1b04ccf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S
@@ -0,0 +1,243 @@
+/* KL43Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 10 Nov 2014
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x200 + 0x400 = 0x600
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x200
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/
+ .long LLWU_IRQHandler /* Low leakage wakeup*/
+ .long I2C0_IRQHandler /* I2C0 interrupt*/
+ .long I2C1_IRQHandler /* I2C1 interrupt*/
+ .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
+ .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
+ .long LPUART0_IRQHandler /* LPUART0 status and error*/
+ .long LPUART1_IRQHandler /* LPUART1 status and error*/
+ .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/
+ .long ADC0_IRQHandler /* ADC0 interrupt*/
+ .long CMP0_IRQHandler /* CMP0 interrupt*/
+ .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
+ .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
+ .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
+ .long RTC_IRQHandler /* RTC alarm*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds*/
+ .long PIT_IRQHandler /* PIT interrupt*/
+ .long I2S0_IRQHandler /* I2S0 interrupt*/
+ .long USB0_IRQHandler /* USB0 interrupt*/
+ .long DAC0_IRQHandler /* DAC0 interrupt*/
+ .long Reserved42_IRQHandler /* Reserved interrupt*/
+ .long Reserved43_IRQHandler /* Reserved interrupt*/
+ .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
+ .long LCD_IRQHandler /* LCD interrupt*/
+ .long PORTA_IRQHandler /* PORTA Pin detect*/
+ .long PORTCD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/
+
+ .size __isr_vector, . - __isr_vector
+
+ /* Reset Handler */
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ /* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler Reserved20_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler PMC_IRQHandler
+ def_irq_default_handler LLWU_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler LPUART0_IRQHandler
+ def_irq_default_handler LPUART1_IRQHandler
+ def_irq_default_handler UART2_FLEXIO_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler I2S0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler Reserved42_IRQHandler
+ def_irq_default_handler Reserved43_IRQHandler
+ def_irq_default_handler LPTMR0_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTCD_IRQHandler
+ def_irq_default_handler DefaultISR
+
+ /* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFF3FFE
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp
new file mode 100644
index 000000000..fe88ed4fc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/types.h>
+#include <errno.h>
+
+extern void exit(int return_code);
+
+int _kill(int pid, int sig) {
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit(int status) {
+ exit(status);
+}
+
+int _getpid(void) {
+ return 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h
new file mode 100644
index 000000000..c7bc71154
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL43Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c
new file mode 100644
index 000000000..8d6430685
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h
new file mode 100644
index 000000000..6acdca9ef
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c
new file mode 100644
index 000000000..e17528f3b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c
@@ -0,0 +1,224 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.4, 2014-09-01
+** Build: b140904
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4
+ * @version 1.4
+ * @date 2014-09-01
+ * @brief Device specific configuration file for MKL43Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL43Z4.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (ACK_ISOLATION)
+ if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
+ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
+ }
+#endif
+
+#if (DISABLE_WDOG)
+ /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+
+ /* Power mode protection initialization */
+#ifdef SMC_PMPROT_VALUE
+ SMC->PMPROT = SMC_PMPROT_VALUE;
+#endif
+
+ /* System clock initialization */
+
+ /* Set system prescalers and clock sources */
+ SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+ SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+#define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */
+ SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~SOPT2_WRITE_MASK)) | ((SYSTEM_SIM_SOPT2_VALUE) & SOPT2_WRITE_MASK); /* Selects the clock source for the TPM counter clock. */
+#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
+ /* Set MCG and OSC0 */
+#if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR3: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
+ MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
+ MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
+ MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
+ OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+
+#else /* MCG_MODE */
+ /* Set MCG and OSC0 */
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR3: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+ MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
+ MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
+ OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
+ MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+ }
+ }
+#endif /* MCG_MODE */
+
+ /* Common for all MCG modes */
+
+#if (MCG_MODE == MCG_MODE_HIRC)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */
+ }
+#elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */
+ }
+#elif (MCG_MODE == MCG_MODE_EXT)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */
+ }
+#endif
+ if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) {
+ SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+ while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
+ }
+ }
+
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
+ /* High internal reference clock is selected */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
+ } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
+ /* Internal reference clock is selected */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
+ } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ;
+ } else {
+ /* Reserved value */
+ return;
+ } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h
new file mode 100644
index 000000000..4b07fde83
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h
@@ -0,0 +1,335 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.4, 2014-09-01
+** Build: b140904
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4
+ * @version 1.4
+ * @date 2014-09-01
+ * @brief Device specific configuration file for MKL43Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL43Z4_H_
+#define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+ #define DISABLE_WDOG 1
+#endif
+
+#define ACK_ISOLATION 1
+
+#ifndef CLOCK_SETUP
+ #define CLOCK_SETUP 1
+#endif
+
+/* MCG_Lite mode constants */
+
+#define MCG_MODE_LIRC_8M 0U
+#define MCG_MODE_HIRC 1U
+#define MCG_MODE_LIRC_2M 2U
+#define MCG_MODE_EXT 3U
+
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
+ Default part configuration.
+ Core clock/Bus clock derived from the internal clock source 8 MHz
+ Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+ Maximum achievable clock frequency configuration using internal clock.
+ Core clock/Bus clock derived from the internal clock source 48MHz
+ Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+ Core clock/Bus clock derived directly from the external crystal 32.768kHz
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
+ Core clock/Bus clock derived from the internal clock source 2 MHz
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+ USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
+ Core clock/Bus clock derived from the internal clock source 48MHz
+ Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
+ 5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+ Core clock/Bus clock derived directly from the external crystal 8 MHz
+ Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,AVLLS=1 */
+#define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
+
+#if (CLOCK_SETUP == 0)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
+ /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x42u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
+ /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x00u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x80u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+ #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
+ /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x82u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
+ #define MCG_C2_VALUE 0x05u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x42u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
+ #define MCG_C2_VALUE 0x00u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x02u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x80u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 5)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x80u /* MCG_C1 */
+ /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
+ #define MCG_C2_VALUE 0x15u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#else
+ #error The selected clock setup is not supported.
+#endif /* (CLOCK_SETUP == 5) */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL43Z4_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h
new file mode 100644
index 000000000..9f975d7d0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h
@@ -0,0 +1,5801 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
+** Version: rev. 2.2, 2013-04-12
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL46Z4
+**
+** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+** - rev. 2.1 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 2.2 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL46Z4.h
+ * @version 2.2
+ * @date 2013-04-12
+ * @brief CMSIS Peripheral Access Layer for MKL46Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL46Z4
+ */
+
+#if !defined(MKL46Z4_H_)
+#define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ SPI1_IRQn = 11, /**< SPI1 interrupt */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ UART1_IRQn = 13, /**< UART1 status/error interrupt */
+ UART2_IRQn = 14, /**< UART2 status/error interrupt */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ LCD_IRQn = 29, /**< Segment LCD Interrupt */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL46Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1 }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_CLKMODE_MASK 0xC000000u
+#define I2S_TCR2_CLKMODE_SHIFT 26
+#define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1u
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x10000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0x3u
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_CLKMODE_MASK 0xC000000u
+#define I2S_RCR2_CLKMODE_SHIFT 26
+#define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1u
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x10000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0x3u
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASES { I2S0 }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
+ __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
+ __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
+ __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
+ __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+ union { /* offset: 0x20 */
+ __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+ __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+ };
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK 0x7u
+#define LCD_GCR_DUTY_SHIFT 0
+#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK 0x38u
+#define LCD_GCR_LCLK_SHIFT 3
+#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK 0x40u
+#define LCD_GCR_SOURCE_SHIFT 6
+#define LCD_GCR_LCDEN_MASK 0x80u
+#define LCD_GCR_LCDEN_SHIFT 7
+#define LCD_GCR_LCDSTP_MASK 0x100u
+#define LCD_GCR_LCDSTP_SHIFT 8
+#define LCD_GCR_LCDDOZE_MASK 0x200u
+#define LCD_GCR_LCDDOZE_SHIFT 9
+#define LCD_GCR_FFR_MASK 0x400u
+#define LCD_GCR_FFR_SHIFT 10
+#define LCD_GCR_ALTSOURCE_MASK 0x800u
+#define LCD_GCR_ALTSOURCE_SHIFT 11
+#define LCD_GCR_ALTDIV_MASK 0x3000u
+#define LCD_GCR_ALTDIV_SHIFT 12
+#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK 0x4000u
+#define LCD_GCR_FDCIEN_SHIFT 14
+#define LCD_GCR_PADSAFE_MASK 0x8000u
+#define LCD_GCR_PADSAFE_SHIFT 15
+#define LCD_GCR_VSUPPLY_MASK 0x20000u
+#define LCD_GCR_VSUPPLY_SHIFT 17
+#define LCD_GCR_LADJ_MASK 0x300000u
+#define LCD_GCR_LADJ_SHIFT 20
+#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_CPSEL_MASK 0x800000u
+#define LCD_GCR_CPSEL_SHIFT 23
+#define LCD_GCR_RVTRIM_MASK 0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT 24
+#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK 0x80000000u
+#define LCD_GCR_RVEN_SHIFT 31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK 0x7u
+#define LCD_AR_BRATE_SHIFT 0
+#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK 0x8u
+#define LCD_AR_BMODE_SHIFT 3
+#define LCD_AR_BLANK_MASK 0x20u
+#define LCD_AR_BLANK_SHIFT 5
+#define LCD_AR_ALT_MASK 0x40u
+#define LCD_AR_ALT_SHIFT 6
+#define LCD_AR_BLINK_MASK 0x80u
+#define LCD_AR_BLINK_SHIFT 7
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK 0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT 0
+#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK 0x40u
+#define LCD_FDCR_FDBPEN_SHIFT 6
+#define LCD_FDCR_FDEN_MASK 0x80u
+#define LCD_FDCR_FDEN_SHIFT 7
+#define LCD_FDCR_FDSWW_MASK 0xE00u
+#define LCD_FDCR_FDSWW_SHIFT 9
+#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK 0x7000u
+#define LCD_FDCR_FDPRS_SHIFT 12
+#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK 0xFFu
+#define LCD_FDSR_FDCNT_SHIFT 0
+#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK 0x8000u
+#define LCD_FDSR_FDCF_SHIFT 15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT 0
+#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT 0
+#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK 0xFFu
+#define LCD_WF_WF0_SHIFT 0
+#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK 0xFFu
+#define LCD_WF_WF60_SHIFT 0
+#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK 0xFFu
+#define LCD_WF_WF56_SHIFT 0
+#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK 0xFFu
+#define LCD_WF_WF52_SHIFT 0
+#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK 0xFFu
+#define LCD_WF_WF4_SHIFT 0
+#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK 0xFFu
+#define LCD_WF_WF48_SHIFT 0
+#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK 0xFFu
+#define LCD_WF_WF44_SHIFT 0
+#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK 0xFFu
+#define LCD_WF_WF40_SHIFT 0
+#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK 0xFFu
+#define LCD_WF_WF8_SHIFT 0
+#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK 0xFFu
+#define LCD_WF_WF36_SHIFT 0
+#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK 0xFFu
+#define LCD_WF_WF32_SHIFT 0
+#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK 0xFFu
+#define LCD_WF_WF28_SHIFT 0
+#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK 0xFFu
+#define LCD_WF_WF12_SHIFT 0
+#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK 0xFFu
+#define LCD_WF_WF24_SHIFT 0
+#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK 0xFFu
+#define LCD_WF_WF20_SHIFT 0
+#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK 0xFFu
+#define LCD_WF_WF16_SHIFT 0
+#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK 0xFF00u
+#define LCD_WF_WF5_SHIFT 8
+#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK 0xFF00u
+#define LCD_WF_WF49_SHIFT 8
+#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK 0xFF00u
+#define LCD_WF_WF45_SHIFT 8
+#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK 0xFF00u
+#define LCD_WF_WF61_SHIFT 8
+#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK 0xFF00u
+#define LCD_WF_WF25_SHIFT 8
+#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK 0xFF00u
+#define LCD_WF_WF17_SHIFT 8
+#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK 0xFF00u
+#define LCD_WF_WF41_SHIFT 8
+#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK 0xFF00u
+#define LCD_WF_WF13_SHIFT 8
+#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK 0xFF00u
+#define LCD_WF_WF57_SHIFT 8
+#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK 0xFF00u
+#define LCD_WF_WF53_SHIFT 8
+#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK 0xFF00u
+#define LCD_WF_WF37_SHIFT 8
+#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK 0xFF00u
+#define LCD_WF_WF9_SHIFT 8
+#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK 0xFF00u
+#define LCD_WF_WF1_SHIFT 8
+#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK 0xFF00u
+#define LCD_WF_WF29_SHIFT 8
+#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK 0xFF00u
+#define LCD_WF_WF33_SHIFT 8
+#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK 0xFF00u
+#define LCD_WF_WF21_SHIFT 8
+#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK 0xFF0000u
+#define LCD_WF_WF26_SHIFT 16
+#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK 0xFF0000u
+#define LCD_WF_WF46_SHIFT 16
+#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK 0xFF0000u
+#define LCD_WF_WF6_SHIFT 16
+#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK 0xFF0000u
+#define LCD_WF_WF42_SHIFT 16
+#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK 0xFF0000u
+#define LCD_WF_WF18_SHIFT 16
+#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK 0xFF0000u
+#define LCD_WF_WF38_SHIFT 16
+#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK 0xFF0000u
+#define LCD_WF_WF22_SHIFT 16
+#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK 0xFF0000u
+#define LCD_WF_WF34_SHIFT 16
+#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK 0xFF0000u
+#define LCD_WF_WF50_SHIFT 16
+#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK 0xFF0000u
+#define LCD_WF_WF14_SHIFT 16
+#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK 0xFF0000u
+#define LCD_WF_WF54_SHIFT 16
+#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK 0xFF0000u
+#define LCD_WF_WF2_SHIFT 16
+#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK 0xFF0000u
+#define LCD_WF_WF58_SHIFT 16
+#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK 0xFF0000u
+#define LCD_WF_WF30_SHIFT 16
+#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK 0xFF0000u
+#define LCD_WF_WF62_SHIFT 16
+#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK 0xFF0000u
+#define LCD_WF_WF10_SHIFT 16
+#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK 0xFF000000u
+#define LCD_WF_WF63_SHIFT 24
+#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK 0xFF000000u
+#define LCD_WF_WF59_SHIFT 24
+#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK 0xFF000000u
+#define LCD_WF_WF55_SHIFT 24
+#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK 0xFF000000u
+#define LCD_WF_WF3_SHIFT 24
+#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK 0xFF000000u
+#define LCD_WF_WF51_SHIFT 24
+#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK 0xFF000000u
+#define LCD_WF_WF47_SHIFT 24
+#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK 0xFF000000u
+#define LCD_WF_WF43_SHIFT 24
+#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK 0xFF000000u
+#define LCD_WF_WF7_SHIFT 24
+#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK 0xFF000000u
+#define LCD_WF_WF39_SHIFT 24
+#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK 0xFF000000u
+#define LCD_WF_WF35_SHIFT 24
+#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK 0xFF000000u
+#define LCD_WF_WF31_SHIFT 24
+#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK 0xFF000000u
+#define LCD_WF_WF11_SHIFT 24
+#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK 0xFF000000u
+#define LCD_WF_WF27_SHIFT 24
+#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK 0xFF000000u
+#define LCD_WF_WF23_SHIFT 24
+#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK 0xFF000000u
+#define LCD_WF_WF19_SHIFT 24
+#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK 0xFF000000u
+#define LCD_WF_WF15_SHIFT 24
+#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK 0x1u
+#define LCD_WF8B_BPALCD0_SHIFT 0
+#define LCD_WF8B_BPALCD63_MASK 0x1u
+#define LCD_WF8B_BPALCD63_SHIFT 0
+#define LCD_WF8B_BPALCD62_MASK 0x1u
+#define LCD_WF8B_BPALCD62_SHIFT 0
+#define LCD_WF8B_BPALCD61_MASK 0x1u
+#define LCD_WF8B_BPALCD61_SHIFT 0
+#define LCD_WF8B_BPALCD60_MASK 0x1u
+#define LCD_WF8B_BPALCD60_SHIFT 0
+#define LCD_WF8B_BPALCD59_MASK 0x1u
+#define LCD_WF8B_BPALCD59_SHIFT 0
+#define LCD_WF8B_BPALCD58_MASK 0x1u
+#define LCD_WF8B_BPALCD58_SHIFT 0
+#define LCD_WF8B_BPALCD57_MASK 0x1u
+#define LCD_WF8B_BPALCD57_SHIFT 0
+#define LCD_WF8B_BPALCD1_MASK 0x1u
+#define LCD_WF8B_BPALCD1_SHIFT 0
+#define LCD_WF8B_BPALCD56_MASK 0x1u
+#define LCD_WF8B_BPALCD56_SHIFT 0
+#define LCD_WF8B_BPALCD55_MASK 0x1u
+#define LCD_WF8B_BPALCD55_SHIFT 0
+#define LCD_WF8B_BPALCD54_MASK 0x1u
+#define LCD_WF8B_BPALCD54_SHIFT 0
+#define LCD_WF8B_BPALCD53_MASK 0x1u
+#define LCD_WF8B_BPALCD53_SHIFT 0
+#define LCD_WF8B_BPALCD52_MASK 0x1u
+#define LCD_WF8B_BPALCD52_SHIFT 0
+#define LCD_WF8B_BPALCD51_MASK 0x1u
+#define LCD_WF8B_BPALCD51_SHIFT 0
+#define LCD_WF8B_BPALCD50_MASK 0x1u
+#define LCD_WF8B_BPALCD50_SHIFT 0
+#define LCD_WF8B_BPALCD2_MASK 0x1u
+#define LCD_WF8B_BPALCD2_SHIFT 0
+#define LCD_WF8B_BPALCD49_MASK 0x1u
+#define LCD_WF8B_BPALCD49_SHIFT 0
+#define LCD_WF8B_BPALCD48_MASK 0x1u
+#define LCD_WF8B_BPALCD48_SHIFT 0
+#define LCD_WF8B_BPALCD47_MASK 0x1u
+#define LCD_WF8B_BPALCD47_SHIFT 0
+#define LCD_WF8B_BPALCD46_MASK 0x1u
+#define LCD_WF8B_BPALCD46_SHIFT 0
+#define LCD_WF8B_BPALCD45_MASK 0x1u
+#define LCD_WF8B_BPALCD45_SHIFT 0
+#define LCD_WF8B_BPALCD44_MASK 0x1u
+#define LCD_WF8B_BPALCD44_SHIFT 0
+#define LCD_WF8B_BPALCD43_MASK 0x1u
+#define LCD_WF8B_BPALCD43_SHIFT 0
+#define LCD_WF8B_BPALCD3_MASK 0x1u
+#define LCD_WF8B_BPALCD3_SHIFT 0
+#define LCD_WF8B_BPALCD42_MASK 0x1u
+#define LCD_WF8B_BPALCD42_SHIFT 0
+#define LCD_WF8B_BPALCD41_MASK 0x1u
+#define LCD_WF8B_BPALCD41_SHIFT 0
+#define LCD_WF8B_BPALCD40_MASK 0x1u
+#define LCD_WF8B_BPALCD40_SHIFT 0
+#define LCD_WF8B_BPALCD39_MASK 0x1u
+#define LCD_WF8B_BPALCD39_SHIFT 0
+#define LCD_WF8B_BPALCD38_MASK 0x1u
+#define LCD_WF8B_BPALCD38_SHIFT 0
+#define LCD_WF8B_BPALCD37_MASK 0x1u
+#define LCD_WF8B_BPALCD37_SHIFT 0
+#define LCD_WF8B_BPALCD36_MASK 0x1u
+#define LCD_WF8B_BPALCD36_SHIFT 0
+#define LCD_WF8B_BPALCD4_MASK 0x1u
+#define LCD_WF8B_BPALCD4_SHIFT 0
+#define LCD_WF8B_BPALCD35_MASK 0x1u
+#define LCD_WF8B_BPALCD35_SHIFT 0
+#define LCD_WF8B_BPALCD34_MASK 0x1u
+#define LCD_WF8B_BPALCD34_SHIFT 0
+#define LCD_WF8B_BPALCD33_MASK 0x1u
+#define LCD_WF8B_BPALCD33_SHIFT 0
+#define LCD_WF8B_BPALCD32_MASK 0x1u
+#define LCD_WF8B_BPALCD32_SHIFT 0
+#define LCD_WF8B_BPALCD31_MASK 0x1u
+#define LCD_WF8B_BPALCD31_SHIFT 0
+#define LCD_WF8B_BPALCD30_MASK 0x1u
+#define LCD_WF8B_BPALCD30_SHIFT 0
+#define LCD_WF8B_BPALCD29_MASK 0x1u
+#define LCD_WF8B_BPALCD29_SHIFT 0
+#define LCD_WF8B_BPALCD5_MASK 0x1u
+#define LCD_WF8B_BPALCD5_SHIFT 0
+#define LCD_WF8B_BPALCD28_MASK 0x1u
+#define LCD_WF8B_BPALCD28_SHIFT 0
+#define LCD_WF8B_BPALCD27_MASK 0x1u
+#define LCD_WF8B_BPALCD27_SHIFT 0
+#define LCD_WF8B_BPALCD26_MASK 0x1u
+#define LCD_WF8B_BPALCD26_SHIFT 0
+#define LCD_WF8B_BPALCD25_MASK 0x1u
+#define LCD_WF8B_BPALCD25_SHIFT 0
+#define LCD_WF8B_BPALCD24_MASK 0x1u
+#define LCD_WF8B_BPALCD24_SHIFT 0
+#define LCD_WF8B_BPALCD23_MASK 0x1u
+#define LCD_WF8B_BPALCD23_SHIFT 0
+#define LCD_WF8B_BPALCD22_MASK 0x1u
+#define LCD_WF8B_BPALCD22_SHIFT 0
+#define LCD_WF8B_BPALCD6_MASK 0x1u
+#define LCD_WF8B_BPALCD6_SHIFT 0
+#define LCD_WF8B_BPALCD21_MASK 0x1u
+#define LCD_WF8B_BPALCD21_SHIFT 0
+#define LCD_WF8B_BPALCD20_MASK 0x1u
+#define LCD_WF8B_BPALCD20_SHIFT 0
+#define LCD_WF8B_BPALCD19_MASK 0x1u
+#define LCD_WF8B_BPALCD19_SHIFT 0
+#define LCD_WF8B_BPALCD18_MASK 0x1u
+#define LCD_WF8B_BPALCD18_SHIFT 0
+#define LCD_WF8B_BPALCD17_MASK 0x1u
+#define LCD_WF8B_BPALCD17_SHIFT 0
+#define LCD_WF8B_BPALCD16_MASK 0x1u
+#define LCD_WF8B_BPALCD16_SHIFT 0
+#define LCD_WF8B_BPALCD15_MASK 0x1u
+#define LCD_WF8B_BPALCD15_SHIFT 0
+#define LCD_WF8B_BPALCD7_MASK 0x1u
+#define LCD_WF8B_BPALCD7_SHIFT 0
+#define LCD_WF8B_BPALCD14_MASK 0x1u
+#define LCD_WF8B_BPALCD14_SHIFT 0
+#define LCD_WF8B_BPALCD13_MASK 0x1u
+#define LCD_WF8B_BPALCD13_SHIFT 0
+#define LCD_WF8B_BPALCD12_MASK 0x1u
+#define LCD_WF8B_BPALCD12_SHIFT 0
+#define LCD_WF8B_BPALCD11_MASK 0x1u
+#define LCD_WF8B_BPALCD11_SHIFT 0
+#define LCD_WF8B_BPALCD10_MASK 0x1u
+#define LCD_WF8B_BPALCD10_SHIFT 0
+#define LCD_WF8B_BPALCD9_MASK 0x1u
+#define LCD_WF8B_BPALCD9_SHIFT 0
+#define LCD_WF8B_BPALCD8_MASK 0x1u
+#define LCD_WF8B_BPALCD8_SHIFT 0
+#define LCD_WF8B_BPBLCD1_MASK 0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT 1
+#define LCD_WF8B_BPBLCD32_MASK 0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT 1
+#define LCD_WF8B_BPBLCD30_MASK 0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT 1
+#define LCD_WF8B_BPBLCD60_MASK 0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT 1
+#define LCD_WF8B_BPBLCD24_MASK 0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT 1
+#define LCD_WF8B_BPBLCD28_MASK 0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT 1
+#define LCD_WF8B_BPBLCD23_MASK 0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT 1
+#define LCD_WF8B_BPBLCD48_MASK 0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT 1
+#define LCD_WF8B_BPBLCD10_MASK 0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT 1
+#define LCD_WF8B_BPBLCD15_MASK 0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT 1
+#define LCD_WF8B_BPBLCD36_MASK 0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT 1
+#define LCD_WF8B_BPBLCD44_MASK 0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT 1
+#define LCD_WF8B_BPBLCD62_MASK 0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT 1
+#define LCD_WF8B_BPBLCD53_MASK 0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT 1
+#define LCD_WF8B_BPBLCD22_MASK 0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT 1
+#define LCD_WF8B_BPBLCD47_MASK 0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT 1
+#define LCD_WF8B_BPBLCD33_MASK 0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT 1
+#define LCD_WF8B_BPBLCD2_MASK 0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT 1
+#define LCD_WF8B_BPBLCD49_MASK 0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT 1
+#define LCD_WF8B_BPBLCD0_MASK 0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT 1
+#define LCD_WF8B_BPBLCD55_MASK 0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT 1
+#define LCD_WF8B_BPBLCD56_MASK 0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT 1
+#define LCD_WF8B_BPBLCD21_MASK 0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT 1
+#define LCD_WF8B_BPBLCD6_MASK 0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT 1
+#define LCD_WF8B_BPBLCD29_MASK 0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT 1
+#define LCD_WF8B_BPBLCD25_MASK 0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT 1
+#define LCD_WF8B_BPBLCD8_MASK 0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT 1
+#define LCD_WF8B_BPBLCD54_MASK 0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT 1
+#define LCD_WF8B_BPBLCD38_MASK 0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT 1
+#define LCD_WF8B_BPBLCD43_MASK 0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT 1
+#define LCD_WF8B_BPBLCD20_MASK 0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT 1
+#define LCD_WF8B_BPBLCD9_MASK 0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT 1
+#define LCD_WF8B_BPBLCD7_MASK 0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT 1
+#define LCD_WF8B_BPBLCD50_MASK 0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT 1
+#define LCD_WF8B_BPBLCD40_MASK 0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT 1
+#define LCD_WF8B_BPBLCD63_MASK 0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT 1
+#define LCD_WF8B_BPBLCD26_MASK 0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT 1
+#define LCD_WF8B_BPBLCD12_MASK 0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT 1
+#define LCD_WF8B_BPBLCD19_MASK 0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT 1
+#define LCD_WF8B_BPBLCD34_MASK 0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT 1
+#define LCD_WF8B_BPBLCD39_MASK 0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT 1
+#define LCD_WF8B_BPBLCD59_MASK 0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT 1
+#define LCD_WF8B_BPBLCD61_MASK 0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT 1
+#define LCD_WF8B_BPBLCD37_MASK 0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT 1
+#define LCD_WF8B_BPBLCD31_MASK 0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT 1
+#define LCD_WF8B_BPBLCD58_MASK 0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT 1
+#define LCD_WF8B_BPBLCD18_MASK 0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT 1
+#define LCD_WF8B_BPBLCD45_MASK 0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT 1
+#define LCD_WF8B_BPBLCD27_MASK 0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT 1
+#define LCD_WF8B_BPBLCD14_MASK 0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT 1
+#define LCD_WF8B_BPBLCD51_MASK 0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT 1
+#define LCD_WF8B_BPBLCD52_MASK 0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT 1
+#define LCD_WF8B_BPBLCD4_MASK 0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT 1
+#define LCD_WF8B_BPBLCD35_MASK 0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT 1
+#define LCD_WF8B_BPBLCD17_MASK 0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT 1
+#define LCD_WF8B_BPBLCD41_MASK 0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT 1
+#define LCD_WF8B_BPBLCD11_MASK 0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT 1
+#define LCD_WF8B_BPBLCD46_MASK 0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT 1
+#define LCD_WF8B_BPBLCD57_MASK 0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT 1
+#define LCD_WF8B_BPBLCD42_MASK 0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT 1
+#define LCD_WF8B_BPBLCD5_MASK 0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT 1
+#define LCD_WF8B_BPBLCD3_MASK 0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT 1
+#define LCD_WF8B_BPBLCD16_MASK 0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT 1
+#define LCD_WF8B_BPBLCD13_MASK 0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT 1
+#define LCD_WF8B_BPCLCD10_MASK 0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT 2
+#define LCD_WF8B_BPCLCD55_MASK 0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT 2
+#define LCD_WF8B_BPCLCD2_MASK 0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT 2
+#define LCD_WF8B_BPCLCD23_MASK 0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT 2
+#define LCD_WF8B_BPCLCD48_MASK 0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT 2
+#define LCD_WF8B_BPCLCD24_MASK 0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT 2
+#define LCD_WF8B_BPCLCD60_MASK 0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT 2
+#define LCD_WF8B_BPCLCD47_MASK 0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT 2
+#define LCD_WF8B_BPCLCD22_MASK 0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT 2
+#define LCD_WF8B_BPCLCD8_MASK 0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT 2
+#define LCD_WF8B_BPCLCD21_MASK 0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT 2
+#define LCD_WF8B_BPCLCD49_MASK 0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT 2
+#define LCD_WF8B_BPCLCD25_MASK 0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT 2
+#define LCD_WF8B_BPCLCD1_MASK 0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT 2
+#define LCD_WF8B_BPCLCD20_MASK 0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT 2
+#define LCD_WF8B_BPCLCD50_MASK 0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT 2
+#define LCD_WF8B_BPCLCD19_MASK 0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT 2
+#define LCD_WF8B_BPCLCD26_MASK 0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT 2
+#define LCD_WF8B_BPCLCD59_MASK 0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT 2
+#define LCD_WF8B_BPCLCD61_MASK 0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT 2
+#define LCD_WF8B_BPCLCD46_MASK 0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT 2
+#define LCD_WF8B_BPCLCD18_MASK 0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT 2
+#define LCD_WF8B_BPCLCD5_MASK 0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT 2
+#define LCD_WF8B_BPCLCD63_MASK 0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT 2
+#define LCD_WF8B_BPCLCD27_MASK 0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT 2
+#define LCD_WF8B_BPCLCD17_MASK 0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT 2
+#define LCD_WF8B_BPCLCD51_MASK 0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT 2
+#define LCD_WF8B_BPCLCD9_MASK 0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT 2
+#define LCD_WF8B_BPCLCD54_MASK 0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT 2
+#define LCD_WF8B_BPCLCD15_MASK 0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT 2
+#define LCD_WF8B_BPCLCD16_MASK 0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT 2
+#define LCD_WF8B_BPCLCD14_MASK 0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT 2
+#define LCD_WF8B_BPCLCD32_MASK 0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT 2
+#define LCD_WF8B_BPCLCD28_MASK 0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT 2
+#define LCD_WF8B_BPCLCD53_MASK 0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT 2
+#define LCD_WF8B_BPCLCD33_MASK 0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT 2
+#define LCD_WF8B_BPCLCD0_MASK 0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT 2
+#define LCD_WF8B_BPCLCD43_MASK 0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT 2
+#define LCD_WF8B_BPCLCD7_MASK 0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT 2
+#define LCD_WF8B_BPCLCD4_MASK 0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT 2
+#define LCD_WF8B_BPCLCD34_MASK 0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT 2
+#define LCD_WF8B_BPCLCD29_MASK 0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT 2
+#define LCD_WF8B_BPCLCD45_MASK 0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT 2
+#define LCD_WF8B_BPCLCD57_MASK 0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT 2
+#define LCD_WF8B_BPCLCD42_MASK 0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT 2
+#define LCD_WF8B_BPCLCD35_MASK 0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT 2
+#define LCD_WF8B_BPCLCD13_MASK 0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT 2
+#define LCD_WF8B_BPCLCD36_MASK 0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT 2
+#define LCD_WF8B_BPCLCD30_MASK 0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT 2
+#define LCD_WF8B_BPCLCD52_MASK 0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT 2
+#define LCD_WF8B_BPCLCD58_MASK 0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT 2
+#define LCD_WF8B_BPCLCD41_MASK 0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT 2
+#define LCD_WF8B_BPCLCD37_MASK 0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT 2
+#define LCD_WF8B_BPCLCD3_MASK 0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT 2
+#define LCD_WF8B_BPCLCD12_MASK 0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT 2
+#define LCD_WF8B_BPCLCD11_MASK 0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT 2
+#define LCD_WF8B_BPCLCD38_MASK 0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT 2
+#define LCD_WF8B_BPCLCD44_MASK 0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT 2
+#define LCD_WF8B_BPCLCD31_MASK 0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT 2
+#define LCD_WF8B_BPCLCD40_MASK 0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT 2
+#define LCD_WF8B_BPCLCD62_MASK 0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT 2
+#define LCD_WF8B_BPCLCD56_MASK 0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT 2
+#define LCD_WF8B_BPCLCD39_MASK 0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT 2
+#define LCD_WF8B_BPCLCD6_MASK 0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT 2
+#define LCD_WF8B_BPDLCD47_MASK 0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT 3
+#define LCD_WF8B_BPDLCD23_MASK 0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT 3
+#define LCD_WF8B_BPDLCD48_MASK 0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT 3
+#define LCD_WF8B_BPDLCD24_MASK 0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT 3
+#define LCD_WF8B_BPDLCD15_MASK 0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT 3
+#define LCD_WF8B_BPDLCD22_MASK 0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT 3
+#define LCD_WF8B_BPDLCD60_MASK 0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT 3
+#define LCD_WF8B_BPDLCD10_MASK 0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT 3
+#define LCD_WF8B_BPDLCD21_MASK 0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT 3
+#define LCD_WF8B_BPDLCD49_MASK 0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT 3
+#define LCD_WF8B_BPDLCD1_MASK 0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT 3
+#define LCD_WF8B_BPDLCD25_MASK 0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT 3
+#define LCD_WF8B_BPDLCD20_MASK 0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT 3
+#define LCD_WF8B_BPDLCD2_MASK 0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT 3
+#define LCD_WF8B_BPDLCD55_MASK 0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT 3
+#define LCD_WF8B_BPDLCD59_MASK 0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT 3
+#define LCD_WF8B_BPDLCD5_MASK 0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT 3
+#define LCD_WF8B_BPDLCD19_MASK 0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT 3
+#define LCD_WF8B_BPDLCD6_MASK 0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT 3
+#define LCD_WF8B_BPDLCD26_MASK 0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT 3
+#define LCD_WF8B_BPDLCD0_MASK 0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT 3
+#define LCD_WF8B_BPDLCD50_MASK 0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT 3
+#define LCD_WF8B_BPDLCD46_MASK 0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT 3
+#define LCD_WF8B_BPDLCD18_MASK 0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT 3
+#define LCD_WF8B_BPDLCD61_MASK 0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT 3
+#define LCD_WF8B_BPDLCD9_MASK 0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT 3
+#define LCD_WF8B_BPDLCD17_MASK 0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT 3
+#define LCD_WF8B_BPDLCD27_MASK 0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT 3
+#define LCD_WF8B_BPDLCD53_MASK 0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT 3
+#define LCD_WF8B_BPDLCD51_MASK 0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT 3
+#define LCD_WF8B_BPDLCD54_MASK 0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT 3
+#define LCD_WF8B_BPDLCD13_MASK 0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT 3
+#define LCD_WF8B_BPDLCD16_MASK 0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT 3
+#define LCD_WF8B_BPDLCD32_MASK 0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT 3
+#define LCD_WF8B_BPDLCD14_MASK 0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT 3
+#define LCD_WF8B_BPDLCD28_MASK 0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT 3
+#define LCD_WF8B_BPDLCD43_MASK 0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT 3
+#define LCD_WF8B_BPDLCD4_MASK 0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT 3
+#define LCD_WF8B_BPDLCD45_MASK 0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT 3
+#define LCD_WF8B_BPDLCD8_MASK 0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT 3
+#define LCD_WF8B_BPDLCD62_MASK 0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT 3
+#define LCD_WF8B_BPDLCD33_MASK 0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT 3
+#define LCD_WF8B_BPDLCD34_MASK 0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT 3
+#define LCD_WF8B_BPDLCD29_MASK 0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT 3
+#define LCD_WF8B_BPDLCD58_MASK 0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT 3
+#define LCD_WF8B_BPDLCD57_MASK 0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT 3
+#define LCD_WF8B_BPDLCD42_MASK 0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT 3
+#define LCD_WF8B_BPDLCD35_MASK 0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT 3
+#define LCD_WF8B_BPDLCD52_MASK 0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT 3
+#define LCD_WF8B_BPDLCD7_MASK 0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT 3
+#define LCD_WF8B_BPDLCD36_MASK 0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT 3
+#define LCD_WF8B_BPDLCD30_MASK 0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT 3
+#define LCD_WF8B_BPDLCD41_MASK 0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT 3
+#define LCD_WF8B_BPDLCD37_MASK 0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT 3
+#define LCD_WF8B_BPDLCD44_MASK 0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT 3
+#define LCD_WF8B_BPDLCD63_MASK 0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT 3
+#define LCD_WF8B_BPDLCD38_MASK 0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT 3
+#define LCD_WF8B_BPDLCD56_MASK 0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT 3
+#define LCD_WF8B_BPDLCD40_MASK 0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT 3
+#define LCD_WF8B_BPDLCD31_MASK 0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT 3
+#define LCD_WF8B_BPDLCD12_MASK 0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT 3
+#define LCD_WF8B_BPDLCD39_MASK 0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT 3
+#define LCD_WF8B_BPDLCD3_MASK 0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT 3
+#define LCD_WF8B_BPDLCD11_MASK 0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT 3
+#define LCD_WF8B_BPELCD12_MASK 0x10u
+#define LCD_WF8B_BPELCD12_SHIFT 4
+#define LCD_WF8B_BPELCD39_MASK 0x10u
+#define LCD_WF8B_BPELCD39_SHIFT 4
+#define LCD_WF8B_BPELCD3_MASK 0x10u
+#define LCD_WF8B_BPELCD3_SHIFT 4
+#define LCD_WF8B_BPELCD38_MASK 0x10u
+#define LCD_WF8B_BPELCD38_SHIFT 4
+#define LCD_WF8B_BPELCD40_MASK 0x10u
+#define LCD_WF8B_BPELCD40_SHIFT 4
+#define LCD_WF8B_BPELCD37_MASK 0x10u
+#define LCD_WF8B_BPELCD37_SHIFT 4
+#define LCD_WF8B_BPELCD41_MASK 0x10u
+#define LCD_WF8B_BPELCD41_SHIFT 4
+#define LCD_WF8B_BPELCD36_MASK 0x10u
+#define LCD_WF8B_BPELCD36_SHIFT 4
+#define LCD_WF8B_BPELCD8_MASK 0x10u
+#define LCD_WF8B_BPELCD8_SHIFT 4
+#define LCD_WF8B_BPELCD35_MASK 0x10u
+#define LCD_WF8B_BPELCD35_SHIFT 4
+#define LCD_WF8B_BPELCD42_MASK 0x10u
+#define LCD_WF8B_BPELCD42_SHIFT 4
+#define LCD_WF8B_BPELCD34_MASK 0x10u
+#define LCD_WF8B_BPELCD34_SHIFT 4
+#define LCD_WF8B_BPELCD33_MASK 0x10u
+#define LCD_WF8B_BPELCD33_SHIFT 4
+#define LCD_WF8B_BPELCD11_MASK 0x10u
+#define LCD_WF8B_BPELCD11_SHIFT 4
+#define LCD_WF8B_BPELCD43_MASK 0x10u
+#define LCD_WF8B_BPELCD43_SHIFT 4
+#define LCD_WF8B_BPELCD32_MASK 0x10u
+#define LCD_WF8B_BPELCD32_SHIFT 4
+#define LCD_WF8B_BPELCD31_MASK 0x10u
+#define LCD_WF8B_BPELCD31_SHIFT 4
+#define LCD_WF8B_BPELCD44_MASK 0x10u
+#define LCD_WF8B_BPELCD44_SHIFT 4
+#define LCD_WF8B_BPELCD30_MASK 0x10u
+#define LCD_WF8B_BPELCD30_SHIFT 4
+#define LCD_WF8B_BPELCD29_MASK 0x10u
+#define LCD_WF8B_BPELCD29_SHIFT 4
+#define LCD_WF8B_BPELCD7_MASK 0x10u
+#define LCD_WF8B_BPELCD7_SHIFT 4
+#define LCD_WF8B_BPELCD45_MASK 0x10u
+#define LCD_WF8B_BPELCD45_SHIFT 4
+#define LCD_WF8B_BPELCD28_MASK 0x10u
+#define LCD_WF8B_BPELCD28_SHIFT 4
+#define LCD_WF8B_BPELCD2_MASK 0x10u
+#define LCD_WF8B_BPELCD2_SHIFT 4
+#define LCD_WF8B_BPELCD27_MASK 0x10u
+#define LCD_WF8B_BPELCD27_SHIFT 4
+#define LCD_WF8B_BPELCD46_MASK 0x10u
+#define LCD_WF8B_BPELCD46_SHIFT 4
+#define LCD_WF8B_BPELCD26_MASK 0x10u
+#define LCD_WF8B_BPELCD26_SHIFT 4
+#define LCD_WF8B_BPELCD10_MASK 0x10u
+#define LCD_WF8B_BPELCD10_SHIFT 4
+#define LCD_WF8B_BPELCD13_MASK 0x10u
+#define LCD_WF8B_BPELCD13_SHIFT 4
+#define LCD_WF8B_BPELCD25_MASK 0x10u
+#define LCD_WF8B_BPELCD25_SHIFT 4
+#define LCD_WF8B_BPELCD5_MASK 0x10u
+#define LCD_WF8B_BPELCD5_SHIFT 4
+#define LCD_WF8B_BPELCD24_MASK 0x10u
+#define LCD_WF8B_BPELCD24_SHIFT 4
+#define LCD_WF8B_BPELCD47_MASK 0x10u
+#define LCD_WF8B_BPELCD47_SHIFT 4
+#define LCD_WF8B_BPELCD23_MASK 0x10u
+#define LCD_WF8B_BPELCD23_SHIFT 4
+#define LCD_WF8B_BPELCD22_MASK 0x10u
+#define LCD_WF8B_BPELCD22_SHIFT 4
+#define LCD_WF8B_BPELCD48_MASK 0x10u
+#define LCD_WF8B_BPELCD48_SHIFT 4
+#define LCD_WF8B_BPELCD21_MASK 0x10u
+#define LCD_WF8B_BPELCD21_SHIFT 4
+#define LCD_WF8B_BPELCD49_MASK 0x10u
+#define LCD_WF8B_BPELCD49_SHIFT 4
+#define LCD_WF8B_BPELCD20_MASK 0x10u
+#define LCD_WF8B_BPELCD20_SHIFT 4
+#define LCD_WF8B_BPELCD19_MASK 0x10u
+#define LCD_WF8B_BPELCD19_SHIFT 4
+#define LCD_WF8B_BPELCD9_MASK 0x10u
+#define LCD_WF8B_BPELCD9_SHIFT 4
+#define LCD_WF8B_BPELCD50_MASK 0x10u
+#define LCD_WF8B_BPELCD50_SHIFT 4
+#define LCD_WF8B_BPELCD18_MASK 0x10u
+#define LCD_WF8B_BPELCD18_SHIFT 4
+#define LCD_WF8B_BPELCD6_MASK 0x10u
+#define LCD_WF8B_BPELCD6_SHIFT 4
+#define LCD_WF8B_BPELCD17_MASK 0x10u
+#define LCD_WF8B_BPELCD17_SHIFT 4
+#define LCD_WF8B_BPELCD51_MASK 0x10u
+#define LCD_WF8B_BPELCD51_SHIFT 4
+#define LCD_WF8B_BPELCD16_MASK 0x10u
+#define LCD_WF8B_BPELCD16_SHIFT 4
+#define LCD_WF8B_BPELCD56_MASK 0x10u
+#define LCD_WF8B_BPELCD56_SHIFT 4
+#define LCD_WF8B_BPELCD57_MASK 0x10u
+#define LCD_WF8B_BPELCD57_SHIFT 4
+#define LCD_WF8B_BPELCD52_MASK 0x10u
+#define LCD_WF8B_BPELCD52_SHIFT 4
+#define LCD_WF8B_BPELCD1_MASK 0x10u
+#define LCD_WF8B_BPELCD1_SHIFT 4
+#define LCD_WF8B_BPELCD58_MASK 0x10u
+#define LCD_WF8B_BPELCD58_SHIFT 4
+#define LCD_WF8B_BPELCD59_MASK 0x10u
+#define LCD_WF8B_BPELCD59_SHIFT 4
+#define LCD_WF8B_BPELCD53_MASK 0x10u
+#define LCD_WF8B_BPELCD53_SHIFT 4
+#define LCD_WF8B_BPELCD14_MASK 0x10u
+#define LCD_WF8B_BPELCD14_SHIFT 4
+#define LCD_WF8B_BPELCD0_MASK 0x10u
+#define LCD_WF8B_BPELCD0_SHIFT 4
+#define LCD_WF8B_BPELCD60_MASK 0x10u
+#define LCD_WF8B_BPELCD60_SHIFT 4
+#define LCD_WF8B_BPELCD15_MASK 0x10u
+#define LCD_WF8B_BPELCD15_SHIFT 4
+#define LCD_WF8B_BPELCD61_MASK 0x10u
+#define LCD_WF8B_BPELCD61_SHIFT 4
+#define LCD_WF8B_BPELCD54_MASK 0x10u
+#define LCD_WF8B_BPELCD54_SHIFT 4
+#define LCD_WF8B_BPELCD62_MASK 0x10u
+#define LCD_WF8B_BPELCD62_SHIFT 4
+#define LCD_WF8B_BPELCD63_MASK 0x10u
+#define LCD_WF8B_BPELCD63_SHIFT 4
+#define LCD_WF8B_BPELCD55_MASK 0x10u
+#define LCD_WF8B_BPELCD55_SHIFT 4
+#define LCD_WF8B_BPELCD4_MASK 0x10u
+#define LCD_WF8B_BPELCD4_SHIFT 4
+#define LCD_WF8B_BPFLCD13_MASK 0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT 5
+#define LCD_WF8B_BPFLCD39_MASK 0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT 5
+#define LCD_WF8B_BPFLCD55_MASK 0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT 5
+#define LCD_WF8B_BPFLCD47_MASK 0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT 5
+#define LCD_WF8B_BPFLCD63_MASK 0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT 5
+#define LCD_WF8B_BPFLCD43_MASK 0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT 5
+#define LCD_WF8B_BPFLCD5_MASK 0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT 5
+#define LCD_WF8B_BPFLCD62_MASK 0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT 5
+#define LCD_WF8B_BPFLCD14_MASK 0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT 5
+#define LCD_WF8B_BPFLCD24_MASK 0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT 5
+#define LCD_WF8B_BPFLCD54_MASK 0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT 5
+#define LCD_WF8B_BPFLCD15_MASK 0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT 5
+#define LCD_WF8B_BPFLCD32_MASK 0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT 5
+#define LCD_WF8B_BPFLCD61_MASK 0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT 5
+#define LCD_WF8B_BPFLCD25_MASK 0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT 5
+#define LCD_WF8B_BPFLCD60_MASK 0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT 5
+#define LCD_WF8B_BPFLCD41_MASK 0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT 5
+#define LCD_WF8B_BPFLCD33_MASK 0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT 5
+#define LCD_WF8B_BPFLCD53_MASK 0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT 5
+#define LCD_WF8B_BPFLCD59_MASK 0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT 5
+#define LCD_WF8B_BPFLCD0_MASK 0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT 5
+#define LCD_WF8B_BPFLCD46_MASK 0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT 5
+#define LCD_WF8B_BPFLCD58_MASK 0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT 5
+#define LCD_WF8B_BPFLCD26_MASK 0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT 5
+#define LCD_WF8B_BPFLCD36_MASK 0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT 5
+#define LCD_WF8B_BPFLCD10_MASK 0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT 5
+#define LCD_WF8B_BPFLCD52_MASK 0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT 5
+#define LCD_WF8B_BPFLCD57_MASK 0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT 5
+#define LCD_WF8B_BPFLCD27_MASK 0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT 5
+#define LCD_WF8B_BPFLCD11_MASK 0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT 5
+#define LCD_WF8B_BPFLCD56_MASK 0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT 5
+#define LCD_WF8B_BPFLCD1_MASK 0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT 5
+#define LCD_WF8B_BPFLCD8_MASK 0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT 5
+#define LCD_WF8B_BPFLCD40_MASK 0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT 5
+#define LCD_WF8B_BPFLCD51_MASK 0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT 5
+#define LCD_WF8B_BPFLCD16_MASK 0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT 5
+#define LCD_WF8B_BPFLCD45_MASK 0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT 5
+#define LCD_WF8B_BPFLCD6_MASK 0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT 5
+#define LCD_WF8B_BPFLCD17_MASK 0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT 5
+#define LCD_WF8B_BPFLCD28_MASK 0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT 5
+#define LCD_WF8B_BPFLCD42_MASK 0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT 5
+#define LCD_WF8B_BPFLCD29_MASK 0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT 5
+#define LCD_WF8B_BPFLCD50_MASK 0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT 5
+#define LCD_WF8B_BPFLCD18_MASK 0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT 5
+#define LCD_WF8B_BPFLCD34_MASK 0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT 5
+#define LCD_WF8B_BPFLCD19_MASK 0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT 5
+#define LCD_WF8B_BPFLCD2_MASK 0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT 5
+#define LCD_WF8B_BPFLCD9_MASK 0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT 5
+#define LCD_WF8B_BPFLCD3_MASK 0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT 5
+#define LCD_WF8B_BPFLCD37_MASK 0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT 5
+#define LCD_WF8B_BPFLCD49_MASK 0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT 5
+#define LCD_WF8B_BPFLCD20_MASK 0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT 5
+#define LCD_WF8B_BPFLCD44_MASK 0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT 5
+#define LCD_WF8B_BPFLCD30_MASK 0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT 5
+#define LCD_WF8B_BPFLCD21_MASK 0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT 5
+#define LCD_WF8B_BPFLCD35_MASK 0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT 5
+#define LCD_WF8B_BPFLCD4_MASK 0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT 5
+#define LCD_WF8B_BPFLCD31_MASK 0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT 5
+#define LCD_WF8B_BPFLCD48_MASK 0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT 5
+#define LCD_WF8B_BPFLCD7_MASK 0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT 5
+#define LCD_WF8B_BPFLCD22_MASK 0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT 5
+#define LCD_WF8B_BPFLCD38_MASK 0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT 5
+#define LCD_WF8B_BPFLCD12_MASK 0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT 5
+#define LCD_WF8B_BPFLCD23_MASK 0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT 5
+#define LCD_WF8B_BPGLCD14_MASK 0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT 6
+#define LCD_WF8B_BPGLCD55_MASK 0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT 6
+#define LCD_WF8B_BPGLCD63_MASK 0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT 6
+#define LCD_WF8B_BPGLCD15_MASK 0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT 6
+#define LCD_WF8B_BPGLCD62_MASK 0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT 6
+#define LCD_WF8B_BPGLCD54_MASK 0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT 6
+#define LCD_WF8B_BPGLCD61_MASK 0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT 6
+#define LCD_WF8B_BPGLCD60_MASK 0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT 6
+#define LCD_WF8B_BPGLCD59_MASK 0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT 6
+#define LCD_WF8B_BPGLCD53_MASK 0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT 6
+#define LCD_WF8B_BPGLCD58_MASK 0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT 6
+#define LCD_WF8B_BPGLCD0_MASK 0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT 6
+#define LCD_WF8B_BPGLCD57_MASK 0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT 6
+#define LCD_WF8B_BPGLCD52_MASK 0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT 6
+#define LCD_WF8B_BPGLCD7_MASK 0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT 6
+#define LCD_WF8B_BPGLCD56_MASK 0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT 6
+#define LCD_WF8B_BPGLCD6_MASK 0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT 6
+#define LCD_WF8B_BPGLCD51_MASK 0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT 6
+#define LCD_WF8B_BPGLCD16_MASK 0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT 6
+#define LCD_WF8B_BPGLCD1_MASK 0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT 6
+#define LCD_WF8B_BPGLCD17_MASK 0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT 6
+#define LCD_WF8B_BPGLCD50_MASK 0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT 6
+#define LCD_WF8B_BPGLCD18_MASK 0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT 6
+#define LCD_WF8B_BPGLCD19_MASK 0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT 6
+#define LCD_WF8B_BPGLCD8_MASK 0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT 6
+#define LCD_WF8B_BPGLCD49_MASK 0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT 6
+#define LCD_WF8B_BPGLCD20_MASK 0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT 6
+#define LCD_WF8B_BPGLCD9_MASK 0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT 6
+#define LCD_WF8B_BPGLCD21_MASK 0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT 6
+#define LCD_WF8B_BPGLCD13_MASK 0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT 6
+#define LCD_WF8B_BPGLCD48_MASK 0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT 6
+#define LCD_WF8B_BPGLCD22_MASK 0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT 6
+#define LCD_WF8B_BPGLCD5_MASK 0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT 6
+#define LCD_WF8B_BPGLCD47_MASK 0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT 6
+#define LCD_WF8B_BPGLCD23_MASK 0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT 6
+#define LCD_WF8B_BPGLCD24_MASK 0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT 6
+#define LCD_WF8B_BPGLCD25_MASK 0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT 6
+#define LCD_WF8B_BPGLCD46_MASK 0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT 6
+#define LCD_WF8B_BPGLCD26_MASK 0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT 6
+#define LCD_WF8B_BPGLCD27_MASK 0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT 6
+#define LCD_WF8B_BPGLCD10_MASK 0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT 6
+#define LCD_WF8B_BPGLCD45_MASK 0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT 6
+#define LCD_WF8B_BPGLCD28_MASK 0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT 6
+#define LCD_WF8B_BPGLCD29_MASK 0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT 6
+#define LCD_WF8B_BPGLCD4_MASK 0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT 6
+#define LCD_WF8B_BPGLCD44_MASK 0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT 6
+#define LCD_WF8B_BPGLCD30_MASK 0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT 6
+#define LCD_WF8B_BPGLCD2_MASK 0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT 6
+#define LCD_WF8B_BPGLCD31_MASK 0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT 6
+#define LCD_WF8B_BPGLCD43_MASK 0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT 6
+#define LCD_WF8B_BPGLCD32_MASK 0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT 6
+#define LCD_WF8B_BPGLCD33_MASK 0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT 6
+#define LCD_WF8B_BPGLCD42_MASK 0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT 6
+#define LCD_WF8B_BPGLCD34_MASK 0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT 6
+#define LCD_WF8B_BPGLCD11_MASK 0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT 6
+#define LCD_WF8B_BPGLCD35_MASK 0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT 6
+#define LCD_WF8B_BPGLCD12_MASK 0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT 6
+#define LCD_WF8B_BPGLCD41_MASK 0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT 6
+#define LCD_WF8B_BPGLCD36_MASK 0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT 6
+#define LCD_WF8B_BPGLCD3_MASK 0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT 6
+#define LCD_WF8B_BPGLCD37_MASK 0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT 6
+#define LCD_WF8B_BPGLCD40_MASK 0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT 6
+#define LCD_WF8B_BPGLCD38_MASK 0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT 6
+#define LCD_WF8B_BPGLCD39_MASK 0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT 6
+#define LCD_WF8B_BPHLCD63_MASK 0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT 7
+#define LCD_WF8B_BPHLCD62_MASK 0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT 7
+#define LCD_WF8B_BPHLCD61_MASK 0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT 7
+#define LCD_WF8B_BPHLCD60_MASK 0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT 7
+#define LCD_WF8B_BPHLCD59_MASK 0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT 7
+#define LCD_WF8B_BPHLCD58_MASK 0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT 7
+#define LCD_WF8B_BPHLCD57_MASK 0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT 7
+#define LCD_WF8B_BPHLCD0_MASK 0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT 7
+#define LCD_WF8B_BPHLCD56_MASK 0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT 7
+#define LCD_WF8B_BPHLCD55_MASK 0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT 7
+#define LCD_WF8B_BPHLCD54_MASK 0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT 7
+#define LCD_WF8B_BPHLCD53_MASK 0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT 7
+#define LCD_WF8B_BPHLCD52_MASK 0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT 7
+#define LCD_WF8B_BPHLCD51_MASK 0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT 7
+#define LCD_WF8B_BPHLCD50_MASK 0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT 7
+#define LCD_WF8B_BPHLCD1_MASK 0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT 7
+#define LCD_WF8B_BPHLCD49_MASK 0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT 7
+#define LCD_WF8B_BPHLCD48_MASK 0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT 7
+#define LCD_WF8B_BPHLCD47_MASK 0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT 7
+#define LCD_WF8B_BPHLCD46_MASK 0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT 7
+#define LCD_WF8B_BPHLCD45_MASK 0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT 7
+#define LCD_WF8B_BPHLCD44_MASK 0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT 7
+#define LCD_WF8B_BPHLCD43_MASK 0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT 7
+#define LCD_WF8B_BPHLCD2_MASK 0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT 7
+#define LCD_WF8B_BPHLCD42_MASK 0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT 7
+#define LCD_WF8B_BPHLCD41_MASK 0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT 7
+#define LCD_WF8B_BPHLCD40_MASK 0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT 7
+#define LCD_WF8B_BPHLCD39_MASK 0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT 7
+#define LCD_WF8B_BPHLCD38_MASK 0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT 7
+#define LCD_WF8B_BPHLCD37_MASK 0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT 7
+#define LCD_WF8B_BPHLCD36_MASK 0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT 7
+#define LCD_WF8B_BPHLCD3_MASK 0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT 7
+#define LCD_WF8B_BPHLCD35_MASK 0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT 7
+#define LCD_WF8B_BPHLCD34_MASK 0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT 7
+#define LCD_WF8B_BPHLCD33_MASK 0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT 7
+#define LCD_WF8B_BPHLCD32_MASK 0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT 7
+#define LCD_WF8B_BPHLCD31_MASK 0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT 7
+#define LCD_WF8B_BPHLCD30_MASK 0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT 7
+#define LCD_WF8B_BPHLCD29_MASK 0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT 7
+#define LCD_WF8B_BPHLCD4_MASK 0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT 7
+#define LCD_WF8B_BPHLCD28_MASK 0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT 7
+#define LCD_WF8B_BPHLCD27_MASK 0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT 7
+#define LCD_WF8B_BPHLCD26_MASK 0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT 7
+#define LCD_WF8B_BPHLCD25_MASK 0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT 7
+#define LCD_WF8B_BPHLCD24_MASK 0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT 7
+#define LCD_WF8B_BPHLCD23_MASK 0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT 7
+#define LCD_WF8B_BPHLCD22_MASK 0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT 7
+#define LCD_WF8B_BPHLCD5_MASK 0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT 7
+#define LCD_WF8B_BPHLCD21_MASK 0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT 7
+#define LCD_WF8B_BPHLCD20_MASK 0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT 7
+#define LCD_WF8B_BPHLCD19_MASK 0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT 7
+#define LCD_WF8B_BPHLCD18_MASK 0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT 7
+#define LCD_WF8B_BPHLCD17_MASK 0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT 7
+#define LCD_WF8B_BPHLCD16_MASK 0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT 7
+#define LCD_WF8B_BPHLCD15_MASK 0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT 7
+#define LCD_WF8B_BPHLCD6_MASK 0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT 7
+#define LCD_WF8B_BPHLCD14_MASK 0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT 7
+#define LCD_WF8B_BPHLCD13_MASK 0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT 7
+#define LCD_WF8B_BPHLCD12_MASK 0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT 7
+#define LCD_WF8B_BPHLCD11_MASK 0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT 7
+#define LCD_WF8B_BPHLCD10_MASK 0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT 7
+#define LCD_WF8B_BPHLCD9_MASK 0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT 7
+#define LCD_WF8B_BPHLCD8_MASK 0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT 7
+#define LCD_WF8B_BPHLCD7_MASK 0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASES { LCD }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS_MASK 0x80u
+#define MCG_S_LOLS_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+#define SIM_SOPT5_UART1ODE_MASK 0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+#define SIM_SCGC5_SLCD_MASK 0x80000u
+#define SIM_SCGC5_SLCD_SHIFT 19
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __I uint8_t S; /**< SPI status register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK 0x1u
+#define SPI_S_RFIFOEF_SHIFT 0
+#define SPI_S_TXFULLF_MASK 0x2u
+#define SPI_S_TXFULLF_SHIFT 1
+#define SPI_S_TNEAREF_MASK 0x4u
+#define SPI_S_TNEAREF_SHIFT 2
+#define SPI_S_RNFULLF_MASK 0x8u
+#define SPI_S_RNFULLF_SHIFT 3
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPIMODE_MASK 0x40u
+#define SPI_C2_SPIMODE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK 0xFFu
+#define SPI_ML_Bits_SHIFT 0
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK 0xFFu
+#define SPI_MH_Bits_SHIFT 0
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK 0xFFu
+#define SPI_DL_Bits_SHIFT 0
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK 0xFFu
+#define SPI_DH_Bits_SHIFT 0
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK 0x1u
+#define SPI_CI_SPRFCI_SHIFT 0
+#define SPI_CI_SPTEFCI_MASK 0x2u
+#define SPI_CI_SPTEFCI_SHIFT 1
+#define SPI_CI_RNFULLFCI_MASK 0x4u
+#define SPI_CI_RNFULLFCI_SHIFT 2
+#define SPI_CI_TNEAREFCI_MASK 0x8u
+#define SPI_CI_TNEAREFCI_SHIFT 3
+#define SPI_CI_RXFOF_MASK 0x10u
+#define SPI_CI_RXFOF_SHIFT 4
+#define SPI_CI_TXFOF_MASK 0x20u
+#define SPI_CI_TXFOF_SHIFT 5
+#define SPI_CI_RXFERR_MASK 0x40u
+#define SPI_CI_RXFERR_SHIFT 6
+#define SPI_CI_TXFERR_MASK 0x80u
+#define SPI_CI_TXFERR_SHIFT 7
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK 0x1u
+#define SPI_C3_FIFOMODE_SHIFT 0
+#define SPI_C3_RNFULLIEN_MASK 0x2u
+#define SPI_C3_RNFULLIEN_SHIFT 1
+#define SPI_C3_TNEARIEN_MASK 0x4u
+#define SPI_C3_TNEARIEN_SHIFT 2
+#define SPI_C3_INTCLR_MASK 0x8u
+#define SPI_C3_INTCLR_SHIFT 3
+#define SPI_C3_RNFULLF_MARK_MASK 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT 4
+#define SPI_C3_TNEAREF_MARK_MASK 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1 }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1, TPM2 }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK 0x1u
+#define UART_D_R0T0_SHIFT 0
+#define UART_D_R1T1_MASK 0x2u
+#define UART_D_R1T1_SHIFT 1
+#define UART_D_R2T2_MASK 0x4u
+#define UART_D_R2T2_SHIFT 2
+#define UART_D_R3T3_MASK 0x8u
+#define UART_D_R3T3_SHIFT 3
+#define UART_D_R4T4_MASK 0x10u
+#define UART_D_R4T4_SHIFT 4
+#define UART_D_R5T5_MASK 0x20u
+#define UART_D_R5T5_SHIFT 5
+#define UART_D_R6T6_MASK 0x40u
+#define UART_D_R6T6_SHIFT 6
+#define UART_D_R7T7_MASK 0x80u
+#define UART_D_R7T7_SHIFT 7
+/* C4 Bit Fields */
+#define UART_C4_RDMAS_MASK 0x20u
+#define UART_C4_RDMAS_SHIFT 5
+#define UART_C4_TDMAS_MASK 0x80u
+#define UART_C4_TDMAS_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART1, UART2 }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART0_BDH_SBR_MASK 0x1Fu
+#define UART0_BDH_SBR_SHIFT 0
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK 0x20u
+#define UART0_BDH_SBNS_SHIFT 5
+#define UART0_BDH_RXEDGIE_MASK 0x40u
+#define UART0_BDH_RXEDGIE_SHIFT 6
+#define UART0_BDH_LBKDIE_MASK 0x80u
+#define UART0_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART0_BDL_SBR_MASK 0xFFu
+#define UART0_BDL_SBR_SHIFT 0
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART0_C1_PT_MASK 0x1u
+#define UART0_C1_PT_SHIFT 0
+#define UART0_C1_PE_MASK 0x2u
+#define UART0_C1_PE_SHIFT 1
+#define UART0_C1_ILT_MASK 0x4u
+#define UART0_C1_ILT_SHIFT 2
+#define UART0_C1_WAKE_MASK 0x8u
+#define UART0_C1_WAKE_SHIFT 3
+#define UART0_C1_M_MASK 0x10u
+#define UART0_C1_M_SHIFT 4
+#define UART0_C1_RSRC_MASK 0x20u
+#define UART0_C1_RSRC_SHIFT 5
+#define UART0_C1_DOZEEN_MASK 0x40u
+#define UART0_C1_DOZEEN_SHIFT 6
+#define UART0_C1_LOOPS_MASK 0x80u
+#define UART0_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART0_C2_SBK_MASK 0x1u
+#define UART0_C2_SBK_SHIFT 0
+#define UART0_C2_RWU_MASK 0x2u
+#define UART0_C2_RWU_SHIFT 1
+#define UART0_C2_RE_MASK 0x4u
+#define UART0_C2_RE_SHIFT 2
+#define UART0_C2_TE_MASK 0x8u
+#define UART0_C2_TE_SHIFT 3
+#define UART0_C2_ILIE_MASK 0x10u
+#define UART0_C2_ILIE_SHIFT 4
+#define UART0_C2_RIE_MASK 0x20u
+#define UART0_C2_RIE_SHIFT 5
+#define UART0_C2_TCIE_MASK 0x40u
+#define UART0_C2_TCIE_SHIFT 6
+#define UART0_C2_TIE_MASK 0x80u
+#define UART0_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART0_S1_PF_MASK 0x1u
+#define UART0_S1_PF_SHIFT 0
+#define UART0_S1_FE_MASK 0x2u
+#define UART0_S1_FE_SHIFT 1
+#define UART0_S1_NF_MASK 0x4u
+#define UART0_S1_NF_SHIFT 2
+#define UART0_S1_OR_MASK 0x8u
+#define UART0_S1_OR_SHIFT 3
+#define UART0_S1_IDLE_MASK 0x10u
+#define UART0_S1_IDLE_SHIFT 4
+#define UART0_S1_RDRF_MASK 0x20u
+#define UART0_S1_RDRF_SHIFT 5
+#define UART0_S1_TC_MASK 0x40u
+#define UART0_S1_TC_SHIFT 6
+#define UART0_S1_TDRE_MASK 0x80u
+#define UART0_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART0_S2_RAF_MASK 0x1u
+#define UART0_S2_RAF_SHIFT 0
+#define UART0_S2_LBKDE_MASK 0x2u
+#define UART0_S2_LBKDE_SHIFT 1
+#define UART0_S2_BRK13_MASK 0x4u
+#define UART0_S2_BRK13_SHIFT 2
+#define UART0_S2_RWUID_MASK 0x8u
+#define UART0_S2_RWUID_SHIFT 3
+#define UART0_S2_RXINV_MASK 0x10u
+#define UART0_S2_RXINV_SHIFT 4
+#define UART0_S2_MSBF_MASK 0x20u
+#define UART0_S2_MSBF_SHIFT 5
+#define UART0_S2_RXEDGIF_MASK 0x40u
+#define UART0_S2_RXEDGIF_SHIFT 6
+#define UART0_S2_LBKDIF_MASK 0x80u
+#define UART0_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART0_C3_PEIE_MASK 0x1u
+#define UART0_C3_PEIE_SHIFT 0
+#define UART0_C3_FEIE_MASK 0x2u
+#define UART0_C3_FEIE_SHIFT 1
+#define UART0_C3_NEIE_MASK 0x4u
+#define UART0_C3_NEIE_SHIFT 2
+#define UART0_C3_ORIE_MASK 0x8u
+#define UART0_C3_ORIE_SHIFT 3
+#define UART0_C3_TXINV_MASK 0x10u
+#define UART0_C3_TXINV_SHIFT 4
+#define UART0_C3_TXDIR_MASK 0x20u
+#define UART0_C3_TXDIR_SHIFT 5
+#define UART0_C3_R9T8_MASK 0x40u
+#define UART0_C3_R9T8_SHIFT 6
+#define UART0_C3_R8T9_MASK 0x80u
+#define UART0_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UART0_D_R0T0_MASK 0x1u
+#define UART0_D_R0T0_SHIFT 0
+#define UART0_D_R1T1_MASK 0x2u
+#define UART0_D_R1T1_SHIFT 1
+#define UART0_D_R2T2_MASK 0x4u
+#define UART0_D_R2T2_SHIFT 2
+#define UART0_D_R3T3_MASK 0x8u
+#define UART0_D_R3T3_SHIFT 3
+#define UART0_D_R4T4_MASK 0x10u
+#define UART0_D_R4T4_SHIFT 4
+#define UART0_D_R5T5_MASK 0x20u
+#define UART0_D_R5T5_SHIFT 5
+#define UART0_D_R6T6_MASK 0x40u
+#define UART0_D_R6T6_SHIFT 6
+#define UART0_D_R7T7_MASK 0x80u
+#define UART0_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UART0_MA1_MA_MASK 0xFFu
+#define UART0_MA1_MA_SHIFT 0
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART0_MA2_MA_MASK 0xFFu
+#define UART0_MA2_MA_SHIFT 0
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART0_C4_OSR_MASK 0x1Fu
+#define UART0_C4_OSR_SHIFT 0
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK 0x20u
+#define UART0_C4_M10_SHIFT 5
+#define UART0_C4_MAEN2_MASK 0x40u
+#define UART0_C4_MAEN2_SHIFT 6
+#define UART0_C4_MAEN1_MASK 0x80u
+#define UART0_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART0_C5_RESYNCDIS_MASK 0x1u
+#define UART0_C5_RESYNCDIS_SHIFT 0
+#define UART0_C5_BOTHEDGE_MASK 0x2u
+#define UART0_C5_BOTHEDGE_SHIFT 1
+#define UART0_C5_RDMAE_MASK 0x20u
+#define UART0_C5_RDMAE_SHIFT 5
+#define UART0_C5_TDMAE_MASK 0x80u
+#define UART0_C5_TDMAE_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASES { UART0 }
+
+/*!
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL46Z4_H_) */
+
+/* MKL46Z4.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
new file mode 100644
index 000000000..82ddfb878
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x8000 - 0xC0 = 0x7F40
+ RW_IRAM1 0x1FFFE0C0 0x7F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
new file mode 100644
index 000000000..b690a22a6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL46Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL46Z4
+; * @version: 2.0
+; * @date: 2012-12-12
+; *
+; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20006000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD I2S0_IRQHandler ; I2S0 transmit interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD LCD_IRQHandler ; Segment LCD Interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld
new file mode 100644
index 000000000..6f20f3212
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL46Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
new file mode 100644
index 000000000..5d5eae6e5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
@@ -0,0 +1,241 @@
+/* KL46Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long I2S_IRQHandler /* I2S transmit interrupt */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long LCD_IRQHandler /* Segment LCD Interrupt*/
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler I2S_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf
new file mode 100644
index 000000000..673f212eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0002ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0bf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0c0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20005fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s
new file mode 100644
index 000000000..618226746
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s
@@ -0,0 +1,217 @@
+/**************************************************
+ *
+ * Copyright 2010 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD 0 ; Reserved
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD I2S0_IRQHandler ; I2S0 transmit interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD LCD_IRQHandler ; Segment LCD Interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK Reserved20_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK TPM2_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h
new file mode 100644
index 000000000..553b60775
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL46Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c
new file mode 100644
index 000000000..077924407
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c
new file mode 100644
index 000000000..8a15912ac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c
@@ -0,0 +1,269 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+** Version: rev. 2.0, 2012-12-12
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL46Z4
+ * @version 2.0
+ * @date 2012-12-12
+ * @brief Device specific configuration file for MKL46Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL46Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 13.98MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 24MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06U;
+ /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
+ /* MCG->C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ MCG->C5 = (uint8_t)0x01U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1AU;
+ while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+ MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h
new file mode 100644
index 000000000..e88304711
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h
@@ -0,0 +1,90 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+** Version: rev. 2.0, 2012-12-12
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL46Z4
+ * @version 2.0
+ * @date 2012-12-12
+ * @brief Device specific configuration file for MKL46Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL46Z4_H_
+#define SYSTEM_MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL46Z4_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h
new file mode 100644
index 000000000..28a78cedc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h
@@ -0,0 +1,14420 @@
+/*
+** ###################################################################
+** Processors: MK64FN1M0VDC12
+** MK64FN1M0VLL12
+** MK64FN1M0VLQ12
+** MK64FN1M0VMD12
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.5, 2014-02-10
+** Build: b140604
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK64F12
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** - rev. 2.5 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.5
+ * @date 2014-02-10
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_) /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
+ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
+ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
+ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
+ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
+ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
+ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
+ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
+ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
+ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
+ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
+ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
+ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
+ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
+ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
+ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
+ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ CMT_IRQn = 45, /**< CMT interrupt */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ USBDCD_IRQn = 54, /**< USBDCD Interrupt */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTimer_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ SPI2_IRQn = 65, /**< SPI2 Interrupt */
+ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
+ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
+ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
+ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
+ CMP2_IRQn = 70, /**< CMP2 interrupt */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ I2C2_IRQn = 74, /**< I2C2 interrupt */
+ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
+ SDHC_IRQn = 81, /**< SDHC interrupt */
+ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
+ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
+ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK64F12.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
+#define ADC1_RA ADC_R_REG(ADC1,0)
+#define ADC1_RB ADC_R_REG(ADC1,1)
+#define ADC1_CV1 ADC_CV1_REG(ADC1)
+#define ADC1_CV2 ADC_CV2_REG(ADC1)
+#define ADC1_SC2 ADC_SC2_REG(ADC1)
+#define ADC1_SC3 ADC_SC3_REG(ADC1)
+#define ADC1_OFS ADC_OFS_REG(ADC1)
+#define ADC1_PG ADC_PG_REG(ADC1)
+#define ADC1_MG ADC_MG_REG(ADC1)
+#define ADC1_CLPD ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+#define ADC1_R(index) ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
+ __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
+ __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
+ __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
+ __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
+ __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
+ __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
+ __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
+ __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
+ __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
+ __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
+ __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
+ __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
+ __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
+ __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base) ((base)->MPRA)
+#define AIPS_PACRA_REG(base) ((base)->PACRA)
+#define AIPS_PACRB_REG(base) ((base)->PACRB)
+#define AIPS_PACRC_REG(base) ((base)->PACRC)
+#define AIPS_PACRD_REG(base) ((base)->PACRD)
+#define AIPS_PACRE_REG(base) ((base)->PACRE)
+#define AIPS_PACRF_REG(base) ((base)->PACRF)
+#define AIPS_PACRG_REG(base) ((base)->PACRG)
+#define AIPS_PACRH_REG(base) ((base)->PACRH)
+#define AIPS_PACRI_REG(base) ((base)->PACRI)
+#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
+#define AIPS_PACRK_REG(base) ((base)->PACRK)
+#define AIPS_PACRL_REG(base) ((base)->PACRL)
+#define AIPS_PACRM_REG(base) ((base)->PACRM)
+#define AIPS_PACRN_REG(base) ((base)->PACRN)
+#define AIPS_PACRO_REG(base) ((base)->PACRO)
+#define AIPS_PACRP_REG(base) ((base)->PACRP)
+#define AIPS_PACRU_REG(base) ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK 0x100u
+#define AIPS_MPRA_MPL5_SHIFT 8
+#define AIPS_MPRA_MTW5_MASK 0x200u
+#define AIPS_MPRA_MTW5_SHIFT 9
+#define AIPS_MPRA_MTR5_MASK 0x400u
+#define AIPS_MPRA_MTR5_SHIFT 10
+#define AIPS_MPRA_MPL4_MASK 0x1000u
+#define AIPS_MPRA_MPL4_SHIFT 12
+#define AIPS_MPRA_MTW4_MASK 0x2000u
+#define AIPS_MPRA_MTW4_SHIFT 13
+#define AIPS_MPRA_MTR4_MASK 0x4000u
+#define AIPS_MPRA_MTR4_SHIFT 14
+#define AIPS_MPRA_MPL3_MASK 0x10000u
+#define AIPS_MPRA_MPL3_SHIFT 16
+#define AIPS_MPRA_MTW3_MASK 0x20000u
+#define AIPS_MPRA_MTW3_SHIFT 17
+#define AIPS_MPRA_MTR3_MASK 0x40000u
+#define AIPS_MPRA_MTR3_SHIFT 18
+#define AIPS_MPRA_MPL2_MASK 0x100000u
+#define AIPS_MPRA_MPL2_SHIFT 20
+#define AIPS_MPRA_MTW2_MASK 0x200000u
+#define AIPS_MPRA_MTW2_SHIFT 21
+#define AIPS_MPRA_MTR2_MASK 0x400000u
+#define AIPS_MPRA_MTR2_SHIFT 22
+#define AIPS_MPRA_MPL1_MASK 0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT 24
+#define AIPS_MPRA_MTW1_MASK 0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT 25
+#define AIPS_MPRA_MTR1_MASK 0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT 26
+#define AIPS_MPRA_MPL0_MASK 0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT 28
+#define AIPS_MPRA_MTW0_MASK 0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT 29
+#define AIPS_MPRA_MTR0_MASK 0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT 30
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK 0x1u
+#define AIPS_PACRA_TP7_SHIFT 0
+#define AIPS_PACRA_WP7_MASK 0x2u
+#define AIPS_PACRA_WP7_SHIFT 1
+#define AIPS_PACRA_SP7_MASK 0x4u
+#define AIPS_PACRA_SP7_SHIFT 2
+#define AIPS_PACRA_TP6_MASK 0x10u
+#define AIPS_PACRA_TP6_SHIFT 4
+#define AIPS_PACRA_WP6_MASK 0x20u
+#define AIPS_PACRA_WP6_SHIFT 5
+#define AIPS_PACRA_SP6_MASK 0x40u
+#define AIPS_PACRA_SP6_SHIFT 6
+#define AIPS_PACRA_TP5_MASK 0x100u
+#define AIPS_PACRA_TP5_SHIFT 8
+#define AIPS_PACRA_WP5_MASK 0x200u
+#define AIPS_PACRA_WP5_SHIFT 9
+#define AIPS_PACRA_SP5_MASK 0x400u
+#define AIPS_PACRA_SP5_SHIFT 10
+#define AIPS_PACRA_TP4_MASK 0x1000u
+#define AIPS_PACRA_TP4_SHIFT 12
+#define AIPS_PACRA_WP4_MASK 0x2000u
+#define AIPS_PACRA_WP4_SHIFT 13
+#define AIPS_PACRA_SP4_MASK 0x4000u
+#define AIPS_PACRA_SP4_SHIFT 14
+#define AIPS_PACRA_TP3_MASK 0x10000u
+#define AIPS_PACRA_TP3_SHIFT 16
+#define AIPS_PACRA_WP3_MASK 0x20000u
+#define AIPS_PACRA_WP3_SHIFT 17
+#define AIPS_PACRA_SP3_MASK 0x40000u
+#define AIPS_PACRA_SP3_SHIFT 18
+#define AIPS_PACRA_TP2_MASK 0x100000u
+#define AIPS_PACRA_TP2_SHIFT 20
+#define AIPS_PACRA_WP2_MASK 0x200000u
+#define AIPS_PACRA_WP2_SHIFT 21
+#define AIPS_PACRA_SP2_MASK 0x400000u
+#define AIPS_PACRA_SP2_SHIFT 22
+#define AIPS_PACRA_TP1_MASK 0x1000000u
+#define AIPS_PACRA_TP1_SHIFT 24
+#define AIPS_PACRA_WP1_MASK 0x2000000u
+#define AIPS_PACRA_WP1_SHIFT 25
+#define AIPS_PACRA_SP1_MASK 0x4000000u
+#define AIPS_PACRA_SP1_SHIFT 26
+#define AIPS_PACRA_TP0_MASK 0x10000000u
+#define AIPS_PACRA_TP0_SHIFT 28
+#define AIPS_PACRA_WP0_MASK 0x20000000u
+#define AIPS_PACRA_WP0_SHIFT 29
+#define AIPS_PACRA_SP0_MASK 0x40000000u
+#define AIPS_PACRA_SP0_SHIFT 30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK 0x1u
+#define AIPS_PACRB_TP7_SHIFT 0
+#define AIPS_PACRB_WP7_MASK 0x2u
+#define AIPS_PACRB_WP7_SHIFT 1
+#define AIPS_PACRB_SP7_MASK 0x4u
+#define AIPS_PACRB_SP7_SHIFT 2
+#define AIPS_PACRB_TP6_MASK 0x10u
+#define AIPS_PACRB_TP6_SHIFT 4
+#define AIPS_PACRB_WP6_MASK 0x20u
+#define AIPS_PACRB_WP6_SHIFT 5
+#define AIPS_PACRB_SP6_MASK 0x40u
+#define AIPS_PACRB_SP6_SHIFT 6
+#define AIPS_PACRB_TP5_MASK 0x100u
+#define AIPS_PACRB_TP5_SHIFT 8
+#define AIPS_PACRB_WP5_MASK 0x200u
+#define AIPS_PACRB_WP5_SHIFT 9
+#define AIPS_PACRB_SP5_MASK 0x400u
+#define AIPS_PACRB_SP5_SHIFT 10
+#define AIPS_PACRB_TP4_MASK 0x1000u
+#define AIPS_PACRB_TP4_SHIFT 12
+#define AIPS_PACRB_WP4_MASK 0x2000u
+#define AIPS_PACRB_WP4_SHIFT 13
+#define AIPS_PACRB_SP4_MASK 0x4000u
+#define AIPS_PACRB_SP4_SHIFT 14
+#define AIPS_PACRB_TP3_MASK 0x10000u
+#define AIPS_PACRB_TP3_SHIFT 16
+#define AIPS_PACRB_WP3_MASK 0x20000u
+#define AIPS_PACRB_WP3_SHIFT 17
+#define AIPS_PACRB_SP3_MASK 0x40000u
+#define AIPS_PACRB_SP3_SHIFT 18
+#define AIPS_PACRB_TP2_MASK 0x100000u
+#define AIPS_PACRB_TP2_SHIFT 20
+#define AIPS_PACRB_WP2_MASK 0x200000u
+#define AIPS_PACRB_WP2_SHIFT 21
+#define AIPS_PACRB_SP2_MASK 0x400000u
+#define AIPS_PACRB_SP2_SHIFT 22
+#define AIPS_PACRB_TP1_MASK 0x1000000u
+#define AIPS_PACRB_TP1_SHIFT 24
+#define AIPS_PACRB_WP1_MASK 0x2000000u
+#define AIPS_PACRB_WP1_SHIFT 25
+#define AIPS_PACRB_SP1_MASK 0x4000000u
+#define AIPS_PACRB_SP1_SHIFT 26
+#define AIPS_PACRB_TP0_MASK 0x10000000u
+#define AIPS_PACRB_TP0_SHIFT 28
+#define AIPS_PACRB_WP0_MASK 0x20000000u
+#define AIPS_PACRB_WP0_SHIFT 29
+#define AIPS_PACRB_SP0_MASK 0x40000000u
+#define AIPS_PACRB_SP0_SHIFT 30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK 0x1u
+#define AIPS_PACRC_TP7_SHIFT 0
+#define AIPS_PACRC_WP7_MASK 0x2u
+#define AIPS_PACRC_WP7_SHIFT 1
+#define AIPS_PACRC_SP7_MASK 0x4u
+#define AIPS_PACRC_SP7_SHIFT 2
+#define AIPS_PACRC_TP6_MASK 0x10u
+#define AIPS_PACRC_TP6_SHIFT 4
+#define AIPS_PACRC_WP6_MASK 0x20u
+#define AIPS_PACRC_WP6_SHIFT 5
+#define AIPS_PACRC_SP6_MASK 0x40u
+#define AIPS_PACRC_SP6_SHIFT 6
+#define AIPS_PACRC_TP5_MASK 0x100u
+#define AIPS_PACRC_TP5_SHIFT 8
+#define AIPS_PACRC_WP5_MASK 0x200u
+#define AIPS_PACRC_WP5_SHIFT 9
+#define AIPS_PACRC_SP5_MASK 0x400u
+#define AIPS_PACRC_SP5_SHIFT 10
+#define AIPS_PACRC_TP4_MASK 0x1000u
+#define AIPS_PACRC_TP4_SHIFT 12
+#define AIPS_PACRC_WP4_MASK 0x2000u
+#define AIPS_PACRC_WP4_SHIFT 13
+#define AIPS_PACRC_SP4_MASK 0x4000u
+#define AIPS_PACRC_SP4_SHIFT 14
+#define AIPS_PACRC_TP3_MASK 0x10000u
+#define AIPS_PACRC_TP3_SHIFT 16
+#define AIPS_PACRC_WP3_MASK 0x20000u
+#define AIPS_PACRC_WP3_SHIFT 17
+#define AIPS_PACRC_SP3_MASK 0x40000u
+#define AIPS_PACRC_SP3_SHIFT 18
+#define AIPS_PACRC_TP2_MASK 0x100000u
+#define AIPS_PACRC_TP2_SHIFT 20
+#define AIPS_PACRC_WP2_MASK 0x200000u
+#define AIPS_PACRC_WP2_SHIFT 21
+#define AIPS_PACRC_SP2_MASK 0x400000u
+#define AIPS_PACRC_SP2_SHIFT 22
+#define AIPS_PACRC_TP1_MASK 0x1000000u
+#define AIPS_PACRC_TP1_SHIFT 24
+#define AIPS_PACRC_WP1_MASK 0x2000000u
+#define AIPS_PACRC_WP1_SHIFT 25
+#define AIPS_PACRC_SP1_MASK 0x4000000u
+#define AIPS_PACRC_SP1_SHIFT 26
+#define AIPS_PACRC_TP0_MASK 0x10000000u
+#define AIPS_PACRC_TP0_SHIFT 28
+#define AIPS_PACRC_WP0_MASK 0x20000000u
+#define AIPS_PACRC_WP0_SHIFT 29
+#define AIPS_PACRC_SP0_MASK 0x40000000u
+#define AIPS_PACRC_SP0_SHIFT 30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK 0x1u
+#define AIPS_PACRD_TP7_SHIFT 0
+#define AIPS_PACRD_WP7_MASK 0x2u
+#define AIPS_PACRD_WP7_SHIFT 1
+#define AIPS_PACRD_SP7_MASK 0x4u
+#define AIPS_PACRD_SP7_SHIFT 2
+#define AIPS_PACRD_TP6_MASK 0x10u
+#define AIPS_PACRD_TP6_SHIFT 4
+#define AIPS_PACRD_WP6_MASK 0x20u
+#define AIPS_PACRD_WP6_SHIFT 5
+#define AIPS_PACRD_SP6_MASK 0x40u
+#define AIPS_PACRD_SP6_SHIFT 6
+#define AIPS_PACRD_TP5_MASK 0x100u
+#define AIPS_PACRD_TP5_SHIFT 8
+#define AIPS_PACRD_WP5_MASK 0x200u
+#define AIPS_PACRD_WP5_SHIFT 9
+#define AIPS_PACRD_SP5_MASK 0x400u
+#define AIPS_PACRD_SP5_SHIFT 10
+#define AIPS_PACRD_TP4_MASK 0x1000u
+#define AIPS_PACRD_TP4_SHIFT 12
+#define AIPS_PACRD_WP4_MASK 0x2000u
+#define AIPS_PACRD_WP4_SHIFT 13
+#define AIPS_PACRD_SP4_MASK 0x4000u
+#define AIPS_PACRD_SP4_SHIFT 14
+#define AIPS_PACRD_TP3_MASK 0x10000u
+#define AIPS_PACRD_TP3_SHIFT 16
+#define AIPS_PACRD_WP3_MASK 0x20000u
+#define AIPS_PACRD_WP3_SHIFT 17
+#define AIPS_PACRD_SP3_MASK 0x40000u
+#define AIPS_PACRD_SP3_SHIFT 18
+#define AIPS_PACRD_TP2_MASK 0x100000u
+#define AIPS_PACRD_TP2_SHIFT 20
+#define AIPS_PACRD_WP2_MASK 0x200000u
+#define AIPS_PACRD_WP2_SHIFT 21
+#define AIPS_PACRD_SP2_MASK 0x400000u
+#define AIPS_PACRD_SP2_SHIFT 22
+#define AIPS_PACRD_TP1_MASK 0x1000000u
+#define AIPS_PACRD_TP1_SHIFT 24
+#define AIPS_PACRD_WP1_MASK 0x2000000u
+#define AIPS_PACRD_WP1_SHIFT 25
+#define AIPS_PACRD_SP1_MASK 0x4000000u
+#define AIPS_PACRD_SP1_SHIFT 26
+#define AIPS_PACRD_TP0_MASK 0x10000000u
+#define AIPS_PACRD_TP0_SHIFT 28
+#define AIPS_PACRD_WP0_MASK 0x20000000u
+#define AIPS_PACRD_WP0_SHIFT 29
+#define AIPS_PACRD_SP0_MASK 0x40000000u
+#define AIPS_PACRD_SP0_SHIFT 30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK 0x1u
+#define AIPS_PACRE_TP7_SHIFT 0
+#define AIPS_PACRE_WP7_MASK 0x2u
+#define AIPS_PACRE_WP7_SHIFT 1
+#define AIPS_PACRE_SP7_MASK 0x4u
+#define AIPS_PACRE_SP7_SHIFT 2
+#define AIPS_PACRE_TP6_MASK 0x10u
+#define AIPS_PACRE_TP6_SHIFT 4
+#define AIPS_PACRE_WP6_MASK 0x20u
+#define AIPS_PACRE_WP6_SHIFT 5
+#define AIPS_PACRE_SP6_MASK 0x40u
+#define AIPS_PACRE_SP6_SHIFT 6
+#define AIPS_PACRE_TP5_MASK 0x100u
+#define AIPS_PACRE_TP5_SHIFT 8
+#define AIPS_PACRE_WP5_MASK 0x200u
+#define AIPS_PACRE_WP5_SHIFT 9
+#define AIPS_PACRE_SP5_MASK 0x400u
+#define AIPS_PACRE_SP5_SHIFT 10
+#define AIPS_PACRE_TP4_MASK 0x1000u
+#define AIPS_PACRE_TP4_SHIFT 12
+#define AIPS_PACRE_WP4_MASK 0x2000u
+#define AIPS_PACRE_WP4_SHIFT 13
+#define AIPS_PACRE_SP4_MASK 0x4000u
+#define AIPS_PACRE_SP4_SHIFT 14
+#define AIPS_PACRE_TP3_MASK 0x10000u
+#define AIPS_PACRE_TP3_SHIFT 16
+#define AIPS_PACRE_WP3_MASK 0x20000u
+#define AIPS_PACRE_WP3_SHIFT 17
+#define AIPS_PACRE_SP3_MASK 0x40000u
+#define AIPS_PACRE_SP3_SHIFT 18
+#define AIPS_PACRE_TP2_MASK 0x100000u
+#define AIPS_PACRE_TP2_SHIFT 20
+#define AIPS_PACRE_WP2_MASK 0x200000u
+#define AIPS_PACRE_WP2_SHIFT 21
+#define AIPS_PACRE_SP2_MASK 0x400000u
+#define AIPS_PACRE_SP2_SHIFT 22
+#define AIPS_PACRE_TP1_MASK 0x1000000u
+#define AIPS_PACRE_TP1_SHIFT 24
+#define AIPS_PACRE_WP1_MASK 0x2000000u
+#define AIPS_PACRE_WP1_SHIFT 25
+#define AIPS_PACRE_SP1_MASK 0x4000000u
+#define AIPS_PACRE_SP1_SHIFT 26
+#define AIPS_PACRE_TP0_MASK 0x10000000u
+#define AIPS_PACRE_TP0_SHIFT 28
+#define AIPS_PACRE_WP0_MASK 0x20000000u
+#define AIPS_PACRE_WP0_SHIFT 29
+#define AIPS_PACRE_SP0_MASK 0x40000000u
+#define AIPS_PACRE_SP0_SHIFT 30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK 0x1u
+#define AIPS_PACRF_TP7_SHIFT 0
+#define AIPS_PACRF_WP7_MASK 0x2u
+#define AIPS_PACRF_WP7_SHIFT 1
+#define AIPS_PACRF_SP7_MASK 0x4u
+#define AIPS_PACRF_SP7_SHIFT 2
+#define AIPS_PACRF_TP6_MASK 0x10u
+#define AIPS_PACRF_TP6_SHIFT 4
+#define AIPS_PACRF_WP6_MASK 0x20u
+#define AIPS_PACRF_WP6_SHIFT 5
+#define AIPS_PACRF_SP6_MASK 0x40u
+#define AIPS_PACRF_SP6_SHIFT 6
+#define AIPS_PACRF_TP5_MASK 0x100u
+#define AIPS_PACRF_TP5_SHIFT 8
+#define AIPS_PACRF_WP5_MASK 0x200u
+#define AIPS_PACRF_WP5_SHIFT 9
+#define AIPS_PACRF_SP5_MASK 0x400u
+#define AIPS_PACRF_SP5_SHIFT 10
+#define AIPS_PACRF_TP4_MASK 0x1000u
+#define AIPS_PACRF_TP4_SHIFT 12
+#define AIPS_PACRF_WP4_MASK 0x2000u
+#define AIPS_PACRF_WP4_SHIFT 13
+#define AIPS_PACRF_SP4_MASK 0x4000u
+#define AIPS_PACRF_SP4_SHIFT 14
+#define AIPS_PACRF_TP3_MASK 0x10000u
+#define AIPS_PACRF_TP3_SHIFT 16
+#define AIPS_PACRF_WP3_MASK 0x20000u
+#define AIPS_PACRF_WP3_SHIFT 17
+#define AIPS_PACRF_SP3_MASK 0x40000u
+#define AIPS_PACRF_SP3_SHIFT 18
+#define AIPS_PACRF_TP2_MASK 0x100000u
+#define AIPS_PACRF_TP2_SHIFT 20
+#define AIPS_PACRF_WP2_MASK 0x200000u
+#define AIPS_PACRF_WP2_SHIFT 21
+#define AIPS_PACRF_SP2_MASK 0x400000u
+#define AIPS_PACRF_SP2_SHIFT 22
+#define AIPS_PACRF_TP1_MASK 0x1000000u
+#define AIPS_PACRF_TP1_SHIFT 24
+#define AIPS_PACRF_WP1_MASK 0x2000000u
+#define AIPS_PACRF_WP1_SHIFT 25
+#define AIPS_PACRF_SP1_MASK 0x4000000u
+#define AIPS_PACRF_SP1_SHIFT 26
+#define AIPS_PACRF_TP0_MASK 0x10000000u
+#define AIPS_PACRF_TP0_SHIFT 28
+#define AIPS_PACRF_WP0_MASK 0x20000000u
+#define AIPS_PACRF_WP0_SHIFT 29
+#define AIPS_PACRF_SP0_MASK 0x40000000u
+#define AIPS_PACRF_SP0_SHIFT 30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK 0x1u
+#define AIPS_PACRG_TP7_SHIFT 0
+#define AIPS_PACRG_WP7_MASK 0x2u
+#define AIPS_PACRG_WP7_SHIFT 1
+#define AIPS_PACRG_SP7_MASK 0x4u
+#define AIPS_PACRG_SP7_SHIFT 2
+#define AIPS_PACRG_TP6_MASK 0x10u
+#define AIPS_PACRG_TP6_SHIFT 4
+#define AIPS_PACRG_WP6_MASK 0x20u
+#define AIPS_PACRG_WP6_SHIFT 5
+#define AIPS_PACRG_SP6_MASK 0x40u
+#define AIPS_PACRG_SP6_SHIFT 6
+#define AIPS_PACRG_TP5_MASK 0x100u
+#define AIPS_PACRG_TP5_SHIFT 8
+#define AIPS_PACRG_WP5_MASK 0x200u
+#define AIPS_PACRG_WP5_SHIFT 9
+#define AIPS_PACRG_SP5_MASK 0x400u
+#define AIPS_PACRG_SP5_SHIFT 10
+#define AIPS_PACRG_TP4_MASK 0x1000u
+#define AIPS_PACRG_TP4_SHIFT 12
+#define AIPS_PACRG_WP4_MASK 0x2000u
+#define AIPS_PACRG_WP4_SHIFT 13
+#define AIPS_PACRG_SP4_MASK 0x4000u
+#define AIPS_PACRG_SP4_SHIFT 14
+#define AIPS_PACRG_TP3_MASK 0x10000u
+#define AIPS_PACRG_TP3_SHIFT 16
+#define AIPS_PACRG_WP3_MASK 0x20000u
+#define AIPS_PACRG_WP3_SHIFT 17
+#define AIPS_PACRG_SP3_MASK 0x40000u
+#define AIPS_PACRG_SP3_SHIFT 18
+#define AIPS_PACRG_TP2_MASK 0x100000u
+#define AIPS_PACRG_TP2_SHIFT 20
+#define AIPS_PACRG_WP2_MASK 0x200000u
+#define AIPS_PACRG_WP2_SHIFT 21
+#define AIPS_PACRG_SP2_MASK 0x400000u
+#define AIPS_PACRG_SP2_SHIFT 22
+#define AIPS_PACRG_TP1_MASK 0x1000000u
+#define AIPS_PACRG_TP1_SHIFT 24
+#define AIPS_PACRG_WP1_MASK 0x2000000u
+#define AIPS_PACRG_WP1_SHIFT 25
+#define AIPS_PACRG_SP1_MASK 0x4000000u
+#define AIPS_PACRG_SP1_SHIFT 26
+#define AIPS_PACRG_TP0_MASK 0x10000000u
+#define AIPS_PACRG_TP0_SHIFT 28
+#define AIPS_PACRG_WP0_MASK 0x20000000u
+#define AIPS_PACRG_WP0_SHIFT 29
+#define AIPS_PACRG_SP0_MASK 0x40000000u
+#define AIPS_PACRG_SP0_SHIFT 30
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK 0x1u
+#define AIPS_PACRH_TP7_SHIFT 0
+#define AIPS_PACRH_WP7_MASK 0x2u
+#define AIPS_PACRH_WP7_SHIFT 1
+#define AIPS_PACRH_SP7_MASK 0x4u
+#define AIPS_PACRH_SP7_SHIFT 2
+#define AIPS_PACRH_TP6_MASK 0x10u
+#define AIPS_PACRH_TP6_SHIFT 4
+#define AIPS_PACRH_WP6_MASK 0x20u
+#define AIPS_PACRH_WP6_SHIFT 5
+#define AIPS_PACRH_SP6_MASK 0x40u
+#define AIPS_PACRH_SP6_SHIFT 6
+#define AIPS_PACRH_TP5_MASK 0x100u
+#define AIPS_PACRH_TP5_SHIFT 8
+#define AIPS_PACRH_WP5_MASK 0x200u
+#define AIPS_PACRH_WP5_SHIFT 9
+#define AIPS_PACRH_SP5_MASK 0x400u
+#define AIPS_PACRH_SP5_SHIFT 10
+#define AIPS_PACRH_TP4_MASK 0x1000u
+#define AIPS_PACRH_TP4_SHIFT 12
+#define AIPS_PACRH_WP4_MASK 0x2000u
+#define AIPS_PACRH_WP4_SHIFT 13
+#define AIPS_PACRH_SP4_MASK 0x4000u
+#define AIPS_PACRH_SP4_SHIFT 14
+#define AIPS_PACRH_TP3_MASK 0x10000u
+#define AIPS_PACRH_TP3_SHIFT 16
+#define AIPS_PACRH_WP3_MASK 0x20000u
+#define AIPS_PACRH_WP3_SHIFT 17
+#define AIPS_PACRH_SP3_MASK 0x40000u
+#define AIPS_PACRH_SP3_SHIFT 18
+#define AIPS_PACRH_TP2_MASK 0x100000u
+#define AIPS_PACRH_TP2_SHIFT 20
+#define AIPS_PACRH_WP2_MASK 0x200000u
+#define AIPS_PACRH_WP2_SHIFT 21
+#define AIPS_PACRH_SP2_MASK 0x400000u
+#define AIPS_PACRH_SP2_SHIFT 22
+#define AIPS_PACRH_TP1_MASK 0x1000000u
+#define AIPS_PACRH_TP1_SHIFT 24
+#define AIPS_PACRH_WP1_MASK 0x2000000u
+#define AIPS_PACRH_WP1_SHIFT 25
+#define AIPS_PACRH_SP1_MASK 0x4000000u
+#define AIPS_PACRH_SP1_SHIFT 26
+#define AIPS_PACRH_TP0_MASK 0x10000000u
+#define AIPS_PACRH_TP0_SHIFT 28
+#define AIPS_PACRH_WP0_MASK 0x20000000u
+#define AIPS_PACRH_WP0_SHIFT 29
+#define AIPS_PACRH_SP0_MASK 0x40000000u
+#define AIPS_PACRH_SP0_SHIFT 30
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK 0x1u
+#define AIPS_PACRI_TP7_SHIFT 0
+#define AIPS_PACRI_WP7_MASK 0x2u
+#define AIPS_PACRI_WP7_SHIFT 1
+#define AIPS_PACRI_SP7_MASK 0x4u
+#define AIPS_PACRI_SP7_SHIFT 2
+#define AIPS_PACRI_TP6_MASK 0x10u
+#define AIPS_PACRI_TP6_SHIFT 4
+#define AIPS_PACRI_WP6_MASK 0x20u
+#define AIPS_PACRI_WP6_SHIFT 5
+#define AIPS_PACRI_SP6_MASK 0x40u
+#define AIPS_PACRI_SP6_SHIFT 6
+#define AIPS_PACRI_TP5_MASK 0x100u
+#define AIPS_PACRI_TP5_SHIFT 8
+#define AIPS_PACRI_WP5_MASK 0x200u
+#define AIPS_PACRI_WP5_SHIFT 9
+#define AIPS_PACRI_SP5_MASK 0x400u
+#define AIPS_PACRI_SP5_SHIFT 10
+#define AIPS_PACRI_TP4_MASK 0x1000u
+#define AIPS_PACRI_TP4_SHIFT 12
+#define AIPS_PACRI_WP4_MASK 0x2000u
+#define AIPS_PACRI_WP4_SHIFT 13
+#define AIPS_PACRI_SP4_MASK 0x4000u
+#define AIPS_PACRI_SP4_SHIFT 14
+#define AIPS_PACRI_TP3_MASK 0x10000u
+#define AIPS_PACRI_TP3_SHIFT 16
+#define AIPS_PACRI_WP3_MASK 0x20000u
+#define AIPS_PACRI_WP3_SHIFT 17
+#define AIPS_PACRI_SP3_MASK 0x40000u
+#define AIPS_PACRI_SP3_SHIFT 18
+#define AIPS_PACRI_TP2_MASK 0x100000u
+#define AIPS_PACRI_TP2_SHIFT 20
+#define AIPS_PACRI_WP2_MASK 0x200000u
+#define AIPS_PACRI_WP2_SHIFT 21
+#define AIPS_PACRI_SP2_MASK 0x400000u
+#define AIPS_PACRI_SP2_SHIFT 22
+#define AIPS_PACRI_TP1_MASK 0x1000000u
+#define AIPS_PACRI_TP1_SHIFT 24
+#define AIPS_PACRI_WP1_MASK 0x2000000u
+#define AIPS_PACRI_WP1_SHIFT 25
+#define AIPS_PACRI_SP1_MASK 0x4000000u
+#define AIPS_PACRI_SP1_SHIFT 26
+#define AIPS_PACRI_TP0_MASK 0x10000000u
+#define AIPS_PACRI_TP0_SHIFT 28
+#define AIPS_PACRI_WP0_MASK 0x20000000u
+#define AIPS_PACRI_WP0_SHIFT 29
+#define AIPS_PACRI_SP0_MASK 0x40000000u
+#define AIPS_PACRI_SP0_SHIFT 30
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK 0x1u
+#define AIPS_PACRJ_TP7_SHIFT 0
+#define AIPS_PACRJ_WP7_MASK 0x2u
+#define AIPS_PACRJ_WP7_SHIFT 1
+#define AIPS_PACRJ_SP7_MASK 0x4u
+#define AIPS_PACRJ_SP7_SHIFT 2
+#define AIPS_PACRJ_TP6_MASK 0x10u
+#define AIPS_PACRJ_TP6_SHIFT 4
+#define AIPS_PACRJ_WP6_MASK 0x20u
+#define AIPS_PACRJ_WP6_SHIFT 5
+#define AIPS_PACRJ_SP6_MASK 0x40u
+#define AIPS_PACRJ_SP6_SHIFT 6
+#define AIPS_PACRJ_TP5_MASK 0x100u
+#define AIPS_PACRJ_TP5_SHIFT 8
+#define AIPS_PACRJ_WP5_MASK 0x200u
+#define AIPS_PACRJ_WP5_SHIFT 9
+#define AIPS_PACRJ_SP5_MASK 0x400u
+#define AIPS_PACRJ_SP5_SHIFT 10
+#define AIPS_PACRJ_TP4_MASK 0x1000u
+#define AIPS_PACRJ_TP4_SHIFT 12
+#define AIPS_PACRJ_WP4_MASK 0x2000u
+#define AIPS_PACRJ_WP4_SHIFT 13
+#define AIPS_PACRJ_SP4_MASK 0x4000u
+#define AIPS_PACRJ_SP4_SHIFT 14
+#define AIPS_PACRJ_TP3_MASK 0x10000u
+#define AIPS_PACRJ_TP3_SHIFT 16
+#define AIPS_PACRJ_WP3_MASK 0x20000u
+#define AIPS_PACRJ_WP3_SHIFT 17
+#define AIPS_PACRJ_SP3_MASK 0x40000u
+#define AIPS_PACRJ_SP3_SHIFT 18
+#define AIPS_PACRJ_TP2_MASK 0x100000u
+#define AIPS_PACRJ_TP2_SHIFT 20
+#define AIPS_PACRJ_WP2_MASK 0x200000u
+#define AIPS_PACRJ_WP2_SHIFT 21
+#define AIPS_PACRJ_SP2_MASK 0x400000u
+#define AIPS_PACRJ_SP2_SHIFT 22
+#define AIPS_PACRJ_TP1_MASK 0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT 24
+#define AIPS_PACRJ_WP1_MASK 0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT 25
+#define AIPS_PACRJ_SP1_MASK 0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT 26
+#define AIPS_PACRJ_TP0_MASK 0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT 28
+#define AIPS_PACRJ_WP0_MASK 0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT 29
+#define AIPS_PACRJ_SP0_MASK 0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT 30
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK 0x1u
+#define AIPS_PACRK_TP7_SHIFT 0
+#define AIPS_PACRK_WP7_MASK 0x2u
+#define AIPS_PACRK_WP7_SHIFT 1
+#define AIPS_PACRK_SP7_MASK 0x4u
+#define AIPS_PACRK_SP7_SHIFT 2
+#define AIPS_PACRK_TP6_MASK 0x10u
+#define AIPS_PACRK_TP6_SHIFT 4
+#define AIPS_PACRK_WP6_MASK 0x20u
+#define AIPS_PACRK_WP6_SHIFT 5
+#define AIPS_PACRK_SP6_MASK 0x40u
+#define AIPS_PACRK_SP6_SHIFT 6
+#define AIPS_PACRK_TP5_MASK 0x100u
+#define AIPS_PACRK_TP5_SHIFT 8
+#define AIPS_PACRK_WP5_MASK 0x200u
+#define AIPS_PACRK_WP5_SHIFT 9
+#define AIPS_PACRK_SP5_MASK 0x400u
+#define AIPS_PACRK_SP5_SHIFT 10
+#define AIPS_PACRK_TP4_MASK 0x1000u
+#define AIPS_PACRK_TP4_SHIFT 12
+#define AIPS_PACRK_WP4_MASK 0x2000u
+#define AIPS_PACRK_WP4_SHIFT 13
+#define AIPS_PACRK_SP4_MASK 0x4000u
+#define AIPS_PACRK_SP4_SHIFT 14
+#define AIPS_PACRK_TP3_MASK 0x10000u
+#define AIPS_PACRK_TP3_SHIFT 16
+#define AIPS_PACRK_WP3_MASK 0x20000u
+#define AIPS_PACRK_WP3_SHIFT 17
+#define AIPS_PACRK_SP3_MASK 0x40000u
+#define AIPS_PACRK_SP3_SHIFT 18
+#define AIPS_PACRK_TP2_MASK 0x100000u
+#define AIPS_PACRK_TP2_SHIFT 20
+#define AIPS_PACRK_WP2_MASK 0x200000u
+#define AIPS_PACRK_WP2_SHIFT 21
+#define AIPS_PACRK_SP2_MASK 0x400000u
+#define AIPS_PACRK_SP2_SHIFT 22
+#define AIPS_PACRK_TP1_MASK 0x1000000u
+#define AIPS_PACRK_TP1_SHIFT 24
+#define AIPS_PACRK_WP1_MASK 0x2000000u
+#define AIPS_PACRK_WP1_SHIFT 25
+#define AIPS_PACRK_SP1_MASK 0x4000000u
+#define AIPS_PACRK_SP1_SHIFT 26
+#define AIPS_PACRK_TP0_MASK 0x10000000u
+#define AIPS_PACRK_TP0_SHIFT 28
+#define AIPS_PACRK_WP0_MASK 0x20000000u
+#define AIPS_PACRK_WP0_SHIFT 29
+#define AIPS_PACRK_SP0_MASK 0x40000000u
+#define AIPS_PACRK_SP0_SHIFT 30
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK 0x1u
+#define AIPS_PACRL_TP7_SHIFT 0
+#define AIPS_PACRL_WP7_MASK 0x2u
+#define AIPS_PACRL_WP7_SHIFT 1
+#define AIPS_PACRL_SP7_MASK 0x4u
+#define AIPS_PACRL_SP7_SHIFT 2
+#define AIPS_PACRL_TP6_MASK 0x10u
+#define AIPS_PACRL_TP6_SHIFT 4
+#define AIPS_PACRL_WP6_MASK 0x20u
+#define AIPS_PACRL_WP6_SHIFT 5
+#define AIPS_PACRL_SP6_MASK 0x40u
+#define AIPS_PACRL_SP6_SHIFT 6
+#define AIPS_PACRL_TP5_MASK 0x100u
+#define AIPS_PACRL_TP5_SHIFT 8
+#define AIPS_PACRL_WP5_MASK 0x200u
+#define AIPS_PACRL_WP5_SHIFT 9
+#define AIPS_PACRL_SP5_MASK 0x400u
+#define AIPS_PACRL_SP5_SHIFT 10
+#define AIPS_PACRL_TP4_MASK 0x1000u
+#define AIPS_PACRL_TP4_SHIFT 12
+#define AIPS_PACRL_WP4_MASK 0x2000u
+#define AIPS_PACRL_WP4_SHIFT 13
+#define AIPS_PACRL_SP4_MASK 0x4000u
+#define AIPS_PACRL_SP4_SHIFT 14
+#define AIPS_PACRL_TP3_MASK 0x10000u
+#define AIPS_PACRL_TP3_SHIFT 16
+#define AIPS_PACRL_WP3_MASK 0x20000u
+#define AIPS_PACRL_WP3_SHIFT 17
+#define AIPS_PACRL_SP3_MASK 0x40000u
+#define AIPS_PACRL_SP3_SHIFT 18
+#define AIPS_PACRL_TP2_MASK 0x100000u
+#define AIPS_PACRL_TP2_SHIFT 20
+#define AIPS_PACRL_WP2_MASK 0x200000u
+#define AIPS_PACRL_WP2_SHIFT 21
+#define AIPS_PACRL_SP2_MASK 0x400000u
+#define AIPS_PACRL_SP2_SHIFT 22
+#define AIPS_PACRL_TP1_MASK 0x1000000u
+#define AIPS_PACRL_TP1_SHIFT 24
+#define AIPS_PACRL_WP1_MASK 0x2000000u
+#define AIPS_PACRL_WP1_SHIFT 25
+#define AIPS_PACRL_SP1_MASK 0x4000000u
+#define AIPS_PACRL_SP1_SHIFT 26
+#define AIPS_PACRL_TP0_MASK 0x10000000u
+#define AIPS_PACRL_TP0_SHIFT 28
+#define AIPS_PACRL_WP0_MASK 0x20000000u
+#define AIPS_PACRL_WP0_SHIFT 29
+#define AIPS_PACRL_SP0_MASK 0x40000000u
+#define AIPS_PACRL_SP0_SHIFT 30
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK 0x1u
+#define AIPS_PACRM_TP7_SHIFT 0
+#define AIPS_PACRM_WP7_MASK 0x2u
+#define AIPS_PACRM_WP7_SHIFT 1
+#define AIPS_PACRM_SP7_MASK 0x4u
+#define AIPS_PACRM_SP7_SHIFT 2
+#define AIPS_PACRM_TP6_MASK 0x10u
+#define AIPS_PACRM_TP6_SHIFT 4
+#define AIPS_PACRM_WP6_MASK 0x20u
+#define AIPS_PACRM_WP6_SHIFT 5
+#define AIPS_PACRM_SP6_MASK 0x40u
+#define AIPS_PACRM_SP6_SHIFT 6
+#define AIPS_PACRM_TP5_MASK 0x100u
+#define AIPS_PACRM_TP5_SHIFT 8
+#define AIPS_PACRM_WP5_MASK 0x200u
+#define AIPS_PACRM_WP5_SHIFT 9
+#define AIPS_PACRM_SP5_MASK 0x400u
+#define AIPS_PACRM_SP5_SHIFT 10
+#define AIPS_PACRM_TP4_MASK 0x1000u
+#define AIPS_PACRM_TP4_SHIFT 12
+#define AIPS_PACRM_WP4_MASK 0x2000u
+#define AIPS_PACRM_WP4_SHIFT 13
+#define AIPS_PACRM_SP4_MASK 0x4000u
+#define AIPS_PACRM_SP4_SHIFT 14
+#define AIPS_PACRM_TP3_MASK 0x10000u
+#define AIPS_PACRM_TP3_SHIFT 16
+#define AIPS_PACRM_WP3_MASK 0x20000u
+#define AIPS_PACRM_WP3_SHIFT 17
+#define AIPS_PACRM_SP3_MASK 0x40000u
+#define AIPS_PACRM_SP3_SHIFT 18
+#define AIPS_PACRM_TP2_MASK 0x100000u
+#define AIPS_PACRM_TP2_SHIFT 20
+#define AIPS_PACRM_WP2_MASK 0x200000u
+#define AIPS_PACRM_WP2_SHIFT 21
+#define AIPS_PACRM_SP2_MASK 0x400000u
+#define AIPS_PACRM_SP2_SHIFT 22
+#define AIPS_PACRM_TP1_MASK 0x1000000u
+#define AIPS_PACRM_TP1_SHIFT 24
+#define AIPS_PACRM_WP1_MASK 0x2000000u
+#define AIPS_PACRM_WP1_SHIFT 25
+#define AIPS_PACRM_SP1_MASK 0x4000000u
+#define AIPS_PACRM_SP1_SHIFT 26
+#define AIPS_PACRM_TP0_MASK 0x10000000u
+#define AIPS_PACRM_TP0_SHIFT 28
+#define AIPS_PACRM_WP0_MASK 0x20000000u
+#define AIPS_PACRM_WP0_SHIFT 29
+#define AIPS_PACRM_SP0_MASK 0x40000000u
+#define AIPS_PACRM_SP0_SHIFT 30
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK 0x1u
+#define AIPS_PACRN_TP7_SHIFT 0
+#define AIPS_PACRN_WP7_MASK 0x2u
+#define AIPS_PACRN_WP7_SHIFT 1
+#define AIPS_PACRN_SP7_MASK 0x4u
+#define AIPS_PACRN_SP7_SHIFT 2
+#define AIPS_PACRN_TP6_MASK 0x10u
+#define AIPS_PACRN_TP6_SHIFT 4
+#define AIPS_PACRN_WP6_MASK 0x20u
+#define AIPS_PACRN_WP6_SHIFT 5
+#define AIPS_PACRN_SP6_MASK 0x40u
+#define AIPS_PACRN_SP6_SHIFT 6
+#define AIPS_PACRN_TP5_MASK 0x100u
+#define AIPS_PACRN_TP5_SHIFT 8
+#define AIPS_PACRN_WP5_MASK 0x200u
+#define AIPS_PACRN_WP5_SHIFT 9
+#define AIPS_PACRN_SP5_MASK 0x400u
+#define AIPS_PACRN_SP5_SHIFT 10
+#define AIPS_PACRN_TP4_MASK 0x1000u
+#define AIPS_PACRN_TP4_SHIFT 12
+#define AIPS_PACRN_WP4_MASK 0x2000u
+#define AIPS_PACRN_WP4_SHIFT 13
+#define AIPS_PACRN_SP4_MASK 0x4000u
+#define AIPS_PACRN_SP4_SHIFT 14
+#define AIPS_PACRN_TP3_MASK 0x10000u
+#define AIPS_PACRN_TP3_SHIFT 16
+#define AIPS_PACRN_WP3_MASK 0x20000u
+#define AIPS_PACRN_WP3_SHIFT 17
+#define AIPS_PACRN_SP3_MASK 0x40000u
+#define AIPS_PACRN_SP3_SHIFT 18
+#define AIPS_PACRN_TP2_MASK 0x100000u
+#define AIPS_PACRN_TP2_SHIFT 20
+#define AIPS_PACRN_WP2_MASK 0x200000u
+#define AIPS_PACRN_WP2_SHIFT 21
+#define AIPS_PACRN_SP2_MASK 0x400000u
+#define AIPS_PACRN_SP2_SHIFT 22
+#define AIPS_PACRN_TP1_MASK 0x1000000u
+#define AIPS_PACRN_TP1_SHIFT 24
+#define AIPS_PACRN_WP1_MASK 0x2000000u
+#define AIPS_PACRN_WP1_SHIFT 25
+#define AIPS_PACRN_SP1_MASK 0x4000000u
+#define AIPS_PACRN_SP1_SHIFT 26
+#define AIPS_PACRN_TP0_MASK 0x10000000u
+#define AIPS_PACRN_TP0_SHIFT 28
+#define AIPS_PACRN_WP0_MASK 0x20000000u
+#define AIPS_PACRN_WP0_SHIFT 29
+#define AIPS_PACRN_SP0_MASK 0x40000000u
+#define AIPS_PACRN_SP0_SHIFT 30
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK 0x1u
+#define AIPS_PACRO_TP7_SHIFT 0
+#define AIPS_PACRO_WP7_MASK 0x2u
+#define AIPS_PACRO_WP7_SHIFT 1
+#define AIPS_PACRO_SP7_MASK 0x4u
+#define AIPS_PACRO_SP7_SHIFT 2
+#define AIPS_PACRO_TP6_MASK 0x10u
+#define AIPS_PACRO_TP6_SHIFT 4
+#define AIPS_PACRO_WP6_MASK 0x20u
+#define AIPS_PACRO_WP6_SHIFT 5
+#define AIPS_PACRO_SP6_MASK 0x40u
+#define AIPS_PACRO_SP6_SHIFT 6
+#define AIPS_PACRO_TP5_MASK 0x100u
+#define AIPS_PACRO_TP5_SHIFT 8
+#define AIPS_PACRO_WP5_MASK 0x200u
+#define AIPS_PACRO_WP5_SHIFT 9
+#define AIPS_PACRO_SP5_MASK 0x400u
+#define AIPS_PACRO_SP5_SHIFT 10
+#define AIPS_PACRO_TP4_MASK 0x1000u
+#define AIPS_PACRO_TP4_SHIFT 12
+#define AIPS_PACRO_WP4_MASK 0x2000u
+#define AIPS_PACRO_WP4_SHIFT 13
+#define AIPS_PACRO_SP4_MASK 0x4000u
+#define AIPS_PACRO_SP4_SHIFT 14
+#define AIPS_PACRO_TP3_MASK 0x10000u
+#define AIPS_PACRO_TP3_SHIFT 16
+#define AIPS_PACRO_WP3_MASK 0x20000u
+#define AIPS_PACRO_WP3_SHIFT 17
+#define AIPS_PACRO_SP3_MASK 0x40000u
+#define AIPS_PACRO_SP3_SHIFT 18
+#define AIPS_PACRO_TP2_MASK 0x100000u
+#define AIPS_PACRO_TP2_SHIFT 20
+#define AIPS_PACRO_WP2_MASK 0x200000u
+#define AIPS_PACRO_WP2_SHIFT 21
+#define AIPS_PACRO_SP2_MASK 0x400000u
+#define AIPS_PACRO_SP2_SHIFT 22
+#define AIPS_PACRO_TP1_MASK 0x1000000u
+#define AIPS_PACRO_TP1_SHIFT 24
+#define AIPS_PACRO_WP1_MASK 0x2000000u
+#define AIPS_PACRO_WP1_SHIFT 25
+#define AIPS_PACRO_SP1_MASK 0x4000000u
+#define AIPS_PACRO_SP1_SHIFT 26
+#define AIPS_PACRO_TP0_MASK 0x10000000u
+#define AIPS_PACRO_TP0_SHIFT 28
+#define AIPS_PACRO_WP0_MASK 0x20000000u
+#define AIPS_PACRO_WP0_SHIFT 29
+#define AIPS_PACRO_SP0_MASK 0x40000000u
+#define AIPS_PACRO_SP0_SHIFT 30
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK 0x1u
+#define AIPS_PACRP_TP7_SHIFT 0
+#define AIPS_PACRP_WP7_MASK 0x2u
+#define AIPS_PACRP_WP7_SHIFT 1
+#define AIPS_PACRP_SP7_MASK 0x4u
+#define AIPS_PACRP_SP7_SHIFT 2
+#define AIPS_PACRP_TP6_MASK 0x10u
+#define AIPS_PACRP_TP6_SHIFT 4
+#define AIPS_PACRP_WP6_MASK 0x20u
+#define AIPS_PACRP_WP6_SHIFT 5
+#define AIPS_PACRP_SP6_MASK 0x40u
+#define AIPS_PACRP_SP6_SHIFT 6
+#define AIPS_PACRP_TP5_MASK 0x100u
+#define AIPS_PACRP_TP5_SHIFT 8
+#define AIPS_PACRP_WP5_MASK 0x200u
+#define AIPS_PACRP_WP5_SHIFT 9
+#define AIPS_PACRP_SP5_MASK 0x400u
+#define AIPS_PACRP_SP5_SHIFT 10
+#define AIPS_PACRP_TP4_MASK 0x1000u
+#define AIPS_PACRP_TP4_SHIFT 12
+#define AIPS_PACRP_WP4_MASK 0x2000u
+#define AIPS_PACRP_WP4_SHIFT 13
+#define AIPS_PACRP_SP4_MASK 0x4000u
+#define AIPS_PACRP_SP4_SHIFT 14
+#define AIPS_PACRP_TP3_MASK 0x10000u
+#define AIPS_PACRP_TP3_SHIFT 16
+#define AIPS_PACRP_WP3_MASK 0x20000u
+#define AIPS_PACRP_WP3_SHIFT 17
+#define AIPS_PACRP_SP3_MASK 0x40000u
+#define AIPS_PACRP_SP3_SHIFT 18
+#define AIPS_PACRP_TP2_MASK 0x100000u
+#define AIPS_PACRP_TP2_SHIFT 20
+#define AIPS_PACRP_WP2_MASK 0x200000u
+#define AIPS_PACRP_WP2_SHIFT 21
+#define AIPS_PACRP_SP2_MASK 0x400000u
+#define AIPS_PACRP_SP2_SHIFT 22
+#define AIPS_PACRP_TP1_MASK 0x1000000u
+#define AIPS_PACRP_TP1_SHIFT 24
+#define AIPS_PACRP_WP1_MASK 0x2000000u
+#define AIPS_PACRP_WP1_SHIFT 25
+#define AIPS_PACRP_SP1_MASK 0x4000000u
+#define AIPS_PACRP_SP1_SHIFT 26
+#define AIPS_PACRP_TP0_MASK 0x10000000u
+#define AIPS_PACRP_TP0_SHIFT 28
+#define AIPS_PACRP_WP0_MASK 0x20000000u
+#define AIPS_PACRP_WP0_SHIFT 29
+#define AIPS_PACRP_SP0_MASK 0x40000000u
+#define AIPS_PACRP_SP0_SHIFT 30
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK 0x1000000u
+#define AIPS_PACRU_TP1_SHIFT 24
+#define AIPS_PACRU_WP1_MASK 0x2000000u
+#define AIPS_PACRU_WP1_SHIFT 25
+#define AIPS_PACRU_SP1_MASK 0x4000000u
+#define AIPS_PACRU_SP1_SHIFT 26
+#define AIPS_PACRU_TP0_MASK 0x10000000u
+#define AIPS_PACRU_TP0_SHIFT 28
+#define AIPS_PACRU_WP0_MASK 0x20000000u
+#define AIPS_PACRU_WP0_SHIFT 29
+#define AIPS_PACRU_SP0_MASK 0x40000000u
+#define AIPS_PACRU_SP0_SHIFT 30
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_1[236];
+ } SLAVE[5];
+ uint8_t RESERVED_0[768];
+ __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
+ uint8_t RESERVED_1[252];
+ __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
+ uint8_t RESERVED_2[252];
+ __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
+ uint8_t RESERVED_3[252];
+ __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
+ uint8_t RESERVED_4[252];
+ __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
+ uint8_t RESERVED_5[252];
+ __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AXBS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
+#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
+#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK 0x7u
+#define AXBS_PRS_M0_SHIFT 0
+#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK 0x70u
+#define AXBS_PRS_M1_SHIFT 4
+#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK 0x700u
+#define AXBS_PRS_M2_SHIFT 8
+#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK 0x7000u
+#define AXBS_PRS_M3_SHIFT 12
+#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK 0x70000u
+#define AXBS_PRS_M4_SHIFT 16
+#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK 0x700000u
+#define AXBS_PRS_M5_SHIFT 20
+#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK 0x7u
+#define AXBS_CRS_PARK_SHIFT 0
+#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK 0x30u
+#define AXBS_CRS_PCTL_SHIFT 4
+#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK 0x300u
+#define AXBS_CRS_ARB_SHIFT 8
+#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK 0x40000000u
+#define AXBS_CRS_HLP_SHIFT 30
+#define AXBS_CRS_RO_MASK 0x80000000u
+#define AXBS_CRS_RO_SHIFT 31
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK 0x7u
+#define AXBS_MGPCR0_AULB_SHIFT 0
+#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK 0x7u
+#define AXBS_MGPCR1_AULB_SHIFT 0
+#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK 0x7u
+#define AXBS_MGPCR2_AULB_SHIFT 0
+#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK 0x7u
+#define AXBS_MGPCR3_AULB_SHIFT 0
+#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK 0x7u
+#define AXBS_MGPCR4_AULB_SHIFT 0
+#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK 0x7u
+#define AXBS_MGPCR5_AULB_SHIFT 0
+#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS { AXBS }
+
+/* ----------------------------------------------------------------------------
+ -- AXBS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
+ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
+ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
+ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
+ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
+ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
+ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
+ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
+ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x80, array step: 0x10 */
+ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+ } MB[16];
+ uint8_t RESERVED_5[1792];
+ __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CAN - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base) ((base)->MCR)
+#define CAN_CTRL1_REG(base) ((base)->CTRL1)
+#define CAN_TIMER_REG(base) ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
+#define CAN_ECR_REG(base) ((base)->ECR)
+#define CAN_ESR1_REG(base) ((base)->ESR1)
+#define CAN_IMASK1_REG(base) ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base) ((base)->CTRL2)
+#define CAN_ESR2_REG(base) ((base)->ESR2)
+#define CAN_CRCR_REG(base) ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base) ((base)->RXFIR)
+#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
+#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
+#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
+#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
+#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK 0x7Fu
+#define CAN_MCR_MAXMB_SHIFT 0
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK 0x300u
+#define CAN_MCR_IDAM_SHIFT 8
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK 0x1000u
+#define CAN_MCR_AEN_SHIFT 12
+#define CAN_MCR_LPRIOEN_MASK 0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT 13
+#define CAN_MCR_IRMQ_MASK 0x10000u
+#define CAN_MCR_IRMQ_SHIFT 16
+#define CAN_MCR_SRXDIS_MASK 0x20000u
+#define CAN_MCR_SRXDIS_SHIFT 17
+#define CAN_MCR_WAKSRC_MASK 0x80000u
+#define CAN_MCR_WAKSRC_SHIFT 19
+#define CAN_MCR_LPMACK_MASK 0x100000u
+#define CAN_MCR_LPMACK_SHIFT 20
+#define CAN_MCR_WRNEN_MASK 0x200000u
+#define CAN_MCR_WRNEN_SHIFT 21
+#define CAN_MCR_SLFWAK_MASK 0x400000u
+#define CAN_MCR_SLFWAK_SHIFT 22
+#define CAN_MCR_SUPV_MASK 0x800000u
+#define CAN_MCR_SUPV_SHIFT 23
+#define CAN_MCR_FRZACK_MASK 0x1000000u
+#define CAN_MCR_FRZACK_SHIFT 24
+#define CAN_MCR_SOFTRST_MASK 0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT 25
+#define CAN_MCR_WAKMSK_MASK 0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT 26
+#define CAN_MCR_NOTRDY_MASK 0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT 27
+#define CAN_MCR_HALT_MASK 0x10000000u
+#define CAN_MCR_HALT_SHIFT 28
+#define CAN_MCR_RFEN_MASK 0x20000000u
+#define CAN_MCR_RFEN_SHIFT 29
+#define CAN_MCR_FRZ_MASK 0x40000000u
+#define CAN_MCR_FRZ_SHIFT 30
+#define CAN_MCR_MDIS_MASK 0x80000000u
+#define CAN_MCR_MDIS_SHIFT 31
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK 0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT 0
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK 0x8u
+#define CAN_CTRL1_LOM_SHIFT 3
+#define CAN_CTRL1_LBUF_MASK 0x10u
+#define CAN_CTRL1_LBUF_SHIFT 4
+#define CAN_CTRL1_TSYN_MASK 0x20u
+#define CAN_CTRL1_TSYN_SHIFT 5
+#define CAN_CTRL1_BOFFREC_MASK 0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT 6
+#define CAN_CTRL1_SMP_MASK 0x80u
+#define CAN_CTRL1_SMP_SHIFT 7
+#define CAN_CTRL1_RWRNMSK_MASK 0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT 10
+#define CAN_CTRL1_TWRNMSK_MASK 0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT 11
+#define CAN_CTRL1_LPB_MASK 0x1000u
+#define CAN_CTRL1_LPB_SHIFT 12
+#define CAN_CTRL1_CLKSRC_MASK 0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT 13
+#define CAN_CTRL1_ERRMSK_MASK 0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT 14
+#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT 15
+#define CAN_CTRL1_PSEG2_MASK 0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT 16
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK 0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT 19
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK 0xC00000u
+#define CAN_CTRL1_RJW_SHIFT 22
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT 24
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK 0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT 0
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT 0
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT 0
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT 0
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK 0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT 0
+#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK 0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT 8
+#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK 0x1u
+#define CAN_ESR1_WAKINT_SHIFT 0
+#define CAN_ESR1_ERRINT_MASK 0x2u
+#define CAN_ESR1_ERRINT_SHIFT 1
+#define CAN_ESR1_BOFFINT_MASK 0x4u
+#define CAN_ESR1_BOFFINT_SHIFT 2
+#define CAN_ESR1_RX_MASK 0x8u
+#define CAN_ESR1_RX_SHIFT 3
+#define CAN_ESR1_FLTCONF_MASK 0x30u
+#define CAN_ESR1_FLTCONF_SHIFT 4
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK 0x40u
+#define CAN_ESR1_TX_SHIFT 6
+#define CAN_ESR1_IDLE_MASK 0x80u
+#define CAN_ESR1_IDLE_SHIFT 7
+#define CAN_ESR1_RXWRN_MASK 0x100u
+#define CAN_ESR1_RXWRN_SHIFT 8
+#define CAN_ESR1_TXWRN_MASK 0x200u
+#define CAN_ESR1_TXWRN_SHIFT 9
+#define CAN_ESR1_STFERR_MASK 0x400u
+#define CAN_ESR1_STFERR_SHIFT 10
+#define CAN_ESR1_FRMERR_MASK 0x800u
+#define CAN_ESR1_FRMERR_SHIFT 11
+#define CAN_ESR1_CRCERR_MASK 0x1000u
+#define CAN_ESR1_CRCERR_SHIFT 12
+#define CAN_ESR1_ACKERR_MASK 0x2000u
+#define CAN_ESR1_ACKERR_SHIFT 13
+#define CAN_ESR1_BIT0ERR_MASK 0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT 14
+#define CAN_ESR1_BIT1ERR_MASK 0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT 15
+#define CAN_ESR1_RWRNINT_MASK 0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT 16
+#define CAN_ESR1_TWRNINT_MASK 0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT 17
+#define CAN_ESR1_SYNCH_MASK 0x40000u
+#define CAN_ESR1_SYNCH_SHIFT 18
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT 0
+#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK 0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT 0
+#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT 1
+#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK 0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT 5
+#define CAN_IFLAG1_BUF6I_MASK 0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT 6
+#define CAN_IFLAG1_BUF7I_MASK 0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT 7
+#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK 0x10000u
+#define CAN_CTRL2_EACEN_SHIFT 16
+#define CAN_CTRL2_RRS_MASK 0x20000u
+#define CAN_CTRL2_RRS_SHIFT 17
+#define CAN_CTRL2_MRP_MASK 0x40000u
+#define CAN_CTRL2_MRP_SHIFT 18
+#define CAN_CTRL2_TASD_MASK 0xF80000u
+#define CAN_CTRL2_TASD_SHIFT 19
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK 0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT 24
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT 28
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK 0x2000u
+#define CAN_ESR2_IMB_SHIFT 13
+#define CAN_ESR2_VPS_MASK 0x4000u
+#define CAN_ESR2_VPS_SHIFT 14
+#define CAN_ESR2_LPTM_MASK 0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT 16
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK 0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT 0
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK 0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT 16
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT 0
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK 0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT 0
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT 0
+#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK 0xF0000u
+#define CAN_CS_DLC_SHIFT 16
+#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK 0x100000u
+#define CAN_CS_RTR_SHIFT 20
+#define CAN_CS_IDE_MASK 0x200000u
+#define CAN_CS_IDE_SHIFT 21
+#define CAN_CS_SRR_MASK 0x400000u
+#define CAN_CS_SRR_SHIFT 22
+#define CAN_CS_CODE_MASK 0xF000000u
+#define CAN_CS_CODE_SHIFT 24
+#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK 0x3FFFFu
+#define CAN_ID_EXT_SHIFT 0
+#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK 0x1FFC0000u
+#define CAN_ID_STD_SHIFT 18
+#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK 0xE0000000u
+#define CAN_ID_PRIO_SHIFT 29
+#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
+#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
+#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
+#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
+#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
+#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
+#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
+#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
+#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT 0
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CAN - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR CAN_ECR_REG(CAN0)
+#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10 CAN_CS_REG(CAN0,10)
+#define CAN0_ID10 CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11 CAN_CS_REG(CAN0,11)
+#define CAN0_ID11 CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12 CAN_CS_REG(CAN0,12)
+#define CAN0_ID12 CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13 CAN_CS_REG(CAN0,13)
+#define CAN0_ID13 CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14 CAN_CS_REG(CAN0,14)
+#define CAN0_ID14 CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15 CAN_CS_REG(CAN0,15)
+#define CAN0_ID15 CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+ __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[2048];
+ __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
+ __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
+ __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+ uint8_t RESERVED_1[20];
+ __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
+ __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
+ __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+ uint8_t RESERVED_2[20];
+ __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
+ __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
+ __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+ uint8_t RESERVED_3[20];
+ __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+ __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+ __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+ uint8_t RESERVED_4[84];
+ __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
+ __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+ __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+ uint8_t RESERVED_5[20];
+ __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
+ __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+ __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+ uint8_t RESERVED_6[276];
+ __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
+ __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+ __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+ uint8_t RESERVED_7[20];
+ __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+ __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+ __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CAU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
+#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
+#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
+#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
+#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
+#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
+#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
+#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
+#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK 0x1u
+#define CAU_LDR_CASR_IC_SHIFT 0
+#define CAU_LDR_CASR_DPE_MASK 0x2u
+#define CAU_LDR_CASR_DPE_SHIFT 1
+#define CAU_LDR_CASR_VER_MASK 0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT 28
+#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT 0
+#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT 0
+#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT 0
+#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT 0
+#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT 0
+#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT 0
+#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT 0
+#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT 0
+#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT 0
+#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT 0
+#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK 0x1u
+#define CAU_STR_CASR_IC_SHIFT 0
+#define CAU_STR_CASR_DPE_MASK 0x2u
+#define CAU_STR_CASR_DPE_SHIFT 1
+#define CAU_STR_CASR_VER_MASK 0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT 28
+#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT 0
+#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT 0
+#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT 0
+#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT 0
+#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT 0
+#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT 0
+#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT 0
+#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT 0
+#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT 0
+#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT 0
+#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK 0x1u
+#define CAU_ADR_CASR_IC_SHIFT 0
+#define CAU_ADR_CASR_DPE_MASK 0x2u
+#define CAU_ADR_CASR_DPE_SHIFT 1
+#define CAU_ADR_CASR_VER_MASK 0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT 28
+#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT 0
+#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT 0
+#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT 0
+#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT 0
+#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT 0
+#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT 0
+#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT 0
+#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT 0
+#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT 0
+#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT 0
+#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK 0x1u
+#define CAU_RADR_CASR_IC_SHIFT 0
+#define CAU_RADR_CASR_DPE_MASK 0x2u
+#define CAU_RADR_CASR_DPE_SHIFT 1
+#define CAU_RADR_CASR_VER_MASK 0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT 28
+#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT 0
+#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT 0
+#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT 0
+#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT 0
+#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT 0
+#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT 0
+#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT 0
+#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT 0
+#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT 0
+#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT 0
+#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK 0x1u
+#define CAU_XOR_CASR_IC_SHIFT 0
+#define CAU_XOR_CASR_DPE_MASK 0x2u
+#define CAU_XOR_CASR_DPE_SHIFT 1
+#define CAU_XOR_CASR_VER_MASK 0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT 28
+#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT 0
+#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT 0
+#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT 0
+#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT 0
+#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT 0
+#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT 0
+#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT 0
+#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT 0
+#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT 0
+#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT 0
+#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK 0x1u
+#define CAU_ROTL_CASR_IC_SHIFT 0
+#define CAU_ROTL_CASR_DPE_MASK 0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT 1
+#define CAU_ROTL_CASR_VER_MASK 0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT 28
+#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT 0
+#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT 0
+#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT 0
+#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT 0
+#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT 0
+#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT 0
+#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT 0
+#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT 0
+#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT 0
+#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT 0
+#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK 0x1u
+#define CAU_AESC_CASR_IC_SHIFT 0
+#define CAU_AESC_CASR_DPE_MASK 0x2u
+#define CAU_AESC_CASR_DPE_SHIFT 1
+#define CAU_AESC_CASR_VER_MASK 0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT 28
+#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT 0
+#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT 0
+#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT 0
+#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT 0
+#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT 0
+#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT 0
+#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT 0
+#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT 0
+#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT 0
+#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT 0
+#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK 0x1u
+#define CAU_AESIC_CASR_IC_SHIFT 0
+#define CAU_AESIC_CASR_DPE_MASK 0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT 1
+#define CAU_AESIC_CASR_VER_MASK 0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT 28
+#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT 0
+#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT 0
+#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT 0
+#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT 0
+#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT 0
+#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT 0
+#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT 0
+#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT 0
+#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT 0
+#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT 0
+#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS { CAU }
+
+/* ----------------------------------------------------------------------------
+ -- CAU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2 ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0 CMP_CR0_REG(CMP1)
+#define CMP1_CR1 CMP_CR1_REG(CMP1)
+#define CMP1_FPR CMP_FPR_REG(CMP1)
+#define CMP1_SCR CMP_SCR_REG(CMP1)
+#define CMP1_DACCR CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0 CMP_CR0_REG(CMP2)
+#define CMP2_CR1 CMP_CR1_REG(CMP2)
+#define CMP2_FPR CMP_FPR_REG(CMP2)
+#define CMP2_SCR CMP_SCR_REG(CMP2)
+#define CMP2_DACCR CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base) ((base)->CGH1)
+#define CMT_CGL1_REG(base) ((base)->CGL1)
+#define CMT_CGH2_REG(base) ((base)->CGH2)
+#define CMT_CGL2_REG(base) ((base)->CGL2)
+#define CMT_OC_REG(base) ((base)->OC)
+#define CMT_MSC_REG(base) ((base)->MSC)
+#define CMT_CMD1_REG(base) ((base)->CMD1)
+#define CMT_CMD2_REG(base) ((base)->CMD2)
+#define CMT_CMD3_REG(base) ((base)->CMD3)
+#define CMT_CMD4_REG(base) ((base)->CMD4)
+#define CMT_PPS_REG(base) ((base)->PPS)
+#define CMT_DMA_REG(base) ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1 CMT_CGH1_REG(CMT)
+#define CMT_CGL1 CMT_CGL1_REG(CMT)
+#define CMT_CGH2 CMT_CGH2_REG(CMT)
+#define CMT_CGL2 CMT_CGL2_REG(CMT)
+#define CMT_OC CMT_OC_REG(CMT)
+#define CMT_MSC CMT_MSC_REG(CMT)
+#define CMT_CMD1 CMT_CMD1_REG(CMT)
+#define CMT_CMD2 CMT_CMD2_REG(CMT)
+#define CMT_CMD3 CMT_CMD3_REG(CMT)
+#define CMT_CMD4 CMT_CMD4_REG(CMT)
+#define CMT_PPS CMT_PPS_REG(CMT)
+#define CMT_DMA CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base) ((base)->DATA)
+#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base) ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base) ((base)->CTRL)
+#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK 0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT 0
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK 0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT 0
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK 0xFFu
+#define CRC_DATA_LL_SHIFT 0
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK 0xFF00u
+#define CRC_DATA_LU_SHIFT 8
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK 0xFF0000u
+#define CRC_DATA_HL_SHIFT 16
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK 0xFF000000u
+#define CRC_DATA_HU_SHIFT 24
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK 0xFFu
+#define CRC_DATALL_DATALL_SHIFT 0
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK 0xFFu
+#define CRC_DATALU_DATALU_SHIFT 0
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK 0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT 0
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK 0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT 0
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC0 }
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA CRC_DATA_REG(CRC0)
+#define CRC_DATAL CRC_DATAL_REG(CRC0)
+#define CRC_DATALL CRC_DATALL_REG(CRC0)
+#define CRC_DATALU CRC_DATALU_REG(CRC0)
+#define CRC_DATAH CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1 ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
+#define DAC1_SR DAC_SR_REG(DAC1)
+#define DAC1_C0 DAC_C0_REG(DAC1)
+#define DAC1_C1 DAC_C1_REG(DAC1)
+#define DAC1_C2 DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
+ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
+ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
+ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
+ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
+ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
+ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
+ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
+ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
+ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
+ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
+ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
+ uint8_t RESERVED_6[3824];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base) ((base)->CR)
+#define DMA_ES_REG(base) ((base)->ES)
+#define DMA_ERQ_REG(base) ((base)->ERQ)
+#define DMA_EEI_REG(base) ((base)->EEI)
+#define DMA_CEEI_REG(base) ((base)->CEEI)
+#define DMA_SEEI_REG(base) ((base)->SEEI)
+#define DMA_CERQ_REG(base) ((base)->CERQ)
+#define DMA_SERQ_REG(base) ((base)->SERQ)
+#define DMA_CDNE_REG(base) ((base)->CDNE)
+#define DMA_SSRT_REG(base) ((base)->SSRT)
+#define DMA_CERR_REG(base) ((base)->CERR)
+#define DMA_CINT_REG(base) ((base)->CINT)
+#define DMA_INT_REG(base) ((base)->INT)
+#define DMA_ERR_REG(base) ((base)->ERR)
+#define DMA_HRS_REG(base) ((base)->HRS)
+#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+#define DMA_ERQ_ERQ4_MASK 0x10u
+#define DMA_ERQ_ERQ4_SHIFT 4
+#define DMA_ERQ_ERQ5_MASK 0x20u
+#define DMA_ERQ_ERQ5_SHIFT 5
+#define DMA_ERQ_ERQ6_MASK 0x40u
+#define DMA_ERQ_ERQ6_SHIFT 6
+#define DMA_ERQ_ERQ7_MASK 0x80u
+#define DMA_ERQ_ERQ7_SHIFT 7
+#define DMA_ERQ_ERQ8_MASK 0x100u
+#define DMA_ERQ_ERQ8_SHIFT 8
+#define DMA_ERQ_ERQ9_MASK 0x200u
+#define DMA_ERQ_ERQ9_SHIFT 9
+#define DMA_ERQ_ERQ10_MASK 0x400u
+#define DMA_ERQ_ERQ10_SHIFT 10
+#define DMA_ERQ_ERQ11_MASK 0x800u
+#define DMA_ERQ_ERQ11_SHIFT 11
+#define DMA_ERQ_ERQ12_MASK 0x1000u
+#define DMA_ERQ_ERQ12_SHIFT 12
+#define DMA_ERQ_ERQ13_MASK 0x2000u
+#define DMA_ERQ_ERQ13_SHIFT 13
+#define DMA_ERQ_ERQ14_MASK 0x4000u
+#define DMA_ERQ_ERQ14_SHIFT 14
+#define DMA_ERQ_ERQ15_MASK 0x8000u
+#define DMA_ERQ_ERQ15_SHIFT 15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+#define DMA_EEI_EEI4_MASK 0x10u
+#define DMA_EEI_EEI4_SHIFT 4
+#define DMA_EEI_EEI5_MASK 0x20u
+#define DMA_EEI_EEI5_SHIFT 5
+#define DMA_EEI_EEI6_MASK 0x40u
+#define DMA_EEI_EEI6_SHIFT 6
+#define DMA_EEI_EEI7_MASK 0x80u
+#define DMA_EEI_EEI7_SHIFT 7
+#define DMA_EEI_EEI8_MASK 0x100u
+#define DMA_EEI_EEI8_SHIFT 8
+#define DMA_EEI_EEI9_MASK 0x200u
+#define DMA_EEI_EEI9_SHIFT 9
+#define DMA_EEI_EEI10_MASK 0x400u
+#define DMA_EEI_EEI10_SHIFT 10
+#define DMA_EEI_EEI11_MASK 0x800u
+#define DMA_EEI_EEI11_SHIFT 11
+#define DMA_EEI_EEI12_MASK 0x1000u
+#define DMA_EEI_EEI12_SHIFT 12
+#define DMA_EEI_EEI13_MASK 0x2000u
+#define DMA_EEI_EEI13_SHIFT 13
+#define DMA_EEI_EEI14_MASK 0x4000u
+#define DMA_EEI_EEI14_SHIFT 14
+#define DMA_EEI_EEI15_MASK 0x8000u
+#define DMA_EEI_EEI15_SHIFT 15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+#define DMA_INT_INT4_MASK 0x10u
+#define DMA_INT_INT4_SHIFT 4
+#define DMA_INT_INT5_MASK 0x20u
+#define DMA_INT_INT5_SHIFT 5
+#define DMA_INT_INT6_MASK 0x40u
+#define DMA_INT_INT6_SHIFT 6
+#define DMA_INT_INT7_MASK 0x80u
+#define DMA_INT_INT7_SHIFT 7
+#define DMA_INT_INT8_MASK 0x100u
+#define DMA_INT_INT8_SHIFT 8
+#define DMA_INT_INT9_MASK 0x200u
+#define DMA_INT_INT9_SHIFT 9
+#define DMA_INT_INT10_MASK 0x400u
+#define DMA_INT_INT10_SHIFT 10
+#define DMA_INT_INT11_MASK 0x800u
+#define DMA_INT_INT11_SHIFT 11
+#define DMA_INT_INT12_MASK 0x1000u
+#define DMA_INT_INT12_SHIFT 12
+#define DMA_INT_INT13_MASK 0x2000u
+#define DMA_INT_INT13_SHIFT 13
+#define DMA_INT_INT14_MASK 0x4000u
+#define DMA_INT_INT14_SHIFT 14
+#define DMA_INT_INT15_MASK 0x8000u
+#define DMA_INT_INT15_SHIFT 15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+#define DMA_ERR_ERR4_MASK 0x10u
+#define DMA_ERR_ERR4_SHIFT 4
+#define DMA_ERR_ERR5_MASK 0x20u
+#define DMA_ERR_ERR5_SHIFT 5
+#define DMA_ERR_ERR6_MASK 0x40u
+#define DMA_ERR_ERR6_SHIFT 6
+#define DMA_ERR_ERR7_MASK 0x80u
+#define DMA_ERR_ERR7_SHIFT 7
+#define DMA_ERR_ERR8_MASK 0x100u
+#define DMA_ERR_ERR8_SHIFT 8
+#define DMA_ERR_ERR9_MASK 0x200u
+#define DMA_ERR_ERR9_SHIFT 9
+#define DMA_ERR_ERR10_MASK 0x400u
+#define DMA_ERR_ERR10_SHIFT 10
+#define DMA_ERR_ERR11_MASK 0x800u
+#define DMA_ERR_ERR11_SHIFT 11
+#define DMA_ERR_ERR12_MASK 0x1000u
+#define DMA_ERR_ERR12_SHIFT 12
+#define DMA_ERR_ERR13_MASK 0x2000u
+#define DMA_ERR_ERR13_SHIFT 13
+#define DMA_ERR_ERR14_MASK 0x4000u
+#define DMA_ERR_ERR14_SHIFT 14
+#define DMA_ERR_ERR15_MASK 0x8000u
+#define DMA_ERR_ERR15_SHIFT 15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+#define DMA_HRS_HRS4_MASK 0x10u
+#define DMA_HRS_HRS4_SHIFT 4
+#define DMA_HRS_HRS5_MASK 0x20u
+#define DMA_HRS_HRS5_SHIFT 5
+#define DMA_HRS_HRS6_MASK 0x40u
+#define DMA_HRS_HRS6_SHIFT 6
+#define DMA_HRS_HRS7_MASK 0x80u
+#define DMA_HRS_HRS7_SHIFT 7
+#define DMA_HRS_HRS8_MASK 0x100u
+#define DMA_HRS_HRS8_SHIFT 8
+#define DMA_HRS_HRS9_MASK 0x200u
+#define DMA_HRS_HRS9_SHIFT 9
+#define DMA_HRS_HRS10_MASK 0x400u
+#define DMA_HRS_HRS10_SHIFT 10
+#define DMA_HRS_HRS11_MASK 0x800u
+#define DMA_HRS_HRS11_SHIFT 11
+#define DMA_HRS_HRS12_MASK 0x1000u
+#define DMA_HRS_HRS12_SHIFT 12
+#define DMA_HRS_HRS13_MASK 0x2000u
+#define DMA_HRS_HRS13_SHIFT 13
+#define DMA_HRS_HRS14_MASK 0x4000u
+#define DMA_HRS_HRS14_SHIFT 14
+#define DMA_HRS_HRS15_MASK 0x8000u
+#define DMA_HRS_HRS15_SHIFT 15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK 0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT 0
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK 0x40u
+#define DMA_DCHPRI7_DPA_SHIFT 6
+#define DMA_DCHPRI7_ECP_MASK 0x80u
+#define DMA_DCHPRI7_ECP_SHIFT 7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK 0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT 0
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK 0x40u
+#define DMA_DCHPRI6_DPA_SHIFT 6
+#define DMA_DCHPRI6_ECP_MASK 0x80u
+#define DMA_DCHPRI6_ECP_SHIFT 7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK 0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT 0
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK 0x40u
+#define DMA_DCHPRI5_DPA_SHIFT 6
+#define DMA_DCHPRI5_ECP_MASK 0x80u
+#define DMA_DCHPRI5_ECP_SHIFT 7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK 0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT 0
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK 0x40u
+#define DMA_DCHPRI4_DPA_SHIFT 6
+#define DMA_DCHPRI4_ECP_MASK 0x80u
+#define DMA_DCHPRI4_ECP_SHIFT 7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK 0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT 0
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK 0x40u
+#define DMA_DCHPRI11_DPA_SHIFT 6
+#define DMA_DCHPRI11_ECP_MASK 0x80u
+#define DMA_DCHPRI11_ECP_SHIFT 7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK 0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT 0
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK 0x40u
+#define DMA_DCHPRI10_DPA_SHIFT 6
+#define DMA_DCHPRI10_ECP_MASK 0x80u
+#define DMA_DCHPRI10_ECP_SHIFT 7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK 0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT 0
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK 0x40u
+#define DMA_DCHPRI9_DPA_SHIFT 6
+#define DMA_DCHPRI9_ECP_MASK 0x80u
+#define DMA_DCHPRI9_ECP_SHIFT 7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK 0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT 0
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK 0x40u
+#define DMA_DCHPRI8_DPA_SHIFT 6
+#define DMA_DCHPRI8_ECP_MASK 0x80u
+#define DMA_DCHPRI8_ECP_SHIFT 7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK 0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT 0
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK 0x40u
+#define DMA_DCHPRI15_DPA_SHIFT 6
+#define DMA_DCHPRI15_ECP_MASK 0x80u
+#define DMA_DCHPRI15_ECP_SHIFT 7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK 0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT 0
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK 0x40u
+#define DMA_DCHPRI14_DPA_SHIFT 6
+#define DMA_DCHPRI14_ECP_MASK 0x80u
+#define DMA_DCHPRI14_ECP_SHIFT 7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK 0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT 0
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK 0x40u
+#define DMA_DCHPRI13_DPA_SHIFT 6
+#define DMA_DCHPRI13_ECP_MASK 0x80u
+#define DMA_DCHPRI13_ECP_SHIFT 7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK 0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT 0
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK 0x40u
+#define DMA_DCHPRI12_DPA_SHIFT 6
+#define DMA_DCHPRI12_ECP_MASK 0x80u
+#define DMA_DCHPRI12_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR DMA_CR_REG(DMA0)
+#define DMA_ES DMA_ES_REG(DMA0)
+#define DMA_ERQ DMA_ERQ_REG(DMA0)
+#define DMA_EEI DMA_EEI_REG(DMA0)
+#define DMA_CEEI DMA_CEEI_REG(DMA0)
+#define DMA_SEEI DMA_SEEI_REG(DMA0)
+#define DMA_CERQ DMA_CERQ_REG(DMA0)
+#define DMA_SERQ DMA_SERQ_REG(DMA0)
+#define DMA_CDNE DMA_CDNE_REG(DMA0)
+#define DMA_SSRT DMA_SSRT_REG(DMA0)
+#define DMA_CERR DMA_CERR_REG(DMA0)
+#define DMA_CINT DMA_CINT_REG(DMA0)
+#define DMA_INT DMA_INT_REG(DMA0)
+#define DMA_ERR DMA_ERR_REG(DMA0)
+#define DMA_HRS DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
+ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
+ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
+ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
+ uint8_t RESERVED_4[28];
+ __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
+ uint8_t RESERVED_5[28];
+ __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
+ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
+ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
+ uint8_t RESERVED_8[40];
+ __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
+ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
+ uint8_t RESERVED_9[28];
+ __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
+ uint8_t RESERVED_10[56];
+ __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+ uint8_t RESERVED_11[4];
+ __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
+ uint8_t RESERVED_12[12];
+ __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+ uint8_t RESERVED_13[60];
+ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
+ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
+ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
+ uint8_t RESERVED_14[4];
+ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+ uint8_t RESERVED_15[4];
+ __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+ uint8_t RESERVED_16[12];
+ __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
+ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+ uint8_t RESERVED_17[4];
+ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+ __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
+ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
+ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+ uint8_t RESERVED_18[284];
+ __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
+ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
+ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
+ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
+ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
+ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
+ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+ uint8_t RESERVED_19[488];
+ __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
+ struct { /* offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+ } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ENET - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base) ((base)->EIR)
+#define ENET_EIMR_REG(base) ((base)->EIMR)
+#define ENET_RDAR_REG(base) ((base)->RDAR)
+#define ENET_TDAR_REG(base) ((base)->TDAR)
+#define ENET_ECR_REG(base) ((base)->ECR)
+#define ENET_MMFR_REG(base) ((base)->MMFR)
+#define ENET_MSCR_REG(base) ((base)->MSCR)
+#define ENET_MIBC_REG(base) ((base)->MIBC)
+#define ENET_RCR_REG(base) ((base)->RCR)
+#define ENET_TCR_REG(base) ((base)->TCR)
+#define ENET_PALR_REG(base) ((base)->PALR)
+#define ENET_PAUR_REG(base) ((base)->PAUR)
+#define ENET_OPD_REG(base) ((base)->OPD)
+#define ENET_IAUR_REG(base) ((base)->IAUR)
+#define ENET_IALR_REG(base) ((base)->IALR)
+#define ENET_GAUR_REG(base) ((base)->GAUR)
+#define ENET_GALR_REG(base) ((base)->GALR)
+#define ENET_TFWR_REG(base) ((base)->TFWR)
+#define ENET_RDSR_REG(base) ((base)->RDSR)
+#define ENET_TDSR_REG(base) ((base)->TDSR)
+#define ENET_MRBR_REG(base) ((base)->MRBR)
+#define ENET_RSFL_REG(base) ((base)->RSFL)
+#define ENET_RSEM_REG(base) ((base)->RSEM)
+#define ENET_RAEM_REG(base) ((base)->RAEM)
+#define ENET_RAFL_REG(base) ((base)->RAFL)
+#define ENET_TSEM_REG(base) ((base)->TSEM)
+#define ENET_TAEM_REG(base) ((base)->TAEM)
+#define ENET_TAFL_REG(base) ((base)->TAFL)
+#define ENET_TIPG_REG(base) ((base)->TIPG)
+#define ENET_FTRL_REG(base) ((base)->FTRL)
+#define ENET_TACC_REG(base) ((base)->TACC)
+#define ENET_RACC_REG(base) ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base) ((base)->ATCR)
+#define ENET_ATVR_REG(base) ((base)->ATVR)
+#define ENET_ATOFF_REG(base) ((base)->ATOFF)
+#define ENET_ATPER_REG(base) ((base)->ATPER)
+#define ENET_ATCOR_REG(base) ((base)->ATCOR)
+#define ENET_ATINC_REG(base) ((base)->ATINC)
+#define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
+#define ENET_TGSR_REG(base) ((base)->TGSR)
+#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
+#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK 0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT 15
+#define ENET_EIR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT 16
+#define ENET_EIR_WAKEUP_MASK 0x20000u
+#define ENET_EIR_WAKEUP_SHIFT 17
+#define ENET_EIR_PLR_MASK 0x40000u
+#define ENET_EIR_PLR_SHIFT 18
+#define ENET_EIR_UN_MASK 0x80000u
+#define ENET_EIR_UN_SHIFT 19
+#define ENET_EIR_RL_MASK 0x100000u
+#define ENET_EIR_RL_SHIFT 20
+#define ENET_EIR_LC_MASK 0x200000u
+#define ENET_EIR_LC_SHIFT 21
+#define ENET_EIR_EBERR_MASK 0x400000u
+#define ENET_EIR_EBERR_SHIFT 22
+#define ENET_EIR_MII_MASK 0x800000u
+#define ENET_EIR_MII_SHIFT 23
+#define ENET_EIR_RXB_MASK 0x1000000u
+#define ENET_EIR_RXB_SHIFT 24
+#define ENET_EIR_RXF_MASK 0x2000000u
+#define ENET_EIR_RXF_SHIFT 25
+#define ENET_EIR_TXB_MASK 0x4000000u
+#define ENET_EIR_TXB_SHIFT 26
+#define ENET_EIR_TXF_MASK 0x8000000u
+#define ENET_EIR_TXF_SHIFT 27
+#define ENET_EIR_GRA_MASK 0x10000000u
+#define ENET_EIR_GRA_SHIFT 28
+#define ENET_EIR_BABT_MASK 0x20000000u
+#define ENET_EIR_BABT_SHIFT 29
+#define ENET_EIR_BABR_MASK 0x40000000u
+#define ENET_EIR_BABR_SHIFT 30
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK 0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT 15
+#define ENET_EIMR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT 16
+#define ENET_EIMR_WAKEUP_MASK 0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT 17
+#define ENET_EIMR_PLR_MASK 0x40000u
+#define ENET_EIMR_PLR_SHIFT 18
+#define ENET_EIMR_UN_MASK 0x80000u
+#define ENET_EIMR_UN_SHIFT 19
+#define ENET_EIMR_RL_MASK 0x100000u
+#define ENET_EIMR_RL_SHIFT 20
+#define ENET_EIMR_LC_MASK 0x200000u
+#define ENET_EIMR_LC_SHIFT 21
+#define ENET_EIMR_EBERR_MASK 0x400000u
+#define ENET_EIMR_EBERR_SHIFT 22
+#define ENET_EIMR_MII_MASK 0x800000u
+#define ENET_EIMR_MII_SHIFT 23
+#define ENET_EIMR_RXB_MASK 0x1000000u
+#define ENET_EIMR_RXB_SHIFT 24
+#define ENET_EIMR_RXF_MASK 0x2000000u
+#define ENET_EIMR_RXF_SHIFT 25
+#define ENET_EIMR_TXB_MASK 0x4000000u
+#define ENET_EIMR_TXB_SHIFT 26
+#define ENET_EIMR_TXF_MASK 0x8000000u
+#define ENET_EIMR_TXF_SHIFT 27
+#define ENET_EIMR_GRA_MASK 0x10000000u
+#define ENET_EIMR_GRA_SHIFT 28
+#define ENET_EIMR_BABT_MASK 0x20000000u
+#define ENET_EIMR_BABT_SHIFT 29
+#define ENET_EIMR_BABR_MASK 0x40000000u
+#define ENET_EIMR_BABR_SHIFT 30
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK 0x1000000u
+#define ENET_RDAR_RDAR_SHIFT 24
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK 0x1000000u
+#define ENET_TDAR_TDAR_SHIFT 24
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK 0x1u
+#define ENET_ECR_RESET_SHIFT 0
+#define ENET_ECR_ETHEREN_MASK 0x2u
+#define ENET_ECR_ETHEREN_SHIFT 1
+#define ENET_ECR_MAGICEN_MASK 0x4u
+#define ENET_ECR_MAGICEN_SHIFT 2
+#define ENET_ECR_SLEEP_MASK 0x8u
+#define ENET_ECR_SLEEP_SHIFT 3
+#define ENET_ECR_EN1588_MASK 0x10u
+#define ENET_ECR_EN1588_SHIFT 4
+#define ENET_ECR_DBGEN_MASK 0x40u
+#define ENET_ECR_DBGEN_SHIFT 6
+#define ENET_ECR_STOPEN_MASK 0x80u
+#define ENET_ECR_STOPEN_SHIFT 7
+#define ENET_ECR_DBSWP_MASK 0x100u
+#define ENET_ECR_DBSWP_SHIFT 8
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK 0xFFFFu
+#define ENET_MMFR_DATA_SHIFT 0
+#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK 0x30000u
+#define ENET_MMFR_TA_SHIFT 16
+#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK 0x7C0000u
+#define ENET_MMFR_RA_SHIFT 18
+#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK 0xF800000u
+#define ENET_MMFR_PA_SHIFT 23
+#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK 0x30000000u
+#define ENET_MMFR_OP_SHIFT 28
+#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK 0xC0000000u
+#define ENET_MMFR_ST_SHIFT 30
+#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT 1
+#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK 0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT 7
+#define ENET_MSCR_HOLDTIME_MASK 0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT 8
+#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT 29
+#define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT 30
+#define ENET_MIBC_MIB_DIS_MASK 0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT 31
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK 0x1u
+#define ENET_RCR_LOOP_SHIFT 0
+#define ENET_RCR_DRT_MASK 0x2u
+#define ENET_RCR_DRT_SHIFT 1
+#define ENET_RCR_MII_MODE_MASK 0x4u
+#define ENET_RCR_MII_MODE_SHIFT 2
+#define ENET_RCR_PROM_MASK 0x8u
+#define ENET_RCR_PROM_SHIFT 3
+#define ENET_RCR_BC_REJ_MASK 0x10u
+#define ENET_RCR_BC_REJ_SHIFT 4
+#define ENET_RCR_FCE_MASK 0x20u
+#define ENET_RCR_FCE_SHIFT 5
+#define ENET_RCR_RMII_MODE_MASK 0x100u
+#define ENET_RCR_RMII_MODE_SHIFT 8
+#define ENET_RCR_RMII_10T_MASK 0x200u
+#define ENET_RCR_RMII_10T_SHIFT 9
+#define ENET_RCR_PADEN_MASK 0x1000u
+#define ENET_RCR_PADEN_SHIFT 12
+#define ENET_RCR_PAUFWD_MASK 0x2000u
+#define ENET_RCR_PAUFWD_SHIFT 13
+#define ENET_RCR_CRCFWD_MASK 0x4000u
+#define ENET_RCR_CRCFWD_SHIFT 14
+#define ENET_RCR_CFEN_MASK 0x8000u
+#define ENET_RCR_CFEN_SHIFT 15
+#define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT 16
+#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK 0x40000000u
+#define ENET_RCR_NLC_SHIFT 30
+#define ENET_RCR_GRS_MASK 0x80000000u
+#define ENET_RCR_GRS_SHIFT 31
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK 0x1u
+#define ENET_TCR_GTS_SHIFT 0
+#define ENET_TCR_FDEN_MASK 0x4u
+#define ENET_TCR_FDEN_SHIFT 2
+#define ENET_TCR_TFC_PAUSE_MASK 0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT 3
+#define ENET_TCR_RFC_PAUSE_MASK 0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT 4
+#define ENET_TCR_ADDSEL_MASK 0xE0u
+#define ENET_TCR_ADDSEL_SHIFT 5
+#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK 0x100u
+#define ENET_TCR_ADDINS_SHIFT 8
+#define ENET_TCR_CRCFWD_MASK 0x200u
+#define ENET_TCR_CRCFWD_SHIFT 9
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT 0
+#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK 0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT 0
+#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT 16
+#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT 0
+#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK 0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT 16
+#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT 0
+#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT 0
+#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT 0
+#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT 0
+#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK 0x3Fu
+#define ENET_TFWR_TFWR_SHIFT 0
+#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK 0x100u
+#define ENET_TFWR_STRFWD_SHIFT 8
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT 3
+#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT 3
+#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT 4
+#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
+#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
+#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
+#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
+#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
+#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
+#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
+#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
+#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK 0x1Fu
+#define ENET_TIPG_IPG_SHIFT 0
+#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT 0
+#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK 0x1u
+#define ENET_TACC_SHIFT16_SHIFT 0
+#define ENET_TACC_IPCHK_MASK 0x8u
+#define ENET_TACC_IPCHK_SHIFT 3
+#define ENET_TACC_PROCHK_MASK 0x10u
+#define ENET_TACC_PROCHK_SHIFT 4
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK 0x1u
+#define ENET_RACC_PADREM_SHIFT 0
+#define ENET_RACC_IPDIS_MASK 0x2u
+#define ENET_RACC_IPDIS_SHIFT 1
+#define ENET_RACC_PRODIS_MASK 0x4u
+#define ENET_RACC_PRODIS_SHIFT 2
+#define ENET_RACC_LINEDIS_MASK 0x40u
+#define ENET_RACC_LINEDIS_SHIFT 6
+#define ENET_RACC_SHIFT16_MASK 0x80u
+#define ENET_RACC_SHIFT16_SHIFT 7
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
+#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
+#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
+#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
+#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
+#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT 0
+#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
+#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
+#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT 0
+#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT 0
+#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
+#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
+#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
+#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
+#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
+#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
+#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
+#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
+#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT 0
+#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT 0
+#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT 0
+#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
+#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
+#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
+#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
+#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
+#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
+#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
+#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT 0
+#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
+#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT 0
+#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
+#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
+#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
+#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK 0x1u
+#define ENET_ATCR_EN_SHIFT 0
+#define ENET_ATCR_OFFEN_MASK 0x4u
+#define ENET_ATCR_OFFEN_SHIFT 2
+#define ENET_ATCR_OFFRST_MASK 0x8u
+#define ENET_ATCR_OFFRST_SHIFT 3
+#define ENET_ATCR_PEREN_MASK 0x10u
+#define ENET_ATCR_PEREN_SHIFT 4
+#define ENET_ATCR_PINPER_MASK 0x80u
+#define ENET_ATCR_PINPER_SHIFT 7
+#define ENET_ATCR_RESTART_MASK 0x200u
+#define ENET_ATCR_RESTART_SHIFT 9
+#define ENET_ATCR_CAPTURE_MASK 0x800u
+#define ENET_ATCR_CAPTURE_SHIFT 11
+#define ENET_ATCR_SLAVE_MASK 0x2000u
+#define ENET_ATCR_SLAVE_SHIFT 13
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT 0
+#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT 0
+#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT 0
+#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT 0
+#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK 0x7Fu
+#define ENET_ATINC_INC_SHIFT 0
+#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT 8
+#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT 0
+#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK 0x1u
+#define ENET_TGSR_TF0_SHIFT 0
+#define ENET_TGSR_TF1_MASK 0x2u
+#define ENET_TGSR_TF1_SHIFT 1
+#define ENET_TGSR_TF2_MASK 0x4u
+#define ENET_TGSR_TF2_SHIFT 2
+#define ENET_TGSR_TF3_MASK 0x8u
+#define ENET_TGSR_TF3_SHIFT 3
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK 0x1u
+#define ENET_TCSR_TDRE_SHIFT 0
+#define ENET_TCSR_TMODE_MASK 0x3Cu
+#define ENET_TCSR_TMODE_SHIFT 2
+#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK 0x40u
+#define ENET_TCSR_TIE_SHIFT 6
+#define ENET_TCSR_TF_MASK 0x80u
+#define ENET_TCSR_TF_SHIFT 7
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT 0
+#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS { ENET_Receive_IRQn }
+#define ENET_Error_IRQS { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ENET - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR ENET_EIR_REG(ENET)
+#define ENET_EIMR ENET_EIMR_REG(ENET)
+#define ENET_RDAR ENET_RDAR_REG(ENET)
+#define ENET_TDAR ENET_TDAR_REG(ENET)
+#define ENET_ECR ENET_ECR_REG(ENET)
+#define ENET_MMFR ENET_MMFR_REG(ENET)
+#define ENET_MSCR ENET_MSCR_REG(ENET)
+#define ENET_MIBC ENET_MIBC_REG(ENET)
+#define ENET_RCR ENET_RCR_REG(ENET)
+#define ENET_TCR ENET_TCR_REG(ENET)
+#define ENET_PALR ENET_PALR_REG(ENET)
+#define ENET_PAUR ENET_PAUR_REG(ENET)
+#define ENET_OPD ENET_OPD_REG(ENET)
+#define ENET_IAUR ENET_IAUR_REG(ENET)
+#define ENET_IALR ENET_IALR_REG(ENET)
+#define ENET_GAUR ENET_GAUR_REG(ENET)
+#define ENET_GALR ENET_GALR_REG(ENET)
+#define ENET_TFWR ENET_TFWR_REG(ENET)
+#define ENET_RDSR ENET_RDSR_REG(ENET)
+#define ENET_TDSR ENET_TDSR_REG(ENET)
+#define ENET_MRBR ENET_MRBR_REG(ENET)
+#define ENET_RSFL ENET_RSFL_REG(ENET)
+#define ENET_RSEM ENET_RSEM_REG(ENET)
+#define ENET_RAEM ENET_RAEM_REG(ENET)
+#define ENET_RAFL ENET_RAFL_REG(ENET)
+#define ENET_TSEM ENET_TSEM_REG(ENET)
+#define ENET_TAEM ENET_TAEM_REG(ENET)
+#define ENET_TAFL ENET_TAFL_REG(ENET)
+#define ENET_TIPG ENET_TIPG_REG(ENET)
+#define ENET_FTRL ENET_FTRL_REG(ENET)
+#define ENET_TACC ENET_TACC_REG(ENET)
+#define ENET_RACC ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR ENET_ATCR_REG(ENET)
+#define ENET_ATVR ENET_ATVR_REG(ENET)
+#define ENET_ATOFF ENET_ATOFF_REG(ENET)
+#define ENET_ATPER ENET_ATPER_REG(ENET)
+#define ENET_ATCOR ENET_ATCOR_REG(ENET)
+#define ENET_ATINC ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR ENET_TGSR_REG(ENET)
+#define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base) ((base)->CTRL)
+#define EWM_SERV_REG(base) ((base)->SERV)
+#define EWM_CMPL_REG(base) ((base)->CMPL)
+#define EWM_CMPH_REG(base) ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL EWM_CTRL_REG(EWM)
+#define EWM_SERV EWM_SERV_REG(EWM)
+#define EWM_CMPL EWM_CMPL_REG(EWM)
+#define EWM_CMPH EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0xC */
+ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+ } CS[6];
+ uint8_t RESERVED_0[24];
+ __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
+#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK 0xFFFF0000u
+#define FB_CSAR_BA_SHIFT 16
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK 0x1u
+#define FB_CSMR_V_SHIFT 0
+#define FB_CSMR_WP_MASK 0x100u
+#define FB_CSMR_WP_SHIFT 8
+#define FB_CSMR_BAM_MASK 0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT 16
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK 0x8u
+#define FB_CSCR_BSTW_SHIFT 3
+#define FB_CSCR_BSTR_MASK 0x10u
+#define FB_CSCR_BSTR_SHIFT 4
+#define FB_CSCR_BEM_MASK 0x20u
+#define FB_CSCR_BEM_SHIFT 5
+#define FB_CSCR_PS_MASK 0xC0u
+#define FB_CSCR_PS_SHIFT 6
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK 0x100u
+#define FB_CSCR_AA_SHIFT 8
+#define FB_CSCR_BLS_MASK 0x200u
+#define FB_CSCR_BLS_SHIFT 9
+#define FB_CSCR_WS_MASK 0xFC00u
+#define FB_CSCR_WS_SHIFT 10
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK 0x30000u
+#define FB_CSCR_WRAH_SHIFT 16
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK 0xC0000u
+#define FB_CSCR_RDAH_SHIFT 18
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK 0x300000u
+#define FB_CSCR_ASET_SHIFT 20
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK 0x400000u
+#define FB_CSCR_EXTS_SHIFT 22
+#define FB_CSCR_SWSEN_MASK 0x800000u
+#define FB_CSCR_SWSEN_SHIFT 23
+#define FB_CSCR_SWS_MASK 0xFC000000u
+#define FB_CSCR_SWS_SHIFT 26
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK 0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT 12
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK 0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT 16
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK 0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT 20
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK 0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT 24
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT 28
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS { FB }
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0 FB_CSAR_REG(FB,0)
+#define FB_CSMR0 FB_CSMR_REG(FB,0)
+#define FB_CSCR0 FB_CSCR_REG(FB,0)
+#define FB_CSAR1 FB_CSAR_REG(FB,1)
+#define FB_CSMR1 FB_CSMR_REG(FB,1)
+#define FB_CSCR1 FB_CSCR_REG(FB,1)
+#define FB_CSAR2 FB_CSAR_REG(FB,2)
+#define FB_CSMR2 FB_CSMR_REG(FB,2)
+#define FB_CSCR2 FB_CSCR_REG(FB,2)
+#define FB_CSAR3 FB_CSAR_REG(FB,3)
+#define FB_CSMR3 FB_CSMR_REG(FB,3)
+#define FB_CSCR3 FB_CSCR_REG(FB,3)
+#define FB_CSAR4 FB_CSAR_REG(FB,4)
+#define FB_CSMR4 FB_CSMR_REG(FB,4)
+#define FB_CSCR4 FB_CSCR_REG(FB,4)
+#define FB_CSAR5 FB_CSAR_REG(FB,5)
+#define FB_CSMR5 FB_CSMR_REG(FB,5)
+#define FB_CSCR5 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index) FB_CSAR_REG(FB,index)
+#define FB_CSMR(index) FB_CSMR_REG(FB,index)
+#define FB_CSCR(index) FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
+ __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[244];
+ __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+ __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+ __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+ uint8_t RESERVED_1[192];
+ struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
+ __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+ __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+ } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base) ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
+#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK 0x300u
+#define FMC_PFAPR_M4AP_SHIFT 8
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK 0xC00u
+#define FMC_PFAPR_M5AP_SHIFT 10
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK 0x3000u
+#define FMC_PFAPR_M6AP_SHIFT 12
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK 0xC000u
+#define FMC_PFAPR_M7AP_SHIFT 14
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+#define FMC_PFAPR_M4PFD_MASK 0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT 20
+#define FMC_PFAPR_M5PFD_MASK 0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT 21
+#define FMC_PFAPR_M6PFD_MASK 0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT 22
+#define FMC_PFAPR_M7PFD_MASK 0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT 23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK 0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT 0
+#define FMC_PFB1CR_B1IPE_MASK 0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT 1
+#define FMC_PFB1CR_B1DPE_MASK 0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT 2
+#define FMC_PFB1CR_B1ICE_MASK 0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT 3
+#define FMC_PFB1CR_B1DCE_MASK 0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT 4
+#define FMC_PFB1CR_B1MW_MASK 0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT 17
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT 28
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK 0x1u
+#define FMC_TAGVDW0S_valid_SHIFT 0
+#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT 5
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK 0x1u
+#define FMC_TAGVDW1S_valid_SHIFT 0
+#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT 5
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK 0x1u
+#define FMC_TAGVDW2S_valid_SHIFT 0
+#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT 5
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK 0x1u
+#define FMC_TAGVDW3S_valid_SHIFT 0
+#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT 5
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT 0
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT 0
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFE - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFE_FSEC_REG(base) ((base)->FSEC)
+#define FTFE_FOPT_REG(base) ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base) ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base) ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT 0
+#define FTFE_FSTAT_FPVIOL_MASK 0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT 4
+#define FTFE_FSTAT_ACCERR_MASK 0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT 5
+#define FTFE_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT 6
+#define FTFE_FSTAT_CCIF_MASK 0x80u
+#define FTFE_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK 0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT 0
+#define FTFE_FCNFG_RAMRDY_MASK 0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT 1
+#define FTFE_FCNFG_PFLSH_MASK 0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT 2
+#define FTFE_FCNFG_SWAP_MASK 0x8u
+#define FTFE_FCNFG_SWAP_SHIFT 3
+#define FTFE_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT 4
+#define FTFE_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT 5
+#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFE_FCNFG_CCIE_MASK 0x80u
+#define FTFE_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK 0x3u
+#define FTFE_FSEC_SEC_SHIFT 0
+#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK 0xCu
+#define FTFE_FSEC_FSLACC_SHIFT 2
+#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK 0x30u
+#define FTFE_FSEC_MEEN_SHIFT 4
+#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK 0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT 6
+#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK 0xFFu
+#define FTFE_FOPT_OPT_SHIFT 0
+#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT 0
+#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT 0
+#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT 0
+#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT 0
+#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT 0
+#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT 0
+#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT 0
+#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT 0
+#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT 0
+#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT 0
+#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT 0
+#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT 0
+#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK 0xFFu
+#define FTFE_FPROT3_PROT_SHIFT 0
+#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK 0xFFu
+#define FTFE_FPROT2_PROT_SHIFT 0
+#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK 0xFFu
+#define FTFE_FPROT1_PROT_SHIFT 0
+#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK 0xFFu
+#define FTFE_FPROT0_PROT_SHIFT 0
+#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK 0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT 0
+#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK 0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT 0
+#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFE - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base) ((base)->SC)
+#define FTM_CNT_REG(base) ((base)->CNT)
+#define FTM_MOD_REG(base) ((base)->MOD)
+#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base) ((base)->CNTIN)
+#define FTM_STATUS_REG(base) ((base)->STATUS)
+#define FTM_MODE_REG(base) ((base)->MODE)
+#define FTM_SYNC_REG(base) ((base)->SYNC)
+#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base) ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
+#define FTM_POL_REG(base) ((base)->POL)
+#define FTM_FMS_REG(base) ((base)->FMS)
+#define FTM_FILTER_REG(base) ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
+#define FTM_CONF_REG(base) ((base)->CONF)
+#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC FTM_SC_REG(FTM0)
+#define FTM0_CNT FTM_CNT_REG(FTM0)
+#define FTM0_MOD FTM_MOD_REG(FTM0)
+#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS FTM_STATUS_REG(FTM0)
+#define FTM0_MODE FTM_MODE_REG(FTM0)
+#define FTM0_SYNC FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL FTM_POL_REG(FTM0)
+#define FTM0_FMS FTM_FMS_REG(FTM0)
+#define FTM0_FILTER FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC FTM_SC_REG(FTM1)
+#define FTM1_CNT FTM_CNT_REG(FTM1)
+#define FTM1_MOD FTM_MOD_REG(FTM1)
+#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS FTM_STATUS_REG(FTM1)
+#define FTM1_MODE FTM_MODE_REG(FTM1)
+#define FTM1_SYNC FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL FTM_POL_REG(FTM1)
+#define FTM1_FMS FTM_FMS_REG(FTM1)
+#define FTM1_FILTER FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC FTM_SC_REG(FTM2)
+#define FTM2_CNT FTM_CNT_REG(FTM2)
+#define FTM2_MOD FTM_MOD_REG(FTM2)
+#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS FTM_STATUS_REG(FTM2)
+#define FTM2_MODE FTM_MODE_REG(FTM2)
+#define FTM2_SYNC FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL FTM_POL_REG(FTM2)
+#define FTM2_FMS FTM_FMS_REG(FTM2)
+#define FTM2_FILTER FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC FTM_SC_REG(FTM3)
+#define FTM3_CNT FTM_CNT_REG(FTM3)
+#define FTM3_MOD FTM_MOD_REG(FTM3)
+#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS FTM_STATUS_REG(FTM3)
+#define FTM3_MODE FTM_MODE_REG(FTM3)
+#define FTM3_SYNC FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL FTM_POL_REG(FTM3)
+#define FTM3_FMS FTM_FMS_REG(FTM3)
+#define FTM3_FILTER FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2 ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1 I2C_A1_REG(I2C2)
+#define I2C2_F I2C_F_REG(I2C2)
+#define I2C2_C1 I2C_C1_REG(I2C2)
+#define I2C2_S I2C_S_REG(I2C2)
+#define I2C2_D I2C_D_REG(I2C2)
+#define I2C2_C2 I2C_C2_REG(I2C2)
+#define I2C2_FLT I2C_FLT_REG(I2C2)
+#define I2C2_RA I2C_RA_REG(I2C2)
+#define I2C2_SMB I2C_SMB_REG(I2C2)
+#define I2C2_A2 I2C_A2_REG(I2C2)
+#define I2C2_SLTH I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR1_REG(base) ((base)->TCR1)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TFR_REG(base,index) ((base)->TFR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR1_REG(base) ((base)->RCR1)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RFR_REG(base,index) ((base)->RFR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+#define I2S_MDR_REG(base) ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+#define I2S0_MDR I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+#define LLWU_RST_REG(base) ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+#define LLWU_RST LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTimer_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_C3_REG(base) ((base)->C3)
+#define MCG_C4_REG(base) ((base)->C4)
+#define MCG_C5_REG(base) ((base)->C5)
+#define MCG_C6_REG(base) ((base)->C6)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_ATCVH_REG(base) ((base)->ATCVH)
+#define MCG_ATCVL_REG(base) ((base)->ATCVL)
+#define MCG_C7_REG(base) ((base)->C7)
+#define MCG_C8_REG(base) ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS_MASK 0x4u
+#define MCG_C2_EREFS_SHIFT 2
+#define MCG_C2_HGO_MASK 0x8u
+#define MCG_C2_HGO_SHIFT 3
+#define MCG_C2_RANGE_MASK 0x30u
+#define MCG_C2_RANGE_SHIFT 4
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x3u
+#define MCG_C7_OSCSEL_SHIFT 0
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_C3 MCG_C3_REG(MCG)
+#define MCG_C4 MCG_C4_REG(MCG)
+#define MCG_C5 MCG_C5_REG(MCG)
+#define MCG_C6 MCG_C6_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_ATCVH MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL MCG_ATCVL_REG(MCG)
+#define MCG_C7 MCG_C7_REG(MCG)
+#define MCG_C8 MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t CR; /**< Control Register, offset: 0xC */
+ __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
+ __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
+ __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
+ __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_CR_REG(base) ((base)->CR)
+#define MCM_ISCR_REG(base) ((base)->ISCR)
+#define MCM_ETBCC_REG(base) ((base)->ETBCC)
+#define MCM_ETBRL_REG(base) ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
+#define MCM_PID_REG(base) ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK 0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT 24
+#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK 0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT 26
+#define MCM_CR_SRAMLAP_MASK 0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT 28
+#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK 0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT 30
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK 0x2u
+#define MCM_ISCR_IRQ_SHIFT 1
+#define MCM_ISCR_NMI_MASK 0x4u
+#define MCM_ISCR_NMI_SHIFT 2
+#define MCM_ISCR_DHREQ_MASK 0x8u
+#define MCM_ISCR_DHREQ_SHIFT 3
+#define MCM_ISCR_FIOC_MASK 0x100u
+#define MCM_ISCR_FIOC_SHIFT 8
+#define MCM_ISCR_FDZC_MASK 0x200u
+#define MCM_ISCR_FDZC_SHIFT 9
+#define MCM_ISCR_FOFC_MASK 0x400u
+#define MCM_ISCR_FOFC_SHIFT 10
+#define MCM_ISCR_FUFC_MASK 0x800u
+#define MCM_ISCR_FUFC_SHIFT 11
+#define MCM_ISCR_FIXC_MASK 0x1000u
+#define MCM_ISCR_FIXC_SHIFT 12
+#define MCM_ISCR_FIDC_MASK 0x8000u
+#define MCM_ISCR_FIDC_SHIFT 15
+#define MCM_ISCR_FIOCE_MASK 0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT 24
+#define MCM_ISCR_FDZCE_MASK 0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT 25
+#define MCM_ISCR_FOFCE_MASK 0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT 26
+#define MCM_ISCR_FUFCE_MASK 0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT 27
+#define MCM_ISCR_FIXCE_MASK 0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT 28
+#define MCM_ISCR_FIDCE_MASK 0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT 31
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK 0x1u
+#define MCM_ETBCC_CNTEN_SHIFT 0
+#define MCM_ETBCC_RSPT_MASK 0x6u
+#define MCM_ETBCC_RSPT_SHIFT 1
+#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK 0x8u
+#define MCM_ETBCC_RLRQ_SHIFT 3
+#define MCM_ETBCC_ETDIS_MASK 0x10u
+#define MCM_ETBCC_ETDIS_SHIFT 4
+#define MCM_ETBCC_ITDIS_MASK 0x20u
+#define MCM_ETBCC_ITDIS_SHIFT 5
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK 0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT 0
+#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK 0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT 0
+#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK 0xFFu
+#define MCM_PID_PID_SHIFT 0
+#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_CR MCM_CR_REG(MCM)
+#define MCM_ISCR MCM_ISCR_REG(MCM)
+#define MCM_ETBCC MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
+#define MCM_PID MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MPU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ struct { /* offset: 0x10, array step: 0x8 */
+ __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+ __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+ } SP[5];
+ uint8_t RESERVED_1[968];
+ __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+ uint8_t RESERVED_2[832];
+ __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MPU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base) ((base)->CESR)
+#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
+#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
+#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
+#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MPU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK 0x1u
+#define MPU_CESR_VLD_SHIFT 0
+#define MPU_CESR_NRGD_MASK 0xF00u
+#define MPU_CESR_NRGD_SHIFT 8
+#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK 0xF000u
+#define MPU_CESR_NSP_SHIFT 12
+#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK 0xF0000u
+#define MPU_CESR_HRL_SHIFT 16
+#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK 0xF8000000u
+#define MPU_CESR_SPERR_SHIFT 27
+#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT 0
+#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK 0x1u
+#define MPU_EDR_ERW_SHIFT 0
+#define MPU_EDR_EATTR_MASK 0xEu
+#define MPU_EDR_EATTR_SHIFT 1
+#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK 0xF0u
+#define MPU_EDR_EMN_SHIFT 4
+#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK 0xFF00u
+#define MPU_EDR_EPID_SHIFT 8
+#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK 0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT 16
+#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK 0x1u
+#define MPU_WORD_VLD_SHIFT 0
+#define MPU_WORD_M0UM_MASK 0x7u
+#define MPU_WORD_M0UM_SHIFT 0
+#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK 0x18u
+#define MPU_WORD_M0SM_SHIFT 3
+#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK 0x20u
+#define MPU_WORD_M0PE_SHIFT 5
+#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT 5
+#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT 5
+#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK 0x1C0u
+#define MPU_WORD_M1UM_SHIFT 6
+#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK 0x600u
+#define MPU_WORD_M1SM_SHIFT 9
+#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK 0x800u
+#define MPU_WORD_M1PE_SHIFT 11
+#define MPU_WORD_M2UM_MASK 0x7000u
+#define MPU_WORD_M2UM_SHIFT 12
+#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK 0x18000u
+#define MPU_WORD_M2SM_SHIFT 15
+#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK 0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT 16
+#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK 0x20000u
+#define MPU_WORD_M2PE_SHIFT 17
+#define MPU_WORD_M3UM_MASK 0x1C0000u
+#define MPU_WORD_M3UM_SHIFT 18
+#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK 0x600000u
+#define MPU_WORD_M3SM_SHIFT 21
+#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK 0x800000u
+#define MPU_WORD_M3PE_SHIFT 23
+#define MPU_WORD_PID_MASK 0xFF000000u
+#define MPU_WORD_PID_SHIFT 24
+#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK 0x1000000u
+#define MPU_WORD_M4WE_SHIFT 24
+#define MPU_WORD_M4RE_MASK 0x2000000u
+#define MPU_WORD_M4RE_SHIFT 25
+#define MPU_WORD_M5WE_MASK 0x4000000u
+#define MPU_WORD_M5WE_SHIFT 26
+#define MPU_WORD_M5RE_MASK 0x8000000u
+#define MPU_WORD_M5RE_SHIFT 27
+#define MPU_WORD_M6WE_MASK 0x10000000u
+#define MPU_WORD_M6WE_SHIFT 28
+#define MPU_WORD_M6RE_MASK 0x20000000u
+#define MPU_WORD_M6RE_SHIFT 29
+#define MPU_WORD_M7WE_MASK 0x40000000u
+#define MPU_WORD_M7WE_SHIFT 30
+#define MPU_WORD_M7RE_MASK 0x80000000u
+#define MPU_WORD_M7RE_SHIFT 31
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK 0x7u
+#define MPU_RGDAAC_M0UM_SHIFT 0
+#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK 0x18u
+#define MPU_RGDAAC_M0SM_SHIFT 3
+#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK 0x20u
+#define MPU_RGDAAC_M0PE_SHIFT 5
+#define MPU_RGDAAC_M1UM_MASK 0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT 6
+#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK 0x600u
+#define MPU_RGDAAC_M1SM_SHIFT 9
+#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK 0x800u
+#define MPU_RGDAAC_M1PE_SHIFT 11
+#define MPU_RGDAAC_M2UM_MASK 0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT 12
+#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK 0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT 15
+#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK 0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT 17
+#define MPU_RGDAAC_M3UM_MASK 0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT 18
+#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK 0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT 21
+#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK 0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT 23
+#define MPU_RGDAAC_M4WE_MASK 0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT 24
+#define MPU_RGDAAC_M4RE_MASK 0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT 25
+#define MPU_RGDAAC_M5WE_MASK 0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT 26
+#define MPU_RGDAAC_M5RE_MASK 0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT 27
+#define MPU_RGDAAC_M6WE_MASK 0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT 28
+#define MPU_RGDAAC_M6RE_MASK 0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT 29
+#define MPU_RGDAAC_M7WE_MASK 0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT 30
+#define MPU_RGDAAC_M7RE_MASK 0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS { MPU }
+
+/* ----------------------------------------------------------------------------
+ -- MPU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR MPU_CESR_REG(MPU)
+#define MPU_EAR0 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index) MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index) MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+#define NV_FEPROT_REG(base) ((base)->FEPROT)
+#define NV_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[2];
+ uint8_t RESERVED_0[240];
+ struct { /* offset: 0x150, array step: 0x8 */
+ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
+ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base) ((base)->SC)
+#define PDB_MOD_REG(base) ((base)->MOD)
+#define PDB_CNT_REG(base) ((base)->CNT)
+#define PDB_IDLY_REG(base) ((base)->IDLY)
+#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
+#define PDB_S_REG(base,index) ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base) ((base)->POEN)
+#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK 0x1u
+#define PDB_INTC_TOE_SHIFT 0
+#define PDB_INTC_EXT_MASK 0x2u
+#define PDB_INTC_EXT_SHIFT 1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK 0xFFFFu
+#define PDB_INT_INT_SHIFT 0
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC PDB_SC_REG(PDB0)
+#define PDB0_MOD PDB_MOD_REG(PDB0)
+#define PDB0_CNT PDB_CNT_REG(PDB0)
+#define PDB0_IDLY PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
+#define PDB0_POEN PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
+#define PDB0_S(index) PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+#define PORT_DFER_REG(base) ((base)->DFER)
+#define PORT_DFCR_REG(base) ((base)->DFCR)
+#define PORT_DFWR_REG(base) ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+#define PORTD_DFER PORT_DFER_REG(PORTD)
+#define PORTD_DFCR PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_MR_REG(base) ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
+ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
+ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base) ((base)->CR)
+#define RNG_SR_REG(base) ((base)->SR)
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_OR_REG(base) ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK 0x1u
+#define RNG_CR_GO_SHIFT 0
+#define RNG_CR_HA_MASK 0x2u
+#define RNG_CR_HA_SHIFT 1
+#define RNG_CR_INTM_MASK 0x4u
+#define RNG_CR_INTM_SHIFT 2
+#define RNG_CR_CLRI_MASK 0x8u
+#define RNG_CR_CLRI_SHIFT 3
+#define RNG_CR_SLP_MASK 0x10u
+#define RNG_CR_SLP_SHIFT 4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK 0x1u
+#define RNG_SR_SECV_SHIFT 0
+#define RNG_SR_LRS_MASK 0x2u
+#define RNG_SR_LRS_SHIFT 1
+#define RNG_SR_ORU_MASK 0x4u
+#define RNG_SR_ORU_SHIFT 2
+#define RNG_SR_ERRI_MASK 0x8u
+#define RNG_SR_ERRI_SHIFT 3
+#define RNG_SR_SLP_MASK 0x10u
+#define RNG_SR_SLP_SHIFT 4
+#define RNG_SR_OREG_LVL_MASK 0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT 8
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT 16
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT 0
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT 0
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR RNG_CR_REG(RNG)
+#define RNG_SR RNG_SR_REG(RNG)
+#define RNG_ER RNG_ER_REG(RNG)
+#define RNG_OR RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+#define RTC_WAR_REG(base) ((base)->WAR)
+#define RTC_RAR_REG(base) ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+#define RTC_WAR RTC_WAR_REG(RTC)
+#define RTC_RAR RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
+ __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
+ __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
+ __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
+ __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
+ __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
+ __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
+ __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
+ __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
+ __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
+ __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
+ __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
+ __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
+ __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
+ __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
+ uint8_t RESERVED_1[100];
+ __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
+ __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
+ uint8_t RESERVED_2[52];
+ __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SDHC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base) ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
+#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base) ((base)->WML)
+#define SDHC_FEVT_REG(base) ((base)->FEVT)
+#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT 2
+#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT 0
+#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT 16
+#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT 0
+#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK 0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT 0
+#define SDHC_XFERTYP_BCEN_MASK 0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT 1
+#define SDHC_XFERTYP_AC12EN_MASK 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT 2
+#define SDHC_XFERTYP_DTDSEL_MASK 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT 4
+#define SDHC_XFERTYP_MSBSEL_MASK 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT 5
+#define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT 16
+#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK 0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT 19
+#define SDHC_XFERTYP_CICEN_MASK 0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT 20
+#define SDHC_XFERTYP_DPSEL_MASK 0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT 21
+#define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT 22
+#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT 24
+#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT 0
+#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK 0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT 0
+#define SDHC_PRSSTAT_CDIHB_MASK 0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT 1
+#define SDHC_PRSSTAT_DLA_MASK 0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT 2
+#define SDHC_PRSSTAT_SDSTB_MASK 0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT 3
+#define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT 4
+#define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT 5
+#define SDHC_PRSSTAT_PEROFF_MASK 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT 6
+#define SDHC_PRSSTAT_SDOFF_MASK 0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT 7
+#define SDHC_PRSSTAT_WTA_MASK 0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT 8
+#define SDHC_PRSSTAT_RTA_MASK 0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT 9
+#define SDHC_PRSSTAT_BWEN_MASK 0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT 10
+#define SDHC_PRSSTAT_BREN_MASK 0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT 11
+#define SDHC_PRSSTAT_CINS_MASK 0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT 16
+#define SDHC_PRSSTAT_CLSL_MASK 0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT 23
+#define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT 24
+#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK 0x1u
+#define SDHC_PROCTL_LCTL_SHIFT 0
+#define SDHC_PROCTL_DTW_MASK 0x6u
+#define SDHC_PROCTL_DTW_SHIFT 1
+#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK 0x8u
+#define SDHC_PROCTL_D3CD_SHIFT 3
+#define SDHC_PROCTL_EMODE_MASK 0x30u
+#define SDHC_PROCTL_EMODE_SHIFT 4
+#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK 0x40u
+#define SDHC_PROCTL_CDTL_SHIFT 6
+#define SDHC_PROCTL_CDSS_MASK 0x80u
+#define SDHC_PROCTL_CDSS_SHIFT 7
+#define SDHC_PROCTL_DMAS_MASK 0x300u
+#define SDHC_PROCTL_DMAS_SHIFT 8
+#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT 16
+#define SDHC_PROCTL_CREQ_MASK 0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT 17
+#define SDHC_PROCTL_RWCTL_MASK 0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT 18
+#define SDHC_PROCTL_IABG_MASK 0x80000u
+#define SDHC_PROCTL_IABG_SHIFT 19
+#define SDHC_PROCTL_WECINT_MASK 0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT 24
+#define SDHC_PROCTL_WECINS_MASK 0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT 25
+#define SDHC_PROCTL_WECRM_MASK 0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT 26
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK 0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT 0
+#define SDHC_SYSCTL_HCKEN_MASK 0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT 1
+#define SDHC_SYSCTL_PEREN_MASK 0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT 2
+#define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT 3
+#define SDHC_SYSCTL_DVS_MASK 0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT 4
+#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT 8
+#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT 16
+#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK 0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT 24
+#define SDHC_SYSCTL_RSTC_MASK 0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT 25
+#define SDHC_SYSCTL_RSTD_MASK 0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT 26
+#define SDHC_SYSCTL_INITA_MASK 0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT 27
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK 0x1u
+#define SDHC_IRQSTAT_CC_SHIFT 0
+#define SDHC_IRQSTAT_TC_MASK 0x2u
+#define SDHC_IRQSTAT_TC_SHIFT 1
+#define SDHC_IRQSTAT_BGE_MASK 0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT 2
+#define SDHC_IRQSTAT_DINT_MASK 0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT 3
+#define SDHC_IRQSTAT_BWR_MASK 0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT 4
+#define SDHC_IRQSTAT_BRR_MASK 0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT 5
+#define SDHC_IRQSTAT_CINS_MASK 0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT 6
+#define SDHC_IRQSTAT_CRM_MASK 0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT 7
+#define SDHC_IRQSTAT_CINT_MASK 0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT 8
+#define SDHC_IRQSTAT_CTOE_MASK 0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT 16
+#define SDHC_IRQSTAT_CCE_MASK 0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT 17
+#define SDHC_IRQSTAT_CEBE_MASK 0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT 18
+#define SDHC_IRQSTAT_CIE_MASK 0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT 19
+#define SDHC_IRQSTAT_DTOE_MASK 0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT 20
+#define SDHC_IRQSTAT_DCE_MASK 0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT 21
+#define SDHC_IRQSTAT_DEBE_MASK 0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT 22
+#define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT 24
+#define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT 28
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT 0
+#define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT 1
+#define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT 2
+#define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
+#define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
+#define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
+#define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT 6
+#define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
+#define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
+#define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
+#define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT 17
+#define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
+#define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT 19
+#define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
+#define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT 21
+#define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
+#define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
+#define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT 0
+#define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT 1
+#define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
+#define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
+#define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
+#define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
+#define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
+#define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
+#define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
+#define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
+#define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
+#define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
+#define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
+#define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
+#define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
+#define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
+#define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
+#define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT 0
+#define SDHC_AC12ERR_AC12TOE_MASK 0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT 1
+#define SDHC_AC12ERR_AC12EBE_MASK 0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT 2
+#define SDHC_AC12ERR_AC12CE_MASK 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT 3
+#define SDHC_AC12ERR_AC12IE_MASK 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT 4
+#define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK 0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT 16
+#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT 20
+#define SDHC_HTCAPBLT_HSS_MASK 0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT 21
+#define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT 22
+#define SDHC_HTCAPBLT_SRS_MASK 0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT 23
+#define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT 24
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK 0xFFu
+#define SDHC_WML_RDWML_SHIFT 0
+#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK 0xFF0000u
+#define SDHC_WML_WRWML_SHIFT 16
+#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK 0x1u
+#define SDHC_FEVT_AC12NE_SHIFT 0
+#define SDHC_FEVT_AC12TOE_MASK 0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT 1
+#define SDHC_FEVT_AC12CE_MASK 0x4u
+#define SDHC_FEVT_AC12CE_SHIFT 2
+#define SDHC_FEVT_AC12EBE_MASK 0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT 3
+#define SDHC_FEVT_AC12IE_MASK 0x10u
+#define SDHC_FEVT_AC12IE_SHIFT 4
+#define SDHC_FEVT_CNIBAC12E_MASK 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT 7
+#define SDHC_FEVT_CTOE_MASK 0x10000u
+#define SDHC_FEVT_CTOE_SHIFT 16
+#define SDHC_FEVT_CCE_MASK 0x20000u
+#define SDHC_FEVT_CCE_SHIFT 17
+#define SDHC_FEVT_CEBE_MASK 0x40000u
+#define SDHC_FEVT_CEBE_SHIFT 18
+#define SDHC_FEVT_CIE_MASK 0x80000u
+#define SDHC_FEVT_CIE_SHIFT 19
+#define SDHC_FEVT_DTOE_MASK 0x100000u
+#define SDHC_FEVT_DTOE_SHIFT 20
+#define SDHC_FEVT_DCE_MASK 0x200000u
+#define SDHC_FEVT_DCE_SHIFT 21
+#define SDHC_FEVT_DEBE_MASK 0x400000u
+#define SDHC_FEVT_DEBE_SHIFT 22
+#define SDHC_FEVT_AC12E_MASK 0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT 24
+#define SDHC_FEVT_DMAE_MASK 0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT 28
+#define SDHC_FEVT_CINT_MASK 0x80000000u
+#define SDHC_FEVT_CINT_SHIFT 31
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK 0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT 0
+#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT 2
+#define SDHC_ADMAES_ADMADCE_MASK 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT 3
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT 2
+#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT 0
+#define SDHC_VENDOR_EXBLKNU_MASK 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT 1
+#define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT 16
+#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
+#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT 4
+#define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
+#define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT 6
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK 0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT 0
+#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK 0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT 8
+#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SDHC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML SDHC_WML_REG(SDHC)
+#define SDHC_FEVT SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
+ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
+ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC1_REG(base) ((base)->SCGC1)
+#define SIM_SCGC2_REG(base) ((base)->SCGC2)
+#define SIM_SCGC3_REG(base) ((base)->SCGC3)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDH_REG(base) ((base)->UIDH)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK 0x300u
+#define SIM_SOPT2_FBSL_SHIFT 8
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_RMIISRC_MASK 0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT 19
+#define SIM_SOPT2_TIMESRC_MASK 0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT 20
+#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT 28
+#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT 2
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT 12
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
+#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK 0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT 28
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK 0x40u
+#define SIM_SCGC1_I2C2_SHIFT 6
+#define SIM_SCGC1_UART4_MASK 0x400u
+#define SIM_SCGC1_UART4_SHIFT 10
+#define SIM_SCGC1_UART5_MASK 0x800u
+#define SIM_SCGC1_UART5_SHIFT 11
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK 0x1u
+#define SIM_SCGC2_ENET_SHIFT 0
+#define SIM_SCGC2_DAC0_MASK 0x1000u
+#define SIM_SCGC2_DAC0_SHIFT 12
+#define SIM_SCGC2_DAC1_MASK 0x2000u
+#define SIM_SCGC2_DAC1_SHIFT 13
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK 0x1u
+#define SIM_SCGC3_RNGA_SHIFT 0
+#define SIM_SCGC3_SPI2_MASK 0x1000u
+#define SIM_SCGC3_SPI2_SHIFT 12
+#define SIM_SCGC3_SDHC_MASK 0x20000u
+#define SIM_SCGC3_SDHC_SHIFT 17
+#define SIM_SCGC3_FTM2_MASK 0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT 24
+#define SIM_SCGC3_FTM3_MASK 0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT 25
+#define SIM_SCGC3_ADC1_MASK 0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT 27
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_UART3_MASK 0x2000u
+#define SIM_SCGC4_UART3_SHIFT 13
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT 4
+#define SIM_SCGC6_RNGA_MASK 0x200u
+#define SIM_SCGC6_RNGA_SHIFT 9
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_FTM2_MASK 0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK 0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT 0
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+#define SIM_SCGC7_MPU_MASK 0x4u
+#define SIM_SCGC7_MPU_SHIFT 2
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC1 SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2 SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3 SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDH SIM_UIDH_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base) ((base)->MCR)
+#define SPI_TCR_REG(base) ((base)->TCR)
+#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base) ((base)->SR)
+#define SPI_RSER_REG(base) ((base)->RSER)
+#define SPI_PUSHR_REG(base) ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base) ((base)->POPR)
+#define SPI_TXFR0_REG(base) ((base)->TXFR0)
+#define SPI_TXFR1_REG(base) ((base)->TXFR1)
+#define SPI_TXFR2_REG(base) ((base)->TXFR2)
+#define SPI_TXFR3_REG(base) ((base)->TXFR3)
+#define SPI_RXFR0_REG(base) ((base)->RXFR0)
+#define SPI_RXFR1_REG(base) ((base)->RXFR1)
+#define SPI_RXFR2_REG(base) ((base)->RXFR2)
+#define SPI_RXFR3_REG(base) ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2 ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR SPI_MCR_REG(SPI0)
+#define SPI0_TCR SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR SPI_SR_REG(SPI0)
+#define SPI0_RSER SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR SPI_MCR_REG(SPI1)
+#define SPI1_TCR SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR SPI_SR_REG(SPI1)
+#define SPI1_RSER SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR SPI_MCR_REG(SPI2)
+#define SPI2_TCR SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR SPI_SR_REG(SPI2)
+#define SPI2_RSER SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_ED_REG(base) ((base)->ED)
+#define UART_MODEM_REG(base) ((base)->MODEM)
+#define UART_IR_REG(base) ((base)->IR)
+#define UART_PFIFO_REG(base) ((base)->PFIFO)
+#define UART_CFIFO_REG(base) ((base)->CFIFO)
+#define UART_SFIFO_REG(base) ((base)->SFIFO)
+#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816T0_REG(base) ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base) ((base)->WP7816T1)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK 0x8u
+#define UART_C5_LBKDDMAS_SHIFT 3
+#define UART_C5_ILDMAS_MASK 0x10u
+#define UART_C5_ILDMAS_SHIFT 4
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TCDMAS_MASK 0x40u
+#define UART_C5_TCDMAS_SHIFT 6
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXOFE_MASK 0x4u
+#define UART_CFIFO_RXOFE_SHIFT 2
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXOF_MASK 0x4u
+#define UART_SFIFO_RXOF_SHIFT 2
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK 0xFFu
+#define UART_WP7816T0_WI_SHIFT 0
+#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK 0xFu
+#define UART_WP7816T1_BWI_SHIFT 0
+#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK 0xF0u
+#define UART_WP7816T1_CWI_SHIFT 4
+#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3 ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4 ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5 ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH UART_BDH_REG(UART0)
+#define UART0_BDL UART_BDL_REG(UART0)
+#define UART0_C1 UART_C1_REG(UART0)
+#define UART0_C2 UART_C2_REG(UART0)
+#define UART0_S1 UART_S1_REG(UART0)
+#define UART0_S2 UART_S2_REG(UART0)
+#define UART0_C3 UART_C3_REG(UART0)
+#define UART0_D UART_D_REG(UART0)
+#define UART0_MA1 UART_MA1_REG(UART0)
+#define UART0_MA2 UART_MA2_REG(UART0)
+#define UART0_C4 UART_C4_REG(UART0)
+#define UART0_C5 UART_C5_REG(UART0)
+#define UART0_ED UART_ED_REG(UART0)
+#define UART0_MODEM UART_MODEM_REG(UART0)
+#define UART0_IR UART_IR_REG(UART0)
+#define UART0_PFIFO UART_PFIFO_REG(UART0)
+#define UART0_CFIFO UART_CFIFO_REG(UART0)
+#define UART0_SFIFO UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
+#define UART0_C7816 UART_C7816_REG(UART0)
+#define UART0_IE7816 UART_IE7816_REG(UART0)
+#define UART0_IS7816 UART_IS7816_REG(UART0)
+#define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
+#define UART0_WN7816 UART_WN7816_REG(UART0)
+#define UART0_WF7816 UART_WF7816_REG(UART0)
+#define UART0_ET7816 UART_ET7816_REG(UART0)
+#define UART0_TL7816 UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH UART_BDH_REG(UART1)
+#define UART1_BDL UART_BDL_REG(UART1)
+#define UART1_C1 UART_C1_REG(UART1)
+#define UART1_C2 UART_C2_REG(UART1)
+#define UART1_S1 UART_S1_REG(UART1)
+#define UART1_S2 UART_S2_REG(UART1)
+#define UART1_C3 UART_C3_REG(UART1)
+#define UART1_D UART_D_REG(UART1)
+#define UART1_MA1 UART_MA1_REG(UART1)
+#define UART1_MA2 UART_MA2_REG(UART1)
+#define UART1_C4 UART_C4_REG(UART1)
+#define UART1_C5 UART_C5_REG(UART1)
+#define UART1_ED UART_ED_REG(UART1)
+#define UART1_MODEM UART_MODEM_REG(UART1)
+#define UART1_IR UART_IR_REG(UART1)
+#define UART1_PFIFO UART_PFIFO_REG(UART1)
+#define UART1_CFIFO UART_CFIFO_REG(UART1)
+#define UART1_SFIFO UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_ED UART_ED_REG(UART2)
+#define UART2_MODEM UART_MODEM_REG(UART2)
+#define UART2_IR UART_IR_REG(UART2)
+#define UART2_PFIFO UART_PFIFO_REG(UART2)
+#define UART2_CFIFO UART_CFIFO_REG(UART2)
+#define UART2_SFIFO UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH UART_BDH_REG(UART3)
+#define UART3_BDL UART_BDL_REG(UART3)
+#define UART3_C1 UART_C1_REG(UART3)
+#define UART3_C2 UART_C2_REG(UART3)
+#define UART3_S1 UART_S1_REG(UART3)
+#define UART3_S2 UART_S2_REG(UART3)
+#define UART3_C3 UART_C3_REG(UART3)
+#define UART3_D UART_D_REG(UART3)
+#define UART3_MA1 UART_MA1_REG(UART3)
+#define UART3_MA2 UART_MA2_REG(UART3)
+#define UART3_C4 UART_C4_REG(UART3)
+#define UART3_C5 UART_C5_REG(UART3)
+#define UART3_ED UART_ED_REG(UART3)
+#define UART3_MODEM UART_MODEM_REG(UART3)
+#define UART3_IR UART_IR_REG(UART3)
+#define UART3_PFIFO UART_PFIFO_REG(UART3)
+#define UART3_CFIFO UART_CFIFO_REG(UART3)
+#define UART3_SFIFO UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH UART_BDH_REG(UART4)
+#define UART4_BDL UART_BDL_REG(UART4)
+#define UART4_C1 UART_C1_REG(UART4)
+#define UART4_C2 UART_C2_REG(UART4)
+#define UART4_S1 UART_S1_REG(UART4)
+#define UART4_S2 UART_S2_REG(UART4)
+#define UART4_C3 UART_C3_REG(UART4)
+#define UART4_D UART_D_REG(UART4)
+#define UART4_MA1 UART_MA1_REG(UART4)
+#define UART4_MA2 UART_MA2_REG(UART4)
+#define UART4_C4 UART_C4_REG(UART4)
+#define UART4_C5 UART_C5_REG(UART4)
+#define UART4_ED UART_ED_REG(UART4)
+#define UART4_MODEM UART_MODEM_REG(UART4)
+#define UART4_IR UART_IR_REG(UART4)
+#define UART4_PFIFO UART_PFIFO_REG(UART4)
+#define UART4_CFIFO UART_CFIFO_REG(UART4)
+#define UART4_SFIFO UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH UART_BDH_REG(UART5)
+#define UART5_BDL UART_BDL_REG(UART5)
+#define UART5_C1 UART_C1_REG(UART5)
+#define UART5_C2 UART_C2_REG(UART5)
+#define UART5_S1 UART_S1_REG(UART5)
+#define UART5_S2 UART_S2_REG(UART5)
+#define UART5_C3 UART_C3_REG(UART5)
+#define UART5_D UART_D_REG(UART5)
+#define UART5_MA1 UART_MA1_REG(UART5)
+#define UART5_MA2 UART_MA2_REG(UART5)
+#define UART5_C4 UART_C4_REG(UART5)
+#define UART5_C5 UART_C5_REG(UART5)
+#define UART5_ED UART_ED_REG(UART5)
+#define UART5_MODEM UART_MODEM_REG(UART5)
+#define UART5_IR UART_IR_REG(UART5)
+#define UART5_PFIFO UART_PFIFO_REG(UART5)
+#define UART5_CFIFO UART_CFIFO_REG(UART5)
+#define UART5_SFIFO UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_26[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_27[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_28[23];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base) ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base) ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
+ union { /* offset: 0x18 */
+ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
+ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
+ };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base) ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_BC12_MASK 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT 17
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
+#define WDOG_WINH_REG(base) ((base)->WINH)
+#define WDOG_WINL_REG(base) ((base)->WINL)
+#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base) ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH WDOG_WINH_REG(WDOG)
+#define WDOG_WINL WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base) This_symbol_has_been_deprecated
+#define DMA_EARS This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
+#define MCG_C9_REG(base) This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define MCG_C9 This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
+#define MCM_PLACR This_symbol_has_been_deprecated
+#define ADC_BASES ADC_BASE_PTRS
+#define AIPS_BASES AIPS_BASE_PTRS
+#define AXBS_BASES AXBS_BASE_PTRS
+#define CAN_BASES CAN_BASE_PTRS
+#define CAU_BASES CAU_BASE_PTRS
+#define CMP_BASES CMP_BASE_PTRS
+#define CMT_BASES CMT_BASE_PTRS
+#define CRC_BASES CRC_BASE_PTRS
+#define DAC_BASES DAC_BASE_PTRS
+#define DMA_BASES DMA_BASE_PTRS
+#define DMAMUX_BASES DMAMUX_BASE_PTRS
+#define ENET_BASES ENET_BASE_PTRS
+#define EWM_BASES EWM_BASE_PTRS
+#define FB_BASES FB_BASE_PTRS
+#define FMC_BASES FMC_BASE_PTRS
+#define FTFE_BASES FTFE_BASE_PTRS
+#define FTM_BASES FTM_BASE_PTRS
+#define GPIO_BASES GPIO_BASE_PTRS
+#define I2C_BASES I2C_BASE_PTRS
+#define I2S_BASES I2S_BASE_PTRS
+#define LLWU_BASES LLWU_BASE_PTRS
+#define LPTMR_BASES LPTMR_BASE_PTRS
+#define MCG_BASES MCG_BASE_PTRS
+#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES MCM_BASE_PTRS
+#define MPU_BASES MPU_BASE_PTRS
+#define NV_BASES NV_BASE_PTRS
+#define OSC_BASES OSC_BASE_PTRS
+#define PDB_BASES PDB_BASE_PTRS
+#define PIT_BASES PIT_BASE_PTRS
+#define PMC_BASES PMC_BASE_PTRS
+#define PORT_BASES PORT_BASE_PTRS
+#define RCM_BASES RCM_BASE_PTRS
+#define RFSYS_BASES RFSYS_BASE_PTRS
+#define RFVBAT_BASES RFVBAT_BASE_PTRS
+#define RNG_BASES RNG_BASE_PTRS
+#define RTC_BASES RTC_BASE_PTRS
+#define SDHC_BASES SDHC_BASE_PTRS
+#define SIM_BASES SIM_BASE_PTRS
+#define SMC_BASES SMC_BASE_PTRS
+#define SPI_BASES SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
+#define UART_BASES UART_BASE_PTRS
+#define USB_BASES USB_BASE_PTRS
+#define USBDCD_BASES USBDCD_BASE_PTRS
+#define VREF_BASES VREF_BASE_PTRS
+#define WDOG_BASES WDOG_BASE_PTRS
+#define DMA_EARS_REG(base) This_symbol_has_been_deprecated
+#define DMA_EARS This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
+#define MCG_C9_REG(base) This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define MCG_C9 This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
+#define MCM_PLACR This_symbol_has_been_deprecated
+#define ADC_BASES ADC_BASE_PTRS
+#define AIPS_BASES AIPS_BASE_PTRS
+#define AXBS_BASES AXBS_BASE_PTRS
+#define CAN_BASES CAN_BASE_PTRS
+#define CAU_BASES CAU_BASE_PTRS
+#define CMP_BASES CMP_BASE_PTRS
+#define CMT_BASES CMT_BASE_PTRS
+#define CRC_BASES CRC_BASE_PTRS
+#define DAC_BASES DAC_BASE_PTRS
+#define DMA_BASES DMA_BASE_PTRS
+#define DMAMUX_BASES DMAMUX_BASE_PTRS
+#define ENET_BASES ENET_BASE_PTRS
+#define EWM_BASES EWM_BASE_PTRS
+#define FB_BASES FB_BASE_PTRS
+#define FMC_BASES FMC_BASE_PTRS
+#define FTFE_BASES FTFE_BASE_PTRS
+#define FTM_BASES FTM_BASE_PTRS
+#define GPIO_BASES GPIO_BASE_PTRS
+#define I2C_BASES I2C_BASE_PTRS
+#define I2S_BASES I2S_BASE_PTRS
+#define LLWU_BASES LLWU_BASE_PTRS
+#define LPTMR_BASES LPTMR_BASE_PTRS
+#define MCG_BASES MCG_BASE_PTRS
+#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES MCM_BASE_PTRS
+#define MPU_BASES MPU_BASE_PTRS
+#define NV_BASES NV_BASE_PTRS
+#define OSC_BASES OSC_BASE_PTRS
+#define PDB_BASES PDB_BASE_PTRS
+#define PIT_BASES PIT_BASE_PTRS
+#define PMC_BASES PMC_BASE_PTRS
+#define PORT_BASES PORT_BASE_PTRS
+#define RCM_BASES RCM_BASE_PTRS
+#define RFSYS_BASES RFSYS_BASE_PTRS
+#define RFVBAT_BASES RFVBAT_BASE_PTRS
+#define RNG_BASES RNG_BASE_PTRS
+#define RTC_BASES RTC_BASE_PTRS
+#define SDHC_BASES SDHC_BASE_PTRS
+#define SIM_BASES SIM_BASE_PTRS
+#define SMC_BASES SMC_BASE_PTRS
+#define SPI_BASES SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
+#define UART_BASES UART_BASE_PTRS
+#define USB_BASES USB_BASE_PTRS
+#define USBDCD_BASES USBDCD_BASE_PTRS
+#define VREF_BASES VREF_BASE_PTRS
+#define WDOG_BASES WDOG_BASE_PTRS
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0200u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/MK64F.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/MK64F.sct
new file mode 100644
index 000000000..1aafaed20
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/MK64F.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
+ ER_IROM1 0x00000000 0x100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
+ ; 0x40000 - 0x198 = 0x3FE68
+ RW_IRAM1 0x1FFF0198 0x3FE68 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.s
new file mode 100644
index 000000000..412795606
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.s
@@ -0,0 +1,685 @@
+;/*****************************************************************************
+; * @file: startup_MK70F12.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK70F12
+; * @version: 1.5
+; * @date: 2012-10-19
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20030000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD RNG_IRQHandler ; RNG Interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
+ DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
+ DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
+ DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
+ DCD DefaultISR ; 102
+ DCD DefaultISR ; 103
+ DCD DefaultISR ; 104
+ DCD DefaultISR ; 105
+ DCD DefaultISR ; 106
+ DCD DefaultISR ; 107
+ DCD DefaultISR ; 108
+ DCD DefaultISR ; 109
+ DCD DefaultISR ; 110
+ DCD DefaultISR ; 111
+ DCD DefaultISR ; 112
+ DCD DefaultISR ; 113
+ DCD DefaultISR ; 114
+ DCD DefaultISR ; 115
+ DCD DefaultISR ; 116
+ DCD DefaultISR ; 117
+ DCD DefaultISR ; 118
+ DCD DefaultISR ; 119
+ DCD DefaultISR ; 120
+ DCD DefaultISR ; 121
+ DCD DefaultISR ; 122
+ DCD DefaultISR ; 123
+ DCD DefaultISR ; 124
+ DCD DefaultISR ; 125
+ DCD DefaultISR ; 126
+ DCD DefaultISR ; 127
+ DCD DefaultISR ; 128
+ DCD DefaultISR ; 129
+ DCD DefaultISR ; 130
+ DCD DefaultISR ; 131
+ DCD DefaultISR ; 132
+ DCD DefaultISR ; 133
+ DCD DefaultISR ; 134
+ DCD DefaultISR ; 135
+ DCD DefaultISR ; 136
+ DCD DefaultISR ; 137
+ DCD DefaultISR ; 138
+ DCD DefaultISR ; 139
+ DCD DefaultISR ; 140
+ DCD DefaultISR ; 141
+ DCD DefaultISR ; 142
+ DCD DefaultISR ; 143
+ DCD DefaultISR ; 144
+ DCD DefaultISR ; 145
+ DCD DefaultISR ; 146
+ DCD DefaultISR ; 147
+ DCD DefaultISR ; 148
+ DCD DefaultISR ; 149
+ DCD DefaultISR ; 150
+ DCD DefaultISR ; 151
+ DCD DefaultISR ; 152
+ DCD DefaultISR ; 153
+ DCD DefaultISR ; 154
+ DCD DefaultISR ; 155
+ DCD DefaultISR ; 156
+ DCD DefaultISR ; 157
+ DCD DefaultISR ; 158
+ DCD DefaultISR ; 159
+ DCD DefaultISR ; 160
+ DCD DefaultISR ; 161
+ DCD DefaultISR ; 162
+ DCD DefaultISR ; 163
+ DCD DefaultISR ; 164
+ DCD DefaultISR ; 165
+ DCD DefaultISR ; 166
+ DCD DefaultISR ; 167
+ DCD DefaultISR ; 168
+ DCD DefaultISR ; 169
+ DCD DefaultISR ; 170
+ DCD DefaultISR ; 171
+ DCD DefaultISR ; 172
+ DCD DefaultISR ; 173
+ DCD DefaultISR ; 174
+ DCD DefaultISR ; 175
+ DCD DefaultISR ; 176
+ DCD DefaultISR ; 177
+ DCD DefaultISR ; 178
+ DCD DefaultISR ; 179
+ DCD DefaultISR ; 180
+ DCD DefaultISR ; 181
+ DCD DefaultISR ; 182
+ DCD DefaultISR ; 183
+ DCD DefaultISR ; 184
+ DCD DefaultISR ; 185
+ DCD DefaultISR ; 186
+ DCD DefaultISR ; 187
+ DCD DefaultISR ; 188
+ DCD DefaultISR ; 189
+ DCD DefaultISR ; 190
+ DCD DefaultISR ; 191
+ DCD DefaultISR ; 192
+ DCD DefaultISR ; 193
+ DCD DefaultISR ; 194
+ DCD DefaultISR ; 195
+ DCD DefaultISR ; 196
+ DCD DefaultISR ; 197
+ DCD DefaultISR ; 198
+ DCD DefaultISR ; 199
+ DCD DefaultISR ; 200
+ DCD DefaultISR ; 201
+ DCD DefaultISR ; 202
+ DCD DefaultISR ; 203
+ DCD DefaultISR ; 204
+ DCD DefaultISR ; 205
+ DCD DefaultISR ; 206
+ DCD DefaultISR ; 207
+ DCD DefaultISR ; 208
+ DCD DefaultISR ; 209
+ DCD DefaultISR ; 210
+ DCD DefaultISR ; 211
+ DCD DefaultISR ; 212
+ DCD DefaultISR ; 213
+ DCD DefaultISR ; 214
+ DCD DefaultISR ; 215
+ DCD DefaultISR ; 216
+ DCD DefaultISR ; 217
+ DCD DefaultISR ; 218
+ DCD DefaultISR ; 219
+ DCD DefaultISR ; 220
+ DCD DefaultISR ; 221
+ DCD DefaultISR ; 222
+ DCD DefaultISR ; 223
+ DCD DefaultISR ; 224
+ DCD DefaultISR ; 225
+ DCD DefaultISR ; 226
+ DCD DefaultISR ; 227
+ DCD DefaultISR ; 228
+ DCD DefaultISR ; 229
+ DCD DefaultISR ; 230
+ DCD DefaultISR ; 231
+ DCD DefaultISR ; 232
+ DCD DefaultISR ; 233
+ DCD DefaultISR ; 234
+ DCD DefaultISR ; 235
+ DCD DefaultISR ; 236
+ DCD DefaultISR ; 237
+ DCD DefaultISR ; 238
+ DCD DefaultISR ; 239
+ DCD DefaultISR ; 240
+ DCD DefaultISR ; 241
+ DCD DefaultISR ; 242
+ DCD DefaultISR ; 243
+ DCD DefaultISR ; 244
+ DCD DefaultISR ; 245
+ DCD DefaultISR ; 246
+ DCD DefaultISR ; 247
+ DCD DefaultISR ; 248
+ DCD DefaultISR ; 249
+ DCD DefaultISR ; 250
+ DCD DefaultISR ; 251
+ DCD DefaultISR ; 252
+ DCD DefaultISR ; 253
+ DCD DefaultISR ; 254
+ DCD DefaultISR ; 255
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is disabled
+; <1=> EzPort operation is enabled
+FOPT EQU 0xFD
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA4_IRQHandler [WEAK]
+ EXPORT DMA5_IRQHandler [WEAK]
+ EXPORT DMA6_IRQHandler [WEAK]
+ EXPORT DMA7_IRQHandler [WEAK]
+ EXPORT DMA8_IRQHandler [WEAK]
+ EXPORT DMA9_IRQHandler [WEAK]
+ EXPORT DMA10_IRQHandler [WEAK]
+ EXPORT DMA11_IRQHandler [WEAK]
+ EXPORT DMA12_IRQHandler [WEAK]
+ EXPORT DMA13_IRQHandler [WEAK]
+ EXPORT DMA14_IRQHandler [WEAK]
+ EXPORT DMA15_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT MCM_IRQHandler [WEAK]
+ EXPORT FTFE_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT UART3_RX_TX_IRQHandler [WEAK]
+ EXPORT UART3_ERR_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT FTM2_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT Reserved71_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART4_RX_TX_IRQHandler [WEAK]
+ EXPORT UART4_ERR_IRQHandler [WEAK]
+ EXPORT UART5_RX_TX_IRQHandler [WEAK]
+ EXPORT UART5_ERR_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT FTM3_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
+ EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
+ EXPORT CAN0_Error_IRQHandler [WEAK]
+ EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
+ EXPORT SDHC_IRQHandler [WEAK]
+ EXPORT ENET_1588_Timer_IRQHandler [WEAK]
+ EXPORT ENET_Transmit_IRQHandler [WEAK]
+ EXPORT ENET_Receive_IRQHandler [WEAK]
+ EXPORT ENET_Error_IRQHandler [WEAK]
+
+DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+DMA_Error_IRQHandler ; DMA Error Interrupt
+MCM_IRQHandler ; Normal Interrupt
+FTFE_IRQHandler ; FTFE Command complete interrupt
+Read_Collision_IRQHandler ; Read Collision Interrupt
+LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+LLW_IRQHandler ; Low Leakage Wakeup
+Watchdog_IRQHandler ; WDOG Interrupt
+RNG_IRQHandler ; RNG Interrupt
+I2C0_IRQHandler ; I2C0 interrupt
+I2C1_IRQHandler ; I2C1 interrupt
+SPI0_IRQHandler ; SPI0 Interrupt
+SPI1_IRQHandler ; SPI1 Interrupt
+I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+UART0_LON_IRQHandler ; UART0 LON interrupt
+UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+UART0_ERR_IRQHandler ; UART0 Error interrupt
+UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+UART1_ERR_IRQHandler ; UART1 Error interrupt
+UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+UART2_ERR_IRQHandler ; UART2 Error interrupt
+UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+UART3_ERR_IRQHandler ; UART3 Error interrupt
+ADC0_IRQHandler ; ADC0 interrupt
+CMP0_IRQHandler ; CMP0 interrupt
+CMP1_IRQHandler ; CMP1 interrupt
+FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+CMT_IRQHandler ; CMT interrupt
+RTC_IRQHandler ; RTC interrupt
+RTC_Seconds_IRQHandler ; RTC seconds interrupt
+PIT0_IRQHandler ; PIT timer channel 0 interrupt
+PIT1_IRQHandler ; PIT timer channel 1 interrupt
+PIT2_IRQHandler ; PIT timer channel 2 interrupt
+PIT3_IRQHandler ; PIT timer channel 3 interrupt
+PDB0_IRQHandler ; PDB0 Interrupt
+USB0_IRQHandler ; USB0 interrupt
+USBDCD_IRQHandler ; USBDCD Interrupt
+Reserved71_IRQHandler ; Reserved interrupt 71
+DAC0_IRQHandler ; DAC0 interrupt
+MCG_IRQHandler ; MCG Interrupt
+LPTimer_IRQHandler ; LPTimer interrupt
+PORTA_IRQHandler ; Port A interrupt
+PORTB_IRQHandler ; Port B interrupt
+PORTC_IRQHandler ; Port C interrupt
+PORTD_IRQHandler ; Port D interrupt
+PORTE_IRQHandler ; Port E interrupt
+SWI_IRQHandler ; Software interrupt
+SPI2_IRQHandler ; SPI2 Interrupt
+UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+UART4_ERR_IRQHandler ; UART4 Error interrupt
+UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+UART5_ERR_IRQHandler ; UART5 Error interrupt
+CMP2_IRQHandler ; CMP2 interrupt
+FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+DAC1_IRQHandler ; DAC1 interrupt
+ADC1_IRQHandler ; ADC1 interrupt
+I2C2_IRQHandler ; I2C2 interrupt
+CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+CAN0_Error_IRQHandler ; CAN0 error interrupt
+CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+SDHC_IRQHandler ; SDHC interrupt
+ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
+ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
+ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
+ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..b129b2c2a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld
new file mode 100644
index 000000000..5bf14b145
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld
@@ -0,0 +1,164 @@
+/*
+ * K64F ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
new file mode 100644
index 000000000..632979af3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S
@@ -0,0 +1,369 @@
+/* K64F startup ARM GCC
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xC00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete */
+ .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete */
+ .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete */
+ .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete */
+ .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete */
+ .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete */
+ .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete */
+ .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete */
+ .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete */
+ .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete */
+ .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete */
+ .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete */
+ .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete */
+ .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete */
+ .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete */
+ .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete */
+ .long DMA_Error_IRQHandler /* DMA Error Interrupt */
+ .long MCM_IRQHandler /* Normal Interrupt */
+ .long FTFE_IRQHandler /* FTFE Command complete interrupt */
+ .long Read_Collision_IRQHandler /* Read Collision Interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long Watchdog_IRQHandler /* WDOG Interrupt */
+ .long RNG_IRQHandler /* RNG Interrupt */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C1 interrupt */
+ .long SPI0_IRQHandler /* SPI0 Interrupt */
+ .long SPI1_IRQHandler /* SPI1 Interrupt */
+ .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */
+ .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */
+ .long UART0_LON_IRQHandler /* UART0 LON interrupt */
+ .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt */
+ .long UART0_ERR_IRQHandler /* UART0 Error interrupt */
+ .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt */
+ .long UART1_ERR_IRQHandler /* UART1 Error interrupt */
+ .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt */
+ .long UART2_ERR_IRQHandler /* UART2 Error interrupt */
+ .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt */
+ .long UART3_ERR_IRQHandler /* UART3 Error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long CMP1_IRQHandler /* CMP1 interrupt */
+ .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */
+ .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */
+ .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt */
+ .long CMT_IRQHandler /* CMT interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT0_IRQHandler /* PIT timer channel 0 interrupt */
+ .long PIT1_IRQHandler /* PIT timer channel 1 interrupt */
+ .long PIT2_IRQHandler /* PIT timer channel 2 interrupt */
+ .long PIT3_IRQHandler /* PIT timer channel 3 interrupt */
+ .long PDB0_IRQHandler /* PDB0 Interrupt */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long USBDCD_IRQHandler /* USBDCD Interrupt */
+ .long Reserved71_IRQHandler /* Reserved interrupt 71 */
+ .long DAC0_IRQHandler /* DAC0 interrupt */
+ .long MCG_IRQHandler /* MCG Interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTB_IRQHandler /* Port B interrupt */
+ .long PORTC_IRQHandler /* Port C interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+ .long PORTE_IRQHandler /* Port E interrupt */
+ .long SWI_IRQHandler /* Software interrupt */
+ .long SPI2_IRQHandler /* SPI2 Interrupt */
+ .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt */
+ .long UART4_ERR_IRQHandler /* UART4 Error interrupt */
+ .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt */
+ .long UART5_ERR_IRQHandler /* UART5 Error interrupt */
+ .long CMP2_IRQHandler /* CMP2 interrupt */
+ .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt */
+ .long DAC1_IRQHandler /* DAC1 interrupt */
+ .long ADC1_IRQHandler /* ADC1 interrupt */
+ .long I2C2_IRQHandler /* I2C2 interrupt */
+ .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt */
+ .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt */
+ .long CAN0_Error_IRQHandler /* CAN0 error interrupt */
+ .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt */
+ .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt */
+ .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt */
+ .long SDHC_IRQHandler /* SDHC interrupt */
+ .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt */
+ .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt */
+ .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt */
+ .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+disable_watchdog:
+ /* unlock */
+ ldr r1, =0x4005200e
+ ldr r0, =0xc520
+ strh r0, [r1]
+ ldr r0, =0xd928
+ strh r0, [r1]
+ /* disable */
+ ldr r1, =0x40052000
+ ldr r0, =0x01d2
+ strh r0, [r1]
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+/* Exception Handlers */
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+/* IRQ Handlers */
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA4_IRQHandler
+ def_irq_default_handler DMA5_IRQHandler
+ def_irq_default_handler DMA6_IRQHandler
+ def_irq_default_handler DMA7_IRQHandler
+ def_irq_default_handler DMA8_IRQHandler
+ def_irq_default_handler DMA9_IRQHandler
+ def_irq_default_handler DMA10_IRQHandler
+ def_irq_default_handler DMA11_IRQHandler
+ def_irq_default_handler DMA12_IRQHandler
+ def_irq_default_handler DMA13_IRQHandler
+ def_irq_default_handler DMA14_IRQHandler
+ def_irq_default_handler DMA15_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler MCM_IRQHandler
+ def_irq_default_handler FTFE_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler RNG_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler UART0_LON_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler UART3_RX_TX_IRQHandler
+ def_irq_default_handler UART3_ERR_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler FTM2_IRQHandler
+ def_irq_default_handler CMT_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USBDCD_IRQHandler
+ def_irq_default_handler Reserved71_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler UART4_RX_TX_IRQHandler
+ def_irq_default_handler UART4_ERR_IRQHandler
+ def_irq_default_handler UART5_RX_TX_IRQHandler
+ def_irq_default_handler UART5_ERR_IRQHandler
+ def_irq_default_handler CMP2_IRQHandler
+ def_irq_default_handler FTM3_IRQHandler
+ def_irq_default_handler DAC1_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
+ def_irq_default_handler CAN0_Bus_Off_IRQHandler
+ def_irq_default_handler CAN0_Error_IRQHandler
+ def_irq_default_handler CAN0_Tx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Rx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Wake_Up_IRQHandler
+ def_irq_default_handler SDHC_IRQHandler
+ def_irq_default_handler ENET_1588_Timer_IRQHandler
+ def_irq_default_handler ENET_Transmit_IRQHandler
+ def_irq_default_handler ENET_Receive_IRQHandler
+ def_irq_default_handler ENET_Error_IRQHandler
+ def_irq_default_handler DefaultISR
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffdfe
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf
new file mode 100644
index 000000000..6300e56e2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x000fffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff0197;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0198;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x8000;
+define symbol __ICFEDIT_size_heap__ = 0x10000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x2002ffff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define symbol __region_FlexRAM_start__ = 0x14000000;
+define symbol __region_FlexRAM_end__ = 0x14000fff;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
+
+place in FlexRAM_region { section .flex_ram };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.s
new file mode 100644
index 000000000..bd1368211
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.s
@@ -0,0 +1,394 @@
+/**************************************************
+ *
+ * Copyright 2010 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD RNG_IRQHandler ; RNG Interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
+ DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
+ DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
+ DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT^0xFF
+
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT^0xFF
+
+FOPT EQU 0xFD
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK DMA4_IRQHandler
+ PUBWEAK DMA5_IRQHandler
+ PUBWEAK DMA6_IRQHandler
+ PUBWEAK DMA7_IRQHandler
+ PUBWEAK DMA8_IRQHandler
+ PUBWEAK DMA9_IRQHandler
+ PUBWEAK DMA10_IRQHandler
+ PUBWEAK DMA11_IRQHandler
+ PUBWEAK DMA12_IRQHandler
+ PUBWEAK DMA13_IRQHandler
+ PUBWEAK DMA14_IRQHandler
+ PUBWEAK DMA15_IRQHandler
+ PUBWEAK DMA_Error_IRQHandler
+ PUBWEAK MCM_IRQHandler
+ PUBWEAK FTFE_IRQHandler
+ PUBWEAK Read_Collision_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK Watchdog_IRQHandler
+ PUBWEAK RNG_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK I2S0_Tx_IRQHandler
+ PUBWEAK I2S0_Rx_IRQHandler
+ PUBWEAK UART0_LON_IRQHandler
+ PUBWEAK UART0_RX_TX_IRQHandler
+ PUBWEAK UART0_ERR_IRQHandler
+ PUBWEAK UART1_RX_TX_IRQHandler
+ PUBWEAK UART1_ERR_IRQHandler
+ PUBWEAK UART2_RX_TX_IRQHandler
+ PUBWEAK UART2_ERR_IRQHandler
+ PUBWEAK UART3_RX_TX_IRQHandler
+ PUBWEAK UART3_ERR_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK FTM0_IRQHandler
+ PUBWEAK FTM1_IRQHandler
+ PUBWEAK FTM2_IRQHandler
+ PUBWEAK CMT_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT0_IRQHandler
+ PUBWEAK PIT1_IRQHandler
+ PUBWEAK PIT2_IRQHandler
+ PUBWEAK PIT3_IRQHandler
+ PUBWEAK PDB0_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USBDCD_IRQHandler
+ PUBWEAK Reserved71_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+ PUBWEAK PORTC_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+ PUBWEAK PORTE_IRQHandler
+ PUBWEAK SWI_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ PUBWEAK UART4_RX_TX_IRQHandler
+ PUBWEAK UART4_ERR_IRQHandler
+ PUBWEAK UART5_RX_TX_IRQHandler
+ PUBWEAK UART5_ERR_IRQHandler
+ PUBWEAK CMP2_IRQHandler
+ PUBWEAK FTM3_IRQHandler
+ PUBWEAK DAC1_IRQHandler
+ PUBWEAK ADC1_IRQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
+ PUBWEAK CAN0_Bus_Off_IRQHandler
+ PUBWEAK CAN0_Error_IRQHandler
+ PUBWEAK CAN0_Tx_Warning_IRQHandler
+ PUBWEAK CAN0_Rx_Warning_IRQHandler
+ PUBWEAK CAN0_Wake_Up_IRQHandler
+ PUBWEAK SDHC_IRQHandler
+ PUBWEAK ENET_1588_Timer_IRQHandler
+ PUBWEAK ENET_Transmit_IRQHandler
+ PUBWEAK ENET_Receive_IRQHandler
+ PUBWEAK ENET_Error_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+RNG_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved71_IRQHandler
+DAC0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+SPI2_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+CMP2_IRQHandler
+FTM3_IRQHandler
+DAC1_IRQHandler
+ADC1_IRQHandler
+I2C2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+SDHC_IRQHandler
+ENET_1588_Timer_IRQHandler
+ENET_Transmit_IRQHandler
+ENET_Receive_IRQHandler
+ENET_Error_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h
new file mode 100644
index 000000000..8c87549bd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK64F12.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c
new file mode 100644
index 000000000..fc13c884f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h
new file mode 100644
index 000000000..206b64543
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c
new file mode 100644
index 000000000..849c58c74
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c
@@ -0,0 +1,391 @@
+/*
+** ###################################################################
+** Processor: MK64FN1M0VMD12
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.5, 2014-02-10
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** - rev. 2.5 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.5
+ * @date 2014-02-10
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "cmsis.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+ /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+ WDOG_STCTRLH_WAITEN_MASK |
+ WDOG_STCTRLH_STOPEN_MASK |
+ WDOG_STCTRLH_ALLOWUPDATE_MASK |
+ WDOG_STCTRLH_CLKSRC_MASK |
+ 0x0100U;
+#endif /* (DISABLE_WDOG) */
+ if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+ {
+ if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+ {
+ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
+ }
+ } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+ if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+ RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+ RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+ RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+ }
+#endif
+ }
+
+ /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+ SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+ /* System clock initialization */
+ /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+ if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
+ MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+ #if defined(SLOW_FINE_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+ #endif
+ #if defined(FAST_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+ #endif
+ #if defined(FAST_FINE_TRIM_ADDRESS)
+ MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+ #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+ }
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+ /* Set system prescalers and clock sources */
+ SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+ SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+ SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ /* Set MCG and OSC */
+#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_BLPI)
+ /* BLPI specific */
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+ #endif
+
+#else /* MCG_MODE */
+ /* Set MCG and OSC */
+#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+ #else
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ #endif
+ if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+ }
+ }
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+ /* Common for all MCG modes */
+
+ /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+ MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+ MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+ MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
+ }
+ /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+ MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+ }
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+ #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#elif (MCG_MODE == MCG_MODE_PEE)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+ SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+ while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
+ }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+ SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+ /* PLL loss of lock interrupt request initialization */
+ if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+ NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+ switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+ case 0x38U:
+ Divider = 1536U;
+ break;
+ case 0x30U:
+ Divider = 1280U;
+ break;
+ default:
+ Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ break;
+ }
+ } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+ Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ }
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x00U:
+ MCGOUTClock *= 640U;
+ break;
+ case 0x20U:
+ MCGOUTClock *= 1280U;
+ break;
+ case 0x40U:
+ MCGOUTClock *= 1920U;
+ break;
+ case 0x60U:
+ MCGOUTClock *= 2560U;
+ break;
+ case 0x80U:
+ MCGOUTClock *= 732U;
+ break;
+ case 0xA0U:
+ MCGOUTClock *= 1464U;
+ break;
+ case 0xC0U:
+ MCGOUTClock *= 2197U;
+ break;
+ case 0xE0U:
+ MCGOUTClock *= 2929U;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ /* PLL is selected */
+ Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h
new file mode 100644
index 000000000..ebb7c2dbd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h
@@ -0,0 +1,339 @@
+/*
+** ###################################################################
+** Processor: MK64FN1M0VMD12
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.5, 2014-02-10
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** - rev. 2.5 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.5
+ * @date 2014-02-10
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#define DISABLE_WDOG 1
+
+#ifndef CLOCK_SETUP
+ #define CLOCK_SETUP 4
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+ 0 ... Default part configuration
+ Multipurpose Clock Generator (MCG) in FEI mode.
+ Reference clock source for MCG module: Slow internal reference clock
+ Core clock = 20.97152MHz
+ Bus clock = 20.97152MHz
+ 1 ... Maximum achievable clock frequency configuration
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPI mode.
+ Reference clock source for MCG module: Fast internal reference clock
+ Core clock = 4MHz
+ Bus clock = 4MHz
+ 3 ... Chip externally clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPE mode.
+ Reference clock source for MCG module: RTC oscillator reference clock
+ Core clock = 0.032768MHz
+ Bus clock = 0.032768MHz
+ 4 ... USB clock setup
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#if (CLOCK_SETUP == 0)
+ #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+ #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+ #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
+ /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+ #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
+ /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+ #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+ #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+ #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+ #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct
new file mode 100644
index 000000000..cdc367ab9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct
@@ -0,0 +1,21 @@
+
+; MAX32600
+; 256KB FLASH (0x40000) @ 0x000000000
+; 2KB RAM (0x8000) @ 0x20000000
+
+
+; MAX32600: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment
+ RW_IRAM1 (0x20000000+0x140) (0x8000-0x140) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+} \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s
new file mode 100644
index 000000000..02ece3a3c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s
@@ -0,0 +1,255 @@
+;*******************************************************************************
+; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice shall be included
+; in all copies or substantial portions of the Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+; OTHER DEALINGS IN THE SOFTWARE.
+;
+; Except as contained in this notice, the name of Maxim Integrated
+; Products, Inc. shall not be used except as stated in the Maxim Integrated
+; Products, Inc. Branding Policy.
+;
+; The mere transfer of this software does not imply any licenses
+; of trade secrets, proprietary technology, copyrights, patents,
+; trademarks, maskwork rights, or any other form of intellectual
+; property whatsoever. Maxim Integrated Products, Inc. retains all
+; ownership rights.
+;*******************************************************************************
+
+__initial_sp EQU 0x20008000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD DefaultIRQ_Handler ; MPU Fault Handler
+ DCD DefaultIRQ_Handler ; Bus Fault Handler
+ DCD DefaultIRQ_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DefaultIRQ_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD DefaultIRQ_Handler ; PendSV Handler
+ DCD SysTick_IRQHandler ; SysTick Handler
+
+ ; Maxim 32600 Externals interrupts
+ DCD UART0_IRQHandler ; 16: 1 UART0
+ DCD UART1_IRQHandler ; 17: 2 UART1
+ DCD I2CM0_IRQHandler ; 18: 3 I2C Master 0
+ DCD I2CS_IRQHandler ; 19: 4 I2C Slave
+ DCD USB_IRQHandler ; 20: 5 USB
+ DCD PMU_IRQHandler ; 21: 6 DMA
+ DCD AFE_IRQHandler ; 22: 7 AFE
+ DCD MAA_IRQHandler ; 23: 8 MAA
+ DCD AES_IRQHandler ; 24: 9 AES
+ DCD SPI0_IRQHandler ; 25:10 SPI0
+ DCD SPI1_IRQHandler ; 26:11 SPI1
+ DCD SPI2_IRQHandler ; 27:12 SPI2
+ DCD TMR0_IRQHandler ; 28:13 Timer32-0
+ DCD TMR1_IRQHandler ; 29:14 Timer32-1
+ DCD TMR2_IRQHandler ; 30:15 Timer32-1
+ DCD TMR3_IRQHandler ; 31:16 Timer32-2
+ DCD RSVD0_IRQHandler ; 32:17 RSVD
+ DCD RSVD1_IRQHandler ; 33:18 RSVD
+ DCD DAC0_IRQHandler ; 34:19 DAC0 (12-bit DAC)
+ DCD DAC1_IRQHandler ; 35:20 DAC1 (12-bit DAC)
+ DCD DAC2_IRQHandler ; 36:21 DAC2 (8-bit DAC)
+ DCD DAC3_IRQHandler ; 37:22 DAC3 (8-bit DAC)
+ DCD ADC_IRQHandler ; 38:23 ADC
+ DCD FLC_IRQHandler ; 39:24 Flash Controller
+ DCD PWRMAN_IRQHandler ; 40:25 PWRMAN
+ DCD CLKMAN_IRQHandler ; 41:26 CLKMAN
+ DCD RTC0_IRQHandler ; 42:27 RTC INT0
+ DCD RTC1_IRQHandler ; 43:28 RTC INT1
+ DCD RTC2_IRQHandler ; 44:29 RTC INT2
+ DCD RTC3_IRQHandler ; 45:30 RTC INT3
+ DCD WDT0_IRQHandler ; 46:31 WATCHDOG0
+ DCD WDT0_P_IRQHandler ; 47:32 WATCHDOG0 PRE-WINDOW
+ DCD WDT1_IRQHandler ; 48:33 WATCHDOG1
+ DCD WDT1_P_IRQHandler ; 49:34 WATCHDOG1 PRE-WINDOW
+ DCD GPIO_P0_IRQHandler ; 50:35 GPIO Port 0
+ DCD GPIO_P1_IRQHandler ; 51:36 GPIO Port 1
+ DCD GPIO_P2_IRQHandler ; 52:37 GPIO Port 2
+ DCD GPIO_P3_IRQHandler ; 53:38 GPIO Port 3
+ DCD GPIO_P4_IRQHandler ; 54:39 GPIO Port 4
+ DCD GPIO_P5_IRQHandler ; 55:40 GPIO Port 5
+ DCD GPIO_P6_IRQHandler ; 56:41 GPIO Port 6
+ DCD GPIO_P7_IRQHandler ; 57:42 GPIO Port 7
+ DCD TMR16_0_IRQHandler ; 58:43 Timer16-s0
+ DCD TMR16_1_IRQHandler ; 59:44 Timer16-s1
+ DCD TMR16_2_IRQHandler ; 60:45 Timer16-s2
+ DCD TMR16_3_IRQHandler ; 61:46 Timer16-s3
+ DCD I2CM1_IRQHandler ; 62:47 I2C Master 1
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B NMI_Handler
+ ENDP
+
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B HardFault_Handler
+ ENDP
+
+DefaultIRQ_Handler PROC
+ EXPORT DefaultIRQ_Handler [WEAK]
+ B DefaultIRQ_Handler
+ ENDP
+
+DebugMon_Handler PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B DebugMon_Handler
+ ENDP
+
+SysTick_IRQHandler PROC
+ EXPORT SysTick_IRQHandler [WEAK]
+ B SysTick_IRQHandler
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT I2CM0_IRQHandler [WEAK]
+ EXPORT I2CS_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT PMU_IRQHandler [WEAK]
+ EXPORT AFE_IRQHandler [WEAK]
+ EXPORT MAA_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT RSVD0_IRQHandler [WEAK]
+ EXPORT RSVD1_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DAC3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FLC_IRQHandler [WEAK]
+ EXPORT PWRMAN_IRQHandler [WEAK]
+ EXPORT CLKMAN_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT RTC2_IRQHandler [WEAK]
+ EXPORT RTC3_IRQHandler [WEAK]
+ EXPORT WDT0_IRQHandler [WEAK]
+ EXPORT WDT0_P_IRQHandler [WEAK]
+ EXPORT WDT1_IRQHandler [WEAK]
+ EXPORT WDT1_P_IRQHandler [WEAK]
+ EXPORT GPIO_P0_IRQHandler [WEAK]
+ EXPORT GPIO_P1_IRQHandler [WEAK]
+ EXPORT GPIO_P2_IRQHandler [WEAK]
+ EXPORT GPIO_P3_IRQHandler [WEAK]
+ EXPORT GPIO_P4_IRQHandler [WEAK]
+ EXPORT GPIO_P5_IRQHandler [WEAK]
+ EXPORT GPIO_P6_IRQHandler [WEAK]
+ EXPORT GPIO_P7_IRQHandler [WEAK]
+ EXPORT TMR16_0_IRQHandler [WEAK]
+ EXPORT TMR16_1_IRQHandler [WEAK]
+ EXPORT TMR16_2_IRQHandler [WEAK]
+ EXPORT TMR16_3_IRQHandler [WEAK]
+ EXPORT I2CM1_IRQHandler [WEAK]
+
+UART0_IRQHandler
+UART1_IRQHandler
+I2CM0_IRQHandler
+I2CS_IRQHandler
+USB_IRQHandler
+PMU_IRQHandler
+AFE_IRQHandler
+MAA_IRQHandler
+AES_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+RSVD0_IRQHandler
+RSVD1_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+DAC2_IRQHandler
+DAC3_IRQHandler
+ADC_IRQHandler
+FLC_IRQHandler
+PWRMAN_IRQHandler
+CLKMAN_IRQHandler
+RTC0_IRQHandler
+RTC1_IRQHandler
+RTC2_IRQHandler
+RTC3_IRQHandler
+WDT0_IRQHandler
+WDT0_P_IRQHandler
+WDT1_IRQHandler
+WDT1_P_IRQHandler
+GPIO_P0_IRQHandler
+GPIO_P1_IRQHandler
+GPIO_P2_IRQHandler
+GPIO_P3_IRQHandler
+GPIO_P4_IRQHandler
+GPIO_P5_IRQHandler
+GPIO_P6_IRQHandler
+GPIO_P7_IRQHandler
+TMR16_0_IRQHandler
+TMR16_1_IRQHandler
+TMR16_2_IRQHandler
+TMR16_3_IRQHandler
+I2CM1_IRQHandler
+
+ B .
+ ENDP
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..90d1391ba
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,57 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld
new file mode 100644
index 000000000..2d5c3112e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld
@@ -0,0 +1,182 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+/******************************************************************************
+ *
+ * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S
new file mode 100644
index 000000000..cda4da904
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S
@@ -0,0 +1,262 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Externals interrupts */
+ .long UART0_IRQHandler /* 16: 1 UART0 */
+ .long UART1_IRQHandler /* 17: 2 UART1 */
+ .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ .long I2CS_IRQHandler /* 19: 4 I2C Slave */
+ .long USB_IRQHandler /* 20: 5 USB */
+ .long PMU_IRQHandler /* 21: 6 DMA */
+ .long AFE_IRQHandler /* 22: 7 AFE */
+ .long MAA_IRQHandler /* 23: 8 MAA */
+ .long AES_IRQHandler /* 24: 9 AES */
+ .long SPI0_IRQHandler /* 25:10 SPI0 */
+ .long SPI1_IRQHandler /* 26:11 SPI1 */
+ .long SPI2_IRQHandler /* 27:12 SPI2 */
+ .long TMR0_IRQHandler /* 28:13 Timer32-0 */
+ .long TMR1_IRQHandler /* 29:14 Timer32-1 */
+ .long TMR2_IRQHandler /* 30:15 Timer32-1 */
+ .long TMR3_IRQHandler /* 31:16 Timer32-2 */
+ .long RSVD0_IRQHandler /* 32:17 RSVD */
+ .long RSVD1_IRQHandler /* 33:18 RSVD */
+ .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ .long ADC_IRQHandler /* 38:23 ADC */
+ .long FLC_IRQHandler /* 39:24 Flash Controller */
+ .long PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ .long CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ .long RTC0_IRQHandler /* 42:27 RTC INT0 */
+ .long RTC1_IRQHandler /* 43:28 RTC INT1 */
+ .long RTC2_IRQHandler /* 44:29 RTC INT2 */
+ .long RTC3_IRQHandler /* 45:30 RTC INT3 */
+ .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */
+ def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */
+ def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */
+ def_irq_default_handler USB_IRQHandler /* 20: 5 USB */
+ def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */
+ def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */
+ def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */
+ def_irq_default_handler AES_IRQHandler /* 24: 9 AES */
+ def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */
+ def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */
+ def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */
+ def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */
+ def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */
+ def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */
+ def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */
+ def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */
+ def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */
+ def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */
+ def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */
+ def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */
+ def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */
+ def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */
+ def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */
+ def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf
new file mode 100644
index 000000000..2b90dc973
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf
@@ -0,0 +1,29 @@
+/* [ROM] */
+define symbol __intvec_start__ = 0x0;
+define symbol __region_ROM_start__ = 0x0;
+define symbol __region_ROM_end__ = 0x0003FFFF;
+
+/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */
+define symbol __NVIC_start__ = 0x00000000;
+define symbol __NVIC_end__ = 0x00000140; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000000;
+define symbol __region_RAM_end__ = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x800;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s
new file mode 100644
index 000000000..740a9150b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s
@@ -0,0 +1,383 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table DCD sfe(CSTACK) /* Top of Stack */
+ DCD Reset_Handler /* Reset Handler */
+ DCD NMI_Handler /* NMI Handler */
+ DCD HardFault_Handler /* Hard Fault Handler */
+ DCD DefaultIRQ_Handler /* MPU Fault Handler */
+ DCD DefaultIRQ_Handler /* Bus Fault Handler */
+ DCD DefaultIRQ_Handler /* Usage Fault Handler */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD DefaultIRQ_Handler /* SVCall Handler */
+ DCD DebugMon_Handler /* Debug Monitor Handler */
+ DCD 0 /* Reserved */
+ DCD DefaultIRQ_Handler /* PendSV Handler */
+ DCD SysTick_IRQHandler /* SysTick Handler */
+
+ /* Maxim 32600 Externals interrupts */
+ DCD UART0_IRQHandler /* 16: 1 UART0 */
+ DCD UART1_IRQHandler /* 17: 2 UART1 */
+ DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ DCD I2CS_IRQHandler /* 19: 4 I2C Slave */
+ DCD USB_IRQHandler /* 20: 5 USB */
+ DCD PMU_IRQHandler /* 21: 6 DMA */
+ DCD AFE_IRQHandler /* 22: 7 AFE */
+ DCD MAA_IRQHandler /* 23: 8 MAA */
+ DCD AES_IRQHandler /* 24: 9 AES */
+ DCD SPI0_IRQHandler /* 25:10 SPI0 */
+ DCD SPI1_IRQHandler /* 26:11 SPI1 */
+ DCD SPI2_IRQHandler /* 27:12 SPI2 */
+ DCD TMR0_IRQHandler /* 28:13 Timer32-0 */
+ DCD TMR1_IRQHandler /* 29:14 Timer32-1 */
+ DCD TMR2_IRQHandler /* 30:15 Timer32-1 */
+ DCD TMR3_IRQHandler /* 31:16 Timer32-2 */
+ DCD RSVD0_IRQHandler /* 32:17 RSVD */
+ DCD RSVD1_IRQHandler /* 33:18 RSVD */
+ DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ DCD ADC_IRQHandler /* 38:23 ADC */
+ DCD FLC_IRQHandler /* 39:24 Flash Controller */
+ DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ DCD RTC0_IRQHandler /* 42:27 RTC INT0 */
+ DCD RTC1_IRQHandler /* 43:28 RTC INT1 */
+ DCD RTC2_IRQHandler /* 44:29 RTC INT2 */
+ DCD RTC3_IRQHandler /* 45:30 RTC INT3 */
+ DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+ THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK DefaultIRQ_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DefaultIRQ_Handler
+ B DefaultIRQ_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK SysTick_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_IRQHandler
+ B SysTick_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK I2CM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM0_IRQHandler
+ B I2CM0_IRQHandler
+
+ PUBWEAK I2CS_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CS_IRQHandler
+ B I2CS_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ PUBWEAK PMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PMU_IRQHandler
+ B PMU_IRQHandler
+
+ PUBWEAK AFE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AFE_IRQHandler
+ B AFE_IRQHandler
+
+ PUBWEAK MAA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MAA_IRQHandler
+ B MAA_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK TMR0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR0_IRQHandler
+ B TMR0_IRQHandler
+
+ PUBWEAK TMR1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_IRQHandler
+ B TMR1_IRQHandler
+
+ PUBWEAK TMR2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+ B TMR2_IRQHandler
+
+ PUBWEAK TMR3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+ B TMR3_IRQHandler
+
+ PUBWEAK RSVD0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD0_IRQHandler
+ B RSVD0_IRQHandler
+
+ PUBWEAK RSVD1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD1_IRQHandler
+ B RSVD1_IRQHandler
+
+ PUBWEAK DAC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC0_IRQHandler
+ B DAC0_IRQHandler
+
+ PUBWEAK DAC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC1_IRQHandler
+ B DAC1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DAC3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC3_IRQHandler
+ B DAC3_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FLC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLC_IRQHandler
+ B FLC_IRQHandler
+
+ PUBWEAK PWRMAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWRMAN_IRQHandler
+ B PWRMAN_IRQHandler
+
+ PUBWEAK CLKMAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLKMAN_IRQHandler
+ B CLKMAN_IRQHandler
+
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B RTC0_IRQHandler
+
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B RTC1_IRQHandler
+
+ PUBWEAK RTC2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC2_IRQHandler
+ B RTC2_IRQHandler
+
+ PUBWEAK RTC3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC3_IRQHandler
+ B RTC3_IRQHandler
+
+ PUBWEAK WDT0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_IRQHandler
+ B WDT0_IRQHandler
+
+ PUBWEAK WDT0_P_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_P_IRQHandler
+ B WDT0_P_IRQHandler
+
+ PUBWEAK WDT1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_IRQHandler
+ B WDT1_IRQHandler
+
+ PUBWEAK WDT1_P_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_P_IRQHandler
+ B WDT1_P_IRQHandler
+
+ PUBWEAK GPIO_P0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P0_IRQHandler
+ B GPIO_P0_IRQHandler
+
+ PUBWEAK GPIO_P1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P1_IRQHandler
+ B GPIO_P1_IRQHandler
+
+ PUBWEAK GPIO_P2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P2_IRQHandler
+ B GPIO_P2_IRQHandler
+
+ PUBWEAK GPIO_P3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P3_IRQHandler
+ B GPIO_P3_IRQHandler
+
+ PUBWEAK GPIO_P4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P4_IRQHandler
+ B GPIO_P4_IRQHandler
+
+ PUBWEAK GPIO_P5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P5_IRQHandler
+ B GPIO_P5_IRQHandler
+
+ PUBWEAK GPIO_P6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P6_IRQHandler
+ B GPIO_P6_IRQHandler
+
+ PUBWEAK GPIO_P7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P7_IRQHandler
+ B GPIO_P7_IRQHandler
+
+ PUBWEAK TMR16_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_0_IRQHandler
+ B TMR16_0_IRQHandler
+
+ PUBWEAK TMR16_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_1_IRQHandler
+ B TMR16_1_IRQHandler
+
+ PUBWEAK TMR16_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_2_IRQHandler
+ B TMR16_2_IRQHandler
+
+ PUBWEAK TMR16_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_3_IRQHandler
+ B TMR16_3_IRQHandler
+
+ PUBWEAK I2CM1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM1_IRQHandler
+ B I2CM1_IRQHandler
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h
new file mode 100644
index 000000000..4e4d5299c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h
@@ -0,0 +1,466 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ADC_REGS_H
+#define _MXC_ADC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file adc_regs.h
+ * @addtogroup adc ADC
+ * @{
+ */
+
+/**
+ * @brief Defines ADC Modes.
+ */
+typedef enum {
+ /** Single Mode Full Rate */
+ MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
+ /** Single Mode Low Power */
+ MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
+ /** Continuous Mode Full Rate */
+ MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
+ /** Continuous Mode Low Power */
+ MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
+ /** Single Mode Full Rate with Scan Enabled */
+ MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
+ /** Single Mode Low Power with Scan Enabled */
+ MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
+ /** Continuous Mode Full Rate with Scan Enabled */
+ MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
+ /** Continuous Mode Low Power with Scan Enabled */
+ MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
+} mxc_adc_mode_t;
+
+/**
+ * @brief Defines ADC Range Control.
+ */
+typedef enum {
+ /** Bi-polar Operation (-Vref/2 -> Vref/2) */
+ MXC_E_ADC_RANGE_HALF = 0,
+ /** Bi-polar Operation (-Vref -> Vref) */
+ MXC_E_ADC_RANGE_FULL
+} mxc_adc_range_t;
+
+/**
+ * @brief Defines ADC Bipolar operation.
+ */
+typedef enum {
+ /** Uni-polar operation (0 -> Vref) */
+ MXC_E_ADC_BI_POL_UNIPOLAR = 0,
+ /** Bi-polar operation see ADC Range Control */
+ MXC_E_ADC_BI_POL_BIPOLAR
+} mxc_adc_bi_pol_t;
+
+/**
+ * @brief Defines Decimation Filter Modes.
+ */
+typedef enum {
+ /** Decimation Filter ByPassed */
+ MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
+ /** Output Average Only*/
+ MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
+ /** Output Average and Raw Data (Test Mode Only) */
+ MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
+} mxc_adc_avg_mode_t;
+
+/**
+ * @brief Defines ADC StartMode Modes.
+ */
+typedef enum {
+ /** StarMode via Software */
+ MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
+ /** StarMode via PulseTrain */
+ MXC_E_ADC_STRT_MODE_PULSETRAIN
+} mxc_adc_strt_mode_t;
+
+/**
+ * @brief Defines Mux Channel Select for the Positive Input to the ADC.
+ */
+typedef enum {
+ /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
+ /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
+ /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
+ /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
+ /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
+ /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
+ /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
+ /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
+ /** Single Mode Input AIN8+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
+ /** Single Mode Input AIN9+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
+ /** Single Mode Input AIN10+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
+ /** Single Mode Input AIN11+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
+ /** Single Mode Input AIN12+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
+ /** Single Mode Input AIN13+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
+ /** Single Mode Input AIN14+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
+ /** Single Mode Input AIN15+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
+ /** Positive Input VSSADC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
+ /** Positive Input TMON_R */
+ MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
+ /** Positive Input VDDA/4 */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
+ /** Positive Input PWRMAN_TST */
+ MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
+ /** Positive Input Ain0Div */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
+ /** Positive Input OpAmp OUTA */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
+ /** Positive Input OpAmp OUTB */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
+ /** Positive Input OpAmp OUTC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
+ /** Positive Input OpAmp OUTD */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
+ /** Positive INA+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
+ /** Positive SNO_or */
+ MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
+ /** Positive SCM_or */
+ MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
+ /** Positive TPROBE_sense */
+ MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
+ /** Positive VREFDAC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
+ /** Positive VREFADJ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
+ /** Positive Vdd3xtal */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
+} mxc_adc_pga_mux_ch_sel_t;
+
+/**
+ * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
+ */
+typedef enum {
+ /** Differential Mode Disabled */
+ MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
+ /** Differential Mode Enabled */
+ MXC_E_ADC_PGA_MUX_DIFF_ENABLE
+} mxc_adc_pga_mux_diff_t;
+
+/**
+ * @brief Defines the PGA Gain Options.
+ */
+typedef enum {
+ /** PGA Gain = 1 */
+ MXC_E_ADC_PGA_GAIN_1 = 0,
+ /** PGA Gain = 2 */
+ MXC_E_ADC_PGA_GAIN_2,
+ /** PGA Gain = 4 */
+ MXC_E_ADC_PGA_GAIN_4,
+ /** PGA Gain = 8 */
+ MXC_E_ADC_PGA_GAIN_8,
+} mxc_adc_pga_gain_t;
+
+/**
+ * @brief Defines the Switch Control Mode.
+ */
+typedef enum {
+ /** Switch Control Mode = Software */
+ MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
+ /** Switch Control Mode = Pulse Train */
+ MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
+} mxc_adc_spst_sw_ctrl_t;
+
+/**
+ * @brief Defines the number of channels to scan when Scan Mode is enabled.
+ */
+typedef enum {
+ /** Number of Channels to Scan = 1 */
+ MXC_E_ADC_SCAN_CNT_1 = 0,
+ /** Number of Channels to Scan = 2 */
+ MXC_E_ADC_SCAN_CNT_2,
+ /** Number of Channels to Scan = 3 */
+ MXC_E_ADC_SCAN_CNT_3,
+ /** Number of Channels to Scan = 4 */
+ MXC_E_ADC_SCAN_CNT_4,
+ /** Number of Channels to Scan = 5 */
+ MXC_E_ADC_SCAN_CNT_5,
+ /** Number of Channels to Scan = 6 */
+ MXC_E_ADC_SCAN_CNT_6,
+ /** Number of Channels to Scan = 7 */
+ MXC_E_ADC_SCAN_CNT_7,
+ /** Number of Channels to Scan = 8 */
+ MXC_E_ADC_SCAN_CNT_8,
+} mxc_adc_scan_cnt_t;
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
+ __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
+ __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
+ __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
+ __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
+ __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
+ __IO uint32_t out; /* 0x0018 ADC Output Register */
+} mxc_adc_regs_t;
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
+ __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
+ __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
+ __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
+ __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
+} mxc_adccfg_regs_t;
+
+typedef struct {
+ __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
+} mxc_adc_fifo_regs_t;
+
+/*
+ Register offsets for module ADC, ADCCFG, ADC_FIFO
+*/
+#define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
+#define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
+#define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
+#define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
+
+#define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
+#define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
+#define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
+
+/*
+ Field positions and masks for module ADC.
+*/
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
+#define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
+#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
+#define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
+#define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_POS 9
+#define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
+#define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
+#define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
+#define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
+#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
+#define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
+#define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
+
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
+
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
+
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
+
+#define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
+#define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
+
+#define MXC_F_ADC_INTR_FIFO_AF_POS 6
+#define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
+#define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
+#define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
+#define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
+#define MXC_F_ADC_INTR_DONE_IF_POS 10
+#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
+#define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
+#define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
+#define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
+#define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
+#define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
+#define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
+#define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
+#define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
+#define MXC_F_ADC_INTR_DONE_IE_POS 26
+#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
+#define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
+#define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
+#define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
+#define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
+#define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
+
+#define MXC_F_ADC_OUT_DATA_REG_POS 0
+#define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
+
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
+
+#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
+#define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
+#define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
+#define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
+#define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
+
+#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
+#define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
+#define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
+#define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
+#define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
+
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
+#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
+#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
+
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
+#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
+#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
+#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_ADC_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h
new file mode 100644
index 000000000..cf9995be4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h
@@ -0,0 +1,159 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AES_REGS_H_
+#define _MXC_AES_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file aes_regs.h
+ * @addtogroup aes AES
+ * @{
+ */
+
+/**
+ * @brief Settings for AES_CTRL.CRYPT_MODE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
+ MXC_E_AES_CTRL_DECRYPT_MODE = 1
+} mxc_aes_ctrl_crypt_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.EXP_KEY_MODE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
+ MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
+} mxc_aes_ctrl_exp_key_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.KEY_SIZE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
+ MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
+ MXC_E_AES_CTRL_KEY_SIZE_256 = 2
+} mxc_aes_ctrl_key_size_t;
+
+/* Offset Register Description
+ ====== =========================================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 AES Control and Status */
+ __I uint32_t rsv004; /* 0x0004 */
+ __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */
+} mxc_aes_regs_t;
+
+/* Offset Register Description
+ ====== =========================================================== */
+typedef struct {
+ __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */
+ __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */
+ __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */
+ __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */
+} mxc_aes_mem_regs_t;
+
+/*
+ Register offsets for module AES.
+*/
+#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL)
+#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL)
+#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL)
+#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL)
+#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL)
+#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL)
+#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL)
+#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL)
+#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL)
+#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL)
+#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL)
+#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL)
+#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL)
+#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL)
+#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL)
+
+#define MXC_F_AES_CTRL_START_POS 0
+#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
+#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1
+#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2
+#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_F_AES_CTRL_KEY_SIZE_POS 3
+#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_F_AES_CTRL_INTEN_POS 5
+#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
+#define MXC_F_AES_CTRL_INTFL_POS 6
+#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
+
+#define MXC_V_AES_CTRL_ENCRYPT_MODE 0
+#define MXC_V_AES_CTRL_DECRYPT_MODE 1
+#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+
+#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0
+#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1
+#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+
+#define MXC_V_AES_CTRL_KEY_SIZE_128 0
+#define MXC_V_AES_CTRL_KEY_SIZE_192 1
+#define MXC_V_AES_CTRL_KEY_SIZE_256 2
+#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_AES_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h
new file mode 100644
index 000000000..31a3f7cb8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h
@@ -0,0 +1,626 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AFE_REGS_H
+#define _MXC_AFE_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file afe_regs.h
+ * @addtogroup afe AFE
+ * @{
+ */
+
+/**
+ * @brief Defines Configure Options for the LED Ports.
+ */
+typedef enum {
+ /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
+ MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
+ /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
+ MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
+ /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
+ MXC_E_AFE_LED_CFG_PORT_DISABLED,
+} mxc_afe_led_cfg_port_t;
+
+/**
+ * @brief Setup of Wake Up Detector for LPCs.
+ */
+typedef enum {
+ /** IDLE */
+ MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
+ /** Activate WUD for falling edges */
+ MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
+ /** Activate WUD for rising edges */
+ MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
+} mxc_afe_en_wud_comp_t;
+
+/**
+ * @brief LPC InMode.
+ */
+typedef enum {
+ /** InMode: both Nch and Pch */
+ MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
+ /** InMode: only Nch */
+ MXC_E_AFE_IN_MODE_COMP_NCH,
+ /** InMode: only Pch */
+ MXC_E_AFE_IN_MODE_COMP_PCH,
+} mxc_afe_in_mode_comp_t;
+
+/**
+ * @brief LPC Bias.
+ */
+typedef enum {
+ /** BIAS 0.52uA Delay 4.0us */
+ MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
+ /** BIAS 1.4uA Delay 1.7us */
+ MXC_E_AFE_BIAS_MODE_COMP_1,
+ /** BIAS 2.8uA Delay 1.1us */
+ MXC_E_AFE_BIAS_MODE_COMP_2,
+ /** BIAS 5.1uA Delay 0.7us */
+ MXC_E_AFE_BIAS_MODE_COMP_3
+} mxc_afe_bias_mode_comp_t;
+
+/**
+ * @brief TMON Current Value.
+ */
+typedef enum {
+ /** TMON Current 4uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
+ /** TMON Current 60uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_1,
+ /** TMON Current 64uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_2,
+ /** TMON Current 120uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_3
+} mxc_afe_tmon_current_t;
+
+/**
+ * @brief REFADC and REFDAC Voltage Select.
+ */
+typedef enum {
+ /** Voltage Reference = 1.024 V */
+ MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
+ /** Voltage Reference = 1.5 V */
+ MXC_E_AFE_REF_VOLT_SEL_1500,
+ /** Voltage Reference = 2.048 V */
+ MXC_E_AFE_REF_VOLT_SEL_2048,
+ /** Voltage Reference = 2.5 V */
+ MXC_E_AFE_REF_VOLT_SEL_2500
+} mxc_afe_ref_volt_sel_t;
+
+/**
+ * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
+ */
+typedef enum {
+ /** DAC Voltage Reference = REFADC */
+ MXC_E_AFE_DAC_REF_REFADC = 0,
+ /** DAC Voltage Reference = REFDAC */
+ MXC_E_AFE_DAC_REF_REFDAC
+} mxc_afe_dac_ref_t;
+
+/**
+ * @brief Selection for LPC Hysteresis.
+ */
+typedef enum {
+ /** LPC Hysteresis = 0 mV */
+ MXC_E_AFE_HYST_COMP_0 = 0,
+ /** LPC Hysteresis = 7.5 mV */
+ MXC_E_AFE_HYST_COMP_1,
+ /** LPC Hysteresis = 15 mV */
+ MXC_E_AFE_HYST_COMP_2,
+ /** LPC Hysteresis = 30 mV */
+ MXC_E_AFE_HYST_COMP_3
+} mxc_afe_hyst_comp_t;
+
+/**
+ * @brief Selection for MUX for SCM_or_sel.
+ */
+typedef enum {
+ /** SCM_or = HIZ */
+ MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
+ /** SCM_or = SCM0 */
+ MXC_E_AFE_SCM_OR_SEL_SCM0,
+ /** SCM_or = SCM1 */
+ MXC_E_AFE_SCM_OR_SEL_SCM1,
+ /** SCM_or = SCM2 */
+ MXC_E_AFE_SCM_OR_SEL_SCM2,
+ /** SCM_or = SCM3 */
+ MXC_E_AFE_SCM_OR_SEL_SCM3
+} mxc_afe_scm_or_sel_t;
+
+/**
+ * @brief Selection for MUX for SNO_or_sel.
+ */
+typedef enum {
+ /** SNO_or = HIZ */
+ MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
+ /** SNO_or = SNO0 */
+ MXC_E_AFE_SNO_OR_SEL_SNO0,
+ /** SNO_or = SNO1 */
+ MXC_E_AFE_SNO_OR_SEL_SNO1,
+ /** SNO_or = SNO2 */
+ MXC_E_AFE_SNO_OR_SEL_SNO2,
+ /** SNO_or = SNO3 */
+ MXC_E_AFE_SNO_OR_SEL_SNO3
+} mxc_afe_sno_or_sel_t;
+
+/**
+ * @brief Selection for MUX DACx_sel.
+ */
+typedef enum {
+ /** dacx = DACOP */
+ MXC_E_AFE_DACX_SEL_P = 0,
+ /** dacx = DACON */
+ MXC_E_AFE_DACX_SEL_N
+} mxc_afe_dacx_sel_t;
+
+/**
+ * @brief Selection for state of Switch.
+ */
+typedef enum {
+ /** Switch is OPEN */
+ MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
+ /** Switch is CLOSED */
+ MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
+} mxc_afe_close_spst_t;
+
+/**
+ * @brief Switch to Connect Positive Pad to GND.
+ */
+typedef enum {
+ /** Positive Pad GND Switch OPEN */
+ MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
+ /** Positive Pad GND Switch CLOSED */
+ MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
+} mxc_afe_gnd_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpPsel.
+ */
+typedef enum {
+ /** OpPsel = INx+ */
+ MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
+ /** OpPsel = DAC_or */
+ MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
+ /** OpPsel = SNO_or */
+ MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
+ /** OpPsel = DAC_or also output on INx+ */
+ MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
+} mxc_afe_p_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpNsel.
+ */
+typedef enum {
+ /** OpNsel = INx- */
+ MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
+ /** OpNsel = OUTx */
+ MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
+ /** OpNsel = SCM_or */
+ MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
+ /**OpNsel = SCM_or also output on INx- */
+ MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
+} mxc_afe_n_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for DAC_sel.
+ */
+typedef enum {
+ /** DAC_or = DAC0 */
+ MXC_E_AFE_DAC_SEL_DAC0 = 0,
+ /** DAC_or = DAC1 */
+ MXC_E_AFE_DAC_SEL_DAC1,
+ /** DAC_or = DAC2P */
+ MXC_E_AFE_DAC_SEL_DAC2P,
+ /** DAC_or = DAC3P */
+ MXC_E_AFE_DAC_SEL_DAC3P
+} mxc_afe_dac_sel_t;
+
+/**
+ * @brief MUX Selection for NPAD_sel.
+ */
+typedef enum {
+ /** NPAD_Sel = HIZ */
+ MXC_E_AFE_NPAD_SEL_HIZ = 0,
+ /** NPAD_Sel = LED Observe Port */
+ MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
+ /** NPAD_Sel = DAC_or */
+ MXC_E_AFE_NPAD_SEL_DAC_OR,
+ /** NPAD_Sel = DAC_or and LED Observe Port */
+ MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
+} mxc_afe_npad_sel_t;
+
+/**
+ * @brief MUX Selection for CmpPSel.
+ */
+typedef enum {
+ /** CmpPSel = INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
+ /** CmpPSel = SCM */
+ MXC_E_AFE_POS_IN_SEL_COMP_SCM,
+ /** CmpPSel = dac1 */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
+ /** CmpPSel = DAC3P */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
+ /** CmpPSel = LED Observe Port */
+ MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
+ /** CmpPSel = dac1 also output on INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
+ /** CmpPSel = DAC3P also output on INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
+ /** CmpPSel = dac1 also output on SCM */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
+} mxc_afe_pos_in_sel_comp_t;
+
+/**
+ * @brief MUX Selection for CmpNSel.
+ */
+typedef enum {
+ /** CmpNSel = INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
+ /** CmpNSel = SNO */
+ MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
+ /** CmpNSel = dac0 */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
+ /** CmpNSel = DAC2P */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
+ /** CmpNSel = LED Observation Port */
+ MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
+ /** CmpNSel = dac0 also output on INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
+ /** CmpNSel = DAC2 also output on INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
+ /** CmpNSel = DAC2 also output on SNO */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
+} mxc_afe_neg_in_sel_comp_t;
+
+/* Offset Register Description
+ ====== ==================================================== */
+typedef struct {
+ __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */
+ __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */
+ __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */
+ __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */
+ __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */
+ __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */
+ __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */
+} mxc_afe_regs_t;
+
+/*
+ Register offsets for module AFE.
+*/
+#define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL)
+#define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL)
+#define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL)
+#define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL)
+#define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL)
+#define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL)
+#define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL)
+
+/*
+ Field positions and masks for module AFE.
+*/
+#define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0
+#define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1
+#define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2
+#define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3
+#define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4
+#define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5
+#define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6
+#define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7
+#define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16
+#define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17
+#define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18
+#define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19
+#define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20
+#define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21
+#define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22
+#define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23
+#define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24
+#define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25
+#define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26
+#define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27
+#define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28
+#define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29
+#define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30
+#define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31
+#define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
+
+#define MXC_F_AFE_CTRL0_LED_CFG_POS 0
+#define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
+
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_SEL_POS 10
+#define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
+#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23
+#define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
+#define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25
+#define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
+
+#define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0
+#define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2
+#define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4
+#define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6
+#define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16
+#define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17
+#define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18
+#define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19
+#define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26
+#define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27
+#define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
+
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
+
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16
+#define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18
+#define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20
+#define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22
+#define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
+
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP0_POS 24
+#define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP1_POS 25
+#define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP2_POS 26
+#define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP3_POS 27
+#define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_AFE_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h
new file mode 100644
index 000000000..28a258b99
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h
@@ -0,0 +1,493 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file clkman_regs.h
+ * @addtogroup clkman CLKMAN
+ * @{
+ */
+
+/**
+ * @brief Defines clock input selections for the phase locked loop.
+ */
+typedef enum {
+ /** Input select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
+ /** Input select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
+} mxc_clkman_pll_input_select_t;
+
+/**
+ * @brief Defines clock input frequency for the phase locked loop.
+ */
+typedef enum {
+ /** Input frequency of 24MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
+ /** Input frequency of 12MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
+ /** Input frequency of 8MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
+} mxc_clkman_pll_divisor_select_t;
+
+/**
+ * @brief Defines terminal count for PLL stable.
+ */
+typedef enum {
+ /** Clock stable after 2^8 = 256 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
+ /** Clock stable after 2^9 = 512 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
+ /** Clock stable after 2^10 = 1024 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
+ /** Clock stable after 2^11 = 2048 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
+ /** Clock stable after 2^12 = 4096 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
+ /** Clock stable after 2^13 = 8192 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
+ /** Clock stable after 2^14 = 16384 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
+ /** Clock stable after 2^15 = 32768 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
+ /** Clock stable after 2^16 = 65536 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
+ /** Clock stable after 2^17 = 131072 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
+ /** Clock stable after 2^18 = 262144 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
+ /** Clock stable after 2^19 = 524288 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
+ /** Clock stable after 2^20 = 1048576 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
+ /** Clock stable after 2^21 = 2097152 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
+ /** Clock stable after 2^22 = 4194304 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
+ /** Clock stable after 2^23 = 8388608 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
+} mxc_clkman_stability_count_t;
+
+/**
+ * @brief Defines clock source selections for system clock.
+ */
+typedef enum {
+ /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
+ /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
+} mxc_clkman_system_source_select_t;
+
+/**
+ * @brief Defines clock source selections for analog to digital converter clock.
+ */
+typedef enum {
+ /** Clock select for system clock frequency */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
+ /** Clock select for 8MHz phase locked loop output */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
+} mxc_clkman_adc_source_select_t;
+
+/**
+ * @brief Defines clock source selections for watchdog timer clock.
+ */
+typedef enum {
+ /** Clock select for system clock frequency */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
+ /** Clock select for 8MHz phase locked loop output */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
+} mxc_clkman_wdt_source_select_t;
+
+/**
+ * @brief Defines clock scales for various clocks.
+ */
+typedef enum {
+ /** Clock disabled */
+ MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
+ /** Clock enabled */
+ MXC_E_CLKMAN_CLK_SCALE_ENABLED,
+ /** Clock scale for dividing by 2 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_2,
+ /** Clock scale for dividing by 4 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_4,
+ /** Clock scale for dividing by 8 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_8,
+ /** Clock scale for dividing by 16 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_16,
+ /** Clock scale for dividing by 32 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_32,
+ /** Clock scale for dividing by 64 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_64,
+ /** Clock scale for dividing by 128 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_128,
+ /** Clock scale for dividing by 256 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_256
+} mxc_clkman_clk_scale_t;
+
+/**
+ * @brief Defines Setting of the Clock Gates .
+ */
+typedef enum {
+ /** Clock Gater is Off */
+ MXC_E_CLKMAN_CLK_GATE_OFF = 0,
+ /** Clock Gater is Dynamic */
+ MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
+ /** Clock Gater is On */
+ MXC_E_CLKMAN_CLK_GATE_ON
+} mxc_clkman_clk_gate_t;
+
+/* Offset Register Description
+ ====== ===================================================================== */
+typedef struct {
+ __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
+ __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
+ __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
+ __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
+ __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
+ __I uint32_t rsv0014[4]; /* 0x0014 */
+ __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
+ __I uint32_t rsv0028[6]; /* 0x0028 */
+ __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
+ __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
+ __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
+ __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
+ __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
+ __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
+ __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
+ __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
+ __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
+ __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
+ __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
+ __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
+ __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
+ __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
+ __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
+ __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
+ __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
+ __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
+ __I uint32_t rsv0088[30]; /* 0x0088 */
+ __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
+ __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
+ __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
+ __I uint32_t rsv010C[13]; /* 0x010C */
+ __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
+ __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
+ __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
+} mxc_clkman_regs_t;
+
+/*
+ Register offsets for module CLKMAN.
+*/
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
+
+/*
+ Field positions and masks for module CLKMAN.
+*/
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+
+#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
+#define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
+#define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_CLKMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h
new file mode 100644
index 000000000..cce733185
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h
@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "max32600.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c
new file mode 100644
index 000000000..369427304
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c
@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "cmsis_nvic.h"
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
+__attribute__((aligned(256)))
+#endif
+#if defined(TOOLCHAIN_IAR)
+#pragma data_alignment=256
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR != (uint32_t)ramVectorTable) {
+ uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
+ vectors = (uint32_t*)ramVectorTable;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)ramVectorTable;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h
new file mode 100644
index 000000000..d3e544761
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_CMSIS_NVIC_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h
new file mode 100644
index 000000000..6acec1104
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h
@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CRC_REGS_H_
+#define _MXC_CRC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file crc_regs.h
+ * @addtogroup crc CRC
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */
+ __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */
+ __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */
+} mxc_crc_regs_t;
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t value16[512]; /* 0x0000 Write Next CRC-16 Data Value / Read CRC-16 Result Value */
+ __IO uint32_t value32[512]; /* 0x0800 Write Next CRC-32 Data Value / Read CRC-32 Result Value */
+} mxc_crc_data_regs_t;
+
+/*
+ Register offsets for module CRC.
+*/
+#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL)
+#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module CRC.
+*/
+#define MXC_F_CRC_RESEED_CRC16_POS 0
+#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS))
+#define MXC_F_CRC_RESEED_CRC32_POS 1
+#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_CRC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h
new file mode 100644
index 000000000..2f0f4bd8c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h
@@ -0,0 +1,180 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_DAC_REGS_H
+#define _MXC_DAC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file dac_regs.h
+ * @addtogroup dac DAC
+ * @{
+ */
+
+/**
+ * @brief Defines the DAC Operational Modes.
+ */
+typedef enum {
+ /** DAC OpMode FIFO */
+ MXC_E_DAC_OP_MODE_FIFO = 0,
+ /** DAC OpMode Sample Count */
+ MXC_E_DAC_OP_MODE_DACSMPLCNT,
+ /** DAC OpMode DAC_REG Control */
+ MXC_E_DAC_OP_MODE_DAC_REG,
+ /** DAC OpMode Continuous */
+ MXC_E_DAC_OP_MODE_CONTINUOUS
+} mxc_dac_op_mode_t;
+
+/**
+ * @brief Defines the DAC Interpolation Options.
+ */
+typedef enum {
+ /** DAC Interpolation is Disabled */
+ MXC_E_DAC_INTERP_MODE_DISABLED = 0,
+ /** DAC Interpolation 2:1 */
+ MXC_E_DAC_INTERP_MODE_2_TO_1,
+ /** DAC Interpolation 4:1 */
+ MXC_E_DAC_INTERP_MODE_4_TO_1,
+ /** DAC Interpolation 8:1 */
+ MXC_E_DAC_INTERP_MODE_8_TO_1
+} mxc_dac_interp_mode_t;
+
+/**
+ * @brief Defines the DAC Start Modes.
+ */
+typedef enum {
+ /** Start on FIFO Not Empty */
+ MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
+ /** Start on ADC generated Start Strobe */
+ MXC_E_DAC_START_MODE_ADC_STROBE,
+ /** Start on DAC generated Start Strobe */
+ MXC_E_DAC_START_MODE_DAC_STROBE
+} mxc_dac_start_mode_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */
+ __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */
+ __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */
+ __IO uint32_t reg; /* 0x000C DAC Data Register */
+ __IO uint32_t trm; /* 0x0010 DAC Trim Register */
+} mxc_dac_regs_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ union {
+ __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */
+ __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */
+ };
+} mxc_dac_fifo_t;
+
+/*
+ Register offsets for module DAC12.
+*/
+#define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
+#define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL)
+#define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL)
+#define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL)
+
+/*
+ Field positions and masks for module DAC.
+*/
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8
+#define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
+#define MXC_F_DAC_CTRL0_START_MODE_POS 16
+#define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
+#define MXC_F_DAC_CTRL0_CPU_START_POS 20
+#define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
+#define MXC_F_DAC_CTRL0_OP_MODE_POS 24
+#define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
+#define MXC_F_DAC_CTRL0_POWER_ON_POS 28
+#define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30
+#define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
+#define MXC_F_DAC_CTRL0_RESET_POS 31
+#define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
+
+#define MXC_F_DAC_RATE_RATE_CNT_POS 0
+#define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
+#define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16
+#define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
+
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _DAC12_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h
new file mode 100644
index 000000000..864c8c9b9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h
@@ -0,0 +1,210 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_FLC_REGS_H
+#define _MXC_FLC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file flc_regs.h
+ * @addtogroup flc FLC
+ * @{
+ */
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
+ __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
+ __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
+ __I uint32_t rsv000C[6]; /* 0x000C */
+ __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __I uint32_t rsv0028[2]; /* 0x0028 */
+ __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
+ __I uint32_t rsv0034[7]; /* 0x0034 */
+ __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
+ __I uint32_t rsv0054[11]; /* 0x0054 */
+ __IO uint32_t status; /* 0x0080 Security Status Flags */
+ __I uint32_t rsv0084; /* 0x0084 */
+ __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
+ __I uint32_t rsv008C[4]; /* 0x008C */
+ __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
+ __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
+ __I uint32_t rsv0104[15]; /* 0x0104 */
+ __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
+ __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
+ __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
+ __I uint32_t rsv014C; /* 0x014C */
+ __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
+} mxc_flc_regs_t;
+
+/*
+ Register offsets for module FLC.
+*/
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
+
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
+
+/*
+ Field positions and masks for module FLC.
+*/
+#define MXC_F_FLC_FADDR_FADDR_POS 0
+#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
+
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
+#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
+
+#define MXC_F_FLC_CTRL_WRITE_POS 0
+#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
+#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
+#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
+#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
+#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
+#define MXC_F_FLC_CTRL_PENDING_POS 24
+#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
+
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
+
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
+
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
+#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
+
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
+
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
+
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
+#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
+
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
+
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_FLC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h
new file mode 100644
index 000000000..8a8122d8c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h
@@ -0,0 +1,477 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file gpio_regs.h
+ * @addtogroup gpio GPIO
+ * @{
+ */
+
+/* Offset Register Description
+ ============= ========================================== */
+typedef struct {
+ __I uint32_t rsv000[16]; /* 0x0000-0x003C */
+
+ __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */
+ __I uint32_t rsv060[8]; /* 0x0060-0x007C */
+
+ __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */
+ __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */
+
+ __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */
+ __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */
+
+ __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */
+ __I uint32_t rsv120[8]; /* 0x0120-0x013C */
+
+ __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */
+ __I uint32_t rsv160[8]; /* 0x0160-0x017C */
+
+ __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */
+ __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */
+
+ __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */
+ __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */
+
+ __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */
+ __I uint32_t rsv220[8]; /* 0x0220-0x023C */
+
+ __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */
+} mxc_gpio_regs_t;
+
+/*
+ Register offsets for module GPIO.
+*/
+#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
+#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
+#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
+#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
+#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
+#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
+#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
+#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL)
+#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
+#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
+#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
+#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
+#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
+#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
+#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
+#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
+#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
+#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
+#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
+#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
+#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL)
+
+
+/*
+ Field positions and masks for module GPIO.
+*/
+#define MXC_F_GPIO_FREE_PIN0_POS 0
+#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_F_GPIO_FREE_PIN1_POS 1
+#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_F_GPIO_FREE_PIN2_POS 2
+#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_F_GPIO_FREE_PIN3_POS 3
+#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_F_GPIO_FREE_PIN4_POS 4
+#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_F_GPIO_FREE_PIN5_POS 5
+#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_F_GPIO_FREE_PIN6_POS 6
+#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_F_GPIO_FREE_PIN7_POS 7
+#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
+#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
+#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
+#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
+#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
+#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
+#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
+#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
+#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0
+#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4
+#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8
+#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12
+#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16
+#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20
+#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24
+#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28
+#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
+
+#define MXC_F_GPIO_IN_MODE_PIN0_POS 0
+#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
+#define MXC_F_GPIO_IN_MODE_PIN1_POS 4
+#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
+#define MXC_F_GPIO_IN_MODE_PIN2_POS 8
+#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
+#define MXC_F_GPIO_IN_MODE_PIN3_POS 12
+#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
+#define MXC_F_GPIO_IN_MODE_PIN4_POS 16
+#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
+#define MXC_F_GPIO_IN_MODE_PIN5_POS 20
+#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
+#define MXC_F_GPIO_IN_MODE_PIN6_POS 24
+#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
+#define MXC_F_GPIO_IN_MODE_PIN7_POS 28
+#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_IN_VAL_PIN0_POS 0
+#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
+#define MXC_F_GPIO_IN_VAL_PIN1_POS 1
+#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
+#define MXC_F_GPIO_IN_VAL_PIN2_POS 2
+#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
+#define MXC_F_GPIO_IN_VAL_PIN3_POS 3
+#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
+#define MXC_F_GPIO_IN_VAL_PIN4_POS 4
+#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
+#define MXC_F_GPIO_IN_VAL_PIN5_POS 5
+#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
+#define MXC_F_GPIO_IN_VAL_PIN6_POS 6
+#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
+#define MXC_F_GPIO_IN_VAL_PIN7_POS 7
+#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_INT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
+#define MXC_F_GPIO_INT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
+#define MXC_F_GPIO_INT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
+#define MXC_F_GPIO_INT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
+#define MXC_F_GPIO_INT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
+#define MXC_F_GPIO_INT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
+#define MXC_F_GPIO_INT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
+#define MXC_F_GPIO_INT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_INTFL_PIN0_POS 0
+#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
+#define MXC_F_GPIO_INTFL_PIN1_POS 1
+#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
+#define MXC_F_GPIO_INTFL_PIN2_POS 2
+#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
+#define MXC_F_GPIO_INTFL_PIN3_POS 3
+#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
+#define MXC_F_GPIO_INTFL_PIN4_POS 4
+#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
+#define MXC_F_GPIO_INTFL_PIN5_POS 5
+#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
+#define MXC_F_GPIO_INTFL_PIN6_POS 6
+#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
+#define MXC_F_GPIO_INTFL_PIN7_POS 7
+#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
+
+#define MXC_F_GPIO_INTEN_PIN0_POS 0
+#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
+#define MXC_F_GPIO_INTEN_PIN1_POS 1
+#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
+#define MXC_F_GPIO_INTEN_PIN2_POS 2
+#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
+#define MXC_F_GPIO_INTEN_PIN3_POS 3
+#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
+#define MXC_F_GPIO_INTEN_PIN4_POS 4
+#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
+#define MXC_F_GPIO_INTEN_PIN5_POS 5
+#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
+#define MXC_F_GPIO_INTEN_PIN6_POS 6
+#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
+#define MXC_F_GPIO_INTEN_PIN7_POS 7
+#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
+
+
+/*
+ Field values and shifted values for module GPIO.
+*/
+#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
+
+#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
+
+#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
+
+#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
+
+#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
+
+#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
+
+#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
+
+#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
+#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
+
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_GPIO_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h
new file mode 100644
index 000000000..173d3107a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h
@@ -0,0 +1,192 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_I2CM_REGS_H_
+#define _MXC_I2CM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file i2cm_regs.h
+ * @addtogroup i2cm I2CM
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */
+ __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */
+ __I uint32_t rsv0008; /* 0x0008 */
+ __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */
+ __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */
+ __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */
+ __IO uint32_t intfl; /* 0x0018 Interrupt Flags */
+ __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */
+ __I uint32_t rsv0020[2]; /* 0x0020 */
+ __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */
+} mxc_i2cm_regs_t;
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */
+ __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */
+} mxc_i2cm_fifo_regs_t;
+
+/*
+ Register offsets for module I2CM.
+*/
+#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL)
+#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
+#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
+#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
+#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
+#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
+#define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL)
+
+#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module I2CM.
+*/
+#define MXC_S_I2CM_TRANS_TAG_START 0x000
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
+#define MXC_S_I2CM_TRANS_TAG_STOP 0x700
+#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
+#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
+
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
+
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
+
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
+
+#define MXC_F_I2CM_TRANS_TX_START_POS 0
+#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
+#define MXC_F_I2CM_TRANS_TX_DONE_POS 2
+#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
+#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
+#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
+
+#define MXC_F_I2CM_INTFL_TX_DONE_POS 0
+#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
+#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
+#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_INTEN_TX_DONE_POS 0
+#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
+#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
+#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
+#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
+#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
+#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
+#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h
new file mode 100644
index 000000000..c8407a843
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file icc_regs.h
+ * @addtogroup icc ICC
+ * @{
+ */
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t id; /* 0x0000 Device ID Register */
+ __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */
+ __I uint32_t rsv0008[62]; /* 0x0008 */
+ __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */
+ __I uint32_t rsv0104[383]; /* 0x0104 */
+ __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */
+} mxc_icc_regs_t;
+
+/*
+ Register offsets for module ICC.
+*/
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL)
+
+/*
+ Field positions and masks for module ICC.
+*/
+#define MXC_F_ICC_ID_RTL_VERSION_POS 0
+#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
+#define MXC_F_ICC_ID_PART_NUM_POS 6
+#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
+#define MXC_F_ICC_ID_CACHE_ID_POS 10
+#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
+
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
+
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0
+#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
+#define MXC_F_ICC_CTRL_STAT_READY_POS 16
+#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_ICC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h
new file mode 100644
index 000000000..930a18159
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h
@@ -0,0 +1,508 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file ioman_regs.h
+ * @addtogroup ioman IO MUX Manager
+ * @{
+ */
+
+typedef enum {
+ /** Pin Mapping 'A' */
+ MXC_E_IOMAN_MAPPING_A = 0,
+ /** Pin Mapping 'B' */
+ MXC_E_IOMAN_MAPPING_B,
+ /** Pin Mapping 'C' */
+ MXC_E_IOMAN_MAPPING_C,
+ /** Pin Mapping 'D' */
+ MXC_E_IOMAN_MAPPING_D,
+ /** Pin Mapping 'E' */
+ MXC_E_IOMAN_MAPPING_E,
+ /** Pin Mapping 'F' */
+ MXC_E_IOMAN_MAPPING_F,
+ /** Pin Mapping 'G' */
+ MXC_E_IOMAN_MAPPING_G,
+ /** Pin Mapping 'H' */
+ MXC_E_IOMAN_MAPPING_H,
+} ioman_mapping_t;
+
+/* Offset Register Description
+ ====== ========================================== */
+typedef struct {
+ __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
+ __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
+ __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
+ __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
+ __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
+ __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
+ __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
+ __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
+ __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
+ __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
+ __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
+ __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
+ __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
+ __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
+ __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
+ __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
+ __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
+ __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
+ __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
+ __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
+ __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
+ __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
+ __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
+ __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
+ __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
+ __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
+ __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
+ __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
+ __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
+ __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
+ __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
+ __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
+ __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
+ __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
+ __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
+ __IO uint32_t padx_control; /* 0x008C PADX Control */
+} mxc_ioman_regs_t;
+
+
+/*
+ Register offsets for module IOMAN.
+*/
+#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
+#define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
+#define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
+
+
+/*
+ Field positions and masks for module IOMAN.
+*/
+#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
+#define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
+#define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
+#define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
+#define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
+#define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
+#define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
+#define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
+#define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
+#define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
+#define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
+#define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
+#define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
+#define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
+#define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
+#define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
+#define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
+#define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
+#define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
+#define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
+#define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
+#define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
+#define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
+#define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
+#define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
+#define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
+#define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
+#define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
+#define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
+#define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
+#define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
+#define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
+#define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_SPI_MAPPING_POS 0
+#define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
+#define MXC_F_IOMAN_SPI_CORE_IO_POS 4
+#define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
+#define MXC_F_IOMAN_SPI_SS0_IO_POS 8
+#define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
+#define MXC_F_IOMAN_SPI_SS1_IO_POS 9
+#define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
+#define MXC_F_IOMAN_SPI_SS2_IO_POS 10
+#define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
+#define MXC_F_IOMAN_SPI_SS3_IO_POS 11
+#define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
+#define MXC_F_IOMAN_SPI_SS4_IO_POS 12
+#define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
+#define MXC_F_IOMAN_SPI_SR0_IO_POS 16
+#define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
+#define MXC_F_IOMAN_SPI_SR1_IO_POS 17
+#define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
+#define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
+#define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
+#define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART_MAPPING_POS 0
+#define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
+#define MXC_F_IOMAN_UART_CORE_IO_POS 4
+#define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
+#define MXC_F_IOMAN_UART_CTS_IO_POS 5
+#define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
+#define MXC_F_IOMAN_UART_RTS_IO_POS 6
+#define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
+
+#define MXC_F_IOMAN_I2CM_MAPPING_POS 0
+#define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
+#define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
+#define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
+
+#define MXC_F_IOMAN_I2CS_MAPPING_POS 0
+#define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
+#define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
+#define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
+
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
+
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_IOMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h
new file mode 100644
index 000000000..db8223fdf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h
@@ -0,0 +1,70 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_LCD_REGS_H
+#define _MXC_LCD_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file lcd_regs.h
+ * @addtogroup lcd LCD
+ * @{
+ */
+
+#define MXC_LCD_ADDRESS_SEGS 21
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t lcfg; /* 0x0000 */
+ __IO uint32_t lcra; /* 0x0004 */
+ __IO uint32_t lpcf; /* 0x0008 LCD Port Configuration Register */
+ __IO uint32_t lcaddr; /* 0x000C */
+ __IO uint32_t lcdata; /* 0x0010 LCD Memory Data Read / Write */
+ __IO uint32_t lpwrctrl; /* 0x0014 LCD Power Control */
+} mxc_lcd_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_LCD_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h
new file mode 100644
index 000000000..e8c80c712
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h
@@ -0,0 +1,124 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_MAA_REGS_H_
+#define _MXC_MAA_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file maa_regs.h
+ * @addtogroup maa MAA
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ========================================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */
+ __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */
+} mxc_maa_regs_t;
+
+/* Offset Register Description
+ ====== ========================================================== */
+typedef struct {
+ __IO uint32_t seg0[16]; /* 0x0000 [64 bytes] MAA Memory Segment 0 */
+ __IO uint32_t seg1[16]; /* 0x0040 [64 bytes] MAA Memory Segment 1 */
+ __IO uint32_t seg2[16]; /* 0x0080 [64 bytes] MAA Memory Segment 2 */
+ __IO uint32_t seg3[16]; /* 0x00C0 [64 bytes] MAA Memory Segment 3 */
+ __IO uint32_t seg4[16]; /* 0x0100 [64 bytes] MAA Memory Segment 4 */
+ __IO uint32_t seg5[16]; /* 0x0140 [64 bytes] MAA Memory Segment 5 */
+} mxc_maa_mem_regs_t;
+
+/*
+ Register offsets for module MAA.
+*/
+#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL)
+#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000040UL)
+#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000080UL)
+#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x000000C0UL)
+#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000100UL)
+#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000140UL)
+
+/*
+ Field positions and masks for module MAA.
+*/
+#define MXC_F_MAA_CTRL_START_POS 0
+#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS))
+#define MXC_F_MAA_CTRL_OPSEL_POS 1
+#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS))
+#define MXC_F_MAA_CTRL_OCALC_POS 4
+#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS))
+#define MXC_F_MAA_CTRL_INTEN_POS 5
+#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS))
+#define MXC_F_MAA_CTRL_IF_DONE_POS 6
+#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS))
+#define MXC_F_MAA_CTRL_IF_ERROR_POS 7
+#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS))
+#define MXC_F_MAA_CTRL_OFS_A_POS 8
+#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS))
+#define MXC_F_MAA_CTRL_OFS_B_POS 10
+#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS))
+#define MXC_F_MAA_CTRL_OFS_EXP_POS 12
+#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS))
+#define MXC_F_MAA_CTRL_OFS_MOD_POS 14
+#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS))
+#define MXC_F_MAA_CTRL_SEG_A_POS 16
+#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS))
+#define MXC_F_MAA_CTRL_SEG_B_POS 20
+#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS))
+#define MXC_F_MAA_CTRL_SEG_RES_POS 24
+#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS))
+#define MXC_F_MAA_CTRL_SEG_TMP_POS 28
+#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS))
+
+#define MXC_F_MAA_MAWS_MODLEN_POS 0
+#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS))
+#define MXC_F_MAA_MAWS_BYTESWAP_POS 16
+#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_MAA_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h
new file mode 100644
index 000000000..5b50a7aab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h
@@ -0,0 +1,666 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX32600_H_
+#define _MAX32600_H_
+
+#include <stdint.h>
+
+typedef enum IRQn_Type {
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+ /* Externals interrupts */
+ UART0_IRQn = 0, /* 16:01 UART0 */
+ UART1_IRQn, /* 17: 2 UART1 */
+ I2CM0_IRQn, /* 18: 3 I2C Master 0 */
+ I2CS_IRQn, /* 19: 4 I2C Slave */
+ USB_IRQn, /* 20: 5 USB */
+ PMU_IRQn, /* 21: 6 DMA */
+ AFE_IRQn, /* 22: 7 AFE */
+ MAA_IRQn, /* 23: 8 MAA */
+ AES_IRQn, /* 24: 9 AES */
+ SPI0_IRQn, /* 25:10 SPI0 */
+ SPI1_IRQn, /* 26:11 SPI1 */
+ SPI2_IRQn, /* 27:12 SPI2 */
+ TMR0_IRQn, /* 28:13 Timer32-0 */
+ TMR1_IRQn, /* 29:14 Timer32-1 */
+ TMR2_IRQn, /* 30:15 Timer32-1 */
+ TMR3_IRQn, /* 31:16 Timer32-2 */
+ RSVD0_IRQn, /* 32:17 RSVD */
+ RSVD1_IRQn, /* 33:18 RSVD */
+ DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
+ DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
+ DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
+ DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
+ ADC_IRQn, /* 38:23 ADC */
+ FLC_IRQn, /* 39:24 Flash Controller */
+ PWRMAN_IRQn, /* 40:25 PWRMAN */
+ CLKMAN_IRQn, /* 41:26 CLKMAN */
+ RTC0_IRQn, /* 42:27 RTC INT0 */
+ RTC1_IRQn, /* 43:28 RTC INT1 */
+ RTC2_IRQn, /* 44:29 RTC INT2 */
+ RTC3_IRQn, /* 45:30 RTC INT3 */
+ WDT0_IRQn, /* 46:31 WATCHDOG0 */
+ WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
+ WDT1_IRQn, /* 48:33 WATCHDOG1 */
+ WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
+ GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
+ GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
+ GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
+ GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
+ GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
+ GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
+ GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
+ GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
+ TMR16_0_IRQn, /* 58:43 Timer16-s0 */
+ TMR16_1_IRQn, /* 59:44 Timer16-s1 */
+ TMR16_2_IRQn, /* 60:45 Timer16-s2 */
+ TMR16_3_IRQn, /* 61:46 Timer16-s3 */
+ I2CM1_IRQn, /* 62:47 I2C Master 1 */
+ MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+
+#include <core_cm3.h> /* Processor and core peripherals */
+#include "system_max32600.h" /* System Header */
+
+/* ================================================================================ */
+/* ================== Device Specific Memory Section ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE 0x00000000UL
+#define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
+#define MXC_FLASH_MEM_SIZE 0x00040000UL
+#define MXC_SYS_MEM_BASE 0x20000000UL
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/*******************************************************************************/
+/* General Purpose I/O Ports (GPIO) */
+
+#define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
+
+#define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
+
+
+/*******************************************************************************/
+/* Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES (13)
+
+#define MXC_BASE_PTG ((uint32_t)0x40001000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT ((uint32_t)0x40001008UL)
+#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
+#define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8 ((uint32_t)0x40001048UL)
+#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9 ((uint32_t)0x40001050UL)
+#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10 ((uint32_t)0x40001058UL)
+#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11 ((uint32_t)0x40001060UL)
+#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
+
+/* PT12, PT13, PT14 are not used */
+
+/*******************************************************************************/
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40010000UL)
+#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
+
+#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40011000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40011400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+
+#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+
+/*******************************************************************************/
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40011800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+
+#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/* 32-Bit PWM Timer/Counter */
+
+#define MXC_CFG_TMR_INSTANCES (4)
+
+#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
+#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
+#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
+
+#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
+#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
+#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
+
+#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
+#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
+#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
+
+#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
+#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
+#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
+
+
+#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : \
+ (i) == 4 ? TMR16_0_IRQn : \
+ (i) == 5 ? TMR16_1_IRQn : \
+ (i) == 6 ? TMR16_2_IRQn : \
+ (i) == 7 ? TMR16_3_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : 0)
+
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : 0)
+/*******************************************************************************/
+/* Watchdog Timer */
+
+#define MXC_CFG_WDT_INSTANCES (2)
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
+#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+
+#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
+#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+
+/*******************************************************************************/
+/* SPI Interface */
+
+#define MXC_CFG_SPI_INSTANCES (3)
+#define MXC_CFG_SPI_FIFO_DEPTH (16)
+
+#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
+#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
+
+#define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
+#define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
+#define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
+#define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
+
+#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
+#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
+
+#define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
+#define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
+#define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
+#define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
+
+#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
+#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
+
+#define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
+#define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
+#define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
+#define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
+
+
+#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
+ (i) == 1 ? SPI1_IRQn : \
+ (i) == 2 ? SPI2_IRQn : 0)
+
+#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
+ (i) == 1 ? MXC_BASE_SPI1 : \
+ (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
+ (i) == 1 ? MXC_SPI1 : \
+ (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
+ (i) == 1 ? MXC_SPI1_RXFIFO : \
+ (i) == 2 ? MXC_SPI2_RXFIFO : 0)
+
+#define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
+ (i) == 1 ? MXC_SPI1_TXFIFO : \
+ (i) == 2 ? MXC_SPI2_TXFIFO : 0)
+
+#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
+#define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
+
+
+/*******************************************************************************/
+/* UART Interface */
+
+#define MXC_CFG_UART_INSTANCES (2)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
+#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+
+#define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
+#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
+
+
+#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
+#define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
+
+
+/*******************************************************************************/
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (2)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
+#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
+#define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
+
+#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
+#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
+#define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
+
+#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
+
+#define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
+
+#define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
+#define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
+
+
+/*******************************************************************************/
+/* I2C Slave Interface */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+
+#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
+#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
+#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
+
+#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
+#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
+
+
+
+/*******************************************************************************/
+/* DACs */
+
+#define MXC_CFG_DAC_INSTANCES (4)
+#define MXC_CFG_DAC_FIFO_DEPTH (32)
+
+#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
+#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
+#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
+#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
+#define MXC_DAC0_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
+#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
+#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
+#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
+#define MXC_DAC1_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
+#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
+#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
+#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
+#define MXC_DAC2_WIDTH ((uint8_t)(1))
+
+#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
+#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
+#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
+#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
+#define MXC_DAC3_WIDTH ((uint8_t)(1))
+
+
+#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
+ (i) == 1 ? DAC1_IRQn : \
+ (i) == 2 ? DAC2_IRQn : \
+ (i) == 3 ? DAC3_IRQn : 0)
+
+
+#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
+ i == 1 ? MXC_BASE_DAC1 : \
+ i == 2 ? MXC_BASE_DAC2 : \
+ i == 3 ? MXC_BASE_DAC3 : 0)
+
+#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
+ i == 1 ? MXC_BASE_DAC1_FIFO : \
+ i == 2 ? MXC_BASE_DAC2_FIFO : \
+ i == 3 ? MXC_BASE_DAC3_FIFO : 0)
+
+#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
+ i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
+ i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
+ i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
+
+#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
+ i == 1 ? MXC_DAC1 : \
+ i == 2 ? MXC_DAC2 : \
+ i == 3 ? MXC_DAC3 : 0)
+
+#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
+ i == 1 ? MXC_DAC1_WIDTH : \
+ i == 2 ? MXC_DAC2_WIDTH : \
+ i == 3 ? MXC_DAC3_WIDTH : 0)
+
+
+/*******************************************************************************/
+/* Analog Front End */
+
+#define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
+#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
+
+
+
+/*******************************************************************************/
+/* ADC */
+
+#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
+
+#define MXC_BASE_ADC ((uint32_t)0x40054000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
+#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
+
+#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
+#define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
+
+
+
+/*******************************************************************************/
+/* LCD */
+#define MXC_BASE_LCD ((uint32_t)0x40060000)
+#define MXC_LCD ((mxc_lcd_regs_t *)MXC_BASE_LCD)
+
+/*******************************************************************************/
+/* Peripheral Management Unit (PMU) - formerly DMA Controller */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
+#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
+/*******************************************************************************/
+
+typedef enum {
+ PMU_IRQ_DAC0_FIFO_AE,
+ PMU_IRQ_DAC1_FIFO_AE,
+ PMU_IRQ_DAC2_FIFO_AE,
+ PMU_IRQ_DAC3_FIFO_AE,
+ PMU_IRQ_DAC0_DONE,
+ PMU_IRQ_DAC1_DONE,
+ PMU_IRQ_DAC2_DONE,
+ PMU_IRQ_DAC3_DONE,
+ PMU_IRQ_ADC_FIFO_AF,
+ PMU_IRQ_ADC_DONE,
+ PMU_IRQ_I2C_MST0_DONE,
+ PMU_IRQ_I2C_MST1_DONE,
+ PMU_IRQ_SPI0_RSLTS_DONE,
+ PMU_IRQ_SPI1_RSLTS_DONE,
+ PMU_IRQ_SPI2_RSLTS_DONE,
+ PMU_IRQ_MAA_DONE,
+ PMU_IRQ_SPI0_TX_FIFO_AE,
+ PMU_IRQ_SPI0_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI1_TX_FIFO_AE,
+ PMU_IRQ_SPI1_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI2_TX_FIFO_AE,
+ PMU_IRQ_SPI3_RSLTS_FIFO_AF,
+ PMU_IRQ_I2C_MST0_TRANS_FIFO,
+ PMU_IRQ_I2C_MST0_RSLT_FIFO,
+ PMU_IRQ_I2C_MST1_TRANS_FIFO,
+ PMU_IRQ_I2C_MST2_RSLT_FIFO,
+ PMU_IRQ_I2C_SLV_TRANS_FIFO,
+ PMU_IRQ_I2C_SLV_RSLT_FIFO,
+ PMU_IRQ_UART0_TX_FIFO,
+ PMU_IRQ_UART0_RX_FIFO,
+ PMU_IRQ_UART1_TX_FIFO,
+ PMU_IRQ_UART1_RX_FIFO,
+ PMU_IRQ_SPI0_EXCP,
+ PMU_IRQ_SPI1_EXCP,
+ PMU_IRQ_SPI2_EXCP,
+ PMU_IRQ_RSVD0,
+ PMU_IRQ_I2C_MST0_EXCP,
+ PMU_IRQ_I2C_MST1_EXCP,
+ PMU_IRQ_I2C_SLV_EXCP,
+ PMU_IRQ_RSVD1,
+ PMU_IRQ_GPIO0,
+ PMU_IRQ_GPIO1,
+ PMU_IRQ_GPIO2,
+ PMU_IRQ_GPIO3,
+ PMU_IRQ_GPIO4,
+ PMU_IRQ_GPIO5,
+ PMU_IRQ_GPIO6,
+ PMU_IRQ_GPIO7,
+ PMU_IRQ_GPIO8,
+ PMU_IRQ_AFE_COMP_NMI,
+ PMU_IRQ_AES_ENGINE,
+} pmu_int_mask_t;
+
+/*******************************************************************************/
+/* USB */
+
+#define MXC_BASE_USB ((uint32_t)0x4010C000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+/*******************************************************************************/
+/* Instruction Cache Controller */
+
+#define MXC_BASE_ICC ((uint32_t)0x40080000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+/* System Manager */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
+
+/*******************************************************************************/
+/* Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+/*******************************************************************************/
+/* Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+/*******************************************************************************/
+/* I/O Manager */
+
+#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+/*******************************************************************************/
+/* RTC: Timer/Alarms */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+
+#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
+ i == 1 ? RTC1_IRQn : \
+ i == 2 ? RTC2_IRQn : \
+ i == 3 ? RTC3_IRQn : 0)
+
+#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+/*******************************************************************************/
+/* RTC: Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+/*******************************************************************************/
+/* Trim Shadow Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
+#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
+
+/*******************************************************************************/
+/* Flash Memory Controller / Security */
+
+#define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
+#define MXC_FLC_PAGE_SIZE_SHIFT 11
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+/*******************************************************************************/
+
+#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
+#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
+#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+/*******************************************************************************/
+
+#endif /* _MAX32600_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h
new file mode 100644
index 000000000..e36b9b04e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h
@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PMU_REGS_H_
+#define _MXC_PMU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pmu_regs.h
+ * @addtogroup pmu PMU
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ======================================================== */
+typedef struct {
+ __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */
+ __IO uint32_t cfg; /* 0x0004 Channel Configuration */
+ __IO uint32_t loop; /* 0x0008 Channel Loop Counters */
+ __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */
+ __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */
+ __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */
+ __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */
+ __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */
+} mxc_pmu_regs_t;
+
+/*
+ Register offsets for module PMU.
+*/
+#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
+#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
+#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL)
+#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL)
+#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL)
+#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL)
+#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL)
+
+/*
+ Field positions and masks for module PMU.
+*/
+#define MXC_F_PMU_CFG_ENABLE_POS 0
+#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
+#define MXC_F_PMU_CFG_LL_STOPPED_POS 2
+#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
+#define MXC_F_PMU_CFG_MANUAL_POS 3
+#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
+#define MXC_F_PMU_CFG_BUS_ERROR_POS 4
+#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
+#define MXC_F_PMU_CFG_TO_STAT_POS 6
+#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
+#define MXC_F_PMU_CFG_TO_SEL_POS 11
+#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
+#define MXC_F_PMU_CFG_PS_SEL_POS 14
+#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
+#define MXC_F_PMU_CFG_INTERRUPT_POS 16
+#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
+#define MXC_F_PMU_CFG_INT_EN_POS 17
+#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
+#define MXC_F_PMU_CFG_BURST_SIZE_POS 24
+#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
+
+#define MXC_F_PMU_LOOP_COUNTER_0_POS 0
+#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
+#define MXC_F_PMU_LOOP_COUNTER_1_POS 16
+#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PMU_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h
new file mode 100644
index 000000000..53936e390
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h
@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PT_REGS_H_
+#define _MXC_PT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pt_regs.h
+ * @addtogroup pt PT
+ * @{
+ */
+
+typedef struct {
+ __IO uint32_t ctrl;
+ __IO uint32_t resync;
+} mxc_ptg_regs_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */
+ __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */
+} mxc_pt_regs_t;
+
+/*
+ Register offsets for module PT.
+*/
+#define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL)
+#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL)
+#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL)
+
+
+/*
+ Field positions and masks for module PT.
+*/
+#define MXC_F_PT_CTRL_ENABLE_ALL_POS 1
+#define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS))
+
+#define MXC_F_PT_RESYNC_PT0_POS 0
+#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS))
+#define MXC_F_PT_RESYNC_PT1_POS 1
+#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS))
+#define MXC_F_PT_RESYNC_PT2_POS 2
+#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS))
+#define MXC_F_PT_RESYNC_PT3_POS 3
+#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS))
+#define MXC_F_PT_RESYNC_PT4_POS 4
+#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS))
+#define MXC_F_PT_RESYNC_PT5_POS 5
+#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS))
+#define MXC_F_PT_RESYNC_PT6_POS 6
+#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS))
+#define MXC_F_PT_RESYNC_PT7_POS 7
+#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS))
+
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS))
+#define MXC_F_PT_RATE_LENGTH_MODE_POS 27
+#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+/*
+ Field values and shifted values for module PT.
+*/
+#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL))
+
+#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PT_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h
new file mode 100644
index 000000000..cc717dd65
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h
@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pwrman_regs.h
+ * @addtogroup pwrman PWRMAN
+ * @{
+ */
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+ /** WUD Mode for Selected PAD = Clear/Activate */
+ MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+ /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+ MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+ /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+ MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+ /** WUD Mode for Selected PAD = No pad state change */
+ MXC_E_PWRMAN_PAD_MODE_NONE
+} mxc_pwrman_pad_mode_t;
+
+/* Offset Register Description
+ ====== =========================================== */
+typedef struct {
+ __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
+ __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
+ __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
+ __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
+ __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
+ __I uint32_t rsv001C[5]; /* 0x001C */
+
+ __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */
+ __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */
+ __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */
+ __IO uint32_t base_part_num; /* 0x003C Base Part Number */
+ __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
+ __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
+ __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
+} mxc_pwrman_regs_t;
+
+/*
+ Register offsets for module PWRMAN.
+*/
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
+
+/*
+ Field positions and masks for module PWRMAN.
+*/
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h
new file mode 100644
index 000000000..506b11bda
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h
@@ -0,0 +1,299 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRSEQ_REGS_H
+#define _MXC_PWRSEQ_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pwrseq_regs.h
+ * @addtogroup pwrseq PWRSEQ
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================= */
+typedef struct {
+ __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
+ __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
+ __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
+ __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
+ __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
+ __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
+ __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
+ __I uint32_t rsv001C; /* 0x001C */
+ __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
+ __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
+} mxc_pwrseq_regs_t;
+
+
+/*
+ Register offsets for module PWRSEQ.
+*/
+#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
+
+
+/*
+ Field positions and masks for module PWRSEQ.
+*/
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
+#define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
+#define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
+#define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRSEQ_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h
new file mode 100644
index 000000000..3c947b028
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h
@@ -0,0 +1,246 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_RTC_REGS_H
+#define _MXC_RTC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file rtc_regs.h
+ * @addtogroup rtc RTCTMR
+ * @{
+ */
+
+/**
+ * @brief Defines clock divider for 4096Hz input clock.
+ */
+typedef enum {
+ /** (4kHz) divide input clock by 2^0 = 1 */
+ MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
+ /** (2kHz) divide input clock by 2^1 = 2 */
+ MXC_E_RTC_PRESCALE_DIV_2_1,
+ /** (1kHz) divide input clock by 2^2 = 4 */
+ MXC_E_RTC_PRESCALE_DIV_2_2,
+ /** (512Hz) divide input clock by 2^3 = 8 */
+ MXC_E_RTC_PRESCALE_DIV_2_3,
+ /** (256Hz) divide input clock by 2^4 = 16 */
+ MXC_E_RTC_PRESCALE_DIV_2_4,
+ /** (128Hz) divide input clock by 2^5 = 32 */
+ MXC_E_RTC_PRESCALE_DIV_2_5,
+ /** (64Hz) divide input clock by 2^6 = 64 */
+ MXC_E_RTC_PRESCALE_DIV_2_6,
+ /** (32Hz) divide input clock by 2^7 = 128 */
+ MXC_E_RTC_PRESCALE_DIV_2_7,
+ /** (16Hz) divide input clock by 2^8 = 256 */
+ MXC_E_RTC_PRESCALE_DIV_2_8,
+ /** (8Hz) divide input clock by 2^9 = 512 */
+ MXC_E_RTC_PRESCALE_DIV_2_9,
+ /** (4Hz) divide input clock by 2^10 = 1024 */
+ MXC_E_RTC_PRESCALE_DIV_2_10,
+ /** (2Hz) divide input clock by 2^11 = 2048 */
+ MXC_E_RTC_PRESCALE_DIV_2_11,
+ /** (1Hz) divide input clock by 2^12 = 4096 */
+ MXC_E_RTC_PRESCALE_DIV_2_12,
+} mxc_rtc_prescale_t;
+
+/* Offset Register Description
+ ====== ========================================= */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
+ __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
+ __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
+ __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
+ __I uint32_t rsv0014; /* 0x0014 */
+ __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
+ __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
+ __I uint32_t rsv0020; /* 0x0020 */
+ __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
+ __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
+ __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
+} mxc_rtctmr_regs_t;
+
+/*
+ Register offsets for module RTCTMR.
+*/
+#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
+#define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
+#define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
+#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
+#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
+
+/*
+ Field positions and masks for module RTCTMR.
+*/
+#define MXC_F_RTC_CTRL_ENABLE_POS 0
+#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
+#define MXC_F_RTC_CTRL_CLEAR_POS 1
+#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
+#define MXC_F_RTC_CTRL_PENDING_POS 2
+#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
+#define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
+#define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
+#define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
+#define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
+
+#define MXC_F_RTC_FLAGS_COMP0_POS 0
+#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
+#define MXC_F_RTC_FLAGS_COMP1_POS 1
+#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
+#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
+#define MXC_F_RTC_FLAGS_TRIM_POS 4
+#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
+
+#define MXC_F_RTC_INTEN_COMP0_POS 0
+#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
+#define MXC_F_RTC_INTEN_COMP1_POS 1
+#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
+#define MXC_F_RTC_INTEN_OVERFLOW_POS 3
+#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
+#define MXC_F_RTC_INTEN_TRIM_POS 4
+#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
+
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
+
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
+
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
+
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
+
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
+
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
+#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
+
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
+
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
+
+/* Offset Register Description
+ ====== ===================================================================== */
+typedef struct {
+ __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
+ __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
+ __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
+ __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
+} mxc_rtccfg_regs_t;
+
+/*
+ Register offsets for module RTCCFG.
+*/
+#define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_RTC_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h
new file mode 100644
index 000000000..645178ca3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h
@@ -0,0 +1,215 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_SPI_REGS_H
+#define _MXC_SPI_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file spi_regs.h
+ * @addtogroup spi SPI
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ============================================ */
+typedef struct {
+ __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
+ __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
+ __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
+ __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
+ __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
+ __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
+ __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
+ __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
+} mxc_spi_regs_t;
+
+/**
+ * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+ union {
+ __O uint8_t txfifo_8;
+ __O uint16_t txfifo_16;
+ __O uint32_t txfifo_32;
+ };
+} mxc_spi_txfifo_regs_t;
+
+/**
+ * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+ union {
+ __I uint8_t rxfifo_8;
+ __I uint16_t rxfifo_16;
+ __I uint32_t rxfifo_32;
+ };
+} mxc_spi_rxfifo_regs_t;
+
+/*
+ Register offsets for module SPI.
+*/
+#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
+#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
+#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
+#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
+
+#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module SPI.
+*/
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
+
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
+
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
+
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_INTFL_TX_STALLED_POS 0
+#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
+#define MXC_F_SPI_INTFL_RX_STALLED_POS 1
+#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
+#define MXC_F_SPI_INTFL_TX_READY_POS 2
+#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
+#define MXC_F_SPI_INTFL_RX_DONE_POS 3
+#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
+#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
+#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
+#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_INTEN_TX_STALLED_POS 0
+#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
+#define MXC_F_SPI_INTEN_RX_STALLED_POS 1
+#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
+#define MXC_F_SPI_INTEN_TX_READY_POS 2
+#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
+#define MXC_F_SPI_INTEN_RX_DONE_POS 3
+#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
+#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
+#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
+#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_FIFO_DIR_POS 0
+#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
+#define MXC_F_SPI_FIFO_UNIT_POS 2
+#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
+#define MXC_F_SPI_FIFO_SIZE_POS 4
+#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
+#define MXC_F_SPI_FIFO_WIDTH_POS 9
+#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
+#define MXC_F_SPI_FIFO_ALT_POS 11
+#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
+#define MXC_F_SPI_FIFO_FLOW_POS 12
+#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
+#define MXC_F_SPI_FIFO_DASS_POS 13
+#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_SPI_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c
new file mode 100644
index 000000000..5357f31b3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c
@@ -0,0 +1,144 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "max32600.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "ioman_regs.h"
+#include "trim_regs.h"
+#include "flc_regs.h"
+#include "pwrseq_regs.h"
+#include "dac_regs.h"
+#include "icc_regs.h"
+
+/* Application developer should override where necessary with different external HFX source */
+#ifndef __SYSTEM_HFX
+#define __SYSTEM_HFX 8000000
+#endif
+
+uint32_t SystemCoreClock = 24000000;
+
+void SystemCoreClockUpdate(void)
+{
+ switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
+ SystemCoreClock = 3000000;
+ break;
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
+ SystemCoreClock = 24000000;
+ break;
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
+ SystemCoreClock = __SYSTEM_HFX;
+ break;
+ }
+
+ uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
+ if (shift) {
+ SystemCoreClock = SystemCoreClock >> (shift - 1);
+ }
+}
+
+/* power seq registers */
+static void set_pwr_regs(void)
+{
+ uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff;
+ uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff;
+ dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
+ dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
+ MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
+ MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
+ MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
+ MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
+ MXC_DAC2->reg = dac2trim;
+ MXC_DAC3->reg = dac3trim;
+}
+
+void ICC_Enable(void)
+{
+ /* clock gater must be 'on' not 'dynamic' for cache control */
+ uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
+ temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+ temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = temp;
+
+
+ /* invalidate, wait, enable */
+ MXC_ICC->invdt_all = 0xFFFF;
+ while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+
+ /* clock gater 'dynamic' safe again */
+ temp = MXC_CLKMAN->clk_gate_ctrl0;
+ temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+ temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = temp;
+}
+
+// This function to be implemented by the hal
+extern void low_level_init(void);
+
+void SystemInit(void)
+{
+ set_pwr_regs();
+
+ // enable instruction cache
+ ICC_Enable();
+
+ low_level_init();
+
+ // Clear IO Active
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
+
+ // Set WUD Clear
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
+
+ // Set IO Active
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
+
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
+
+ // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+ SystemCoreClockUpdate();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h
new file mode 100644
index 000000000..9bbd239f1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef SYSTEM_MAX32600_H_
+#define SYSTEM_MAX32600_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit (void);
+
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MAX32600_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h
new file mode 100644
index 000000000..1803814ee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h
@@ -0,0 +1,146 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TMR_REGS_H
+#define _MXC_TMR_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file tmr_regs.h
+ * @addtogroup tmr TMR
+ * @{
+ */
+
+/**
+ * @brief Defines timer modes for 16 and 32-bit timers
+ */
+typedef enum {
+ /** 32-bit or 16-bit timer one-shot mode */
+ MXC_E_TMR_MODE_ONE_SHOT = 0,
+ /** 32-bit or 16-bit timer one-shot mode */
+ MXC_E_TMR_MODE_CONTINUOUS,
+ /** 32-bit timer counter mode */
+ MXC_E_TMR_MODE_COUNTER,
+ /** 32-bit timer pulse width modulation mode */
+ MXC_E_TMR_MODE_PWM,
+ /** 32-bit timer capture mode */
+ MXC_E_TMR_MODE_CAPTURE,
+ /** 32-bit timer compare mode */
+ MXC_E_TMR_MODE_COMPARE,
+ /** 32-bit timer gated mode */
+ MXC_E_TMR_MODE_GATED,
+ /** 32-bit timer measure mode */
+ MXC_E_TMR_MODE_MEASURE
+} mxc_tmr_mode_t;
+
+/* Offset Register Description
+ ====== ============================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
+ __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */
+ __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */
+ __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */
+ __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */
+ __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */
+ __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */
+ __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */
+ __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */
+ __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+
+/*
+ Register offsets for module TMR.
+*/
+#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
+#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
+#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
+#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
+#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
+#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
+#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
+
+/*
+ Field positions and masks for module TMR.
+*/
+#define MXC_F_TMR_CTRL_MODE_POS 0
+#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_F_TMR_CTRL_TMR2X16_POS 3
+#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
+#define MXC_F_TMR_CTRL_PRESCALE_POS 4
+#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_F_TMR_CTRL_POLARITY_POS 8
+#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
+#define MXC_F_TMR_CTRL_ENABLE0_POS 12
+#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
+#define MXC_F_TMR_CTRL_ENABLE1_POS 13
+#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
+
+#define MXC_F_TMR_COUNT16_0_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
+
+#define MXC_F_TMR_COUNT16_1_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
+
+#define MXC_F_TMR_INTFL_TIMER0_POS 0
+#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
+#define MXC_F_TMR_INTFL_TIMER1_POS 1
+#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
+
+#define MXC_F_TMR_INTEN_TIMER0_POS 0
+#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
+#define MXC_F_TMR_INTEN_TIMER1_POS 1
+#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TMR_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h
new file mode 100644
index 000000000..1a0c8f49b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h
@@ -0,0 +1,108 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TPU_REGS_H_
+#define _MXC_TPU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file tpu_regs.h
+ * @addtogroup tpu TPU
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __I uint32_t rsv0000; /* 0x0000 Reserved */
+ __I uint32_t rsv0004; /* 0x0004 Reserved - PUF Control (Deprecated) */
+ __I uint32_t rsv0008; /* 0x0008 Reserved - PUF Output (Deprecated) */
+ __I uint32_t rsv000C[125]; /* 0x000C */
+ __IO uint32_t prng_user_entropy; /* 0x0200 PRNG User Entropy Value */
+ __IO uint32_t prng_rnd_num; /* 0x0204 PRNG Random Number Output */
+} mxc_tpu_regs_t;
+
+/* Offset Register Description
+ ====== ================================================= */
+typedef struct {
+ __IO uint32_t status; /* 0x0000 Dynamic Tamper Sensor Status */
+ __IO uint32_t ctrl0; /* 0x0004 Dynamic Tamper Sensor Control 0 */
+ __IO uint32_t ctrl1; /* 0x0008 Dynamic Tamper Sensor Control 1 */
+ __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 0 */
+} mxc_tpu_tsr_regs_t;
+
+/*
+ Register offsets for module TPU.
+*/
+#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000200UL)
+#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000204UL)
+#define MXC_R_TPU_TSR_OFFS_STATUS ((uint32_t)0x00000000UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL0 ((uint32_t)0x00000004UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL1 ((uint32_t)0x00000008UL)
+#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL)
+#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL)
+#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL)
+#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL)
+
+
+/*
+ Field positions and masks for module TPU.
+*/
+#define MXC_F_TPU_CTRL0_ERR_THR_POS 0
+#define MXC_F_TPU_CTRL0_ERR_THR ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS))
+#define MXC_F_TPU_CTRL0_OUT_FREQ_POS 5
+#define MXC_F_TPU_CTRL0_OUT_FREQ ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS))
+#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS 8
+#define MXC_F_TPU_CTRL0_CLOCK_DIV ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS))
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS 14
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS))
+#define MXC_F_TPU_CTRL0_LOCK_POS 15
+#define MXC_F_TPU_CTRL0_LOCK ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TPU_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h
new file mode 100644
index 000000000..2c6ecac55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h
@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TRIM_REGS_H
+#define _MXC_TRIM_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+ __IO uint32_t trim_reg_00;
+ __IO uint32_t trim_reg_01;
+ __IO uint32_t trim_reg_02;
+ __IO uint32_t trim_reg_03;
+ __IO uint32_t trim_reg_04;
+ __IO uint32_t trim_reg_05;
+ __IO uint32_t trim_reg_06;
+ __IO uint32_t trim_reg_07;
+ __IO uint32_t trim_reg_08;
+ __IO uint32_t trim_reg_09;
+ __IO uint32_t trim_reg_10;
+ __IO uint32_t trim_reg_11;
+ __IO uint32_t trim_reg_12;
+ __IO uint32_t trim_reg_13;
+ __IO uint32_t trim_reg_14;
+ __IO uint32_t trim_reg_15;
+ __IO uint32_t trim_reg_16;
+ __IO uint32_t trim_reg_17;
+ __IO uint32_t trim_reg_18;
+ __IO uint32_t trim_reg_19;
+ __IO uint32_t trim_reg_20;
+ __IO uint32_t trim_reg_21;
+ __IO uint32_t trim_reg_22;
+ __IO uint32_t trim_reg_23;
+ __IO uint32_t trim_reg_24;
+ __IO uint32_t trim_reg_25;
+ __IO uint32_t trim_reg_26;
+ __IO uint32_t trim_reg_27;
+ __IO uint32_t trim_reg_28;
+ __IO uint32_t trim_reg_29;
+ __IO uint32_t trim_reg_30;
+ __IO uint32_t trim_reg_31;
+ __IO uint32_t trim_reg_32;
+ __IO uint32_t trim_reg_33;
+ __IO uint32_t trim_reg_34;
+ __IO uint32_t trim_reg_35;
+ __IO uint32_t trim_reg_36;
+ __IO uint32_t trim_reg_37;
+ __IO uint32_t trim_reg_38;
+ __IO uint32_t trim_reg_39;
+ __IO uint32_t trim_reg_40;
+ __IO uint32_t trim_reg_41;
+} mxc_ftr_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h
new file mode 100644
index 000000000..49fbe5d96
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h
@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file uart_regs.h
+ * @addtogroup uart UART
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ============================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 UART Control Register */
+ __IO uint32_t status; /* 0x0004 UART Status Register */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t intfl; /* 0x000C Interrupt Flags */
+ __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */
+ __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */
+ __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */
+ __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */
+ __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */
+} mxc_uart_regs_t;
+
+
+/*
+ Register offsets for module UART.
+*/
+#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL)
+#define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL)
+#define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL)
+
+/*
+ Field positions and masks for module UART.
+*/
+#define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0
+#define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
+#define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4
+#define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
+#define MXC_F_UART_CTRL_PARITY_MODE_POS 5
+#define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
+#define MXC_F_UART_CTRL_PARITY_BIAS_POS 6
+#define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10
+#define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
+#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12
+#define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
+#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14
+#define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
+
+#define MXC_F_UART_STATUS_TX_BUSY_POS 0
+#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_BUSY_POS 1
+#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5
+#define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7
+#define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
+
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTEN_CTS_CHANGE_POS 2
+#define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
+#define MXC_F_UART_INTEN_RX_OVERRUN_POS 3
+#define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTFL_CTS_CHANGE_POS 2
+#define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
+#define MXC_F_UART_INTFL_RX_OVERRUN_POS 3
+#define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_BAUD_INT_FBAUD_POS 0
+#define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
+
+#define MXC_F_UART_BAUD_DIV_128_DIV_POS 0
+#define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
+
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
+
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
+
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_UART_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h
new file mode 100644
index 000000000..6f2b9b8e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h
@@ -0,0 +1,480 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file usb_regs.h
+ * @addtogroup usb USB
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t cn; /* 0x0000 USB Control Register */
+ __I uint32_t rsv0004[127]; /* 0x0004 */
+ __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
+ __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
+ __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
+ __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
+ __I uint32_t rsv0210[4]; /* 0x0210 */
+ __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
+ __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
+ __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
+ __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
+ __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
+ __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
+ __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
+ __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
+ __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
+ __I uint32_t rsv0244[7]; /* 0x0244 */
+ __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
+ __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
+ __I uint32_t rsv0268[6]; /* 0x0268 */
+ __IO uint32_t ep[MXC_USB_NUM_EP]; /* 0x0280 USB Endpoint Control Registers */
+} mxc_usb_regs_t;
+
+
+/*
+ Register offsets for module USB.
+*/
+#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
+
+
+/*
+ Field positions and masks for module USB.
+*/
+#define MXC_F_USB_CN_USB_EN_POS 0
+#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
+#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS 3
+#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS 4
+#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS 5
+#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS 6
+#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
+#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
+#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS 2
+#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS 3
+#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
+#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
+#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
+#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
+#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS 2
+#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS 3
+#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
+#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
+#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
+#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
+#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
+#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
+#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV0_POS 0
+#define MXC_F_USB_IN_INT_INBAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS))
+#define MXC_F_USB_IN_INT_INBAV1_POS 1
+#define MXC_F_USB_IN_INT_INBAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS))
+#define MXC_F_USB_IN_INT_INBAV2_POS 2
+#define MXC_F_USB_IN_INT_INBAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS))
+#define MXC_F_USB_IN_INT_INBAV3_POS 3
+#define MXC_F_USB_IN_INT_INBAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS))
+#define MXC_F_USB_IN_INT_INBAV4_POS 4
+#define MXC_F_USB_IN_INT_INBAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS))
+#define MXC_F_USB_IN_INT_INBAV5_POS 5
+#define MXC_F_USB_IN_INT_INBAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS))
+#define MXC_F_USB_IN_INT_INBAV6_POS 6
+#define MXC_F_USB_IN_INT_INBAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS))
+#define MXC_F_USB_IN_INT_INBAV7_POS 7
+#define MXC_F_USB_IN_INT_INBAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV0_POS 0
+#define MXC_F_USB_OUT_INT_OUTDAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV1_POS 1
+#define MXC_F_USB_OUT_INT_OUTDAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV2_POS 2
+#define MXC_F_USB_OUT_INT_OUTDAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV3_POS 3
+#define MXC_F_USB_OUT_INT_OUTDAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV4_POS 4
+#define MXC_F_USB_OUT_INT_OUTDAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV5_POS 5
+#define MXC_F_USB_OUT_INT_OUTDAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV6_POS 6
+#define MXC_F_USB_OUT_INT_OUTDAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV7_POS 7
+#define MXC_F_USB_OUT_INT_OUTDAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS))
+
+#define MXC_F_USB_NAK_INT_NAK0_POS 0
+#define MXC_F_USB_NAK_INT_NAK0 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS))
+#define MXC_F_USB_NAK_INT_NAK1_POS 1
+#define MXC_F_USB_NAK_INT_NAK1 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS))
+#define MXC_F_USB_NAK_INT_NAK2_POS 2
+#define MXC_F_USB_NAK_INT_NAK2 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS))
+#define MXC_F_USB_NAK_INT_NAK3_POS 3
+#define MXC_F_USB_NAK_INT_NAK3 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS))
+#define MXC_F_USB_NAK_INT_NAK4_POS 4
+#define MXC_F_USB_NAK_INT_NAK4 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS))
+#define MXC_F_USB_NAK_INT_NAK5_POS 5
+#define MXC_F_USB_NAK_INT_NAK5 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS))
+#define MXC_F_USB_NAK_INT_NAK6_POS 6
+#define MXC_F_USB_NAK_INT_NAK6 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS))
+#define MXC_F_USB_NAK_INT_NAK7_POS 7
+#define MXC_F_USB_NAK_INT_NAK7 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS 0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS 1
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS 2
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS 3
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS 4
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS 5
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS 6
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS 7
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS 0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS 1
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS 2
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS 3
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS 4
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS 5
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS 6
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS 7
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS 0
+#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS 8
+#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS 16
+#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS 24
+#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE4_POS 0
+#define MXC_F_USB_SETUP1_BYTE4 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS))
+#define MXC_F_USB_SETUP1_BYTE5_POS 8
+#define MXC_F_USB_SETUP1_BYTE5 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS))
+#define MXC_F_USB_SETUP1_BYTE6_POS 16
+#define MXC_F_USB_SETUP1_BYTE6 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS))
+#define MXC_F_USB_SETUP1_BYTE7_POS 24
+#define MXC_F_USB_SETUP1_BYTE7 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS))
+
+#define MXC_F_USB_EP0_EP_DIR_POS 0
+#define MXC_F_USB_EP0_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS))
+#define MXC_F_USB_EP0_EP_BUF2_POS 3
+#define MXC_F_USB_EP0_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS))
+#define MXC_F_USB_EP0_EP_INT_EN_POS 4
+#define MXC_F_USB_EP0_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS))
+#define MXC_F_USB_EP0_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP0_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS))
+#define MXC_F_USB_EP0_EP_DT_POS 6
+#define MXC_F_USB_EP0_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS))
+#define MXC_F_USB_EP0_EP_STALL_POS 8
+#define MXC_F_USB_EP0_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP0_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP0_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP1_EP_DIR_POS 0
+#define MXC_F_USB_EP1_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS))
+#define MXC_F_USB_EP1_EP_BUF2_POS 3
+#define MXC_F_USB_EP1_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS))
+#define MXC_F_USB_EP1_EP_INT_EN_POS 4
+#define MXC_F_USB_EP1_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS))
+#define MXC_F_USB_EP1_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP1_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS))
+#define MXC_F_USB_EP1_EP_DT_POS 6
+#define MXC_F_USB_EP1_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS))
+#define MXC_F_USB_EP1_EP_STALL_POS 8
+#define MXC_F_USB_EP1_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP1_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP1_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP2_EP_DIR_POS 0
+#define MXC_F_USB_EP2_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS))
+#define MXC_F_USB_EP2_EP_BUF2_POS 3
+#define MXC_F_USB_EP2_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS))
+#define MXC_F_USB_EP2_EP_INT_EN_POS 4
+#define MXC_F_USB_EP2_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS))
+#define MXC_F_USB_EP2_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP2_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS))
+#define MXC_F_USB_EP2_EP_DT_POS 6
+#define MXC_F_USB_EP2_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS))
+#define MXC_F_USB_EP2_EP_STALL_POS 8
+#define MXC_F_USB_EP2_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP2_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP2_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP3_EP_DIR_POS 0
+#define MXC_F_USB_EP3_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS))
+#define MXC_F_USB_EP3_EP_BUF2_POS 3
+#define MXC_F_USB_EP3_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS))
+#define MXC_F_USB_EP3_EP_INT_EN_POS 4
+#define MXC_F_USB_EP3_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS))
+#define MXC_F_USB_EP3_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP3_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS))
+#define MXC_F_USB_EP3_EP_DT_POS 6
+#define MXC_F_USB_EP3_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS))
+#define MXC_F_USB_EP3_EP_STALL_POS 8
+#define MXC_F_USB_EP3_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP3_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP3_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP4_EP_DIR_POS 0
+#define MXC_F_USB_EP4_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS))
+#define MXC_F_USB_EP4_EP_BUF2_POS 3
+#define MXC_F_USB_EP4_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS))
+#define MXC_F_USB_EP4_EP_INT_EN_POS 4
+#define MXC_F_USB_EP4_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS))
+#define MXC_F_USB_EP4_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP4_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS))
+#define MXC_F_USB_EP4_EP_DT_POS 6
+#define MXC_F_USB_EP4_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS))
+#define MXC_F_USB_EP4_EP_STALL_POS 8
+#define MXC_F_USB_EP4_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP4_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP4_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP5_EP_DIR_POS 0
+#define MXC_F_USB_EP5_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS))
+#define MXC_F_USB_EP5_EP_BUF2_POS 3
+#define MXC_F_USB_EP5_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS))
+#define MXC_F_USB_EP5_EP_INT_EN_POS 4
+#define MXC_F_USB_EP5_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS))
+#define MXC_F_USB_EP5_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP5_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS))
+#define MXC_F_USB_EP5_EP_DT_POS 6
+#define MXC_F_USB_EP5_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS))
+#define MXC_F_USB_EP5_EP_STALL_POS 8
+#define MXC_F_USB_EP5_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP5_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP5_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP6_EP_DIR_POS 0
+#define MXC_F_USB_EP6_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS))
+#define MXC_F_USB_EP6_EP_BUF2_POS 3
+#define MXC_F_USB_EP6_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS))
+#define MXC_F_USB_EP6_EP_INT_EN_POS 4
+#define MXC_F_USB_EP6_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS))
+#define MXC_F_USB_EP6_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP6_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS))
+#define MXC_F_USB_EP6_EP_DT_POS 6
+#define MXC_F_USB_EP6_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS))
+#define MXC_F_USB_EP6_EP_STALL_POS 8
+#define MXC_F_USB_EP6_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP6_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP6_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP7_EP_DIR_POS 0
+#define MXC_F_USB_EP7_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS))
+#define MXC_F_USB_EP7_EP_BUF2_POS 3
+#define MXC_F_USB_EP7_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS))
+#define MXC_F_USB_EP7_EP_INT_EN_POS 4
+#define MXC_F_USB_EP7_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS))
+#define MXC_F_USB_EP7_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP7_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS))
+#define MXC_F_USB_EP7_EP_DT_POS 6
+#define MXC_F_USB_EP7_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS))
+#define MXC_F_USB_EP7_EP_STALL_POS 8
+#define MXC_F_USB_EP7_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP7_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP7_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP_DIR_POS (0)
+#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+
+#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+#define MXC_F_USB_EP_BUF2_POS (3)
+#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INTEN_POS (4)
+#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INTEN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS (5)
+#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS (6)
+#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS (8)
+#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS (9)
+#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS (10)
+#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_USB_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h
new file mode 100644
index 000000000..906e80146
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_WDT_REGS_H_
+#define _MXC_WDT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file wdt_regs.h
+ * @addtogroup wdt WDT
+ * @{
+ */
+
+/**
+ * @brief Defines watchdog timer periods
+ */
+typedef enum {
+ /** 2^31 cycle period */
+ MXC_E_WDT_PERIOD_2_31_CLKS = 0,
+ /** 2^30 cycle period */
+ MXC_E_WDT_PERIOD_2_30_CLKS,
+ /** 2^29 cycle period */
+ MXC_E_WDT_PERIOD_2_29_CLKS,
+ /** 2^28 cycle period */
+ MXC_E_WDT_PERIOD_2_28_CLKS,
+ /** 2^27 cycle period */
+ MXC_E_WDT_PERIOD_2_27_CLKS,
+ /** 2^26 cycle period */
+ MXC_E_WDT_PERIOD_2_26_CLKS,
+ /** 2^25 cycle period */
+ MXC_E_WDT_PERIOD_2_25_CLKS,
+ /** 2^24 cycle period */
+ MXC_E_WDT_PERIOD_2_24_CLKS,
+ /** 2^23 cycle period */
+ MXC_E_WDT_PERIOD_2_23_CLKS,
+ /** 2^22 cycle period */
+ MXC_E_WDT_PERIOD_2_22_CLKS,
+ /** 2^21 cycle period */
+ MXC_E_WDT_PERIOD_2_21_CLKS,
+ /** 2^20 cycle period */
+ MXC_E_WDT_PERIOD_2_20_CLKS,
+ /** 2^19 cycle period */
+ MXC_E_WDT_PERIOD_2_19_CLKS,
+ /** 2^18 cycle period */
+ MXC_E_WDT_PERIOD_2_18_CLKS,
+ /** 2^17 cycle period */
+ MXC_E_WDT_PERIOD_2_17_CLKS,
+ /** 2^16 cycle period */
+ MXC_E_WDT_PERIOD_2_16_CLKS,
+} mxc_wdt_period_t;
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
+ __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */
+ __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */
+ __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */
+ __I uint32_t rsv0010; /* 0x0010 */
+ __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */
+} mxc_wdt_regs_t;
+
+/*
+ Register offsets for module WDT.
+*/
+#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
+#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL)
+#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL)
+#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
+
+#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24)
+#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42)
+
+
+/*
+ Field positions and masks for module WDT.
+*/
+#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
+#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
+#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
+#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
+#define MXC_F_WDT_CTRL_EN_TIMER_POS 8
+#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
+#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
+#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
+#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
+#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
+
+#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
+#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
+#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
+#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
+#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
+#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
+
+#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
+#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
+#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
+#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
+#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
+#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
+
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_WDT_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct
new file mode 100644
index 000000000..61369d305
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct
@@ -0,0 +1,21 @@
+
+; MAX32610
+; 256KB FLASH (0x40000) @ 0x000000000
+; 2KB RAM (0x8000) @ 0x20000000
+
+
+; MAX32610: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment
+ RW_IRAM1 (0x20000000+0x140) (0x8000-0x140) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+} \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s
new file mode 100644
index 000000000..e3c52cae9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.s
@@ -0,0 +1,255 @@
+;*******************************************************************************
+; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice shall be included
+; in all copies or substantial portions of the Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+; OTHER DEALINGS IN THE SOFTWARE.
+;
+; Except as contained in this notice, the name of Maxim Integrated
+; Products, Inc. shall not be used except as stated in the Maxim Integrated
+; Products, Inc. Branding Policy.
+;
+; The mere transfer of this software does not imply any licenses
+; of trade secrets, proprietary technology, copyrights, patents,
+; trademarks, maskwork rights, or any other form of intellectual
+; property whatsoever. Maxim Integrated Products, Inc. retains all
+; ownership rights.
+;*******************************************************************************
+
+__initial_sp EQU 0x20008000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD DefaultIRQ_Handler ; MPU Fault Handler
+ DCD DefaultIRQ_Handler ; Bus Fault Handler
+ DCD DefaultIRQ_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DefaultIRQ_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD DefaultIRQ_Handler ; PendSV Handler
+ DCD SysTick_IRQHandler ; SysTick Handler
+
+ ; Maxim 32610 Externals interrupts
+ DCD UART0_IRQHandler ; 16: 1 UART0
+ DCD UART1_IRQHandler ; 17: 2 UART1
+ DCD I2CM0_IRQHandler ; 18: 3 I2C Master 0
+ DCD I2CS_IRQHandler ; 19: 4 I2C Slave
+ DCD USB_IRQHandler ; 20: 5 USB
+ DCD PMU_IRQHandler ; 21: 6 DMA
+ DCD AFE_IRQHandler ; 22: 7 AFE
+ DCD MAA_IRQHandler ; 23: 8 MAA
+ DCD AES_IRQHandler ; 24: 9 AES
+ DCD SPI0_IRQHandler ; 25:10 SPI0
+ DCD SPI1_IRQHandler ; 26:11 SPI1
+ DCD SPI2_IRQHandler ; 27:12 SPI2
+ DCD TMR0_IRQHandler ; 28:13 Timer32-0
+ DCD TMR1_IRQHandler ; 29:14 Timer32-1
+ DCD TMR2_IRQHandler ; 30:15 Timer32-1
+ DCD TMR3_IRQHandler ; 31:16 Timer32-2
+ DCD RSVD0_IRQHandler ; 32:17 RSVD
+ DCD RSVD1_IRQHandler ; 33:18 RSVD
+ DCD DAC0_IRQHandler ; 34:19 DAC0 (12-bit DAC)
+ DCD DAC1_IRQHandler ; 35:20 DAC1 (12-bit DAC)
+ DCD DAC2_IRQHandler ; 36:21 DAC2 (8-bit DAC)
+ DCD DAC3_IRQHandler ; 37:22 DAC3 (8-bit DAC)
+ DCD ADC_IRQHandler ; 38:23 ADC
+ DCD FLC_IRQHandler ; 39:24 Flash Controller
+ DCD PWRMAN_IRQHandler ; 40:25 PWRMAN
+ DCD CLKMAN_IRQHandler ; 41:26 CLKMAN
+ DCD RTC0_IRQHandler ; 42:27 RTC INT0
+ DCD RTC1_IRQHandler ; 43:28 RTC INT1
+ DCD RTC2_IRQHandler ; 44:29 RTC INT2
+ DCD RTC3_IRQHandler ; 45:30 RTC INT3
+ DCD WDT0_IRQHandler ; 46:31 WATCHDOG0
+ DCD WDT0_P_IRQHandler ; 47:32 WATCHDOG0 PRE-WINDOW
+ DCD WDT1_IRQHandler ; 48:33 WATCHDOG1
+ DCD WDT1_P_IRQHandler ; 49:34 WATCHDOG1 PRE-WINDOW
+ DCD GPIO_P0_IRQHandler ; 50:35 GPIO Port 0
+ DCD GPIO_P1_IRQHandler ; 51:36 GPIO Port 1
+ DCD GPIO_P2_IRQHandler ; 52:37 GPIO Port 2
+ DCD GPIO_P3_IRQHandler ; 53:38 GPIO Port 3
+ DCD GPIO_P4_IRQHandler ; 54:39 GPIO Port 4
+ DCD GPIO_P5_IRQHandler ; 55:40 GPIO Port 5
+ DCD GPIO_P6_IRQHandler ; 56:41 GPIO Port 6
+ DCD GPIO_P7_IRQHandler ; 57:42 GPIO Port 7
+ DCD TMR16_0_IRQHandler ; 58:43 Timer16-s0
+ DCD TMR16_1_IRQHandler ; 59:44 Timer16-s1
+ DCD TMR16_2_IRQHandler ; 60:45 Timer16-s2
+ DCD TMR16_3_IRQHandler ; 61:46 Timer16-s3
+ DCD I2CM1_IRQHandler ; 62:47 I2C Master 1
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B NMI_Handler
+ ENDP
+
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B HardFault_Handler
+ ENDP
+
+DefaultIRQ_Handler PROC
+ EXPORT DefaultIRQ_Handler [WEAK]
+ B DefaultIRQ_Handler
+ ENDP
+
+DebugMon_Handler PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B DebugMon_Handler
+ ENDP
+
+SysTick_IRQHandler PROC
+ EXPORT SysTick_IRQHandler [WEAK]
+ B SysTick_IRQHandler
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT I2CM0_IRQHandler [WEAK]
+ EXPORT I2CS_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT PMU_IRQHandler [WEAK]
+ EXPORT AFE_IRQHandler [WEAK]
+ EXPORT MAA_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT RSVD0_IRQHandler [WEAK]
+ EXPORT RSVD1_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DAC3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FLC_IRQHandler [WEAK]
+ EXPORT PWRMAN_IRQHandler [WEAK]
+ EXPORT CLKMAN_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT RTC2_IRQHandler [WEAK]
+ EXPORT RTC3_IRQHandler [WEAK]
+ EXPORT WDT0_IRQHandler [WEAK]
+ EXPORT WDT0_P_IRQHandler [WEAK]
+ EXPORT WDT1_IRQHandler [WEAK]
+ EXPORT WDT1_P_IRQHandler [WEAK]
+ EXPORT GPIO_P0_IRQHandler [WEAK]
+ EXPORT GPIO_P1_IRQHandler [WEAK]
+ EXPORT GPIO_P2_IRQHandler [WEAK]
+ EXPORT GPIO_P3_IRQHandler [WEAK]
+ EXPORT GPIO_P4_IRQHandler [WEAK]
+ EXPORT GPIO_P5_IRQHandler [WEAK]
+ EXPORT GPIO_P6_IRQHandler [WEAK]
+ EXPORT GPIO_P7_IRQHandler [WEAK]
+ EXPORT TMR16_0_IRQHandler [WEAK]
+ EXPORT TMR16_1_IRQHandler [WEAK]
+ EXPORT TMR16_2_IRQHandler [WEAK]
+ EXPORT TMR16_3_IRQHandler [WEAK]
+ EXPORT I2CM1_IRQHandler [WEAK]
+
+UART0_IRQHandler
+UART1_IRQHandler
+I2CM0_IRQHandler
+I2CS_IRQHandler
+USB_IRQHandler
+PMU_IRQHandler
+AFE_IRQHandler
+MAA_IRQHandler
+AES_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+RSVD0_IRQHandler
+RSVD1_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+DAC2_IRQHandler
+DAC3_IRQHandler
+ADC_IRQHandler
+FLC_IRQHandler
+PWRMAN_IRQHandler
+CLKMAN_IRQHandler
+RTC0_IRQHandler
+RTC1_IRQHandler
+RTC2_IRQHandler
+RTC3_IRQHandler
+WDT0_IRQHandler
+WDT0_P_IRQHandler
+WDT1_IRQHandler
+WDT1_P_IRQHandler
+GPIO_P0_IRQHandler
+GPIO_P1_IRQHandler
+GPIO_P2_IRQHandler
+GPIO_P3_IRQHandler
+GPIO_P4_IRQHandler
+GPIO_P5_IRQHandler
+GPIO_P6_IRQHandler
+GPIO_P7_IRQHandler
+TMR16_0_IRQHandler
+TMR16_1_IRQHandler
+TMR16_2_IRQHandler
+TMR16_3_IRQHandler
+I2CM1_IRQHandler
+
+ B .
+ ENDP
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..90d1391ba
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,57 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld
new file mode 100644
index 000000000..be14fd10a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld
@@ -0,0 +1,182 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+/******************************************************************************
+ *
+ * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S
new file mode 100644
index 000000000..cda4da904
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S
@@ -0,0 +1,262 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Externals interrupts */
+ .long UART0_IRQHandler /* 16: 1 UART0 */
+ .long UART1_IRQHandler /* 17: 2 UART1 */
+ .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ .long I2CS_IRQHandler /* 19: 4 I2C Slave */
+ .long USB_IRQHandler /* 20: 5 USB */
+ .long PMU_IRQHandler /* 21: 6 DMA */
+ .long AFE_IRQHandler /* 22: 7 AFE */
+ .long MAA_IRQHandler /* 23: 8 MAA */
+ .long AES_IRQHandler /* 24: 9 AES */
+ .long SPI0_IRQHandler /* 25:10 SPI0 */
+ .long SPI1_IRQHandler /* 26:11 SPI1 */
+ .long SPI2_IRQHandler /* 27:12 SPI2 */
+ .long TMR0_IRQHandler /* 28:13 Timer32-0 */
+ .long TMR1_IRQHandler /* 29:14 Timer32-1 */
+ .long TMR2_IRQHandler /* 30:15 Timer32-1 */
+ .long TMR3_IRQHandler /* 31:16 Timer32-2 */
+ .long RSVD0_IRQHandler /* 32:17 RSVD */
+ .long RSVD1_IRQHandler /* 33:18 RSVD */
+ .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ .long ADC_IRQHandler /* 38:23 ADC */
+ .long FLC_IRQHandler /* 39:24 Flash Controller */
+ .long PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ .long CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ .long RTC0_IRQHandler /* 42:27 RTC INT0 */
+ .long RTC1_IRQHandler /* 43:28 RTC INT1 */
+ .long RTC2_IRQHandler /* 44:29 RTC INT2 */
+ .long RTC3_IRQHandler /* 45:30 RTC INT3 */
+ .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */
+ def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */
+ def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */
+ def_irq_default_handler USB_IRQHandler /* 20: 5 USB */
+ def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */
+ def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */
+ def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */
+ def_irq_default_handler AES_IRQHandler /* 24: 9 AES */
+ def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */
+ def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */
+ def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */
+ def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */
+ def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */
+ def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */
+ def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */
+ def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */
+ def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */
+ def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */
+ def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */
+ def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */
+ def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */
+ def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */
+ def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */
+ def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf
new file mode 100644
index 000000000..2b90dc973
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf
@@ -0,0 +1,29 @@
+/* [ROM] */
+define symbol __intvec_start__ = 0x0;
+define symbol __region_ROM_start__ = 0x0;
+define symbol __region_ROM_end__ = 0x0003FFFF;
+
+/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */
+define symbol __NVIC_start__ = 0x00000000;
+define symbol __NVIC_end__ = 0x00000140; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000000;
+define symbol __region_RAM_end__ = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x800;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s
new file mode 100644
index 000000000..518756c0b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.s
@@ -0,0 +1,383 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table DCD sfe(CSTACK) /* Top of Stack */
+ DCD Reset_Handler /* Reset Handler */
+ DCD NMI_Handler /* NMI Handler */
+ DCD HardFault_Handler /* Hard Fault Handler */
+ DCD DefaultIRQ_Handler /* MPU Fault Handler */
+ DCD DefaultIRQ_Handler /* Bus Fault Handler */
+ DCD DefaultIRQ_Handler /* Usage Fault Handler */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD 0 /* Reserved */
+ DCD DefaultIRQ_Handler /* SVCall Handler */
+ DCD DebugMon_Handler /* Debug Monitor Handler */
+ DCD 0 /* Reserved */
+ DCD DefaultIRQ_Handler /* PendSV Handler */
+ DCD SysTick_IRQHandler /* SysTick Handler */
+
+ /* Maxim 32610 Externals interrupts */
+ DCD UART0_IRQHandler /* 16: 1 UART0 */
+ DCD UART1_IRQHandler /* 17: 2 UART1 */
+ DCD I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
+ DCD I2CS_IRQHandler /* 19: 4 I2C Slave */
+ DCD USB_IRQHandler /* 20: 5 USB */
+ DCD PMU_IRQHandler /* 21: 6 DMA */
+ DCD AFE_IRQHandler /* 22: 7 AFE */
+ DCD MAA_IRQHandler /* 23: 8 MAA */
+ DCD AES_IRQHandler /* 24: 9 AES */
+ DCD SPI0_IRQHandler /* 25:10 SPI0 */
+ DCD SPI1_IRQHandler /* 26:11 SPI1 */
+ DCD SPI2_IRQHandler /* 27:12 SPI2 */
+ DCD TMR0_IRQHandler /* 28:13 Timer32-0 */
+ DCD TMR1_IRQHandler /* 29:14 Timer32-1 */
+ DCD TMR2_IRQHandler /* 30:15 Timer32-1 */
+ DCD TMR3_IRQHandler /* 31:16 Timer32-2 */
+ DCD RSVD0_IRQHandler /* 32:17 RSVD */
+ DCD RSVD1_IRQHandler /* 33:18 RSVD */
+ DCD DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
+ DCD DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
+ DCD DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
+ DCD DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
+ DCD ADC_IRQHandler /* 38:23 ADC */
+ DCD FLC_IRQHandler /* 39:24 Flash Controller */
+ DCD PWRMAN_IRQHandler /* 40:25 PWRMAN */
+ DCD CLKMAN_IRQHandler /* 41:26 CLKMAN */
+ DCD RTC0_IRQHandler /* 42:27 RTC INT0 */
+ DCD RTC1_IRQHandler /* 43:28 RTC INT1 */
+ DCD RTC2_IRQHandler /* 44:29 RTC INT2 */
+ DCD RTC3_IRQHandler /* 45:30 RTC INT3 */
+ DCD WDT0_IRQHandler /* 46:31 WATCHDOG0 */
+ DCD WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
+ DCD WDT1_IRQHandler /* 48:33 WATCHDOG1 */
+ DCD WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
+ DCD GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
+ DCD GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
+ DCD GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
+ DCD GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
+ DCD GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
+ DCD GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
+ DCD GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
+ DCD GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
+ DCD TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
+ DCD TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
+ DCD TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
+ DCD TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
+ DCD I2CM1_IRQHandler /* 62:47 I2C Master 1 */
+
+ THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK DefaultIRQ_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DefaultIRQ_Handler
+ B DefaultIRQ_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK SysTick_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_IRQHandler
+ B SysTick_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK I2CM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM0_IRQHandler
+ B I2CM0_IRQHandler
+
+ PUBWEAK I2CS_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CS_IRQHandler
+ B I2CS_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ PUBWEAK PMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PMU_IRQHandler
+ B PMU_IRQHandler
+
+ PUBWEAK AFE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AFE_IRQHandler
+ B AFE_IRQHandler
+
+ PUBWEAK MAA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MAA_IRQHandler
+ B MAA_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK TMR0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR0_IRQHandler
+ B TMR0_IRQHandler
+
+ PUBWEAK TMR1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_IRQHandler
+ B TMR1_IRQHandler
+
+ PUBWEAK TMR2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+ B TMR2_IRQHandler
+
+ PUBWEAK TMR3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+ B TMR3_IRQHandler
+
+ PUBWEAK RSVD0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD0_IRQHandler
+ B RSVD0_IRQHandler
+
+ PUBWEAK RSVD1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD1_IRQHandler
+ B RSVD1_IRQHandler
+
+ PUBWEAK DAC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC0_IRQHandler
+ B DAC0_IRQHandler
+
+ PUBWEAK DAC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC1_IRQHandler
+ B DAC1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DAC3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DAC3_IRQHandler
+ B DAC3_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FLC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLC_IRQHandler
+ B FLC_IRQHandler
+
+ PUBWEAK PWRMAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWRMAN_IRQHandler
+ B PWRMAN_IRQHandler
+
+ PUBWEAK CLKMAN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CLKMAN_IRQHandler
+ B CLKMAN_IRQHandler
+
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B RTC0_IRQHandler
+
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B RTC1_IRQHandler
+
+ PUBWEAK RTC2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC2_IRQHandler
+ B RTC2_IRQHandler
+
+ PUBWEAK RTC3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC3_IRQHandler
+ B RTC3_IRQHandler
+
+ PUBWEAK WDT0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_IRQHandler
+ B WDT0_IRQHandler
+
+ PUBWEAK WDT0_P_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_P_IRQHandler
+ B WDT0_P_IRQHandler
+
+ PUBWEAK WDT1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_IRQHandler
+ B WDT1_IRQHandler
+
+ PUBWEAK WDT1_P_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_P_IRQHandler
+ B WDT1_P_IRQHandler
+
+ PUBWEAK GPIO_P0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P0_IRQHandler
+ B GPIO_P0_IRQHandler
+
+ PUBWEAK GPIO_P1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P1_IRQHandler
+ B GPIO_P1_IRQHandler
+
+ PUBWEAK GPIO_P2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P2_IRQHandler
+ B GPIO_P2_IRQHandler
+
+ PUBWEAK GPIO_P3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P3_IRQHandler
+ B GPIO_P3_IRQHandler
+
+ PUBWEAK GPIO_P4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P4_IRQHandler
+ B GPIO_P4_IRQHandler
+
+ PUBWEAK GPIO_P5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P5_IRQHandler
+ B GPIO_P5_IRQHandler
+
+ PUBWEAK GPIO_P6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P6_IRQHandler
+ B GPIO_P6_IRQHandler
+
+ PUBWEAK GPIO_P7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P7_IRQHandler
+ B GPIO_P7_IRQHandler
+
+ PUBWEAK TMR16_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_0_IRQHandler
+ B TMR16_0_IRQHandler
+
+ PUBWEAK TMR16_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_1_IRQHandler
+ B TMR16_1_IRQHandler
+
+ PUBWEAK TMR16_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_2_IRQHandler
+ B TMR16_2_IRQHandler
+
+ PUBWEAK TMR16_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_3_IRQHandler
+ B TMR16_3_IRQHandler
+
+ PUBWEAK I2CM1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM1_IRQHandler
+ B I2CM1_IRQHandler
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h
new file mode 100644
index 000000000..4e4d5299c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h
@@ -0,0 +1,466 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ADC_REGS_H
+#define _MXC_ADC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file adc_regs.h
+ * @addtogroup adc ADC
+ * @{
+ */
+
+/**
+ * @brief Defines ADC Modes.
+ */
+typedef enum {
+ /** Single Mode Full Rate */
+ MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
+ /** Single Mode Low Power */
+ MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
+ /** Continuous Mode Full Rate */
+ MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
+ /** Continuous Mode Low Power */
+ MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
+ /** Single Mode Full Rate with Scan Enabled */
+ MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
+ /** Single Mode Low Power with Scan Enabled */
+ MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
+ /** Continuous Mode Full Rate with Scan Enabled */
+ MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
+ /** Continuous Mode Low Power with Scan Enabled */
+ MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
+} mxc_adc_mode_t;
+
+/**
+ * @brief Defines ADC Range Control.
+ */
+typedef enum {
+ /** Bi-polar Operation (-Vref/2 -> Vref/2) */
+ MXC_E_ADC_RANGE_HALF = 0,
+ /** Bi-polar Operation (-Vref -> Vref) */
+ MXC_E_ADC_RANGE_FULL
+} mxc_adc_range_t;
+
+/**
+ * @brief Defines ADC Bipolar operation.
+ */
+typedef enum {
+ /** Uni-polar operation (0 -> Vref) */
+ MXC_E_ADC_BI_POL_UNIPOLAR = 0,
+ /** Bi-polar operation see ADC Range Control */
+ MXC_E_ADC_BI_POL_BIPOLAR
+} mxc_adc_bi_pol_t;
+
+/**
+ * @brief Defines Decimation Filter Modes.
+ */
+typedef enum {
+ /** Decimation Filter ByPassed */
+ MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
+ /** Output Average Only*/
+ MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
+ /** Output Average and Raw Data (Test Mode Only) */
+ MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
+} mxc_adc_avg_mode_t;
+
+/**
+ * @brief Defines ADC StartMode Modes.
+ */
+typedef enum {
+ /** StarMode via Software */
+ MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
+ /** StarMode via PulseTrain */
+ MXC_E_ADC_STRT_MODE_PULSETRAIN
+} mxc_adc_strt_mode_t;
+
+/**
+ * @brief Defines Mux Channel Select for the Positive Input to the ADC.
+ */
+typedef enum {
+ /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
+ /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
+ /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
+ /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
+ /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
+ /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
+ /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
+ /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
+ /** Single Mode Input AIN8+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
+ /** Single Mode Input AIN9+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
+ /** Single Mode Input AIN10+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
+ /** Single Mode Input AIN11+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
+ /** Single Mode Input AIN12+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
+ /** Single Mode Input AIN13+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
+ /** Single Mode Input AIN14+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
+ /** Single Mode Input AIN15+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
+ /** Positive Input VSSADC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
+ /** Positive Input TMON_R */
+ MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
+ /** Positive Input VDDA/4 */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
+ /** Positive Input PWRMAN_TST */
+ MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
+ /** Positive Input Ain0Div */
+ MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
+ /** Positive Input OpAmp OUTA */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
+ /** Positive Input OpAmp OUTB */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
+ /** Positive Input OpAmp OUTC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
+ /** Positive Input OpAmp OUTD */
+ MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
+ /** Positive INA+ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
+ /** Positive SNO_or */
+ MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
+ /** Positive SCM_or */
+ MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
+ /** Positive TPROBE_sense */
+ MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
+ /** Positive VREFDAC */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
+ /** Positive VREFADJ */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
+ /** Positive Vdd3xtal */
+ MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
+} mxc_adc_pga_mux_ch_sel_t;
+
+/**
+ * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
+ */
+typedef enum {
+ /** Differential Mode Disabled */
+ MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
+ /** Differential Mode Enabled */
+ MXC_E_ADC_PGA_MUX_DIFF_ENABLE
+} mxc_adc_pga_mux_diff_t;
+
+/**
+ * @brief Defines the PGA Gain Options.
+ */
+typedef enum {
+ /** PGA Gain = 1 */
+ MXC_E_ADC_PGA_GAIN_1 = 0,
+ /** PGA Gain = 2 */
+ MXC_E_ADC_PGA_GAIN_2,
+ /** PGA Gain = 4 */
+ MXC_E_ADC_PGA_GAIN_4,
+ /** PGA Gain = 8 */
+ MXC_E_ADC_PGA_GAIN_8,
+} mxc_adc_pga_gain_t;
+
+/**
+ * @brief Defines the Switch Control Mode.
+ */
+typedef enum {
+ /** Switch Control Mode = Software */
+ MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
+ /** Switch Control Mode = Pulse Train */
+ MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
+} mxc_adc_spst_sw_ctrl_t;
+
+/**
+ * @brief Defines the number of channels to scan when Scan Mode is enabled.
+ */
+typedef enum {
+ /** Number of Channels to Scan = 1 */
+ MXC_E_ADC_SCAN_CNT_1 = 0,
+ /** Number of Channels to Scan = 2 */
+ MXC_E_ADC_SCAN_CNT_2,
+ /** Number of Channels to Scan = 3 */
+ MXC_E_ADC_SCAN_CNT_3,
+ /** Number of Channels to Scan = 4 */
+ MXC_E_ADC_SCAN_CNT_4,
+ /** Number of Channels to Scan = 5 */
+ MXC_E_ADC_SCAN_CNT_5,
+ /** Number of Channels to Scan = 6 */
+ MXC_E_ADC_SCAN_CNT_6,
+ /** Number of Channels to Scan = 7 */
+ MXC_E_ADC_SCAN_CNT_7,
+ /** Number of Channels to Scan = 8 */
+ MXC_E_ADC_SCAN_CNT_8,
+} mxc_adc_scan_cnt_t;
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
+ __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
+ __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
+ __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
+ __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
+ __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
+ __IO uint32_t out; /* 0x0018 ADC Output Register */
+} mxc_adc_regs_t;
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
+ __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
+ __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
+ __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
+ __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
+} mxc_adccfg_regs_t;
+
+typedef struct {
+ __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
+} mxc_adc_fifo_regs_t;
+
+/*
+ Register offsets for module ADC, ADCCFG, ADC_FIFO
+*/
+#define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
+#define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
+#define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
+#define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
+
+#define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
+#define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
+#define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
+
+/*
+ Field positions and masks for module ADC.
+*/
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
+#define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
+#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
+#define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
+#define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_POS 9
+#define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
+#define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
+#define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
+#define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
+#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
+#define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
+#define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
+
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
+
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
+
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
+
+#define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
+#define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
+
+#define MXC_F_ADC_INTR_FIFO_AF_POS 6
+#define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
+#define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
+#define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
+#define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
+#define MXC_F_ADC_INTR_DONE_IF_POS 10
+#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
+#define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
+#define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
+#define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
+#define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
+#define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
+#define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
+#define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
+#define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
+#define MXC_F_ADC_INTR_DONE_IE_POS 26
+#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
+#define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
+#define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
+#define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
+#define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
+#define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
+
+#define MXC_F_ADC_OUT_DATA_REG_POS 0
+#define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
+
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
+
+#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
+#define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
+#define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
+#define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
+#define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
+
+#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
+#define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
+#define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
+#define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
+#define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
+
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
+#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
+#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
+
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
+#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
+#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
+#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_ADC_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h
new file mode 100644
index 000000000..cf9995be4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h
@@ -0,0 +1,159 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AES_REGS_H_
+#define _MXC_AES_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file aes_regs.h
+ * @addtogroup aes AES
+ * @{
+ */
+
+/**
+ * @brief Settings for AES_CTRL.CRYPT_MODE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
+ MXC_E_AES_CTRL_DECRYPT_MODE = 1
+} mxc_aes_ctrl_crypt_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.EXP_KEY_MODE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
+ MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
+} mxc_aes_ctrl_exp_key_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.KEY_SIZE
+ */
+typedef enum {
+ MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
+ MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
+ MXC_E_AES_CTRL_KEY_SIZE_256 = 2
+} mxc_aes_ctrl_key_size_t;
+
+/* Offset Register Description
+ ====== =========================================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 AES Control and Status */
+ __I uint32_t rsv004; /* 0x0004 */
+ __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */
+} mxc_aes_regs_t;
+
+/* Offset Register Description
+ ====== =========================================================== */
+typedef struct {
+ __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */
+ __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */
+ __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */
+ __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */
+} mxc_aes_mem_regs_t;
+
+/*
+ Register offsets for module AES.
+*/
+#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL)
+#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL)
+#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL)
+#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL)
+#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL)
+#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL)
+#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL)
+#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL)
+#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL)
+#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL)
+#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL)
+#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL)
+#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL)
+#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL)
+#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL)
+
+#define MXC_F_AES_CTRL_START_POS 0
+#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
+#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1
+#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2
+#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_F_AES_CTRL_KEY_SIZE_POS 3
+#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_F_AES_CTRL_INTEN_POS 5
+#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
+#define MXC_F_AES_CTRL_INTFL_POS 6
+#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
+
+#define MXC_V_AES_CTRL_ENCRYPT_MODE 0
+#define MXC_V_AES_CTRL_DECRYPT_MODE 1
+#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+
+#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0
+#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1
+#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+
+#define MXC_V_AES_CTRL_KEY_SIZE_128 0
+#define MXC_V_AES_CTRL_KEY_SIZE_192 1
+#define MXC_V_AES_CTRL_KEY_SIZE_256 2
+#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_AES_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h
new file mode 100644
index 000000000..31a3f7cb8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h
@@ -0,0 +1,626 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AFE_REGS_H
+#define _MXC_AFE_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file afe_regs.h
+ * @addtogroup afe AFE
+ * @{
+ */
+
+/**
+ * @brief Defines Configure Options for the LED Ports.
+ */
+typedef enum {
+ /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
+ MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
+ /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
+ MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
+ /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
+ MXC_E_AFE_LED_CFG_PORT_DISABLED,
+} mxc_afe_led_cfg_port_t;
+
+/**
+ * @brief Setup of Wake Up Detector for LPCs.
+ */
+typedef enum {
+ /** IDLE */
+ MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
+ /** Activate WUD for falling edges */
+ MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
+ /** Activate WUD for rising edges */
+ MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
+} mxc_afe_en_wud_comp_t;
+
+/**
+ * @brief LPC InMode.
+ */
+typedef enum {
+ /** InMode: both Nch and Pch */
+ MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
+ /** InMode: only Nch */
+ MXC_E_AFE_IN_MODE_COMP_NCH,
+ /** InMode: only Pch */
+ MXC_E_AFE_IN_MODE_COMP_PCH,
+} mxc_afe_in_mode_comp_t;
+
+/**
+ * @brief LPC Bias.
+ */
+typedef enum {
+ /** BIAS 0.52uA Delay 4.0us */
+ MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
+ /** BIAS 1.4uA Delay 1.7us */
+ MXC_E_AFE_BIAS_MODE_COMP_1,
+ /** BIAS 2.8uA Delay 1.1us */
+ MXC_E_AFE_BIAS_MODE_COMP_2,
+ /** BIAS 5.1uA Delay 0.7us */
+ MXC_E_AFE_BIAS_MODE_COMP_3
+} mxc_afe_bias_mode_comp_t;
+
+/**
+ * @brief TMON Current Value.
+ */
+typedef enum {
+ /** TMON Current 4uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
+ /** TMON Current 60uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_1,
+ /** TMON Current 64uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_2,
+ /** TMON Current 120uA */
+ MXC_E_AFE_TMON_CURRENT_VAL_3
+} mxc_afe_tmon_current_t;
+
+/**
+ * @brief REFADC and REFDAC Voltage Select.
+ */
+typedef enum {
+ /** Voltage Reference = 1.024 V */
+ MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
+ /** Voltage Reference = 1.5 V */
+ MXC_E_AFE_REF_VOLT_SEL_1500,
+ /** Voltage Reference = 2.048 V */
+ MXC_E_AFE_REF_VOLT_SEL_2048,
+ /** Voltage Reference = 2.5 V */
+ MXC_E_AFE_REF_VOLT_SEL_2500
+} mxc_afe_ref_volt_sel_t;
+
+/**
+ * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
+ */
+typedef enum {
+ /** DAC Voltage Reference = REFADC */
+ MXC_E_AFE_DAC_REF_REFADC = 0,
+ /** DAC Voltage Reference = REFDAC */
+ MXC_E_AFE_DAC_REF_REFDAC
+} mxc_afe_dac_ref_t;
+
+/**
+ * @brief Selection for LPC Hysteresis.
+ */
+typedef enum {
+ /** LPC Hysteresis = 0 mV */
+ MXC_E_AFE_HYST_COMP_0 = 0,
+ /** LPC Hysteresis = 7.5 mV */
+ MXC_E_AFE_HYST_COMP_1,
+ /** LPC Hysteresis = 15 mV */
+ MXC_E_AFE_HYST_COMP_2,
+ /** LPC Hysteresis = 30 mV */
+ MXC_E_AFE_HYST_COMP_3
+} mxc_afe_hyst_comp_t;
+
+/**
+ * @brief Selection for MUX for SCM_or_sel.
+ */
+typedef enum {
+ /** SCM_or = HIZ */
+ MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
+ /** SCM_or = SCM0 */
+ MXC_E_AFE_SCM_OR_SEL_SCM0,
+ /** SCM_or = SCM1 */
+ MXC_E_AFE_SCM_OR_SEL_SCM1,
+ /** SCM_or = SCM2 */
+ MXC_E_AFE_SCM_OR_SEL_SCM2,
+ /** SCM_or = SCM3 */
+ MXC_E_AFE_SCM_OR_SEL_SCM3
+} mxc_afe_scm_or_sel_t;
+
+/**
+ * @brief Selection for MUX for SNO_or_sel.
+ */
+typedef enum {
+ /** SNO_or = HIZ */
+ MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
+ /** SNO_or = SNO0 */
+ MXC_E_AFE_SNO_OR_SEL_SNO0,
+ /** SNO_or = SNO1 */
+ MXC_E_AFE_SNO_OR_SEL_SNO1,
+ /** SNO_or = SNO2 */
+ MXC_E_AFE_SNO_OR_SEL_SNO2,
+ /** SNO_or = SNO3 */
+ MXC_E_AFE_SNO_OR_SEL_SNO3
+} mxc_afe_sno_or_sel_t;
+
+/**
+ * @brief Selection for MUX DACx_sel.
+ */
+typedef enum {
+ /** dacx = DACOP */
+ MXC_E_AFE_DACX_SEL_P = 0,
+ /** dacx = DACON */
+ MXC_E_AFE_DACX_SEL_N
+} mxc_afe_dacx_sel_t;
+
+/**
+ * @brief Selection for state of Switch.
+ */
+typedef enum {
+ /** Switch is OPEN */
+ MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
+ /** Switch is CLOSED */
+ MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
+} mxc_afe_close_spst_t;
+
+/**
+ * @brief Switch to Connect Positive Pad to GND.
+ */
+typedef enum {
+ /** Positive Pad GND Switch OPEN */
+ MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
+ /** Positive Pad GND Switch CLOSED */
+ MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
+} mxc_afe_gnd_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpPsel.
+ */
+typedef enum {
+ /** OpPsel = INx+ */
+ MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
+ /** OpPsel = DAC_or */
+ MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
+ /** OpPsel = SNO_or */
+ MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
+ /** OpPsel = DAC_or also output on INx+ */
+ MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
+} mxc_afe_p_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpNsel.
+ */
+typedef enum {
+ /** OpNsel = INx- */
+ MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
+ /** OpNsel = OUTx */
+ MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
+ /** OpNsel = SCM_or */
+ MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
+ /**OpNsel = SCM_or also output on INx- */
+ MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
+} mxc_afe_n_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for DAC_sel.
+ */
+typedef enum {
+ /** DAC_or = DAC0 */
+ MXC_E_AFE_DAC_SEL_DAC0 = 0,
+ /** DAC_or = DAC1 */
+ MXC_E_AFE_DAC_SEL_DAC1,
+ /** DAC_or = DAC2P */
+ MXC_E_AFE_DAC_SEL_DAC2P,
+ /** DAC_or = DAC3P */
+ MXC_E_AFE_DAC_SEL_DAC3P
+} mxc_afe_dac_sel_t;
+
+/**
+ * @brief MUX Selection for NPAD_sel.
+ */
+typedef enum {
+ /** NPAD_Sel = HIZ */
+ MXC_E_AFE_NPAD_SEL_HIZ = 0,
+ /** NPAD_Sel = LED Observe Port */
+ MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
+ /** NPAD_Sel = DAC_or */
+ MXC_E_AFE_NPAD_SEL_DAC_OR,
+ /** NPAD_Sel = DAC_or and LED Observe Port */
+ MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
+} mxc_afe_npad_sel_t;
+
+/**
+ * @brief MUX Selection for CmpPSel.
+ */
+typedef enum {
+ /** CmpPSel = INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
+ /** CmpPSel = SCM */
+ MXC_E_AFE_POS_IN_SEL_COMP_SCM,
+ /** CmpPSel = dac1 */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
+ /** CmpPSel = DAC3P */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
+ /** CmpPSel = LED Observe Port */
+ MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
+ /** CmpPSel = dac1 also output on INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
+ /** CmpPSel = DAC3P also output on INx+ */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
+ /** CmpPSel = dac1 also output on SCM */
+ MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
+} mxc_afe_pos_in_sel_comp_t;
+
+/**
+ * @brief MUX Selection for CmpNSel.
+ */
+typedef enum {
+ /** CmpNSel = INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
+ /** CmpNSel = SNO */
+ MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
+ /** CmpNSel = dac0 */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
+ /** CmpNSel = DAC2P */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
+ /** CmpNSel = LED Observation Port */
+ MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
+ /** CmpNSel = dac0 also output on INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
+ /** CmpNSel = DAC2 also output on INx- */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
+ /** CmpNSel = DAC2 also output on SNO */
+ MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
+} mxc_afe_neg_in_sel_comp_t;
+
+/* Offset Register Description
+ ====== ==================================================== */
+typedef struct {
+ __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */
+ __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */
+ __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */
+ __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */
+ __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */
+ __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */
+ __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */
+} mxc_afe_regs_t;
+
+/*
+ Register offsets for module AFE.
+*/
+#define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL)
+#define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL)
+#define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL)
+#define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL)
+#define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL)
+#define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL)
+#define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL)
+
+/*
+ Field positions and masks for module AFE.
+*/
+#define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0
+#define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1
+#define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2
+#define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3
+#define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4
+#define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5
+#define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6
+#define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7
+#define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16
+#define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17
+#define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18
+#define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19
+#define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20
+#define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21
+#define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22
+#define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23
+#define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24
+#define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25
+#define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26
+#define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27
+#define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28
+#define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29
+#define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30
+#define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31
+#define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
+
+#define MXC_F_AFE_CTRL0_LED_CFG_POS 0
+#define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
+
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_SEL_POS 10
+#define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
+#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23
+#define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
+#define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25
+#define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
+
+#define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0
+#define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2
+#define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4
+#define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6
+#define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16
+#define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17
+#define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18
+#define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19
+#define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26
+#define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27
+#define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
+
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
+
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16
+#define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18
+#define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20
+#define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22
+#define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
+
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP0_POS 24
+#define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP1_POS 25
+#define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP2_POS 26
+#define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP3_POS 27
+#define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_AFE_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h
new file mode 100644
index 000000000..28a258b99
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h
@@ -0,0 +1,493 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file clkman_regs.h
+ * @addtogroup clkman CLKMAN
+ * @{
+ */
+
+/**
+ * @brief Defines clock input selections for the phase locked loop.
+ */
+typedef enum {
+ /** Input select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
+ /** Input select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
+} mxc_clkman_pll_input_select_t;
+
+/**
+ * @brief Defines clock input frequency for the phase locked loop.
+ */
+typedef enum {
+ /** Input frequency of 24MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
+ /** Input frequency of 12MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
+ /** Input frequency of 8MHz */
+ MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
+} mxc_clkman_pll_divisor_select_t;
+
+/**
+ * @brief Defines terminal count for PLL stable.
+ */
+typedef enum {
+ /** Clock stable after 2^8 = 256 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
+ /** Clock stable after 2^9 = 512 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
+ /** Clock stable after 2^10 = 1024 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
+ /** Clock stable after 2^11 = 2048 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
+ /** Clock stable after 2^12 = 4096 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
+ /** Clock stable after 2^13 = 8192 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
+ /** Clock stable after 2^14 = 16384 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
+ /** Clock stable after 2^15 = 32768 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
+ /** Clock stable after 2^16 = 65536 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
+ /** Clock stable after 2^17 = 131072 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
+ /** Clock stable after 2^18 = 262144 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
+ /** Clock stable after 2^19 = 524288 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
+ /** Clock stable after 2^20 = 1048576 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
+ /** Clock stable after 2^21 = 2097152 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
+ /** Clock stable after 2^22 = 4194304 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
+ /** Clock stable after 2^23 = 8388608 clock cycles */
+ MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
+} mxc_clkman_stability_count_t;
+
+/**
+ * @brief Defines clock source selections for system clock.
+ */
+typedef enum {
+ /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
+ /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
+ MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
+} mxc_clkman_system_source_select_t;
+
+/**
+ * @brief Defines clock source selections for analog to digital converter clock.
+ */
+typedef enum {
+ /** Clock select for system clock frequency */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
+ /** Clock select for 8MHz phase locked loop output */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
+} mxc_clkman_adc_source_select_t;
+
+/**
+ * @brief Defines clock source selections for watchdog timer clock.
+ */
+typedef enum {
+ /** Clock select for system clock frequency */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
+ /** Clock select for 8MHz phase locked loop output */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
+ /** Clock select for high frequency crystal oscillator */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
+ /** Clock select for 24MHz ring oscillator */
+ MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
+} mxc_clkman_wdt_source_select_t;
+
+/**
+ * @brief Defines clock scales for various clocks.
+ */
+typedef enum {
+ /** Clock disabled */
+ MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
+ /** Clock enabled */
+ MXC_E_CLKMAN_CLK_SCALE_ENABLED,
+ /** Clock scale for dividing by 2 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_2,
+ /** Clock scale for dividing by 4 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_4,
+ /** Clock scale for dividing by 8 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_8,
+ /** Clock scale for dividing by 16 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_16,
+ /** Clock scale for dividing by 32 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_32,
+ /** Clock scale for dividing by 64 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_64,
+ /** Clock scale for dividing by 128 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_128,
+ /** Clock scale for dividing by 256 */
+ MXC_E_CLKMAN_CLK_SCALE_DIV_256
+} mxc_clkman_clk_scale_t;
+
+/**
+ * @brief Defines Setting of the Clock Gates .
+ */
+typedef enum {
+ /** Clock Gater is Off */
+ MXC_E_CLKMAN_CLK_GATE_OFF = 0,
+ /** Clock Gater is Dynamic */
+ MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
+ /** Clock Gater is On */
+ MXC_E_CLKMAN_CLK_GATE_ON
+} mxc_clkman_clk_gate_t;
+
+/* Offset Register Description
+ ====== ===================================================================== */
+typedef struct {
+ __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
+ __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
+ __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
+ __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
+ __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
+ __I uint32_t rsv0014[4]; /* 0x0014 */
+ __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
+ __I uint32_t rsv0028[6]; /* 0x0028 */
+ __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
+ __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
+ __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
+ __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
+ __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
+ __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
+ __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
+ __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
+ __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
+ __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
+ __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
+ __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
+ __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
+ __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
+ __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
+ __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
+ __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
+ __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
+ __I uint32_t rsv0088[30]; /* 0x0088 */
+ __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
+ __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
+ __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
+ __I uint32_t rsv010C[13]; /* 0x010C */
+ __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
+ __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
+ __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
+} mxc_clkman_regs_t;
+
+/*
+ Register offsets for module CLKMAN.
+*/
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
+
+/*
+ Field positions and masks for module CLKMAN.
+*/
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+
+#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
+#define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
+#define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_CLKMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h
new file mode 100644
index 000000000..8ca978a2f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h
@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "max32610.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c
new file mode 100644
index 000000000..369427304
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c
@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "cmsis_nvic.h"
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
+__attribute__((aligned(256)))
+#endif
+#if defined(TOOLCHAIN_IAR)
+#pragma data_alignment=256
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR != (uint32_t)ramVectorTable) {
+ uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
+ vectors = (uint32_t*)ramVectorTable;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)ramVectorTable;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h
new file mode 100644
index 000000000..d3e544761
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS MXC_IRQ_COUNT
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_CMSIS_NVIC_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h
new file mode 100644
index 000000000..6acec1104
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h
@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CRC_REGS_H_
+#define _MXC_CRC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file crc_regs.h
+ * @addtogroup crc CRC
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t reseed; /* 0x0000 CRC-16/CRC-32 Reseed Controls */
+ __IO uint32_t seed16; /* 0x0004 Reseed Value for CRC-16 Calculations */
+ __IO uint32_t seed32; /* 0x0008 Reseed Value for CRC-32 Calculations */
+} mxc_crc_regs_t;
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t value16[512]; /* 0x0000 Write Next CRC-16 Data Value / Read CRC-16 Result Value */
+ __IO uint32_t value32[512]; /* 0x0800 Write Next CRC-32 Data Value / Read CRC-32 Result Value */
+} mxc_crc_data_regs_t;
+
+/*
+ Register offsets for module CRC.
+*/
+#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL)
+#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module CRC.
+*/
+#define MXC_F_CRC_RESEED_CRC16_POS 0
+#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS))
+#define MXC_F_CRC_RESEED_CRC32_POS 1
+#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_CRC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h
new file mode 100644
index 000000000..2f0f4bd8c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h
@@ -0,0 +1,180 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_DAC_REGS_H
+#define _MXC_DAC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file dac_regs.h
+ * @addtogroup dac DAC
+ * @{
+ */
+
+/**
+ * @brief Defines the DAC Operational Modes.
+ */
+typedef enum {
+ /** DAC OpMode FIFO */
+ MXC_E_DAC_OP_MODE_FIFO = 0,
+ /** DAC OpMode Sample Count */
+ MXC_E_DAC_OP_MODE_DACSMPLCNT,
+ /** DAC OpMode DAC_REG Control */
+ MXC_E_DAC_OP_MODE_DAC_REG,
+ /** DAC OpMode Continuous */
+ MXC_E_DAC_OP_MODE_CONTINUOUS
+} mxc_dac_op_mode_t;
+
+/**
+ * @brief Defines the DAC Interpolation Options.
+ */
+typedef enum {
+ /** DAC Interpolation is Disabled */
+ MXC_E_DAC_INTERP_MODE_DISABLED = 0,
+ /** DAC Interpolation 2:1 */
+ MXC_E_DAC_INTERP_MODE_2_TO_1,
+ /** DAC Interpolation 4:1 */
+ MXC_E_DAC_INTERP_MODE_4_TO_1,
+ /** DAC Interpolation 8:1 */
+ MXC_E_DAC_INTERP_MODE_8_TO_1
+} mxc_dac_interp_mode_t;
+
+/**
+ * @brief Defines the DAC Start Modes.
+ */
+typedef enum {
+ /** Start on FIFO Not Empty */
+ MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
+ /** Start on ADC generated Start Strobe */
+ MXC_E_DAC_START_MODE_ADC_STROBE,
+ /** Start on DAC generated Start Strobe */
+ MXC_E_DAC_START_MODE_DAC_STROBE
+} mxc_dac_start_mode_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */
+ __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */
+ __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */
+ __IO uint32_t reg; /* 0x000C DAC Data Register */
+ __IO uint32_t trm; /* 0x0010 DAC Trim Register */
+} mxc_dac_regs_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ union {
+ __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */
+ __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */
+ };
+} mxc_dac_fifo_t;
+
+/*
+ Register offsets for module DAC12.
+*/
+#define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
+#define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL)
+#define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL)
+#define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL)
+
+/*
+ Field positions and masks for module DAC.
+*/
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8
+#define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
+#define MXC_F_DAC_CTRL0_START_MODE_POS 16
+#define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
+#define MXC_F_DAC_CTRL0_CPU_START_POS 20
+#define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
+#define MXC_F_DAC_CTRL0_OP_MODE_POS 24
+#define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
+#define MXC_F_DAC_CTRL0_POWER_ON_POS 28
+#define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30
+#define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
+#define MXC_F_DAC_CTRL0_RESET_POS 31
+#define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
+
+#define MXC_F_DAC_RATE_RATE_CNT_POS 0
+#define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
+#define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16
+#define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
+
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _DAC12_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h
new file mode 100644
index 000000000..864c8c9b9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h
@@ -0,0 +1,210 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_FLC_REGS_H
+#define _MXC_FLC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file flc_regs.h
+ * @addtogroup flc FLC
+ * @{
+ */
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
+ __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
+ __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
+ __I uint32_t rsv000C[6]; /* 0x000C */
+ __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __I uint32_t rsv0028[2]; /* 0x0028 */
+ __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
+ __I uint32_t rsv0034[7]; /* 0x0034 */
+ __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
+ __I uint32_t rsv0054[11]; /* 0x0054 */
+ __IO uint32_t status; /* 0x0080 Security Status Flags */
+ __I uint32_t rsv0084; /* 0x0084 */
+ __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
+ __I uint32_t rsv008C[4]; /* 0x008C */
+ __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
+ __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
+ __I uint32_t rsv0104[15]; /* 0x0104 */
+ __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
+ __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
+ __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
+ __I uint32_t rsv014C; /* 0x014C */
+ __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
+} mxc_flc_regs_t;
+
+/*
+ Register offsets for module FLC.
+*/
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
+
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
+
+/*
+ Field positions and masks for module FLC.
+*/
+#define MXC_F_FLC_FADDR_FADDR_POS 0
+#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
+
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
+#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
+
+#define MXC_F_FLC_CTRL_WRITE_POS 0
+#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
+#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
+#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
+#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
+#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
+#define MXC_F_FLC_CTRL_PENDING_POS 24
+#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
+
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
+
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
+
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
+#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
+
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
+
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
+
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
+#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
+
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
+
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_FLC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h
new file mode 100644
index 000000000..8a8122d8c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h
@@ -0,0 +1,477 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file gpio_regs.h
+ * @addtogroup gpio GPIO
+ * @{
+ */
+
+/* Offset Register Description
+ ============= ========================================== */
+typedef struct {
+ __I uint32_t rsv000[16]; /* 0x0000-0x003C */
+
+ __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */
+ __I uint32_t rsv060[8]; /* 0x0060-0x007C */
+
+ __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */
+ __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */
+
+ __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */
+ __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */
+
+ __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */
+ __I uint32_t rsv120[8]; /* 0x0120-0x013C */
+
+ __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */
+ __I uint32_t rsv160[8]; /* 0x0160-0x017C */
+
+ __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */
+ __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */
+
+ __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */
+ __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */
+
+ __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */
+ __I uint32_t rsv220[8]; /* 0x0220-0x023C */
+
+ __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */
+} mxc_gpio_regs_t;
+
+/*
+ Register offsets for module GPIO.
+*/
+#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
+#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
+#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
+#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
+#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
+#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
+#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
+#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL)
+#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
+#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
+#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
+#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
+#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
+#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
+#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
+#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
+#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
+#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
+#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
+#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
+#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL)
+
+
+/*
+ Field positions and masks for module GPIO.
+*/
+#define MXC_F_GPIO_FREE_PIN0_POS 0
+#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_F_GPIO_FREE_PIN1_POS 1
+#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_F_GPIO_FREE_PIN2_POS 2
+#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_F_GPIO_FREE_PIN3_POS 3
+#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_F_GPIO_FREE_PIN4_POS 4
+#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_F_GPIO_FREE_PIN5_POS 5
+#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_F_GPIO_FREE_PIN6_POS 6
+#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_F_GPIO_FREE_PIN7_POS 7
+#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
+#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
+#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
+#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
+#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
+#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
+#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
+#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
+#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0
+#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4
+#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8
+#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12
+#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16
+#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20
+#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24
+#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28
+#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
+
+#define MXC_F_GPIO_IN_MODE_PIN0_POS 0
+#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
+#define MXC_F_GPIO_IN_MODE_PIN1_POS 4
+#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
+#define MXC_F_GPIO_IN_MODE_PIN2_POS 8
+#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
+#define MXC_F_GPIO_IN_MODE_PIN3_POS 12
+#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
+#define MXC_F_GPIO_IN_MODE_PIN4_POS 16
+#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
+#define MXC_F_GPIO_IN_MODE_PIN5_POS 20
+#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
+#define MXC_F_GPIO_IN_MODE_PIN6_POS 24
+#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
+#define MXC_F_GPIO_IN_MODE_PIN7_POS 28
+#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_IN_VAL_PIN0_POS 0
+#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
+#define MXC_F_GPIO_IN_VAL_PIN1_POS 1
+#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
+#define MXC_F_GPIO_IN_VAL_PIN2_POS 2
+#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
+#define MXC_F_GPIO_IN_VAL_PIN3_POS 3
+#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
+#define MXC_F_GPIO_IN_VAL_PIN4_POS 4
+#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
+#define MXC_F_GPIO_IN_VAL_PIN5_POS 5
+#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
+#define MXC_F_GPIO_IN_VAL_PIN6_POS 6
+#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
+#define MXC_F_GPIO_IN_VAL_PIN7_POS 7
+#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_INT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
+#define MXC_F_GPIO_INT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
+#define MXC_F_GPIO_INT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
+#define MXC_F_GPIO_INT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
+#define MXC_F_GPIO_INT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
+#define MXC_F_GPIO_INT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
+#define MXC_F_GPIO_INT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
+#define MXC_F_GPIO_INT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_INTFL_PIN0_POS 0
+#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
+#define MXC_F_GPIO_INTFL_PIN1_POS 1
+#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
+#define MXC_F_GPIO_INTFL_PIN2_POS 2
+#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
+#define MXC_F_GPIO_INTFL_PIN3_POS 3
+#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
+#define MXC_F_GPIO_INTFL_PIN4_POS 4
+#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
+#define MXC_F_GPIO_INTFL_PIN5_POS 5
+#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
+#define MXC_F_GPIO_INTFL_PIN6_POS 6
+#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
+#define MXC_F_GPIO_INTFL_PIN7_POS 7
+#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
+
+#define MXC_F_GPIO_INTEN_PIN0_POS 0
+#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
+#define MXC_F_GPIO_INTEN_PIN1_POS 1
+#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
+#define MXC_F_GPIO_INTEN_PIN2_POS 2
+#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
+#define MXC_F_GPIO_INTEN_PIN3_POS 3
+#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
+#define MXC_F_GPIO_INTEN_PIN4_POS 4
+#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
+#define MXC_F_GPIO_INTEN_PIN5_POS 5
+#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
+#define MXC_F_GPIO_INTEN_PIN6_POS 6
+#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
+#define MXC_F_GPIO_INTEN_PIN7_POS 7
+#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
+
+
+/*
+ Field values and shifted values for module GPIO.
+*/
+#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
+
+#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
+
+#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
+
+#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
+
+#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
+
+#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
+
+#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
+
+#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
+#define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
+
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_GPIO_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h
new file mode 100644
index 000000000..173d3107a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h
@@ -0,0 +1,192 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_I2CM_REGS_H_
+#define _MXC_I2CM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file i2cm_regs.h
+ * @addtogroup i2cm I2CM
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */
+ __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */
+ __I uint32_t rsv0008; /* 0x0008 */
+ __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */
+ __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */
+ __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */
+ __IO uint32_t intfl; /* 0x0018 Interrupt Flags */
+ __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */
+ __I uint32_t rsv0020[2]; /* 0x0020 */
+ __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */
+} mxc_i2cm_regs_t;
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */
+ __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */
+} mxc_i2cm_fifo_regs_t;
+
+/*
+ Register offsets for module I2CM.
+*/
+#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL)
+#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
+#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
+#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
+#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
+#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
+#define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL)
+
+#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module I2CM.
+*/
+#define MXC_S_I2CM_TRANS_TAG_START 0x000
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
+#define MXC_S_I2CM_TRANS_TAG_STOP 0x700
+#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
+#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
+
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
+
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
+
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
+
+#define MXC_F_I2CM_TRANS_TX_START_POS 0
+#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
+#define MXC_F_I2CM_TRANS_TX_DONE_POS 2
+#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
+#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
+#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
+
+#define MXC_F_I2CM_INTFL_TX_DONE_POS 0
+#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
+#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
+#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_INTEN_TX_DONE_POS 0
+#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
+#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
+#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
+#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
+#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
+#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
+#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h
new file mode 100644
index 000000000..c8407a843
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file icc_regs.h
+ * @addtogroup icc ICC
+ * @{
+ */
+
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ __IO uint32_t id; /* 0x0000 Device ID Register */
+ __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */
+ __I uint32_t rsv0008[62]; /* 0x0008 */
+ __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */
+ __I uint32_t rsv0104[383]; /* 0x0104 */
+ __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */
+} mxc_icc_regs_t;
+
+/*
+ Register offsets for module ICC.
+*/
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL)
+
+/*
+ Field positions and masks for module ICC.
+*/
+#define MXC_F_ICC_ID_RTL_VERSION_POS 0
+#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
+#define MXC_F_ICC_ID_PART_NUM_POS 6
+#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
+#define MXC_F_ICC_ID_CACHE_ID_POS 10
+#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
+
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
+
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0
+#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
+#define MXC_F_ICC_CTRL_STAT_READY_POS 16
+#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_ICC_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h
new file mode 100644
index 000000000..930a18159
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h
@@ -0,0 +1,508 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file ioman_regs.h
+ * @addtogroup ioman IO MUX Manager
+ * @{
+ */
+
+typedef enum {
+ /** Pin Mapping 'A' */
+ MXC_E_IOMAN_MAPPING_A = 0,
+ /** Pin Mapping 'B' */
+ MXC_E_IOMAN_MAPPING_B,
+ /** Pin Mapping 'C' */
+ MXC_E_IOMAN_MAPPING_C,
+ /** Pin Mapping 'D' */
+ MXC_E_IOMAN_MAPPING_D,
+ /** Pin Mapping 'E' */
+ MXC_E_IOMAN_MAPPING_E,
+ /** Pin Mapping 'F' */
+ MXC_E_IOMAN_MAPPING_F,
+ /** Pin Mapping 'G' */
+ MXC_E_IOMAN_MAPPING_G,
+ /** Pin Mapping 'H' */
+ MXC_E_IOMAN_MAPPING_H,
+} ioman_mapping_t;
+
+/* Offset Register Description
+ ====== ========================================== */
+typedef struct {
+ __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
+ __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
+ __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
+ __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
+ __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
+ __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
+ __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
+ __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
+ __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
+ __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
+ __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
+ __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
+ __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
+ __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
+ __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
+ __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
+ __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
+ __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
+ __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
+ __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
+ __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
+ __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
+ __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
+ __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
+ __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
+ __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
+ __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
+ __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
+ __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
+ __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
+ __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
+ __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
+ __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
+ __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
+ __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
+ __IO uint32_t padx_control; /* 0x008C PADX Control */
+} mxc_ioman_regs_t;
+
+
+/*
+ Register offsets for module IOMAN.
+*/
+#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
+#define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
+#define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
+
+
+/*
+ Field positions and masks for module IOMAN.
+*/
+#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
+#define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
+#define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
+#define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
+#define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
+#define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
+#define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
+#define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
+#define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
+#define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
+#define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
+#define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
+#define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
+#define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
+#define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
+#define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
+#define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
+#define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
+#define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
+#define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
+#define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
+#define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
+#define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
+#define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
+#define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
+#define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
+#define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
+#define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
+#define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
+#define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
+#define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
+#define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
+#define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_SPI_MAPPING_POS 0
+#define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
+#define MXC_F_IOMAN_SPI_CORE_IO_POS 4
+#define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
+#define MXC_F_IOMAN_SPI_SS0_IO_POS 8
+#define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
+#define MXC_F_IOMAN_SPI_SS1_IO_POS 9
+#define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
+#define MXC_F_IOMAN_SPI_SS2_IO_POS 10
+#define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
+#define MXC_F_IOMAN_SPI_SS3_IO_POS 11
+#define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
+#define MXC_F_IOMAN_SPI_SS4_IO_POS 12
+#define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
+#define MXC_F_IOMAN_SPI_SR0_IO_POS 16
+#define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
+#define MXC_F_IOMAN_SPI_SR1_IO_POS 17
+#define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
+#define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
+#define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
+#define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART_MAPPING_POS 0
+#define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
+#define MXC_F_IOMAN_UART_CORE_IO_POS 4
+#define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
+#define MXC_F_IOMAN_UART_CTS_IO_POS 5
+#define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
+#define MXC_F_IOMAN_UART_RTS_IO_POS 6
+#define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
+
+#define MXC_F_IOMAN_I2CM_MAPPING_POS 0
+#define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
+#define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
+#define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
+
+#define MXC_F_IOMAN_I2CS_MAPPING_POS 0
+#define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
+#define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
+#define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
+
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
+
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_IOMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h
new file mode 100644
index 000000000..e8c80c712
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h
@@ -0,0 +1,124 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_MAA_REGS_H_
+#define _MXC_MAA_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file maa_regs.h
+ * @addtogroup maa MAA
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ========================================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 MAA Control, Configuration and Status */
+ __IO uint32_t maws; /* 0x0004 MAA Word (Operand) Size, Big/Little Endian Mode Select */
+} mxc_maa_regs_t;
+
+/* Offset Register Description
+ ====== ========================================================== */
+typedef struct {
+ __IO uint32_t seg0[16]; /* 0x0000 [64 bytes] MAA Memory Segment 0 */
+ __IO uint32_t seg1[16]; /* 0x0040 [64 bytes] MAA Memory Segment 1 */
+ __IO uint32_t seg2[16]; /* 0x0080 [64 bytes] MAA Memory Segment 2 */
+ __IO uint32_t seg3[16]; /* 0x00C0 [64 bytes] MAA Memory Segment 3 */
+ __IO uint32_t seg4[16]; /* 0x0100 [64 bytes] MAA Memory Segment 4 */
+ __IO uint32_t seg5[16]; /* 0x0140 [64 bytes] MAA Memory Segment 5 */
+} mxc_maa_mem_regs_t;
+
+/*
+ Register offsets for module MAA.
+*/
+#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL)
+#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000040UL)
+#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000080UL)
+#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x000000C0UL)
+#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000100UL)
+#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000140UL)
+
+/*
+ Field positions and masks for module MAA.
+*/
+#define MXC_F_MAA_CTRL_START_POS 0
+#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS))
+#define MXC_F_MAA_CTRL_OPSEL_POS 1
+#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS))
+#define MXC_F_MAA_CTRL_OCALC_POS 4
+#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS))
+#define MXC_F_MAA_CTRL_INTEN_POS 5
+#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS))
+#define MXC_F_MAA_CTRL_IF_DONE_POS 6
+#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS))
+#define MXC_F_MAA_CTRL_IF_ERROR_POS 7
+#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS))
+#define MXC_F_MAA_CTRL_OFS_A_POS 8
+#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS))
+#define MXC_F_MAA_CTRL_OFS_B_POS 10
+#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS))
+#define MXC_F_MAA_CTRL_OFS_EXP_POS 12
+#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS))
+#define MXC_F_MAA_CTRL_OFS_MOD_POS 14
+#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS))
+#define MXC_F_MAA_CTRL_SEG_A_POS 16
+#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS))
+#define MXC_F_MAA_CTRL_SEG_B_POS 20
+#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS))
+#define MXC_F_MAA_CTRL_SEG_RES_POS 24
+#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS))
+#define MXC_F_MAA_CTRL_SEG_TMP_POS 28
+#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS))
+
+#define MXC_F_MAA_MAWS_MODLEN_POS 0
+#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS))
+#define MXC_F_MAA_MAWS_BYTESWAP_POS 16
+#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_MAA_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h
new file mode 100644
index 000000000..182a9078f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h
@@ -0,0 +1,655 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX32610_H_
+#define _MAX32610_H_
+
+#include <stdint.h>
+
+typedef enum IRQn_Type {
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+ /* Externals interrupts */
+ UART0_IRQn = 0, /* 16:01 UART0 */
+ UART1_IRQn, /* 17: 2 UART1 */
+ I2CM0_IRQn, /* 18: 3 I2C Master 0 */
+ I2CS_IRQn, /* 19: 4 I2C Slave */
+ USB_IRQn, /* 20: 5 USB */
+ PMU_IRQn, /* 21: 6 DMA */
+ AFE_IRQn, /* 22: 7 AFE */
+ MAA_IRQn, /* 23: 8 MAA */
+ AES_IRQn, /* 24: 9 AES */
+ SPI0_IRQn, /* 25:10 SPI0 */
+ SPI1_IRQn, /* 26:11 SPI1 */
+ SPI2_IRQn, /* 27:12 SPI2 */
+ TMR0_IRQn, /* 28:13 Timer32-0 */
+ TMR1_IRQn, /* 29:14 Timer32-1 */
+ TMR2_IRQn, /* 30:15 Timer32-1 */
+ TMR3_IRQn, /* 31:16 Timer32-2 */
+ RSVD0_IRQn, /* 32:17 RSVD */
+ RSVD1_IRQn, /* 33:18 RSVD */
+ DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
+ DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
+ DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
+ DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
+ ADC_IRQn, /* 38:23 ADC */
+ FLC_IRQn, /* 39:24 Flash Controller */
+ PWRMAN_IRQn, /* 40:25 PWRMAN */
+ CLKMAN_IRQn, /* 41:26 CLKMAN */
+ RTC0_IRQn, /* 42:27 RTC INT0 */
+ RTC1_IRQn, /* 43:28 RTC INT1 */
+ RTC2_IRQn, /* 44:29 RTC INT2 */
+ RTC3_IRQn, /* 45:30 RTC INT3 */
+ WDT0_IRQn, /* 46:31 WATCHDOG0 */
+ WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
+ WDT1_IRQn, /* 48:33 WATCHDOG1 */
+ WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
+ GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
+ GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
+ GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
+ GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
+ GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
+ GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
+ GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
+ GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
+ TMR16_0_IRQn, /* 58:43 Timer16-s0 */
+ TMR16_1_IRQn, /* 59:44 Timer16-s1 */
+ TMR16_2_IRQn, /* 60:45 Timer16-s2 */
+ TMR16_3_IRQn, /* 61:46 Timer16-s3 */
+ I2CM1_IRQn, /* 62:47 I2C Master 1 */
+ MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+
+#include <core_cm3.h> /* Processor and core peripherals */
+#include "system_max32610.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================== Device Specific Memory Section ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE 0x00000000UL
+#define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
+#define MXC_FLASH_MEM_SIZE 0x00040000UL
+#define MXC_SYS_MEM_BASE 0x20000000UL
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/*******************************************************************************/
+/* General Purpose I/O Ports (GPIO) */
+
+
+#define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
+
+#define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
+
+
+/*******************************************************************************/
+/* Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES (13)
+
+#define MXC_BASE_PTG ((uint32_t)0x40001000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT ((uint32_t)0x40001008UL)
+#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
+#define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+
+/* PT12, PT13, PT14 are not used */
+
+/*******************************************************************************/
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40010000UL)
+#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
+
+#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40011000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40011400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+
+#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+
+/*******************************************************************************/
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40011800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+
+#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/* 32-Bit PWM Timer/Counter */
+
+#define MXC_CFG_TMR_INSTANCES (4)
+
+#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
+#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
+#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
+
+#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
+#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
+#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
+
+#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
+#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
+#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
+
+#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
+#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
+#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
+
+
+#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : \
+ (i) == 4 ? TMR16_0_IRQn : \
+ (i) == 5 ? TMR16_1_IRQn : \
+ (i) == 6 ? TMR16_2_IRQn : \
+ (i) == 7 ? TMR16_3_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : 0)
+
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : 0)
+/*******************************************************************************/
+/* Watchdog Timer */
+
+#define MXC_CFG_WDT_INSTANCES (2)
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
+#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+
+#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
+#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+
+/*******************************************************************************/
+/* SPI Interface */
+
+#define MXC_CFG_SPI_INSTANCES (3)
+#define MXC_CFG_SPI_FIFO_DEPTH (16)
+
+#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
+#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
+
+#define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
+#define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
+#define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
+#define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
+
+#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
+#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
+
+#define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
+#define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
+#define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
+#define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
+
+#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
+#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
+
+#define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
+#define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
+#define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
+#define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
+
+
+#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
+ (i) == 1 ? SPI1_IRQn : \
+ (i) == 2 ? SPI2_IRQn : 0)
+
+#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
+ (i) == 1 ? MXC_BASE_SPI1 : \
+ (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
+ (i) == 1 ? MXC_SPI1 : \
+ (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
+ (i) == 1 ? MXC_SPI1_RXFIFO : \
+ (i) == 2 ? MXC_SPI2_RXFIFO : 0)
+
+#define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
+ (i) == 1 ? MXC_SPI1_TXFIFO : \
+ (i) == 2 ? MXC_SPI2_TXFIFO : 0)
+
+#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
+#define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
+
+
+/*******************************************************************************/
+/* UART Interface */
+
+#define MXC_CFG_UART_INSTANCES (2)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
+#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+
+#define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
+#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
+
+
+#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
+#define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
+
+
+/*******************************************************************************/
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (2)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
+#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
+#define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
+
+#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
+#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
+#define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
+
+#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
+
+#define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
+
+#define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
+#define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
+
+
+/*******************************************************************************/
+/* I2C Slave Interface */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+
+#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
+#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
+#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
+
+#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
+#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
+
+
+
+/*******************************************************************************/
+/* DACs */
+
+#define MXC_CFG_DAC_INSTANCES (4)
+#define MXC_CFG_DAC_FIFO_DEPTH (32)
+
+#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
+#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
+#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
+#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
+#define MXC_DAC0_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
+#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
+#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
+#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
+#define MXC_DAC1_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
+#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
+#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
+#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
+#define MXC_DAC2_WIDTH ((uint8_t)(1))
+
+#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
+#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
+#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
+#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
+#define MXC_DAC3_WIDTH ((uint8_t)(1))
+
+
+#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
+ (i) == 1 ? DAC1_IRQn : \
+ (i) == 2 ? DAC2_IRQn : \
+ (i) == 3 ? DAC3_IRQn : 0)
+
+
+#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
+ i == 1 ? MXC_BASE_DAC1 : \
+ i == 2 ? MXC_BASE_DAC2 : \
+ i == 3 ? MXC_BASE_DAC3 : 0)
+
+#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
+ i == 1 ? MXC_BASE_DAC1_FIFO : \
+ i == 2 ? MXC_BASE_DAC2_FIFO : \
+ i == 3 ? MXC_BASE_DAC3_FIFO : 0)
+
+#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
+ i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
+ i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
+ i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
+
+#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
+ i == 1 ? MXC_DAC1 : \
+ i == 2 ? MXC_DAC2 : \
+ i == 3 ? MXC_DAC3 : 0)
+
+#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
+ i == 1 ? MXC_DAC1_WIDTH : \
+ i == 2 ? MXC_DAC2_WIDTH : \
+ i == 3 ? MXC_DAC3_WIDTH : 0)
+
+
+/*******************************************************************************/
+/* Analog Front End */
+
+#define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
+#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
+
+
+
+/*******************************************************************************/
+/* ADC */
+
+#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
+
+#define MXC_BASE_ADC ((uint32_t)0x40054000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
+#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
+
+#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
+#define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
+
+
+
+/*******************************************************************************/
+/* Peripheral Management Unit (PMU) - formerly DMA Controller */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
+#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
+/*******************************************************************************/
+
+typedef enum {
+ PMU_IRQ_DAC0_FIFO_AE,
+ PMU_IRQ_DAC1_FIFO_AE,
+ PMU_IRQ_DAC2_FIFO_AE,
+ PMU_IRQ_DAC3_FIFO_AE,
+ PMU_IRQ_DAC0_DONE,
+ PMU_IRQ_DAC1_DONE,
+ PMU_IRQ_DAC2_DONE,
+ PMU_IRQ_DAC3_DONE,
+ PMU_IRQ_ADC_FIFO_AF,
+ PMU_IRQ_ADC_DONE,
+ PMU_IRQ_I2C_MST0_DONE,
+ PMU_IRQ_I2C_MST1_DONE,
+ PMU_IRQ_SPI0_RSLTS_DONE,
+ PMU_IRQ_SPI1_RSLTS_DONE,
+ PMU_IRQ_SPI2_RSLTS_DONE,
+ PMU_IRQ_MAA_DONE,
+ PMU_IRQ_SPI0_TX_FIFO_AE,
+ PMU_IRQ_SPI0_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI1_TX_FIFO_AE,
+ PMU_IRQ_SPI1_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI2_TX_FIFO_AE,
+ PMU_IRQ_SPI3_RSLTS_FIFO_AF,
+ PMU_IRQ_I2C_MST0_TRANS_FIFO,
+ PMU_IRQ_I2C_MST0_RSLT_FIFO,
+ PMU_IRQ_I2C_MST1_TRANS_FIFO,
+ PMU_IRQ_I2C_MST2_RSLT_FIFO,
+ PMU_IRQ_I2C_SLV_TRANS_FIFO,
+ PMU_IRQ_I2C_SLV_RSLT_FIFO,
+ PMU_IRQ_UART0_TX_FIFO,
+ PMU_IRQ_UART0_RX_FIFO,
+ PMU_IRQ_UART1_TX_FIFO,
+ PMU_IRQ_UART1_RX_FIFO,
+ PMU_IRQ_SPI0_EXCP,
+ PMU_IRQ_SPI1_EXCP,
+ PMU_IRQ_SPI2_EXCP,
+ PMU_IRQ_RSVD0,
+ PMU_IRQ_I2C_MST0_EXCP,
+ PMU_IRQ_I2C_MST1_EXCP,
+ PMU_IRQ_I2C_SLV_EXCP,
+ PMU_IRQ_RSVD1,
+ PMU_IRQ_GPIO0,
+ PMU_IRQ_GPIO1,
+ PMU_IRQ_GPIO2,
+ PMU_IRQ_GPIO3,
+ PMU_IRQ_GPIO4,
+ PMU_IRQ_GPIO5,
+ PMU_IRQ_GPIO6,
+ PMU_IRQ_GPIO7,
+ PMU_IRQ_GPIO8,
+ PMU_IRQ_AFE_COMP_NMI,
+ PMU_IRQ_AES_ENGINE,
+} pmu_int_mask_t;
+
+/*******************************************************************************/
+/* USB */
+
+#define MXC_BASE_USB ((uint32_t)0x4010C000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+/*******************************************************************************/
+/* Instruction Cache Controller */
+
+#define MXC_BASE_ICC ((uint32_t)0x40080000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+/* System Manager */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
+
+/*******************************************************************************/
+/* Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+/*******************************************************************************/
+/* Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+/*******************************************************************************/
+/* I/O Manager */
+
+#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+/*******************************************************************************/
+/* RTC: Timer/Alarms */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+
+#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
+ i == 1 ? RTC1_IRQn : \
+ i == 2 ? RTC2_IRQn : \
+ i == 3 ? RTC3_IRQn : 0)
+
+#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+/*******************************************************************************/
+/* RTC: Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+/*******************************************************************************/
+/* Trim Shadow Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
+#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
+
+/*******************************************************************************/
+/* Flash Memory Controller / Security */
+
+#define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
+#define MXC_FLC_PAGE_SIZE_SHIFT 11
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+/*******************************************************************************/
+
+#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
+#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
+#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+/*******************************************************************************/
+
+#endif /* _MAX32610_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h
new file mode 100644
index 000000000..e36b9b04e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h
@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PMU_REGS_H_
+#define _MXC_PMU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pmu_regs.h
+ * @addtogroup pmu PMU
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ======================================================== */
+typedef struct {
+ __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */
+ __IO uint32_t cfg; /* 0x0004 Channel Configuration */
+ __IO uint32_t loop; /* 0x0008 Channel Loop Counters */
+ __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */
+ __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */
+ __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */
+ __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */
+ __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */
+} mxc_pmu_regs_t;
+
+/*
+ Register offsets for module PMU.
+*/
+#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
+#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
+#define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL)
+#define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL)
+#define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL)
+#define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL)
+#define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL)
+
+/*
+ Field positions and masks for module PMU.
+*/
+#define MXC_F_PMU_CFG_ENABLE_POS 0
+#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
+#define MXC_F_PMU_CFG_LL_STOPPED_POS 2
+#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
+#define MXC_F_PMU_CFG_MANUAL_POS 3
+#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
+#define MXC_F_PMU_CFG_BUS_ERROR_POS 4
+#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
+#define MXC_F_PMU_CFG_TO_STAT_POS 6
+#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
+#define MXC_F_PMU_CFG_TO_SEL_POS 11
+#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
+#define MXC_F_PMU_CFG_PS_SEL_POS 14
+#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
+#define MXC_F_PMU_CFG_INTERRUPT_POS 16
+#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
+#define MXC_F_PMU_CFG_INT_EN_POS 17
+#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
+#define MXC_F_PMU_CFG_BURST_SIZE_POS 24
+#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
+
+#define MXC_F_PMU_LOOP_COUNTER_0_POS 0
+#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
+#define MXC_F_PMU_LOOP_COUNTER_1_POS 16
+#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PMU_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h
new file mode 100644
index 000000000..53936e390
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h
@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PT_REGS_H_
+#define _MXC_PT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pt_regs.h
+ * @addtogroup pt PT
+ * @{
+ */
+
+typedef struct {
+ __IO uint32_t ctrl;
+ __IO uint32_t resync;
+} mxc_ptg_regs_t;
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __IO uint32_t rate_length; /* 0x0000 Pulse train Output length and rate */
+ __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */
+} mxc_pt_regs_t;
+
+/*
+ Register offsets for module PT.
+*/
+#define MXC_R_PTG_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL)
+#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL)
+#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL)
+
+
+/*
+ Field positions and masks for module PT.
+*/
+#define MXC_F_PT_CTRL_ENABLE_ALL_POS 1
+#define MXC_F_PT_CTRL_ENABLE_ALL ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS))
+
+#define MXC_F_PT_RESYNC_PT0_POS 0
+#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS))
+#define MXC_F_PT_RESYNC_PT1_POS 1
+#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS))
+#define MXC_F_PT_RESYNC_PT2_POS 2
+#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS))
+#define MXC_F_PT_RESYNC_PT3_POS 3
+#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS))
+#define MXC_F_PT_RESYNC_PT4_POS 4
+#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS))
+#define MXC_F_PT_RESYNC_PT5_POS 5
+#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS))
+#define MXC_F_PT_RESYNC_PT6_POS 6
+#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS))
+#define MXC_F_PT_RESYNC_PT7_POS 7
+#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS))
+
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS))
+#define MXC_F_PT_RATE_LENGTH_MODE_POS 27
+#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+/*
+ Field values and shifted values for module PT.
+*/
+#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(0x0x00000000UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x0x00000001UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(0x0x00000002UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(0x0x00000003UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(0x0x00000004UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(0x0x00000005UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(0x0x00000006UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(0x0x00000007UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(0x0x00000008UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(0x0x00000009UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(0x0x00000010UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(0x0x00000011UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(0x0x00000012UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(0x0x00000013UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(0x0x00000014UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(0x0x00000015UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(0x0x00000016UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(0x0x00000017UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(0x0x00000018UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(0x0x00000019UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(0x0x00000020UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(0x0x00000021UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(0x0x00000022UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(0x0x00000023UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(0x0x00000024UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(0x0x00000025UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(0x0x00000026UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(0x0x00000027UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(0x0x00000028UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(0x0x00000029UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(0x0x00000030UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(0x0x00000031UL))
+
+#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PT_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h
new file mode 100644
index 000000000..cc717dd65
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h
@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pwrman_regs.h
+ * @addtogroup pwrman PWRMAN
+ * @{
+ */
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+ /** WUD Mode for Selected PAD = Clear/Activate */
+ MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+ /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+ MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+ /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+ MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+ /** WUD Mode for Selected PAD = No pad state change */
+ MXC_E_PWRMAN_PAD_MODE_NONE
+} mxc_pwrman_pad_mode_t;
+
+/* Offset Register Description
+ ====== =========================================== */
+typedef struct {
+ __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
+ __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
+ __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
+ __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
+ __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
+ __I uint32_t rsv001C[5]; /* 0x001C */
+
+ __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */
+ __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */
+ __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */
+ __IO uint32_t base_part_num; /* 0x003C Base Part Number */
+ __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
+ __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
+ __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
+} mxc_pwrman_regs_t;
+
+/*
+ Register offsets for module PWRMAN.
+*/
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
+
+/*
+ Field positions and masks for module PWRMAN.
+*/
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRMAN_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h
new file mode 100644
index 000000000..506b11bda
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h
@@ -0,0 +1,299 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRSEQ_REGS_H
+#define _MXC_PWRSEQ_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file pwrseq_regs.h
+ * @addtogroup pwrseq PWRSEQ
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================= */
+typedef struct {
+ __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
+ __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
+ __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
+ __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
+ __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
+ __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
+ __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
+ __I uint32_t rsv001C; /* 0x001C */
+ __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
+ __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
+} mxc_pwrseq_regs_t;
+
+
+/*
+ Register offsets for module PWRSEQ.
+*/
+#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
+
+
+/*
+ Field positions and masks for module PWRSEQ.
+*/
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
+#define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
+#define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
+#define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRSEQ_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h
new file mode 100644
index 000000000..3c947b028
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h
@@ -0,0 +1,246 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_RTC_REGS_H
+#define _MXC_RTC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file rtc_regs.h
+ * @addtogroup rtc RTCTMR
+ * @{
+ */
+
+/**
+ * @brief Defines clock divider for 4096Hz input clock.
+ */
+typedef enum {
+ /** (4kHz) divide input clock by 2^0 = 1 */
+ MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
+ /** (2kHz) divide input clock by 2^1 = 2 */
+ MXC_E_RTC_PRESCALE_DIV_2_1,
+ /** (1kHz) divide input clock by 2^2 = 4 */
+ MXC_E_RTC_PRESCALE_DIV_2_2,
+ /** (512Hz) divide input clock by 2^3 = 8 */
+ MXC_E_RTC_PRESCALE_DIV_2_3,
+ /** (256Hz) divide input clock by 2^4 = 16 */
+ MXC_E_RTC_PRESCALE_DIV_2_4,
+ /** (128Hz) divide input clock by 2^5 = 32 */
+ MXC_E_RTC_PRESCALE_DIV_2_5,
+ /** (64Hz) divide input clock by 2^6 = 64 */
+ MXC_E_RTC_PRESCALE_DIV_2_6,
+ /** (32Hz) divide input clock by 2^7 = 128 */
+ MXC_E_RTC_PRESCALE_DIV_2_7,
+ /** (16Hz) divide input clock by 2^8 = 256 */
+ MXC_E_RTC_PRESCALE_DIV_2_8,
+ /** (8Hz) divide input clock by 2^9 = 512 */
+ MXC_E_RTC_PRESCALE_DIV_2_9,
+ /** (4Hz) divide input clock by 2^10 = 1024 */
+ MXC_E_RTC_PRESCALE_DIV_2_10,
+ /** (2Hz) divide input clock by 2^11 = 2048 */
+ MXC_E_RTC_PRESCALE_DIV_2_11,
+ /** (1Hz) divide input clock by 2^12 = 4096 */
+ MXC_E_RTC_PRESCALE_DIV_2_12,
+} mxc_rtc_prescale_t;
+
+/* Offset Register Description
+ ====== ========================================= */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
+ __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
+ __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
+ __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
+ __I uint32_t rsv0014; /* 0x0014 */
+ __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
+ __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
+ __I uint32_t rsv0020; /* 0x0020 */
+ __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
+ __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
+ __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
+} mxc_rtctmr_regs_t;
+
+/*
+ Register offsets for module RTCTMR.
+*/
+#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
+#define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
+#define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
+#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
+#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
+
+/*
+ Field positions and masks for module RTCTMR.
+*/
+#define MXC_F_RTC_CTRL_ENABLE_POS 0
+#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
+#define MXC_F_RTC_CTRL_CLEAR_POS 1
+#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
+#define MXC_F_RTC_CTRL_PENDING_POS 2
+#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
+#define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
+#define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
+#define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
+#define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
+
+#define MXC_F_RTC_FLAGS_COMP0_POS 0
+#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
+#define MXC_F_RTC_FLAGS_COMP1_POS 1
+#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
+#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
+#define MXC_F_RTC_FLAGS_TRIM_POS 4
+#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
+
+#define MXC_F_RTC_INTEN_COMP0_POS 0
+#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
+#define MXC_F_RTC_INTEN_COMP1_POS 1
+#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
+#define MXC_F_RTC_INTEN_OVERFLOW_POS 3
+#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
+#define MXC_F_RTC_INTEN_TRIM_POS 4
+#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
+
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
+
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
+
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
+
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
+
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
+
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
+#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
+
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
+
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
+
+/* Offset Register Description
+ ====== ===================================================================== */
+typedef struct {
+ __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
+ __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
+ __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
+ __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
+} mxc_rtccfg_regs_t;
+
+/*
+ Register offsets for module RTCCFG.
+*/
+#define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_RTC_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h
new file mode 100644
index 000000000..645178ca3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h
@@ -0,0 +1,215 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_SPI_REGS_H
+#define _MXC_SPI_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file spi_regs.h
+ * @addtogroup spi SPI
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ============================================ */
+typedef struct {
+ __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
+ __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
+ __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
+ __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
+ __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
+ __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
+ __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
+ __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
+} mxc_spi_regs_t;
+
+/**
+ * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+ union {
+ __O uint8_t txfifo_8;
+ __O uint16_t txfifo_16;
+ __O uint32_t txfifo_32;
+ };
+} mxc_spi_txfifo_regs_t;
+
+/**
+ * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+ union {
+ __I uint8_t rxfifo_8;
+ __I uint16_t rxfifo_16;
+ __I uint32_t rxfifo_32;
+ };
+} mxc_spi_rxfifo_regs_t;
+
+/*
+ Register offsets for module SPI.
+*/
+#define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
+#define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
+#define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
+#define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
+
+#define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
+
+/*
+ Field positions and masks for module SPI.
+*/
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
+
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
+
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
+
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_INTFL_TX_STALLED_POS 0
+#define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
+#define MXC_F_SPI_INTFL_RX_STALLED_POS 1
+#define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
+#define MXC_F_SPI_INTFL_TX_READY_POS 2
+#define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
+#define MXC_F_SPI_INTFL_RX_DONE_POS 3
+#define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
+#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
+#define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
+#define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_INTEN_TX_STALLED_POS 0
+#define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
+#define MXC_F_SPI_INTEN_RX_STALLED_POS 1
+#define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
+#define MXC_F_SPI_INTEN_TX_READY_POS 2
+#define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
+#define MXC_F_SPI_INTEN_RX_DONE_POS 3
+#define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
+#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
+#define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
+#define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_FIFO_DIR_POS 0
+#define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
+#define MXC_F_SPI_FIFO_UNIT_POS 2
+#define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
+#define MXC_F_SPI_FIFO_SIZE_POS 4
+#define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
+#define MXC_F_SPI_FIFO_WIDTH_POS 9
+#define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
+#define MXC_F_SPI_FIFO_ALT_POS 11
+#define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
+#define MXC_F_SPI_FIFO_FLOW_POS 12
+#define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
+#define MXC_F_SPI_FIFO_DASS_POS 13
+#define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_SPI_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c
new file mode 100644
index 000000000..6915b2433
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c
@@ -0,0 +1,147 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "max32610.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "ioman_regs.h"
+#include "trim_regs.h"
+#include "flc_regs.h"
+#include "pwrseq_regs.h"
+#include "dac_regs.h"
+#include "icc_regs.h"
+
+/* Application developer should override where necessary with different external HFX source */
+#ifndef __SYSTEM_HFX
+#define __SYSTEM_HFX 24000000
+#endif
+
+uint32_t SystemCoreClock = 24000000;
+
+void SystemCoreClockUpdate(void)
+{
+ switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
+ SystemCoreClock = 3000000;
+ break;
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
+ SystemCoreClock = 24000000;
+ break;
+ case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
+ SystemCoreClock = __SYSTEM_HFX;
+ break;
+ }
+
+ uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
+ if (shift) {
+ SystemCoreClock = SystemCoreClock >> (shift - 1);
+ }
+}
+
+/* power seq registers */
+static void set_pwr_regs(void)
+{
+ uint32_t dac2trim = MXC_DAC2->reg & 0xff00ffff;
+ uint32_t dac3trim = MXC_DAC3->reg & 0xff00ffff;
+ dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
+ dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
+ MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
+ MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
+ MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
+ MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
+ MXC_DAC2->reg = dac2trim;
+ MXC_DAC3->reg = dac3trim;
+}
+
+void ICC_Enable(void)
+{
+ /* clock gater must be 'on' not 'dynamic' for cache control */
+ uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
+ temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+ temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = temp;
+
+
+ /* invalidate, wait, enable */
+ MXC_ICC->invdt_all = 0xFFFF;
+ while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+
+ /* clock gater 'dynamic' safe again */
+ temp = MXC_CLKMAN->clk_gate_ctrl0;
+ temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+ temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = temp;
+}
+
+// This function to be implemented by the hal
+extern void low_level_init(void);
+
+void SystemInit(void)
+{
+ set_pwr_regs();
+
+ // Turn off PADX
+ MXC_IOMAN->padx_control = 0x00000441;
+
+ // enable instruction cache
+ ICC_Enable();
+
+ low_level_init();
+
+ // Clear IO Active
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
+
+ // Set WUD Clear
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
+
+ // Set IO Active
+ MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
+ MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
+
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
+
+ // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+ SystemCoreClockUpdate();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h
new file mode 100644
index 000000000..094e5de6b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef SYSTEM_MAX32610_H_
+#define SYSTEM_MAX32610_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit (void);
+
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MAX32610_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h
new file mode 100644
index 000000000..1803814ee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h
@@ -0,0 +1,146 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TMR_REGS_H
+#define _MXC_TMR_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file tmr_regs.h
+ * @addtogroup tmr TMR
+ * @{
+ */
+
+/**
+ * @brief Defines timer modes for 16 and 32-bit timers
+ */
+typedef enum {
+ /** 32-bit or 16-bit timer one-shot mode */
+ MXC_E_TMR_MODE_ONE_SHOT = 0,
+ /** 32-bit or 16-bit timer one-shot mode */
+ MXC_E_TMR_MODE_CONTINUOUS,
+ /** 32-bit timer counter mode */
+ MXC_E_TMR_MODE_COUNTER,
+ /** 32-bit timer pulse width modulation mode */
+ MXC_E_TMR_MODE_PWM,
+ /** 32-bit timer capture mode */
+ MXC_E_TMR_MODE_CAPTURE,
+ /** 32-bit timer compare mode */
+ MXC_E_TMR_MODE_COMPARE,
+ /** 32-bit timer gated mode */
+ MXC_E_TMR_MODE_GATED,
+ /** 32-bit timer measure mode */
+ MXC_E_TMR_MODE_MEASURE
+} mxc_tmr_mode_t;
+
+/* Offset Register Description
+ ====== ============================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
+ __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */
+ __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */
+ __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */
+ __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */
+ __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */
+ __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */
+ __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */
+ __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */
+ __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+
+/*
+ Register offsets for module TMR.
+*/
+#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
+#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
+#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
+#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
+#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
+#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
+#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
+
+/*
+ Field positions and masks for module TMR.
+*/
+#define MXC_F_TMR_CTRL_MODE_POS 0
+#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_F_TMR_CTRL_TMR2X16_POS 3
+#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
+#define MXC_F_TMR_CTRL_PRESCALE_POS 4
+#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_F_TMR_CTRL_POLARITY_POS 8
+#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
+#define MXC_F_TMR_CTRL_ENABLE0_POS 12
+#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
+#define MXC_F_TMR_CTRL_ENABLE1_POS 13
+#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
+
+#define MXC_F_TMR_COUNT16_0_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
+
+#define MXC_F_TMR_COUNT16_1_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
+
+#define MXC_F_TMR_INTFL_TIMER0_POS 0
+#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
+#define MXC_F_TMR_INTFL_TIMER1_POS 1
+#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
+
+#define MXC_F_TMR_INTEN_TIMER0_POS 0
+#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
+#define MXC_F_TMR_INTEN_TIMER1_POS 1
+#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TMR_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h
new file mode 100644
index 000000000..1a0c8f49b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h
@@ -0,0 +1,108 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TPU_REGS_H_
+#define _MXC_TPU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file tpu_regs.h
+ * @addtogroup tpu TPU
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================== */
+typedef struct {
+ __I uint32_t rsv0000; /* 0x0000 Reserved */
+ __I uint32_t rsv0004; /* 0x0004 Reserved - PUF Control (Deprecated) */
+ __I uint32_t rsv0008; /* 0x0008 Reserved - PUF Output (Deprecated) */
+ __I uint32_t rsv000C[125]; /* 0x000C */
+ __IO uint32_t prng_user_entropy; /* 0x0200 PRNG User Entropy Value */
+ __IO uint32_t prng_rnd_num; /* 0x0204 PRNG Random Number Output */
+} mxc_tpu_regs_t;
+
+/* Offset Register Description
+ ====== ================================================= */
+typedef struct {
+ __IO uint32_t status; /* 0x0000 Dynamic Tamper Sensor Status */
+ __IO uint32_t ctrl0; /* 0x0004 Dynamic Tamper Sensor Control 0 */
+ __IO uint32_t ctrl1; /* 0x0008 Dynamic Tamper Sensor Control 1 */
+ __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 0 */
+ __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 0 */
+} mxc_tpu_tsr_regs_t;
+
+/*
+ Register offsets for module TPU.
+*/
+#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY ((uint32_t)0x00000200UL)
+#define MXC_R_TPU_OFFS_PRNG_RND_NUM ((uint32_t)0x00000204UL)
+#define MXC_R_TPU_TSR_OFFS_STATUS ((uint32_t)0x00000000UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL0 ((uint32_t)0x00000004UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL1 ((uint32_t)0x00000008UL)
+#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL)
+#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL)
+#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL)
+#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL)
+
+
+/*
+ Field positions and masks for module TPU.
+*/
+#define MXC_F_TPU_CTRL0_ERR_THR_POS 0
+#define MXC_F_TPU_CTRL0_ERR_THR ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS))
+#define MXC_F_TPU_CTRL0_OUT_FREQ_POS 5
+#define MXC_F_TPU_CTRL0_OUT_FREQ ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS))
+#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS 8
+#define MXC_F_TPU_CTRL0_CLOCK_DIV ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS))
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS 14
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS))
+#define MXC_F_TPU_CTRL0_LOCK_POS 15
+#define MXC_F_TPU_CTRL0_LOCK ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TPU_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h
new file mode 100644
index 000000000..2c6ecac55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h
@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TRIM_REGS_H
+#define _MXC_TRIM_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+ __IO uint32_t trim_reg_00;
+ __IO uint32_t trim_reg_01;
+ __IO uint32_t trim_reg_02;
+ __IO uint32_t trim_reg_03;
+ __IO uint32_t trim_reg_04;
+ __IO uint32_t trim_reg_05;
+ __IO uint32_t trim_reg_06;
+ __IO uint32_t trim_reg_07;
+ __IO uint32_t trim_reg_08;
+ __IO uint32_t trim_reg_09;
+ __IO uint32_t trim_reg_10;
+ __IO uint32_t trim_reg_11;
+ __IO uint32_t trim_reg_12;
+ __IO uint32_t trim_reg_13;
+ __IO uint32_t trim_reg_14;
+ __IO uint32_t trim_reg_15;
+ __IO uint32_t trim_reg_16;
+ __IO uint32_t trim_reg_17;
+ __IO uint32_t trim_reg_18;
+ __IO uint32_t trim_reg_19;
+ __IO uint32_t trim_reg_20;
+ __IO uint32_t trim_reg_21;
+ __IO uint32_t trim_reg_22;
+ __IO uint32_t trim_reg_23;
+ __IO uint32_t trim_reg_24;
+ __IO uint32_t trim_reg_25;
+ __IO uint32_t trim_reg_26;
+ __IO uint32_t trim_reg_27;
+ __IO uint32_t trim_reg_28;
+ __IO uint32_t trim_reg_29;
+ __IO uint32_t trim_reg_30;
+ __IO uint32_t trim_reg_31;
+ __IO uint32_t trim_reg_32;
+ __IO uint32_t trim_reg_33;
+ __IO uint32_t trim_reg_34;
+ __IO uint32_t trim_reg_35;
+ __IO uint32_t trim_reg_36;
+ __IO uint32_t trim_reg_37;
+ __IO uint32_t trim_reg_38;
+ __IO uint32_t trim_reg_39;
+ __IO uint32_t trim_reg_40;
+ __IO uint32_t trim_reg_41;
+} mxc_ftr_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h
new file mode 100644
index 000000000..49fbe5d96
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h
@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file uart_regs.h
+ * @addtogroup uart UART
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ============================================== */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 UART Control Register */
+ __IO uint32_t status; /* 0x0004 UART Status Register */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t intfl; /* 0x000C Interrupt Flags */
+ __IO uint32_t baud_int; /* 0x0010 Baud Rate Setting (Integer Portion) */
+ __IO uint32_t baud_div_128; /* 0x0014 Baud Rate Setting */
+ __IO uint32_t tx_fifo_out; /* 0x0018 TX FIFO Output End (read-only) */
+ __IO uint32_t hw_flow_ctrl; /* 0x001C Hardware Flow Control Register */
+ __IO uint32_t tx_rx_fifo; /* 0x0020 Write to load TX FIFO, Read to unload RX FIFO */
+} mxc_uart_regs_t;
+
+
+/*
+ Register offsets for module UART.
+*/
+#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_STATUS ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_BAUD_INT ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_BAUD_DIV_128 ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_TX_FIFO_OUT ((uint32_t)0x00000018UL)
+#define MXC_R_UART_OFFS_HW_FLOW_CTRL ((uint32_t)0x0000001CUL)
+#define MXC_R_UART_OFFS_TX_RX_FIFO ((uint32_t)0x00000020UL)
+
+/*
+ Field positions and masks for module UART.
+*/
+#define MXC_F_UART_CTRL_RX_THRESHOLD_POS 0
+#define MXC_F_UART_CTRL_RX_THRESHOLD ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
+#define MXC_F_UART_CTRL_PARITY_ENABLE_POS 4
+#define MXC_F_UART_CTRL_PARITY_ENABLE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
+#define MXC_F_UART_CTRL_PARITY_MODE_POS 5
+#define MXC_F_UART_CTRL_PARITY_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
+#define MXC_F_UART_CTRL_PARITY_BIAS_POS 6
+#define MXC_F_UART_CTRL_PARITY_BIAS ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS 8
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS 9
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_CHAR_LENGTH_POS 10
+#define MXC_F_UART_CTRL_CHAR_LENGTH ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
+#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS 12
+#define MXC_F_UART_CTRL_STOP_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS 13
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
+#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS 14
+#define MXC_F_UART_CTRL_BAUD_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
+
+#define MXC_F_UART_STATUS_TX_BUSY_POS 0
+#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_BUSY_POS 1
+#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS 4
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS 5
+#define MXC_F_UART_STATUS_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS 6
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS 7
+#define MXC_F_UART_STATUS_TX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS 8
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS 12
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
+
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS 0
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS 1
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTEN_CTS_CHANGE_POS 2
+#define MXC_F_UART_INTEN_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
+#define MXC_F_UART_INTEN_RX_OVERRUN_POS 3
+#define MXC_F_UART_INTEN_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS 4
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS 5
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS 6
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS 0
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS 1
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTFL_CTS_CHANGE_POS 2
+#define MXC_F_UART_INTFL_CTS_CHANGE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
+#define MXC_F_UART_INTFL_RX_OVERRUN_POS 3
+#define MXC_F_UART_INTFL_RX_OVERRUN ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS 4
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS 5
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS 6
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_BAUD_INT_FBAUD_POS 0
+#define MXC_F_UART_BAUD_INT_FBAUD ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
+
+#define MXC_F_UART_BAUD_DIV_128_DIV_POS 0
+#define MXC_F_UART_BAUD_DIV_128_DIV ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
+
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS 0
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
+
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS 0
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS 1
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
+
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS 0
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS 8
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_UART_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h
new file mode 100644
index 000000000..bea640a78
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h
@@ -0,0 +1,453 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file usb_regs.h
+ * @addtogroup usb USB
+ * @{
+ */
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t cn; /* 0x0000 USB Control Register */
+ __I uint32_t rsv0004[127]; /* 0x0004 */
+ __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
+ __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
+ __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
+ __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
+ __I uint32_t rsv0210[4]; /* 0x0210 */
+ __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
+ __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
+ __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
+ __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
+ __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
+ __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
+ __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
+ __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
+ __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
+ __I uint32_t rsv0244[7]; /* 0x0244 */
+ __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
+ __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
+ __I uint32_t rsv0268[6]; /* 0x0268 */
+ __IO uint32_t ep[MXC_USB_NUM_EP]; /* 0x0280 USB Endpoint Control Registers */
+} mxc_usb_regs_t;
+
+
+/*
+ Register offsets for module USB.
+*/
+#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
+
+
+/*
+ Field positions and masks for module USB.
+*/
+#define MXC_F_USB_CN_USB_EN_POS 0
+#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
+#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS 3
+#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS 4
+#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS 5
+#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS 6
+#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
+#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
+#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS 2
+#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS 3
+#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
+#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
+#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
+#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
+#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS 2
+#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS 3
+#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
+#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
+#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
+#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
+#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
+#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
+#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV0_POS 0
+#define MXC_F_USB_IN_INT_INBAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS))
+#define MXC_F_USB_IN_INT_INBAV1_POS 1
+#define MXC_F_USB_IN_INT_INBAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS))
+#define MXC_F_USB_IN_INT_INBAV2_POS 2
+#define MXC_F_USB_IN_INT_INBAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS))
+#define MXC_F_USB_IN_INT_INBAV3_POS 3
+#define MXC_F_USB_IN_INT_INBAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS))
+#define MXC_F_USB_IN_INT_INBAV4_POS 4
+#define MXC_F_USB_IN_INT_INBAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS))
+#define MXC_F_USB_IN_INT_INBAV5_POS 5
+#define MXC_F_USB_IN_INT_INBAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS))
+#define MXC_F_USB_IN_INT_INBAV6_POS 6
+#define MXC_F_USB_IN_INT_INBAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS))
+#define MXC_F_USB_IN_INT_INBAV7_POS 7
+#define MXC_F_USB_IN_INT_INBAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV0_POS 0
+#define MXC_F_USB_OUT_INT_OUTDAV0 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV1_POS 1
+#define MXC_F_USB_OUT_INT_OUTDAV1 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV2_POS 2
+#define MXC_F_USB_OUT_INT_OUTDAV2 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV3_POS 3
+#define MXC_F_USB_OUT_INT_OUTDAV3 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV4_POS 4
+#define MXC_F_USB_OUT_INT_OUTDAV4 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV5_POS 5
+#define MXC_F_USB_OUT_INT_OUTDAV5 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV6_POS 6
+#define MXC_F_USB_OUT_INT_OUTDAV6 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV7_POS 7
+#define MXC_F_USB_OUT_INT_OUTDAV7 ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS))
+
+#define MXC_F_USB_NAK_INT_NAK0_POS 0
+#define MXC_F_USB_NAK_INT_NAK0 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS))
+#define MXC_F_USB_NAK_INT_NAK1_POS 1
+#define MXC_F_USB_NAK_INT_NAK1 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS))
+#define MXC_F_USB_NAK_INT_NAK2_POS 2
+#define MXC_F_USB_NAK_INT_NAK2 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS))
+#define MXC_F_USB_NAK_INT_NAK3_POS 3
+#define MXC_F_USB_NAK_INT_NAK3 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS))
+#define MXC_F_USB_NAK_INT_NAK4_POS 4
+#define MXC_F_USB_NAK_INT_NAK4 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS))
+#define MXC_F_USB_NAK_INT_NAK5_POS 5
+#define MXC_F_USB_NAK_INT_NAK5 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS))
+#define MXC_F_USB_NAK_INT_NAK6_POS 6
+#define MXC_F_USB_NAK_INT_NAK6 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS))
+#define MXC_F_USB_NAK_INT_NAK7_POS 7
+#define MXC_F_USB_NAK_INT_NAK7 ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS 0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS 1
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS 2
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS 3
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS 4
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS 5
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS 6
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS 7
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7 ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS 0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS 1
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS 2
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS 3
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS 4
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS 5
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS 6
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS 7
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7 ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS 0
+#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS 8
+#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS 16
+#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS 24
+#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE4_POS 0
+#define MXC_F_USB_SETUP1_BYTE4 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS))
+#define MXC_F_USB_SETUP1_BYTE5_POS 8
+#define MXC_F_USB_SETUP1_BYTE5 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS))
+#define MXC_F_USB_SETUP1_BYTE6_POS 16
+#define MXC_F_USB_SETUP1_BYTE6 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS))
+#define MXC_F_USB_SETUP1_BYTE7_POS 24
+#define MXC_F_USB_SETUP1_BYTE7 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS))
+
+
+#define MXC_F_USB_EP0_EP_DIR_POS 0
+#define MXC_F_USB_EP0_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS))
+#define MXC_F_USB_EP0_EP_BUF2_POS 3
+#define MXC_F_USB_EP0_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS))
+#define MXC_F_USB_EP0_EP_INT_EN_POS 4
+#define MXC_F_USB_EP0_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS))
+#define MXC_F_USB_EP0_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP0_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS))
+#define MXC_F_USB_EP0_EP_DT_POS 6
+#define MXC_F_USB_EP0_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS))
+#define MXC_F_USB_EP0_EP_STALL_POS 8
+#define MXC_F_USB_EP0_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP0_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP0_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP1_EP_DIR_POS 0
+#define MXC_F_USB_EP1_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS))
+#define MXC_F_USB_EP1_EP_BUF2_POS 3
+#define MXC_F_USB_EP1_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS))
+#define MXC_F_USB_EP1_EP_INT_EN_POS 4
+#define MXC_F_USB_EP1_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS))
+#define MXC_F_USB_EP1_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP1_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS))
+#define MXC_F_USB_EP1_EP_DT_POS 6
+#define MXC_F_USB_EP1_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS))
+#define MXC_F_USB_EP1_EP_STALL_POS 8
+#define MXC_F_USB_EP1_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP1_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP1_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP2_EP_DIR_POS 0
+#define MXC_F_USB_EP2_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS))
+#define MXC_F_USB_EP2_EP_BUF2_POS 3
+#define MXC_F_USB_EP2_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS))
+#define MXC_F_USB_EP2_EP_INT_EN_POS 4
+#define MXC_F_USB_EP2_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS))
+#define MXC_F_USB_EP2_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP2_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS))
+#define MXC_F_USB_EP2_EP_DT_POS 6
+#define MXC_F_USB_EP2_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS))
+#define MXC_F_USB_EP2_EP_STALL_POS 8
+#define MXC_F_USB_EP2_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP2_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP2_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP3_EP_DIR_POS 0
+#define MXC_F_USB_EP3_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS))
+#define MXC_F_USB_EP3_EP_BUF2_POS 3
+#define MXC_F_USB_EP3_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS))
+#define MXC_F_USB_EP3_EP_INT_EN_POS 4
+#define MXC_F_USB_EP3_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS))
+#define MXC_F_USB_EP3_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP3_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS))
+#define MXC_F_USB_EP3_EP_DT_POS 6
+#define MXC_F_USB_EP3_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS))
+#define MXC_F_USB_EP3_EP_STALL_POS 8
+#define MXC_F_USB_EP3_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP3_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP3_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP4_EP_DIR_POS 0
+#define MXC_F_USB_EP4_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS))
+#define MXC_F_USB_EP4_EP_BUF2_POS 3
+#define MXC_F_USB_EP4_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS))
+#define MXC_F_USB_EP4_EP_INT_EN_POS 4
+#define MXC_F_USB_EP4_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS))
+#define MXC_F_USB_EP4_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP4_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS))
+#define MXC_F_USB_EP4_EP_DT_POS 6
+#define MXC_F_USB_EP4_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS))
+#define MXC_F_USB_EP4_EP_STALL_POS 8
+#define MXC_F_USB_EP4_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP4_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP4_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP5_EP_DIR_POS 0
+#define MXC_F_USB_EP5_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS))
+#define MXC_F_USB_EP5_EP_BUF2_POS 3
+#define MXC_F_USB_EP5_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS))
+#define MXC_F_USB_EP5_EP_INT_EN_POS 4
+#define MXC_F_USB_EP5_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS))
+#define MXC_F_USB_EP5_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP5_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS))
+#define MXC_F_USB_EP5_EP_DT_POS 6
+#define MXC_F_USB_EP5_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS))
+#define MXC_F_USB_EP5_EP_STALL_POS 8
+#define MXC_F_USB_EP5_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP5_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP5_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP6_EP_DIR_POS 0
+#define MXC_F_USB_EP6_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS))
+#define MXC_F_USB_EP6_EP_BUF2_POS 3
+#define MXC_F_USB_EP6_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS))
+#define MXC_F_USB_EP6_EP_INT_EN_POS 4
+#define MXC_F_USB_EP6_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS))
+#define MXC_F_USB_EP6_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP6_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS))
+#define MXC_F_USB_EP6_EP_DT_POS 6
+#define MXC_F_USB_EP6_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS))
+#define MXC_F_USB_EP6_EP_STALL_POS 8
+#define MXC_F_USB_EP6_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP6_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP6_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP7_EP_DIR_POS 0
+#define MXC_F_USB_EP7_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS))
+#define MXC_F_USB_EP7_EP_BUF2_POS 3
+#define MXC_F_USB_EP7_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS))
+#define MXC_F_USB_EP7_EP_INT_EN_POS 4
+#define MXC_F_USB_EP7_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS))
+#define MXC_F_USB_EP7_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP7_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS))
+#define MXC_F_USB_EP7_EP_DT_POS 6
+#define MXC_F_USB_EP7_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS))
+#define MXC_F_USB_EP7_EP_STALL_POS 8
+#define MXC_F_USB_EP7_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP7_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP7_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_USB_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h
new file mode 100644
index 000000000..906e80146
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_WDT_REGS_H_
+#define _MXC_WDT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file wdt_regs.h
+ * @addtogroup wdt WDT
+ * @{
+ */
+
+/**
+ * @brief Defines watchdog timer periods
+ */
+typedef enum {
+ /** 2^31 cycle period */
+ MXC_E_WDT_PERIOD_2_31_CLKS = 0,
+ /** 2^30 cycle period */
+ MXC_E_WDT_PERIOD_2_30_CLKS,
+ /** 2^29 cycle period */
+ MXC_E_WDT_PERIOD_2_29_CLKS,
+ /** 2^28 cycle period */
+ MXC_E_WDT_PERIOD_2_28_CLKS,
+ /** 2^27 cycle period */
+ MXC_E_WDT_PERIOD_2_27_CLKS,
+ /** 2^26 cycle period */
+ MXC_E_WDT_PERIOD_2_26_CLKS,
+ /** 2^25 cycle period */
+ MXC_E_WDT_PERIOD_2_25_CLKS,
+ /** 2^24 cycle period */
+ MXC_E_WDT_PERIOD_2_24_CLKS,
+ /** 2^23 cycle period */
+ MXC_E_WDT_PERIOD_2_23_CLKS,
+ /** 2^22 cycle period */
+ MXC_E_WDT_PERIOD_2_22_CLKS,
+ /** 2^21 cycle period */
+ MXC_E_WDT_PERIOD_2_21_CLKS,
+ /** 2^20 cycle period */
+ MXC_E_WDT_PERIOD_2_20_CLKS,
+ /** 2^19 cycle period */
+ MXC_E_WDT_PERIOD_2_19_CLKS,
+ /** 2^18 cycle period */
+ MXC_E_WDT_PERIOD_2_18_CLKS,
+ /** 2^17 cycle period */
+ MXC_E_WDT_PERIOD_2_17_CLKS,
+ /** 2^16 cycle period */
+ MXC_E_WDT_PERIOD_2_16_CLKS,
+} mxc_wdt_period_t;
+
+/* Offset Register Description
+ ====== ================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
+ __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */
+ __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */
+ __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */
+ __I uint32_t rsv0010; /* 0x0010 */
+ __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */
+} mxc_wdt_regs_t;
+
+/*
+ Register offsets for module WDT.
+*/
+#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
+#define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL)
+#define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL)
+#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
+
+#define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24)
+#define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42)
+
+
+/*
+ Field positions and masks for module WDT.
+*/
+#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
+#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
+#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
+#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
+#define MXC_F_WDT_CTRL_EN_TIMER_POS 8
+#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
+#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
+#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
+#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
+#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
+
+#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
+#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
+#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
+#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
+#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
+#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
+
+#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
+#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
+#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
+#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
+#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
+#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
+
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_WDT_REGS_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct
new file mode 100644
index 000000000..62638400f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/nRF51822.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000 {
+; ER_IROM1 0x00000000 0x00040000 {
+; *.o (RESET, +First)
+; *(InRoot$$Sections)
+; .ANY (+RO)
+; }
+; RW_IRAM1 0x20000000 0x00004000 {
+; .ANY (+RW +ZI)
+; }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x18000 0x0028000 {
+ ER_IROM1 0x18000 0x0028000 {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20002000 0x00002000 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.s
new file mode 100644
index 000000000..f57ccfe64
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.s
@@ -0,0 +1,187 @@
+; mbed Microcontroller Library
+; Copyright (c) 2013 Nordic Semiconductor.
+;Licensed under the Apache License, Version 2.0 (the "License");
+;you may not use this file except in compliance with the License.
+;You may obtain a copy of the License at
+;http://www.apache.org/licenses/LICENSE-2.0
+;Unless required by applicable law or agreed to in writing, software
+;distributed under the License is distributed on an "AS IS" BASIS,
+;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;See the License for the specific language governing permissions and
+;limitations under the License.
+
+; Description message
+
+__initial_sp EQU 0x20004000
+
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
+ DCD RADIO_IRQHandler ;RADIO
+ DCD UART0_IRQHandler ;UART0
+ DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
+ DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
+ DCD 0 ;Reserved
+ DCD GPIOTE_IRQHandler ;GPIOTE
+ DCD ADC_IRQHandler ;ADC
+ DCD TIMER0_IRQHandler ;TIMER0
+ DCD TIMER1_IRQHandler ;TIMER1
+ DCD TIMER2_IRQHandler ;TIMER2
+ DCD RTC0_IRQHandler ;RTC0
+ DCD TEMP_IRQHandler ;TEMP
+ DCD RNG_IRQHandler ;RNG
+ DCD ECB_IRQHandler ;ECB
+ DCD CCM_AAR_IRQHandler ;CCM_AAR
+ DCD WDT_IRQHandler ;WDT
+ DCD RTC1_IRQHandler ;RTC1
+ DCD QDEC_IRQHandler ;QDEC
+ DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+ DCD SWI0_IRQHandler ;SWI0
+ DCD SWI1_IRQHandler ;SWI1
+ DCD SWI2_IRQHandler ;SWI2
+ DCD SWI3_IRQHandler ;SWI3
+ DCD SWI4_IRQHandler ;SWI4
+ DCD SWI5_IRQHandler ;SWI5
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+ ORRS R2, R2, R1
+ STR R2, [R0]
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT POWER_CLOCK_IRQHandler [WEAK]
+ EXPORT RADIO_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT SPI0_TWI0_IRQHandler [WEAK]
+ EXPORT SPI1_TWI1_IRQHandler [WEAK]
+ EXPORT GPIOTE_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT TEMP_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT ECB_IRQHandler [WEAK]
+ EXPORT CCM_AAR_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT QDEC_IRQHandler [WEAK]
+ EXPORT LPCOMP_COMP_IRQHandler [WEAK]
+ EXPORT SWI0_IRQHandler [WEAK]
+ EXPORT SWI1_IRQHandler [WEAK]
+ EXPORT SWI2_IRQHandler [WEAK]
+ EXPORT SWI3_IRQHandler [WEAK]
+ EXPORT SWI4_IRQHandler [WEAK]
+ EXPORT SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UART0_IRQHandler
+SPI0_TWI0_IRQHandler
+SPI1_TWI1_IRQHandler
+GPIOTE_IRQHandler
+ADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+LPCOMP_COMP_IRQHandler
+SWI0_IRQHandler
+SWI1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+
+ B .
+ ENDP
+ ALIGN
+ END
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
new file mode 100644
index 000000000..6dd0642fd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000 {
+; ER_IROM1 0x00000000 0x00040000 {
+; *.o (RESET, +First)
+; *(InRoot$$Sections)
+; .ANY (+RO)
+; }
+; RW_IRAM1 0x20000000 0x00008000 {
+; .ANY (+RW +ZI)
+; }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x18000 0x0028000 {
+ ER_IROM1 0x18000 0x0028000 {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20002000 0x00006000 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s
new file mode 100644
index 000000000..ea211543d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s
@@ -0,0 +1,196 @@
+; mbed Microcontroller Library
+; Copyright (c) 2013 Nordic Semiconductor.
+;Licensed under the Apache License, Version 2.0 (the "License");
+;you may not use this file except in compliance with the License.
+;You may obtain a copy of the License at
+;http://www.apache.org/licenses/LICENSE-2.0
+;Unless required by applicable law or agreed to in writing, software
+;distributed under the License is distributed on an "AS IS" BASIS,
+;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;See the License for the specific language governing permissions and
+;limitations under the License.
+
+; Description message
+
+__initial_sp EQU 0x20008000
+
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
+ DCD RADIO_IRQHandler ;RADIO
+ DCD UART0_IRQHandler ;UART0
+ DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
+ DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
+ DCD 0 ;Reserved
+ DCD GPIOTE_IRQHandler ;GPIOTE
+ DCD ADC_IRQHandler ;ADC
+ DCD TIMER0_IRQHandler ;TIMER0
+ DCD TIMER1_IRQHandler ;TIMER1
+ DCD TIMER2_IRQHandler ;TIMER2
+ DCD RTC0_IRQHandler ;RTC0
+ DCD TEMP_IRQHandler ;TEMP
+ DCD RNG_IRQHandler ;RNG
+ DCD ECB_IRQHandler ;ECB
+ DCD CCM_AAR_IRQHandler ;CCM_AAR
+ DCD WDT_IRQHandler ;WDT
+ DCD RTC1_IRQHandler ;RTC1
+ DCD QDEC_IRQHandler ;QDEC
+ DCD LPCOMP_IRQHandler ;LPCOMP
+ DCD SWI0_IRQHandler ;SWI0
+ DCD SWI1_IRQHandler ;SWI1
+ DCD SWI2_IRQHandler ;SWI2
+ DCD SWI3_IRQHandler ;SWI3
+ DCD SWI4_IRQHandler ;SWI4
+ DCD SWI5_IRQHandler ;SWI5
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
+NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
+NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R2, R1
+ STR R2, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT POWER_CLOCK_IRQHandler [WEAK]
+ EXPORT RADIO_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT SPI0_TWI0_IRQHandler [WEAK]
+ EXPORT SPI1_TWI1_IRQHandler [WEAK]
+ EXPORT GPIOTE_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT TEMP_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT ECB_IRQHandler [WEAK]
+ EXPORT CCM_AAR_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT QDEC_IRQHandler [WEAK]
+ EXPORT LPCOMP_IRQHandler [WEAK]
+ EXPORT SWI0_IRQHandler [WEAK]
+ EXPORT SWI1_IRQHandler [WEAK]
+ EXPORT SWI2_IRQHandler [WEAK]
+ EXPORT SWI3_IRQHandler [WEAK]
+ EXPORT SWI4_IRQHandler [WEAK]
+ EXPORT SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UART0_IRQHandler
+SPI0_TWI0_IRQHandler
+SPI1_TWI1_IRQHandler
+GPIOTE_IRQHandler
+ADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+LPCOMP_IRQHandler
+SWI0_IRQHandler
+SWI1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+
+ B .
+ ENDP
+ ALIGN
+ END
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld
new file mode 100644
index 000000000..cb472e564
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_16K/NRF51822.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000
+ RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000
+}
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
new file mode 100644
index 000000000..812a86d4e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000
+ RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x6000
+}
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.s
new file mode 100644
index 000000000..e5de3f95f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.s
@@ -0,0 +1,262 @@
+/*
+Copyright (c) 2013, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 2048
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 2048
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .Vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler /*POWER_CLOCK */
+ .long RADIO_IRQHandler /*RADIO */
+ .long UART0_IRQHandler /*UART0 */
+ .long SPI0_TWI0_IRQHandler /*SPI0_TWI0 */
+ .long SPI1_TWI1_IRQHandler /*SPI1_TWI1 */
+ .long 0 /*Reserved */
+ .long GPIOTE_IRQHandler /*GPIOTE */
+ .long ADC_IRQHandler /*ADC */
+ .long TIMER0_IRQHandler /*TIMER0 */
+ .long TIMER1_IRQHandler /*TIMER1 */
+ .long TIMER2_IRQHandler /*TIMER2 */
+ .long RTC0_IRQHandler /*RTC0 */
+ .long TEMP_IRQHandler /*TEMP */
+ .long RNG_IRQHandler /*RNG */
+ .long ECB_IRQHandler /*ECB */
+ .long CCM_AAR_IRQHandler /*CCM_AAR */
+ .long WDT_IRQHandler /*WDT */
+ .long RTC1_IRQHandler /*RTC1 */
+ .long QDEC_IRQHandler /*QDEC */
+ .long LPCOMP_IRQHandler /*LPCOMP */
+ .long SWI0_IRQHandler /*SWI0 */
+ .long SWI1_IRQHandler /*SWI1 */
+ .long SWI2_IRQHandler /*SWI2 */
+ .long SWI3_IRQHandler /*SWI3 */
+ .long SWI4_IRQHandler /*SWI4 */
+ .long SWI5_IRQHandler /*SWI5 */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+
+ .size __Vectors, . - __Vectors
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMON_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UART0_IRQHandler
+ IRQ SPI0_TWI0_IRQHandler
+ IRQ SPI1_TWI1_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ ADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ LPCOMP_IRQHandler
+ IRQ SWI0_IRQHandler
+ IRQ SWI1_IRQHandler
+ IRQ SWI2_IRQHandler
+ IRQ SWI3_IRQHandler
+ IRQ SWI4_IRQHandler
+ IRQ SWI5_IRQHandler
+
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf
new file mode 100644
index 000000000..d71c75cb3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00016000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x900;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK,
+ block HEAP };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+ place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+} \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s
new file mode 100644
index 000000000..b1e263009
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s
@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+ MODULE ?cstartup
+
+ ;; Stack size default : 1024
+ ;; Heap size default : 2048
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+;__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
+ DCD RADIO_IRQHandler ;RADIO
+ DCD UART0_IRQHandler ;UART0
+ DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
+ DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
+ DCD 0 ;Reserved
+ DCD GPIOTE_IRQHandler ;GPIOTE
+ DCD ADC_IRQHandler ;ADC
+ DCD TIMER0_IRQHandler ;TIMER0
+ DCD TIMER1_IRQHandler ;TIMER1
+ DCD TIMER2_IRQHandler ;TIMER2
+ DCD RTC0_IRQHandler ;RTC0
+ DCD TEMP_IRQHandler ;TEMP
+ DCD RNG_IRQHandler ;RNG
+ DCD ECB_IRQHandler ;ECB
+ DCD CCM_AAR_IRQHandler ;CCM_AAR
+ DCD WDT_IRQHandler ;WDT
+ DCD RTC1_IRQHandler ;RTC1
+ DCD QDEC_IRQHandler ;QDEC
+ DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+ DCD SWI0_IRQHandler ;SWI0
+ DCD SWI1_IRQHandler ;SWI1
+ DCD SWI2_IRQHandler ;SWI2
+ DCD SWI3_IRQHandler ;SWI3
+ DCD SWI4_IRQHandler ;SWI4
+ DCD SWI5_IRQHandler ;SWI5
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+
+
+__Vectors_End
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+ ORRS R2, R2, R1
+ STR R2, [R0]
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ ; Dummy exception handlers
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+ ; Dummy interrupt handlers
+
+ PUBWEAK POWER_CLOCK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+ B .
+ PUBWEAK RADIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+ B .
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B .
+ PUBWEAK SPI0_TWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+ B .
+ PUBWEAK SPI1_TWI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+ B .
+ PUBWEAK GPIOTE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+ B .
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B .
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+ B .
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+ B .
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+ B .
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B .
+ PUBWEAK TEMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+ B .
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+ B .
+ PUBWEAK ECB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+ B .
+ PUBWEAK CCM_AAR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+ B .
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B .
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B .
+ PUBWEAK QDEC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+ B .
+ PUBWEAK LPCOMP_COMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+ B .
+ PUBWEAK SWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+ B .
+ PUBWEAK SWI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+ B .
+ PUBWEAK SWI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+ B .
+ PUBWEAK SWI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+ B .
+ PUBWEAK SWI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+ B .
+ PUBWEAK SWI5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+ B .
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf
new file mode 100644
index 000000000..e53b889cc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00016000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0xc00;
+define symbol __ICFEDIT_size_heap__ = 0x1800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK,
+ block HEAP };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+ place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s
new file mode 100644
index 000000000..c0a2b08ea
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s
@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+ MODULE ?cstartup
+
+ ;; Stack size default : 1024
+ ;; Heap size default : 2048
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+;__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
+ DCD RADIO_IRQHandler ;RADIO
+ DCD UART0_IRQHandler ;UART0
+ DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
+ DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
+ DCD 0 ;Reserved
+ DCD GPIOTE_IRQHandler ;GPIOTE
+ DCD ADC_IRQHandler ;ADC
+ DCD TIMER0_IRQHandler ;TIMER0
+ DCD TIMER1_IRQHandler ;TIMER1
+ DCD TIMER2_IRQHandler ;TIMER2
+ DCD RTC0_IRQHandler ;RTC0
+ DCD TEMP_IRQHandler ;TEMP
+ DCD RNG_IRQHandler ;RNG
+ DCD ECB_IRQHandler ;ECB
+ DCD CCM_AAR_IRQHandler ;CCM_AAR
+ DCD WDT_IRQHandler ;WDT
+ DCD RTC1_IRQHandler ;RTC1
+ DCD QDEC_IRQHandler ;QDEC
+ DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+ DCD SWI0_IRQHandler ;SWI0
+ DCD SWI1_IRQHandler ;SWI1
+ DCD SWI2_IRQHandler ;SWI2
+ DCD SWI3_IRQHandler ;SWI3
+ DCD SWI4_IRQHandler ;SWI4
+ DCD SWI5_IRQHandler ;SWI5
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+
+
+__Vectors_End
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+ ORRS R2, R2, R1
+ STR R2, [R0]
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ ; Dummy exception handlers
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+ ; Dummy interrupt handlers
+
+ PUBWEAK POWER_CLOCK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+ B .
+ PUBWEAK RADIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+ B .
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+ B .
+ PUBWEAK SPI0_TWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+ B .
+ PUBWEAK SPI1_TWI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+ B .
+ PUBWEAK GPIOTE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+ B .
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B .
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+ B .
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+ B .
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+ B .
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B .
+ PUBWEAK TEMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+ B .
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+ B .
+ PUBWEAK ECB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+ B .
+ PUBWEAK CCM_AAR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+ B .
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B .
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B .
+ PUBWEAK QDEC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+ B .
+ PUBWEAK LPCOMP_COMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+ B .
+ PUBWEAK SWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+ B .
+ PUBWEAK SWI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+ B .
+ PUBWEAK SWI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+ B .
+ PUBWEAK SWI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+ B .
+ PUBWEAK SWI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+ B .
+ PUBWEAK SWI5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+ B .
+
+
+ END \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin
new file mode 100644
index 000000000..151801682
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin
Binary files differ
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h
new file mode 100644
index 000000000..b73fdadde
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC407x_8x specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "nrf.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c
new file mode 100644
index 000000000..5fe8d89d6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ *
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ *
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
+ * - No flash accesses will go to ram, as there will be nothing there
+ * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ * - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+/*
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}*/
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ // int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ /*
+ // Copy and switch to dynamic vectors if first time called
+ if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
+ uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
+ for(i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+ }*/
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ // We can always read vectors at 0x0, as the addresses are remapped
+ uint32_t *vectors = (uint32_t*)0;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h
new file mode 100644
index 000000000..ab365b2a7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "nrf51.h"
+#include "cmsis.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h
new file mode 100644
index 000000000..18d70eb20
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h
@@ -0,0 +1,109 @@
+/* Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _COMPILER_ABSTRACTION_H
+#define _COMPILER_ABSTRACTION_H
+
+/*lint ++flb "Enter library region" */
+
+#if defined ( __CC_ARM )
+
+ #ifndef __ASM
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #endif
+
+ #ifndef __INLINE
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #endif
+
+ #ifndef __WEAK
+ #define __WEAK __weak /*!< weak keyword for ARM Compiler */
+ #endif
+
+ #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+
+ #ifndef __ASM
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #endif
+
+ #ifndef __INLINE
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #endif
+
+ #ifndef __WEAK
+ #define __WEAK __weak /*!> define weak function for IAR Compiler */
+ #endif
+
+ #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */
+
+#elif defined ( __GNUC__ )
+
+ #ifndef __ASM
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #endif
+
+ #ifndef __INLINE
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #endif
+
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */
+ #endif
+
+ #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */
+
+ static inline unsigned int gcc_current_sp(void)
+ {
+ register unsigned sp asm("sp");
+ return sp;
+ }
+
+#elif defined ( __TASKING__ )
+
+ #ifndef __ASM
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #endif
+
+ #ifndef __INLINE
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #endif
+
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */
+ #endif
+
+ #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */
+
+#endif
+
+/*lint --flb "Leave library region" */
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h
new file mode 100644
index 000000000..e77307f3f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef NRF_H
+#define NRF_H
+
+#ifndef _WIN32
+
+/* Family selection for main includes. NRF51 must be selected. */
+#ifdef NRF51
+ #include "nrf51.h"
+ #include "nrf51_bitfields.h"
+#else
+ #error "Device family must be defined. See nrf.h."
+#endif /* NRF51 */
+
+#include "compiler_abstraction.h"
+
+#endif /* _WIN32 */
+
+#endif /* NRF_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h
new file mode 100644
index 000000000..266d8f0ed
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h
@@ -0,0 +1,1312 @@
+
+/****************************************************************************************************//**
+ * @file nRF51.h
+ *
+ * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ * nRF51 from Nordic Semiconductor.
+ *
+ * @version V522
+ * @date 31. October 2014
+ *
+ * @note Generated with SVDConv V2.81d
+ * from CMSIS SVD File 'nRF51.xml' Version 522,
+ *
+ * @par Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+/** @addtogroup nRF51
+ * @{
+ */
+
+#ifndef NRF51_H
+#define NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UART0_IRQn = 2, /*!< 2 UART0 */
+ SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
+ SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ ADC_IRQn = 7, /*!< 7 ADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
+ SWI0_IRQn = 20, /*!< 20 SWI0 */
+ SWI1_IRQn = 21, /*!< 21 SWI1 */
+ SWI2_IRQn = 22, /*!< 22 SWI2 */
+ SWI3_IRQn = 23, /*!< 23 SWI3 */
+ SWI4_IRQn = 24, /*!< 24 SWI4 */
+ SWI5_IRQn = 25 /*!< 25 SWI5 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_nrf51.h" /*!< nRF51 System */
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+ __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
+ __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
+ __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
+ __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
+ __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
+ __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
+} AMLI_RAMPRI_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK. */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t MISO; /*!< Pin select for MISO. */
+} SPIM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
+ __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
+} SPIM_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
+ __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
+} SPIM_TXD_Type;
+
+typedef struct {
+ __O uint32_t EN; /*!< Enable channel group. */
+ __O uint32_t DIS; /*!< Disable channel group. */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+ __IO uint32_t EEP; /*!< Channel event end-point. */
+ __IO uint32_t TEP; /*!< Channel task end-point. */
+} PPI_CH_Type;
+
+typedef struct {
+ __I uint32_t PART; /*!< Part code */
+ __I uint32_t VARIANT; /*!< Part variant */
+ __I uint32_t PACKAGE; /*!< Package option */
+ __I uint32_t RAM; /*!< RAM variant */
+ __I uint32_t FLASH; /*!< Flash variant */
+ __I uint32_t RESERVED[3]; /*!< Reserved */
+} FICR_INFO_Type;
+
+
+/* ================================================================================ */
+/* ================ POWER ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Control. (POWER)
+ */
+
+typedef struct { /*!< POWER Structure */
+ __I uint32_t RESERVED0[30];
+ __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
+ __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
+ __I uint32_t RESERVED1[34];
+ __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __IO uint32_t RESETREAS; /*!< Reset reason. */
+ __I uint32_t RESERVED4[9];
+ __I uint32_t RAMSTATUS; /*!< Ram status register. */
+ __I uint32_t RESERVED5[53];
+ __O uint32_t SYSTEMOFF; /*!< System off register. */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t POFCON; /*!< Power failure configuration. */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
+ register. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t RAMON; /*!< Ram on/off. */
+ __I uint32_t RESERVED9[7];
+ __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
+ is a retained register. */
+ __I uint32_t RESERVED10[3];
+ __IO uint32_t RAMONB; /*!< Ram on/off. */
+ __I uint32_t RESERVED11[8];
+ __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
+ __I uint32_t RESERVED12[291];
+ __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================ CLOCK ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Clock control. (CLOCK)
+ */
+
+typedef struct { /*!< CLOCK Structure */
+ __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
+ __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
+ __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
+ __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
+ __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
+ __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
+ __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
+ __I uint32_t RESERVED0[57];
+ __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
+ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
+ __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
+ __I uint32_t RESERVED2[124];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[63];
+ __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
+ __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
+ __I uint32_t RESERVED4;
+ __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
+ __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
+ __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+ triggered. */
+ __I uint32_t RESERVED5[62];
+ __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t CTIV; /*!< Calibration timer interval. */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================ MPU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Memory Protection Unit. (MPU)
+ */
+
+typedef struct { /*!< MPU Structure */
+ __I uint32_t RESERVED0[330];
+ __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
+ __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
+ __I uint32_t RESERVED1[52];
+ __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
+ __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
+} NRF_MPU_Type;
+
+
+/* ================================================================================ */
+/* ================ PU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Patch unit. (PU)
+ */
+
+typedef struct { /*!< PU Structure */
+ __I uint32_t RESERVED0[448];
+ __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
+ __I uint32_t RESERVED1[24];
+ __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
+ __I uint32_t RESERVED2[24];
+ __IO uint32_t PATCHEN; /*!< Patch enable register. */
+ __IO uint32_t PATCHENSET; /*!< Patch enable register. */
+ __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
+} NRF_PU_Type;
+
+
+/* ================================================================================ */
+/* ================ AMLI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AHB Multi-Layer Interface. (AMLI)
+ */
+
+typedef struct { /*!< AMLI Structure */
+ __I uint32_t RESERVED0[896];
+ AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
+} NRF_AMLI_Type;
+
+
+/* ================================================================================ */
+/* ================ RADIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief The radio. (RADIO)
+ */
+
+typedef struct { /*!< RADIO Structure */
+ __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
+ __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
+ __O uint32_t TASKS_START; /*!< Start radio. */
+ __O uint32_t TASKS_STOP; /*!< Stop radio. */
+ __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
+ __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
+ __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
+ __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
+ __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
+ __I uint32_t RESERVED0[55];
+ __IO uint32_t EVENTS_READY; /*!< Ready event. */
+ __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
+ __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
+ __IO uint32_t EVENTS_END; /*!< End event. */
+ __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
+ __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
+ __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
+ __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
+ sample is ready for readout at the RSSISAMPLE register. */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
+ __I uint32_t RESERVED2[53];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
+ __I uint32_t RESERVED3[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED4[61];
+ __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
+ __I uint32_t CD; /*!< Carrier detect. */
+ __I uint32_t RXMATCH; /*!< Received address. */
+ __I uint32_t RXCRC; /*!< Received CRC. */
+ __I uint32_t DAI; /*!< Device address match index. */
+ __I uint32_t RESERVED5[60];
+ __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
+ __IO uint32_t FREQUENCY; /*!< Frequency. */
+ __IO uint32_t TXPOWER; /*!< Output power. */
+ __IO uint32_t MODE; /*!< Data rate and modulation. */
+ __IO uint32_t PCNF0; /*!< Packet configuration 0. */
+ __IO uint32_t PCNF1; /*!< Packet configuration 1. */
+ __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
+ __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
+ __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
+ __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
+ __IO uint32_t TXADDRESS; /*!< Transmit address select. */
+ __IO uint32_t RXADDRESSES; /*!< Receive address select. */
+ __IO uint32_t CRCCNF; /*!< CRC configuration. */
+ __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
+ __IO uint32_t CRCINIT; /*!< CRC initial value. */
+ __IO uint32_t TEST; /*!< Test features enable register. */
+ __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
+ __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
+ __I uint32_t RESERVED6;
+ __I uint32_t STATE; /*!< Current radio state. */
+ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t BCC; /*!< Bit counter compare. */
+ __I uint32_t RESERVED8[39];
+ __IO uint32_t DAB[8]; /*!< Device address base segment. */
+ __IO uint32_t DAP[8]; /*!< Device address prefix. */
+ __IO uint32_t DACNF; /*!< Device address match configuration. */
+ __I uint32_t RESERVED9[56];
+ __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
+ __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
+ __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
+ __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
+ __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
+ __I uint32_t RESERVED10[561];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================ UART ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+ */
+
+typedef struct { /*!< UART Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
+ __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
+ __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
+ __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
+ __I uint32_t RESERVED0[3];
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
+ __I uint32_t RESERVED1[56];
+ __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
+ __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
+ __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
+ __I uint32_t RESERVED2[4];
+ __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
+ __I uint32_t RESERVED3;
+ __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
+ __I uint32_t RESERVED5[46];
+ __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
+ __I uint32_t RESERVED6[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED7[93];
+ __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
+ __I uint32_t RESERVED8[31];
+ __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
+ __I uint32_t RESERVED9;
+ __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
+ __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
+ __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
+ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
+ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
+ Once read the character is consumed. If read when no character
+ available, the UART will stop working. */
+ __O uint32_t TXD; /*!< TXD register. */
+ __I uint32_t RESERVED10;
+ __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
+ __I uint32_t RESERVED11[17];
+ __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
+ __I uint32_t RESERVED12[675];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI master 0. (SPI)
+ */
+
+typedef struct { /*!< SPI Structure */
+ __I uint32_t RESERVED0[66];
+ __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
+ __I uint32_t RESERVED1[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[125];
+ __IO uint32_t ENABLE; /*!< Enable SPI. */
+ __I uint32_t RESERVED3;
+ __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
+ __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
+ __I uint32_t RESERVED4;
+ __I uint32_t RXD; /*!< RX data. */
+ __IO uint32_t TXD; /*!< TX data. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t FREQUENCY; /*!< SPI frequency */
+ __I uint32_t RESERVED6[11];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED7[681];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================ TWI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Two-wire interface master 0. (TWI)
+ */
+
+typedef struct { /*!< TWI Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
+ __I uint32_t RESERVED0;
+ __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
+ __I uint32_t RESERVED2;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
+ __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
+ __I uint32_t RESERVED3[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
+ __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
+ __I uint32_t RESERVED4[4];
+ __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
+ __I uint32_t RESERVED6[4];
+ __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
+ __I uint32_t RESERVED8[45];
+ __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
+ __I uint32_t RESERVED9[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED10[110];
+ __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
+ __I uint32_t RESERVED11[14];
+ __IO uint32_t ENABLE; /*!< Enable two-wire master. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
+ __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
+ __I uint32_t RESERVED13[2];
+ __I uint32_t RXD; /*!< RX data register. */
+ __IO uint32_t TXD; /*!< TX data register. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
+ __I uint32_t RESERVED15[24];
+ __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
+ __I uint32_t RESERVED16[668];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIS ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI slave 1. (SPIS)
+ */
+
+typedef struct { /*!< SPIS Structure */
+ __I uint32_t RESERVED0[9];
+ __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
+ __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
+ __I uint32_t RESERVED1[54];
+ __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
+ __I uint32_t RESERVED2[8];
+ __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
+ __I uint32_t RESERVED3[53];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
+ __I uint32_t RESERVED4[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED5[61];
+ __I uint32_t SEMSTAT; /*!< Semaphore status. */
+ __I uint32_t RESERVED6[15];
+ __IO uint32_t STATUS; /*!< Status from last transaction. */
+ __I uint32_t RESERVED7[47];
+ __IO uint32_t ENABLE; /*!< Enable SPIS. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
+ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
+ __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
+ __I uint32_t RESERVED9[7];
+ __IO uint32_t RXDPTR; /*!< RX data pointer. */
+ __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
+ __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
+ __I uint32_t RESERVED10;
+ __IO uint32_t TXDPTR; /*!< TX data pointer. */
+ __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
+ __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
+ __I uint32_t RESERVED11;
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t DEF; /*!< Default character. */
+ __I uint32_t RESERVED13[24];
+ __IO uint32_t ORC; /*!< Over-read character. */
+ __I uint32_t RESERVED14[654];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI master with easyDMA 1. (SPIM)
+ */
+
+typedef struct { /*!< SPIM Structure */
+ __I uint32_t RESERVED0[4];
+ __O uint32_t TASKS_START; /*!< Start SPI transaction. */
+ __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
+ __I uint32_t RESERVED1;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
+ __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
+ __I uint32_t RESERVED2[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
+ __I uint32_t RESERVED6[10];
+ __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
+ __I uint32_t RESERVED7[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
+ __I uint32_t RESERVED8[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED9[125];
+ __IO uint32_t ENABLE; /*!< Enable SPIM. */
+ __I uint32_t RESERVED10;
+ SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
+ __I uint32_t RESERVED11;
+ __I uint32_t RXDDATA; /*!< RXD register. */
+ __IO uint32_t TXDDATA; /*!< TXD register. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t FREQUENCY; /*!< SPI frequency. */
+ __I uint32_t RESERVED13[3];
+ SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED14;
+ SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED16[26];
+ __IO uint32_t ORC; /*!< Over-read character. */
+ __I uint32_t RESERVED17[654];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIOTE ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GPIO tasks and events. (GPIOTE)
+ */
+
+typedef struct { /*!< GPIOTE Structure */
+ __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
+ __I uint32_t RESERVED0[60];
+ __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
+ __I uint32_t RESERVED1[27];
+ __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
+ __I uint32_t RESERVED2[97];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[129];
+ __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
+ __I uint32_t RESERVED4[695];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog to digital converter. (ADC)
+ */
+
+typedef struct { /*!< ADC Structure */
+ __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
+ __O uint32_t TASKS_STOP; /*!< Stop ADC. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[61];
+ __I uint32_t BUSY; /*!< ADC busy register. */
+ __I uint32_t RESERVED3[63];
+ __IO uint32_t ENABLE; /*!< ADC enable. */
+ __IO uint32_t CONFIG; /*!< ADC configuration register. */
+ __I uint32_t RESULT; /*!< Result of ADC conversion. */
+ __I uint32_t RESERVED4[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ TIMER ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Timer 0. (TIMER)
+ */
+
+typedef struct { /*!< TIMER Structure */
+ __O uint32_t TASKS_START; /*!< Start Timer. */
+ __O uint32_t TASKS_STOP; /*!< Stop Timer. */
+ __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
+ __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
+ __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
+ __I uint32_t RESERVED0[11];
+ __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
+ __I uint32_t RESERVED1[60];
+ __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
+ __I uint32_t RESERVED2[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
+ __I uint32_t RESERVED3[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED4[126];
+ __IO uint32_t MODE; /*!< Timer Mode selection. */
+ __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
+ clock frequency is divided by 2^SCALE. */
+ __I uint32_t RESERVED6[11];
+ __IO uint32_t CC[4]; /*!< Capture/compare registers. */
+ __I uint32_t RESERVED7[683];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Real time counter 0. (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+ __O uint32_t TASKS_START; /*!< Start RTC Counter. */
+ __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
+ __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
+ __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
+ __I uint32_t RESERVED0[60];
+ __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
+ __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
+ __I uint32_t RESERVED1[14];
+ __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
+ __I uint32_t RESERVED2[109];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[13];
+ __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
+ __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
+ the value of EVTEN. */
+ __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
+ gives the value of EVTEN. */
+ __I uint32_t RESERVED4[110];
+ __I uint32_t COUNTER; /*!< Current COUNTER value. */
+ __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+ Must be written when RTC is STOPed. */
+ __I uint32_t RESERVED5[13];
+ __IO uint32_t CC[4]; /*!< Capture/compare registers. */
+ __I uint32_t RESERVED6[683];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ TEMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Temperature Sensor. (TEMP)
+ */
+
+typedef struct { /*!< TEMP Structure */
+ __O uint32_t TASKS_START; /*!< Start temperature measurement. */
+ __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[127];
+ __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
+ __I uint32_t RESERVED3[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================ RNG ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Random Number Generator. (RNG)
+ */
+
+typedef struct { /*!< RNG Structure */
+ __O uint32_t TASKS_START; /*!< Start the random number generator. */
+ __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
+ __I uint32_t RESERVED1[63];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
+ __I uint32_t RESERVED3[126];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t VALUE; /*!< RNG random number. */
+ __I uint32_t RESERVED4[700];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================ ECB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AES ECB Mode Encryption. (ECB)
+ */
+
+typedef struct { /*!< ECB Structure */
+ __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
+ will not initiate a new encryption and the ERRORECB event will
+ be triggered. */
+ __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
+ this will will trigger the ERRORECB event. */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
+ __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
+ error. */
+ __I uint32_t RESERVED1[127];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
+ __I uint32_t RESERVED3[701];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================ AAR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Accelerated Address Resolver. (AAR)
+ */
+
+typedef struct { /*!< AAR Structure */
+ __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
+ data structure. */
+ __I uint32_t RESERVED0;
+ __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
+ __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
+ __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
+ __I uint32_t RESERVED2[126];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t STATUS; /*!< Resolution status. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< Enable AAR. */
+ __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
+ __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 3 bytes must be reserved. */
+ __I uint32_t RESERVED6[697];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================ CCM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief AES CCM Mode Encryption. (CCM)
+ */
+
+typedef struct { /*!< CCM Structure */
+ __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
+ itself when completed. */
+ __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
+ completed. */
+ __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
+ __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
+ __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< CCM enable. */
+ __IO uint32_t MODE; /*!< Operation mode. */
+ __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
+ __IO uint32_t INPTR; /*!< Pointer to the input packet. */
+ __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 43 bytes must be reserved. */
+ __I uint32_t RESERVED5[697];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================ WDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Watchdog Timer. (WDT)
+ */
+
+typedef struct { /*!< WDT Structure */
+ __O uint32_t TASKS_START; /*!< Start the watchdog. */
+ __I uint32_t RESERVED0[63];
+ __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED2[61];
+ __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
+ __I uint32_t REQSTATUS; /*!< Request status. */
+ __I uint32_t RESERVED3[63];
+ __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
+ __IO uint32_t RREN; /*!< Reload request enable. */
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED4[60];
+ __O uint32_t RR[8]; /*!< Reload requests registers. */
+ __I uint32_t RESERVED5[631];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================ QDEC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Rotary decoder. (QDEC)
+ */
+
+typedef struct { /*!< QDEC Structure */
+ __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
+ __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
+ __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
+ and clears the ACC registers. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
+ __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
+ ACC register different than zero. */
+ __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
+ __I uint32_t RESERVED1[61];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[125];
+ __IO uint32_t ENABLE; /*!< Enable the QDEC. */
+ __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
+ __IO uint32_t SAMPLEPER; /*!< Sample period. */
+ __I int32_t SAMPLE; /*!< Motion sample value. */
+ __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
+ __I int32_t ACC; /*!< Accumulated valid transitions register. */
+ __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
+ task. */
+ __IO uint32_t PSELLED; /*!< Pin select for LED output. */
+ __IO uint32_t PSELA; /*!< Pin select for phase A input. */
+ __IO uint32_t PSELB; /*!< Pin select for phase B input. */
+ __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
+ __I uint32_t RESERVED4[5];
+ __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
+ __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
+ __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
+ task. */
+ __I uint32_t RESERVED5[684];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================ LPCOMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Low power comparator. (LPCOMP)
+ */
+
+typedef struct { /*!< LPCOMP Structure */
+ __O uint32_t TASKS_START; /*!< Start the comparator. */
+ __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
+ __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
+ __I uint32_t RESERVED0[61];
+ __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
+ __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
+ __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
+ __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
+ __I uint32_t RESERVED1[60];
+ __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
+ __I uint32_t RESERVED2[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED3[61];
+ __I uint32_t RESULT; /*!< Result of last compare. */
+ __I uint32_t RESERVED4[63];
+ __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
+ __IO uint32_t PSEL; /*!< Input pin select. */
+ __IO uint32_t REFSEL; /*!< Reference select. */
+ __IO uint32_t EXTREFSEL; /*!< External reference select. */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
+ __I uint32_t RESERVED6[694];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================ SWI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SW Interrupts. (SWI)
+ */
+
+typedef struct { /*!< SWI Structure */
+ __I uint32_t UNUSED; /*!< Unused. */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================ NVMC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Non Volatile Memory Controller. (NVMC)
+ */
+
+typedef struct { /*!< NVMC Structure */
+ __I uint32_t RESERVED0[256];
+ __I uint32_t READY; /*!< Ready flag. */
+ __I uint32_t RESERVED1[64];
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
+ __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
+ __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
+ __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================ PPI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief PPI controller. (PPI)
+ */
+
+typedef struct { /*!< PPI Structure */
+ PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
+ __I uint32_t RESERVED0[312];
+ __IO uint32_t CHEN; /*!< Channel enable. */
+ __IO uint32_t CHENSET; /*!< Channel enable set. */
+ __IO uint32_t CHENCLR; /*!< Channel enable clear. */
+ __I uint32_t RESERVED1;
+ PPI_CH_Type CH[16]; /*!< PPI Channel. */
+ __I uint32_t RESERVED2[156];
+ __IO uint32_t CHG[4]; /*!< Channel group configuration. */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================ FICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Factory Information Configuration. (FICR)
+ */
+
+typedef struct { /*!< FICR Structure */
+ __I uint32_t RESERVED0[4];
+ __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
+ __I uint32_t CODESIZE; /*!< Code memory size in pages. */
+ __I uint32_t RESERVED1[4];
+ __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
+ __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
+ __I uint32_t RESERVED2;
+ __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
+
+ union {
+ __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
+ kept for backward compatinility purposes. Use SIZERAMBLOCKS
+ instead. */
+ __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
+ };
+ __I uint32_t RESERVED3[5];
+ __I uint32_t CONFIGID; /*!< Configuration identifier. */
+ __I uint32_t DEVICEID[2]; /*!< Device identifier. */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t ER[4]; /*!< Encryption root. */
+ __I uint32_t IR[4]; /*!< Identity root. */
+ __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
+ __I uint32_t DEVICEADDR[2]; /*!< Device address. */
+ __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
+ __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+ mode. */
+ __I uint32_t RESERVED5[10];
+ __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
+ mode. */
+ FICR_INFO_Type INFO; /*!< Device info */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================ UICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief User Information Configuration. (UICR)
+ */
+
+typedef struct { /*!< UICR Structure */
+ __IO uint32_t CLENR0; /*!< Length of code region 0. */
+ __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
+ __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
+ __I uint32_t RESERVED0;
+ __I uint32_t FWID; /*!< Firmware ID. */
+ __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General purpose input and output. (GPIO)
+ */
+
+typedef struct { /*!< GPIO Structure */
+ __I uint32_t RESERVED0[321];
+ __IO uint32_t OUT; /*!< Write GPIO port. */
+ __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
+ __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
+ __I uint32_t IN; /*!< Read GPIO port. */
+ __IO uint32_t DIR; /*!< Direction of GPIO pins. */
+ __IO uint32_t DIRSET; /*!< DIR set register. */
+ __IO uint32_t DIRCLR; /*!< DIR clear register. */
+ __I uint32_t RESERVED1[120];
+ __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
+} NRF_GPIO_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_MPU_BASE 0x40000000UL
+#define NRF_PU_BASE 0x40000000UL
+#define NRF_AMLI_BASE 0x40000000UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_SPI0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_SPI1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
+#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_SPIM1_BASE 0x40004000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_ADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
+#define NRF_LPCOMP_BASE 0x40013000UL
+#define NRF_SWI_BASE 0x40014000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_GPIO_BASE 0x50000000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
+#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
+#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
+#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
+#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
+#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
+#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
+#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
+#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
+#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
+#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
+#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
+#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
+#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nRF51 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* nRF51_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h
new file mode 100644
index 000000000..52aa65394
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h
@@ -0,0 +1,7135 @@
+/* Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef __NRF51_BITS_H
+#define __NRF51_BITS_H
+
+/*lint ++flb "Enter library region */
+
+#include <core_cm0.h>
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver. */
+
+/* Register: AAR_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on RESOLVED event. */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: AAR_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on RESOLVED event. */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status. */
+
+/* Bits 3..0 : The IRK used last time an address was resolved. */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR. */
+
+/* Bits 1..0 : Enable AAR. */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
+#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
+
+/* Register: AAR_NIRK */
+/* Description: Number of Identity root Keys in the IRK data structure. */
+
+/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: ADC */
+/* Description: Analog to digital converter. */
+
+/* Register: ADC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ADC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on END event. */
+#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ADC_BUSY */
+/* Description: ADC busy register. */
+
+/* Bit 0 : ADC busy register. */
+#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
+#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
+#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
+#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
+
+/* Register: ADC_ENABLE */
+/* Description: ADC enable. */
+
+/* Bits 1..0 : ADC enable. */
+#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
+#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
+
+/* Register: ADC_CONFIG */
+/* Description: ADC configuration register. */
+
+/* Bits 17..16 : ADC external reference pin selection. */
+#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
+
+/* Bits 15..8 : ADC analog pin selection. */
+#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
+#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
+
+/* Bits 6..5 : ADC reference selection. */
+#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
+#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
+#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
+#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
+#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
+
+/* Bits 4..2 : ADC input selection. */
+#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
+#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
+#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
+
+/* Bits 1..0 : ADC resolution. */
+#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
+#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
+#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
+#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
+#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
+
+/* Register: ADC_RESULT */
+/* Description: Result of ADC conversion. */
+
+/* Bits 9..0 : Result of ADC conversion. */
+#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+
+/* Register: ADC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: AMLI */
+/* Description: AHB Multi-Layer Interface. */
+
+/* Register: AMLI_RAMPRI_CPU0 */
+/* Description: Configurable priority configuration register for CPU0. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_SPIS1 */
+/* Description: Configurable priority configuration register for SPIS1. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_RADIO */
+/* Description: Configurable priority configuration register for RADIO. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_ECB */
+/* Description: Configurable priority configuration register for ECB. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_CCM */
+/* Description: Configurable priority configuration register for CCM. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_AAR */
+/* Description: Configurable priority configuration register for AAR. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption. */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts for the CCM. */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: CCM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ERROR event. */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ENDCRYPT event. */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDKSGEN event. */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CCM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ERROR event. */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ENDCRYPT event. */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CCM_MICSTATUS */
+/* Description: CCM RX MIC check result. */
+
+/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
+
+/* Register: CCM_ENABLE */
+/* Description: CCM enable. */
+
+/* Bits 1..0 : CCM enable. */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
+#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode. */
+
+/* Bit 0 : CCM mode operation. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
+
+/* Register: CCM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control. */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 4 : Enable interrupt on CTTO event. */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on DONE event. */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 4 : Disable interrupt on CTTO event. */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on DONE event. */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Task HFCLKSTART trigger status. */
+
+/* Bit 0 : Task HFCLKSTART trigger status. */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: High frequency clock status. */
+
+/* Bit 16 : State for the HFCLK. */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
+
+/* Bit 0 : Active clock source for the HF clock. */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Task LFCLKSTART triggered status. */
+
+/* Bit 0 : Task LFCLKSTART triggered status. */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: Low frequency clock status. */
+
+/* Bit 16 : State for the LF clock. */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
+
+/* Bits 1..0 : Active clock source for the LF clock. */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+
+/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK clock. */
+
+/* Bits 1..0 : Clock source. */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval. */
+
+/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_XTALFREQ */
+/* Description: Crystal frequency. */
+
+/* Bits 7..0 : External Xtal frequency selection. */
+#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
+#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption. */
+
+/* Register: ECB_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 1 : Enable interrupt on ERRORECB event. */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDECB event. */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ECB_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 1 : Disable interrupt on ERRORECB event. */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDECB event. */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ECB_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration. */
+
+/* Register: FICR_PPFC */
+/* Description: Pre-programmed factory code present. */
+
+/* Bits 7..0 : Pre-programmed factory code present. */
+#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
+#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
+#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
+#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
+
+/* Register: FICR_CONFIGID */
+/* Description: Configuration identifier. */
+
+/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
+#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
+#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+/* Bits 15..0 : Hardware Identification Number. */
+#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
+#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type. */
+
+/* Bit 0 : Device address type. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
+
+/* Register: FICR_OVERRIDEEN */
+/* Description: Radio calibration override enable. */
+
+/* Bit 3 : Override default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
+
+/* Bit 0 : Override default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
+#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part variant */
+
+/* Bits 31..0 : Part variant */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
+#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
+#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
+#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
+#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
+#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
+
+
+/* Peripheral: GPIO */
+/* Description: General purpose input and output. */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register. */
+
+/* Bit 31 : Set as output pin 31. */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 30 : Set as output pin 30. */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 29 : Set as output pin 29. */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 28 : Set as output pin 28. */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 27 : Set as output pin 27. */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 26 : Set as output pin 26. */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 25 : Set as output pin 25. */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 24 : Set as output pin 24. */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 23 : Set as output pin 23. */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 22 : Set as output pin 22. */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 21 : Set as output pin 21. */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 20 : Set as output pin 20. */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 19 : Set as output pin 19. */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 18 : Set as output pin 18. */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 17 : Set as output pin 17. */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 16 : Set as output pin 16. */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 15 : Set as output pin 15. */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 14 : Set as output pin 14. */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 13 : Set as output pin 13. */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 12 : Set as output pin 12. */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 11 : Set as output pin 11. */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 10 : Set as output pin 10. */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 9 : Set as output pin 9. */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 8 : Set as output pin 8. */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 7 : Set as output pin 7. */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 6 : Set as output pin 6. */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 5 : Set as output pin 5. */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 4 : Set as output pin 4. */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 3 : Set as output pin 3. */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 2 : Set as output pin 2. */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 1 : Set as output pin 1. */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 0 : Set as output pin 0. */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register. */
+
+/* Bit 31 : Set as input pin 31. */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 30 : Set as input pin 30. */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 29 : Set as input pin 29. */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 28 : Set as input pin 28. */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 27 : Set as input pin 27. */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 26 : Set as input pin 26. */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 25 : Set as input pin 25. */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 24 : Set as input pin 24. */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 23 : Set as input pin 23. */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 22 : Set as input pin 22. */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 21 : Set as input pin 21. */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 20 : Set as input pin 20. */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 19 : Set as input pin 19. */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 18 : Set as input pin 18. */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 17 : Set as input pin 17. */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 16 : Set as input pin 16. */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 15 : Set as input pin 15. */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 14 : Set as input pin 14. */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 13 : Set as input pin 13. */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 12 : Set as input pin 12. */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 11 : Set as input pin 11. */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 10 : Set as input pin 10. */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 9 : Set as input pin 9. */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 8 : Set as input pin 8. */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 7 : Set as input pin 7. */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 6 : Set as input pin 6. */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 5 : Set as input pin 5. */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 4 : Set as input pin 4. */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 3 : Set as input pin 3. */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 2 : Set as input pin 2. */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 1 : Set as input pin 1. */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 0 : Set as input pin 0. */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Configuration of GPIO pins. */
+
+/* Bits 17..16 : Pin sensing mechanism. */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
+#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
+
+/* Bits 10..8 : Drive configuration. */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
+
+/* Bits 3..2 : Pull-up or -down configuration. */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
+#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
+#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
+
+/* Bit 1 : Connect or disconnect input path. */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
+
+/* Bit 0 : Pin direction. */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO tasks and events. */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 31 : Enable interrupt on PORT event. */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on IN[3] event. */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on IN[2] event. */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on IN[1] event. */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on IN[0] event. */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 31 : Disable interrupt on PORT event. */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on IN[3] event. */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on IN[2] event. */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on IN[1] event. */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on IN[0] event. */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Channel configuration registers. */
+
+/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
+
+/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
+
+/* Bits 12..8 : Pin select. */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
+#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
+
+/* Register: GPIOTE_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low power comparator. */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcuts for the LPCOMP. */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task. */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between UP event and STOP task. */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task. */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between RADY event and STOP task. */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 3 : Enable interrupt on CROSS event. */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on UP event. */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on DOWN event. */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 3 : Disable interrupt on CROSS event. */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on UP event. */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on DOWN event. */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Result of last compare. */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable the LPCOMP. */
+
+/* Bits 1..0 : Enable or disable LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select. */
+
+/* Bits 2..0 : Analog input pin select. */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select. */
+
+/* Bits 2..0 : Reference select. */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select. */
+
+/* Bit 0 : External analog reference pin selection. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration. */
+
+/* Bits 1..0 : Analog detect configuration. */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
+
+/* Register: LPCOMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: MPU */
+/* Description: Memory Protection Unit. */
+
+/* Register: MPU_PERR0 */
+/* Description: Configuration of peripherals in mpu regions. */
+
+/* Bit 31 : PPI region configuration. */
+#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
+#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
+#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 30 : NVMC region configuration. */
+#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
+#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
+#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 19 : LPCOMP region configuration. */
+#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 18 : QDEC region configuration. */
+#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
+#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
+#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 17 : RTC1 region configuration. */
+#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
+#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
+#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 16 : WDT region configuration. */
+#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
+#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
+#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 15 : CCM and AAR region configuration. */
+#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 14 : ECB region configuration. */
+#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
+#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
+#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 13 : RNG region configuration. */
+#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
+#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
+#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 12 : TEMP region configuration. */
+#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
+#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
+#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 11 : RTC0 region configuration. */
+#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
+#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
+#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 10 : TIMER2 region configuration. */
+#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
+#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
+#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 9 : TIMER1 region configuration. */
+#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
+#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
+#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 8 : TIMER0 region configuration. */
+#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
+#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
+#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 7 : ADC region configuration. */
+#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
+#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
+#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 6 : GPIOTE region configuration. */
+#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 4 : SPI1 and TWI1 region configuration. */
+#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 3 : SPI0 and TWI0 region configuration. */
+#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 2 : UART0 region configuration. */
+#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
+#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
+#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 1 : RADIO region configuration. */
+#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
+#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
+#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 0 : POWER_CLOCK region configuration. */
+#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Register: MPU_PROTENSET0 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 31. */
+#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 30. */
+#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 29. */
+#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 28. */
+#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 27. */
+#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 26. */
+#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 25. */
+#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 24. */
+#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 23. */
+#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 22. */
+#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 21. */
+#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 20. */
+#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 19. */
+#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 18. */
+#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 17. */
+#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 16. */
+#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 15. */
+#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 14. */
+#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 13. */
+#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 12. */
+#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 11. */
+#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 10. */
+#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 9. */
+#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 8. */
+#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 7. */
+#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 6. */
+#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 5. */
+#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 4. */
+#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 3. */
+#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 2. */
+#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 1. */
+#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 0. */
+#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_PROTENSET1 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 63. */
+#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 62. */
+#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 61. */
+#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 60. */
+#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 59. */
+#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 58. */
+#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 57. */
+#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 56. */
+#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 55. */
+#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 54. */
+#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 53. */
+#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 52. */
+#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 51. */
+#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 50. */
+#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 49. */
+#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 48. */
+#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 47. */
+#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 46. */
+#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 45. */
+#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 44. */
+#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 43. */
+#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 42. */
+#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 41. */
+#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 40. */
+#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 39. */
+#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 38. */
+#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 37. */
+#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 36. */
+#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 35. */
+#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 34. */
+#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 33. */
+#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 32. */
+#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_DISABLEINDEBUG */
+/* Description: Disable erase and write protection mechanism in debug mode. */
+
+/* Bit 0 : Disable protection mechanism in debug mode. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
+
+/* Register: MPU_PROTBLOCKSIZE */
+/* Description: Erase and write protection block size. */
+
+/* Bits 1..0 : Erase and write protection block size. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller. */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag. */
+
+/* Bit 0 : NVMC ready. */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register. */
+
+/* Bits 1..0 : Program write enable. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
+#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
+#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory. */
+
+/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for start erasing User Information Congfiguration Registers. */
+
+/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
+
+
+/* Peripheral: POWER */
+/* Description: Power Control. */
+
+/* Register: POWER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on POFWARN event. */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: POWER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on POFWARN event. */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason. */
+
+/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+
+/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+
+/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+
+/* Bit 3 : Reset from CPU lock-up detected. */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+
+/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+
+/* Bit 1 : Reset from watchdog detected. */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+
+/* Bit 0 : Reset from pin-reset detected. */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Ram status register. */
+
+/* Bit 3 : RAM block 3 status. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
+
+/* Bit 2 : RAM block 2 status. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
+
+/* Bit 1 : RAM block 1 status. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
+
+/* Bit 0 : RAM block 0 status. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System off register. */
+
+/* Bit 0 : Enter system off mode. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure configuration. */
+
+/* Bits 2..1 : Set threshold level. */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
+#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
+#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
+#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
+
+/* Bit 0 : Power failure comparator enable. */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register. This register is a retained register. */
+
+/* Bits 7..0 : General purpose retention register. */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 1 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
+
+/* Bit 16 : RAM block 0 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
+
+/* Bit 1 : RAM block 1 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
+
+/* Bit 0 : RAM block 0 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
+
+/* Register: POWER_RESET */
+/* Description: Pin reset functionality configuration register. This register is a retained register. */
+
+/* Bit 0 : Enable or disable pin reset in debug interface mode. */
+#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
+#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
+#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
+#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
+
+/* Register: POWER_RAMONB */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 3 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
+
+/* Bit 16 : RAM block 2 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
+
+/* Bit 1 : RAM block 3 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
+
+/* Bit 0 : RAM block 2 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
+
+/* Register: POWER_DCDCEN */
+/* Description: DCDC converter enable configuration register. */
+
+/* Bit 0 : Enable DCDC converter. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
+
+/* Register: POWER_DCDCFORCE */
+/* Description: DCDC power-up force register. */
+
+/* Bit 1 : DCDC power-up force on. */
+#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
+
+/* Bit 0 : DCDC power-up force off. */
+#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
+
+
+/* Peripheral: PPI */
+/* Description: PPI controller. */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear. */
+
+/* Bit 31 : Disable PPI channel 31. */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 30 : Disable PPI channel 30. */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 29 : Disable PPI channel 29. */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 28 : Disable PPI channel 28. */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 27 : Disable PPI channel 27. */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 26 : Disable PPI channel 26. */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 25 : Disable PPI channel 25. */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 24 : Disable PPI channel 24. */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 23 : Disable PPI channel 23. */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 22 : Disable PPI channel 22. */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 21 : Disable PPI channel 21. */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 20 : Disable PPI channel 20. */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 15 : Disable PPI channel 15. */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 14 : Disable PPI channel 14. */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 13 : Disable PPI channel 13. */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 12 : Disable PPI channel 12. */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 11 : Disable PPI channel 11. */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 10 : Disable PPI channel 10. */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 9 : Disable PPI channel 9. */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 8 : Disable PPI channel 8. */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 7 : Disable PPI channel 7. */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 6 : Disable PPI channel 6. */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 5 : Disable PPI channel 5. */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 4 : Disable PPI channel 4. */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 3 : Disable PPI channel 3. */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 2 : Disable PPI channel 2. */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 1 : Disable PPI channel 1. */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 0 : Disable PPI channel 0. */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
+
+/* Register: PPI_CHG */
+/* Description: Channel group configuration. */
+
+/* Bit 31 : Include CH31 in channel group. */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
+
+/* Bit 30 : Include CH30 in channel group. */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
+
+/* Bit 29 : Include CH29 in channel group. */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
+
+/* Bit 28 : Include CH28 in channel group. */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
+
+/* Bit 27 : Include CH27 in channel group. */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
+
+/* Bit 26 : Include CH26 in channel group. */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
+
+/* Bit 25 : Include CH25 in channel group. */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
+
+/* Bit 24 : Include CH24 in channel group. */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
+
+/* Bit 23 : Include CH23 in channel group. */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
+
+/* Bit 22 : Include CH22 in channel group. */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
+
+/* Bit 21 : Include CH21 in channel group. */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
+
+/* Bit 20 : Include CH20 in channel group. */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
+
+/* Bit 15 : Include CH15 in channel group. */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
+
+/* Bit 14 : Include CH14 in channel group. */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
+
+/* Bit 13 : Include CH13 in channel group. */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
+
+/* Bit 12 : Include CH12 in channel group. */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
+
+/* Bit 11 : Include CH11 in channel group. */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
+
+/* Bit 10 : Include CH10 in channel group. */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
+
+/* Bit 9 : Include CH9 in channel group. */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
+
+/* Bit 8 : Include CH8 in channel group. */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
+
+/* Bit 7 : Include CH7 in channel group. */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
+
+/* Bit 6 : Include CH6 in channel group. */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
+
+/* Bit 5 : Include CH5 in channel group. */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
+
+/* Bit 4 : Include CH4 in channel group. */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
+
+/* Bit 3 : Include CH3 in channel group. */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
+
+/* Bit 2 : Include CH2 in channel group. */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
+
+/* Bit 1 : Include CH1 in channel group. */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
+
+/* Bit 0 : Include CH0 in channel group. */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
+
+
+/* Peripheral: PU */
+/* Description: Patch unit. */
+
+/* Register: PU_PATCHADDR */
+/* Description: Relative address of patch instructions. */
+
+/* Bits 24..0 : Relative address of patch instructions. */
+#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
+#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
+
+/* Register: PU_PATCHEN */
+/* Description: Patch enable register. */
+
+/* Bit 7 : Patch 7 enabled. */
+#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
+#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
+#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 6 : Patch 6 enabled. */
+#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
+#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
+#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 5 : Patch 5 enabled. */
+#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
+#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
+#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 4 : Patch 4 enabled. */
+#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
+#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
+#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 3 : Patch 3 enabled. */
+#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
+#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
+#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 2 : Patch 2 enabled. */
+#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
+#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
+#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 1 : Patch 1 enabled. */
+#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
+#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
+#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
+
+/* Bit 0 : Patch 0 enabled. */
+#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
+#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
+#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
+
+/* Register: PU_PATCHENSET */
+/* Description: Patch enable register. */
+
+/* Bit 7 : Patch 7 enabled. */
+#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
+#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
+#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 6 : Patch 6 enabled. */
+#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
+#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
+#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 5 : Patch 5 enabled. */
+#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
+#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
+#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 4 : Patch 4 enabled. */
+#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
+#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
+#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 3 : Patch 3 enabled. */
+#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
+#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
+#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 2 : Patch 2 enabled. */
+#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
+#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
+#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 1 : Patch 1 enabled. */
+#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
+#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
+#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
+
+/* Bit 0 : Patch 0 enabled. */
+#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
+#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
+#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
+
+/* Register: PU_PATCHENCLR */
+/* Description: Patch disable register. */
+
+/* Bit 7 : Patch 7 enabled. */
+#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
+#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
+#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 6 : Patch 6 enabled. */
+#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
+#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
+#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 5 : Patch 5 enabled. */
+#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
+#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
+#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 4 : Patch 4 enabled. */
+#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
+#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
+#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 3 : Patch 3 enabled. */
+#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
+#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
+#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 2 : Patch 2 enabled. */
+#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
+#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
+#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 1 : Patch 1 enabled. */
+#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
+#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
+#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
+
+/* Bit 0 : Patch 0 enabled. */
+#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
+#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
+#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
+#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
+#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
+
+
+/* Peripheral: QDEC */
+/* Description: Rotary decoder. */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcuts for the QDEC. */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: QDEC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ACCOF event. */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on REPORTRDY event. */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on SAMPLERDY event. */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ACCOF event. */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on REPORTRDY event. */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on SAMPLERDY event. */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the QDEC. */
+
+/* Bit 0 : Enable or disable QDEC. */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity. */
+
+/* Bit 0 : LED output pin polarity. */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period. */
+
+/* Bits 2..0 : Sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value. */
+
+/* Bits 31..0 : Last sample taken in compliment to 2. */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to generate an EVENT_REPORTRDY. */
+
+/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable debouncer input filters. */
+
+/* Bit 0 : Enable debounce input filters. */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time LED is switched ON before the sample. */
+
+/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Accumulated double (error) transitions register. */
+
+/* Bits 3..0 : Accumulated double (error) transitions. */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
+
+/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+/* Register: QDEC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RADIO */
+/* Description: The radio. */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts for the radio. */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 5 : Shortcut between END event and START task. */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between END event and DISABLE task. */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and START task. */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RADIO_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on BCMATCH event. */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on RSSIEND event. */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 6 : Enable interrupt on DEVMISS event. */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 5 : Enable interrupt on DEVMATCH event. */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on DISABLED event. */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on END event. */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on PAYLOAD event. */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ADDRESS event. */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on BCMATCH event. */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on RSSIEND event. */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 6 : Disable interrupt on DEVMISS event. */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 5 : Disable interrupt on DEVMATCH event. */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on DISABLED event. */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on END event. */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on PAYLOAD event. */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ADDRESS event. */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status of received packet. */
+
+/* Bit 0 : CRC status of received packet. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
+
+/* Register: RADIO_CD */
+/* Description: Carrier detect. */
+
+/* Bit 0 : Carrier detect. */
+#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
+#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address. */
+
+/* Bits 2..0 : Logical address in which previous packet was received. */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: Received CRC. */
+
+/* Bits 23..0 : CRC field of previously received packet. */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index. */
+
+/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency. */
+
+/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power. */
+
+/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation. */
+
+/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration 0. */
+
+/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration 1. */
+
+/* Bit 25 : Packet whitening enable. */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
+
+/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0 to 3. */
+
+/* Bits 31..24 : Address prefix 3. Decision point: START task. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. Decision point: START task. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. Decision point: START task. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. Decision point: START task. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4 to 7. */
+
+/* Bits 31..24 : Address prefix 7. Decision point: START task. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. Decision point: START task. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. Decision point: START task. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. Decision point: START task. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select. */
+
+/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select. */
+
+/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration. */
+
+/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length. Decision point: START task. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial. */
+
+/* Bits 23..0 : CRC polynomial. Decision point: START task. */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value. */
+
+/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TEST */
+/* Description: Test features enable register. */
+
+/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
+#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
+#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
+
+/* Bit 0 : Constant carrier. Decision point: TXEN task. */
+#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
+#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in microseconds. */
+
+/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample. */
+
+/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state. */
+
+/* Bits 3..0 : Current radio state. */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
+#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
+#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
+#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
+#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
+#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
+#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
+#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
+#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value. */
+
+/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_DAP */
+/* Description: Device address prefix. */
+
+/* Bits 15..0 : Device address prefix. */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration. */
+
+/* Bit 15 : TxAdd for device address 7. */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6. */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5. */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4. */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3. */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2. */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1. */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0. */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7. */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 6 : Enable or disable device address matching using device address 6. */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 5 : Enable or disable device address matching using device address 5. */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 4 : Enable or disable device address matching using device address 4. */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 3 : Enable or disable device address matching using device address 3. */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 2 : Enable or disable device address matching using device address 2. */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 1 : Enable or disable device address matching using device address 1. */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 0 : Enable or disable device address matching using device address 0. */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
+
+/* Register: RADIO_OVERRIDE0 */
+/* Description: Trim value override register 0. */
+
+/* Bits 31..0 : Trim value override 0. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
+
+/* Register: RADIO_OVERRIDE1 */
+/* Description: Trim value override register 1. */
+
+/* Bits 31..0 : Trim value override 1. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
+
+/* Register: RADIO_OVERRIDE2 */
+/* Description: Trim value override register 2. */
+
+/* Bits 31..0 : Trim value override 2. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
+
+/* Register: RADIO_OVERRIDE3 */
+/* Description: Trim value override register 3. */
+
+/* Bits 31..0 : Trim value override 3. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
+
+/* Register: RADIO_OVERRIDE4 */
+/* Description: Trim value override register 4. */
+
+/* Bit 31 : Enable or disable override of default trim values. */
+#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
+#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
+
+/* Bits 27..0 : Trim value override 4. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator. */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts for the RNG. */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task. */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RNG_INTENSET */
+/* Description: Interrupt enable set register */
+
+/* Bit 0 : Enable interrupt on VALRDY event. */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RNG_INTENCLR */
+/* Description: Interrupt enable clear register */
+
+/* Bit 0 : Disable interrupt on VALRDY event. */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 0 : Digital error correction enable. */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
+
+/* Register: RNG_VALUE */
+/* Description: RNG random number. */
+
+/* Bits 7..0 : Generated random number. */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+/* Register: RNG_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0. */
+
+/* Register: RTC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] event. */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] event. */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] event. */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] event. */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on OVRFLW event. */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on TICK event. */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RTC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] event. */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] event. */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] event. */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] event. */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on OVRFLW event. */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on TICK event. */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RTC_EVTEN */
+/* Description: Configures event enable routing to PPI for each RTC event. */
+
+/* Bit 19 : COMPARE[3] event enable. */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 18 : COMPARE[2] event enable. */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 17 : COMPARE[1] event enable. */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 16 : COMPARE[0] event enable. */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 1 : OVRFLW event enable. */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 0 : TICK event enable. */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 1 : Enable routing to PPI of OVRFLW event. */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 0 : Enable routing to PPI of TICK event. */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 1 : Disable routing to PPI of OVRFLW event. */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 0 : Disable routing to PPI of TICK event. */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value. */
+
+/* Bits 23..0 : Counter value. */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
+
+/* Bits 11..0 : RTC PRESCALER value. */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Capture/compare registers. */
+
+/* Bits 23..0 : Compare value. */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+/* Register: RTC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPI */
+/* Description: SPI master 0. */
+
+/* Register: SPI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on READY event. */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI. */
+
+/* Bits 2..0 : Enable or disable SPI. */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
+#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
+
+/* Register: SPI_RXD */
+/* Description: RX data. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TX data. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI data rate. */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPIM */
+/* Description: SPI master with easyDMA 1. */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcuts for SPIM. */
+
+/* Bit 17 : Shortcut between END event and START task. */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: SPIM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on STARTED event. */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 8 : Enable interrupt on ENDTX event. */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 6 : Enable interrupt on END event. */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on ENDRX event. */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on STARTED event. */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 8 : Disable interrupt on ENDTX event. */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 6 : Disable interrupt on END event. */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on ENDRX event. */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM. */
+
+/* Bits 3..0 : Enable or disable SPIM. */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
+#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
+
+/* Register: SPIM_RXDDATA */
+/* Description: RXD register. */
+
+/* Bits 7..0 : RX data received. Double buffered. */
+#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPIM_TXDDATA */
+/* Description: TXD register. */
+
+/* Bits 7..0 : TX data to send. Double buffered. */
+#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. */
+
+/* Bits 31..0 : SPI master data rate. */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer. */
+
+/* Bits 31..0 : Data pointer. */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of buffer bytes to receive. */
+
+/* Bits 7..0 : Maximum number of buffer bytes to receive. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes received in the last transaction. */
+
+/* Bits 7..0 : Number of bytes received in the last transaction. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer. */
+
+/* Bits 31..0 : Data pointer. */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of buffer bytes to send. */
+
+/* Bits 7..0 : Maximum number of buffer bytes to send. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes sent in the last transaction. */
+
+/* Bits 7..0 : Number of bytes sent in the last transaction. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI slave 1. */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts for SPIS. */
+
+/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: SPIS_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on ACQUIRED event. */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on END event. */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on ACQUIRED event. */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on END event. */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status. */
+
+/* Bits 1..0 : Semaphore status. */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction. */
+
+/* Bit 1 : RX buffer overflow detected, and prevented. */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
+
+/* Bit 0 : TX buffer overread detected, and prevented. */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPIS. */
+
+/* Bits 2..0 : Enable or disable SPIS. */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
+#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
+
+/* Register: SPIS_MAXRX */
+/* Description: Maximum number of bytes in the receive buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
+#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
+#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
+
+/* Register: SPIS_AMOUNTRX */
+/* Description: Number of bytes received in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes received in last granted transaction. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
+
+/* Register: SPIS_MAXTX */
+/* Description: Maximum number of bytes in the transmit buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
+#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
+#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
+
+/* Register: SPIS_AMOUNTTX */
+/* Description: Number of bytes transmitted in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. */
+
+/* Bits 7..0 : Default character. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIS_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor. */
+
+/* Register: TEMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on DATARDY event. */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on DATARDY event. */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TEMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer 0. */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts for Timer. */
+
+/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TIMER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TIMER_MODE */
+/* Description: Timer Mode selection. */
+
+/* Bit 0 : Select Normal or Counter mode. */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
+
+/* Register: TIMER_BITMODE */
+/* Description: Sets timer behaviour. */
+
+/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
+
+/* Register: TIMER_PRESCALER */
+/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
+
+/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TWI */
+/* Description: Two-wire interface master 0. */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts for TWI. */
+
+/* Bit 1 : Shortcut between BB event and the STOP task. */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TWI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 18 : Enable interrupt on SUSPENDED event. */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 14 : Enable interrupt on BB event. */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXDSENT event. */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TWI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 18 : Disable interrupt on SUSPENDED event. */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 14 : Disable interrupt on BB event. */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXDSENT event. */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXDREADY event. */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Two-wire error source. Write error field to 1 to clear error. */
+
+/* Bit 2 : NACK received after sending a data byte. */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : NACK received after sending the address. */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable two-wire master. */
+
+/* Bits 2..0 : Enable or disable W2M */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
+#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
+
+/* Register: TWI_RXD */
+/* Description: RX data register. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TX data register. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: Two-wire frequency. */
+
+/* Bits 31..0 : Two-wire master clock frequency. */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the two-wire transfer. */
+
+/* Bits 6..0 : Two-wire address. */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter. */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts for UART. */
+
+/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: UART_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 17 : Enable interrupt on RXTO event. */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXRDY event. */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on RXRDY event. */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on NCTS event. */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on CTS event. */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: UART_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 17 : Disable interrupt on RXTO event. */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXRDY event. */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXRDY event. */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on NCTS event. */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on CTS event. */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source. Write error field to 1 to clear error. */
+
+/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART and acquire IOs. */
+
+/* Bits 2..0 : Enable or disable UART and acquire IOs. */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
+#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
+
+/* Register: UART_RXD */
+/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
+
+/* Bits 7..0 : RX data from previous transfer. Double buffered. */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register. */
+
+/* Bits 7..0 : TX data for transfer. */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: UART Baudrate. */
+
+/* Bits 31..0 : UART baudrate. */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control register. */
+
+/* Bits 3..1 : Include parity bit. */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
+#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
+
+/* Bit 0 : Hardware flow control. */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
+
+/* Register: UART_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration. */
+
+/* Register: UICR_RBPCONF */
+/* Description: Readback protection configuration. */
+
+/* Bits 15..8 : Readback protect all code in the device. */
+#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
+#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
+#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
+
+/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
+#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
+#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
+#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
+#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
+
+/* Register: UICR_XTALFREQ */
+/* Description: Reset value for CLOCK XTALFREQ register. */
+
+/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
+#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
+#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
+
+/* Register: UICR_FWID */
+/* Description: Firmware ID. */
+
+/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
+#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
+#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer. */
+
+/* Register: WDT_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on TIMEOUT event. */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: WDT_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on TIMEOUT event. */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Watchdog running status. */
+
+/* Bit 0 : Watchdog running status. */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status. */
+
+/* Bit 7 : Request status for RR[7]. */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
+
+/* Bit 6 : Request status for RR[6]. */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
+
+/* Bit 5 : Request status for RR[5]. */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
+
+/* Bit 4 : Request status for RR[4]. */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
+
+/* Bit 3 : Request status for RR[3]. */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
+
+/* Bit 2 : Request status for RR[2]. */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
+
+/* Bit 1 : Request status for RR[1]. */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
+
+/* Bit 0 : Request status for RR[0]. */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
+
+/* Register: WDT_RREN */
+/* Description: Reload request enable. */
+
+/* Bit 7 : Enable or disable RR[7] register. */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
+
+/* Bit 6 : Enable or disable RR[6] register. */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
+
+/* Bit 5 : Enable or disable RR[5] register. */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
+
+/* Bit 4 : Enable or disable RR[4] register. */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
+
+/* Bit 3 : Enable or disable RR[3] register. */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
+
+/* Bit 2 : Enable or disable RR[2] register. */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
+
+/* Bit 1 : Enable or disable RR[1] register. */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
+
+/* Bit 0 : Enable or disable RR[0] register. */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
+
+/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
+
+/* Register: WDT_RR */
+/* Description: Reload requests registers. */
+
+/* Bits 31..0 : Reload register. */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
+
+/* Register: WDT_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h
new file mode 100644
index 000000000..c9b012334
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h
@@ -0,0 +1,74 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+// #include "nrf.h"
+
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BNE loop
+ BX LR
+}
+#elif defined ( __ICCARM__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " BNE loop\n\t");
+}
+#elif defined ( __GNUC__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+ do
+ {
+ __ASM volatile (
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ );
+ } while (--number_of_us);
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c
new file mode 100644
index 000000000..cb98405fe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c
@@ -0,0 +1,134 @@
+/* Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+ be copied into the application project folder prior to its use! */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf51.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
+
+static bool is_manual_peripheral_setup_needed(void);
+static bool is_disabled_in_debug_needed(void);
+
+
+#if defined ( __CC_ARM )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#elif defined ( __ICCARM__ )
+ __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
+#elif defined ( __GNUC__ )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+void SystemInit(void)
+{
+ /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
+ It can also be done in the application main() function. */
+
+ /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
+ to enable the use of peripherals" found at Product Anomaly document for your device found at
+ https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
+ that do not need it is that the new peripherals in the second generation devices (LPCOMP for
+ example) will not be available. */
+ if (is_manual_peripheral_setup_needed())
+ {
+ *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
+ *(uint32_t volatile *)0x40006C18 = 0x00008000;
+ }
+
+ /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
+ register is incorrect" found at Product Anomaly document four your device found at
+ https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
+ if (is_disabled_in_debug_needed())
+ {
+ NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
+ }
+
+ // Start the external 32khz crystal oscillator.
+
+#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017)
+ NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
+#else
+ NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
+#endif
+ NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+ NRF_CLOCK->TASKS_LFCLKSTART = 1;
+
+ // Wait for the external oscillator to start up.
+ while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
+ // Do nothing.
+ }
+}
+
+static bool is_manual_peripheral_setup_needed(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+ {
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool is_disabled_in_debug_needed(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+ {
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*lint --flb "Leave library region" */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h
new file mode 100644
index 000000000..ae613609d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h
@@ -0,0 +1,68 @@
+/* Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef SYSTEM_NRF51_H
+#define SYSTEM_NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF51_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h
new file mode 100644
index 000000000..f757231b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h
@@ -0,0 +1,1247 @@
+
+/****************************************************************************************************//**
+ * @file LPC11U6x.h
+ *
+ * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
+ * LPC11U6x from .
+ *
+ * @version V0.4
+ * @date 22. October 2013
+ *
+ * @note Generated with SVDConv V2.81a
+ * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
+ *
+ * modified by Keil
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC11U6x
+ * @{
+ */
+
+#ifndef LPC11U6X_H
+#define LPC11U6X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+
+
+
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+
+
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
+ PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
+ PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
+ PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
+ PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
+ PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
+ PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
+ PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
+ PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
+ GINT0_IRQn = 8, /*!< 8 GINT0 */
+ GINT1_IRQn = 9, /*!< 9 GINT1 */
+ I2C1_IRQn = 10, /*!< 10 I2C1 */
+ USART1_4_IRQn = 11, /*!< 11 USART1_4 */
+ USART2_3_IRQn = 12, /*!< 12 USART2_3 */
+ SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
+ SSP1_IRQn = 14, /*!< 14 SSP1 */
+ I2C0_IRQn = 15, /*!< 15 I2C0 */
+ CT16B0_IRQn = 16, /*!< 16 CT16B0 */
+ CT16B1_IRQn = 17, /*!< 17 CT16B1 */
+ CT32B0_IRQn = 18, /*!< 18 CT32B0 */
+ CT32B1_IRQn = 19, /*!< 19 CT32B1 */
+ SSP0_IRQn = 20, /*!< 20 SSP0 */
+ USART0_IRQn = 21, /*!< 21 USART0 */
+ USB_IRQn = 22, /*!< 22 USB */
+ USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
+ ADC_A_IRQn = 24, /*!< 24 ADC_A */
+ RTC_IRQn = 25, /*!< 25 RTC */
+ BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
+ FLASH_IRQn = 27, /*!< 27 FLASH */
+ DMA_IRQn = 28, /*!< 28 DMA */
+ ADC_B_IRQn = 29, /*!< 29 ADC_B */
+ USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
+#define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
+#include "system_LPC11U6x.h" /*!< LPC11U6x System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C-bus controller (I2C0)
+ */
+
+typedef struct { /*!< I2C0 Structure */
+ __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
+ this register, the corresponding bit in the I2C control register
+ is set. Writing a zero has no effect on the corresponding bit
+ in the I2C control register. */
+ __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
+ detailed status codes that allow software to determine the next
+ action needed. */
+ __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
+ to be transmitted is written to this register. During master
+ or slave receive mode, data that has been received may be read
+ from this register. */
+ __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
+ time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
+ of the I2C clock. I2nSCLL and I2nSCLH together determine the
+ clock frequency generated by an I2C master and certain times
+ used in slave mode. */
+ __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
+ this register, the corresponding bit in the I2C control register
+ is cleared. Writing a zero has no effect on the corresponding
+ bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
+ __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
+ for operation of the I2C interface in slave mode, and is not
+ used in master mode. The least significant bit determines whether
+ a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
+ shift register will be transferred to the DATA_BUFFER automatically
+ after every nine bits (8 bits of data plus ACK or NACK) has
+ been received on the bus. */
+ __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+ __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
+ with I2ADR0 to determine an address match. The mask register
+ has no effect when comparing to the General Call address (0000000). */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< WWDT Structure */
+ __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
+ and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
+ the time-out value. */
+ __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
+ to this register reloads the Watchdog timer with the value contained
+ in WDTC. */
+ __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
+ the current value of the Watchdog timer. */
+ __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< USART0 Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
+ value. The full divisor is used to generate a baud rate from
+ the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
+ is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
+ to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
+ bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
+ value. The full divisor is used to generate a baud rate from
+ the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
+ and break generation. */
+ __IO uint32_t MCR; /*!< Modem Control Register. */
+ __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
+ status, including line errors. */
+ __I uint32_t MSR; /*!< Modem Status Register. */
+ __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
+ feature. */
+ __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
+ control) mode. */
+ __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
+ baud rate divider. */
+ __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
+ each bit time. */
+ __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
+ with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
+ the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
+ aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
+ for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ CT16B0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 16-bit counter/timers CT16B0 (CT16B0)
+ */
+
+typedef struct { /*!< CT16B0 Structure */
+ __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
+ The IR can be read to identify which of eight possible interrupt
+ sources are pending. */
+ __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
+ Counter functions. The Timer Counter can be disabled or reset
+ through the TCR. */
+ __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
+ of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
+ to this value, the next clock increments the TC and clears the
+ PC. */
+ __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
+ to the value stored in PR. When the value in PR is reached,
+ the TC is incremented and the PC is cleared. The PC is observable
+ and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
+ is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
+ capture inputs are used to load the Capture Registers and whether
+ or not an interrupt is generated when a capture takes place. */
+ __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
+ and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+ __I uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
+ mode, and in Counter mode selects the signal and edge(s) for
+ counting. */
+ __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
+ match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B0_Type;
+
+
+/* ================================================================================ */
+/* ================ CT32B0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 32-bit counter/timers CT32B0 (CT32B0)
+ */
+
+typedef struct { /*!< CT32B0 Structure */
+ __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
+ The IR can be read to identify which of eight possible interrupt
+ sources are pending. */
+ __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
+ Counter functions. The Timer Counter can be disabled or reset
+ through the TCR. */
+ __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
+ of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
+ to this value, the next clock increments the TC and clears the
+ PC. */
+ __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
+ to the value stored in PR. When the value in PR is reached,
+ the TC is incremented and the PC is cleared. The PC is observable
+ and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
+ is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
+ TC, stop both the TC and PC, and/or generate an interrupt every
+ time MR0 matches the TC. */
+ __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
+ capture inputs are used to load the Capture Registers and whether
+ or not an interrupt is generated when a capture takes place. */
+ __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
+ is an event on the CAP input. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
+ and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
+ mode, and in Counter mode selects the signal and edge(s) for
+ counting. */
+ __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
+ match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B0_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
+ */
+
+typedef struct { /*!< ADC Structure */
+ __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
+ bits for each sequence and the A/D power-down bit. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
+ and channel selection for conversion sequence-A. Also specifies
+ interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
+ and channel selection for conversion sequence-B. Also specifies
+ interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-B */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
+ of the most recent conversion completed on channel 0. */
+ __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
+ threshold compare registers are to be used for each channel */
+ __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
+ bits that enable the sequence-A, sequence-B, threshold compare
+ and data overrun interrupts to be generated. */
+ __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
+ and the individual component overrun and threshold-compare flags.
+ (The overrun bits replicate information stored in the result
+ registers). */
+ __IO uint32_t TRM; /*!< ADC trim register. */
+} LPC_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Real-Time Clock (RTC) (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+ __IO uint32_t CTRL; /*!< RTC control register */
+ __IO uint32_t MATCH; /*!< RTC match register */
+ __IO uint32_t COUNT; /*!< RTC counter register */
+ __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
+} LPC_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ DMATRIGMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
+ */
+
+typedef struct { /*!< DMATRIGMUX Structure */
+ __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
+} LPC_DMATRIGMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
+ */
+
+typedef struct { /*!< PMU Structure */
+ __IO uint32_t PCON; /*!< Power control register */
+ __IO uint32_t GPREG0; /*!< General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< Deep power down control register */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0; /*!< Signature Word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ SSP0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SSP/SPI (SSP0)
+ */
+
+typedef struct { /*!< SSP0 Structure */
+ __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
+ and data size. */
+ __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
+ the receive FIFO. */
+ __I uint32_t SR; /*!< Status Register */
+ __IO uint32_t CPSR; /*!< Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
+} LPC_SSP0_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
+ */
+
+typedef struct { /*!< IOCON Structure */
+ __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
+ __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
+ __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
+ __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
+} LPC_IOCON_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
+ */
+
+typedef struct { /*!< SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< USB PLL status */
+ __I uint32_t RESERVED0;
+ __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
+ __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
+ __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
+ __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
+ of USART1 to USART4 */
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t USBCLKSEL; /*!< USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
+ __I uint32_t RESERVED8;
+ __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
+ __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
+ __I uint32_t RESERVED9;
+ __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
+ __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
+ __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
+ __I uint32_t RESERVED10[10];
+ __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
+ __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
+ __I uint32_t RESERVED11[5];
+ __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
+ __IO uint32_t NMISRC; /*!< NMI Source Control */
+ union {
+ __IO uint32_t PINTSEL[8];
+ struct {
+ __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
+ };
+ };
+ __IO uint32_t USBCLKCTRL; /*!< USB clock control */
+ __I uint32_t USBCLKST; /*!< USB clock status */
+ __I uint32_t RESERVED12[25];
+ __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED14[6];
+ __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< Power configuration register */
+ __I uint32_t RESERVED15[110];
+ __I uint32_t DEVICE_ID; /*!< Device ID */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ USART4 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART4 (USART4)
+ */
+
+typedef struct { /*!< USART4 Structure */
+ __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
+ that typically are not changed during operation. */
+ __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
+ likely to change during operation. */
+ __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
+ here. Writing ones clears some bits in the register. Some bits
+ can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
+ interrupt enable bit for each potential USART interrupt. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
+ of bits in the INTENSET register. Writing a 1 to any implemented
+ bit position causes the corresponding bit to be cleared. */
+ __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
+ __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
+ received with the current USART receive status. Allows DMA or
+ software to recover incoming data and status together. */
+ __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
+ __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
+ value. */
+ __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
+ enabled. */
+ __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
+ __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
+} LPC_USART4_Type;
+
+
+/* ================================================================================ */
+/* ================ GINT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief GPIO group interrupt 0 (GINT0)
+ */
+
+typedef struct { /*!< GINT0 Structure */
+ __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
+} LPC_GINT0_Type;
+
+
+/* ================================================================================ */
+/* ================ USB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USB device controller (USB)
+ */
+
+typedef struct { /*!< USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
+ __IO uint32_t LPM; /*!< Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< USB interrupt status register */
+ __IO uint32_t INTEN; /*!< USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
+ __I uint32_t RESERVED0;
+ __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< CRC Structure */
+ __IO uint32_t MODE; /*!< CRC mode register */
+ __IO uint32_t SEED; /*!< CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< CRC data register */
+ __I uint32_t SUM; /*!< CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
+ */
+
+typedef struct { /*!< DMA Structure */
+ __IO uint32_t CTRL; /*!< DMA control. */
+ __I uint32_t INTSTAT; /*!< Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
+ */
+
+typedef struct { /*!< SCT0 Structure */
+ __IO uint32_t CONFIG; /*!< SCT configuration register */
+ __IO uint32_t CTRL; /*!< SCT control register */
+ __IO uint32_t LIMIT; /*!< SCT limit register */
+ __IO uint32_t HALT; /*!< SCT halt condition register */
+ __IO uint32_t STOP; /*!< SCT stop condition register */
+ __IO uint32_t START; /*!< SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< SCT counter register */
+ __IO uint32_t STATE; /*!< SCT state register */
+ __I uint32_t INPUT; /*!< SCT input register */
+ __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
+ __IO uint32_t RES; /*!< SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< SCT event flag register */
+ __IO uint32_t CONEN; /*!< SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
+
+ union {
+ __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
+ REGMODE4 = 0 */
+ };
+ __I uint32_t RESERVED2[59];
+
+ union {
+ __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
+ = 1 */
+ __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
+ = 0 */
+ };
+ __I uint32_t RESERVED3[59];
+ __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
+ __I uint32_t RESERVED4[116];
+ __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
+} LPC_SCT0_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< GPIO_PORT Structure */
+ __IO uint8_t B[88]; /*!< Byte pin registers */
+ __I uint32_t RESERVED0[42];
+ __IO uint32_t W[88]; /*!< Word pin registers */
+ __I uint32_t RESERVED1[1896];
+ __IO uint32_t DIR[3]; /*!< Port Direction registers */
+ __I uint32_t RESERVED2[29];
+ __IO uint32_t MASK[3]; /*!< Port Mask register */
+ __I uint32_t RESERVED3[29];
+ __IO uint32_t PIN[3]; /*!< Port pin register */
+ __I uint32_t RESERVED4[29];
+ __IO uint32_t MPIN[3]; /*!< Masked port register */
+ __I uint32_t RESERVED5[29];
+ __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
+ __I uint32_t RESERVED6[29];
+ __O uint32_t CLR[3]; /*!< Clear port */
+ __I uint32_t RESERVED7[29];
+ __O uint32_t NOT[3]; /*!< Toggle port */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ PINT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interruptand pattern match (PINT) (PINT)
+ */
+
+typedef struct { /*!< PINT Structure */
+ __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
+ __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
+ __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
+ __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
+ register */
+ __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
+ __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
+ __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
+} LPC_PINT_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_I2C0_BASE 0x40000000UL
+#define LPC_WWDT_BASE 0x40004000UL
+#define LPC_USART0_BASE 0x40008000UL
+#define LPC_CT16B0_BASE 0x4000C000UL
+#define LPC_CT16B1_BASE 0x40010000UL
+#define LPC_CT32B0_BASE 0x40014000UL
+#define LPC_CT32B1_BASE 0x40018000UL
+#define LPC_ADC_BASE 0x4001C000UL
+#define LPC_I2C1_BASE 0x40020000UL
+#define LPC_RTC_BASE 0x40024000UL
+#define LPC_DMATRIGMUX_BASE 0x40028000UL
+#define LPC_PMU_BASE 0x40038000UL
+#define LPC_FLASHCTRL_BASE 0x4003C000UL
+#define LPC_SSP0_BASE 0x40040000UL
+#define LPC_IOCON_BASE 0x40044000UL
+#define LPC_SYSCON_BASE 0x40048000UL
+#define LPC_USART4_BASE 0x4004C000UL
+#define LPC_SSP1_BASE 0x40058000UL
+#define LPC_GINT0_BASE 0x4005C000UL
+#define LPC_GINT1_BASE 0x40060000UL
+#define LPC_USART1_BASE 0x4006C000UL
+#define LPC_USART2_BASE 0x40070000UL
+#define LPC_USART3_BASE 0x40074000UL
+#define LPC_USB_BASE 0x40080000UL
+#define LPC_CRC_BASE 0x50000000UL
+#define LPC_DMA_BASE 0x50004000UL
+#define LPC_SCT0_BASE 0x5000C000UL
+#define LPC_SCT1_BASE 0x5000E000UL
+#define LPC_GPIO_PORT_BASE 0xA0000000UL
+#define LPC_PINT_BASE 0xA0004000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
+#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
+#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
+#define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
+#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
+#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
+#define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
+#define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
+#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC11U6x */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC11U6x_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct
new file mode 100644
index 000000000..8a9325406
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
+ ; 32kB (0x8000) - 0x100 = 0x7F00
+ RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.s
new file mode 100644
index 000000000..7a331f18c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.s
@@ -0,0 +1,244 @@
+;/**************************************************************************//**
+; * @file startup_LPC11U6x.s
+; * @brief CMSIS Cortex-M0+ Core Device Startup File for
+; * NXP LPC11U6x Device Series
+; * @version V1.00
+; * @date 22. October 2013
+; *
+; * @note
+; * Copyright (C) 2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
+ DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
+ DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
+ DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
+ DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
+ DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
+ DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
+ DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
+ DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
+ DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
+ DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
+ DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
+ DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
+ DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
+ DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
+ DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
+ DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
+ DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
+ DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
+ DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
+ DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
+ DCD USART0_IRQHandler ; 16+21 USART0 interrupt
+ DCD USB_IRQHandler ; 16+22 USB interrupt
+ DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
+ DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
+ DCD RTC_IRQHandler ; 16+25 RTC interrupt
+ DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
+ DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
+ DCD DMA_IRQHandler ; 16+28 DMA interrupt
+ DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
+ DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
+ DCD 0 ; 16+31 Reserved
+
+; <h> Code Read Protection
+; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
+; <0x12345678=>CRP Level 1
+; <0x87654321=>CRP Level 2
+; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
+; <0x4E697370=>NO ISP (ARE YOU SURE?)
+; </h>
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+ DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT PIN_INT0_IRQHandler [WEAK]
+ EXPORT PIN_INT1_IRQHandler [WEAK]
+ EXPORT PIN_INT2_IRQHandler [WEAK]
+ EXPORT PIN_INT3_IRQHandler [WEAK]
+ EXPORT PIN_INT4_IRQHandler [WEAK]
+ EXPORT PIN_INT5_IRQHandler [WEAK]
+ EXPORT PIN_INT6_IRQHandler [WEAK]
+ EXPORT PIN_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT USART1_4_IRQHandler [WEAK]
+ EXPORT USART2_3_IRQHandler [WEAK]
+ EXPORT SCT0_1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT CT16B0_IRQHandler [WEAK]
+ EXPORT CT16B1_IRQHandler [WEAK]
+ EXPORT CT32B0_IRQHandler [WEAK]
+ EXPORT CT32B1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQ_IRQHandler [WEAK]
+ EXPORT ADC_A_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT BOD_WDT_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT ADC_B_IRQHandler [WEAK]
+ EXPORT USBWAKEUP_IRQHandler [WEAK]
+
+PIN_INT0_IRQHandler
+PIN_INT1_IRQHandler
+PIN_INT2_IRQHandler
+PIN_INT3_IRQHandler
+PIN_INT4_IRQHandler
+PIN_INT5_IRQHandler
+PIN_INT6_IRQHandler
+PIN_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+I2C1_IRQHandler
+USART1_4_IRQHandler
+USART2_3_IRQHandler
+SCT0_1_IRQHandler
+SSP1_IRQHandler
+I2C0_IRQHandler
+CT16B0_IRQHandler
+CT16B1_IRQHandler
+CT32B0_IRQHandler
+CT32B1_IRQHandler
+SSP0_IRQHandler
+USART0_IRQHandler
+USB_IRQHandler
+USB_FIQ_IRQHandler
+ADC_A_IRQHandler
+RTC_IRQHandler
+BOD_WDT_IRQHandler
+FLASH_IRQHandler
+DMA_IRQHandler
+ADC_B_IRQHandler
+USBWAKEUP_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct
new file mode 100644
index 000000000..8a9325406
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
+ ; 32kB (0x8000) - 0x100 = 0x7F00
+ RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s
new file mode 100644
index 000000000..7a331f18c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s
@@ -0,0 +1,244 @@
+;/**************************************************************************//**
+; * @file startup_LPC11U6x.s
+; * @brief CMSIS Cortex-M0+ Core Device Startup File for
+; * NXP LPC11U6x Device Series
+; * @version V1.00
+; * @date 22. October 2013
+; *
+; * @note
+; * Copyright (C) 2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
+ DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
+ DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
+ DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
+ DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
+ DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
+ DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
+ DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
+ DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
+ DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
+ DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
+ DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
+ DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
+ DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
+ DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
+ DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
+ DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
+ DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
+ DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
+ DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
+ DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
+ DCD USART0_IRQHandler ; 16+21 USART0 interrupt
+ DCD USB_IRQHandler ; 16+22 USB interrupt
+ DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
+ DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
+ DCD RTC_IRQHandler ; 16+25 RTC interrupt
+ DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
+ DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
+ DCD DMA_IRQHandler ; 16+28 DMA interrupt
+ DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
+ DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
+ DCD 0 ; 16+31 Reserved
+
+; <h> Code Read Protection
+; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
+; <0x12345678=>CRP Level 1
+; <0x87654321=>CRP Level 2
+; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
+; <0x4E697370=>NO ISP (ARE YOU SURE?)
+; </h>
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+ DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT PIN_INT0_IRQHandler [WEAK]
+ EXPORT PIN_INT1_IRQHandler [WEAK]
+ EXPORT PIN_INT2_IRQHandler [WEAK]
+ EXPORT PIN_INT3_IRQHandler [WEAK]
+ EXPORT PIN_INT4_IRQHandler [WEAK]
+ EXPORT PIN_INT5_IRQHandler [WEAK]
+ EXPORT PIN_INT6_IRQHandler [WEAK]
+ EXPORT PIN_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT USART1_4_IRQHandler [WEAK]
+ EXPORT USART2_3_IRQHandler [WEAK]
+ EXPORT SCT0_1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT CT16B0_IRQHandler [WEAK]
+ EXPORT CT16B1_IRQHandler [WEAK]
+ EXPORT CT32B0_IRQHandler [WEAK]
+ EXPORT CT32B1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQ_IRQHandler [WEAK]
+ EXPORT ADC_A_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT BOD_WDT_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT ADC_B_IRQHandler [WEAK]
+ EXPORT USBWAKEUP_IRQHandler [WEAK]
+
+PIN_INT0_IRQHandler
+PIN_INT1_IRQHandler
+PIN_INT2_IRQHandler
+PIN_INT3_IRQHandler
+PIN_INT4_IRQHandler
+PIN_INT5_IRQHandler
+PIN_INT6_IRQHandler
+PIN_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+I2C1_IRQHandler
+USART1_4_IRQHandler
+USART2_3_IRQHandler
+SCT0_1_IRQHandler
+SSP1_IRQHandler
+I2C0_IRQHandler
+CT16B0_IRQHandler
+CT16B1_IRQHandler
+CT32B0_IRQHandler
+CT32B1_IRQHandler
+SSP0_IRQHandler
+USART0_IRQHandler
+USB_IRQHandler
+USB_FIQ_IRQHandler
+ADC_A_IRQHandler
+RTC_IRQHandler
+BOD_WDT_IRQHandler
+FLASH_IRQHandler
+DMA_IRQHandler
+ADC_B_IRQHandler
+USBWAKEUP_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld
new file mode 100644
index 000000000..873774403
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld
@@ -0,0 +1,235 @@
+/*Based on following file*/
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2014
+ * Generated linker script file for LPC11U68
+ * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
+ * By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
+ Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
+ Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
+ Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash256 = 0x0 + 0x40000;
+ __top_Ram0_32 = 0x10000000 + 0x8000;
+ __top_Ram1_2 = 0x20000000 + 0x800;
+ __top_Ram2USB_2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > MFlash256
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash256
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash256
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* possible MTB section for Ram1_2 */
+ .mtb_buffer_RAM2 (NOLOAD) :
+ {
+ KEEP(*(.mtb.$RAM2*))
+ KEEP(*(.mtb.$RAM1_2*))
+ } > Ram1_2
+
+ /* DATA section for Ram1_2 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$Ram1_2)
+ *(.data.$RAM2*)
+ *(.data.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2 AT>MFlash256
+ /* possible MTB section for Ram2USB_2 */
+ .mtb_buffer_RAM3 (NOLOAD) :
+ {
+ KEEP(*(.mtb.$RAM3*))
+ KEEP(*(.mtb.$RAM2USB_2*))
+ } > Ram2USB_2
+
+ /* DATA section for Ram2USB_2 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$Ram2USB_2)
+ *(.data.$RAM3*)
+ *(.data.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2 AT>MFlash256
+
+ /* MAIN DATA SECTION */
+
+ /* Default MTB section */
+ .mtb_buffer_default (NOLOAD) :
+ {
+ KEEP(*(.mtb*))
+ } > Ram0_32
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > Ram0_32
+
+
+ /* Main DATA section (Ram0_32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > Ram0_32 AT>MFlash256
+
+ /* BSS section for Ram1_2 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2
+ /* BSS section for Ram2USB_2 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ *(.bss.$RAM3*)
+ *(.bss.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > Ram0_32
+
+ /* NOINIT section for Ram1_2 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2
+ /* NOINIT section for Ram2USB_2 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > Ram0_32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_Ram0_32 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp
new file mode 100644
index 000000000..8a716d2da
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp
@@ -0,0 +1,181 @@
+extern "C" {
+
+#include "LPC11U6x.h"
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+extern void (* const g_pfnVectors[])(void);
+
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
+void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
+void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
+void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM0
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ 0, // Reserved
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC11U68
+ PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
+ PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
+ PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
+ PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
+ PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
+ PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
+ PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
+ PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
+ GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
+ GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
+ I2C1_IRQHandler, // 10 - I2C1
+ USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
+ USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
+ SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
+ SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
+ I2C0_IRQHandler, // 15 - I2C0
+ TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
+ TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
+ TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
+ TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
+ SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
+ USART0_IRQHandler, // 21 - USART0
+ USB_IRQHandler, // 22 - USB IRQ
+ USB_FIQHandler, // 23 - USB FIQ
+ ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
+ RTC_IRQHandler, // 25 - Real Time CLock interrpt
+ BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
+ FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
+ DMA_IRQHandler, // 28 - DMA interrupt
+ ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
+ USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
+ 0, // 31 - Reserved
+};
+/* End Vector */
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+
+/* Reset entry point*/
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ SectionTableAddr = &__data_section_table;
+
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ SystemInit();
+ if (software_init_hook)
+ software_init_hook();
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {}
+AFTER_VECTORS void HardFault_Handler (void) {}
+AFTER_VECTORS void MemManage_Handler (void) {}
+AFTER_VECTORS void BusFault_Handler (void) {}
+AFTER_VECTORS void UsageFault_Handler(void) {}
+AFTER_VECTORS void SVC_Handler (void) {}
+AFTER_VECTORS void DebugMon_Handler (void) {}
+AFTER_VECTORS void PendSV_Handler (void) {}
+AFTER_VECTORS void SysTick_Handler (void) {}
+AFTER_VECTORS void IntDefaultHandler (void) {}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld
new file mode 100644
index 000000000..a1b642df3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld
@@ -0,0 +1,237 @@
+/*Based on following file*/
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2014
+ * Generated linker script file for LPC11U68
+ * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
+ * By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
+ Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
+ Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
+ Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash256 = 0x0 + 0x40000;
+ __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;
+ __top_Ram1_2 = 0x20000000 + 0x800;
+ __top_Ram2USB_2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ *(.text.SystemInit)
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > MFlash256
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash256
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash256
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* possible MTB section for Ram1_2 */
+ .mtb_buffer_RAM2 (NOLOAD) :
+ {
+ KEEP(*(.mtb.$RAM2*))
+ KEEP(*(.mtb.$RAM1_2*))
+ } > Ram1_2
+
+ /* DATA section for Ram1_2 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$Ram1_2)
+ *(.data.$RAM2*)
+ *(.data.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2 AT>MFlash256
+ /* possible MTB section for Ram2USB_2 */
+ .mtb_buffer_RAM3 (NOLOAD) :
+ {
+ KEEP(*(.mtb.$RAM3*))
+ KEEP(*(.mtb.$RAM2USB_2*))
+ } > Ram2USB_2
+
+ /* DATA section for Ram2USB_2 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$Ram2USB_2)
+ *(.data.$RAM3*)
+ *(.data.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2 AT>MFlash256
+
+ /* MAIN DATA SECTION */
+
+ /* Default MTB section */
+ .mtb_buffer_default (NOLOAD) :
+ {
+ KEEP(*(.mtb*))
+ } > Ram0_32
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > Ram0_32
+
+
+ /* Main DATA section (Ram0_32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > Ram0_32 AT>MFlash256
+
+ /* BSS section for Ram1_2 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2
+ /* BSS section for Ram2USB_2 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ *(.bss.$RAM3*)
+ *(.bss.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > Ram0_32
+
+ /* NOINIT section for Ram1_2 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$Ram1_2*)
+ . = ALIGN(4) ;
+ } > Ram1_2
+ /* NOINIT section for Ram2USB_2 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$Ram2USB_2*)
+ . = ALIGN(4) ;
+ } > Ram2USB_2
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > Ram0_32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_Ram0_32 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.s
new file mode 100644
index 000000000..bbbf1e946
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.s
@@ -0,0 +1,93 @@
+//*****************************************************************************
+// aeabi_romdiv_patch.s
+// - Provides "patch" versions of the aeabi integer divide functions to
+// replace the standard ones pulled in from the C library, which vector
+// integer divides onto the rom division functions contained in
+// specific NXP MCUs such as LPC11Uxx and LPC12xx.
+// - Note that this patching will only occur if "__USE_ROMDIVIDE" is
+// defined for the project build for both the compiler and assembler.
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+#if defined(__USE_ROMDIVIDE)
+
+// Note that the romdivide "divmod" functions are not actually called from
+// the below code, as these functions are actually just wrappers to the
+// main romdivide "div" functions which push the quotient and remainder onto
+// the stack, so as to be compatible with the way that C returns structures.
+//
+// This is not needed for the aeabi "divmod" functions, as the compiler
+// automatically generates code that handles the return values being passed
+// back in registers when it generates inline calls to __aeabi_idivmod and
+// __aeabi_uidivmod routines.
+
+ .syntax unified
+ .text
+
+// ========= __aeabi_idiv & __aeabi_idivmod =========
+ .align 2
+ .section .text.__aeabi_idiv
+
+ .global __aeabi_idiv
+ .set __aeabi_idivmod, __aeabi_idiv // make __aeabi_uidivmod an alias
+ .global __aeabi_idivmod
+ .global pDivRom_idiv // pointer to the romdivide 'idiv' functione
+ .func
+ .thumb_func
+ .type __aeabi_idiv, %function
+
+__aeabi_idiv:
+ push {r4, lr}
+ ldr r3, =pDivRom_idiv
+ ldr r3, [r3, #0] // Load address of function
+ blx r3 // Call divide function
+ pop {r4, pc}
+
+ .endfunc
+
+// ======== __aeabi_uidiv & __aeabi_uidivmod ========
+ .align 2
+
+ .section .text.__aeabi_uidiv
+
+ .global __aeabi_uidiv
+ .set __aeabi_uidivmod, __aeabi_uidiv // make __aeabi_uidivmod an alias
+ .global __aeabi_uidivmod
+ .global pDivRom_uidiv // pointer to the romdivide 'uidiv' function
+ .func
+ .thumb_func
+ .type __aeabi_uidiv, %function
+
+__aeabi_uidiv:
+ push {r4, lr}
+ ldr r3, =pDivRom_uidiv
+ ldr r3, [r3, #0] // Load address of function
+ blx r3 // Call divide function
+ pop {r4, pc}
+
+ .endfunc
+
+#endif // (__USE_ROMDIVIDE)
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c
new file mode 100644
index 000000000..089a4f5dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c
@@ -0,0 +1,85 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
+//
+// mtb.c
+//
+// Optionally defines an array to be used as a buffer for Micro Trace
+// Buffer (MTB) instruction trace on Cortex-M0+ parts
+//
+// Version : 130502
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+
+/*******************************************************************
+ * Symbols controlling behavior of this code...
+ *
+ * __MTB_DISABLE
+ * If this symbol is defined, then the buffer array for the MTB
+ * will not be created.
+ *
+ * __MTB_BUFFER_SIZE
+ * Symbol specifying the sizer of the buffer array for the MTB.
+ * This must be a power of 2 in size, and fit into the available
+ * RAM. The MTB buffer will also be aligned to its 'size'
+ * boundary and be placed at the start of a RAM bank (which
+ * should ensure minimal or zero padding due to alignment).
+ *
+ * __MTB_RAM_BANK
+ * Allows MTB Buffer to be placed into specific RAM bank. When
+ * this is not defined, the "default" (first if there are
+ * several) RAM bank is used.
+ *******************************************************************/
+
+// Ignore with none Code Red tools
+#if defined (__CODE_RED)
+
+// Allow MTB to be removed by setting a define (via command line)
+#if !defined (__MTB_DISABLE)
+
+ // Allow for MTB buffer size being set by define set via command line
+ // Otherwise provide small default buffer
+ #if !defined (__MTB_BUFFER_SIZE)
+ #define __MTB_BUFFER_SIZE 128
+ #endif
+
+ // Check that buffer size requested is >0 bytes in size
+ #if (__MTB_BUFFER_SIZE > 0)
+ // Pull in MTB related macros
+ #include <cr_mtb_buffer.h>
+
+ // Check if MYTB buffer is to be placed in specific RAM bank
+ #if defined(__MTB_RAM_BANK)
+ // Place MTB buffer into explicit bank of RAM
+ __CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
+ #else
+ // Place MTB buffer into 'default' bank of RAM
+ __CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
+
+ #endif // defined(__MTB_RAM_BANK)
+
+ #endif // (__MTB_BUFFER_SIZE > 0)
+
+#endif // !defined (__MTB_DISABLE)
+
+#endif // defined (__CODE_RED)
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp
new file mode 100644
index 000000000..65cab8cac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp
@@ -0,0 +1,201 @@
+extern "C" {
+
+#include "LPC11U6x.h"
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
+
+// Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+// Location in memory that holds the address of the ROM Driver table
+#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
+// Variables to store addresses of idiv and udiv functions within MCU ROM
+unsigned int *pDivRom_idiv;
+unsigned int *pDivRom_uidiv;
+#endif
+
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+extern void (* const g_pfnVectors[])(void);
+
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
+void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
+void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
+void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM0
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ 0, // Reserved
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC11U68
+ PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
+ PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
+ PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
+ PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
+ PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
+ PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
+ PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
+ PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
+ GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
+ GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
+ I2C1_IRQHandler, // 10 - I2C1
+ USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
+ USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
+ SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
+ SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
+ I2C0_IRQHandler, // 15 - I2C0
+ TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
+ TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
+ TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
+ TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
+ SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
+ USART0_IRQHandler, // 21 - USART0
+ USB_IRQHandler, // 22 - USB IRQ
+ USB_FIQHandler, // 23 - USB FIQ
+ ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
+ RTC_IRQHandler, // 25 - Real Time CLock interrpt
+ BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
+ FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
+ DMA_IRQHandler, // 28 - DMA interrupt
+ ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
+ USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
+ 0, // 31 - Reserved
+};
+/* End Vector */
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+
+/* Reset entry point*/
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ SectionTableAddr = &__data_section_table;
+
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ // Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+ // Get address of Integer division routines function table in ROM
+ unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
+ // Get addresses of integer divide routines in ROM
+ // These address are then used by the code in aeabi_romdiv_patch.s
+ pDivRom_idiv = (unsigned int *)div_ptr[0];
+ pDivRom_uidiv = (unsigned int *)div_ptr[1];
+#endif
+
+
+ SystemInit();
+ if (software_init_hook)
+ software_init_hook();
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {}
+AFTER_VECTORS void HardFault_Handler (void) {}
+AFTER_VECTORS void MemManage_Handler (void) {}
+AFTER_VECTORS void BusFault_Handler (void) {}
+AFTER_VECTORS void UsageFault_Handler(void) {}
+AFTER_VECTORS void SVC_Handler (void) {}
+AFTER_VECTORS void DebugMon_Handler (void) {}
+AFTER_VECTORS void PendSV_Handler (void) {}
+AFTER_VECTORS void SysTick_Handler (void) {}
+AFTER_VECTORS void IntDefaultHandler (void) {}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf
new file mode 100644
index 000000000..4fa111c6f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf
@@ -0,0 +1,47 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000FF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000100;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __RAM1_start__ = 0x20000000;
+define symbol __RAM1_end__ = 0x200007FF;
+
+define symbol __RAM_USB_start__= 0x20004000;
+define symbol __RAM_USB_end__ = 0x200047FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
+define region RAM_USB_region = mem:[from __RAM_USB_start__ to __RAM_USB_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in RAM1_region { section .sram1 };
+place in RAM_USB_region { section .sram_usb };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s
new file mode 100644
index 000000000..30ade0e71
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s
@@ -0,0 +1,251 @@
+;/*****************************************************************************
+; * @file: startup_LPC11u6x.s
+; * @purpose: CMSIS Cortex-M0PLUS Core Device Startup File
+; * for the NXP LPC11u6x Device Series (manually edited)
+; * @version: V1.00
+; * @date: 19. October 2009
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ DCD PIN_INT0_IRQHandler ; Pin interrupt 0
+ DCD PIN_INT1_IRQHandler ; Pin interrupt 1
+ DCD PIN_INT2_IRQHandler ; Pin interrupt 2
+ DCD PIN_INT3_IRQHandler ; Pin interrupt 3
+ DCD PIN_INT4_IRQHandler ; Pin interrupt 4
+ DCD PIN_INT5_IRQHandler ; Pin interrupt 5
+ DCD PIN_INT6_IRQHandler ; Pin interrupt 6
+ DCD PIN_INT7_IRQHandler ; Pin interrupt 7
+ DCD GINT0_IRQHandler ; Port interrupt group 0
+ DCD GINT1_IRQHandler ; Port interrupt group 1
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD USART1_4_IRQHandler ; USARTS 1 and 4 shared interrupt
+ DCD USART2_3_IRQHandler ; USARTS 2 and 3 shared interrupt
+ DCD SCT0_1_IRQHandler ; SCT 0 and 1 shared interrupt
+ DCD SSP1_IRQHandler ; SSP1 interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD CT16B0_IRQHandler ; CT16B0 (16-bit Timer 0)
+ DCD CT16B1_IRQHandler ; CT16B1 (16-bit Timer 1)
+ DCD CT32B0_IRQHandler ; CT32B0 (32-bit Timer 0)
+ DCD CT32B1_IRQHandler ; CT32B0 (32-bit Timer 1)
+ DCD SSP0_IRQHandler ; SSP0 interrupt interrupt
+ DCD USART0_IRQHandler ; USART 0 interrupt interrupt
+ DCD USB_IRQHandler ; USB IRQ interrupt
+ DCD USB_FIQ_IRQHandler ; USB FIQ interrupt
+ DCD ADC_A_IRQHandler ; ADC A sequence (A/D Converter) interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD BOD_WDT_IRQHandler ; Shared BOD (Brownout Detect) and WDT interrupts
+ DCD FLASH_IRQHandler ; Flash Memory Controller interrupt
+ DCD DMA_IRQHandler ; DMA Controller interrupt
+ DCD ADC_B_IRQHandler ; ADC B sequence interrupt
+ DCD USBWakeup_IRQHandler ; USB wake-up interrupt
+ DCD Reserved_IRQHandler
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+ PUBWEAK Reserved_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+Reserved_IRQHandler
+ B .
+
+
+ PUBWEAK PIN_INT0_IRQHandler
+ PUBWEAK PIN_INT1_IRQHandler
+ PUBWEAK PIN_INT2_IRQHandler
+ PUBWEAK PIN_INT3_IRQHandler
+ PUBWEAK PIN_INT4_IRQHandler
+ PUBWEAK PIN_INT5_IRQHandler
+ PUBWEAK PIN_INT6_IRQHandler
+ PUBWEAK PIN_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK USART1_4_IRQHandler
+ PUBWEAK USART2_3_IRQHandler
+ PUBWEAK SCT0_1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK CT16B0_IRQHandler
+ PUBWEAK CT16B1_IRQHandler
+ PUBWEAK CT32B0_IRQHandler
+ PUBWEAK CT32B1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK USART0_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQ_IRQHandler
+ PUBWEAK ADC_A_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK BOD_WDT_IRQHandler
+ PUBWEAK FLASH_IRQHandler
+ PUBWEAK DMA_IRQHandler
+ PUBWEAK ADC_B_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+PIN_INT0_IRQHandler
+PIN_INT1_IRQHandler
+PIN_INT2_IRQHandler
+PIN_INT3_IRQHandler
+PIN_INT4_IRQHandler
+PIN_INT5_IRQHandler
+PIN_INT6_IRQHandler
+PIN_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+I2C1_IRQHandler
+USART1_4_IRQHandler
+USART2_3_IRQHandler
+SCT0_1_IRQHandler
+SSP1_IRQHandler
+I2C0_IRQHandler
+CT16B0_IRQHandler
+CT16B1_IRQHandler
+CT32B0_IRQHandler
+CT32B1_IRQHandler
+SSP0_IRQHandler
+USART0_IRQHandler
+USB_IRQHandler
+USB_FIQ_IRQHandler
+ADC_A_IRQHandler
+RTC_IRQHandler
+BOD_WDT_IRQHandler
+FLASH_IRQHandler
+DMA_IRQHandler
+ADC_B_IRQHandler
+USBWakeup_IRQHandler
+Default_Handler
+ B Default_Handler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h
new file mode 100644
index 000000000..539e1f32b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC11U6x.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c
new file mode 100644
index 000000000..ee0e4a718
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c
new file mode 100644
index 000000000..4523729e7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c
@@ -0,0 +1,574 @@
+/**************************************************************************//**
+ * @file system_LPC11U6x.c
+ * @brief CMSIS Cortex-M3 Device System Source File for
+ * NXP LPC11U6x Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11U6x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*- SystemCoreClock Configuration -------------------------------------------*/
+// <e0> SystemCoreClock Configuration
+#define CLOCK_SETUP 1
+//
+// <h> System Oscillator Control (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
+//
+// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
+// <0=> IRC Oscillator
+// <1=> Crystal Oscillator (SYSOSC)
+// <3=> RTC Oscillator (32 kHz)
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <e> Clock Configuration (Manual)
+#define CLOCK_SETUP_REG 1
+//
+// <h> WD Oscillator Setting (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+#define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
+//
+// <h> System PLL Setting (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
+//
+// <o.0..1> Main Clock Source Select (MAINCLKSEL)
+// <0=> IRC Oscillator
+// <1=> PLL Input
+// <2=> WD Oscillator
+// <3=> PLL Output
+#define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
+//
+// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
+// </e>
+//
+// <e> Clock Configuration (via ROM PLL API)
+#define CLOCK_SETUP_API 0
+//
+// <o> PLL API Mode Select
+// <0=> Exact
+// <1=> Less than or equal
+// <2=> Greater than or equal
+// <3=> As close as possible
+#define PLL_API_MODE_Val 0
+//
+// <o> CPU Frequency [Hz] <1000000-50000000:1000>
+#define PLL_API_FREQ_Val 48000000
+// </e>
+//
+// <e> USB Clock Configuration
+#define USB_CLOCK_SETUP 1
+// <h> USB PLL Control (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
+//
+// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
+// <0=> USB PLL out
+// <1=> Main clock
+#define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
+//
+// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
+// </e>
+//
+// </e>
+//
+// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
+// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
+//
+#define XTAL_CLK_Val 12000000
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
+#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
+#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
+#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
+ #if (CLOCK_SETUP_API == 1)
+ #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
+ #endif
+ #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
+ #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
+ #endif
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
+ #error "You must select either manual or API based Clock Configuration!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
+ #error "XTAL frequency is out of bounds"
+#endif
+
+#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
+ #error "PLL API Mode Select not valid"
+#endif
+
+#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
+ #error "CPU Frequency (API mode) not valid"
+#endif
+
+
+
+/*----------------------------------------------------------------------------
+ Calculate system core clock
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__RTC_OSC_CLK)
+ #else
+ #error "Oops"
+ #endif
+
+ #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+ #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+ #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+ #if (__FREQSEL == 0)
+ #error "WDTOSCCTRL.FREQSEL undefined!"
+ #elif (__FREQSEL == 1)
+ #define __OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #define __MAIN_CLOCK (__OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #error "Oops"
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+ #endif /* Clock Setup via Register */
+
+ #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
+ #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
+ #endif /* Clock Setup via PLL API */
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif /* CLOCK_SETUP */
+
+
+
+#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
+#include "power_api.h"
+
+typedef struct _ROM {
+ const unsigned p_dev0;
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const PWRD * pPWRD; /* ROM Power Management API */
+ const unsigned p_dev4;
+ const unsigned p_dev5;
+ const unsigned p_dev6;
+ const unsigned p_dev7;
+} ROM;
+
+/*----------------------------------------------------------------------------
+ PLL API Function
+ *----------------------------------------------------------------------------*/
+static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
+{
+ uint32_t cmd[5], res[5];
+ ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
+
+ cmd[0] = pllInFreq; /* PLL's input freq in KHz */
+ cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
+ cmd[2] = pllMode;
+ cmd[3] = 0; /* no timeout for PLL to lock */
+
+ /* Execute API call */
+ (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
+ if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
+ while(1); /* ... stay here */
+ }
+}
+#endif
+
+
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t oscClk = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: oscClk = 0; break;
+ case 1: oscClk = 500000; break;
+ case 2: oscClk = 800000; break;
+ case 3: oscClk = 1100000; break;
+ case 4: oscClk = 1400000; break;
+ case 5: oscClk = 1600000; break;
+ case 6: oscClk = 1800000; break;
+ case 7: oscClk = 2000000; break;
+ case 8: oscClk = 2200000; break;
+ case 9: oscClk = 2400000; break;
+ case 10: oscClk = 2600000; break;
+ case 11: oscClk = 2700000; break;
+ case 12: oscClk = 2900000; break;
+ case 13: oscClk = 3100000; break;
+ case 14: oscClk = 3200000; break;
+ case 15: oscClk = 3400000; break;
+ }
+ oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = oscClk;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+#define PDRUN_VALID_BITS 0x000025FFL
+#define PDRUN_RESERVED_ONE 0x0000C800L
+
+static void power_down_config(uint32_t val)
+{
+ volatile uint32_t tmp;
+ tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
+ tmp |= (val & PDRUN_VALID_BITS);
+ LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
+}
+
+static void power_up_config(uint32_t val)
+{
+ volatile uint32_t tmp;
+ tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
+ tmp &= ~(val & PDRUN_VALID_BITS);
+ LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ */
+void SystemInit (void) {
+#if (CLOCK_SETUP)
+ volatile uint32_t i;
+#endif
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ // Initialize XTALIN/XTALOUT pins
+ LPC_IOCON->PIO2_0 = 0x01;
+ LPC_IOCON->PIO2_1 = 0x01;
+
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ power_up_config(1<<5); /* Power-up sysosc */
+ for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ power_down_config(1<<7); /* Power-down SYSPLL */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ power_up_config(1<<7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif /* Clock Setup via Register */
+
+#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
+// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+// LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+// while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = 1;
+
+ setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
+#endif /* Clock Setup via PLL API */
+
+#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
+
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+
+ LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
+#endif
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
+#endif
+
+#endif /* Clock Setup */
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.h
new file mode 100644
index 000000000..fa09f481c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11U6x.h
+ * @brief CMSIS Cortex-M3 Device System Header File for
+ * NXP LPC11U6x Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11U6x_H
+#define __SYSTEM_LPC11U6x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11U6x_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h
new file mode 100644
index 000000000..bc3f737aa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h
@@ -0,0 +1,670 @@
+
+/****************************************************************************************************//**
+ * @file LPC11Uxx.h
+ *
+ *
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * default LPC11Uxx Device Series
+ *
+ * @version V0.1
+ * @date 21. March 2011
+ *
+ * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
+ *
+ * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
+ * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
+ *
+ *******************************************************************************************************/
+
+// ################################################################################
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
+// ################################################################################
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC11Uxx
+ * @{
+ */
+
+#ifndef __LPC11UXX_H__
+#define __LPC11UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
+FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
+ FLEX_INT1_IRQn = 1,
+ FLEX_INT2_IRQn = 2,
+ FLEX_INT3_IRQn = 3,
+ FLEX_INT4_IRQn = 4,
+ FLEX_INT5_IRQn = 5,
+ FLEX_INT6_IRQn = 6,
+ FLEX_INT7_IRQn = 7,
+ GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
+ GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
+ Reserved0_IRQn = 10, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 11,
+ Reserved2_IRQn = 12,
+ Reserved3_IRQn = 13,
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ USB_IRQn = 22, /*!< USB IRQ Interrupt */
+ USB_FIQn = 23, /*!< USB FIQ Interrupt */
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ Reserved4_IRQn = 28, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 29, /*!< Reserved Interrupt */
+ USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
+ Reserved6_IRQn = 31, /*!< Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
+
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
+ __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
+ __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
+ __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
+ __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
+union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
+ __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
+ */
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL;
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Timer -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
+ */
+
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
+} LPC_CTxxBx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
+ __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
+ __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
+ __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
+ __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
+ __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
+ __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
+ __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCONFIG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
+ __IO uint32_t PIO1_1;
+ __IO uint32_t PIO1_2;
+ __IO uint32_t PIO1_3;
+ __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6;
+ __IO uint32_t PIO1_7;
+ __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
+ __IO uint32_t PIO1_9;
+ __IO uint32_t PIO1_10;
+ __IO uint32_t PIO1_11;
+ __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17;
+ __IO uint32_t PIO1_18;
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30;
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED6[8];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED8[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED9[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
+ */
+
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INTx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
+ */
+
+typedef struct { /*!< (@ 0x40080000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /* 0x2000 */
+ uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /* 0x2080 */
+ uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /* 0x2100 */
+ uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /* 0x2180 */
+ uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /* 0x2200 */
+ uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /* 0x2280 */
+ uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /* 0x2300 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group LPC11Uxx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC11UXX_H__
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct
new file mode 100644
index 000000000..398efab55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
+ ER_IROM1 0x00000000 0xC000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s
new file mode 100644
index 000000000..0d0cd2f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct
new file mode 100644
index 000000000..5a6e12b24
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.s
new file mode 100644
index 000000000..88fa96f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct
new file mode 100644
index 000000000..093772cc0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.s
new file mode 100644
index 000000000..0d0cd2f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct
new file mode 100644
index 000000000..398efab55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
+ ER_IROM1 0x00000000 0xC000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s
new file mode 100644
index 000000000..0d0cd2f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct
new file mode 100644
index 000000000..99d9a6c20
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.s
new file mode 100644
index 000000000..0d0cd2f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct
new file mode 100644
index 000000000..2d8853b91
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s
new file mode 100644
index 000000000..69b9f3586
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct
new file mode 100644
index 000000000..2d8853b91
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.s
new file mode 100755
index 000000000..69b9f3586
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct
new file mode 100644
index 000000000..7a8a1e245
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.s
new file mode 100644
index 000000000..10ad58dc0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct
new file mode 100644
index 000000000..5a6e12b24
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.s
new file mode 100644
index 000000000..88fa96f8f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.s
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct
new file mode 100644
index 000000000..398efab55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
+ ER_IROM1 0x00000000 0xC000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s
new file mode 100644
index 000000000..bcc3899bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct
new file mode 100644
index 000000000..5a6e12b24
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.s
new file mode 100644
index 000000000..c75cb5e43
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct
new file mode 100644
index 000000000..093772cc0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.s
new file mode 100644
index 000000000..bcc3899bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct
new file mode 100644
index 000000000..398efab55
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
+ ER_IROM1 0x00000000 0xC000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s
new file mode 100644
index 000000000..bcc3899bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct
new file mode 100644
index 000000000..99d9a6c20
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.s
new file mode 100644
index 000000000..bcc3899bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct
new file mode 100644
index 000000000..7a8a1e245
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region (64k)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.s
new file mode 100644
index 000000000..9cf7bcd73
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct
new file mode 100644
index 000000000..ff71e26bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s
new file mode 100644
index 000000000..e8bb645b7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct
new file mode 100644
index 000000000..ff71e26bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.s
new file mode 100755
index 000000000..e8bb645b7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct
new file mode 100644
index 000000000..5a6e12b24
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.s
new file mode 100644
index 000000000..c75cb5e43
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.s
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10001800 ; Top of RAM from LPC11U
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ ; for LPC11Uxx (With USB)
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+ EXPORT NMI_Handler [WEAK]
+ EXPORT FLEX_INT0_IRQHandler [WEAK]
+ EXPORT FLEX_INT1_IRQHandler [WEAK]
+ EXPORT FLEX_INT2_IRQHandler [WEAK]
+ EXPORT FLEX_INT3_IRQHandler [WEAK]
+ EXPORT FLEX_INT4_IRQHandler [WEAK]
+ EXPORT FLEX_INT5_IRQHandler [WEAK]
+ EXPORT FLEX_INT6_IRQHandler [WEAK]
+ EXPORT FLEX_INT7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT USBWakeup_IRQHandler [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld
new file mode 100644
index 000000000..be3ac7861
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld
new file mode 100644
index 000000000..159019e26
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld
new file mode 100644
index 000000000..52168576b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld
new file mode 100644
index 000000000..be3ac7861
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld
new file mode 100644
index 000000000..a1a87cd4a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld
new file mode 100644
index 000000000..a1a87cd4a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld
new file mode 100644
index 000000000..a1a87cd4a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld
new file mode 100644
index 000000000..463c4287d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld
@@ -0,0 +1,152 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ RAMIO (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld
new file mode 100644
index 000000000..c2f8e6fe5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld
new file mode 100644
index 000000000..c2f8e6fe5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld
@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld
new file mode 100644
index 000000000..159019e26
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
new file mode 100644
index 000000000..2b695fd92
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
@@ -0,0 +1,218 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC11xx interrupts */
+ .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */
+ .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */
+ .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */
+ .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */
+ .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */
+ .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */
+ .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */
+ .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */
+ .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */
+ .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */
+ .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */
+ .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */
+ .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */
+ .long Default_Handler /* 29 13 */
+ .long SSP1_IRQHandler /* 30 14 SSP1 */
+ .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */
+ .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */
+ .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */
+ .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */
+ .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
+ .long SSP0_IRQHandler /* 36 20 SSP */
+ .long UART_IRQHandler /* 37 21 UART */
+ .long USB_IRQHandler /* 38 22 USB IRQ */
+ .long USB_FIQHandler /* 39 23 USB FIQ */
+ .long ADC_IRQHandler /* 40 24 ADC end of conversion */
+ .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
+ .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
+ .long Default_Handler /* 43 27 */
+ .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */
+ .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */
+ .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */
+ .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WAKEUP_IRQHandler
+ def_irq_default_handler SSP1_IRQHandler
+ def_irq_default_handler I2C_IRQHandler
+ def_irq_default_handler TIMER16_0_IRQHandler
+ def_irq_default_handler TIMER16_1_IRQHandler
+ def_irq_default_handler TIMER32_0_IRQHandler
+ def_irq_default_handler TIMER32_1_IRQHandler
+ def_irq_default_handler SSP0_IRQHandler
+ def_irq_default_handler UART_IRQHandler
+ def_irq_default_handler USB_IRQHandler
+ def_irq_default_handler USB_FIQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler PIOINT3_IRQHandler
+ def_irq_default_handler PIOINT2_IRQHandler
+ def_irq_default_handler PIOINT1_IRQHandler
+ def_irq_default_handler PIOINT0_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld
new file mode 100644
index 000000000..7a885a65e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld
@@ -0,0 +1,153 @@
+/* mbed - LPC11U24 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x8000;
+ __top_RamLoc8 = 0x10000000 + 0x2000;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld
new file mode 100644
index 000000000..0ec42868b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld
@@ -0,0 +1,155 @@
+/* mbed - LPC11U35 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x1F40;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld
new file mode 100644
index 000000000..0ec42868b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld
@@ -0,0 +1,155 @@
+/* mbed - LPC11U35 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x1F40;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld
new file mode 100644
index 000000000..55ee248fa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld
@@ -0,0 +1,157 @@
+/* mbed - LPC11U35 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamIo1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x1F40;
+ __top_RamIo1 = 0x20000000 + 0x800;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld
new file mode 100755
index 000000000..44b0354e8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld
@@ -0,0 +1,155 @@
+/* mbed - LPC11U35 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x1F40;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp
new file mode 100644
index 000000000..68163d3ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp
@@ -0,0 +1,167 @@
+extern "C" {
+
+#include "LPC11Uxx.h"
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
+
+ void ResetISR (void);
+WEAK void NMI_Handler (void);
+WEAK void HardFault_Handler (void);
+WEAK void SVC_Handler (void);
+WEAK void PendSV_Handler (void);
+WEAK void SysTick_Handler (void);
+WEAK void IntDefaultHandler (void);
+ void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void UART_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
+ void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ &_vStackTop,
+ ResetISR,
+ NMI_Handler,
+ HardFault_Handler,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ SVC_Handler,
+ 0,
+ 0,
+ PendSV_Handler,
+ SysTick_Handler,
+ FLEX_INT0_IRQHandler,
+ FLEX_INT1_IRQHandler,
+ FLEX_INT2_IRQHandler,
+ FLEX_INT3_IRQHandler,
+ FLEX_INT4_IRQHandler,
+ FLEX_INT5_IRQHandler,
+ FLEX_INT6_IRQHandler,
+ FLEX_INT7_IRQHandler,
+ GINT0_IRQHandler,
+ GINT1_IRQHandler,
+ 0,
+ 0,
+ 0,
+ 0,
+ SSP1_IRQHandler,
+ I2C_IRQHandler,
+ TIMER16_0_IRQHandler,
+ TIMER16_1_IRQHandler,
+ TIMER32_0_IRQHandler,
+ TIMER32_1_IRQHandler,
+ SSP0_IRQHandler,
+ UART_IRQHandler,
+ USB_IRQHandler,
+ USB_FIQHandler,
+ ADC_IRQHandler,
+ WDT_IRQHandler,
+ BOD_IRQHandler,
+ FMC_IRQHandler,
+ 0,
+ 0,
+ USBWakeup_IRQHandler,
+ 0,
+};
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table_end;
+
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Data Init
+ SectionTableAddr = &__data_section_table;
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // BSS Init
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ SystemInit();
+ if (software_init_hook) // give control to the RTOS
+ software_init_hook(); // this will also call __libc_init_array
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {while(1){}}
+AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
+AFTER_VECTORS void SVC_Handler (void) {while(1){}}
+AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
+AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
+AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
+
+#include <stdlib.h>
+
+void *operator new (size_t size) {return malloc(size);}
+void *operator new[](size_t size) {return malloc(size);}
+
+void operator delete (void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
+ return 0;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/LPC11U24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/LPC11U24.ld
new file mode 100644
index 000000000..6cbc461f7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/LPC11U24.ld
@@ -0,0 +1,207 @@
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ram LENGTH: 8KB - 0xC0 = 0xF40
+*/
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+
+ ram (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ usb_ram (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+
+ .heap (NOLOAD) :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+ {
+ *(.stack)
+ _estack = .;
+ PROVIDE(estack = .);
+ } >ram
+
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s
new file mode 100644
index 000000000..cc8ab7bc2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s
@@ -0,0 +1,112 @@
+ .equ Stack_Size, 0x80
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+ .equ Heap_Size, 0x80
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack
+ .long __cs3_reset
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVC_Handler
+ .long 0
+ .long 0
+ .long PendSV_Handler
+ .long SysTick_Handler
+
+ .long DEF_IRQHandler
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+ .thumb
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=__cs3_start_c
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ DEF_IRQHandler
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp
new file mode 100644
index 000000000..6fc5736da
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp
@@ -0,0 +1,79 @@
+#include "cmsis.h"
+#include <sys/types.h>
+#include <errno.h>
+
+extern "C" {
+
+struct SCS3Regions {
+ unsigned long Dummy;
+ unsigned long* InitRam;
+ unsigned long* StartRam;
+ unsigned long InitSizeRam;
+ unsigned long ZeroSizeRam;
+};
+
+extern unsigned long __cs3_regions;
+extern unsigned long __cs3_heap_start;
+
+int main(void);
+void __libc_init_array(void);
+void exit(int ErrorCode);
+
+static void *heap_pointer = NULL;
+
+void __cs3_start_c(void) {
+ static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
+ unsigned long* pulDest;
+ unsigned long* pulSrc;
+ unsigned long ByteCount;
+ unsigned long i;
+
+ pulSrc = pCS3Regions->InitRam;
+ pulDest = pCS3Regions->StartRam;
+ ByteCount = pCS3Regions->InitSizeRam;
+ if (pulSrc != pulDest) {
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = *(pulSrc++);
+ }
+ } else {
+ pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
+ }
+
+ ByteCount = pCS3Regions->ZeroSizeRam;
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = 0;
+ }
+
+ heap_pointer = &__cs3_heap_start;
+ __libc_init_array();
+ exit(main());
+}
+
+int _kill(int pid, int sig) {
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit(int status) {
+ exit(status);
+}
+
+int _getpid(void) {
+ return 1;
+}
+
+void *_sbrk(unsigned int incr) {
+ void *mem;
+
+ unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
+ if (next > __get_MSP()) {
+ mem = NULL;
+ } else {
+ mem = (void *)heap_pointer;
+ }
+ heap_pointer = (void *)next;
+
+ return mem;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf
new file mode 100644
index 000000000..82211b9d2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf
@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x100017DF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf
new file mode 100644
index 000000000..64a361e64
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf
@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0xA00;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf
new file mode 100644
index 000000000..5a70d38b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf
@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf
new file mode 100644
index 000000000..e351413f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define symbol __SRAM1_start__ = 0x20000000;
+define symbol __SRAM1_end__ = 0x200007FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
+place in SRAM1_region { section .SRAM1 };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf
new file mode 100644
index 000000000..1985c370e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000000C0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define symbol __SRAM1_start__ = 0x20000000;
+define symbol __SRAM1_end__ = 0x200007FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region SRAM1_region = mem:[from __SRAM1_start__ to __SRAM1_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
+place in SRAM1_region { section .SRAM1 };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf
new file mode 100644
index 000000000..2384f52e8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf
@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __URAM_start__ = 0x20004000;
+define symbol __URAM_end__ = 0x200047FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region URAM_region = mem:[from __URAM_start__ to __URAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in URAM_region { section USB_PACKET_MEMORY };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s
new file mode 100644
index 000000000..0d9b2ef00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.s
@@ -0,0 +1,333 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
+ DCD FLEX_INT1_IRQHandler
+ DCD FLEX_INT2_IRQHandler
+ DCD FLEX_INT3_IRQHandler
+ DCD FLEX_INT4_IRQHandler
+ DCD FLEX_INT5_IRQHandler
+ DCD FLEX_INT6_IRQHandler
+ DCD FLEX_INT7_IRQHandler
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD Reserved_IRQHandler
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD USB_IRQHandler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD Reserved_IRQHandler ; Reserved
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FMC_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK Reserved_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler:
+ B .
+HardFault_Handler:
+ B .
+MemManage_Handler:
+ B .
+BusFault_Handler:
+ B .
+UsageFault_Handler:
+ B .
+SVC_Handler:
+ B .
+DebugMon_Handler:
+ B .
+PendSV_Handler:
+ B .
+SysTick_Handler:
+ B .
+FLEX_INT0_IRQHandler:
+ B .
+FLEX_INT1_IRQHandler:
+ B .
+FLEX_INT2_IRQHandler:
+ B .
+FLEX_INT3_IRQHandler:
+ B .
+FLEX_INT4_IRQHandler:
+ B .
+FLEX_INT5_IRQHandler:
+ B .
+FLEX_INT6_IRQHandler:
+ B .
+FLEX_INT7_IRQHandler:
+ B .
+GINT0_IRQHandler:
+ B .
+GINT1_IRQHandler:
+ B .
+SSP1_IRQHandler:
+ B .
+I2C_IRQHandler:
+ B .
+TIMER16_0_IRQHandler:
+ B .
+TIMER16_1_IRQHandler:
+ B .
+TIMER32_0_IRQHandler:
+ B .
+TIMER32_1_IRQHandler:
+ B .
+SSP0_IRQHandler:
+ B .
+UART_IRQHandler:
+ B .
+USB_IRQHandler:
+ B .
+USB_FIQHandler:
+ B .
+ADC_IRQHandler:
+ B .
+WDT_IRQHandler:
+ B .
+BOD_IRQHandler:
+ B .
+FMC_IRQHandler:
+ B .
+USBWakeup_IRQHandler:
+ B .
+Reserved_IRQHandler:
+ B .
+Default_Handler:
+ B .
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h
new file mode 100644
index 000000000..4e3857913
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC11Uxx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c
new file mode 100644
index 000000000..4127988d6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ *
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ *
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
+ * - No flash accesses will go to ram, as there will be nothing there
+ * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ * - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
+ uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
+ for(i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ // We can always read vectors at 0x0, as the addresses are remapped
+ uint32_t *vectors = (uint32_t*)0;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h
new file mode 100644
index 000000000..324e79704
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/power_api.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/power_api.h
new file mode 100644
index 000000000..23296c5ff
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/power_api.h
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
+ * Project: NXP LPC11Uxx software example
+ *
+ * Description:
+ * Power API Header File for NXP LPC11Uxx Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __LPC11UXX_POWER_API_H__
+#define __LPC11UXX_POWER_API_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define PWRROMD_PRESENT
+
+typedef struct _PWRD {
+ void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
+ void (*set_power)(unsigned int cmd[], unsigned int resp[]);
+} PWRD;
+
+typedef struct _ROM {
+#ifdef USBROMD_PRESENT
+ const USB * pUSBD;
+#else
+ const unsigned p_usbd;
+#endif /* USBROMD_PRESENT */
+ const unsigned p_clib;
+ const unsigned p_cand;
+#ifdef PWRROMD_PRESENT
+ const PWRD * pPWRD;
+#else
+ const unsigned p_pwrd;
+#endif /* PWRROMD_PRESENT */
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const unsigned p_dev3;
+ const unsigned p_dev4;
+} ROM;
+
+//PLL setup related definitions
+#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
+#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
+#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
+#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
+
+#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
+#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
+#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
+#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
+#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
+
+//power setup elated definitions
+#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
+#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
+#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
+#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
+
+#define PARAM_CMD_SUCCESS 0 //power setting successfully found
+#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
+#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
+
+#define MAX_CLOCK_KHZ_PARAM 50000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11UXX_POWER_API_H__ */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.c
new file mode 100644
index 000000000..7c4d7e73c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+ * @file system_LPC11Uxx.c
+ * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC13xx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11Uxx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+//
+// <h> USB PLL Control Register (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o7.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o7.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
+// <o8.0..1> SEL: USB PLL Clock Source
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Source Select Register (USBCLKSEL)
+// <o9.0..1> SEL: System PLL Clock Source
+// <0=> USB PLL out
+// <1=> Main clock
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Divider Register (USBCLKDIV)
+// <o10.0..7> DIV: USB Clock Divider
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
+#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __IRC_OSC_CLK;
+ } else {
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __SYS_OSC_CLK;
+ } else {
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+
+#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
+
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+ LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
+#endif
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
+#endif
+
+#endif
+
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h
new file mode 100644
index 000000000..aaf73f705
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11Uxx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11Uxx_H
+#define __SYSTEM_LPC11Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11Uxx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h
new file mode 100644
index 000000000..3465e38f6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h
@@ -0,0 +1,602 @@
+/****************************************************************************
+ * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
+ * Project: NXP LPC11xx software example
+ *
+ * Description:
+ * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * NXP LPC11xx Device Series
+
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+
+****************************************************************************/
+#ifndef __LPC11xx_H__
+#define __LPC11xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
+ This file defines all structures and symbols for LPC11xx:
+ - Registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
+ WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
+ WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
+ WAKEUP2_IRQn = 2,
+ WAKEUP3_IRQn = 3,
+ WAKEUP4_IRQn = 4,
+ WAKEUP5_IRQn = 5,
+ WAKEUP6_IRQn = 6,
+ WAKEUP7_IRQn = 7,
+ WAKEUP8_IRQn = 8,
+ WAKEUP9_IRQn = 9,
+ WAKEUP10_IRQn = 10,
+ WAKEUP11_IRQn = 11,
+ WAKEUP12_IRQn = 12,
+ CAN_IRQn = 13, /*!< CAN Interrupt */
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ Reserved0_IRQn = 22, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 23,
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
+ EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
+ EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
+ EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC11xx_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_LPC11xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
+ uint32_t RESERVED1[1];
+ __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
+ __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
+ uint32_t RESERVED6[12];
+
+ __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
+ __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
+ __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED9[5];
+
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
+ uint32_t RESERVED10[18];
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
+
+ uint32_t RESERVED13[7];
+ __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
+ uint32_t RESERVED14[34];
+
+ __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
+ __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
+ __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
+ __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
+ __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
+ uint32_t RESERVED17[4];
+
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED15[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_SYSCON */
+
+
+/*------------- Pin Connect Block (IOCON) --------------------------------*/
+/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
+ uint32_t RESERVED0[1];
+ __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
+ __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
+ __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
+ __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
+ __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
+
+ __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
+ __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
+ __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
+ __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
+ __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
+ __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
+ __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
+ __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
+
+ __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
+ __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
+ __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
+ __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
+ __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
+ __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
+ __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
+ __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
+
+ __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
+ __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
+ __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
+ __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
+ __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
+ __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
+ __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
+
+ __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
+ __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
+ __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
+ __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
+ __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
+ __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
+ __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
+ __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
+
+ __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
+ __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
+ __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
+ __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
+ __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
+ __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
+ __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
+ __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
+
+ __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
+ __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
+ __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
+ __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
+ __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
+ __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_IOCON */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC11xx_PMU */
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
+ struct {
+ uint32_t RESERVED0[4095];
+ __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
+ };
+ };
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
+ __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
+ __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
+ __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
+ __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
+ __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
+ __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
+} LPC_GPIO_TypeDef;
+/*@}*/ /* end of group LPC11xx_GPIO */
+
+/*------------- Timer (TMR) --------------------------------------------------*/
+/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ union {
+ __IO uint32_t MR[4]; /*!< Offset: Match Register base */
+ struct{
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ };
+ };
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ uint32_t RESERVED1[2];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED2[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+ __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
+} LPC_TMR_TypeDef;
+/*@}*/ /* end of group LPC11xx_TMR */
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
+} LPC_UART_TypeDef;
+/*@}*/ /* end of group LPC11xx_UART */
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
+ __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
+ __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
+} LPC_SSP_TypeDef;
+/*@}*/ /* end of group LPC11xx_SSP */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+/*@}*/ /* end of group LPC11xx_I2C */
+
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
+ uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+ __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WDT_TypeDef;
+/*@}*/ /* end of group LPC11xx_WDT */
+
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+} LPC_ADC_TypeDef;
+/*@}*/ /* end of group LPC11xx_ADC */
+
+
+/*------------- CAN Controller (CAN) ----------------------------*/
+/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CNTL; /* 0x000 */
+ __IO uint32_t STAT;
+ __IO uint32_t EC;
+ __IO uint32_t BT;
+ __IO uint32_t INT;
+ __IO uint32_t TEST;
+ __IO uint32_t BRPE;
+ uint32_t RESERVED0;
+ __IO uint32_t IF1_CMDREQ; /* 0x020 */
+ __IO uint32_t IF1_CMDMSK;
+ __IO uint32_t IF1_MSK1;
+ __IO uint32_t IF1_MSK2;
+ __IO uint32_t IF1_ARB1;
+ __IO uint32_t IF1_ARB2;
+ __IO uint32_t IF1_MCTRL;
+ __IO uint32_t IF1_DA1;
+ __IO uint32_t IF1_DA2;
+ __IO uint32_t IF1_DB1;
+ __IO uint32_t IF1_DB2;
+ uint32_t RESERVED1[13];
+ __IO uint32_t IF2_CMDREQ; /* 0x080 */
+ __IO uint32_t IF2_CMDMSK;
+ __IO uint32_t IF2_MSK1;
+ __IO uint32_t IF2_MSK2;
+ __IO uint32_t IF2_ARB1;
+ __IO uint32_t IF2_ARB2;
+ __IO uint32_t IF2_MCTRL;
+ __IO uint32_t IF2_DA1;
+ __IO uint32_t IF2_DA2;
+ __IO uint32_t IF2_DB1;
+ __IO uint32_t IF2_DB2;
+ uint32_t RESERVED2[21];
+ __I uint32_t TXREQ1; /* 0x100 */
+ __I uint32_t TXREQ2;
+ uint32_t RESERVED3[6];
+ __I uint32_t ND1; /* 0x120 */
+ __I uint32_t ND2;
+ uint32_t RESERVED4[6];
+ __I uint32_t IR1; /* 0x140 */
+ __I uint32_t IR2;
+ uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /* 0x160 */
+ __I uint32_t MSGV2;
+ uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /* 0x180 */
+} LPC_CAN_TypeDef;
+/*@}*/ /* end of group LPC11xx_CAN */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
+
+/* AHB peripherals */
+#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
+#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
+#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
+#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
+#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11xx_H__ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c
new file mode 100644
index 000000000..b1fb04dd5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c
@@ -0,0 +1,367 @@
+/**************************************************************************//**
+ * @file system_LPC11xx.c
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
+ * for the NXP LPC11xx/LPC11Cxx Devices
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __IRC_OSC_CLK;
+ } else {
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __SYS_OSC_CLK;
+ } else {
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c
new file mode 100644
index 000000000..f321255d9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c
@@ -0,0 +1,367 @@
+/**************************************************************************//**
+ * @file system_LPC11xx.c
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
+ * for the NXP LPC11xx/LPC11Cxx Devices
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __IRC_OSC_CLK;
+ } else {
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __SYS_OSC_CLK;
+ } else {
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct
new file mode 100644
index 000000000..9fcb33a3e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct
@@ -0,0 +1,16 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors * 4 bytes = 0xC0 for remap
+ RW_IRAM1 (0x10000000+0xC0) (0x2000-0xC0) {
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.s
new file mode 100644
index 000000000..272c4c1ee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.s
@@ -0,0 +1,304 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC1114
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC1114
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SLWU_INT0_IRQHandler [WEAK]
+ EXPORT SLWU_INT1_IRQHandler [WEAK]
+ EXPORT SLWU_INT2_IRQHandler [WEAK]
+ EXPORT SLWU_INT3_IRQHandler [WEAK]
+ EXPORT SLWU_INT4_IRQHandler [WEAK]
+ EXPORT SLWU_INT5_IRQHandler [WEAK]
+ EXPORT SLWU_INT6_IRQHandler [WEAK]
+ EXPORT SLWU_INT7_IRQHandler [WEAK]
+ EXPORT SLWU_INT8_IRQHandler [WEAK]
+ EXPORT SLWU_INT9_IRQHandler [WEAK]
+ EXPORT SLWU_INT10_IRQHandler [WEAK]
+ EXPORT SLWU_INT11_IRQHandler [WEAK]
+ EXPORT SLWU_INT12_IRQHandler [WEAK]
+ EXPORT C_CAN_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT PIO_3_IRQHandler [WEAK]
+ EXPORT PIO_2_IRQHandler [WEAK]
+ EXPORT PIO_1_IRQHandler [WEAK]
+ EXPORT PIO_0_IRQHandler [WEAK]
+
+NMI_Handler
+
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct
new file mode 100644
index 000000000..44850e6a9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct
@@ -0,0 +1,16 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors * 4 bytes = 0xC0 for remap
+ RW_IRAM1 (0x10000000+0xC0) (0x1000-0xC0) {
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.s
new file mode 100644
index 000000000..2f24b504a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.s
@@ -0,0 +1,304 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC1114
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SLWU_INT0_IRQHandler [WEAK]
+ EXPORT SLWU_INT1_IRQHandler [WEAK]
+ EXPORT SLWU_INT2_IRQHandler [WEAK]
+ EXPORT SLWU_INT3_IRQHandler [WEAK]
+ EXPORT SLWU_INT4_IRQHandler [WEAK]
+ EXPORT SLWU_INT5_IRQHandler [WEAK]
+ EXPORT SLWU_INT6_IRQHandler [WEAK]
+ EXPORT SLWU_INT7_IRQHandler [WEAK]
+ EXPORT SLWU_INT8_IRQHandler [WEAK]
+ EXPORT SLWU_INT9_IRQHandler [WEAK]
+ EXPORT SLWU_INT10_IRQHandler [WEAK]
+ EXPORT SLWU_INT11_IRQHandler [WEAK]
+ EXPORT SLWU_INT12_IRQHandler [WEAK]
+ EXPORT C_CAN_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT PIO_3_IRQHandler [WEAK]
+ EXPORT PIO_2_IRQHandler [WEAK]
+ EXPORT PIO_1_IRQHandler [WEAK]
+ EXPORT PIO_0_IRQHandler [WEAK]
+
+NMI_Handler
+
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct
new file mode 100644
index 000000000..8868823c4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.s
new file mode 100644
index 000000000..fc39c49f4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.s
@@ -0,0 +1,292 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC1114
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC1114
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SLWU_INT0_IRQHandler [WEAK]
+ EXPORT SLWU_INT1_IRQHandler [WEAK]
+ EXPORT SLWU_INT2_IRQHandler [WEAK]
+ EXPORT SLWU_INT3_IRQHandler [WEAK]
+ EXPORT SLWU_INT4_IRQHandler [WEAK]
+ EXPORT SLWU_INT5_IRQHandler [WEAK]
+ EXPORT SLWU_INT6_IRQHandler [WEAK]
+ EXPORT SLWU_INT7_IRQHandler [WEAK]
+ EXPORT SLWU_INT8_IRQHandler [WEAK]
+ EXPORT SLWU_INT9_IRQHandler [WEAK]
+ EXPORT SLWU_INT10_IRQHandler [WEAK]
+ EXPORT SLWU_INT11_IRQHandler [WEAK]
+ EXPORT SLWU_INT12_IRQHandler [WEAK]
+ EXPORT C_CAN_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT PIO_3_IRQHandler [WEAK]
+ EXPORT PIO_2_IRQHandler [WEAK]
+ EXPORT PIO_1_IRQHandler [WEAK]
+ EXPORT PIO_0_IRQHandler [WEAK]
+
+NMI_Handler
+
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct
new file mode 100644
index 000000000..0a7772d0c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0xF40
+ RW_IRAM1 0x100000C0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.s
new file mode 100644
index 000000000..332771707
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.s
@@ -0,0 +1,292 @@
+;/*****************************************************************************
+; * @file: startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File
+; * for the NXP LPC11xx Device Series
+; * @version: V1.0
+; * @date: 25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Reserved_IRQHandler PROC
+ EXPORT Reserved_IRQHandler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; for LPC1114
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SLWU_INT0_IRQHandler [WEAK]
+ EXPORT SLWU_INT1_IRQHandler [WEAK]
+ EXPORT SLWU_INT2_IRQHandler [WEAK]
+ EXPORT SLWU_INT3_IRQHandler [WEAK]
+ EXPORT SLWU_INT4_IRQHandler [WEAK]
+ EXPORT SLWU_INT5_IRQHandler [WEAK]
+ EXPORT SLWU_INT6_IRQHandler [WEAK]
+ EXPORT SLWU_INT7_IRQHandler [WEAK]
+ EXPORT SLWU_INT8_IRQHandler [WEAK]
+ EXPORT SLWU_INT9_IRQHandler [WEAK]
+ EXPORT SLWU_INT10_IRQHandler [WEAK]
+ EXPORT SLWU_INT11_IRQHandler [WEAK]
+ EXPORT SLWU_INT12_IRQHandler [WEAK]
+ EXPORT C_CAN_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT TIMER16_0_IRQHandler [WEAK]
+ EXPORT TIMER16_1_IRQHandler [WEAK]
+ EXPORT TIMER32_0_IRQHandler [WEAK]
+ EXPORT TIMER32_1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT UART_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT PIO_3_IRQHandler [WEAK]
+ EXPORT PIO_2_IRQHandler [WEAK]
+ EXPORT PIO_1_IRQHandler [WEAK]
+ EXPORT PIO_0_IRQHandler [WEAK]
+
+NMI_Handler
+
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld
new file mode 100644
index 000000000..e5b873ddd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld
@@ -0,0 +1,149 @@
+/* Linker script for mbed LPC1114 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld
new file mode 100644
index 000000000..dd2e65da5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld
@@ -0,0 +1,149 @@
+/* Linker script for mbed LPC1114 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x0F40
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
new file mode 100644
index 000000000..f5155aedf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
@@ -0,0 +1,216 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC11xx interrupts */
+ .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */
+ .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */
+ .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */
+ .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */
+ .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */
+ .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */
+ .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */
+ .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */
+ .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */
+ .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */
+ .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */
+ .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */
+ .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */
+ .long Default_Handler /* 29 13 */
+ .long SSP1_IRQHandler /* 30 14 SSP1 */
+ .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */
+ .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */
+ .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */
+ .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */
+ .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
+ .long SSP0_IRQHandler /* 36 20 SSP */
+ .long UART_IRQHandler /* 37 21 UART */
+ .long Default_Handler /* 38 22 */
+ .long Default_Handler /* 39 23 */
+ .long ADC_IRQHandler /* 40 24 ADC end of conversion */
+ .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
+ .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
+ .long Default_Handler /* 43 27 */
+ .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */
+ .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */
+ .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */
+ .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WAKEUP_IRQHandler
+ def_irq_default_handler SSP1_IRQHandler
+ def_irq_default_handler I2C_IRQHandler
+ def_irq_default_handler TIMER16_0_IRQHandler
+ def_irq_default_handler TIMER16_1_IRQHandler
+ def_irq_default_handler TIMER32_0_IRQHandler
+ def_irq_default_handler TIMER32_1_IRQHandler
+ def_irq_default_handler SSP0_IRQHandler
+ def_irq_default_handler UART_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler PIOINT3_IRQHandler
+ def_irq_default_handler PIOINT2_IRQHandler
+ def_irq_default_handler PIOINT1_IRQHandler
+ def_irq_default_handler PIOINT0_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld
new file mode 100644
index 000000000..a9931373f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld
@@ -0,0 +1,135 @@
+/* mbed - LPC1114 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x0F40 /* 4k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x8000;
+ __top_RamLoc8 = 0x10000000 + 0x0F40;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ *(.text.SystemInit)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp
new file mode 100644
index 000000000..d5d330466
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp
@@ -0,0 +1,167 @@
+extern "C" {
+
+#include "LPC11xx.h"
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
+
+ void ResetISR (void);
+WEAK void NMI_Handler (void);
+WEAK void HardFault_Handler (void);
+WEAK void SVC_Handler (void);
+WEAK void PendSV_Handler (void);
+WEAK void SysTick_Handler (void);
+WEAK void IntDefaultHandler (void);
+ void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+ void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void UART_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
+ void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
+ void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ &_vStackTop,
+ ResetISR,
+ NMI_Handler,
+ HardFault_Handler,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ SVC_Handler,
+ 0,
+ 0,
+ PendSV_Handler,
+ SysTick_Handler,
+ FLEX_INT0_IRQHandler,
+ FLEX_INT1_IRQHandler,
+ FLEX_INT2_IRQHandler,
+ FLEX_INT3_IRQHandler,
+ FLEX_INT4_IRQHandler,
+ FLEX_INT5_IRQHandler,
+ FLEX_INT6_IRQHandler,
+ FLEX_INT7_IRQHandler,
+ GINT0_IRQHandler,
+ GINT1_IRQHandler,
+ 0,
+ 0,
+ 0,
+ 0,
+ SSP1_IRQHandler,
+ I2C_IRQHandler,
+ TIMER16_0_IRQHandler,
+ TIMER16_1_IRQHandler,
+ TIMER32_0_IRQHandler,
+ TIMER32_1_IRQHandler,
+ SSP0_IRQHandler,
+ UART_IRQHandler,
+ USB_IRQHandler,
+ USB_FIQHandler,
+ ADC_IRQHandler,
+ WDT_IRQHandler,
+ BOD_IRQHandler,
+ FMC_IRQHandler,
+ 0,
+ 0,
+ USBWakeup_IRQHandler,
+ 0,
+};
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table_end;
+
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Data Init
+ SectionTableAddr = &__data_section_table;
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // BSS Init
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ SystemInit();
+ if (software_init_hook) // give control to the RTOS
+ software_init_hook(); // this will also call __libc_init_array
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {while(1){}}
+AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
+AFTER_VECTORS void SVC_Handler (void) {while(1){}}
+AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
+AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
+AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
+
+#include <stdlib.h>
+
+void *operator new (size_t size) {return malloc(size);}
+void *operator new[](size_t size) {return malloc(size);}
+
+void operator delete (void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
+ return 0;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s
new file mode 100644
index 000000000..cc8ab7bc2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s
@@ -0,0 +1,112 @@
+ .equ Stack_Size, 0x80
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+ .equ Heap_Size, 0x80
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack
+ .long __cs3_reset
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVC_Handler
+ .long 0
+ .long 0
+ .long PendSV_Handler
+ .long SysTick_Handler
+
+ .long DEF_IRQHandler
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+ .thumb
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=__cs3_start_c
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ DEF_IRQHandler
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp
new file mode 100644
index 000000000..6fc5736da
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp
@@ -0,0 +1,79 @@
+#include "cmsis.h"
+#include <sys/types.h>
+#include <errno.h>
+
+extern "C" {
+
+struct SCS3Regions {
+ unsigned long Dummy;
+ unsigned long* InitRam;
+ unsigned long* StartRam;
+ unsigned long InitSizeRam;
+ unsigned long ZeroSizeRam;
+};
+
+extern unsigned long __cs3_regions;
+extern unsigned long __cs3_heap_start;
+
+int main(void);
+void __libc_init_array(void);
+void exit(int ErrorCode);
+
+static void *heap_pointer = NULL;
+
+void __cs3_start_c(void) {
+ static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
+ unsigned long* pulDest;
+ unsigned long* pulSrc;
+ unsigned long ByteCount;
+ unsigned long i;
+
+ pulSrc = pCS3Regions->InitRam;
+ pulDest = pCS3Regions->StartRam;
+ ByteCount = pCS3Regions->InitSizeRam;
+ if (pulSrc != pulDest) {
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = *(pulSrc++);
+ }
+ } else {
+ pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
+ }
+
+ ByteCount = pCS3Regions->ZeroSizeRam;
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = 0;
+ }
+
+ heap_pointer = &__cs3_heap_start;
+ __libc_init_array();
+ exit(main());
+}
+
+int _kill(int pid, int sig) {
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit(int status) {
+ exit(status);
+}
+
+int _getpid(void) {
+ return 1;
+}
+
+void *_sbrk(unsigned int incr) {
+ void *mem;
+
+ unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
+ if (next > __get_MSP()) {
+ mem = NULL;
+ } else {
+ mem = (void *)heap_pointer;
+ }
+ heap_pointer = (void *)next;
+
+ return mem;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf
new file mode 100644
index 000000000..ebf55e755
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s
new file mode 100644
index 000000000..8af59274d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.s
@@ -0,0 +1,299 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK Reserved_IRQHandler
+ PUBWEAK SLWU_INT0_IRQHandler
+ PUBWEAK SLWU_INT1_IRQHandler
+ PUBWEAK SLWU_INT2_IRQHandler
+ PUBWEAK SLWU_INT3_IRQHandler
+ PUBWEAK SLWU_INT4_IRQHandler
+ PUBWEAK SLWU_INT5_IRQHandler
+ PUBWEAK SLWU_INT6_IRQHandler
+ PUBWEAK SLWU_INT7_IRQHandler
+ PUBWEAK SLWU_INT8_IRQHandler
+ PUBWEAK SLWU_INT9_IRQHandler
+ PUBWEAK SLWU_INT10_IRQHandler
+ PUBWEAK SLWU_INT11_IRQHandler
+ PUBWEAK SLWU_INT12_IRQHandler
+ PUBWEAK C_CAN_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK PIO_3_IRQHandler
+ PUBWEAK PIO_2_IRQHandler
+ PUBWEAK PIO_1_IRQHandler
+ PUBWEAK PIO_0_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+Reserved_IRQHandler
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+Default_Handler
+ B Default_Handler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf
new file mode 100644
index 000000000..e52023155
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10000FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s
new file mode 100644
index 000000000..8af59274d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.s
@@ -0,0 +1,299 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ DATA
+
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0
+ DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1
+ DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2
+ DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3
+ DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4
+ DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5
+ DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6
+ DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7
+ DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8
+ DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9
+ DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10
+ DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11
+ DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12
+ DCD C_CAN_IRQHandler ; C_CAN
+ DCD SSP1_IRQHandler ; SSP1
+ DCD I2C_IRQHandler ; I2C
+ DCD TIMER16_0_IRQHandler ; 16-bit Timer0
+ DCD TIMER16_1_IRQHandler ; 16-bit Timer1
+ DCD TIMER32_0_IRQHandler ; 32-bit Timer0
+ DCD TIMER32_1_IRQHandler ; 32-bit Timer1
+ DCD SSP0_IRQHandler ; SSP0
+ DCD UART_IRQHandler ; UART
+ DCD Reserved_IRQHandler ; Reserved
+ DCD Reserved_IRQHandler ; Reserved
+ DCD ADC_IRQHandler ; A/D Converter
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Reserved_IRQHandler ; Reserved
+ DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3
+ DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2
+ DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1
+ DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0
+
+ ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+ DCD 0xFFFFFFFF ; Datafill
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK Reserved_IRQHandler
+ PUBWEAK SLWU_INT0_IRQHandler
+ PUBWEAK SLWU_INT1_IRQHandler
+ PUBWEAK SLWU_INT2_IRQHandler
+ PUBWEAK SLWU_INT3_IRQHandler
+ PUBWEAK SLWU_INT4_IRQHandler
+ PUBWEAK SLWU_INT5_IRQHandler
+ PUBWEAK SLWU_INT6_IRQHandler
+ PUBWEAK SLWU_INT7_IRQHandler
+ PUBWEAK SLWU_INT8_IRQHandler
+ PUBWEAK SLWU_INT9_IRQHandler
+ PUBWEAK SLWU_INT10_IRQHandler
+ PUBWEAK SLWU_INT11_IRQHandler
+ PUBWEAK SLWU_INT12_IRQHandler
+ PUBWEAK C_CAN_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK TIMER16_0_IRQHandler
+ PUBWEAK TIMER16_1_IRQHandler
+ PUBWEAK TIMER32_0_IRQHandler
+ PUBWEAK TIMER32_1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK UART_IRQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK PIO_3_IRQHandler
+ PUBWEAK PIO_2_IRQHandler
+ PUBWEAK PIO_1_IRQHandler
+ PUBWEAK PIO_0_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+Reserved_IRQHandler
+SLWU_INT0_IRQHandler
+SLWU_INT1_IRQHandler
+SLWU_INT2_IRQHandler
+SLWU_INT3_IRQHandler
+SLWU_INT4_IRQHandler
+SLWU_INT5_IRQHandler
+SLWU_INT6_IRQHandler
+SLWU_INT7_IRQHandler
+SLWU_INT8_IRQHandler
+SLWU_INT9_IRQHandler
+SLWU_INT10_IRQHandler
+SLWU_INT11_IRQHandler
+SLWU_INT12_IRQHandler
+C_CAN_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+PIO_3_IRQHandler
+PIO_2_IRQHandler
+PIO_1_IRQHandler
+PIO_0_IRQHandler
+Default_Handler
+ B Default_Handler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h
new file mode 100644
index 000000000..59ea73864
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h
@@ -0,0 +1,1768 @@
+#ifndef MBED_BITFIELDS_H
+#define MBED_BITFIELDS_H
+
+//! Massage  x for use in bitfield  name.
+#define BFN_PREP(x, name) ( ((x)<<name##_SHIFT) & name##_MASK )
+
+//! Get the value of bitfield  name from  y. Equivalent to (var=) y.name
+#define BFN_GET(y, name) ( ((y) & name##_MASK)>>name##_SHIFT )
+
+//! Set bitfield  name from  y to  x: y.name= x.
+#define BFN_SET(y, x, name) (y = ((y)&~name##_MASK) | BFN_PREP(x,name) )
+
+
+/* SYSMEMREMAP, address 0x4004 8000 */
+#define SYSMEMREMAP_MAP_MASK 0x0003 // System memory remap
+#define SYSMEMREMAP_MAP_SHIFT 0
+
+/* PRESETCTRL, address 0x4004 8004 */
+#define PRESETCTRL_SSP0_RST_N (1 << 0) // SPI0 reset control
+#define PRESETCTRL_I2C_RST_N (1 << 1) // I2C reset control
+#define PRESETCTRL_SSP1_RST_N (1 << 2) // SPI1 reset control
+#define PRESETCTRL_CAN_RST_N (1 << 3) // C_CAN reset control. See Section 3.1 for part specific details.
+
+/* SYSPLLCTRL, address 0x4004 8008 */
+#define SYSPLLCTRL_MSEL_MASK 0x001F // Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
+#define SYSPLLCTRL_MSEL_SHIFT 0
+#define SYSPLLCTRL_PSEL_MASK 0x0060 // Post divider ratio P. The division ratio is 2 P.
+#define SYSPLLCTRL_PSEL_SHIFT 5
+
+/* SYSPLLSTAT, address 0x4004 800C */
+#define SYSPLLSTAT_LOCK (1 << 0) // PLL lock status
+
+/* SYSOSCCTRL, address 0x4004 8020 */
+#define SYSOSCCTRL_BYPASS (1 << 0) // Bypass system oscillator
+#define SYSOSCCTRL_FREQRANGE (1 << 1) // Determines frequency range for Low-power oscillator.
+
+/* WDTOSCCTRL, address 0x4004 8024 */
+#define WDTOSCCTRL_DIVSEL_MASK 0x001F // Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL)) 00000: 2 (1 + DIVSEL) = 2 00001: 2 (1 + DIVSEL) = 4 to 11111: 2 (1 + DIVSEL) = 64
+#define WDTOSCCTRL_DIVSEL_SHIFT 0
+#define WDTOSCCTRL_FREQSEL_MASK 0x01E0 // Select watchdog oscillator analog output frequency (Fclkana).
+#define WDTOSCCTRL_FREQSEL_SHIFT 5
+
+/* IRCCTRL, address 0x4004 8028 */
+#define IRCCTRL_TRIM_MASK 0x00FF // Trim value
+#define IRCCTRL_TRIM_SHIFT 0
+
+/* SYSRSTSTAT, address 0x4004 8030 */
+#define SYSRSTSTAT_POR (1 << 0) // POR reset status
+#define SYSRSTSTAT_EXTRST (1 << 1) // Status of the external RESET pin.
+#define SYSRSTSTAT_WDT (1 << 2) // Status of the Watchdog reset
+#define SYSRSTSTAT_BOD (1 << 3) // Status of the Brown-out detect reset
+#define SYSRSTSTAT_SYSRST (1 << 4) // Status of the software system reset
+
+/* SYSPLLCLKSEL, address 0x4004 8040 */
+#define SYSPLLCLKSEL_SEL_MASK 0x0003 // System PLL clock source
+#define SYSPLLCLKSEL_SEL_SHIFT 0
+
+/* SYSPLLCLKUEN, address 0x4004 8044 */
+#define SYSPLLCLKUEN_ENA (1 << 0) // Enable system PLL clock source update
+
+/* MAINCLKSEL, address 0x4004 8070 */
+#define MAINCLKSEL_SEL_MASK 0x0003 // Clock source for main clock
+#define MAINCLKSEL_SEL_SHIFT 0
+
+/* MAINCLKUEN, address 0x4004 8074 */
+#define MAINCLKUEN_ENA (1 << 0) // Enable main clock source update 0
+
+/* SYSAHBCLKDIV, address 0x4004 8078 */
+#define SYSAHBCLKDIV_DIV_MASK 0x00FF // System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
+#define SYSAHBCLKDIV_DIV_SHIFT 0
+
+/* SYSAHBCLKCTRL, address 0x4004 8080 */
+#define SYSAHBCLKCTRL_SYS (1 << 0) // Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
+#define SYSAHBCLKCTRL_ROM (1 << 1) // Enables clock for ROM.
+#define SYSAHBCLKCTRL_RAM (1 << 2) // Enables clock for RAM.
+#define SYSAHBCLKCTRL_FLASHREG (1 << 3) // Enables clock for flash register interface.
+#define SYSAHBCLKCTRL_FLASHARRAY (1 << 4) // Enables clock for flash array access.
+#define SYSAHBCLKCTRL_I2C (1 << 5) // Enables clock for I2C.
+#define SYSAHBCLKCTRL_GPIO (1 << 6) // Enables clock for GPIO.
+#define SYSAHBCLKCTRL_CT16B0 (1 << 7) // Enables clock for 16-bit counter/timer 0.
+#define SYSAHBCLKCTRL_CT16B1 (1 << 8) // Enables clock for 16-bit counter/timer 1.
+#define SYSAHBCLKCTRL_CT32B0 (1 << 9) // Enables clock for 32-bit counter/timer 0.
+#define SYSAHBCLKCTRL_CT32B1 (1 << 10) // Enables clock for 32-bit counter/timer 1.
+#define SYSAHBCLKCTRL_SSP0 (1 << 11) // Enables clock for SPI0.
+#define SYSAHBCLKCTRL_UART (1 << 12) // Enables clock for UART. See Section 3.1 for part specific details.
+#define SYSAHBCLKCTRL_ADC (1 << 13) // Enables clock for ADC.
+#define SYSAHBCLKCTRL_WDT (1 << 15) // Enables clock for WDT.
+#define SYSAHBCLKCTRL_IOCON (1 << 16) // Enables clock for I/O configuration block.
+#define SYSAHBCLKCTRL_CAN (1 << 17) // Enables clock for C_CAN. See Section 3.1 for part specific details.
+#define SYSAHBCLKCTRL_SSP1 (1 << 18) // Enables clock for SPI1.
+
+/* SSP0CLKDIV, address 0x4004 8094 */
+#define SSP0CLKDIV_DIV_MASK 0x00FF // SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.
+#define SSP0CLKDIV_DIV_SHIFT 0
+
+/* UARTCLKDIV, address 0x4004 8098 */
+#define UARTCLKDIV_DIV_MASK 0x00FF // UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
+#define UARTCLKDIV_DIV_SHIFT 0
+
+/* SSP1CLKDIV, address 0x4004 809C */
+#define SSP1CLKDIV_DIV_MASK 0x00FF // SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255.
+#define SSP1CLKDIV_DIV_SHIFT 0
+
+/* WDTCLKSEL, address 0x4004 80D0 */
+#define WDTCLKSEL_SEL_MASK 0x0003 // WDT clock source
+#define WDTCLKSEL_SEL_SHIFT 0
+
+/* WDTCLKUEN, address 0x4004 80D4 */
+#define WDTCLKUEN_ENA (1 << 0) // Enable WDT clock source update
+
+/* WDTCLKDIV, address 0x4004 80D8 */
+#define WDTCLKDIV_DIV_MASK 0x00FF // WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
+#define WDTCLKDIV_DIV_SHIFT 0
+
+/* CLKOUTCLKSEL, address 0x4004 80E0 */
+#define CLKOUTCLKSEL_SEL_MASK 0x0003 // CLKOUT clock source
+#define CLKOUTCLKSEL_SEL_SHIFT 0
+
+/* CLKOUTUEN, address 0x4004 80E4 */
+#define CLKOUTUEN_ENA (1 << 0) // Enable CLKOUT clock source update 0
+
+/* CLKOUTCLKDIV, address 0x4004 80E8 */
+#define CLKOUTCLKDIV_DIV_MASK 0x00FF // Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
+#define CLKOUTCLKDIV_DIV_SHIFT 0
+
+/* PIOPORCAP0, address 0x4004 8100 */
+#define PIOPORCAP0_CAPPIO0_N_MASK 0x0FFF // Raw reset status input PIO0_n: PIO0_11 to PIO0_0
+#define PIOPORCAP0_CAPPIO0_N_SHIFT 0
+#define PIOPORCAP0_CAPPIO1_N_MASK 0xFFF000 // Raw reset status input PIO1_n: PIO1_11 to PIO1_0
+#define PIOPORCAP0_CAPPIO1_N_SHIFT 12
+#define PIOPORCAP0_CAPPIO2_N_MASK 0xFF000000 // Raw reset status input PIO2_n: PIO2_7 to PIO2_0
+#define PIOPORCAP0_CAPPIO2_N_SHIFT 24
+
+/* PIOPORCAP1, address 0x4004 8104 */
+#define PIOPORCAP1_CAPPIO2_8 (1 << 0) // Raw reset status input PIO2_8
+#define PIOPORCAP1_CAPPIO2_9 (1 << 1) // Raw reset status input PIO2_9
+#define PIOPORCAP1_CAPPIO2_10 (1 << 2) // Raw reset status input PIO2_10
+#define PIOPORCAP1_CAPPIO2_11 (1 << 3) // Raw reset status input PIO2_11
+#define PIOPORCAP1_CAPPIO3_0 (1 << 4) // Raw reset status input PIO3_0
+#define PIOPORCAP1_CAPPIO3_1 (1 << 5) // Raw reset status input PIO3_1
+#define PIOPORCAP1_CAPPIO3_2 (1 << 6) // Raw reset status input PIO3_2
+#define PIOPORCAP1_CAPPIO3_3 (1 << 7) // Raw reset status input PIO3_3
+#define PIOPORCAP1_CAPPIO3_4 (1 << 8) // Raw reset status input PIO3_4
+#define PIOPORCAP1_CAPPIO3_5 (1 << 9) // Raw reset status input PIO3_5
+
+/* BODCTRL, address 0x4004 8150 */
+#define BODCTRL_BODRSTLEV_MASK 0x0003 // BOD reset level
+#define BODCTRL_BODRSTLEV_SHIFT 0
+#define BODCTRL_BODINTVAL_MASK 0x000C // BOD interrupt level
+#define BODCTRL_BODINTVAL_SHIFT 2
+#define BODCTRL_BODRSTENA (1 << 4) // BOD reset enable
+
+/* SYSTCKCAL, address 0x4004 8154 */
+#define SYSTCKCAL_CAL_MASK 0x3FFFFFF // System tick timer calibration value
+#define SYSTCKCAL_CAL_SHIFT 0
+
+/* NMISRC, address 0x4004 8174 */
+#define NMISRC_IRQNO_MASK 0x001F // The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.
+#define NMISRC_IRQNO_SHIFT 0
+#define NMISRC_NMIEN (1 << 31) // Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
+
+/* STARTAPRP0, address 0x4004 8200 */
+#define STARTAPRP0_APRPIO0_N_MASK 0x0FFF // Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge
+#define STARTAPRP0_APRPIO0_N_SHIFT 0
+#define STARTAPRP0_APRPIO1_0 (1 << 12) // Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge Reserved. Do not write a 1 to reserved bits in this register.
+
+/* STARTERP0, address 0x4004 8204 */
+#define STARTERP0_ERPIO0_N_MASK 0x0FFF // Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled
+#define STARTERP0_ERPIO0_N_SHIFT 0
+#define STARTERP0_ERPIO1_0 (1 << 12) // Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled Reserved. Do not write a 1 to reserved bits in this register.
+
+/* STARTRSRP0CLR, address 0x4004 8208 */
+#define STARTRSRP0CLR_RSRPIO0_N_MASK 0x0FFF // Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
+#define STARTRSRP0CLR_RSRPIO0_N_SHIFT 0
+#define STARTRSRP0CLR_RSRPIO1_0 (1 << 12) // Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
+
+/* STARTSRP0, address 0x4004 820C */
+#define STARTSRP0_SRPIO0_N_MASK 0x0FFF // Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.
+#define STARTSRP0_SRPIO0_N_SHIFT 0
+#define STARTSRP0_SRPIO1_0 (1 << 12) // Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending.
+
+/* PDSLEEPCFG, address 0x4004 8230 */
+#define PDSLEEPCFG_BOD_PD (1 << 3) // BOD power-down control in Deep-sleep mode, see Table 40.
+#define PDSLEEPCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power control in Deep-sleep mode, see Table 40.
+
+/* PDAWAKECFG, address 0x4004 8234 */
+#define PDAWAKECFG_IRCOUT_PD (1 << 0) // IRC oscillator output wake-up configuration
+#define PDAWAKECFG_IRC_PD (1 << 1) // IRC oscillator power-down wake-up configuration
+#define PDAWAKECFG_FLASH_PD (1 << 2) // Flash wake-up configuration
+#define PDAWAKECFG_BOD_PD (1 << 3) // BOD wake-up configuration
+#define PDAWAKECFG_ADC_PD (1 << 4) // ADC wake-up configuration
+#define PDAWAKECFG_SYSOSC_PD (1 << 5) // System oscillator wake-up configuration
+#define PDAWAKECFG_WDTOSC_PD (1 << 6) // Watchdog oscillator wake-up configuration
+#define PDAWAKECFG_SYSPLL_PD (1 << 7) // System PLL wake-up configuration
+
+/* PDRUNCFG, address 0x4004 8238 */
+#define PDRUNCFG_IRCOUT_PD (1 << 0) // IRC oscillator output power-down
+#define PDRUNCFG_IRC_PD (1 << 1) // IRC oscillator power-down
+#define PDRUNCFG_FLASH_PD (1 << 2) // Flash power-down
+#define PDRUNCFG_BOD_PD (1 << 3) // BOD power-down
+#define PDRUNCFG_ADC_PD (1 << 4) // ADC power-down
+#define PDRUNCFG_SYSOSC_PD (1 << 5) // System oscillator power-down
+#define PDRUNCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power-down
+#define PDRUNCFG_SYSPLL_PD (1 << 7) // System PLL power-down
+
+/* DEVICE_ID, address 0x4004 83F4 */
+#define DEVICE_ID_DEVICEID_MASK 0xFFFFFFFF // Part ID numbers for LPC111x/LPC11Cxx parts
+#define DEVICE_ID_DEVICEID_SHIFT 0
+
+/* FLASHCFG, address 0x4003 C010 */
+#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
+#define FLASHCFG_FLASHTIM_SHIFT 0
+
+/* PCON, address 0x4003 8000 */
+#define PCON_DPDEN (1 << 1) // Deep power-down mode enable
+#define PCON_SLEEPFLAG (1 << 8) // Sleep mode flag
+#define PCON_DPDFLAG (1 << 11) // Deep power-down flag
+
+/* GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010 */
+#define GPREGn_GPDATA_MASK 0xFFFFFFFF // Data retained during Deep power-down mode.
+#define GPREGn_GPDATA_SHIFT 0
+
+/* GPREG4, address 0x4003 8014 */
+#define GPREG4_WAKEUPHYS (1 << 10) // WAKEUP pin hysteresis enable
+#define GPREG4_GPDATA_MASK 0xFFFFF800 // Data retained during Deep power-down mode.
+#define GPREG4_GPDATA_SHIFT 11
+
+/* IOCON_PIO2_6, address 0x4004 4000 */
+#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_6_FUNC_SHIFT 0
+#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_6_MODE_SHIFT 3
+#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_0, address 0x4004 4008 */
+#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_0_FUNC_SHIFT 0
+#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_0_MODE_SHIFT 3
+#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_RESET_PIO0_0, address 0x4004 400C */
+#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
+#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
+#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_1, address 0x4004 4010 */
+#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_1_FUNC_SHIFT 0
+#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_1_MODE_SHIFT 3
+#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO1_8, address 0x4004 4014 */
+#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_8_FUNC_SHIFT 0
+#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_8_MODE_SHIFT 3
+#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_2, address 0x4004 401C */
+#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_2_FUNC_SHIFT 0
+#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_2_MODE_SHIFT 3
+#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_7, address 0x4004 4020 */
+#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_7_FUNC_SHIFT 0
+#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_7_MODE_SHIFT 3
+#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_8, address 0x4004 4024 */
+#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_8_FUNC_SHIFT 0
+#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_8_MODE_SHIFT 3
+#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_1, address 0x4004 4028 */
+#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_1_FUNC_SHIFT 0
+#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_1_MODE_SHIFT 3
+#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_3, address 0x4004 402C */
+#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_3_FUNC_SHIFT 0
+#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_3_MODE_SHIFT 3
+#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_4, address 0x4004 4030 */
+#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_4_FUNC_SHIFT 0
+#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
+#define IOCON_PIO0_4_I2CMODE_SHIFT 8
+
+/* IOCON_PIO0_5, address 0x4004 4034 */
+#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_5_FUNC_SHIFT 0
+#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
+#define IOCON_PIO0_5_I2CMODE_SHIFT 8
+
+/* IOCON_PIO1_9, address 0x4004 4038 */
+#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_9_FUNC_SHIFT 0
+#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_9_MODE_SHIFT 3
+#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO3_4, address 0x4004 403C */
+#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_4_FUNC_SHIFT 0
+#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_4_MODE_SHIFT 3
+#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_4, address 0x4004 4040 */
+#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_4_FUNC_SHIFT 0
+#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_4_MODE_SHIFT 3
+#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_5, address 0x4004 4044 */
+#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_5_FUNC_SHIFT 0
+#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_5_MODE_SHIFT 3
+#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_5, address 0x4004 4048 */
+#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_5_FUNC_SHIFT 0
+#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_5_MODE_SHIFT 3
+#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_6, address 0x4004 404C */
+#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_6_FUNC_SHIFT 0
+#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_6_MODE_SHIFT 3
+#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_7, address 0x4004 4050 */
+#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_7_FUNC_SHIFT 0
+#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_7_MODE_SHIFT 3
+#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_9, address 0x4004 4054 */
+#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_9_FUNC_SHIFT 0
+#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_9_MODE_SHIFT 3
+#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_10, address 0x4004 4058 */
+#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_10_FUNC_SHIFT 0
+#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_10_MODE_SHIFT 3
+#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_2, address 0x4004 405C */
+#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_2_FUNC_SHIFT 0
+#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_2_MODE_SHIFT 3
+#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_8, address 0x4004 4060 */
+#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_8_FUNC_SHIFT 0
+#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_8_MODE_SHIFT 3
+#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO0_9, address 0x4004 4064 */
+#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_9_FUNC_SHIFT 0
+#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_9_MODE_SHIFT 3
+#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
+#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
+#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
+#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_10, address 0x4004 406C */
+#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_10_FUNC_SHIFT 0
+#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_10_MODE_SHIFT 3
+#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_11, address 0x4004 4070 */
+#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_11_FUNC_SHIFT 0
+#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_11_MODE_SHIFT 3
+#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_R_PIO0_11, address 0x4004 4074 */
+#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO0_11_FUNC_SHIFT 0
+#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO0_11_MODE_SHIFT 3
+#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_R_PIO1_0, address 0x4004 4078 */
+#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_0_FUNC_SHIFT 0
+#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_0_MODE_SHIFT 3
+#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_R_PIO1_1, address 0x4004 407C */
+#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_1_FUNC_SHIFT 0
+#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_1_MODE_SHIFT 3
+#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_R_PIO1_2, address 0x4004 4080 */
+#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_2_FUNC_SHIFT 0
+#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_2_MODE_SHIFT 3
+#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO3_0, address 0x4004 4084 */
+#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_0_FUNC_SHIFT 0
+#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_0_MODE_SHIFT 3
+#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_1, address 0x4004 4088 */
+#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_1_FUNC_SHIFT 0
+#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_1_MODE_SHIFT 3
+#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO2_3, address 0x4004 408C */
+#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_3_FUNC_SHIFT 0
+#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_3_MODE_SHIFT 3
+#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
+#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
+#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
+#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_4, address 0x4004 4094 */
+#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
+#define IOCON_PIO1_4_FUNC_SHIFT 0
+#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_4_MODE_SHIFT 3
+#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO1_11, address 0x4004 4098 */
+#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_11_FUNC_SHIFT 0
+#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_11_MODE_SHIFT 3
+#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO3_2, address 0x4004 409C */
+#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_2_FUNC_SHIFT 0
+#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_2_MODE_SHIFT 3
+#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_5, address 0x4004 40A0 */
+#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_5_FUNC_SHIFT 0
+#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_5_MODE_SHIFT 3
+#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO1_6, address 0x4004 40A4 */
+#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_6_FUNC_SHIFT 0
+#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_6_MODE_SHIFT 3
+#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO1_7, address 0x4004 40A8 */
+#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_7_FUNC_SHIFT 0
+#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_7_MODE_SHIFT 3
+#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_PIO3_3, address 0x4004 40AC */
+#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_3_FUNC_SHIFT 0
+#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_3_MODE_SHIFT 3
+#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
+
+/* IOCON_SCK_LOC, address 0x4004 40B0 */
+#define IOCON_SCK_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
+#define IOCON_SCK_LOC_SCKLOC_SHIFT 0
+
+/* IOCON_DSR_LOC, address 0x4004 40B4 */
+#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
+#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
+
+/* IOCON_DCD_LOC, address 0x4004 40B8 */
+#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
+#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
+
+/* IOCON_RI_LOC, address 0x4004 40BC */
+#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
+#define IOCON_RI_LOC_RILOC_SHIFT 0
+
+/* IOCON_PIO2_6, address 0x4004 4000 */
+#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_6_FUNC_SHIFT 0
+#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_6_MODE_SHIFT 3
+#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_0, address 0x4004 4008 */
+#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_0_FUNC_SHIFT 0
+#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_0_MODE_SHIFT 3
+#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_RESET_PIO0_0, address 0x4004 400C */
+#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
+#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
+#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_1, address 0x4004 4010 */
+#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_1_FUNC_SHIFT 0
+#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_1_MODE_SHIFT 3
+#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_8, address 0x4004 4014 */
+#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_8_FUNC_SHIFT 0
+#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_8_MODE_SHIFT 3
+#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_2, address 0x4004 401C */
+#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_2_FUNC_SHIFT 0
+#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_2_MODE_SHIFT 3
+#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_7, address 0x4004 4020 */
+#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_7_FUNC_SHIFT 0
+#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_7_MODE_SHIFT 3
+#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_8, address 0x4004 4024 */
+#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_8_FUNC_SHIFT 0
+#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_8_MODE_SHIFT 3
+#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_1, address 0x4004 4028 */
+#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_1_FUNC_SHIFT 0
+#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_1_MODE_SHIFT 3
+#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_3, address 0x4004 402C */
+#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_3_FUNC_SHIFT 0
+#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_3_MODE_SHIFT 3
+#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_4, address 0x4004 4030 */
+#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_4_FUNC_SHIFT 0
+#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
+#define IOCON_PIO0_4_I2CMODE_SHIFT 8
+
+/* IOCON_PIO0_5, address 0x4004 4034 */
+#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_5_FUNC_SHIFT 0
+#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
+#define IOCON_PIO0_5_I2CMODE_SHIFT 8
+
+/* IOCON_PIO1_9, address 0x4004 4038 */
+#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_9_FUNC_SHIFT 0
+#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_9_MODE_SHIFT 3
+#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_4, address 0x4004 403C */
+#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_4_FUNC_SHIFT 0
+#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_4_MODE_SHIFT 3
+#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_4, address 0x4004 4040 */
+#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_4_FUNC_SHIFT 0
+#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_4_MODE_SHIFT 3
+#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_5, address 0x4004 4044 */
+#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_5_FUNC_SHIFT 0
+#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_5_MODE_SHIFT 3
+#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_5, address 0x4004 4048 */
+#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_5_FUNC_SHIFT 0
+#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_5_MODE_SHIFT 3
+#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_6, address 0x4004 404C */
+#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_6_FUNC_SHIFT 0
+#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_6_MODE_SHIFT 3
+#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_7, address 0x4004 4050 */
+#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_7_FUNC_SHIFT 0
+#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_7_MODE_SHIFT 3
+#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_9, address 0x4004 4054 */
+#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_9_FUNC_SHIFT 0
+#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_9_MODE_SHIFT 3
+#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_10, address 0x4004 4058 */
+#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_10_FUNC_SHIFT 0
+#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_10_MODE_SHIFT 3
+#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_2, address 0x4004 405C */
+#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_2_FUNC_SHIFT 0
+#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_2_MODE_SHIFT 3
+#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_8, address 0x4004 4060 */
+#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_8_FUNC_SHIFT 0
+#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_8_MODE_SHIFT 3
+#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO0_9, address 0x4004 4064 */
+#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO0_9_FUNC_SHIFT 0
+#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO0_9_MODE_SHIFT 3
+#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
+#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
+#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
+#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_10, address 0x4004 406C */
+#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_10_FUNC_SHIFT 0
+#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_10_MODE_SHIFT 3
+#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_11, address 0x4004 4070 */
+#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_11_FUNC_SHIFT 0
+#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_11_MODE_SHIFT 3
+#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_R_PIO0_11, address 0x4004 4074 */
+#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO0_11_FUNC_SHIFT 0
+#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO0_11_MODE_SHIFT 3
+#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_R_PIO1_0, address 0x4004 4078 */
+#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_0_FUNC_SHIFT 0
+#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_0_MODE_SHIFT 3
+#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_R_PIO1_1, address 0x4004 407C */
+#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_1_FUNC_SHIFT 0
+#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_1_MODE_SHIFT 3
+#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_R_PIO1_2, address 0x4004 4080 */
+#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_R_PIO1_2_FUNC_SHIFT 0
+#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_R_PIO1_2_MODE_SHIFT 3
+#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_0, address 0x4004 4084 */
+#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_0_FUNC_SHIFT 0
+#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_0_MODE_SHIFT 3
+#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_1, address 0x4004 4088 */
+#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_1_FUNC_SHIFT 0
+#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_1_MODE_SHIFT 3
+#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO2_3, address 0x4004 408C */
+#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO2_3_FUNC_SHIFT 0
+#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO2_3_MODE_SHIFT 3
+#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
+#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
+#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
+#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_4, address 0x4004 4094 */
+#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
+#define IOCON_PIO1_4_FUNC_SHIFT 0
+#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_4_MODE_SHIFT 3
+#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_11, address 0x4004 4098 */
+#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_11_FUNC_SHIFT 0
+#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_11_MODE_SHIFT 3
+#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
+#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_2, address 0x4004 409C */
+#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_2_FUNC_SHIFT 0
+#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_2_MODE_SHIFT 3
+#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_5, address 0x4004 40A0 */
+#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_5_FUNC_SHIFT 0
+#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_5_MODE_SHIFT 3
+#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_6, address 0x4004 40A4 */
+#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_6_FUNC_SHIFT 0
+#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_6_MODE_SHIFT 3
+#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO1_7, address 0x4004 40A8 */
+#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO1_7_FUNC_SHIFT 0
+#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO1_7_MODE_SHIFT 3
+#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_PIO3_3, address 0x4004 40AC */
+#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
+#define IOCON_PIO3_3_FUNC_SHIFT 0
+#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
+#define IOCON_PIO3_3_MODE_SHIFT 3
+#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
+#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode.
+
+/* IOCON_SCK0_LOC, address 0x4004 40B0 */
+#define IOCON_SCK0_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
+#define IOCON_SCK0_LOC_SCKLOC_SHIFT 0
+
+/* IOCON_DSR_LOC, address 0x4004 40B4 */
+#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
+#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
+
+/* IOCON_DCD_LOC, address 0x4004 40B8 */
+#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
+#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
+
+/* IOCON_RI_LOC, address 0x4004 40BC */
+#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
+#define IOCON_RI_LOC_RILOC_SHIFT 0
+
+/* IOCON_SSEL1_LOC, address 0x4004 4018 */
+#define IOCON_SSEL1_LOC_SSEL1LOC_MASK 0x0003 // Selects pin location for SSEL1 function.
+#define IOCON_SSEL1_LOC_SSEL1LOC_SHIFT 0
+
+/* IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0 */
+#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_MASK 0x0003 // Selects pin location for CT16B0_CAP0 function.
+#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_SHIFT 0
+
+/* IOCON_SCK1_LOC, address 0x4004 40C4 */
+#define IOCON_SCK1_LOC_SCK1LOC_MASK 0x0003 // Selects pin location for SCK1 function.
+#define IOCON_SCK1_LOC_SCK1LOC_SHIFT 0
+
+/* IOCON_MISO1_LOC, address 0x4004 40C8 */
+#define IOCON_MISO1_LOC_MISO1LOC_MASK 0x0003 // Selects pin location for the MISO1 function.
+#define IOCON_MISO1_LOC_MISO1LOC_SHIFT 0
+
+/* IOCON_MOSI1_LOC, address 0x4004 40CC */
+#define IOCON_MOSI1_LOC_MOSI1LOC_MASK 0x0003 // Selects pin location for the MOSI1 function.
+#define IOCON_MOSI1_LOC_MOSI1LOC_SHIFT 0
+
+/* IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0 */
+#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_MASK 0x0003 // Selects pin location for the CT32B0_CAP0 function.
+#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_SHIFT 0
+
+/* IOCON_RXD_LOC, address 0x4004 40D4 */
+#define IOCON_RXD_LOC_RXDLOC_MASK 0x0003 // Selects pin location for the RXD function.
+#define IOCON_RXD_LOC_RXDLOC_SHIFT 0
+
+/* GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000 */
+#define GPIO0DIR_IO_MASK 0x0FFF // Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
+#define GPIO0DIR_IO_SHIFT 0
+
+/* GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003 8004 */
+#define GPIO0IS_ISENSE_MASK 0x0FFF // Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
+#define GPIO0IS_ISENSE_SHIFT 0
+
+/* GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 8008 */
+#define GPIO0IBE_IBE_MASK 0x0FFF // Selects interrupt on pin x to be triggered on both edges (x = 0 0x00 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
+#define GPIO0IBE_IBE_SHIFT 0
+
+/* GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 800C */
+#define GPIO0IEV_IEV_MASK 0x0FFF // Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 175), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 175), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
+#define GPIO0IEV_IEV_SHIFT 0
+
+/* GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003 8010 */
+#define GPIO0IE_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
+#define GPIO0IE_MASK_SHIFT 0
+
+/* GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 8014 */
+#define GPIO0RIS_RAWST_MASK 0x0FFF // Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
+#define GPIO0RIS_RAWST_SHIFT 0
+
+/* GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address 0x5003 8018 */
+#define GPIO0MIS_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
+#define GPIO0MIS_MASK_SHIFT 0
+
+/* GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003 801C */
+#define GPIO0IC_CLR_MASK 0x0FFF // Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic. This register is write-only. Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
+#define GPIO0IC_CLR_SHIFT 0
+
+/* U0IIR - address 0x4004 8008, Read Only */
+#define U0IIR_INTSTATUS (1 << 0) // Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating U0IIR[3:1].
+#define U0IIR_INTID_MASK 0x000E // Interrupt identification. U0IER[3:1] identifies an interrupt 0 corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).
+#define U0IIR_INTID_SHIFT 1
+#define U0IIR_FIFOENABLE_MASK 0x00C0 // These bits are equivalent to U0FCR[0].
+#define U0IIR_FIFOENABLE_SHIFT 6
+#define U0IIR_ABEOINT (1 << 8) // End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
+#define U0IIR_ABTOINT (1 << 9) // Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+
+/* U0FCR - address 0x4000 8008, Write Only */
+#define U0FCR_FIFOEN (1 << 0) // FIFO Enable
+#define U0FCR_RXFIFORES (1 << 1) // RX FIFO Reset
+#define U0FCR_TXFIFORES (1 << 2) // TX FIFO Reset
+#define U0FCR_RXTL_MASK 0x00C0 // RX Trigger Level. These two bits determine how many 0 receiver UART FIFO characters must be written before an interrupt is activated.
+#define U0FCR_RXTL_SHIFT 6
+
+/* U0LCR - address 0x4000 800C */
+#define U0LCR_WLS_MASK 0x0003 // Word Length Select
+#define U0LCR_WLS_SHIFT 0
+#define U0LCR_SBS (1 << 2) // Stop Bit Select
+#define U0LCR_PE (1 << 3) // Parity Enable
+#define U0LCR_PS_MASK 0x0030 // Parity Select 0x0 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x2 Forced 1 stick parity. 0x3 Forced 0 stick parity.
+#define U0LCR_PS_SHIFT 4
+#define U0LCR_BC (1 << 6) // Break Control
+#define U0LCR_DLAB (1 << 7) // Divisor Latch Access Bit
+
+/* U0MCR - address 0x4000 8010 */
+#define U0MCR_DTRC (1 << 0) // DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
+#define U0MCR_RTSC (1 << 1) // RTS Control. Source for modem output pin RTS. This bit reads as 0 0 when modem loopback mode is active.
+#define U0MCR_LMS (1 << 4) // Loopback Mode Select. The modem loopback mode provides a 0 mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.
+#define U0MCR_RTSEN (1 << 6) // RTS flow control
+#define U0MCR_CTSEN (1 << 7) // CTS flow control
+
+/* U0LSR - address 0x4000 8014, Read Only */
+#define U0LSR_RDR (1 << 0) // Receiver Data Ready. U0LSR[0] is set when the U0RBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty.
+#define U0LSR_OE (1 << 1) // Overrun Error. The overrun error condition is set as soon as it 0 occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
+#define U0LSR_PE (1 << 2) // Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
+#define U0LSR_FE (1 << 3) // Framing Error. When the stop bit of a received character is a 0 logic 0, a framing error occurs. A U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
+#define U0LSR_BI (1 << 4) // Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
+#define U0LSR_THRE (1 << 5) // Transmitter Holding Register Empty. THRE is set immediately 1 upon detection of an empty UART THR and is cleared on a U0THR write.
+#define U0LSR_TEMT (1 << 6) // Transmitter Empty. TEMT is set when both U0THR and 1 U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the THR.
+#define U0LSR_RXFE (1 << 7) // Error in RX FIFO. U0LSR[7] is set when a character with a RX 0 error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART FIFO.
+
+/* U0MSR - address 0x4000 8018 */
+#define U0MSR_DCTS (1 << 0) // Delta CTS. Set upon state change of input CTS. Cleared on a U0MSR read. 0 No change detected on modem input CTS. 1 State change detected on modem input CTS.
+#define U0MSR_DDSR (1 << 1) // Delta DSR. Set upon state change of input DSR. Cleared on a U0MSR read. 0 No change detected on modem input DSR. 1 State change detected on modem input DSR.
+#define U0MSR_TERI (1 << 2) // Trailing Edge RI. Set upon low to high transition of input RI. Cleared 0 on a U0MSR read. 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI.
+#define U0MSR_DDCD (1 << 3) // Delta DCD. Set upon state change of input DCD. Cleared on a U0MSR read. 0 No change detected on modem input DCD. 1 State change detected on modem input DCD.
+#define U0MSR_CTS (1 << 4) // Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.
+#define U0MSR_DSR (1 << 5) // Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.
+#define U0MSR_RI (1 << 6) // Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.
+#define U0MSR_DCD (1 << 7) // Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.
+
+/* U0SCR - address 0x4000 801C */
+#define U0SCR_PAD_MASK 0x00FF // A readable, writable byte.
+#define U0SCR_PAD_SHIFT 0
+
+/* U0ACR - address 0x4000 8020 */
+#define U0ACR_START (1 << 0) // Start bit. This bit is automatically cleared after auto-baud completion.
+#define U0ACR_MODE (1 << 1) // Auto-baud mode select
+#define U0ACR_AUTORESTART (1 << 2) // Restart enable
+#define U0ACR_ABEOINTCLR (1 << 8) // End of auto-baud interrupt clear (write only accessible)
+#define U0ACR_ABTOINTCLR (1 << 9) // Auto-baud time-out interrupt clear (write only accessible)
+
+/* U0TER - address 0x4000 8030 */
+#define U0TER_TXEN (1 << 7) // When this bit is 1, as it is after a Reset, data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved
+
+/* U0RS485CTRL - address 0x4000 804C */
+#define U0RS485CTRL_NMMEN (1 << 0) // NMM enable.
+#define U0RS485CTRL_RXDIS (1 << 1) // Receiver enable.
+#define U0RS485CTRL_AADEN (1 << 2) // AAD enable.
+#define U0RS485CTRL_SEL (1 << 3) // Select direction control pin
+#define U0RS485CTRL_DCTRL (1 << 4) // Auto direction control enable.
+#define U0RS485CTRL_OINV (1 << 5) // Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
+
+/* U0RS485ADRMATCH - address 0x4000 8050 */
+#define U0RS485ADRMATCH_ADRMATCH_MASK 0x00FF // Contains the address match value. 0
+#define U0RS485ADRMATCH_ADRMATCH_SHIFT 0
+
+/* U0RS485DLY - address 0x4000 8054 */
+#define U0RS485DLY_DLY_MASK 0x00FF // Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
+#define U0RS485DLY_DLY_SHIFT 0
+
+/* SSP0CR0 - address 0x4004 0000, SSP1CR0 - address 0x4005 8000 */
+#define SSP0CR0_DSS_MASK 0x000F // Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
+#define SSP0CR0_DSS_SHIFT 0
+#define SSP0CR0_FRF_MASK 0x0030 // Frame Format.
+#define SSP0CR0_FRF_SHIFT 4
+#define SSP0CR0_CPOL (1 << 6) // Clock Out Polarity. This bit is only used in SPI mode.
+#define SSP0CR0_CPHA (1 << 7) // Clock Out Phase. This bit is only used in SPI mode.
+#define SSP0CR0_SCR_MASK 0xFF00 // Serial Clock Rate. The number of prescaler output clocks per 0x00 bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR [SCR+1]). Reserved
+#define SSP0CR0_SCR_SHIFT 8
+
+/* SSP0CR1 - address 0x4004 0004, SSP1CR1 - address 0x4005 8004 */
+#define SSP0CR1_LBM (1 << 0) // Loop Back Mode.
+#define SSP0CR1_SSE (1 << 1) // SPI Enable.
+#define SSP0CR1_MS (1 << 2) // Master/Slave Mode.This bit can only be written when the SSE bit is 0.
+#define SSP0CR1_SOD (1 << 3) // Slave Output Disable. This bit is relevant only in slave 0 mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
+
+/* SSP0DR - address 0x4004 0008, SSP1DR - address 0x4005 8008 */
+#define SSP0DR_DATA_MASK 0xFFFF // Write: software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. Reserved.
+#define SSP0DR_DATA_SHIFT 0
+
+/* SSP0SR - address 0x4004 000C, SSP1SR - address 0x4005 800C */
+#define SSP0SR_TFE (1 << 0) // Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
+#define SSP0SR_TNF (1 << 1) // Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
+#define SSP0SR_RNE (1 << 2) // Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
+#define SSP0SR_RFF (1 << 3) // Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
+#define SSP0SR_BSY (1 << 4) // Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
+
+/* SSP0CPSR - address 0x4004 0010, SSP1CPSR - address 0x4005 8010 */
+#define SSP0CPSR_CPSDVSR_MASK 0x00FF // This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
+#define SSP0CPSR_CPSDVSR_SHIFT 0
+
+/* SSP0IMSC - address 0x4004 0014, SSP1IMSC - address 0x4005 8014 */
+#define SSP0IMSC_RORIM (1 << 0) // Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
+#define SSP0IMSC_RTIM (1 << 1) // Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
+#define SSP0IMSC_RXIM (1 << 2) // Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full.
+#define SSP0IMSC_TXIM (1 << 3) // Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty.
+
+/* SSP0RIS - address 0x4004 0018, SSP1RIS - address 0x4005 8018 */
+#define SSP0RIS_RORRIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
+#define SSP0RIS_RTRIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, and has not been read 0 for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
+#define SSP0RIS_RXRIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full.
+#define SSP0RIS_TXRIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty.
+
+/* SSP0MIS - address 0x4004 001C, SSP1MIS - address 0x4005 801C */
+#define SSP0MIS_RORMIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled.
+#define SSP0MIS_RTMIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
+#define SSP0MIS_RXMIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0 is enabled.
+#define SSP0MIS_TXMIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
+
+/* SSP0ICR - address 0x4004 0020, SSP1ICR - address 0x4005 8020 */
+#define SSP0ICR_RORIC (1 << 0) // Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt.
+#define SSP0ICR_RTIC (1 << 1) // Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
+
+/* I2C0CONSET - address 0x4000 0000 */
+#define I2C0CONSET_AA (1 << 2) // Assert acknowledge flag.
+#define I2C0CONSET_SI (1 << 3) // I2C interrupt flag.
+#define I2C0CONSET_STO (1 << 4) // STOP flag.
+#define I2C0CONSET_STA (1 << 5) // START flag.
+#define I2C0CONSET_I2EN (1 << 6) // I2C interface enable. Reserved. The value read from a reserved bit is not defined.
+
+/* I2C0STAT - 0x4000 0004 */
+#define I2C0STAT_STATUS_MASK 0x00F8 // These bits give the actual status information about the I2 C interface. Reserved. The value read from a reserved bit is not defined.
+#define I2C0STAT_STATUS_SHIFT 3
+
+/* I2C0DAT - 0x4000 0008 */
+#define I2C0DAT_DATA_MASK 0x00FF // This register holds data values that have been received or are to 0 be transmitted. Reserved. The value read from a reserved bit is not defined.
+#define I2C0DAT_DATA_SHIFT 0
+
+/* I2C0ADR0 - 0x4000 000C */
+#define I2C0ADR0_GC (1 << 0) // General Call enable bit.
+#define I2C0ADR0_ADDRESS_MASK 0x00FE // The I2C device address for slave mode. Reserved. The value read from a reserved bit is not defined.
+#define I2C0ADR0_ADDRESS_SHIFT 1
+
+/* I2C0SCLH - address 0x4000 0010 */
+#define I2C0SCLH_SCLH_MASK 0xFFFF // Count for SCL HIGH time period selection.
+#define I2C0SCLH_SCLH_SHIFT 0
+
+/* I2C0SCLL - 0x4000 0014 */
+#define I2C0SCLL_SCLL_MASK 0xFFFF // Count for SCL low time period selection.
+#define I2C0SCLL_SCLL_SHIFT 0
+
+/* I2C0CONCLR - 0x4000 0018 */
+#define I2C0CONCLR_AAC (1 << 2) // Assert acknowledge Clear bit.
+#define I2C0CONCLR_SIC (1 << 3) // I2C interrupt Clear bit.
+#define I2C0CONCLR_STAC (1 << 5) // START flag Clear bit.
+#define I2C0CONCLR_I2ENC (1 << 6) // I2C interface Disable bit. Reserved. The value read from a reserved bit is not defined.
+
+/* I2C0MMCTRL - 0x4000 001C */
+#define I2C0MMCTRL_MM_ENA (1 << 0) // Monitor mode enable.
+#define I2C0MMCTRL_ENA_SCL (1 << 1) // SCL output enable.
+
+/* I2C0DATA_BUFFER - 0x4000 002C */
+#define I2C0DATA_BUFFER_DATA_MASK 0x00FF // This register holds contents of the 8 MSBs of the DAT shift register. Reserved. The value read from a reserved bit is not defined.
+#define I2C0DATA_BUFFER_DATA_SHIFT 0
+
+/* CANCNTL, address 0x4005 0000 */
+#define CANCNTL_INIT (1 << 0) // Initialization
+#define CANCNTL_IE (1 << 1) // Module interrupt enable
+#define CANCNTL_SIE (1 << 2) // Status change interrupt enable
+#define CANCNTL_EIE (1 << 3) // Error interrupt enable
+#define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
+#define CANCNTL_CCE (1 << 6) // Configuration change enable
+#define CANCNTL_TEST (1 << 7) // Test mode enable
+
+/* CANSTAT, address 0x4005 0004 */
+#define CANSTAT_LEC_MASK 0x0007 // Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to `0' when a message has been transferred (reception or transmission) without error. The unused code `111' may be written by the CPU to check for updates.
+#define CANSTAT_LEC_SHIFT 0
+#define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
+#define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
+#define CANSTAT_EPASS (1 << 5) // Error passive
+#define CANSTAT_EWARN (1 << 6) // Warning status
+#define CANSTAT_BOFF (1 << 7) // Busoff status
+
+/* CANEC, address 0x4005 0008 */
+#define CANEC_TEC_MASK 0x00FF // Transmit error counter Current value of the transmit error counter (maximum value 255)
+#define CANEC_TEC_SHIFT 0
+#define CANEC_REC_MASK 0x7F00 // Receive error counter Current value of the receive error counter (maximum value 127).
+#define CANEC_REC_SHIFT 8
+#define CANEC_RP (1 << 15) // Receive error passive
+
+/* CANBT, address 0x4005 000C */
+#define CANBT_BRP_MASK 0x003F // Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
+#define CANBT_BRP_SHIFT 0
+#define CANBT_SJW_MASK 0x00C0 // (Re)synchronization jump width Valid programmed values are 0 to 3.[1]
+#define CANBT_SJW_SHIFT 6
+#define CANBT_TSEG1_MASK 0x0F00 // Time segment before the sample point Valid values are 1 to 15.[1]
+#define CANBT_TSEG1_SHIFT 8
+#define CANBT_TSEG2_MASK 0x7000 // Time segment after the sample point Valid values are 0 to 7.[1]
+#define CANBT_TSEG2_SHIFT 12
+
+/* CANINT, address 0x4005 0010 */
+#define CANINT_INTID_MASK 0xFFFF // 0x0000 = No interrupt is pending. 0 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused
+#define CANINT_INTID_SHIFT 0
+
+/* CANTEST, address 0x4005 0014 */
+#define CANTEST_BASIC (1 << 2) // Basic mode
+#define CANTEST_SILENT (1 << 3) // Silent mode
+#define CANTEST_LBACK (1 << 4) // Loop back mode
+#define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
+#define CANTEST_TX_SHIFT 5
+#define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
+
+/* CANBRPE, address 0x4005 0018 */
+#define CANBRPE_BRPE_MASK 0x000F // Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
+#define CANBRPE_BRPE_SHIFT 0
+
+/* CANIF1_CMDREQ, address 0x4005 0020 and CANIF2_CMDREQ, address 0x4005 0080 */
+#define CANIFn_CMDREQ_MN_MASK 0x003F // Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
+#define CANIFn_CMDREQ_MN_SHIFT 0
+#define CANIFn_CMDREQ_BUSY (1 << 15) // BUSY flag
+
+/* CANIF1_CMDMSK, address 0x4005 0024 and CANIF2_CMDMSK, address 0x4005 0084 */
+#define CANIFn_CMDMSK_DATA_B (1 << 0) // Access data bytes 4-7
+#define CANIFn_CMDMSK_DATA_A (1 << 1) // Access data bytes 0-3
+#define CANIFn_CMDMSK_TXRQST (1 << 2) // Access transmission request bit (Write direction)
+#define CANIFn_CMDMSK_NEWDAT (1 << 2) // Access new data bit (Read direction)
+#define CANIFn_CMDMSK_CLRINTPND (1 << 3) // This bit is ignored in the write direction.
+#define CANIFn_CMDMSK_CTRL (1 << 4) // Access control bits
+#define CANIFn_CMDMSK_ARB (1 << 5) // Access arbitration bits
+#define CANIFn_CMDMSK_MASK (1 << 6) // Access mask bits
+#define CANIFn_CMDMSK_WR (1 << 7) // Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
+#define CANIFn_CMDMSK_RD (0 << 7) // Read transfer Read data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
+
+/* CANIF1_MSK1, address 0x4005 0028 and CANIF2_MASK1, address 0x4005 0088 */
+#define CANIFn_MSK1_MSK_MASK 0xFFFF // Identifier mask
+#define CANIFn_MSK1_MSK_SHIFT 0
+
+/* CANIF1_MSK2, address 0x4005 002C and CANIF2_MASK2, address 0x4005 008C */
+#define CANIFn_MSK2_MSK_MASK 0x1FFF // Identifier mask
+#define CANIFn_MSK2_MSK_SHIFT 0
+#define CANIFn_MSK2_MDIR (1 << 14) // Mask message direction
+#define CANIFn_MSK2_MXTD (1 << 15) // Mask extend identifier
+
+/* CANIF1_ARB1, address 0x4005 0030 and CANIF2_ARB1, address 0x4005 0090 */
+#define CANIFn_ARB1_ID_MASK 0xFFFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
+#define CANIFn_ARB1_ID_SHIFT 0
+
+/* CANIF1_ARB2, address 0x4005 0034 and CANIF2_ARB2, address 0x4005 0094 */
+#define CANIFn_ARB2_ID_MASK 0x1FFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
+#define CANIFn_ARB2_ID_SHIFT 0
+#define CANIFn_ARB2_DIR (1 << 13) // Message direction
+#define CANIFn_ARB2_XTD (1 << 14) // Extend identifier
+#define CANIFn_ARB2_MSGVAL (1 << 15) // Message valid Remark: The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
+
+/* CANIF1_MCTRL, address 0x4005 0038 and CANIF2_MCTRL, address 0x4005 0098 */
+#define CANIFn_MCTRL_DLC_MASK 0x000F // Data length code Remark: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
+#define CANIFn_MCTRL_DLC_SHIFT 0
+#define CANIFn_MCTRL_EOB (1 << 7) // End of buffer
+#define CANIFn_MCTRL_TXRQST (1 << 8) // Transmit request
+#define CANIFn_MCTRL_RMTEN (1 << 9) // Remote enable
+#define CANIFn_MCTRL_RXIE (1 << 10) // Receive interrupt enable
+#define CANIFn_MCTRL_TXIE (1 << 11) // Transmit interrupt enable
+#define CANIFn_MCTRL_UMASK (1 << 12) // Use acceptance mask Remark: If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
+#define CANIFn_MCTRL_INTPND (1 << 13) // Interrupt pending
+#define CANIFn_MCTRL_MSGLST (1 << 14) // Message lost (only valid for message objects in the direction receive).
+#define CANIFn_MCTRL_NEWDAT (1 << 15) // New data
+
+/* CANIF1_DA1, address 0x4005 003C and CANIF2_DA1, address 0x4005 009C */
+#define CANIFn_DA1_DATA0_MASK 0x00FF // Data byte 0
+#define CANIFn_DA1_DATA0_SHIFT 0
+#define CANIFn_DA1_DATA1_MASK 0xFF00 // Data byte 1
+#define CANIFn_DA1_DATA1_SHIFT 8
+
+/* CANIF1_DA2, address 0x4005 0040 and CANIF2_DA2, address 0x4005 00A0 */
+#define CANIFn_DA2_DATA2_MASK 0x00FF // Data byte 2
+#define CANIFn_DA2_DATA2_SHIFT 0
+#define CANIFn_DA2_DATA3_MASK 0xFF00 // Data byte 3
+#define CANIFn_DA2_DATA3_SHIFT 8
+
+/* CANIF1_DB1, address 0x4005 0044 and CANIF2_DB1, address 0x4005 00A4 */
+#define CANIFn_DB1_DATA4_MASK 0x00FF // Data byte 4
+#define CANIFn_DB1_DATA4_SHIFT 0
+#define CANIFn_DB1_DATA5_MASK 0xFF00 // Data byte 5
+#define CANIFn_DB1_DATA5_SHIFT 8
+
+/* CANIF1_DB2, address 0x4005 0048 and CANIF2_DB2, address 0x4005 00A8 */
+#define CANIFn_DB2_DATA6_MASK 0x00FF // Data byte 6
+#define CANIFn_DB2_DATA6_SHIFT 0
+#define CANIFn_DB2_DATA7_MASK 0xFF00 // Data byte 7
+#define CANIFn_DB2_DATA7_SHIFT 8
+
+/* CANTXREQ1, address 0x4005 0100 */
+#define CANTXREQ1_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
+#define CANTXREQ1_TXRQST_SHIFT 0
+
+/* CANTXREQ2, address 0x4005 0104 */
+#define CANTXREQ2_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
+#define CANTXREQ2_TXRQST_SHIFT 0
+
+/* CANND1, address 0x4005 0120 */
+#define CANND1_NEWDAT_MASK 0xFFFF // New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
+#define CANND1_NEWDAT_SHIFT 0
+
+/* CANND2, address 0x4005 0124 */
+#define CANND2_NEWDAT_MASK 0xFFFF // New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
+#define CANND2_NEWDAT_SHIFT 0
+
+/* CANIR1, address 0x4005 0140 */
+#define CANIR1_INTPND_INTERRUPT_MASK 0xFFFF // pending bits of message objects 16 to 1. essage object is ignored by the message essage object is the source of an interrupt. Reserved
+#define CANIR1_INTPND_INTERRUPT_SHIFT 0
+
+/* CANIR2, addresses 0x4005 0144 */
+#define CANIR2_INTPND_MASK 0xFFFF // Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. Reserved
+#define CANIR2_INTPND_SHIFT 0
+
+/* CANMSGV1, addresses 0x4005 0160 */
+#define CANMSGV1_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
+#define CANMSGV1_MSGVAL_SHIFT 0
+
+/* CANMSGV2, address 0x4005 0164 */
+#define CANMSGV2_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
+#define CANMSGV2_MSGVAL_SHIFT 0
+
+/* CANCLKDIV, address 0x4005 0180 */
+#define CANCLKDIV_CLKDIVVAL_MASK 0x000F // Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0011: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16.
+#define CANCLKDIV_CLKDIVVAL_SHIFT 0
+
+/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
+#define TMR16B0IR_MR0 (1 << 0) // Interrupt flag for match channel 0.
+#define TMR16B0IR_MR1 (1 << 1) // Interrupt flag for match channel 1.
+#define TMR16B0IR_MR2 (1 << 2) // Interrupt flag for match channel 2.
+#define TMR16B0IR_MR3 (1 << 3) // Interrupt flag for match channel 3.
+#define TMR16B0IR_CR0 (1 << 4) // Interrupt flag for capture channel 0 event.
+
+/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
+#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
+#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
+
+/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
+#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
+#define TMR16B0TC_TC_SHIFT 0
+
+/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
+#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
+#define TMR16B0PR_PR_SHIFT 0
+
+/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
+#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
+#define TMR16B0PC_PC_SHIFT 0
+
+/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
+#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
+#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
+#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
+#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
+#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
+#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
+#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
+#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
+
+/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
+#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
+#define TMR16B0MR0_to_3_MATCH_SHIFT 0
+
+/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
+#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
+
+/* TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0, address 0x4001 002C */
+#define TMR16B0CR0_CAP_MASK 0xFFFF // Timer counter capture value.
+#define TMR16B0CR0_CAP_SHIFT 0
+
+/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
+#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
+#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
+#define TMR16B0EMR_EMC0_SHIFT 4
+#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
+#define TMR16B0EMR_EMC1_SHIFT 6
+#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
+#define TMR16B0EMR_EMC2_SHIFT 8
+#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
+#define TMR16B0EMR_EMC3_SHIFT 10
+
+/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
+#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
+#define TMR16B0CTCR_CTM_SHIFT 0
+
+/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
+#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
+#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
+#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
+#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
+
+/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
+#define TMR16B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
+#define TMR16B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
+#define TMR16B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
+#define TMR16B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
+#define TMR16B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
+#define TMR16B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
+
+/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
+#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
+#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
+
+/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
+#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
+#define TMR16B0TC_TC_SHIFT 0
+
+/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
+#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
+#define TMR16B0PR_PR_SHIFT 0
+
+/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
+#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
+#define TMR16B0PC_PC_SHIFT 0
+
+/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
+#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
+#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
+#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
+#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
+#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
+#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
+#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
+#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
+
+/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
+#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
+#define TMR16B0MR0_to_3_MATCH_SHIFT 0
+
+/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
+#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
+#define TMR16B0CCR_CAP1RE (1 << 3) // Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP1FE (1 << 4) // Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
+#define TMR16B0CCR_CAP1I (1 << 5) // Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.
+
+/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
+#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
+#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
+#define TMR16B0EMR_EMC0_SHIFT 4
+#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
+#define TMR16B0EMR_EMC1_SHIFT 6
+#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
+#define TMR16B0EMR_EMC2_SHIFT 8
+#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
+#define TMR16B0EMR_EMC3_SHIFT 10
+
+/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
+#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
+#define TMR16B0CTCR_CTM_SHIFT 0
+#define TMR16B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
+#define TMR16B0CTCR_SELCC_SHIFT 5
+
+/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
+#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
+#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
+#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
+#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
+
+/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
+#define TMR32B0IR_MR0_INTERRUPT (1 << 0) // Interrupt flag for match channel 0.
+#define TMR32B0IR_MR1_INTERRUPT (1 << 1) // Interrupt flag for match channel 1.
+#define TMR32B0IR_MR2_INTERRUPT (1 << 2) // Interrupt flag for match channel 2.
+#define TMR32B0IR_MR3_INTERRUPT (1 << 3) // Interrupt flag for match channel 3.
+#define TMR32B0IR_CR0_INTERRUPT (1 << 4) // Interrupt flag for capture channel 0 event.
+
+/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
+#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
+#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
+
+/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
+#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
+#define TMR32B0TC_TC_SHIFT 0
+
+/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
+#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
+#define TMR32B0PR_PR_SHIFT 0
+
+/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
+#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
+#define TMR32B0PC_PC_SHIFT 0
+
+/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
+#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
+#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
+#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
+#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
+#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
+#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
+#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
+#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
+
+/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
+#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
+#define TMR32B0MRn_MATCH_SHIFT 0
+
+/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
+#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
+
+/* TMR32B0CR0, addresses 0x4001 402C and TMR32B1CR0, addresses 0x4001 802C */
+#define TMR32B0CR0_CAP_MASK 0xFFFFFFFF // Timer counter capture value.
+#define TMR32B0CR0_CAP_SHIFT 0
+
+/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
+#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
+#define TMR32B0EMR_EMC0_SHIFT 4
+#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
+#define TMR32B0EMR_EMC1_SHIFT 6
+#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
+#define TMR32B0EMR_EMC2_SHIFT 8
+#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
+#define TMR32B0EMR_EMC3_SHIFT 10
+
+/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
+#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
+#define TMR32B0CTCR_CTM_SHIFT 0
+#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
+#define TMR32B0CTCR_CIS_SHIFT 2
+
+/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
+#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
+#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
+#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
+#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
+
+/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
+#define TMR32B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
+#define TMR32B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
+#define TMR32B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
+#define TMR32B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
+#define TMR32B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
+#define TMR32B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
+
+/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
+#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
+#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
+
+/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
+#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
+#define TMR32B0TC_TC_SHIFT 0
+
+/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
+#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
+#define TMR32B0PR_PR_SHIFT 0
+
+/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
+#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
+#define TMR32B0PC_PC_SHIFT 0
+
+/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
+#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
+#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
+#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
+#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
+#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
+#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
+#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
+#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
+
+/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
+#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
+#define TMR32B0MRn_MATCH_SHIFT 0
+
+/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
+#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
+#define TMR32B0CCR_CAP1RE (1 << 3) // Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP1FE (1 << 4) // Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
+#define TMR32B0CCR_CAP1I (1 << 5) // Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
+
+/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
+#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
+#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
+#define TMR32B0EMR_EMC0_SHIFT 4
+#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
+#define TMR32B0EMR_EMC1_SHIFT 6
+#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
+#define TMR32B0EMR_EMC2_SHIFT 8
+#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
+#define TMR32B0EMR_EMC3_SHIFT 10
+
+/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
+#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
+#define TMR32B0CTCR_CTM_SHIFT 0
+#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
+#define TMR32B0CTCR_CIS_SHIFT 2
+#define TMR32B0CTCR_ENCC (1 << 4) // Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
+#define TMR32B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
+#define TMR32B0CTCR_SELCC_SHIFT 5
+
+/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
+#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
+#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
+#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
+#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
+
+/* WDMOD - 0x4000 4000 */
+#define WDMOD_WDEN (1 << 0) // Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
+#define WDMOD_WDRESET (1 << 1) // Watchdog reset enable bit. This bit is Set Only.
+#define WDMOD_WDTOF (1 << 2) // Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
+#define WDMOD_WDINT (1 << 3) // Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
+#define WDMOD_WDPROTECT (1 << 4) // Watchdog update mode. This bit is Set Only.
+
+/* WDTC - 0x4000 4004 */
+#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
+#define WDTC_COUNT_SHIFT 0
+
+/* WDFEED - 0x4000 4008 */
+#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
+#define WDFEED_FEED_SHIFT 0
+
+/* WDTV - 0x4000 400C */
+#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
+#define WDTV_COUNT_SHIFT 0
+
+/* WDWARNINT - 0x4000 4014 */
+#define WDWARNINT_WARNINT_MASK 0x03FF // Watchdog warning interrupt compare value.
+#define WDWARNINT_WARNINT_SHIFT 0
+
+/* WDWINDOW - 0x4000 4018 */
+#define WDWINDOW_WINDOW_MASK 0xFFFFFF // Watchdog window value.
+#define WDWINDOW_WINDOW_SHIFT 0
+
+/* WDMOD - address 0x4000 4000 */
+#define WDMOD_WDEN (1 << 0) // WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. The clock source lock feature is not available on all parts, see Section 23.1).
+#define WDMOD_WDRESET_WDRESET (1 << 1) // Watchdog reset enable bit (Set Only). When 1, og time-out will cause a chip reset.
+#define WDMOD_WDTOF (1 << 2) // WDTOF Watchdog time-out flag. Set when the watchdog
+#define WDMOD_WDINT (1 << 3) // WDINT Watchdog interrupt flag (Read Only, not clearable by software).
+
+/* WDTC - address 0x4000 4004 */
+#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
+#define WDTC_COUNT_SHIFT 0
+
+/* WDFEED - address 0x4000 4008 */
+#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
+#define WDFEED_FEED_SHIFT 0
+
+/* WDTV - address 0x4000 000C */
+#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
+#define WDTV_COUNT_SHIFT 0
+
+/* SYST_CSR - 0xE000 E010 */
+#define SYST_CSR_ENABLE (1 << 0) // System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
+#define SYST_CSR_TICKINT (1 << 1) // System Tick interrupt enable. When 1, the System Tick interrupt 0 is enabled. When 0, the System Tick interrupt is disabled. When enabled, the interrupt is generated when the System Tick counter counts down to 0.
+#define SYST_CSR_CLKSOURCE (1 << 2) // System Tick clock source selection. When 1, the system clock (CPU) clock is selected. When 0, the system clock/2 is selected as the reference clock.
+#define SYST_CSR_COUNTFLAG (1 << 16) // Returns 1 if the SysTick timer counted to 0 since the last read of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+
+/* SYST_RVR - 0xE000 E014 */
+#define SYST_RVR_RELOAD_MASK 0xFFFFFF // This is the value that is loaded into the System Tick counter when it 0 counts down to 0.
+#define SYST_RVR_RELOAD_SHIFT 0
+
+/* SYST_CVR - 0xE000 E018 */
+#define SYST_CVR_CURRENT_MASK 0xFFFFFF // Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
+#define SYST_CVR_CURRENT_SHIFT 0
+
+/* SYST_CALIB - 0xE000 E01C */
+#define SYST_CALIB_TENMS_MASK 0xFFFFFF // See Table 461.
+#define SYST_CALIB_TENMS_SHIFT 0
+#define SYST_CALIB_SKEW (1 << 30) // See Table 461.
+#define SYST_CALIB_NOREF (1 << 31) // See Table 461.
+
+/* AD0CR - address 0x4001 C000 */
+#define AD0CR_SEL_MASK 0x00FF // Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
+#define AD0CR_SEL_SHIFT 0
+#define AD0CR_CLKDIV_MASK 0xFF00 // The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0 should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
+#define AD0CR_CLKDIV_SHIFT 8
+#define AD0CR_BURST (1 << 16) // Burst mode Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register (Table 365) must be set to 0.
+#define AD0CR_CLKS_MASK 0xE0000 // This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
+#define AD0CR_CLKS_SHIFT 17
+#define AD0CR_START_MASK 0x7000000 // When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
+#define AD0CR_START_SHIFT 24
+#define AD0CR_EDGE (1 << 27) // This bit is significant only when the START field contains 010-111. In these cases:
+
+/* AD0GDR - address 0x4001 C004 */
+#define AD0GDR_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
+#define AD0GDR_V_VREF_SHIFT 6
+#define AD0GDR_CHN_MASK 0x7000000 // These bits contain the channel from which the result bits V_VREF X were converted.
+#define AD0GDR_CHN_SHIFT 24
+#define AD0GDR_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions 0 was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
+#define AD0GDR_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared 0 when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
+
+/* AD0INTEN - address 0x4001 C00C */
+#define AD0INTEN_ADINTEN_MASK 0x00FF // These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
+#define AD0INTEN_ADINTEN_SHIFT 0
+#define AD0INTEN_ADGINTEN (1 << 8) // When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. Remark: This bit must be set to 0 in burst mode (BURST = 1 in the AD0CR register). Reserved. Unused, always 0.
+
+/* AD0DR0 to AD0DR7 - addresses 0x4001 C010 to 0x4001 C02C */
+#define AD0DRn_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing the NA voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. Reserved.
+#define AD0DRn_V_VREF_SHIFT 6
+#define AD0DRn_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
+#define AD0DRn_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
+
+/* AD0STAT - address 0x4001 C030 */
+#define AD0STAT_DONE_MASK 0x00FF // These bits mirror the DONE status flags that appear in the result register for each A/D channel n.
+#define AD0STAT_DONE_SHIFT 0
+#define AD0STAT_OVERRUN_MASK 0xFF00 // These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
+#define AD0STAT_OVERRUN_SHIFT 8
+#define AD0STAT_ADINT (1 << 16) // This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. Reserved. Unused, always 0.
+
+/* FLASHCFG, address 0x4003 C010 */
+#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
+#define FLASHCFG_FLASHTIM_SHIFT 0
+
+/* FMSSTART - 0x4003 C020 */
+#define FMSSTART_START_MASK 0x1FFFF // Signature generation start address (corresponds to AHB byte address bits[20:4]).
+#define FMSSTART_START_SHIFT 0
+
+/* FMSSTOP - 0x4003 C024 */
+#define FMSSTOP_STOP_MASK 0x1FFFF // BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
+#define FMSSTOP_STOP_SHIFT 0
+#define FMSSTOP_SIG_START (1 << 17) // Start control bit for signature generation.
+
+/* FMSTAT - 0x4003 CFE0 */
+#define FMSTAT_SIG_DONE (1 << 2) // When 1, a previously started signature generation has 0 completed. See FMSTATCLR register description for clearing this flag.
+
+/* FMSTATCLR - 0x0x4003 CFE8 */
+#define FMSTATCLR_SIG_DONE_CLR (1 << 2) // Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h
new file mode 100644
index 000000000..4b9e4353c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h
@@ -0,0 +1,14 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC11xx.h"
+#include "cmsis_nvic.h"
+#include "bitfields.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c
new file mode 100644
index 000000000..3057d5551
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ *
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ *
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
+ * - No flash accesses will go to ram, as there will be nothing there
+ * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ * - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
+ uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
+ for(i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ // We can always read vectors at 0x0, as the addresses are remapped
+ uint32_t *vectors = (uint32_t*)0;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h
new file mode 100644
index 000000000..324e79704
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h
new file mode 100644
index 000000000..fa57304d4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11xx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11xx/LPC11Cxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11xx_H
+#define __SYSTEM_LPC11xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11xx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h
new file mode 100644
index 000000000..78d1a20d6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h
@@ -0,0 +1,776 @@
+
+/****************************************************************************************************//**
+ * @file LPC13Uxx.h
+ *
+ *
+ *
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * default LPC13Uxx Device Series
+ *
+ * @version V0.1
+ * @date 18. Jan 2012
+ *
+ * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
+ *
+ * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
+ * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
+ *
+ *******************************************************************************************************/
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC13Uxx
+ * @{
+ */
+
+#ifndef __LPC13UXX_H__
+#define __LPC13UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
+ PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
+ PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
+ PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
+ PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
+ PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
+ PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
+ PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
+ PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
+ GINT0_IRQn = 8, /*!< 8 GINT0 */
+ GINT1_IRQn = 9, /*!< 9 GINT1 */
+ Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
+ Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
+ RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
+ Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
+ SSP1_IRQn = 14, /*!< 14 SSP1 */
+ I2C_IRQn = 15, /*!< 15 I2C */
+ CT16B0_IRQn = 16, /*!< 16 CT16B0 */
+ CT16B1_IRQn = 17, /*!< 17 CT16B1 */
+ CT32B0_IRQn = 18, /*!< 18 CT32B0 */
+ CT32B1_IRQn = 19, /*!< 19 CT32B1 */
+ SSP0_IRQn = 20, /*!< 20 SSP0 */
+ USART_IRQn = 21, /*!< 21 USART */
+ USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
+ USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
+ ADC_IRQn = 24, /*!< 24 ADC */
+ WDT_IRQn = 25, /*!< 25 WDT */
+ BOD_IRQn = 26, /*!< 26 BOD */
+ FMC_IRQn = 27, /*!< 27 FMC */
+ Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
+ Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
+ USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
+ Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
+
+#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
+#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
+ union{
+ __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ struct{
+ __IO uint32_t ADR1;
+ __IO uint32_t ADR2;
+ __IO uint32_t ADR3;
+ };
+ };
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT16B0 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
+ __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CTxxBx_Type;
+
+typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT16B1 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT32B0 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT32B1 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
+ __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
+ __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
+ __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
+ __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
+ __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
+ __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
+ __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+ __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCON -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40044000) IOCON Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
+ __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
+ __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
+ __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
+ __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
+ __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
+ __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
+ __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
+ __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
+ __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
+ __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
+ __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __I uint32_t RESERVED3;
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __I uint32_t RESERVED4[9];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __I uint32_t RESERVED5;
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED6;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED7[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
+ __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
+ __I uint32_t RESERVED9[3];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __I uint32_t RESERVED10;
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED11[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __I uint32_t RESERVED12;
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED13[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED14[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED15[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED16[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED17[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED18[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED19[111];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT1 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Repetitive Interrupt Timer (RIT) -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
+ __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
+ __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
+ __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
+ __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
+ __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
+ __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40020000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
+ __I uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
+ __I uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
+ __I uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
+ __I uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
+ __I uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_RITIMER_BASE (0x40064000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group h1usf */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC13UXX_H__
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/LPC1347.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/LPC1347.sct
new file mode 100644
index 000000000..2b47f77f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/LPC1347.sct
@@ -0,0 +1,19 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (AHBSRAM1)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/startup_LPC13xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/startup_LPC13xx.s
new file mode 100644
index 000000000..49fdbeb40
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/startup_LPC13xx.s
@@ -0,0 +1,231 @@
+;/*****************************************************************************
+; * @file: startup_LPC13xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC13xx Device Series
+; * @version: V1.02, modified for mbed
+; * @date: 27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC1347
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+
+ DCD PIN_INT0_Handler ; All GPIO pin can be routed to PIN_INTx
+ DCD PIN_INT1_Handler
+ DCD PIN_INT2_Handler
+ DCD PIN_INT3_Handler
+ DCD PIN_INT4_Handler
+ DCD PIN_INT5_Handler
+ DCD PIN_INT6_Handler
+ DCD PIN_INT7_Handler
+ DCD GINT0_Handler
+ DCD GINT1_Handler ; PIO0 (0:7)
+ DCD 0
+ DCD 0
+ DCD OSTIMER_Handler
+ DCD 0
+ DCD SSP1_Handler ; SSP1
+ DCD I2C_Handler ; I2C
+ DCD CT16B0_Handler ; 16-bit Timer0
+ DCD CT16B1_Handler ; 16-bit Timer1
+ DCD CT32B0_Handler ; 32-bit Timer0
+ DCD CT32B1_Handler ; 32-bit Timer1
+ DCD SSP0_Handler ; SSP0
+ DCD USART_Handler ; USART
+ DCD USB_Handler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_Handler ; A/D Converter
+ DCD WDT_Handler ; Watchdog timer
+ DCD BOD_Handler ; Brown Out Detect
+ DCD FMC_Handler ; IP2111 Flash Memory Controller
+ DCD OSCFAIL_Handler ; OSC FAIL
+ DCD PVTCIRCUIT_Handler ; PVT CIRCUIT
+ DCD USBWakeup_Handler ; USB wake up
+ DCD 0
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT PIN_INT0_Handler [WEAK]
+ EXPORT PIN_INT1_Handler [WEAK]
+ EXPORT PIN_INT2_Handler [WEAK]
+ EXPORT PIN_INT3_Handler [WEAK]
+ EXPORT PIN_INT4_Handler [WEAK]
+ EXPORT PIN_INT5_Handler [WEAK]
+ EXPORT PIN_INT6_Handler [WEAK]
+ EXPORT PIN_INT7_Handler [WEAK]
+ EXPORT GINT0_Handler [WEAK]
+ EXPORT GINT1_Handler [WEAK]
+ EXPORT OSTIMER_Handler [WEAK]
+ EXPORT SSP1_Handler [WEAK]
+ EXPORT I2C_Handler [WEAK]
+ EXPORT CT16B0_Handler [WEAK]
+ EXPORT CT16B1_Handler [WEAK]
+ EXPORT CT32B0_Handler [WEAK]
+ EXPORT CT32B1_Handler [WEAK]
+ EXPORT SSP0_Handler [WEAK]
+ EXPORT USART_Handler [WEAK]
+ EXPORT USB_Handler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_Handler [WEAK]
+ EXPORT WDT_Handler [WEAK]
+ EXPORT BOD_Handler [WEAK]
+ EXPORT FMC_Handler [WEAK]
+ EXPORT OSCFAIL_Handler [WEAK]
+ EXPORT PVTCIRCUIT_Handler [WEAK]
+ EXPORT USBWakeup_Handler [WEAK]
+
+PIN_INT0_Handler
+PIN_INT1_Handler
+PIN_INT2_Handler
+PIN_INT3_Handler
+PIN_INT4_Handler
+PIN_INT5_Handler
+PIN_INT6_Handler
+PIN_INT7_Handler
+GINT0_Handler
+GINT1_Handler
+OSTIMER_Handler
+SSP1_Handler
+I2C_Handler
+CT16B0_Handler
+CT16B1_Handler
+CT32B0_Handler
+CT32B1_Handler
+SSP0_Handler
+USART_Handler
+USB_Handler
+USB_FIQHandler
+ADC_Handler
+WDT_Handler
+BOD_Handler
+FMC_Handler
+OSCFAIL_Handler
+PVTCIRCUIT_Handler
+USBWakeup_Handler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/LPC1347.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/LPC1347.sct
new file mode 100644
index 000000000..2b47f77f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/LPC1347.sct
@@ -0,0 +1,19 @@
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (AHBSRAM1)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/startup_LPC13xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/startup_LPC13xx.s
new file mode 100644
index 000000000..eade695de
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/startup_LPC13xx.s
@@ -0,0 +1,215 @@
+;/*****************************************************************************
+; * @file: startup_LPC13xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC13xx Device Series
+; * @version: V1.02, modified for mbed
+; * @date: 27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10002000 ; Top of RAM from LPC1347
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+
+ DCD PIN_INT0_Handler ; All GPIO pin can be routed to PIN_INTx
+ DCD PIN_INT1_Handler
+ DCD PIN_INT2_Handler
+ DCD PIN_INT3_Handler
+ DCD PIN_INT4_Handler
+ DCD PIN_INT5_Handler
+ DCD PIN_INT6_Handler
+ DCD PIN_INT7_Handler
+ DCD GINT0_Handler
+ DCD GINT1_Handler ; PIO0 (0:7)
+ DCD 0
+ DCD 0
+ DCD OSTIMER_Handler
+ DCD 0
+ DCD SSP1_Handler ; SSP1
+ DCD I2C_Handler ; I2C
+ DCD CT16B0_Handler ; 16-bit Timer0
+ DCD CT16B1_Handler ; 16-bit Timer1
+ DCD CT32B0_Handler ; 32-bit Timer0
+ DCD CT32B1_Handler ; 32-bit Timer1
+ DCD SSP0_Handler ; SSP0
+ DCD USART_Handler ; USART
+ DCD USB_Handler ; USB IRQ
+ DCD USB_FIQHandler ; USB FIQ
+ DCD ADC_Handler ; A/D Converter
+ DCD WDT_Handler ; Watchdog timer
+ DCD BOD_Handler ; Brown Out Detect
+ DCD FMC_Handler ; IP2111 Flash Memory Controller
+ DCD OSCFAIL_Handler ; OSC FAIL
+ DCD PVTCIRCUIT_Handler ; PVT CIRCUIT
+ DCD USBWakeup_Handler ; USB wake up
+ DCD 0
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT PIN_INT0_Handler [WEAK]
+ EXPORT PIN_INT1_Handler [WEAK]
+ EXPORT PIN_INT2_Handler [WEAK]
+ EXPORT PIN_INT3_Handler [WEAK]
+ EXPORT PIN_INT4_Handler [WEAK]
+ EXPORT PIN_INT5_Handler [WEAK]
+ EXPORT PIN_INT6_Handler [WEAK]
+ EXPORT PIN_INT7_Handler [WEAK]
+ EXPORT GINT0_Handler [WEAK]
+ EXPORT GINT1_Handler [WEAK]
+ EXPORT OSTIMER_Handler [WEAK]
+ EXPORT SSP1_Handler [WEAK]
+ EXPORT I2C_Handler [WEAK]
+ EXPORT CT16B0_Handler [WEAK]
+ EXPORT CT16B1_Handler [WEAK]
+ EXPORT CT32B0_Handler [WEAK]
+ EXPORT CT32B1_Handler [WEAK]
+ EXPORT SSP0_Handler [WEAK]
+ EXPORT USART_Handler [WEAK]
+ EXPORT USB_Handler [WEAK]
+ EXPORT USB_FIQHandler [WEAK]
+ EXPORT ADC_Handler [WEAK]
+ EXPORT WDT_Handler [WEAK]
+ EXPORT BOD_Handler [WEAK]
+ EXPORT FMC_Handler [WEAK]
+ EXPORT OSCFAIL_Handler [WEAK]
+ EXPORT PVTCIRCUIT_Handler [WEAK]
+ EXPORT USBWakeup_Handler [WEAK]
+
+PIN_INT0_Handler
+PIN_INT1_Handler
+PIN_INT2_Handler
+PIN_INT3_Handler
+PIN_INT4_Handler
+PIN_INT5_Handler
+PIN_INT6_Handler
+PIN_INT7_Handler
+GINT0_Handler
+GINT1_Handler
+OSTIMER_Handler
+SSP1_Handler
+I2C_Handler
+CT16B0_Handler
+CT16B1_Handler
+CT32B0_Handler
+CT32B1_Handler
+SSP0_Handler
+USART_Handler
+USB_Handler
+USB_FIQHandler
+ADC_Handler
+WDT_Handler
+BOD_Handler
+FMC_Handler
+OSCFAIL_Handler
+PVTCIRCUIT_Handler
+USBWakeup_Handler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/LPC1347.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/LPC1347.ld
new file mode 100644
index 000000000..026266613
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/LPC1347.ld
@@ -0,0 +1,149 @@
+/* Linker script for mbed LPC1347 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+
+ RAM1(rwx) : ORIGIN = 0x20000000, LENGTH = 2K
+ USB_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 2K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s
new file mode 100644
index 000000000..7d5f0e04d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s
@@ -0,0 +1,213 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x800
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+
+ .long PIN_INT0_Handler /* All GPIO pin can be routed to PIN_INTx */
+ .long PIN_INT1_Handler
+ .long PIN_INT2_Handler
+ .long PIN_INT3_Handler
+ .long PIN_INT4_Handler
+ .long PIN_INT5_Handler
+ .long PIN_INT6_Handler
+ .long PIN_INT7_Handler
+ .long GINT0_Handler
+ .long GINT1_Handler /* PIO0 (0:7) */
+ .long 0
+ .long 0
+ .long OSTIMER_Handler
+ .long 0
+ .long SSP1_Handler /* SSP1 */
+ .long I2C_Handler /* I2C */
+ .long CT16B0_Handler /* 16-bit Timer0 */
+ .long CT16B1_Handler /* 16-bit Timer1 */
+ .long CT32B0_Handler /* 32-bit Timer0 */
+ .long CT32B1_Handler /* 32-bit Timer1 */
+ .long SSP0_Handler /* SSP0 */
+ .long USART_Handler /* USART */
+ .long USB_Handler /* USB IRQ */
+ .long USB_FIQHandler /* USB FIQ */
+ .long ADC_Handler /* A/D Converter */
+ .long WDT_Handler /* Watchdog timer */
+ .long BOD_Handler /* Brown Out Detect */
+ .long FMC_Handler /* IP2111 Flash Memory Controller */
+ .long OSCFAIL_Handler /* OSC FAIL */
+ .long PVTCIRCUIT_Handler /* PVT CIRCUIT */
+ .long USBWakeup_Handler /* USB wake up */
+ .long 0
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler PIN_INT0_Handler
+ def_irq_default_handler PIN_INT1_Handler
+ def_irq_default_handler PIN_INT2_Handler
+ def_irq_default_handler PIN_INT3_Handler
+ def_irq_default_handler PIN_INT4_Handler
+ def_irq_default_handler PIN_INT5_Handler
+ def_irq_default_handler PIN_INT6_Handler
+ def_irq_default_handler PIN_INT7_Handler
+ def_irq_default_handler GINT0_Handler
+ def_irq_default_handler GINT1_Handler
+ def_irq_default_handler OSTIMER_Handler
+ def_irq_default_handler SSP1_Handler
+ def_irq_default_handler I2C_Handler
+ def_irq_default_handler CT16B0_Handler
+ def_irq_default_handler CT16B1_Handler
+ def_irq_default_handler CT32B0_Handler
+ def_irq_default_handler CT32B1_Handler
+ def_irq_default_handler SSP0_Handler
+ def_irq_default_handler USART_Handler
+ def_irq_default_handler USB_Handler
+ def_irq_default_handler USB_FIQHandler
+ def_irq_default_handler ADC_Handler
+ def_irq_default_handler WDT_Handler
+ def_irq_default_handler BOD_Handler
+ def_irq_default_handler FMC_Handler
+ def_irq_default_handler OSCFAIL_Handler
+ def_irq_default_handler PVTCIRCUIT_Handler
+ def_irq_default_handler USBWakeup_Handler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf
new file mode 100644
index 000000000..fb6b9bb26
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf
@@ -0,0 +1,47 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FDF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __region_USB_PKG_RAM_start__ = 0x20004000;
+define symbol __region_USB_PKG_RAM_end__ = 0x200047FF;
+
+define symbol __RAM1_start__ = 0x20000000;
+define symbol __RAM1_end__ = 0x200007FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+define region USB_PKG_RAM_region = mem:[from __region_USB_PKG_RAM_start__ to __region_USB_PKG_RAM_end__];
+define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in USB_PKG_RAM_region
+ { readwrite data section USB_PACKET_MEMORY };
+place in RAM1_region { section .sram };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/startup_LPC1347.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/startup_LPC1347.s
new file mode 100644
index 000000000..b90a8bee4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/startup_LPC1347.s
@@ -0,0 +1,178 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 1106 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ DCD FLEX_INT0_IRQHandler ; GPIO pin interrupt 0
+ DCD FLEX_INT1_IRQHandler ; GPIO pin interrupt 1
+ DCD FLEX_INT2_IRQHandler ; GPIO pin interrupt 2
+ DCD FLEX_INT3_IRQHandler ; GPIO pin interrupt 3
+ DCD FLEX_INT4_IRQHandler ; GPIO pin interrupt 4
+ DCD FLEX_INT5_IRQHandler ; GPIO pin interrupt 5
+ DCD FLEX_INT6_IRQHandler ; GPIO pin interrupt 6
+ DCD FLEX_INT7_IRQHandler ; GPIO pin interrupt 7
+ DCD GINT0_IRQHandler ; GPIO GROUP0 interrupt
+ DCD GINT1_IRQHandler ; GPIO GROUP1 interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SSP1_IRQHandler ; SSP1 interrupt
+ DCD I2C_IRQHandler ; I2C interrupt
+ DCD CT16B0_IRQHandler ; CT16B0 Match 0-3, Capture 0
+ DCD CT16B1_IRQHandler ; CT16B1 Match 0-3, Capture 0
+ DCD CT32B0_IRQHandler ; CT32B0 Match 0-3, Capture 0
+ DCD CT32B1_IRQHandler ; CT32B1 Match 0-3, Capture 0
+ DCD SSP0_IRQHandler ; SSP0 interrupt
+ DCD USART_IRQHandler ; USART interrupt
+ DCD USB_IRQHandler ; USB_IRQ interrupt
+ DCD USB_FIQHandler ; USB_FIQ interrupt
+ DCD ADC_IRQHandler ; ADC interrupt
+ DCD WWDT_IRQHandler ; WWDT interrupt
+ DCD BOD_IRQHandler ; BOD interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USBWakeup_IRQHandler ; USB_WAKEUP interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK FLEX_INT0_IRQHandler
+ PUBWEAK FLEX_INT1_IRQHandler
+ PUBWEAK FLEX_INT2_IRQHandler
+ PUBWEAK FLEX_INT3_IRQHandler
+ PUBWEAK FLEX_INT4_IRQHandler
+ PUBWEAK FLEX_INT5_IRQHandler
+ PUBWEAK FLEX_INT6_IRQHandler
+ PUBWEAK FLEX_INT7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK CT16B0_IRQHandler
+ PUBWEAK CT16B1_IRQHandler
+ PUBWEAK CT32B0_IRQHandler
+ PUBWEAK CT32B1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK USART_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK USB_FIQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK WWDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+CT16B0_IRQHandler
+CT16B1_IRQHandler
+CT32B0_IRQHandler
+CT32B1_IRQHandler
+SSP0_IRQHandler
+USART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WWDT_IRQHandler
+BOD_IRQHandler
+USBWakeup_IRQHandler
+Default_Handler
+ B Default_Handler
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h
new file mode 100644
index 000000000..de462e148
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC13XX specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC13Uxx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c
new file mode 100644
index 000000000..c057a64d9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h
new file mode 100644
index 000000000..324e79704
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c
new file mode 100644
index 000000000..acb4341e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c
@@ -0,0 +1,437 @@
+/******************************************************************************
+ * @file system_LPC13Uxx.c
+ * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC13xx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC13Uxx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+//
+// <h> USB PLL Control Register (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o7.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o7.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
+// <o8.0..1> SEL: USB PLL Clock Source
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Source Select Register (USBCLKSEL)
+// <o9.0..1> SEL: System PLL Clock Source
+// <0=> USB PLL out
+// <1=> Main clock
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Divider Register (USBCLKDIV)
+// <o10.0..7> DIV: USB Clock Divider
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
+#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __IRC_OSC_CLK;
+ } else {
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __SYS_OSC_CLK;
+ } else {
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+
+#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
+
+ /* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
+#endif
+
+#endif
+
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h
new file mode 100644
index 000000000..615a5e23c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC13Uxx.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC13Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC13Uxx_H
+#define __SYSTEM_LPC13Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC13Uxx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h
new file mode 100644
index 000000000..60469c47e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h
@@ -0,0 +1,1725 @@
+
+/****************************************************************************************************//**
+ * @file LPC15xx.h
+ *
+ * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
+ * LPC15xx from .
+ *
+ * @version V0.3
+ * @date 17. July 2013
+ *
+ * @note Generated with SVDConv V2.80
+ * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
+ *
+ * modified by Keil
+ * modified by ytsuboi
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC15xx
+ * @{
+ */
+
+#ifndef LPC15XX_H
+#define LPC15XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
+ WDT_IRQn = 0, /*!< 0 WDT */
+ BOD_IRQn = 1, /*!< 1 BOD */
+ FLASH_IRQn = 2, /*!< 2 FLASH */
+ EE_IRQn = 3, /*!< 3 EE */
+ DMA_IRQn = 4, /*!< 4 DMA */
+ GINT0_IRQn = 5, /*!< 5 GINT0 */
+ GINT1_IRQn = 6, /*!< 6 GINT1 */
+ PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */
+ PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */
+ PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */
+ PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */
+ PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */
+ PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */
+ PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */
+ PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */
+ RIT_IRQn = 15, /*!< 15 RIT */
+ SCT0_IRQn = 16, /*!< 16 SCT0 */
+ SCT1_IRQn = 17, /*!< 17 SCT1 */
+ SCT2_IRQn = 18, /*!< 18 SCT2 */
+ SCT3_IRQn = 19, /*!< 19 SCT3 */
+ MRT_IRQn = 20, /*!< 20 MRT */
+ UART0_IRQn = 21, /*!< 21 UART0 */
+ UART1_IRQn = 22, /*!< 22 UART1 */
+ UART2_IRQn = 23, /*!< 23 UART2 */
+ I2C0_IRQn = 24, /*!< 24 I2C0 */
+ SPI0_IRQn = 25, /*!< 25 SPI0 */
+ SPI1_IRQn = 26, /*!< 26 SPI1 */
+ C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */
+ USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */
+ USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */
+ USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
+ ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */
+ ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */
+ ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */
+ ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */
+ ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */
+ ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */
+ ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */
+ ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */
+ DAC_IRQn = 39, /*!< 39 DAC */
+ CMP0_IRQn = 40, /*!< 40 CMP0 */
+ CMP1_IRQn = 41, /*!< 41 CMP1 */
+ CMP2_IRQn = 42, /*!< 42 CMP2 */
+ CMP3_IRQn = 43, /*!< 43 CMP3 */
+ QEI_IRQn = 44, /*!< 44 QEI */
+ RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */
+ RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
+#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
+#include "system_LPC15xx.h" /*!< LPC15xx System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< GPIO_PORT Structure */
+ __IO uint8_t B[76]; /*!< Byte pin registers */
+ __I uint32_t RESERVED0[45];
+ __IO uint32_t W[76]; /*!< Word pin registers */
+ __I uint32_t RESERVED1[1908];
+ __IO uint32_t DIR[3]; /*!< Port Direction registers */
+ __I uint32_t RESERVED2[29];
+ __IO uint32_t MASK[3]; /*!< Port Mask register */
+ __I uint32_t RESERVED3[29];
+ __IO uint32_t PIN[3]; /*!< Port pin register */
+ __I uint32_t RESERVED4[29];
+ __IO uint32_t MPIN[3]; /*!< Masked port register */
+ __I uint32_t RESERVED5[29];
+ __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
+ __I uint32_t RESERVED6[29];
+ __O uint32_t CLR[3]; /*!< Clear port */
+ __I uint32_t RESERVED7[29];
+ __O uint32_t NOT[3]; /*!< Toggle port */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA controller (DMA)
+ */
+
+typedef struct { /*!< DMA Structure */
+ __IO uint32_t CTRL; /*!< DMA control. */
+ __I uint32_t INTSTAT; /*!< Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED28;
+ __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */
+ __I uint32_t RESERVED29;
+ __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ USB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USB device controller (USB)
+ */
+
+typedef struct { /*!< USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
+ __IO uint32_t LPM; /*!< Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< USB interrupt status register */
+ __IO uint32_t INTEN; /*!< USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
+ __I uint32_t RESERVED0;
+ __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< CRC Structure */
+ __IO uint32_t MODE; /*!< CRC mode register */
+ __IO uint32_t SEED; /*!< CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< CRC data register */
+ __I uint32_t SUM; /*!< CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
+ */
+
+typedef struct { /*!< SCT0 Structure */
+ __IO uint32_t CONFIG; /*!< SCT configuration register */
+ __IO uint32_t CTRL; /*!< SCT control register */
+ __IO uint32_t LIMIT; /*!< SCT limit register */
+ __IO uint32_t HALT; /*!< SCT halt condition register */
+ __IO uint32_t STOP; /*!< SCT stop condition register */
+ __IO uint32_t START; /*!< SCT start condition register */
+ __IO uint32_t DITHER; /*!< SCT dither condition register */
+ __I uint32_t RESERVED0[9];
+ __IO uint32_t COUNT; /*!< SCT counter register */
+ __IO uint32_t STATE; /*!< SCT state register */
+ __I uint32_t INPUT; /*!< SCT input register */
+ __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
+ __IO uint32_t RES; /*!< SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< SCT event flag register */
+ __IO uint32_t CONEN; /*!< SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
+
+ union {
+ __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+
+ union {
+ __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
+ to REGMODE15 = 0 */
+ __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
+ REGMODE15 = 1 */
+ };
+ __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
+ 0 to 5. */
+ __I uint32_t RESERVED2[42];
+
+ union {
+ __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
+ = 1 */
+ __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
+ = 0 */
+ };
+ __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
+ registers 0 to 5. */
+ __I uint32_t RESERVED3[42];
+ __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */
+ __I uint32_t RESERVED4[96];
+ __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */
+} LPC_SCT0_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT2 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
+ */
+
+typedef struct { /*!< SCT2 Structure */
+ __IO uint32_t CONFIG; /*!< SCT configuration register */
+ __IO uint32_t CTRL; /*!< SCT control register */
+ __IO uint32_t LIMIT; /*!< SCT limit register */
+ __IO uint32_t HALT; /*!< SCT halt condition register */
+ __IO uint32_t STOP; /*!< SCT stop condition register */
+ __IO uint32_t START; /*!< SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< SCT counter register */
+ __IO uint32_t STATE; /*!< SCT state register */
+ __I uint32_t INPUT; /*!< SCT input register */
+ __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
+ __IO uint32_t RES; /*!< SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< SCT event flag register */
+ __IO uint32_t CONEN; /*!< SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
+
+ union {
+ __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ };
+
+ union {
+ __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ };
+
+ union {
+ __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+
+ union {
+ __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
+ REGMODE7 = 0 */
+ };
+ __I uint32_t RESERVED2[56];
+
+ union {
+ __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
+ = 1 */
+ __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
+ = 0 */
+ };
+ __I uint32_t RESERVED3[56];
+ __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
+ __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
+ __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
+ __I uint32_t RESERVED4[108];
+ __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
+ __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
+ __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
+} LPC_SCT2_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 12-bit ADC controller ADC0/1 (ADC0)
+ */
+
+typedef struct { /*!< ADC0 Structure */
+ __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
+ bits for each sequence and the A/D power-down bit. */
+ __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
+ internal source for various channels */
+ __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
+ and channel selection for conversion sequence-A. Also specifies
+ interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
+ and channel selection for conversion sequence-B. Also specifies
+ interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
+ the result of the most recent A/D conversion performed under
+ sequence-B */
+ __I uint32_t RESERVED0[2];
+ __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
+ of the most recent conversion completed on channel 0. */
+ __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
+ level for automatic threshold comparison for any channels linked
+ to threshold pair 1. */
+ __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
+ threshold compare registers are to be used for each channel */
+ __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
+ bits that enable the sequence-A, sequence-B, threshold compare
+ and data overrun interrupts to be generated. */
+ __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
+ and the individual component overrun and threshold-compare flags.
+ (The overrun bits replicate information stored in the result
+ registers). */
+ __IO uint32_t TRM; /*!< ADC trim register. */
+} LPC_ADC0_Type;
+
+
+/* ================================================================================ */
+/* ================ DAC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 12-bit DAC Modification (DAC)
+ */
+
+typedef struct { /*!< DAC Structure */
+ __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
+ value to be converted to analog. */
+ __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
+ DAC operation and the interrupt/dma request flag. */
+ __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
+ value for the internal DAC DMA/Interrupt timer. */
+} LPC_DAC_Type;
+
+
+/* ================================================================================ */
+/* ================ ACMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog comparators ACMP0/1/2/3 (ACMP)
+ */
+
+typedef struct { /*!< ACMP Structure */
+ __IO uint32_t CTRL; /*!< Comparator block control register */
+ __IO uint32_t CMP0; /*!< Comparator 0 source control */
+ __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */
+ __IO uint32_t CMP1; /*!< Comparator 1 source control */
+ __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */
+ __IO uint32_t CMP2; /*!< Comparator 2 source control */
+ __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */
+ __IO uint32_t CMP3; /*!< Comparator 3 source control */
+ __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */
+} LPC_ACMP_Type;
+
+
+/* ================================================================================ */
+/* ================ INMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Input multiplexing (INMUX) (INMUX)
+ */
+
+typedef struct { /*!< INMUX Structure */
+ __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */
+ __I uint32_t RESERVED2[5];
+ __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */
+ __I uint32_t RESERVED3[21];
+ __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */
+ __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */
+ __I uint32_t RESERVED4[14];
+ __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
+ clock */
+ __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */
+} LPC_INMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ RTC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Real-Time Clock (RTC) (RTC)
+ */
+
+typedef struct { /*!< RTC Structure */
+ __IO uint32_t CTRL; /*!< RTC control register */
+ __IO uint32_t MATCH; /*!< RTC match register */
+ __IO uint32_t COUNT; /*!< RTC counter register */
+ __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
+} LPC_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< WWDT Structure */
+ __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
+ and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
+ the time-out value. */
+ __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
+ to this register reloads the Watchdog timer with the value contained
+ in WDTC. */
+ __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
+ the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ SWM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Switch Matrix (SWM) (SWM)
+ */
+
+typedef struct { /*!< SWM Structure */
+ union {
+ __IO uint32_t PINASSIGN[16];
+ struct {
+ __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
+ U0_RTS, U0_CTS. */
+ __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
+ U1_RXD, U1_RTS. */
+ __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
+ U2_TXD, U2_RXD. */
+ __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */
+ __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */
+ __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */
+ __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */
+ __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */
+ __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */
+ __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */
+ __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */
+ __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */
+ __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */
+ __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
+ __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
+ __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
+ };
+ };
+ __I uint32_t RESERVED0[96];
+ __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
+ __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
+} LPC_SWM_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Management Unit (PMU) (PMU)
+ */
+
+typedef struct { /*!< PMU Structure */
+ __IO uint32_t PCON; /*!< Power control register */
+ __IO uint32_t GPREG0; /*!< General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< Deep power-down control register */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< USART0 Structure */
+ __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
+ that typically are not changed during operation. */
+ __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
+ likely to change during operation. */
+ __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
+ here. Writing ones clears some bits in the register. Some bits
+ can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
+ interrupt enable bit for each potential USART interrupt. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
+ of bits in the INTENSET register. Writing a 1 to any implemented
+ bit position causes the corresponding bit to be cleared. */
+ __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */
+ __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
+ received with the current USART receive status. Allows DMA or
+ software to recover incoming data and status together. */
+ __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */
+ __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
+ value. */
+ __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
+ enabled. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< SPI0 Structure */
+ __IO uint32_t CFG; /*!< SPI Configuration register */
+ __IO uint32_t DLY; /*!< SPI Delay register */
+ __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
+ to that bit position */
+ __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
+ from this register. Writing a 1 to any implemented bit position
+ causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
+ position causes the corresponding bit in INTENSET to be cleared. */
+ __I uint32_t RXDAT; /*!< SPI Receive Data */
+ __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */
+ __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */
+ __IO uint32_t TXCTL; /*!< SPI Transmit Control */
+ __IO uint32_t DIV; /*!< SPI clock Divider */
+ __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
+} LPC_SPI0_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C-bus interface (I2C0)
+ */
+
+typedef struct { /*!< I2C0 Structure */
+ __IO uint32_t CFG; /*!< Configuration for shared functions. */
+ __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
+ __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
+ __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
+ __IO uint32_t TIMEOUT; /*!< Time-out value register. */
+ __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
+ what time increments are used for the MSTTIME and SLVTIME registers. */
+ __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MSTCTL; /*!< Master control register. */
+ __IO uint32_t MSTTIME; /*!< Master timing configuration. */
+ __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t SLVCTL; /*!< Slave control register. */
+ __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
+ __IO uint32_t SLVADR0; /*!< Slave address 0. */
+ __IO uint32_t SLVADR1; /*!< Slave address 0. */
+ __IO uint32_t SLVADR2; /*!< Slave address 0. */
+ __IO uint32_t SLVADR3; /*!< Slave address 0. */
+ __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
+ __I uint32_t RESERVED2[9];
+ __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ QEI ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Quadrature Encoder Interface (QEI) (QEI)
+ */
+
+typedef struct { /*!< QEI Structure */
+ __O uint32_t CON; /*!< Control register */
+ __I uint32_t STAT; /*!< Encoder status register */
+ __IO uint32_t CONF; /*!< Configuration register */
+ __I uint32_t POS; /*!< Position register */
+ __IO uint32_t MAXPOS; /*!< Maximum position register */
+ __IO uint32_t CMPOS0; /*!< position compare register 0 */
+ __IO uint32_t CMPOS1; /*!< position compare register 1 */
+ __IO uint32_t CMPOS2; /*!< position compare register 2 */
+ __I uint32_t INXCNT; /*!< Index count register */
+ __IO uint32_t INXCMP0; /*!< Index compare register 0 */
+ __IO uint32_t LOAD; /*!< Velocity timer reload register */
+ __I uint32_t TIME; /*!< Velocity timer register */
+ __I uint32_t VEL; /*!< Velocity counter register */
+ __I uint32_t CAP; /*!< Velocity capture register */
+ __IO uint32_t VELCOMP; /*!< Velocity compare register */
+ __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /*!< Index acceptance window register */
+ __IO uint32_t INXCMP1; /*!< Index compare register 1 */
+ __IO uint32_t INXCMP2; /*!< Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /*!< Interrupt enable clear register */
+ __O uint32_t IES; /*!< Interrupt enable set register */
+ __I uint32_t INTSTAT; /*!< Interrupt status register */
+ __O uint32_t IE; /*!< Interrupt enable clear register */
+ __O uint32_t CLR; /*!< Interrupt status clear register */
+ __O uint32_t SET; /*!< Interrupt status set register */
+} LPC_QEI_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief System configuration (SYSCON) (SYSCON)
+ */
+
+typedef struct { /*!< SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
+ __I uint32_t RESERVED1;
+ __IO uint32_t NMISRC; /*!< NMI Source Control */
+ __I uint32_t RESERVED2[8];
+ __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
+ __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
+ __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
+ __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
+ __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */
+ __I uint32_t RESERVED3[10];
+ __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */
+ __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */
+ __IO uint32_t USBCLKSEL; /*!< USB clock source select */
+ __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */
+ __I uint32_t RESERVED4;
+ __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */
+ __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */
+ __I uint32_t RESERVED5;
+ __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
+ __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
+ __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */
+ __I uint32_t RESERVED6[5];
+ __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
+ __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */
+ __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */
+ __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
+ baud rate generator. */
+ __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
+ filter */
+ __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */
+ __I uint32_t RESERVED7[4];
+ __IO uint32_t USBCLKDIV; /*!< USB clock divider */
+ __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
+ __I uint32_t RESERVED8;
+ __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
+ __I uint32_t RESERVED9[11];
+ __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */
+ __IO uint32_t USBCLKCTRL; /*!< USB clock control */
+ __IO uint32_t USBCLKST; /*!< USB clock status */
+ __I uint32_t RESERVED10[19];
+ __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
+ __I uint32_t RESERVED11;
+ __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
+ __I uint32_t RESERVED12;
+ __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */
+ __I uint32_t RESERVED13;
+ __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< USB PLL status */
+ __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */
+ __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */
+ __I uint32_t RESERVED14[21];
+ __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< Power configuration register */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */
+ __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ MRT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Multi-Rate Timer (MRT) (MRT)
+ */
+
+typedef struct { /*!< MRT Structure */
+ __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
+ the TIMER0 register. */
+ __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
+ __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */
+ __IO uint32_t STAT0; /*!< MRT0 Status register. */
+ __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
+ the TIMER0 register. */
+ __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
+ __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */
+ __IO uint32_t STAT1; /*!< MRT0 Status register. */
+ __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
+ the TIMER0 register. */
+ __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
+ __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */
+ __IO uint32_t STAT2; /*!< MRT0 Status register. */
+ __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
+ the TIMER0 register. */
+ __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
+ __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */
+ __IO uint32_t STAT3; /*!< MRT0 Status register. */
+ __I uint32_t RESERVED0[45];
+ __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
+ first idle channel. */
+ __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */
+} LPC_MRT_Type;
+
+
+/* ================================================================================ */
+/* ================ PINT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interruptand pattern match (PINT) (PINT)
+ */
+
+typedef struct { /*!< PINT Structure */
+ __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
+ __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
+ __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
+ __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
+ register */
+ __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
+ __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
+ __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
+} LPC_PINT_Type;
+
+
+/* ================================================================================ */
+/* ================ GINT0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Group interrupt 0/1 (GINT0/1) (GINT0)
+ */
+
+typedef struct { /*!< GINT0 Structure */
+ __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */
+} LPC_GINT0_Type;
+
+
+/* ================================================================================ */
+/* ================ RIT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Repetitive Interrupt Timer (RIT) (RIT)
+ */
+
+typedef struct { /*!< RIT Structure */
+ __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
+ value. */
+ __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
+ value. A 1 written to any bit will force a compare on the corresponding
+ bit of the counter and compare register. */
+ __IO uint32_t CTRL; /*!< Control register. */
+ __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */
+ __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
+ value. */
+ __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
+ value. A 1 written to any bit will force a compare on the corresponding
+ bit of the counter and compare register. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */
+} LPC_RIT_Type;
+
+
+/* ================================================================================ */
+/* ================ SCTIPU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SCT Input Processing Unit (IPU) (SCTIPU)
+ */
+
+typedef struct { /*!< SCTIPU Structure */
+ __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
+ latch/sample-enable mux selects, and sample overrride bits for
+ the SAMPLE module. */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
+ to ORed Abort Output 0. */
+ __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
+ input source caused abort output 0. */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
+ to ORed Abort Output 0. */
+ __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
+ input source caused abort output 0. */
+ __I uint32_t RESERVED2[6];
+ __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
+ to ORed Abort Output 0. */
+ __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
+ input source caused abort output 0. */
+ __I uint32_t RESERVED3[6];
+ __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
+ to ORed Abort Output 0. */
+ __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
+ input source caused abort output 0. */
+} LPC_SCTIPU_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< FLASHCTRL Structure */
+ __I uint32_t RESERVED0[8];
+ __IO uint32_t FMSSTART; /*!< Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
+ __I uint32_t RESERVED1;
+ __I uint32_t FMSW0; /*!< Signature word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ C_CAN0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Controller Area Network C_CAN0 (C_CAN0)
+ */
+
+typedef struct { /*!< C_CAN0 Structure */
+ __IO uint32_t CANCNTL; /*!< CAN control */
+ __IO uint32_t CANSTAT; /*!< Status register */
+ __I uint32_t CANEC; /*!< Error counter */
+ __IO uint32_t CANBT; /*!< Bit timing register */
+ __I uint32_t CANINT; /*!< Interrupt register */
+ __IO uint32_t CANTEST; /*!< Test register */
+ __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */
+
+ union {
+ __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
+ __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
+ };
+ __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */
+ __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */
+ __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */
+ __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */
+ __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */
+ __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */
+ __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */
+ __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */
+ __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */
+ __I uint32_t RESERVED1[13];
+ __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */
+
+ union {
+ __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
+ __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
+ };
+ __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */
+ __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */
+ __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
+ __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
+ __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
+ __IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
+ __IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
+ __IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
+ __IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
+ __I uint32_t RESERVED2[21];
+ __I uint32_t CANTXREQ1; /*!< Transmission request 1 */
+ __I uint32_t CANTXREQ2; /*!< Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t CANND1; /*!< New data 1 */
+ __I uint32_t CANND2; /*!< New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t CANIR1; /*!< Interrupt pending 1 */
+ __I uint32_t CANIR2; /*!< Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t CANMSGV1; /*!< Message valid 1 */
+ __I uint32_t CANMSGV2; /*!< Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CANCLKDIV; /*!< Can clock divider register */
+} LPC_C_CAN0_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I/O pin configuration (IOCON) (IOCON)
+ */
+
+typedef struct { /*!< IOCON Structure */
+ __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
+ __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
+ the I2C-bus SCL function. */
+ __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
+ the I2C-bus SCL function. */
+ __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
+ __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
+ __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+ __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
+} LPC_IOCON_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_GPIO_PORT_BASE 0x1C000000UL
+#define LPC_DMA_BASE 0x1C004000UL
+#define LPC_USB_BASE 0x1C00C000UL
+#define LPC_CRC_BASE 0x1C010000UL
+#define LPC_SCT0_BASE 0x1C018000UL
+#define LPC_SCT1_BASE 0x1C01C000UL
+#define LPC_SCT2_BASE 0x1C020000UL
+#define LPC_SCT3_BASE 0x1C024000UL
+#define LPC_ADC0_BASE 0x40000000UL
+#define LPC_DAC_BASE 0x40004000UL
+#define LPC_ACMP_BASE 0x40008000UL
+#define LPC_INMUX_BASE 0x40014000UL
+#define LPC_RTC_BASE 0x40028000UL
+#define LPC_WWDT_BASE 0x4002C000UL
+#define LPC_SWM_BASE 0x40038000UL
+#define LPC_PMU_BASE 0x4003C000UL
+#define LPC_USART0_BASE 0x40040000UL
+#define LPC_USART1_BASE 0x40044000UL
+#define LPC_SPI0_BASE 0x40048000UL
+#define LPC_SPI1_BASE 0x4004C000UL
+#define LPC_I2C0_BASE 0x40050000UL
+#define LPC_QEI_BASE 0x40058000UL
+#define LPC_SYSCON_BASE 0x40074000UL
+#define LPC_ADC1_BASE 0x40080000UL
+#define LPC_MRT_BASE 0x400A0000UL
+#define LPC_PINT_BASE 0x400A4000UL
+#define LPC_GINT0_BASE 0x400A8000UL
+#define LPC_GINT1_BASE 0x400AC000UL
+#define LPC_RIT_BASE 0x400B4000UL
+#define LPC_SCTIPU_BASE 0x400B8000UL
+#define LPC_FLASHCTRL_BASE 0x400BC000UL
+#define LPC_USART2_BASE 0x400C0000UL
+#define LPC_C_CAN0_BASE 0x400F0000UL
+#define LPC_IOCON_BASE 0x400F8000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
+#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
+#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
+#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
+#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
+#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
+#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
+#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
+#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
+#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
+#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
+#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
+#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
+#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
+#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
+#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
+#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
+#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC15xx */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC15XX_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct
new file mode 100644
index 000000000..1f1b09c5b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
+ ; 36kB(0x9000) - 0x100 = 0x8F00
+ RW_IRAM1 (0x02000000+0x100) (0x9000-0x100) {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s
new file mode 100644
index 000000000..0c9e87ff3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s
@@ -0,0 +1,317 @@
+;/**************************************************************************//**
+; * @file startup_LPC15xx.s
+; * @brief CMSIS Cortex-M3 Core Device Startup File for
+; * NXP LPC15xx Device Series
+; * @version V1.00
+; * @date 17. July 2013
+; *
+; * @note
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x02009000 ; Top of RAM from LPC1549
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt
+ DCD BOD_IRQHandler ; 16+ 1 BOD interrupt
+ DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt
+ DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt
+ DCD DMA_IRQHandler ; 16+ 4 DMA interrupt
+ DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt
+ DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt
+ DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
+ DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
+ DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
+ DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
+ DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
+ DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
+ DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
+ DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
+ DCD RIT_IRQHandler ; 16+15 RIT interrupt
+ DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt
+ DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt
+ DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt
+ DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt
+ DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt
+ DCD UART0_IRQHandler ; 16+21 USART0 interrupt
+ DCD UART1_IRQHandler ; 16+22 USART1 interrupt
+ DCD UART2_IRQHandler ; 16+23 USART2 interrupt
+ DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt
+ DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt
+ DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt
+ DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt
+ DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt
+ DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt
+ DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt
+ DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion.
+ DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion.
+ DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare
+ DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun
+ DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion.
+ DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion.
+ DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare
+ DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun
+ DCD DAC_IRQHandler ; 16+39 DAC interrupt
+ DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0)
+ DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1)
+ DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2)
+ DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3)
+ DCD QEI_IRQHandler ; 16+44 QEI interrupt
+ DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt
+ DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut
+
+; <h> Code Read Protection
+; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
+; <0x12345678=>CRP Level 1
+; <0x87654321=>CRP Level 2
+; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
+; <0x4E697370=>NO ISP (ARE YOU SURE?)
+; </h>
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+ DCD 0xFFFFFFFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+;--- enable SRAM1 and SRAM2 memory
+ LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr
+ LDR R2, [R0] ; read SYSAHBCLKCTRL0
+ ORR R2, R2, #0x18 ; enable SRAM1, SRAM2
+ STR R2, [R0] ; store SYSAHBCLKCTRL0
+;---
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT EE_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT PIN_INT0_IRQHandler [WEAK]
+ EXPORT PIN_INT1_IRQHandler [WEAK]
+ EXPORT PIN_INT2_IRQHandler [WEAK]
+ EXPORT PIN_INT3_IRQHandler [WEAK]
+ EXPORT PIN_INT4_IRQHandler [WEAK]
+ EXPORT PIN_INT5_IRQHandler [WEAK]
+ EXPORT PIN_INT6_IRQHandler [WEAK]
+ EXPORT PIN_INT7_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT SCT0_IRQHandler [WEAK]
+ EXPORT SCT1_IRQHandler [WEAK]
+ EXPORT SCT2_IRQHandler [WEAK]
+ EXPORT SCT3_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT C_CAN0_IRQHandler [WEAK]
+ EXPORT USB_IRQ_IRQHandler [WEAK]
+ EXPORT USB_FIQ_IRQHandler [WEAK]
+ EXPORT USBWAKEUP_IRQHandler [WEAK]
+ EXPORT ADC0_SEQA_IRQHandler [WEAK]
+ EXPORT ADC0_SEQB_IRQHandler [WEAK]
+ EXPORT ADC0_THCMP_IRQHandler [WEAK]
+ EXPORT ADC0_OVR_IRQHandler [WEAK]
+ EXPORT ADC1_SEQA_IRQHandler [WEAK]
+ EXPORT ADC1_SEQB_IRQHandler [WEAK]
+ EXPORT ADC1_THCMP_IRQHandler [WEAK]
+ EXPORT ADC1_OVR_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT CMP3_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT RTC_ALARM_IRQHandler [WEAK]
+ EXPORT RTC_WAKE_IRQHandler [WEAK]
+
+WDT_IRQHandler
+BOD_IRQHandler
+FLASH_IRQHandler
+EE_IRQHandler
+DMA_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+PIN_INT0_IRQHandler
+PIN_INT1_IRQHandler
+PIN_INT2_IRQHandler
+PIN_INT3_IRQHandler
+PIN_INT4_IRQHandler
+PIN_INT5_IRQHandler
+PIN_INT6_IRQHandler
+PIN_INT7_IRQHandler
+RIT_IRQHandler
+SCT0_IRQHandler
+SCT1_IRQHandler
+SCT2_IRQHandler
+SCT3_IRQHandler
+MRT_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+C_CAN0_IRQHandler
+USB_IRQ_IRQHandler
+USB_FIQ_IRQHandler
+USBWAKEUP_IRQHandler
+ADC0_SEQA_IRQHandler
+ADC0_SEQB_IRQHandler
+ADC0_THCMP_IRQHandler
+ADC0_OVR_IRQHandler
+ADC1_SEQA_IRQHandler
+ADC1_SEQB_IRQHandler
+ADC1_THCMP_IRQHandler
+ADC1_OVR_IRQHandler
+DAC_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+CMP3_IRQHandler
+QEI_IRQHandler
+RTC_ALARM_IRQHandler
+RTC_WAKE_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/LPC1549.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/LPC1549.ld
new file mode 100644
index 000000000..7358b9da4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/LPC1549.ld
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1549 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+ Ram0_16 (rwx) : ORIGIN = 0x2000000 + 0x100, LENGTH = (16K - 0x100)
+ Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 16K
+ Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 4K
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > Ram0_16
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > Ram0_16
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > Ram0_16
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > Ram0_16
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(Ram0_16) + LENGTH(Ram0_16);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/startup_LPC15xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/startup_LPC15xx.s
new file mode 100644
index 000000000..814aa4262
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/startup_LPC15xx.s
@@ -0,0 +1,247 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x800
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 0: Windowed watchdog timer */
+ .long BOD_IRQHandler /* 1: Brown-Out Detect */
+ .long FMC_IRQHandler /* 2: Flash controller */
+ .long EEPROM_IRQHandler /* 3: EEPROM controller */
+ .long DMA_IRQHandler /* 4: DMA */
+ .long GINT0_IRQHandler /* 5: GPIO group 0 */
+ .long GINT1_IRQHandler /* 6: GPIO group 1 */
+ .long PIN_INT0_IRQHandler /* 7: PIO INT0 */
+ .long PIN_INT1_IRQHandler /* 8: PIO INT1 */
+ .long PIN_INT2_IRQHandler /* 9: PIO INT2 */
+ .long PIN_INT3_IRQHandler /* 10: PIO INT3 */
+ .long PIN_INT4_IRQHandler /* 11: PIO INT4 */
+ .long PIN_INT5_IRQHandler /* 12: PIO INT5 */
+ .long PIN_INT6_IRQHandler /* 13: PIO INT6 */
+ .long PIN_INT7_IRQHandler /* 14: PIO INT7 */
+ .long RIT_IRQHandler /* 15: Repetitive Interrupt Timer */
+ .long SCT0_IRQHandler /* 16: State configurable timer */
+ .long SCT1_IRQHandler /* 17: State configurable timer */
+ .long SCT2_IRQHandler /* 18: State configurable timer */
+ .long SCT3_IRQHandler /* 19: State configurable timer */
+ .long MRT_IRQHandler /* 20: Multi-Rate Timer */
+ .long UART0_IRQHandler /* 21: UART0 */
+ .long UART1_IRQHandler /* 22: UART1 */
+ .long UART2_IRQHandler /* 23: UART2 */
+ .long I2C0_IRQHandler /* 24: I2C0 controller */
+ .long SPI0_IRQHandler /* 25: SPI0 controller */
+ .long SPI1_IRQHandler /* 26: SPI1 controller */
+ .long CAN_IRQHandler /* 27: C_CAN0 */
+ .long USB_IRQHandler /* 28: USB IRQ */
+ .long USB_FIQHandler /* 29: USB FIQ */
+ .long USBWakeup_IRQHandler /* 30: USB wake-up */
+ .long ADC0A_IRQHandler /* 31: ADC0 sequence A completion */
+ .long ADC0B_IRQHandler /* 32: ADC0 sequence B completion */
+ .long ADC0_THCMP_IRQHandler /* 33: ADC0 threshold compare */
+ .long ADC0_OVR_IRQHandler /* 34: ADC0 overrun */
+ .long ADC1A_IRQHandler /* 35: ADC1 sequence A completion */
+ .long ADC1B_IRQHandler /* 36: ADC1 sequence B completion */
+ .long ADC1_THCMP_IRQHandler /* 37: ADC1 threshold compare */
+ .long ADC1_OVR_IRQHandler /* 38: ADC1 overrun */
+ .long DAC_IRQHandler /* 39: DAC */
+ .long ACMP0_IRQHandler /* 40: Analog Comparator 0 */
+ .long ACMP1_IRQHandler /* 41: Analog Comparator 1 */
+ .long ACMP2_IRQHandler /* 42: Analog Comparator 2 */
+ .long ACMP3_IRQHandler /* 43: Analog Comparator 3 */
+ .long QEI_IRQHandler /* 44: Quadrature Encoder Interface */
+ .long RTC_ALARM_IRQHandler /* 45: RTC alarm */
+ .long RTC_WAKE_IRQHandler /* 46: RTC wake-up */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler FMC_IRQHandler
+ def_irq_default_handler EEPROM_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler GINT0_IRQHandler
+ def_irq_default_handler GINT1_IRQHandler
+ def_irq_default_handler PIN_INT0_IRQHandler
+ def_irq_default_handler PIN_INT1_IRQHandler
+ def_irq_default_handler PIN_INT2_IRQHandler
+ def_irq_default_handler PIN_INT3_IRQHandler
+ def_irq_default_handler PIN_INT4_IRQHandler
+ def_irq_default_handler PIN_INT5_IRQHandler
+ def_irq_default_handler PIN_INT6_IRQHandler
+ def_irq_default_handler PIN_INT7_IRQHandler
+ def_irq_default_handler RIT_IRQHandler
+ def_irq_default_handler SCT0_IRQHandler
+ def_irq_default_handler SCT1_IRQHandler
+ def_irq_default_handler SCT2_IRQHandler
+ def_irq_default_handler SCT3_IRQHandler
+ def_irq_default_handler MRT_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler CAN_IRQHandler
+ def_irq_default_handler USB_IRQHandler
+ def_irq_default_handler USB_FIQHandler
+ def_irq_default_handler USBWakeup_IRQHandler
+ def_irq_default_handler ADC0A_IRQHandler
+ def_irq_default_handler ADC0B_IRQHandler
+ def_irq_default_handler ADC0_THCMP_IRQHandler
+ def_irq_default_handler ADC0_OVR_IRQHandler
+ def_irq_default_handler ADC1A_IRQHandler
+ def_irq_default_handler ADC1B_IRQHandler
+ def_irq_default_handler ADC1_THCMP_IRQHandler
+ def_irq_default_handler ADC1_OVR_IRQHandler
+ def_irq_default_handler DAC_IRQHandler
+ def_irq_default_handler ACMP0_IRQHandler
+ def_irq_default_handler ACMP1_IRQHandler
+ def_irq_default_handler ACMP2_IRQHandler
+ def_irq_default_handler ACMP3_IRQHandler
+ def_irq_default_handler QEI_IRQHandler
+ def_irq_default_handler RTC_ALARM_IRQHandler
+ def_irq_default_handler RTC_WAKE_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/LPC1549.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/LPC1549.ld
new file mode 100644
index 000000000..92fe9deb1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/LPC1549.ld
@@ -0,0 +1,214 @@
+/*Based on following file*/
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2014
+ * Generated linker script file for LPC1549
+ * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
+ * By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Tue Jun 10 00:20:53 JST 2014
+ */
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
+ Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 /* 16K bytes */
+ Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes */
+ Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash256 = 0x0 + 0x40000;
+ __top_Ram0_16 = 0x2000000 + 0x4000;
+ __top_Ram1_16 = 0x2004000 + 0x4000;
+ __top_Ram2_4 = 0x2008000 + 0x1000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > MFlash256
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash256
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash256
+ __exidx_end = .;
+
+ _etext = .;
+
+ /* DATA section for Ram1_16 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$Ram1_16)
+ *(.data.$RAM2*)
+ *(.data.$Ram1_16*)
+ . = ALIGN(4) ;
+ } > Ram1_16 AT>MFlash256
+
+ /* DATA section for Ram2_4 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$Ram2_4)
+ *(.data.$RAM3*)
+ *(.data.$Ram2_4*)
+ . = ALIGN(4) ;
+ } > Ram2_4 AT>MFlash256
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > Ram0_16
+
+ /* Main DATA section (Ram0_16) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > Ram0_16 AT>MFlash256
+
+ /* BSS section for Ram1_16 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$Ram1_16*)
+ . = ALIGN(4) ;
+ } > Ram1_16
+ /* BSS section for Ram2_4 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ *(.bss.$RAM3*)
+ *(.bss.$Ram2_4*)
+ . = ALIGN(4) ;
+ } > Ram2_4
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > Ram0_16
+
+ /* NOINIT section for Ram1_16 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$Ram1_16*)
+ . = ALIGN(4) ;
+ } > Ram1_16
+ /* NOINIT section for Ram2_4 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$Ram2_4*)
+ . = ALIGN(4) ;
+ } > Ram2_4
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > Ram0_16
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_Ram0_16 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp
new file mode 100644
index 000000000..3337ed5bf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp
@@ -0,0 +1,219 @@
+extern "C" {
+
+#include "LPC15xx.h"
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+extern void (* const g_pfnVectors[])(void);
+
+ void ResetISR (void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
+void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0A_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0B_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1A_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1B_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ACMP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ACMP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ACMP2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ACMP3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_ALARM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_WAKE_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC15xx
+ WDT_IRQHandler, // 0 - Windowed watchdog timer
+ BOD_IRQHandler, // 1 - BOD
+ FMC_IRQHandler, // 2 - Flash controller
+ EEPROM_IRQHandler, // 3 - EEPROM controller
+ DMA_IRQHandler, // 4 - DMA
+ GINT0_IRQHandler, // 5 - GINT0
+ GINT1_IRQHandler, // 6 - GINT1
+ PIN_INT0_IRQHandler, // 7 - PIO INT0
+ PIN_INT1_IRQHandler, // 8 - PIO INT1
+ PIN_INT2_IRQHandler, // 9 - PIO INT2
+ PIN_INT3_IRQHandler, // 10 - PIO INT3
+ PIN_INT4_IRQHandler, // 11 - PIO INT4
+ PIN_INT5_IRQHandler, // 12 - PIO INT5
+ PIN_INT6_IRQHandler, // 13 - PIO INT6
+ PIN_INT7_IRQHandler, // 14 - PIO INT7
+ RIT_IRQHandler, // 15 - RIT
+ SCT0_IRQHandler, // 16 - State configurable timer
+ SCT1_IRQHandler, // 17 - State configurable timer
+ SCT2_IRQHandler, // 18 - State configurable timer
+ SCT3_IRQHandler, // 19 - State configurable timer
+ MRT_IRQHandler, // 20 - Multi-Rate Timer
+ UART0_IRQHandler, // 21 - UART0
+ UART1_IRQHandler, // 22 - UART1
+ UART2_IRQHandler, // 23 - UART2
+ I2C0_IRQHandler, // 24 - I2C0 controller
+ SPI0_IRQHandler, // 25 - SPI0 controller
+ SPI1_IRQHandler, // 26 - SPI1 controller
+ CAN_IRQHandler, // 27 - C_CAN0
+ USB_IRQHandler, // 28 - USB IRQ
+ USB_FIQHandler, // 29 - USB FIQ
+ USBWakeup_IRQHandler, // 30 - USB wake-up
+ ADC0A_IRQHandler, // 31 - ADC0 sequence A completion
+ ADC0B_IRQHandler, // 32 - ADC0 sequence B completion
+ ADC0_THCMP_IRQHandler, // 33 - ADC0 threshold compare
+ ADC0_OVR_IRQHandler, // 34 - ADC0 overrun
+ ADC1A_IRQHandler, // 35 - ADC1 sequence A completion
+ ADC1B_IRQHandler, // 36 - ADC1 sequence B completion
+ ADC1_THCMP_IRQHandler, // 37 - ADC1 threshold compare
+ ADC1_OVR_IRQHandler, // 38 - ADC1 overrun
+ DAC_IRQHandler, // 39 - DAC
+ ACMP0_IRQHandler, // 40 - Analog Comparator 0
+ ACMP1_IRQHandler, // 41 - Analog Comparator 1
+ ACMP2_IRQHandler, // 42 - Analog Comparator 2
+ ACMP3_IRQHandler, // 43 - Analog Comparator 3
+ QEI_IRQHandler, // 44 - QEI
+ RTC_ALARM_IRQHandler, // 45 - RTC alarm
+ RTC_WAKE_IRQHandler, // 46 - RTC wake-up
+
+};
+/* End Vector */
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+
+/* Reset entry point*/
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ SectionTableAddr = &__data_section_table;
+
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ SystemInit();
+ if (software_init_hook)
+ software_init_hook();
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {}
+AFTER_VECTORS void HardFault_Handler (void) {}
+AFTER_VECTORS void MemManage_Handler (void) {}
+AFTER_VECTORS void BusFault_Handler (void) {}
+AFTER_VECTORS void UsageFault_Handler(void) {}
+AFTER_VECTORS void SVC_Handler (void) {}
+AFTER_VECTORS void DebugMon_Handler (void) {}
+AFTER_VECTORS void PendSV_Handler (void) {}
+AFTER_VECTORS void SysTick_Handler (void) {}
+AFTER_VECTORS void IntDefaultHandler (void) {}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf
new file mode 100644
index 000000000..c2bf00701
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf
@@ -0,0 +1,37 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x02000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x020000FF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x02000100;
+define symbol __ICFEDIT_region_RAM_end__ = 0x02008FDF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x1200;
+define symbol __ICFEDIT_size_heap__ = 0x2400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s
new file mode 100644
index 000000000..c7f63c0b2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.s
@@ -0,0 +1,274 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2009 IAR Systems. All rights reserved.
+ *
+ * $Revision: 28 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+__vector_table_0x1c
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+
+; External Interrupts
+ DCD WDT_IRQHandler ; Watchdog timer
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD FLASH_IRQHandler ; NVMC Flash Controller
+ DCD EE_IRQHandler ; NVMC EE Controller
+ DCD DMA_IRQHandler ; DMA Controller
+ DCD GINT0_IRQHandler
+ DCD GINT1_IRQHandler ; PIO0 (0:7)
+ DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
+ DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
+ DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
+ DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
+ DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
+ DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
+ DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
+ DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
+ DCD RIT_IRQHandler ; RIT Timer
+ DCD SCT0_IRQHandler ; SCT Timer0
+ DCD SCT1_IRQHandler ; SCT Timer1
+ DCD SCT2_IRQHandler ; SCT Timer2
+ DCD SCT3_IRQHandler ; SCT Timer3
+ DCD MRT_IRQHandler ; MRT timer
+ DCD UART0_IRQHandler ; MIN UART0
+ DCD UART1_IRQHandler ; MIN UART1
+ DCD UART2_IRQHandler ; MIN UART2
+ DCD I2C0_IRQHandler ; BI2C
+ DCD SPI0_IRQHandler ; LSPI0
+ DCD SPI1_IRQHandler ; LSPI1
+ DCD C_CAN0_IRQHandler ; CAN
+ DCD USB_IRQ_IRQHandler ; USB IRQ
+ DCD USB_FIQ_IRQHandler ; USB FIQ
+ DCD USBWakeup_IRQHandler ; USB wake up
+ DCD ADC0_SEQA_IRQHandler ; ADC0 SEQA
+ DCD ADC0_SEQB_IRQHandler ; ADC0 SEQB
+ DCD ADC0_THCMP_IRQHandler ; ADC0 THCMP
+ DCD ADC0_OVR_IRQHandler ; ADC0 OVR
+ DCD ADC1_SEQA_IRQHandler ; ADC1 SEQA
+ DCD ADC1_SEQB_IRQHandler ; ADC1 SEQB
+ DCD ADC1_THCMP_IRQHandler ; ADC1 THCMP
+ DCD ADC1_OVR_IRQHandler ; ADC1 OVR
+ DCD DAC_IRQHandler ; D/A Converter
+ DCD CMP0_IRQHandler ; Comparator 0
+ DCD CMP1_IRQHandler ; Comparator 1
+ DCD CMP2_IRQHandler ; Comparator 2
+ DCD CMP3_IRQHandler ; Comparator 3
+ DCD QEI_IRQHandler ; QEI
+ DCD RTC_ALARM_IRQHandler ; RTC Alarm
+ DCD RTC_WAKE_IRQHandler ; RTC Wake
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK FLASH_IRQHandler
+ PUBWEAK EE_IRQHandler
+ PUBWEAK DMA_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK PIN_INT0_IRQHandler
+ PUBWEAK PIN_INT1_IRQHandler
+ PUBWEAK PIN_INT2_IRQHandler
+ PUBWEAK PIN_INT3_IRQHandler
+ PUBWEAK PIN_INT4_IRQHandler
+ PUBWEAK PIN_INT5_IRQHandler
+ PUBWEAK PIN_INT6_IRQHandler
+ PUBWEAK PIN_INT7_IRQHandler
+ PUBWEAK RIT_IRQHandler
+ PUBWEAK SCT0_IRQHandler
+ PUBWEAK SCT1_IRQHandler
+ PUBWEAK SCT2_IRQHandler
+ PUBWEAK SCT3_IRQHandler
+ PUBWEAK MRT_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK C_CAN0_IRQHandler
+ PUBWEAK USB_IRQ_IRQHandler
+ PUBWEAK USB_FIQ_IRQHandler
+ PUBWEAK USBWakeup_IRQHandler
+ PUBWEAK ADC0_SEQA_IRQHandler
+ PUBWEAK ADC0_SEQB_IRQHandler
+ PUBWEAK ADC0_THCMP_IRQHandler
+ PUBWEAK ADC0_OVR_IRQHandler
+ PUBWEAK ADC1_SEQA_IRQHandler
+ PUBWEAK ADC1_SEQB_IRQHandler
+ PUBWEAK ADC1_THCMP_IRQHandler
+ PUBWEAK ADC1_OVR_IRQHandler
+ PUBWEAK DAC_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK CMP2_IRQHandler
+ PUBWEAK CMP3_IRQHandler
+ PUBWEAK QEI_IRQHandler
+ PUBWEAK RTC_ALARM_IRQHandler
+ PUBWEAK RTC_WAKE_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+WDT_IRQHandler
+BOD_IRQHandler
+FLASH_IRQHandler
+EE_IRQHandler
+DMA_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+PIN_INT0_IRQHandler
+PIN_INT1_IRQHandler
+PIN_INT2_IRQHandler
+PIN_INT3_IRQHandler
+PIN_INT4_IRQHandler
+PIN_INT5_IRQHandler
+PIN_INT6_IRQHandler
+PIN_INT7_IRQHandler
+RIT_IRQHandler
+SCT0_IRQHandler
+SCT1_IRQHandler
+SCT2_IRQHandler
+SCT3_IRQHandler
+MRT_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+C_CAN0_IRQHandler
+USB_IRQ_IRQHandler
+USB_FIQ_IRQHandler
+USBWakeup_IRQHandler
+ADC0_SEQA_IRQHandler
+ADC0_SEQB_IRQHandler
+ADC0_THCMP_IRQHandler
+ADC0_OVR_IRQHandler
+ADC1_SEQA_IRQHandler
+ADC1_SEQB_IRQHandler
+ADC1_THCMP_IRQHandler
+ADC1_OVR_IRQHandler
+DAC_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+CMP3_IRQHandler
+QEI_IRQHandler
+RTC_ALARM_IRQHandler
+RTC_WAKE_IRQHandler
+Default_Handler
+ B Default_Handler
+
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200.
+ - Read Memory command: disabled.
+ - Copy RAM to Flash command: cannot write to Sector 0.
+ - "Go" command: disabled.
+ - Erase sector(s) command: can erase any individual sector except
+ sector 0 only, or can erase all sectors at once.
+ - Compare command: disabled
+CRP2 0x87654321 - Write to RAM command: disabled.
+ - Copy RAM to Flash: disabled.
+ - Erase command: only allows erase of all sectors.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h
new file mode 100644
index 000000000..6846f59da
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC15xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c
new file mode 100644
index 000000000..d1c12690d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h
new file mode 100644
index 000000000..0d94c0364
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
new file mode 100644
index 000000000..86dbd933e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
@@ -0,0 +1,517 @@
+/**************************************************************************//**
+ * @file system_LPC15xx.c
+ * @brief CMSIS Cortex-M3 Device System Source File for
+ * NXP LPC15xx Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC15xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*- SystemCoreClock Configuration -------------------------------------------*/
+// <e0> SystemCoreClock Configuration
+#define CLOCK_SETUP 1
+//
+// <h> System Oscillator Control (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
+//
+// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
+// <0=> IRC Oscillator
+// <1=> Crystal Oscillator (SYSOSC)
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <e> Clock Configuration (Manual)
+#define CLOCK_SETUP_REG 1
+//
+// <o.0..1> Main Clock Source Select A (MAINCLKSELA)
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> WD Oscillator
+#define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
+//
+// <o.0..1> Main Clock Source Select B (MAINCLKSELB)
+// <0=> MAINCLKSELA
+// <1=> System PLL Input
+// <2=> System PLL Output
+// <3=> RTC Oscillator
+#define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
+//
+// <h> System PLL Setting (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..5> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..7> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000
+//
+// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
+// </e>
+//
+// <e> Clock Configuration (via ROM PLL API)
+#define CLOCK_SETUP_API 0
+//
+// <o> PLL API Mode Select
+// <0=> Exact
+// <1=> Less than or equal
+// <2=> Greater than or equal
+// <3=> As close as possible
+#define PLL_API_MODE_Val 0
+//
+// <o> CPU Frequency [Hz] <1000000-72000000:1000>
+#define PLL_API_FREQ_Val 72000000
+// </e>
+//
+// <e> USB Clock Configuration
+#define USB_CLOCK_SETUP 0
+// <h> USB PLL Control (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..5> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.7..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
+//
+// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+//
+// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> USB PLL out
+// <3=> Main clock
+#define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
+//
+// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
+// </e>
+//
+// <e> SCT Clock Configuration
+#define SCT_CLOCK_SETUP 1
+// <h> SCT PLL Control (SCTPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..5> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.7..6> PSEL: Post Divider Selection
+// <i> Post divider ratio P. Division ratio is 2 * P
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SCTPLLCTRL_Val 0x00000005 // Reset value: 0x000
+//
+// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+#define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
+// </e>
+//
+// </e>
+//
+// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
+// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
+//
+#define XTAL_CLK_Val 12000000
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
+#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
+#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
+#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
+#define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+#if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
+ #error "MAINCLKSELA: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
+ #error "MAINCLKSELB: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
+ #error "You must select either manual or API based Clock Configuration!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
+ #error "SCTPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
+ #error "SCTPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
+ #error "XTAL frequency is out of bounds"
+#endif
+
+#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
+ #error "PLL API Mode Select not valid"
+#endif
+
+#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
+ #error "CPU Frequency (API mode) not valid"
+#endif
+
+
+
+/*----------------------------------------------------------------------------
+ Calculate system core clock
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #error "Oops"
+ #endif
+
+ #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+ #if ((MAINCLKSELA_Val & 0x03) == 0)
+ #define __MAINA_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSELA_Val & 0x03) == 1)
+ #define __MAINA_CLOCK (__SYS_OSC_CLK)
+ #elif ((MAINCLKSELA_Val & 0x03) == 2)
+ #define __MAINA_CLOCK (__WDT_OSC_CLK)
+ #else
+ #error "Oops"
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSELB_Val & 0x03) == 0)
+ #define __MAINB_CLOCK (__MAINA_CLOCK)
+ #elif ((MAINCLKSELB_Val & 0x03) == 1)
+ #define __MAINB_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSELB_Val & 0x03) == 2)
+ #define __MAINB_CLOCK (__SYS_PLLCLKOUT)
+ #elif ((MAINCLKSELB_Val & 0x03) == 3)
+ #define __MAINB_CLOCK (__RTC_OSC_CLK)
+ #else
+ #error "Oops"
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
+ #endif /* Clock Setup via Register */
+
+ #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
+ #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
+ #endif /* Clock Setup via PLL API */
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif /* CLOCK_SETUP */
+
+
+
+#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
+#include "power_api.h"
+
+typedef struct _ROM {
+ const unsigned p_dev0;
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const PWRD * pPWRD; /* ROM Power Management API */
+ const unsigned p_dev4;
+ const unsigned p_dev5;
+ const unsigned p_dev6;
+ const unsigned p_dev7;
+} ROM;
+
+/*----------------------------------------------------------------------------
+ PLL API Function
+ *----------------------------------------------------------------------------*/
+static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
+{
+ uint32_t cmd[5], res[5];
+ ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
+
+ cmd[0] = pllInFreq; /* PLL's input freq in KHz */
+ cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
+ cmd[2] = pllMode;
+ cmd[3] = 0; /* no timeout for PLL to lock */
+
+ /* Execute API call */
+ (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
+ if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
+ while(1); /* ... stay here */
+ }
+}
+#endif
+
+
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
+ case 0: /* MAINCLKSELA clock sel */
+ switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Watchdog oscillator */
+ SystemCoreClock = __WDT_OSC_CLK;
+ break;
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 3: /* WDT Oscillator */
+ SystemCoreClock = __WDT_OSC_CLK;
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ */
+void SystemInit (void) {
+#if (CLOCK_SETUP)
+ volatile uint32_t i;
+#endif
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+
+#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
+
+#if (((MAINCLKSELA_Val & 0x03) == 1) )
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+#if (((MAINCLKSELA_Val & 0x03) == 2) )
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+#if ((MAINCLKSELB_Val & 0x03) == 3)
+ LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
+ for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
+#endif
+
+ LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
+
+#if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+ LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif /* Clock Setup via Register */
+
+#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
+// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
+
+ LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
+
+ LPC_SYSCON->SYSAHBCLKDIV = 1;
+
+ setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
+#endif /* Clock Setup via PLL API */
+
+#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
+
+#if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+
+ LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
+#endif
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
+#endif
+
+#if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
+ LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
+
+ LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
+ while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#else /* SCT clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
+#endif
+
+#endif /* Clock Setup */
+
+
+ LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.h
new file mode 100644
index 000000000..022ef472f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.h
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file system_LPC15xx.h
+ * @brief CMSIS Cortex-M3 Device System Header File for
+ * NXP LPC15xx Device Series
+ * @version V1.00
+ * @date 19. July 2013
+ *
+ * @note
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC15xx_H
+#define __SYSTEM_LPC15xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/** @addtogroup LPC15xx_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __SYSTEM_LPC15xx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h
new file mode 100644
index 000000000..377fdf240
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h
@@ -0,0 +1,1035 @@
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /* USB Activity interrupt */
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+#endif // __LPC17xx_H__
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/LPC1768.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/LPC1768.sct
new file mode 100644
index 000000000..56b9495f9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/LPC1768.sct
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ ; 32KB - 0xC8 = 0x7F38
+ RW_IRAM1 0x100000C8 0x7F38 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x2007C000 0x4000 { ; RW data, USB RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.s
new file mode 100644
index 000000000..9646f2f17
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.s
@@ -0,0 +1,243 @@
+;/*****************************************************************************
+; * @file: startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC17xx Device Series
+; * @version: V1.02, modified for mbed
+; * @date: 27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10008000 ; Top of RAM from LPC1768
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+RIT_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/LPC1768.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/LPC1768.sct
new file mode 100644
index 000000000..6fb28c5d3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/LPC1768.sct
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ ; 32KB - 0xC8 = 0x7F38
+ RW_IRAM1 0x100000C8 0x7F38 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/startup_LPC17xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/startup_LPC17xx.s
new file mode 100644
index 000000000..32e2abf7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/startup_LPC17xx.s
@@ -0,0 +1,226 @@
+;/*****************************************************************************
+; * @file: startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC17xx Device Series
+; * @version: V1.02, modified for mbed
+; * @date: 27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp EQU 0x10008000 ; Top of RAM from LPC1768
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+RIT_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/LPC1768.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/LPC1768.ld
new file mode 100644
index 000000000..ae8c58fda
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/LPC1768.ld
@@ -0,0 +1,172 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
+
+ USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > USB_RAM
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > ETH_RAM
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s
new file mode 100644
index 000000000..4a8e973a3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s
@@ -0,0 +1,223 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x800
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 16: Watchdog Timer */
+ .long TIMER0_IRQHandler /* 17: Timer0 */
+ .long TIMER1_IRQHandler /* 18: Timer1 */
+ .long TIMER2_IRQHandler /* 19: Timer2 */
+ .long TIMER3_IRQHandler /* 20: Timer3 */
+ .long UART0_IRQHandler /* 21: UART0 */
+ .long UART1_IRQHandler /* 22: UART1 */
+ .long UART2_IRQHandler /* 23: UART2 */
+ .long UART3_IRQHandler /* 24: UART3 */
+ .long PWM1_IRQHandler /* 25: PWM1 */
+ .long I2C0_IRQHandler /* 26: I2C0 */
+ .long I2C1_IRQHandler /* 27: I2C1 */
+ .long I2C2_IRQHandler /* 28: I2C2 */
+ .long SPI_IRQHandler /* 29: SPI */
+ .long SSP0_IRQHandler /* 30: SSP0 */
+ .long SSP1_IRQHandler /* 31: SSP1 */
+ .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
+ .long RTC_IRQHandler /* 33: Real Time Clock */
+ .long EINT0_IRQHandler /* 34: External Interrupt 0 */
+ .long EINT1_IRQHandler /* 35: External Interrupt 1 */
+ .long EINT2_IRQHandler /* 36: External Interrupt 2 */
+ .long EINT3_IRQHandler /* 37: External Interrupt 3 */
+ .long ADC_IRQHandler /* 38: A/D Converter */
+ .long BOD_IRQHandler /* 39: Brown-Out Detect */
+ .long USB_IRQHandler /* 40: USB */
+ .long CAN_IRQHandler /* 41: CAN */
+ .long DMA_IRQHandler /* 42: General Purpose DMA */
+ .long I2S_IRQHandler /* 43: I2S */
+ .long ENET_IRQHandler /* 44: Ethernet */
+ .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
+ .long MCPWM_IRQHandler /* 46: Motor Control PWM */
+ .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
+ .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
+ .long USBActivity_IRQHandler /* 49: USB Activity */
+ .long CANActivity_IRQHandler /* 50: CAN Activity */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler TIMER0_IRQHandler
+ def_irq_default_handler TIMER1_IRQHandler
+ def_irq_default_handler TIMER2_IRQHandler
+ def_irq_default_handler TIMER3_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler UART3_IRQHandler
+ def_irq_default_handler PWM1_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler SPI_IRQHandler
+ def_irq_default_handler SSP0_IRQHandler
+ def_irq_default_handler SSP1_IRQHandler
+ def_irq_default_handler PLL0_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler EINT0_IRQHandler
+ def_irq_default_handler EINT1_IRQHandler
+ def_irq_default_handler EINT2_IRQHandler
+ def_irq_default_handler EINT3_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler USB_IRQHandler
+ def_irq_default_handler CAN_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler I2S_IRQHandler
+ def_irq_default_handler ENET_IRQHandler
+ def_irq_default_handler RIT_IRQHandler
+ def_irq_default_handler MCPWM_IRQHandler
+ def_irq_default_handler QEI_IRQHandler
+ def_irq_default_handler PLL1_IRQHandler
+ def_irq_default_handler USBActivity_IRQHandler
+ def_irq_default_handler CANActivity_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld
new file mode 100644
index 000000000..e67c27368
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld
@@ -0,0 +1,154 @@
+/* mbed - LPC1768 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc32
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc32 AT>MFlash512
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp
new file mode 100644
index 000000000..4da3084c3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp
@@ -0,0 +1,183 @@
+extern "C" {
+
+#include "LPC17xx.h"
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+extern void (* const g_pfnVectors[])(void);
+
+ void ResetISR (void);
+WEAK void NMI_Handler (void);
+WEAK void HardFault_Handler (void);
+WEAK void MemManage_Handler (void);
+WEAK void BusFault_Handler (void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler (void);
+WEAK void DebugMon_Handler (void);
+WEAK void PendSV_Handler (void);
+WEAK void SysTick_Handler (void);
+WEAK void IntDefaultHandler (void);
+
+void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler (void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler (void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler (void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler (void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler (void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler (void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler (void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler (void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler (void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ &_vStackTop, ResetISR, NMI_Handler,
+ HardFault_Handler,
+ MemManage_Handler,
+ BusFault_Handler,
+ UsageFault_Handler,
+ 0,
+ 0,
+ 0,
+ 0,
+ SVC_Handler,
+ DebugMon_Handler,
+ 0,
+ PendSV_Handler,
+ SysTick_Handler,
+ WDT_IRQHandler,
+ TIMER0_IRQHandler,
+ TIMER1_IRQHandler,
+ TIMER2_IRQHandler,
+ TIMER3_IRQHandler,
+ UART0_IRQHandler,
+ UART1_IRQHandler,
+ UART2_IRQHandler,
+ UART3_IRQHandler,
+ PWM1_IRQHandler,
+ I2C0_IRQHandler,
+ I2C1_IRQHandler,
+ I2C2_IRQHandler,
+ SPI_IRQHandler,
+ SSP0_IRQHandler,
+ SSP1_IRQHandler,
+ PLL0_IRQHandler,
+ RTC_IRQHandler,
+ EINT0_IRQHandler,
+ EINT1_IRQHandler,
+ EINT2_IRQHandler,
+ EINT3_IRQHandler,
+ ADC_IRQHandler,
+ BOD_IRQHandler,
+ USB_IRQHandler,
+ CAN_IRQHandler,
+ DMA_IRQHandler,
+ I2S_IRQHandler,
+ ENET_IRQHandler,
+ RIT_IRQHandler,
+ MCPWM_IRQHandler,
+ QEI_IRQHandler,
+ PLL1_IRQHandler,
+ USBActivity_IRQHandler,
+ CANActivity_IRQHandler,
+};
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+AFTER_VECTORS void ResetISR(void) {
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ SectionTableAddr = &__data_section_table;
+
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ SystemInit();
+ if (software_init_hook) // give control to the RTOS
+ software_init_hook(); // this will also call __libc_init_array
+ else {
+ __libc_init_array();
+ main();
+ }
+ while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler (void) {}
+AFTER_VECTORS void HardFault_Handler (void) {}
+AFTER_VECTORS void MemManage_Handler (void) {}
+AFTER_VECTORS void BusFault_Handler (void) {}
+AFTER_VECTORS void UsageFault_Handler(void) {}
+AFTER_VECTORS void SVC_Handler (void) {}
+AFTER_VECTORS void DebugMon_Handler (void) {}
+AFTER_VECTORS void PendSV_Handler (void) {}
+AFTER_VECTORS void SysTick_Handler (void) {}
+AFTER_VECTORS void IntDefaultHandler (void) {}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/LPC1768.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/LPC1768.ld
new file mode 100644
index 000000000..e88d34de6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/LPC1768.ld
@@ -0,0 +1,212 @@
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ram LENGTH: 32KB - 0xC8 = 0x7F38
+*/
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+
+ ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
+
+ ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* This used for USB RAM section */
+ .usb_ram (NOLOAD):
+ {
+ *.o (USB_RAM)
+ } > ram2
+ .heap (NOLOAD) :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+ {
+ *(.stack)
+ _estack = .;
+ PROVIDE(estack = .);
+ } >ram
+
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/startup_LPC17xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/startup_LPC17xx.s
new file mode 100644
index 000000000..564e6d774
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/startup_LPC17xx.s
@@ -0,0 +1,204 @@
+ .equ Stack_Size, 0x1024
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+ .equ Heap_Size, 0x8000
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack
+ .long __cs3_reset
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long MemManage_Handler
+ .long BusFault_Handler
+ .long UsageFault_Handler
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVC_Handler
+ .long DebugMon_Handler
+ .long 0
+ .long PendSV_Handler
+ .long SysTick_Handler
+
+ .long WDT_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long TIMER3_IRQHandler
+ .long UART0_IRQHandler
+ .long UART1_IRQHandler
+ .long UART2_IRQHandler
+ .long UART3_IRQHandler
+ .long PWM1_IRQHandler
+ .long I2C0_IRQHandler
+ .long I2C1_IRQHandler
+ .long I2C2_IRQHandler
+ .long SPI_IRQHandler
+ .long SSP0_IRQHandler
+ .long SSP1_IRQHandler
+ .long PLL0_IRQHandler
+ .long RTC_IRQHandler
+ .long EINT0_IRQHandler
+ .long EINT1_IRQHandler
+ .long EINT2_IRQHandler
+ .long EINT3_IRQHandler
+ .long ADC_IRQHandler
+ .long BOD_IRQHandler
+ .long USB_IRQHandler
+ .long CAN_IRQHandler
+ .long DMA_IRQHandler
+ .long I2S_IRQHandler
+ .long ENET_IRQHandler
+ .long RIT_IRQHandler
+ .long MCPWM_IRQHandler
+ .long QEI_IRQHandler
+ .long PLL1_IRQHandler
+ .long USBActivity_IRQHandler
+ .long CANActivity_IRQHandler
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+ .thumb
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__cs3_start_c
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+MemManage_Handler:
+ B .
+ .size MemManage_Handler, . - MemManage_Handler
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ B .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ WDT_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ UART0_IRQHandler
+ IRQ UART1_IRQHandler
+ IRQ UART2_IRQHandler
+ IRQ UART3_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ I2C0_IRQHandler
+ IRQ I2C1_IRQHandler
+ IRQ I2C2_IRQHandler
+ IRQ SPI_IRQHandler
+ IRQ SSP0_IRQHandler
+ IRQ SSP1_IRQHandler
+ IRQ PLL0_IRQHandler
+ IRQ RTC_IRQHandler
+ IRQ EINT0_IRQHandler
+ IRQ EINT1_IRQHandler
+ IRQ EINT2_IRQHandler
+ IRQ EINT3_IRQHandler
+ IRQ ADC_IRQHandler
+ IRQ BOD_IRQHandler
+ IRQ USB_IRQHandler
+ IRQ CAN_IRQHandler
+ IRQ DMA_IRQHandler
+ IRQ I2S_IRQHandler
+ IRQ ENET_IRQHandler
+ IRQ RIT_IRQHandler
+ IRQ MCPWM_IRQHandler
+ IRQ QEI_IRQHandler
+ IRQ PLL1_IRQHandler
+ IRQ USBActivity_IRQHandler
+ IRQ CANActivity_IRQHandler
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp
new file mode 100644
index 000000000..9eb0108e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp
@@ -0,0 +1,80 @@
+#include "cmsis.h"
+#include <sys/types.h>
+#include <errno.h>
+
+extern "C" {
+
+struct SCS3Regions {
+ unsigned long Dummy;
+ unsigned long* InitRam;
+ unsigned long* StartRam;
+ unsigned long InitSizeRam;
+ unsigned long ZeroSizeRam;
+};
+
+extern unsigned long __cs3_regions;
+extern unsigned long __cs3_heap_start;
+
+int main(void);
+void __libc_init_array(void);
+void exit(int ErrorCode);
+
+static void *heap_pointer = NULL;
+
+void __cs3_start_c(void) {
+ static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
+ unsigned long* pulDest;
+ unsigned long* pulSrc;
+ unsigned long ByteCount;
+ unsigned long i;
+
+ pulSrc = pCS3Regions->InitRam;
+ pulDest = pCS3Regions->StartRam;
+ ByteCount = pCS3Regions->InitSizeRam;
+ if (pulSrc != pulDest) {
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = *(pulSrc++);
+ }
+ } else {
+ pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
+ }
+
+ ByteCount = pCS3Regions->ZeroSizeRam;
+ for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+ *(pulDest++) = 0;
+ }
+
+ heap_pointer = &__cs3_heap_start;
+ __libc_init_array();
+
+ exit(main());
+}
+
+int _kill(int pid, int sig) {
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit(int status) {
+ exit(status);
+}
+
+int _getpid(void) {
+ return 1;
+}
+
+void *_sbrk(unsigned int incr) {
+ void *mem;
+
+ unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
+ if (next > __get_MSP()) {
+ mem = NULL;
+ } else {
+ mem = (void *)heap_pointer;
+ }
+ heap_pointer = (void *)next;
+
+ return mem;
+}
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf
new file mode 100644
index 000000000..44594b381
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf
@@ -0,0 +1,45 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000C7;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C8;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
+
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __RAM1_start__ = 0x2007C000;
+define symbol __RAM1_end__ = 0x20083FFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+
+place in CRP_region { section .crp };
+place in RAM1_region { section USB_RAM };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/startup_LPC17xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/startup_LPC17xx.s
new file mode 100644
index 000000000..4ffb5331a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/startup_LPC17xx.s
@@ -0,0 +1,375 @@
+;/*****************************************************************************
+; * @file: startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC17xx Device Series
+; * @version: V1.03
+; * @date: 09. February 2010
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPI_IRQHandler ; 29: SPI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+ DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
+ DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+ B TIMER0_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK PWM1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PWM1_IRQHandler
+ B PWM1_IRQHandler
+
+ PUBWEAK I2C0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+ B I2C0_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ PUBWEAK SSP0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+ B SSP0_IRQHandler
+
+ PUBWEAK SSP1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+ B SSP1_IRQHandler
+
+ PUBWEAK PLL0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PLL0_IRQHandler
+ B PLL0_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK EINT0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT0_IRQHandler
+ B EINT0_IRQHandler
+
+ PUBWEAK EINT1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT1_IRQHandler
+ B EINT1_IRQHandler
+
+ PUBWEAK EINT2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT2_IRQHandler
+ B EINT2_IRQHandler
+
+ PUBWEAK EINT3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EINT3_IRQHandler
+ B EINT3_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK BOD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+BOD_IRQHandler
+ B BOD_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK DMA_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+ B DMA_IRQHandler
+
+ PUBWEAK I2S_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2S_IRQHandler
+ B I2S_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK RIT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RIT_IRQHandler
+ B RIT_IRQHandler
+
+ PUBWEAK MCPWM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+ B MCPWM_IRQHandler
+
+ PUBWEAK QEI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+ B QEI_IRQHandler
+
+ PUBWEAK PLL1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PLL1_IRQHandler
+ B PLL1_IRQHandler
+
+ PUBWEAK USBActivity_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBActivity_IRQHandler
+ B USBActivity_IRQHandler
+
+ PUBWEAK CANActivity_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CANActivity_IRQHandler
+ B CANActivity_IRQHandler
+
+#ifndef SRAM
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200.
+ - Read Memory command: disabled.
+ - Copy RAM to Flash command: cannot write to Sector 0.
+ - "Go" command: disabled.
+ - Erase sector(s) command: can erase any individual sector except
+ sector 0 only, or can erase all sectors at once.
+ - Compare command: disabled
+CRP2 0x87654321 - Write to RAM command: disabled.
+ - Copy RAM to Flash: disabled.
+ - Erase command: only allows erase of all sectors.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+#endif
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h
new file mode 100644
index 000000000..2e51a087d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC17xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c
new file mode 100644
index 000000000..1c2578468
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR < NVIC_RAM_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h
new file mode 100644
index 000000000..9b81fd25b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 33)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c
new file mode 100644
index 000000000..c86e32ca0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c
@@ -0,0 +1,584 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.c
+ * @brief CMSIS Cortex-M3 Device System Source File for
+ * NXP LPC17xx Device Series
+ * @version V1.11
+ * @date 21. June 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 25 MHz
+// <e1.5> OSCEN: Main Oscillator Enable
+// </e>
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0..1> CLKSRC: PLL Clock Source Selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// <2=> RTC oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> F_cco0 = (2 * M * F_in) / N
+// <i> F_in must be in the range of 32 kHz to 50 MHz
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+// <o4.0..14> MSEL: PLL Multiplier Selection
+// <6-32768><#-1>
+// <i> M Value
+// <o4.16..23> NSEL: PLL Divider Selection
+// <1-256><#-1>
+// <i> N Value
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (USB PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+// <i> F_cco1 = F_osc * M * 2 * P
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <1-32><#-1>
+// <i> M Value (for USB maximum value is 4)
+// <o6.5..6> PSEL: PLL Divider Selection
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <i> P Value
+// </h>
+// </e>
+//
+// <h> CPU Clock Configuration Register (CCLKCFG)
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
+// <1-256><#-1>
+// </h>
+//
+// <h> USB Clock Configuration Register (USBCLKCFG)
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
+// <0-15>
+// <i> Divide is USBSEL + 1
+// </h>
+//
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// </h>
+//
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.6> PCPWM1: PWM 1 power/clock enable
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable
+// <o11.8> PCSPI: SPI interface power/clock enable
+// <o11.9> PCRTC: RTC power/clock enable
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable
+// <o11.12> PCAD: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: GPIOs power/clock enable
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
+// <o11.17> PCMC: Motor control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.29> PCGPDMA: GP DMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
+// <0=> CPU clock
+// <1=> Main oscillator
+// <2=> Internal RC oscillator
+// <3=> USB clock
+// <4=> RTC oscillator
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable control
+// </h>
+//
+// </e>
+*/
+
+
+
+/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
+ @{
+ */
+
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+
+#ifdef MCB1700
+# define PLL0CFG_Val 0x00050063
+# define PLL1_SETUP 1
+# define PLL1CFG_Val 0x00000023
+# define CCLKCFG_Val 0x00000003
+# define USBCLKCFG_Val 0x00000000
+#else
+# define PLL0CFG_Val 0x0000000B
+# define PLL1_SETUP 0
+# define PLL1CFG_Val 0x00000000
+# define CCLKCFG_Val 0x00000002
+# define USBCLKCFG_Val 0x00000005
+#endif
+
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x0000303A
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (PLL0_SETUP) /* if PLL0 is used */
+ #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
+ #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
+ #endif
+#endif
+
+#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
+ #error "CCLKCFG: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+ #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
+ #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
+ #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
+ #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+
+/* F_cco0 = (2 * M * F_in) / N */
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+ #endif
+ #else
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #endif
+ #endif
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
+ @{
+ */
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
+ @{
+ */
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = (IRC_OSC *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = (OSC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = (RTC_CLK *
+ ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+ /* Periphral clock must be selected before PLL0 enabling and connecting
+ * - according errata.lpc1768-16.March.2010 -
+ */
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+
+#if (PLL0_SETUP)
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+
+ LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
+#else
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h
new file mode 100644
index 000000000..c8e522f0b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h
@@ -0,0 +1,60 @@
+/******************************************************************************
+ * @file: system_LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version: V1.02
+ * @date: 27. July 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h
new file mode 100644
index 000000000..9adaac488
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h
@@ -0,0 +1,864 @@
+/* mbed Microcontroller Library - LPC23xx CMSIS-like structs
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
+ */
+
+#ifndef __LPC23xx_H
+#define __LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** LPC23xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+
+ TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
+ UART0_IRQn = 6, /*!< UART0 Interrupt */
+ UART1_IRQn = 7, /*!< UART1 Interrupt */
+ PWM1_IRQn = 8, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 9, /*!< I2C0 Interrupt */
+ SPI_IRQn = 10, /*!< SPI Interrupt */
+ SSP0_IRQn = 10, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 11, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 18, /*!< A/D Converter Interrupt */
+ I2C1_IRQn = 19, /*!< I2C1 Interrupt */
+ BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
+ ENET_IRQn = 21, /*!< Ethernet Interrupt */
+ USB_IRQn = 22, /*!< USB Interrupt */
+ CAN_IRQn = 23, /*!< CAN Interrupt */
+ MIC_IRQn = 24, /*!< Multimedia Interface Controler */
+ DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
+ TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
+ UART2_IRQn = 28, /*!< UART2 Interrupt */
+ UART3_IRQn = 29, /*!< UART3 Interrupt */
+ I2C2_IRQn = 30, /*!< I2C2 Interrupt */
+ I2S_IRQn = 31, /*!< I2S Interrupt */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the ARM7 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include <core_arm7.h>
+#include "system_LPC23xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+/*------------- Vector Interupt Controler (VIC) ------------------------------*/
+typedef struct
+{
+ __I uint32_t IRQStatus;
+ __I uint32_t FIQStatus;
+ __I uint32_t RawIntr;
+ __IO uint32_t IntSelect;
+ __IO uint32_t IntEnable;
+ __O uint32_t IntEnClr;
+ __IO uint32_t SoftInt;
+ __O uint32_t SoftIntClr;
+ __IO uint32_t Protection;
+ __IO uint32_t SWPriorityMask;
+ __IO uint32_t RESERVED0[54];
+ __IO uint32_t VectAddr[32];
+ __IO uint32_t RESERVED1[32];
+ __IO uint32_t VectPriority[32];
+ __IO uint32_t RESERVED2[800];
+ __IO uint32_t Address;
+} LPC_VIC_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t MAMCR;
+ __IO uint32_t MAMTIM;
+ uint32_t RESERVED0[14];
+ __IO uint32_t MEMMAP;
+ uint32_t RESERVED1[15];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED2[12];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ uint32_t RESERVED4[12];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ __IO uint32_t INTWAKE;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ __IO uint32_t CSPR;
+ __IO uint32_t AHBCFG1;
+ __IO uint32_t AHBCFG2;
+ uint32_t RESERVED7[4];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ uint32_t RESERVED9;
+// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t FIODIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t FIOMASK;
+ __IO uint32_t FIOPIN;
+ __IO uint32_t FIOSET;
+ __O uint32_t FIOCLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __IO uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED7[3];
+ __IO uint8_t ADRMATCH;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __IO uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __I uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[3];
+ __IO uint8_t CTC;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CCR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED3[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED4[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED5[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED6[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED8[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED9[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED10;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED11[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED12;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t WAKEUPDIS;
+ uint8_t RESERVED13[3];
+ __IO uint8_t PWRCTRL;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED18[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED19[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED20;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED21[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED22;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Multimedia Card Interface (MCI) ------------------------------*/
+typedef struct
+{
+ __IO uint32_t MCIPower; /* Power control */
+ __IO uint32_t MCIClock; /* Clock control */
+ __IO uint32_t MCIArgument;
+ __IO uint32_t MMCCommand;
+ __I uint32_t MCIRespCmd;
+ __I uint32_t MCIResponse0;
+ __I uint32_t MCIResponse1;
+ __I uint32_t MCIResponse2;
+ __I uint32_t MCIResponse3;
+ __IO uint32_t MCIDataTimer;
+ __IO uint32_t MCIDataLength;
+ __IO uint32_t MCIDataCtrl;
+ __I uint32_t MCIDataCnt;
+} LPC_MCI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_WO;
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[823];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+
+/* AHB Peripheral # 0 */
+
+/*
+#define FLASH_BASE (0x00000000UL)
+#define RAM_BASE (0x10000000UL)
+#define GPIO_BASE (0x2009C000UL)
+#define APB0_BASE (0x40000000UL)
+#define APB1_BASE (0x40080000UL)
+#define AHB_BASE (0x50000000UL)
+#define CM3_BASE (0xE0000000UL)
+*/
+
+// TODO - #define VIC_BASE_ADDR 0xFFFFF000
+
+#define LPC_WDT_BASE (0xE0000000)
+#define LPC_TIM0_BASE (0xE0004000)
+#define LPC_TIM1_BASE (0xE0008000)
+#define LPC_UART0_BASE (0xE000C000)
+#define LPC_UART1_BASE (0xE0010000)
+#define LPC_PWM1_BASE (0xE0018000)
+#define LPC_I2C0_BASE (0xE001C000)
+#define LPC_SPI_BASE (0xE0020000)
+#define LPC_RTC_BASE (0xE0024000)
+#define LPC_GPIOINT_BASE (0xE0028080)
+#define LPC_PINCON_BASE (0xE002C000)
+#define LPC_SSP1_BASE (0xE0030000)
+#define LPC_ADC_BASE (0xE0034000)
+#define LPC_CANAF_RAM_BASE (0xE0038000)
+#define LPC_CANAF_BASE (0xE003C000)
+#define LPC_CANCR_BASE (0xE0040000)
+#define LPC_CAN1_BASE (0xE0044000)
+#define LPC_CAN2_BASE (0xE0048000)
+#define LPC_I2C1_BASE (0xE005C000)
+#define LPC_SSP0_BASE (0xE0068000)
+#define LPC_DAC_BASE (0xE006C000)
+#define LPC_TIM2_BASE (0xE0070000)
+#define LPC_TIM3_BASE (0xE0074000)
+#define LPC_UART2_BASE (0xE0078000)
+#define LPC_UART3_BASE (0xE007C000)
+#define LPC_I2C2_BASE (0xE0080000)
+#define LPC_I2S_BASE (0xE0088000)
+#define LPC_MCI_BASE (0xE008C000)
+#define LPC_SC_BASE (0xE01FC000)
+#define LPC_EMAC_BASE (0xFFE00000)
+#define LPC_GPDMA_BASE (0xFFE04000)
+#define LPC_GPDMACH0_BASE (0xFFE04100)
+#define LPC_GPDMACH1_BASE (0xFFE04120)
+#define LPC_USB_BASE (0xFFE0C000)
+#define LPC_VIC_BASE (0xFFFFF000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (0x3FFFC000)
+#define LPC_GPIO1_BASE (0x3FFFC020)
+#define LPC_GPIO2_BASE (0x3FFFC040)
+#define LPC_GPIO3_BASE (0x3FFFC060)
+#define LPC_GPIO4_BASE (0x3FFFC080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
+#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
+#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
+#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
+#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
+#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
+#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
+#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
+#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
+#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
+#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
+#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
+#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
+#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
+#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
+#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
+#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
+#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
+#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
+#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
+#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
+#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
+#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
+#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
+#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
+#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
+#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
+#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
+#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
+#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
+#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
+#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
+#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
+#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
+#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
+#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
+#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
+#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif // __LPC23xx_H
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/LPC2368.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/LPC2368.sct
new file mode 100644
index 000000000..e2fdfdc09
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/LPC2368.sct
@@ -0,0 +1,24 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x40000120 0x7EE0 { ; RW data, inc space for realmonitor
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x7FD00000 0x2000 { ; RW data, USB RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x7FE00000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0xE0038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+ RW_IRAM5 0xE0084000 0x0800 { ; RW data, RTC RAM
+ .ANY (RTCRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_functions.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_functions.s
new file mode 100644
index 000000000..462eb73c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_functions.s
@@ -0,0 +1,248 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+
+#line 1 "vector_functions.s"
+;
+;
+;
+
+#line 1 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 6 "vector_functions.s"
+
+
+ AREA VECFUNCS, CODE, READONLY
+ ARM
+ PRESERVE8
+
+
+
+
+
+ EXPORT __mbed_fiq [WEAK]
+ EXPORT __mbed_undef [WEAK]
+ EXPORT __mbed_prefetch_abort [WEAK]
+ EXPORT __mbed_data_abort [WEAK]
+ EXPORT __mbed_irq [WEAK]
+ EXPORT __mbed_swi [WEAK]
+ EXPORT __mbed_dcc_irq [WEAK]
+ EXPORT __mbed_reset [WEAK]
+ IMPORT __mbed_init_realmonitor
+
+;
+;
+__mbed_fiq
+ B __mbed_fiq
+
+;
+;
+__mbed_undef
+ LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort
+ LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort
+ LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq
+ ;
+ MSR CPSR_c, #0x1F:OR:0x80:OR:0x40
+
+ ;
+ STMDB sp!, {r0-r3,r12,lr}
+
+ ;
+ MOV r0, #0xFFFFFF00
+ LDR r0, [r0]
+
+ ;
+ MOV lr, pc
+ BX r0
+
+ ;
+ MOV r0, #0xFFFFFF00
+ STR r0, [r0] ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+
+ ;
+ SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi
+ ;
+ ;
+ STMFD sp!, {a4, r4, ip, lr}
+
+ ;
+ LDR r4, =0x40000040
+
+ ;
+ ;
+ LDR a4, =0x00940000
+ LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq
+
+ ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+
+ ;
+
+ ;
+ SUB lr, lr, #4 ;
+ STMFD sp!, {ip,lr} ;
+
+ ;
+ LDR LR, =0xfffff000
+ STR LR, [LR, #0xf00]
+
+ ;
+ ;
+ ;
+ ;
+ LDR PC, =0x7fffffe0
+
+;
+; __mbed_reset is called after reset
+; we setup the stacks and realmonitor, then call Reset_Handler like on M3
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ MOV LR, PC
+ BX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+__mbed_reset
+
+ ;
+
+ LDR R0, =(0x40000000 + 0x8000)
+
+ ;
+ MSR CPSR_c, #0x1B:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x17:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x11:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000000
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x13:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x10
+ MOV SP, R0
+
+ ;
+ LDR R0, =__mbed_init_realmonitor
+ MOV LR, PC
+ BX R0
+
+ ;
+ LDR R0, =Reset_Handler
+ BX R0
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_table.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_table.s
new file mode 100644
index 000000000..2fca32472
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_table.s
@@ -0,0 +1,99 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+
+#line 1 "vector_table.s"
+;
+
+
+
+
+#line 1 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 7 "vector_table.s"
+
+;
+
+
+ AREA RESET, CODE, READONLY
+ ARM
+; ENTRY
+ PRESERVE8
+
+
+
+
+
+; EXPORT __main
+ IMPORT __mbed_reset
+ IMPORT __mbed_undef
+ IMPORT __mbed_swi
+ IMPORT __mbed_prefetch_abort
+ IMPORT __mbed_data_abort
+ IMPORT __mbed_irq
+ IMPORT __mbed_fiq
+
+;
+
+
+;__main
+ LDR PC, =__mbed_reset
+ LDR PC, =__mbed_undef
+ LDR PC, =__mbed_swi
+ LDR PC, =__mbed_prefetch_abort
+ LDR PC, =__mbed_data_abort
+ NOP ;
+ LDR PC, =__mbed_irq
+ LDR PC, =__mbed_fiq
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/LPC2368.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/LPC2368.sct
new file mode 100644
index 000000000..e2fdfdc09
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/LPC2368.sct
@@ -0,0 +1,24 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x40000120 0x7EE0 { ; RW data, inc space for realmonitor
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x7FD00000 0x2000 { ; RW data, USB RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x7FE00000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0xE0038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+ RW_IRAM5 0xE0084000 0x0800 { ; RW data, RTC RAM
+ .ANY (RTCRAM)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_functions.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_functions.s
new file mode 100644
index 000000000..462eb73c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_functions.s
@@ -0,0 +1,248 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+
+#line 1 "vector_functions.s"
+;
+;
+;
+
+#line 1 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 6 "vector_functions.s"
+
+
+ AREA VECFUNCS, CODE, READONLY
+ ARM
+ PRESERVE8
+
+
+
+
+
+ EXPORT __mbed_fiq [WEAK]
+ EXPORT __mbed_undef [WEAK]
+ EXPORT __mbed_prefetch_abort [WEAK]
+ EXPORT __mbed_data_abort [WEAK]
+ EXPORT __mbed_irq [WEAK]
+ EXPORT __mbed_swi [WEAK]
+ EXPORT __mbed_dcc_irq [WEAK]
+ EXPORT __mbed_reset [WEAK]
+ IMPORT __mbed_init_realmonitor
+
+;
+;
+__mbed_fiq
+ B __mbed_fiq
+
+;
+;
+__mbed_undef
+ LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort
+ LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort
+ LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq
+ ;
+ MSR CPSR_c, #0x1F:OR:0x80:OR:0x40
+
+ ;
+ STMDB sp!, {r0-r3,r12,lr}
+
+ ;
+ MOV r0, #0xFFFFFF00
+ LDR r0, [r0]
+
+ ;
+ MOV lr, pc
+ BX r0
+
+ ;
+ MOV r0, #0xFFFFFF00
+ STR r0, [r0] ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+
+ ;
+ SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi
+ ;
+ ;
+ STMFD sp!, {a4, r4, ip, lr}
+
+ ;
+ LDR r4, =0x40000040
+
+ ;
+ ;
+ LDR a4, =0x00940000
+ LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq
+
+ ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+
+ ;
+
+ ;
+ SUB lr, lr, #4 ;
+ STMFD sp!, {ip,lr} ;
+
+ ;
+ LDR LR, =0xfffff000
+ STR LR, [LR, #0xf00]
+
+ ;
+ ;
+ ;
+ ;
+ LDR PC, =0x7fffffe0
+
+;
+; __mbed_reset is called after reset
+; we setup the stacks and realmonitor, then call Reset_Handler like on M3
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ MOV LR, PC
+ BX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+__mbed_reset
+
+ ;
+
+ LDR R0, =(0x40000000 + 0x8000)
+
+ ;
+ MSR CPSR_c, #0x1B:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x17:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x11:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000000
+
+ ;
+ MSR CPSR_c, #0x12:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x13:OR:0x80:OR:0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x10
+ MOV SP, R0
+
+ ;
+ LDR R0, =__mbed_init_realmonitor
+ MOV LR, PC
+ BX R0
+
+ ;
+ LDR R0, =Reset_Handler
+ BX R0
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_table.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_table.s
new file mode 100644
index 000000000..2fca32472
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_table.s
@@ -0,0 +1,99 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+
+#line 1 "vector_table.s"
+;
+
+
+
+
+#line 1 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 7 "vector_table.s"
+
+;
+
+
+ AREA RESET, CODE, READONLY
+ ARM
+; ENTRY
+ PRESERVE8
+
+
+
+
+
+; EXPORT __main
+ IMPORT __mbed_reset
+ IMPORT __mbed_undef
+ IMPORT __mbed_swi
+ IMPORT __mbed_prefetch_abort
+ IMPORT __mbed_data_abort
+ IMPORT __mbed_irq
+ IMPORT __mbed_fiq
+
+;
+
+
+;__main
+ LDR PC, =__mbed_reset
+ LDR PC, =__mbed_undef
+ LDR PC, =__mbed_swi
+ LDR PC, =__mbed_prefetch_abort
+ LDR PC, =__mbed_data_abort
+ NOP ;
+ LDR PC, =__mbed_irq
+ LDR PC, =__mbed_fiq
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/LPC2368.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/LPC2368.ld
new file mode 100644
index 000000000..503141fd5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/LPC2368.ld
@@ -0,0 +1,208 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+
+/* Memory Definitions: */
+MEMORY
+{
+ Flash (rx) : ORIGIN = 0x00000000, LENGTH = 512k
+ Ram (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+ UsbRam (rw) : ORIGIN = 0x7FD00000, LENGTH = 8k
+ EthRam (rw) : ORIGIN = 0x7FE00000, LENGTH = 16k
+ CanRam (rw) : ORIGIN = 0xE0038000, LENGTH = 2k
+ BatRam (rw) : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__ = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__ = ORIGIN( Ram );
+__SRAM_segment_end__ = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+ __text_start__ = . ;
+ .text : {
+ __privileged_code_start__ = . ;
+ KEEP( *( .vectors ) )
+ *( .privileged_code )
+
+ __privileged_code_end__ = .;
+
+ *( .text .text.* .gnu.linkonce.t.* )
+ *( .plt )
+ *( .gnu.warning )
+ *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+
+ *( .rodata .rodata.* .gnu.linkonce.r.* )
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .init ) )
+ . = ALIGN( 4 ) ;
+ __preinit_array_start = . ;
+ KEEP( *( .preinit_array ) )
+ __preinit_array_end = . ;
+ . = ALIGN( 4 ) ;
+ __init_array_start = . ;
+ KEEP( *( SORT( .init_array.* ) ) )
+ KEEP( *( .init_array ) )
+ __init_array_end = . ;
+
+ . = ALIGN( 4 ) ;
+ KEEP( *crtbegin.o( .ctors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+ KEEP( *( SORT( .ctors.* ) ) )
+ KEEP( *crtend.o( .ctors ) )
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .fini ) )
+ . = ALIGN( 4 ) ;
+ __fini_array_start = . ;
+ KEEP( *( .fini_array ) )
+ KEEP( *( SORT( .fini_array.* ) ) )
+ __fini_array_end = . ;
+
+ KEEP( *crtbegin.o( .dtors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+ KEEP( *( SORT( .dtors.* ) ) )
+ KEEP( *crtend.o( .dtors ) )
+
+ } >Flash
+
+ __exidx_start = . ;
+ .ARM.exidx : {
+ *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+ } >Flash
+ __exidx_end = . ;
+
+ .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+ __text_end__ = . ;
+
+ /* .bss section -- used for uninitialized data */
+ /* Located at the start of RAM */
+ .bss (NOLOAD) : {
+ __bss_start__ = . ;
+ *crt0.o( .ram_vectors )
+
+ __user_bss_start__ = . ;
+ *( .user_bss )
+ __user_bss_end__ = . ;
+
+ *( .shbss )
+ *( .bss .bss.* .gnu.linkonce.b.* )
+ *( COMMON )
+ *( .ram.b )
+ . = ALIGN( 8 ) ;
+
+ __bss_end__ = . ;
+ } >Ram AT>Flash
+
+ /* .data section -- used for initialized data */
+ .data : {
+ __data_start__ = . ;
+ KEEP( *( .jcr ) )
+ *( .got.plt ) *( .got )
+ *( .shdata )
+ *( .data .data.* .gnu.linkonce.d.* )
+ *( .ram )
+ . = ALIGN( 8 ) ;
+ __data_end__ = . ;
+ } >Ram AT>Flash
+
+ __data_init_start__ = LOADADDR( .data ) ;
+
+ /* Heap starts here and grows up in memory */
+ . = ALIGN( 8 ) ;
+ __heap_start__ = . ;
+ end = . ;
+ __end__ = . ;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections. */
+ /* Symbols in the DWARF debugging sections are relative to the */
+ /* beginning of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+
+ .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+ .ARM.attributes 0 : {
+ KEEP( *( .ARM.attributes ) )
+ KEEP( *( .gnu.attributes ) )
+ }
+ /DISCARD/ : { *( .note.GNU-stack ) }
+
+ /* C data can be defined as being in special purpose RAMs using
+ * __attribute__ ((section ("ethram"))) for example. */
+ .usbram (NOLOAD):
+ {
+ *( .usbram )
+ *( .usbram.* )
+ } > UsbRam
+ .ethram (NOLOAD):
+ {
+ *( .ethram )
+ *( .ethram.* )
+ } > EthRam
+ .canram (NOLOAD):
+ {
+ *( .canram )
+ *( .canram.* )
+ } > CanRam
+ .batram (NOLOAD):
+ {
+ *( .batram )
+ *( .batram.* )
+ } > BatRam
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.s
new file mode 100644
index 000000000..a3803a0f2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.s
@@ -0,0 +1,148 @@
+/* .include "vector_defns.h" */
+
+
+
+.section .privileged_code, "ax"
+.arm
+
+
+.weak __mbed_fiq
+.weak __mbed_undef
+.weak __mbed_prefetch_abort
+.weak __mbed_data_abort
+.weak __mbed_irq
+.weak __mbed_swi
+.weak __mbed_dcc_irq
+.weak __mbed_reset
+.global __mbed_init_realmonitor
+/* .global __mbed_init */
+
+
+
+
+__mbed_fiq:
+ B __mbed_fiq
+__mbed_undef:
+ LDR PC, =0x7fffffa0
+__mbed_prefetch_abort:
+ LDR PC, =0x7fffffb0
+__mbed_data_abort:
+ LDR PC, =0x7fffffc0
+__mbed_irq:
+ MSR CPSR_c, #0x1F|0x80|0x40
+
+ STMDB sp!, {r0-r3,r12,lr}
+
+ MOV r0, #0xFFFFFF00
+ LDR r0, [r0]
+
+ MOV lr, pc
+ BX r0
+
+ MOV r0, #0xFFFFFF00
+ STR r0, [r0]
+
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ SUBS pc, lr, #4
+__mbed_swi:
+ STMFD sp!, {a4, r4, ip, lr}
+
+ LDR r4, =0x40000040
+
+ LDR a4, =0x00940000
+ LDR PC, =0x7ffff820
+__mbed_dcc_irq:
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ SUB lr, lr, #4
+ STMFD sp!, {ip,lr}
+
+ LDR LR, =0xfffff000
+ STR LR, [LR, #0xf00]
+
+ LDR PC, =0x7fffffe0
+/*
+ __mbed_reset is called after reset
+ we setup the stacks and realmonitor, then call Reset_Handler like on M3
+*/
+
+.section .text, "ax"
+.arm
+.global Reset_handler
+Reset_Handler:
+ .extern __libc_init_array
+ .extern SystemInit
+ LDR R0, =SystemInit
+ MOV LR, PC
+ BX R0
+
+ LDR R0, =__libc_init_array
+ MOV LR, PC
+ BX R0
+
+ LDR R0, =main
+ BX R0
+
+__mbed_reset:
+ LDR R0, =( __SRAM_segment_end__ )
+
+ MSR CPSR_c, #0x1B|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x17|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x11|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000000
+
+ MSR CPSR_c, #0x12|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x13|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x10
+ MOV SP, R0
+
+/* Relocate .data section (Copy from ROM to RAM) */
+ LDR R1, =__text_end__ /* _etext */
+ LDR R2, =__data_start__ /* _data */
+ LDR R3, =__data_end__ /* _edata */
+ CMP R2, R3
+ BEQ DataIsEmpty
+LoopRel: CMP R2, R3
+ LDRLO R0, [R1], #4
+ STRLO R0, [R2], #4
+ BLO LoopRel
+DataIsEmpty:
+
+/* Clear .bss section (Zero init) */
+ MOV R0, #0
+ LDR R1, =__bss_start__
+ LDR R2, =__bss_end__
+ CMP R1,R2
+ BEQ BSSIsEmpty
+LoopZI: CMP R1, R2
+ STRLO R0, [R1], #4
+ BLO LoopZI
+BSSIsEmpty:
+
+
+/* Init realmonitor */
+ LDR R0, =__mbed_init_realmonitor
+ MOV LR, PC
+ BX R0
+
+/* Go to Reset_Handler */
+ LDR R0, =Reset_Handler
+ BX R0
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_table.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_table.s
new file mode 100644
index 000000000..d797c3794
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_table.s
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+ .section .vectors, "ax"
+ .arm
+
+
+ .global __main
+ .global __mbed_reset
+ .global __mbed_undef
+ .global __mbed_swi
+ .global __mbed_prefetch_abort
+ .global __mbed_data_abort
+ .global __mbed_irq
+ .global __mbed_fiq
+
+;
+
+
+_start:
+ LDR PC, =__mbed_reset
+ LDR PC, =__mbed_undef
+ LDR PC, =__mbed_swi
+ LDR PC, =__mbed_prefetch_abort
+ LDR PC, =__mbed_data_abort
+ NOP ;
+ LDR PC, =__mbed_irq
+ LDR PC, =__mbed_fiq
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/LPC2368.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/LPC2368.ld
new file mode 100644
index 000000000..29c738fbf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/LPC2368.ld
@@ -0,0 +1,210 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+
+GROUP( libgcc.a libc.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o )
+
+/* Memory Definitions: */
+MEMORY
+{
+ Flash (rx) : ORIGIN = 0x00000000, LENGTH = 512k
+ Ram (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+ UsbRam (rw) : ORIGIN = 0x7FD00000, LENGTH = 8k
+ EthRam (rw) : ORIGIN = 0x7FE00000, LENGTH = 16k
+ CanRam (rw) : ORIGIN = 0xE0038000, LENGTH = 2k
+ BatRam (rw) : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__ = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__ = ORIGIN( Ram );
+__SRAM_segment_end__ = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+ __text_start__ = . ;
+ .text : {
+ __privileged_code_start__ = . ;
+ KEEP( *( .vectors ) )
+ *( .privileged_code )
+
+ __privileged_code_end__ = .;
+
+ *( .text .text.* .gnu.linkonce.t.* )
+ *( .plt )
+ *( .gnu.warning )
+ *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+
+ *( .rodata .rodata.* .gnu.linkonce.r.* )
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .init ) )
+ . = ALIGN( 4 ) ;
+ __preinit_array_start = . ;
+ KEEP( *( .preinit_array ) )
+ __preinit_array_end = . ;
+ . = ALIGN( 4 ) ;
+ __init_array_start = . ;
+ KEEP( *( SORT( .init_array.* ) ) )
+ KEEP( *( .init_array ) )
+ __init_array_end = . ;
+
+ . = ALIGN( 4 ) ;
+ KEEP( *crtbegin.o( .ctors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+ KEEP( *( SORT( .ctors.* ) ) )
+ KEEP( *crtend.o( .ctors ) )
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .fini ) )
+ . = ALIGN( 4 ) ;
+ __fini_array_start = . ;
+ KEEP( *( .fini_array ) )
+ KEEP( *( SORT( .fini_array.* ) ) )
+ __fini_array_end = . ;
+
+ KEEP( *crtbegin.o( .dtors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+ KEEP( *( SORT( .dtors.* ) ) )
+ KEEP( *crtend.o( .dtors ) )
+
+ } >Flash
+
+ __exidx_start = . ;
+ .ARM.exidx : {
+ *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+ } >Flash
+ __exidx_end = . ;
+
+ .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+ __text_end__ = . ;
+
+ /* .bss section -- used for uninitialized data */
+ /* Located at the start of RAM */
+ .bss (NOLOAD) : {
+ __bss_start__ = . ;
+ *crt0.o( .ram_vectors )
+
+ __user_bss_start__ = . ;
+ *( .user_bss )
+ __user_bss_end__ = . ;
+
+ *( .shbss )
+ *( .bss .bss.* .gnu.linkonce.b.* )
+ *( COMMON )
+ *( .ram.b )
+ . = ALIGN( 8 ) ;
+
+ __bss_end__ = . ;
+ } >Ram AT>Flash
+
+ /* .data section -- used for initialized data */
+ .data : {
+ __data_start__ = . ;
+ KEEP( *( .jcr ) )
+ *( .got.plt ) *( .got )
+ *( .shdata )
+ *( .data .data.* .gnu.linkonce.d.* )
+ *( .ram )
+ . = ALIGN( 8 ) ;
+ __data_end__ = . ;
+ } >Ram AT>Flash
+
+ __data_init_start__ = LOADADDR( .data ) ;
+
+ /* Heap starts here and grows up in memory */
+ . = ALIGN( 8 ) ;
+ __heap_start__ = . ;
+ _pvHeapStart = . ;
+ end = . ;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections. */
+ /* Symbols in the DWARF debugging sections are relative to the */
+ /* beginning of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+
+ .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+ .ARM.attributes 0 : {
+ KEEP( *( .ARM.attributes ) )
+ KEEP( *( .gnu.attributes ) )
+ }
+ /DISCARD/ : { *( .note.GNU-stack ) }
+
+ /* C data can be defined as being in special purpose RAMs using
+ * __attribute__ ((section ("ethram"))) for example. */
+ .usbram (NOLOAD):
+ {
+ *( .usbram )
+ *( .usbram.* )
+ } > UsbRam
+ .ethram (NOLOAD):
+ {
+ *( .ethram )
+ *( .ethram.* )
+ } > EthRam
+ .canram (NOLOAD):
+ {
+ *( .canram )
+ *( .canram.* )
+ } > CanRam
+ .batram (NOLOAD):
+ {
+ *( .batram )
+ *( .batram.* )
+ } > BatRam
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_functions.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_functions.s
new file mode 100644
index 000000000..6e99ec8e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_functions.s
@@ -0,0 +1,149 @@
+/* .include "vector_defns.h" */
+
+
+
+.section .privileged_code, "ax"
+.arm
+
+
+.weak __mbed_fiq
+.weak __mbed_undef
+.weak __mbed_prefetch_abort
+.weak __mbed_data_abort
+.weak __mbed_irq
+.weak __mbed_swi
+.weak __mbed_dcc_irq
+.weak __mbed_reset
+.global __mbed_init_realmonitor
+/* .global __mbed_init */
+
+
+
+
+__mbed_fiq:
+ B __mbed_fiq
+__mbed_undef:
+ LDR PC, =0x7fffffa0
+__mbed_prefetch_abort:
+ LDR PC, =0x7fffffb0
+__mbed_data_abort:
+ LDR PC, =0x7fffffc0
+__mbed_irq:
+ MSR CPSR_c, #0x1F|0x80|0x40
+
+ STMDB sp!, {r0-r3,r12,lr}
+
+ MOV r0, #0xFFFFFF00
+ LDR r0, [r0]
+
+ MOV lr, pc
+ BX r0
+
+ MOV r0, #0xFFFFFF00
+ STR r0, [r0]
+
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ SUBS pc, lr, #4
+__mbed_swi:
+ STMFD sp!, {a4, r4, ip, lr}
+
+ LDR r4, =0x40000040
+
+ LDR a4, =0x00940000
+ LDR PC, =0x7ffff820
+__mbed_dcc_irq:
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ SUB lr, lr, #4
+ STMFD sp!, {ip,lr}
+
+ LDR LR, =0xfffff000
+ STR LR, [LR, #0xf00]
+
+ LDR PC, =0x7fffffe0
+/*
+ __mbed_reset is called after reset
+ we setup the stacks and realmonitor, then call Reset_Handler like on M3
+*/
+
+.section .text, "ax"
+.arm
+.global Reset_handler
+Reset_Handler:
+ .extern __libc_init_array
+ .extern SystemInit
+ .extern __wrap_main
+ LDR R0, =SystemInit
+ MOV LR, PC
+ BX R0
+
+ LDR R0, =__libc_init_array
+ MOV LR, PC
+ BX R0
+
+ LDR R0, =__wrap_main
+ BX R0
+
+__mbed_reset:
+ LDR R0, =( __SRAM_segment_end__ )
+
+ MSR CPSR_c, #0x1B|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x17|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x11|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000000
+
+ MSR CPSR_c, #0x12|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x13|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ MSR CPSR_c, #0x10
+ MOV SP, R0
+
+/* Relocate .data section (Copy from ROM to RAM) */
+ LDR R1, =__text_end__ /* _etext */
+ LDR R2, =__data_start__ /* _data */
+ LDR R3, =__data_end__ /* _edata */
+ CMP R2, R3
+ BEQ DataIsEmpty
+LoopRel: CMP R2, R3
+ LDRLO R0, [R1], #4
+ STRLO R0, [R2], #4
+ BLO LoopRel
+DataIsEmpty:
+
+/* Clear .bss section (Zero init) */
+ MOV R0, #0
+ LDR R1, =__bss_start__
+ LDR R2, =__bss_end__
+ CMP R1,R2
+ BEQ BSSIsEmpty
+LoopZI: CMP R1, R2
+ STRLO R0, [R1], #4
+ BLO LoopZI
+BSSIsEmpty:
+
+
+/* Init realmonitor */
+ LDR R0, =__mbed_init_realmonitor
+ MOV LR, PC
+ BX R0
+
+/* Go to Reset_Handler */
+ LDR R0, =Reset_Handler
+ BX R0
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_table.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_table.s
new file mode 100644
index 000000000..d797c3794
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_table.s
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+ .section .vectors, "ax"
+ .arm
+
+
+ .global __main
+ .global __mbed_reset
+ .global __mbed_undef
+ .global __mbed_swi
+ .global __mbed_prefetch_abort
+ .global __mbed_data_abort
+ .global __mbed_irq
+ .global __mbed_fiq
+
+;
+
+
+_start:
+ LDR PC, =__mbed_reset
+ LDR PC, =__mbed_undef
+ LDR PC, =__mbed_swi
+ LDR PC, =__mbed_prefetch_abort
+ LDR PC, =__mbed_data_abort
+ NOP ;
+ LDR PC, =__mbed_irq
+ LDR PC, =__mbed_fiq
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/LPC2368.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/LPC2368.ld
new file mode 100644
index 000000000..fcac82648
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/LPC2368.ld
@@ -0,0 +1,207 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+GROUP(-lsupc++ -lm -lc -lcs3unhosted -lcs3 -lgcc)
+
+/* Memory Definitions: */
+MEMORY
+{
+ Flash (rx) : ORIGIN = 0x00000000, LENGTH = 512k
+ Ram (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+ UsbRam (rw) : ORIGIN = 0x7FD00000, LENGTH = 8k
+ EthRam (rw) : ORIGIN = 0x7FE00000, LENGTH = 16k
+ CanRam (rw) : ORIGIN = 0xE0038000, LENGTH = 2k
+ BatRam (rw) : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__ = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__ = ORIGIN( Ram );
+__SRAM_segment_end__ = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+ __text_start__ = . ;
+ .text : {
+ __privileged_code_start__ = . ;
+ KEEP( *( .vectors ) )
+ *( .privileged_code )
+
+ __privileged_code_end__ = .;
+
+ *( .text .text.* .gnu.linkonce.t.* )
+ *( .plt )
+ *( .gnu.warning )
+ *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+
+ *( .rodata .rodata.* .gnu.linkonce.r.* )
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .init ) )
+ . = ALIGN( 4 ) ;
+ __preinit_array_start = . ;
+ KEEP( *( .preinit_array ) )
+ __preinit_array_end = . ;
+ . = ALIGN( 4 ) ;
+ __init_array_start = . ;
+ KEEP( *( SORT( .init_array.* ) ) )
+ KEEP( *( .init_array ) )
+ __init_array_end = . ;
+
+ . = ALIGN( 4 ) ;
+ KEEP( *crtbegin.o( .ctors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+ KEEP( *( SORT( .ctors.* ) ) )
+ KEEP( *crtend.o( .ctors ) )
+
+ . = ALIGN( 4 ) ;
+ KEEP( *( .fini ) )
+ . = ALIGN( 4 ) ;
+ __fini_array_start = . ;
+ KEEP( *( .fini_array ) )
+ KEEP( *( SORT( .fini_array.* ) ) )
+ __fini_array_end = . ;
+
+ KEEP( *crtbegin.o( .dtors ) )
+ KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+ KEEP( *( SORT( .dtors.* ) ) )
+ KEEP( *crtend.o( .dtors ) )
+
+ } >Flash
+
+ __exidx_start = . ;
+ .ARM.exidx : {
+ *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+ } >Flash
+ __exidx_end = . ;
+
+ .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+ __text_end__ = . ;
+
+ /* .bss section -- used for uninitialized data */
+ /* Located at the start of RAM */
+ .bss (NOLOAD) : {
+ __bss_start__ = . ;
+ *crt0.o( .ram_vectors )
+
+ __user_bss_start__ = . ;
+ *( .user_bss )
+ __user_bss_end__ = . ;
+
+ *( .shbss )
+ *( .bss .bss.* .gnu.linkonce.b.* )
+ *( COMMON )
+ *( .ram.b )
+ . = ALIGN( 8 ) ;
+
+ __bss_end__ = . ;
+ } >Ram AT>Flash
+
+ /* .data section -- used for initialized data */
+ .data : {
+ __data_start__ = . ;
+ KEEP( *( .jcr ) )
+ *( .got.plt ) *( .got )
+ *( .shdata )
+ *( .data .data.* .gnu.linkonce.d.* )
+ *( .ram )
+ . = ALIGN( 8 ) ;
+ __data_end__ = . ;
+ } >Ram AT>Flash
+
+ __data_init_start__ = LOADADDR( .data ) ;
+
+ /* Heap starts here and grows up in memory */
+ . = ALIGN( 8 ) ;
+ __heap_start__ = . ;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections. */
+ /* Symbols in the DWARF debugging sections are relative to the */
+ /* beginning of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+
+ .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+ .ARM.attributes 0 : {
+ KEEP( *( .ARM.attributes ) )
+ KEEP( *( .gnu.attributes ) )
+ }
+ /DISCARD/ : { *( .note.GNU-stack ) }
+
+ /* C data can be defined as being in special purpose RAMs using
+ * __attribute__ ((section ("ethram"))) for example. */
+ .usbram (NOLOAD):
+ {
+ *( .usbram )
+ *( .usbram.* )
+ } > UsbRam
+ .ethram (NOLOAD):
+ {
+ *( .ethram )
+ *( .ethram.* )
+ } > EthRam
+ .canram (NOLOAD):
+ {
+ *( .canram )
+ *( .canram.* )
+ } > CanRam
+ .batram (NOLOAD):
+ {
+ *( .batram )
+ *( .batram.* )
+ } > BatRam
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_functions.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_functions.s
new file mode 100644
index 000000000..0751c5059
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_functions.s
@@ -0,0 +1,180 @@
+# 1 "vector_functions.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_functions.s"
+;
+;
+;
+
+# 1 "vector_defns.h" 1
+# 6 "vector_functions.s" 2
+
+
+
+
+
+
+ .section VECFUNCS, "ax"
+ .arm
+
+
+ .weak __mbed_fiq
+ .weak __mbed_undef
+ .weak __mbed_prefetch_abort
+ .weak __mbed_data_abort
+ .weak __mbed_irq
+ .weak __mbed_swi
+ .weak __mbed_dcc_irq
+ .weak __mbed_reset
+ .global __mbed_init_realmonitor
+ .global __mbed_init
+
+;
+;
+__mbed_fiq:
+ B __mbed_fiq
+
+;
+;
+__mbed_undef:
+ LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort:
+ LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort:
+ LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq:
+ ;
+ MSR CPSR_c, #0x1F|0x80|0x40
+
+ ;
+ STMDB sp!, {r0-r3,r12,lr}
+
+ ;
+ MOV r0, #0xFFFFFF00
+ LDR r0, [r0]
+
+ ;
+ MOV lr, pc
+ BX r0
+
+ ;
+ MOV r0, #0xFFFFFF00
+ STR r0, [r0] ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ ;
+ SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi:
+ ;
+ ;
+ STMFD sp!, {a4, r4, ip, lr}
+
+ ;
+ LDR r4, =0x40000040
+
+ ;
+ ;
+ LDR a4, =0x00940000
+ LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq:
+
+ ;
+
+ ;
+ LDMFD sp!,{r0-r3,r12,lr}
+
+ ;
+ MSR CPSR_c, #0x12|0x80|0x40
+
+ ;
+
+ ;
+ SUB lr, lr, #4 ;
+ STMFD sp!, {ip,lr} ;
+
+ ;
+ LDR LR, =0xfffff000
+ STR LR, [LR, #0xf00]
+
+ ;
+ ;
+ ;
+ ;
+ LDR PC, =0x7fffffe0
+
+;
+;
+__mbed_reset:
+
+ ;
+
+ LDR R0, =(0x40000000 + 0x8000)
+
+ ;
+ MSR CPSR_c, #0x1B|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x17|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x11|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000000
+
+ ;
+ MSR CPSR_c, #0x12|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x13|0x80|0x40
+ MOV SP, R0
+ SUB R0, R0, #0x00000040
+
+ ;
+ MSR CPSR_c, #0x10
+ MOV SP, R0
+
+ ;
+ LDR R0, =__mbed_init_realmonitor
+ MOV LR, PC
+ BX R0
+
+ ;
+ LDR R0, =__mbed_init
+ BX R0
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_table.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_table.s
new file mode 100644
index 000000000..281e7a9bd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_table.s
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+ .section VECTOR_TABLE, "ax"
+ .arm
+
+
+ .global __main
+ .global __mbed_reset
+ .global __mbed_undef
+ .global __mbed_swi
+ .global __mbed_prefetch_abort
+ .global __mbed_data_abort
+ .global __mbed_irq
+ .global __mbed_fiq
+
+;
+
+
+__main:
+ LDR PC, =__mbed_reset
+ LDR PC, =__mbed_undef
+ LDR PC, =__mbed_swi
+ LDR PC, =__mbed_prefetch_abort
+ LDR PC, =__mbed_data_abort
+ NOP ;
+ LDR PC, =__mbed_irq
+ LDR PC, =__mbed_fiq
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h
new file mode 100644
index 000000000..3926baf40
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC2368 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC23xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c
new file mode 100644
index 000000000..6df47d1b3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ LPC_VIC->VectAddr[(int)IRQn] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ return LPC_VIC->VectAddr[(int)IRQn];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h
new file mode 100644
index 000000000..a4ab25649
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS 32
+#define NVIC_USER_IRQ_OFFSET 0
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.c
new file mode 100644
index 000000000..3ed1daeeb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.c
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on core_cm3.h, V1.20
+ */
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for armcc */
+ #define __INLINE __inline /*!< inline keyword for armcc */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for iarcc */
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for gcc */
+ #define __INLINE inline /*!< inline keyword for gcc */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+#if defined ( __CC_ARM )
+/**
+ * @brief Return the Main Stack Pointer (return current ARM7 stack)
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ return __current_sp();
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h
new file mode 100644
index 000000000..965581305
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h
@@ -0,0 +1,276 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on core_cm3.h, V1.20
+ */
+
+#ifndef __ARM7_CORE_H__
+#define __ARM7_CORE_H__
+
+#include "vector_defns.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+#include <stdint.h> /* Include standard types */
+
+#if defined ( __CC_ARM )
+/**
+ * @brief Return the Main Stack Pointer (current ARM7 stack)
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+#endif
+
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+typedef struct
+{
+ uint32_t IRQStatus;
+ uint32_t FIQStatus;
+ uint32_t RawIntr;
+ uint32_t IntSelect;
+ uint32_t IntEnable;
+ uint32_t IntEnClr;
+ uint32_t SoftInt;
+ uint32_t SoftIntClr;
+ uint32_t Protection;
+ uint32_t SWPriorityMask;
+ uint32_t RESERVED0[54];
+ uint32_t VectAddr[32];
+ uint32_t RESERVED1[32];
+ uint32_t VectPriority[32];
+ uint32_t RESERVED2[800];
+ uint32_t Address;
+} NVIC_TypeDef;
+
+#define NVIC_BASE (0xFFFFF000)
+#define NVIC (( NVIC_TypeDef *) NVIC_BASE)
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define __I volatile /*!< defines 'read only' permissions */
+#else
+#define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+//#define __WFI __wfi
+//#define __WFE __wfe
+//#define __SEV __sev
+//#define __ISB() __isb(0)
+//#define __DSB() __dsb(0)
+//#define __DMB() __dmb(0)
+//#define __REV __rev
+//#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
+ LPC_VIC->IntEnClr = 0xffffffff
+
+#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+static __INLINE void __enable_irq() {
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+static __INLINE void __disable_irq() {
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ // return (old & 0x80) == 0;
+}
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnable = 1 << (uint32_t)IRQn;
+}
+
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnClr = 1 << (uint32_t)IRQn;
+}
+
+static __INLINE uint32_t __get_IPSR(void)
+{
+ unsigned i;
+
+ for(i = 0; i < 32; i ++)
+ if(NVIC->Address == NVIC->VectAddr[i])
+ return i;
+ return 1; // 1 is an invalid entry in the interrupt table on LPC2368
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM7_CORE_H__ */
+
+/*lint -restore */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c
new file mode 100644
index 000000000..fc5d804ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ */
+
+#include <stdint.h>
+#include "LPC23xx.h"
+
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00000013
+#define CCLKCFG_Val 0x00000007
+#define USBCLKCFG_Val 0x00000009
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000000
+#define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
+#define MAMTIM_Val 0x00000004
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+/* F_cco0 = (2 * M * F_in) / N */
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+ #endif
+ #endif
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = (IRC_OSC *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = (OSC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = (RTC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+
+#if (PLL0_SETUP)
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
+
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+#endif
+
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ // Setup MAM
+ LPC_SC->MAMTIM = MAMTIM_Val;
+ LPC_SC->MAMCR = MAMCR_Val;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.h
new file mode 100644
index 000000000..f14b72a83
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.h
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on cmsis system_LPC17xx.h
+ */
+
+#ifndef __SYSTEM_LPC23xx_H
+#define __SYSTEM_LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h
new file mode 100644
index 000000000..10b0b6a05
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library - Vectors
+ * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+ */
+
+#ifndef MBED_VECTOR_DEFNS_H
+#define MBED_VECTOR_DEFNS_H
+
+// Assember Macros
+#ifdef __ARMCC_VERSION
+#define EXPORT(x) EXPORT x
+#define WEAK_EXPORT(x) EXPORT x [WEAK]
+#define IMPORT(x) IMPORT x
+#define LABEL(x) x
+#else
+#define EXPORT(x) .global x
+#define WEAK_EXPORT(x) .weak x
+#define IMPORT(x) .global x
+#define LABEL(x) x:
+#endif
+
+// RealMonitor
+// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
+
+// RealMonitor entry points
+#define rm_init_entry 0x7fffff91
+#define rm_undef_handler 0x7fffffa0
+#define rm_prefetchabort_handler 0x7fffffb0
+#define rm_dataabort_handler 0x7fffffc0
+#define rm_irqhandler2 0x7fffffe0
+//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
+#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
+
+// Unofficial RealMonitor entry points and variables
+#define RM_MSG_SWI 0x00940000
+#define StateP 0x40000040
+
+// VIC register addresses
+#define VIC_Base 0xfffff000
+#define VICAddress_Offset 0xf00
+#define VICVectAddr0_Offset 0x100
+#define VICVectAddr2_Offset 0x108
+#define VICVectAddr3_Offset 0x10c
+#define VICVectAddr31_Offset 0x17c
+#define VICIntEnClr_Offset 0x014
+#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
+#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
+#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
+
+// ARM Mode bits and Interrupt flags in PSRs
+#define Mode_USR 0x10
+#define Mode_FIQ 0x11
+#define Mode_IRQ 0x12
+#define Mode_SVC 0x13
+#define Mode_ABT 0x17
+#define Mode_UND 0x1B
+#define Mode_SYS 0x1F
+#define I_Bit 0x80 // when I bit is set, IRQ is disabled
+#define F_Bit 0x40 // when F bit is set, FIQ is disabled
+
+// MCU RAM
+#define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base
+#define LPC2368_RAM_SIZE 0x8000 // 32KB
+
+// ISR Stack Allocation
+#define UND_stack_size 0x00000040
+#define SVC_stack_size 0x00000040
+#define ABT_stack_size 0x00000040
+#define FIQ_stack_size 0x00000000
+#define IRQ_stack_size 0x00000040
+
+#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
+
+// Full Descending Stack, so top-most stack points to just above the top of RAM
+#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
+#define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size)
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_realmonitor.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_realmonitor.c
new file mode 100644
index 000000000..921fe4329
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_realmonitor.c
@@ -0,0 +1,22 @@
+/* mbed Microcontroller Library - RealMonitor
+ * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+ */
+#include "vector_defns.h"
+
+extern void __mbed_dcc_irq(void);
+
+/* Function: __mbed_init_realmonitor
+ * Setup the RealMonitor DCC Interrupt Handlers
+ */
+void __mbed_init_realmonitor(void) __attribute__((weak));
+void __mbed_init_realmonitor() {
+ // Disable all interrupts
+ VICIntEnClr = 0xffffffff;
+
+ // Set DCC interrupt vector addresses
+ VICVectAddr2 = (unsigned)&__mbed_dcc_irq;
+ VICVectAddr3 = (unsigned)&__mbed_dcc_irq;
+
+ // Initialise RealMonitor
+ ((void (*)(void))rm_init_entry)();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h
new file mode 100644
index 000000000..2a2220b0d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h
@@ -0,0 +1,1523 @@
+/****************************************************************************************************//**
+* $Id$ LPC407x_8x_177x_8x.h 2012-04-25
+*//**
+ * @file LPC407x_8x_177x_8x.h
+ *
+ * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
+ * NXP LPC407x_8x_177x_8x.
+ * @version V0.7
+ * @date 20. June 2012
+ * @author NXP MCU SW Application Team
+*
+* Copyright(C) 2012, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __LPC407x_8x_177x_8x_H__
+#define __LPC407x_8x_177x_8x_H__
+
+#if defined(__CORTEX_M4) && !defined(CORE_M4)
+ #define CORE_M4
+#endif
+
+// ##################
+// Code Red - excluded extern "C" as unrequired
+// ##################
+#if 0
+#ifdef __cplusplus
+extern "C" {
+#endif
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ Reserved0_IRQn = 13, /*!< Reserved */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /*!< USB Activity interrupt */
+ CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
+ UART4_IRQn = 35, /*!< UART4 Interrupt */
+ SSP2_IRQn = 36, /*!< SSP2 Interrupt */
+ LCD_IRQn = 37, /*!< LCD Interrupt */
+ GPIO_IRQn = 38, /*!< GPIO Interrupt */
+ PWM0_IRQn = 39, /*!< 39 PWM0 */
+ EEPROM_IRQn = 40, /*!< 40 EEPROM */
+ CMP0_IRQn = 41, /*!< 41 CMP0 */
+ CMP1_IRQn = 42 /*!< 42 CMP1 */
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+#ifdef CORE_M4
+/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
+#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#else
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+
+#endif
+
+#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t IntStat;
+ __I uint32_t IntTCStat;
+ __O uint32_t IntTCClear;
+ __I uint32_t IntErrStat;
+ __O uint32_t IntErrClr;
+ __I uint32_t RawIntTCStat;
+ __I uint32_t RawIntErrStat;
+ __I uint32_t EnbldChns;
+ __IO uint32_t SoftBReq;
+ __IO uint32_t SoftSReq;
+ __IO uint32_t SoftLBReq;
+ __IO uint32_t SoftLSReq;
+ __IO uint32_t Config;
+ __IO uint32_t Sync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t CSrcAddr;
+ __IO uint32_t CDestAddr;
+ __IO uint32_t CLLI;
+ __IO uint32_t CControl;
+ __IO uint32_t CConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
+ __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
+ __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
+ __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
+ __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
+ __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
+ __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
+ __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
+ __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
+ uint32_t RESERVED3[13];
+ __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
+ __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
+ __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
+ __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
+ __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
+ __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
+ uint32_t RESERVED5[1];
+ __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
+ __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
+ __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
+ __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
+ uint32_t RESERVED8;
+ __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
+ __IO uint32_t SPIFICLKSEL;
+ __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
+ uint32_t RESERVED10[1];
+ __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
+ __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
+ __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
+ __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
+ __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
+ uint32_t RESERVED11[2];
+ __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
+ __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
+ } LPC_SC_TypeDef;
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __I uint32_t RxFilterWoLStatus;
+ __O uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+/*------------- LCD controller (LCD) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t TIMH; /* LCD Registers */
+ __IO uint32_t TIMV;
+ __IO uint32_t POL;
+ __IO uint32_t LE;
+ __IO uint32_t UPBASE;
+ __IO uint32_t LPBASE;
+ __IO uint32_t CTRL;
+ __IO uint32_t INTMSK;
+ __I uint32_t INTRAW;
+ __I uint32_t INTSTAT;
+ __O uint32_t INTCLR;
+ __I uint32_t UPCURR;
+ __I uint32_t LPCURR;
+ uint32_t RESERVED0[115];
+ __IO uint32_t PAL[128];
+ uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];
+ __IO uint32_t CRSR_CTRL;
+ __IO uint32_t CRSR_CFG;
+ __IO uint32_t CRSR_PAL0;
+ __IO uint32_t CRSR_PAL1;
+ __IO uint32_t CRSR_XY;
+ __IO uint32_t CRSR_CLIP;
+ uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK;
+ __O uint32_t CRSR_INTCLR;
+ __I uint32_t CRSR_INTRAW;
+ __I uint32_t CRSR_INTSTAT;
+} LPC_LCD_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t Revision; /* USB Host Registers */
+ __IO uint32_t Control;
+ __IO uint32_t CommandStatus;
+ __IO uint32_t InterruptStatus;
+ __IO uint32_t InterruptEnable;
+ __IO uint32_t InterruptDisable;
+ __IO uint32_t HCCA;
+ __I uint32_t PeriodCurrentED;
+ __IO uint32_t ControlHeadED;
+ __IO uint32_t ControlCurrentED;
+ __IO uint32_t BulkHeadED;
+ __IO uint32_t BulkCurrentED;
+ __I uint32_t DoneHead;
+ __IO uint32_t FmInterval;
+ __I uint32_t FmRemaining;
+ __I uint32_t FmNumber;
+ __IO uint32_t PeriodicStart;
+ __IO uint32_t LSTreshold;
+ __IO uint32_t RhDescriptorA;
+ __IO uint32_t RhDescriptorB;
+ __IO uint32_t RhStatus;
+ __IO uint32_t RhPortStatus1;
+ __IO uint32_t RhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t IntSt; /* USB On-The-Go Registers */
+ __IO uint32_t IntEn;
+ __O uint32_t IntSet;
+ __O uint32_t IntClr;
+ __IO uint32_t StCtrl;
+ __IO uint32_t Tmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t DevIntEn;
+ __O uint32_t DevIntClr;
+ __O uint32_t DevIntSet;
+
+ __O uint32_t CmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t CmdData;
+
+ __I uint32_t RxData; /* USB Device Transfer Registers */
+ __O uint32_t TxData;
+ __I uint32_t RxPLen;
+ __O uint32_t TxPLen;
+ __IO uint32_t Ctrl;
+ __O uint32_t DevIntPri;
+
+ __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t EpIntEn;
+ __O uint32_t EpIntClr;
+ __O uint32_t EpIntSet;
+ __O uint32_t EpIntPri;
+
+ __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t EpInd;
+ __IO uint32_t MaxPSize;
+
+ __I uint32_t DMARSt; /* USB Device DMA Registers */
+ __O uint32_t DMARClr;
+ __O uint32_t DMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t UDCAH;
+ __I uint32_t EpDMASt;
+ __O uint32_t EpDMAEn;
+ __O uint32_t EpDMADis;
+ __I uint32_t DMAIntSt;
+ __IO uint32_t DMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t EoTIntSt;
+ __O uint32_t EoTIntClr;
+ __O uint32_t EoTIntSet;
+ __I uint32_t NDDRIntSt;
+ __O uint32_t NDDRIntClr;
+ __O uint32_t NDDRIntSet;
+ __I uint32_t SysErrIntSt;
+ __O uint32_t SysErrIntClr;
+ __O uint32_t SysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __IO uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ struct {
+ __O uint32_t DATA;
+ } WR_DATA_DWORD;
+
+ struct {
+ __O uint16_t DATA;
+ uint16_t RESERVED;
+ }WR_DATA_WORD;
+
+ struct {
+ __O uint8_t DATA;
+ uint8_t RESERVED[3];
+ }WR_DATA_BYTE;
+ };
+} LPC_CRC_TypeDef;
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t DIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t MASK;
+ __IO uint32_t PIN;
+ __IO uint32_t SET;
+ __O uint32_t CLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- External Memory Controller (EMC) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t Control;
+ __I uint32_t Status;
+ __IO uint32_t Config;
+ uint32_t RESERVED0[5];
+ __IO uint32_t DynamicControl;
+ __IO uint32_t DynamicRefresh;
+ __IO uint32_t DynamicReadConfig;
+ uint32_t RESERVED1[1];
+ __IO uint32_t DynamicRP;
+ __IO uint32_t DynamicRAS;
+ __IO uint32_t DynamicSREX;
+ __IO uint32_t DynamicAPR;
+ __IO uint32_t DynamicDAL;
+ __IO uint32_t DynamicWR;
+ __IO uint32_t DynamicRC;
+ __IO uint32_t DynamicRFC;
+ __IO uint32_t DynamicXSR;
+ __IO uint32_t DynamicRRD;
+ __IO uint32_t DynamicMRD;
+ uint32_t RESERVED2[9];
+ __IO uint32_t StaticExtendedWait;
+ uint32_t RESERVED3[31];
+ __IO uint32_t DynamicConfig0;
+ __IO uint32_t DynamicRasCas0;
+ uint32_t RESERVED4[6];
+ __IO uint32_t DynamicConfig1;
+ __IO uint32_t DynamicRasCas1;
+ uint32_t RESERVED5[6];
+ __IO uint32_t DynamicConfig2;
+ __IO uint32_t DynamicRasCas2;
+ uint32_t RESERVED6[6];
+ __IO uint32_t DynamicConfig3;
+ __IO uint32_t DynamicRasCas3;
+ uint32_t RESERVED7[38];
+ __IO uint32_t StaticConfig0;
+ __IO uint32_t StaticWaitWen0;
+ __IO uint32_t StaticWaitOen0;
+ __IO uint32_t StaticWaitRd0;
+ __IO uint32_t StaticWaitPage0;
+ __IO uint32_t StaticWaitWr0;
+ __IO uint32_t StaticWaitTurn0;
+ uint32_t RESERVED8[1];
+ __IO uint32_t StaticConfig1;
+ __IO uint32_t StaticWaitWen1;
+ __IO uint32_t StaticWaitOen1;
+ __IO uint32_t StaticWaitRd1;
+ __IO uint32_t StaticWaitPage1;
+ __IO uint32_t StaticWaitWr1;
+ __IO uint32_t StaticWaitTurn1;
+ uint32_t RESERVED9[1];
+ __IO uint32_t StaticConfig2;
+ __IO uint32_t StaticWaitWen2;
+ __IO uint32_t StaticWaitOen2;
+ __IO uint32_t StaticWaitRd2;
+ __IO uint32_t StaticWaitPage2;
+ __IO uint32_t StaticWaitWr2;
+ __IO uint32_t StaticWaitTurn2;
+ uint32_t RESERVED10[1];
+ __IO uint32_t StaticConfig3;
+ __IO uint32_t StaticWaitWen3;
+ __IO uint32_t StaticWaitOen3;
+ __IO uint32_t StaticWaitRd3;
+ __IO uint32_t StaticWaitPage3;
+ __IO uint32_t StaticWaitWr3;
+ __IO uint32_t StaticWaitTurn3;
+} LPC_EMC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t MOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t TC;
+ __O uint8_t FEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t TV;
+ uint32_t RESERVED2;
+ __IO uint32_t WARNINT;
+ __IO uint32_t WINDOW;
+} LPC_WDT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+} LPC_TIM_TypeDef;
+
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
+ __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
+ uint32_t RESERVED0;
+ __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
+ __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
+ __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
+ __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
+ __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
+/* There are three types of UARTs on the chip:
+(1) UART0,UART2, and UART3 are the standard UART.
+(2) UART1 is the standard with modem capability.
+(3) USART(UART4) is the sync/async UART with smart card capability.
+More details can be found on the Users Manual. */
+
+#if 0
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL;
+} LPC_UART_TypeDef;
+#else
+typedef struct
+{
+ union
+ {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union
+ {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union
+ {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];//Reserved
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];//Reserved
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];//Reserved
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];//Reserved
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];//Reserved
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];//Reserved
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];//Reserved
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];//Reserved
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];//Reserved
+ __I uint8_t FIFOLVL;
+}LPC_UART_TypeDef;
+#endif
+
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __I uint8_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
+ __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
+ __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
+ __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[989];
+ __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
+ __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
+ __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
+ __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
+ __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
+ __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
+ __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
+ uint32_t RESERVED3[3];
+ __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
+} LPC_UART4_TypeDef;
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+ __IO uint32_t ERSTATUS;
+ __IO uint32_t ERCONTROL;
+ __IO uint32_t ERCOUNTERS;
+ uint32_t RESERVED22;
+ __IO uint32_t ERFIRSTSTAMP0;
+ __IO uint32_t ERFIRSTSTAMP1;
+ __IO uint32_t ERFIRSTSTAMP2;
+ uint32_t RESERVED23;
+ __IO uint32_t ERLASTSTAMP0;
+ __IO uint32_t ERLASTSTAMP1;
+ __IO uint32_t ERLASTSTAMP2;
+} LPC_RTC_TypeDef;
+
+
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t P0_0; /* 0x000 */
+ __IO uint32_t P0_1;
+ __IO uint32_t P0_2;
+ __IO uint32_t P0_3;
+ __IO uint32_t P0_4;
+ __IO uint32_t P0_5;
+ __IO uint32_t P0_6;
+ __IO uint32_t P0_7;
+
+ __IO uint32_t P0_8; /* 0x020 */
+ __IO uint32_t P0_9;
+ __IO uint32_t P0_10;
+ __IO uint32_t P0_11;
+ __IO uint32_t P0_12;
+ __IO uint32_t P0_13;
+ __IO uint32_t P0_14;
+ __IO uint32_t P0_15;
+
+ __IO uint32_t P0_16; /* 0x040 */
+ __IO uint32_t P0_17;
+ __IO uint32_t P0_18;
+ __IO uint32_t P0_19;
+ __IO uint32_t P0_20;
+ __IO uint32_t P0_21;
+ __IO uint32_t P0_22;
+ __IO uint32_t P0_23;
+
+ __IO uint32_t P0_24; /* 0x060 */
+ __IO uint32_t P0_25;
+ __IO uint32_t P0_26;
+ __IO uint32_t P0_27;
+ __IO uint32_t P0_28;
+ __IO uint32_t P0_29;
+ __IO uint32_t P0_30;
+ __IO uint32_t P0_31;
+
+ __IO uint32_t P1_0; /* 0x080 */
+ __IO uint32_t P1_1;
+ __IO uint32_t P1_2;
+ __IO uint32_t P1_3;
+ __IO uint32_t P1_4;
+ __IO uint32_t P1_5;
+ __IO uint32_t P1_6;
+ __IO uint32_t P1_7;
+
+ __IO uint32_t P1_8; /* 0x0A0 */
+ __IO uint32_t P1_9;
+ __IO uint32_t P1_10;
+ __IO uint32_t P1_11;
+ __IO uint32_t P1_12;
+ __IO uint32_t P1_13;
+ __IO uint32_t P1_14;
+ __IO uint32_t P1_15;
+
+ __IO uint32_t P1_16; /* 0x0C0 */
+ __IO uint32_t P1_17;
+ __IO uint32_t P1_18;
+ __IO uint32_t P1_19;
+ __IO uint32_t P1_20;
+ __IO uint32_t P1_21;
+ __IO uint32_t P1_22;
+ __IO uint32_t P1_23;
+
+ __IO uint32_t P1_24; /* 0x0E0 */
+ __IO uint32_t P1_25;
+ __IO uint32_t P1_26;
+ __IO uint32_t P1_27;
+ __IO uint32_t P1_28;
+ __IO uint32_t P1_29;
+ __IO uint32_t P1_30;
+ __IO uint32_t P1_31;
+
+ __IO uint32_t P2_0; /* 0x100 */
+ __IO uint32_t P2_1;
+ __IO uint32_t P2_2;
+ __IO uint32_t P2_3;
+ __IO uint32_t P2_4;
+ __IO uint32_t P2_5;
+ __IO uint32_t P2_6;
+ __IO uint32_t P2_7;
+
+ __IO uint32_t P2_8; /* 0x120 */
+ __IO uint32_t P2_9;
+ __IO uint32_t P2_10;
+ __IO uint32_t P2_11;
+ __IO uint32_t P2_12;
+ __IO uint32_t P2_13;
+ __IO uint32_t P2_14;
+ __IO uint32_t P2_15;
+
+ __IO uint32_t P2_16; /* 0x140 */
+ __IO uint32_t P2_17;
+ __IO uint32_t P2_18;
+ __IO uint32_t P2_19;
+ __IO uint32_t P2_20;
+ __IO uint32_t P2_21;
+ __IO uint32_t P2_22;
+ __IO uint32_t P2_23;
+
+ __IO uint32_t P2_24; /* 0x160 */
+ __IO uint32_t P2_25;
+ __IO uint32_t P2_26;
+ __IO uint32_t P2_27;
+ __IO uint32_t P2_28;
+ __IO uint32_t P2_29;
+ __IO uint32_t P2_30;
+ __IO uint32_t P2_31;
+
+ __IO uint32_t P3_0; /* 0x180 */
+ __IO uint32_t P3_1;
+ __IO uint32_t P3_2;
+ __IO uint32_t P3_3;
+ __IO uint32_t P3_4;
+ __IO uint32_t P3_5;
+ __IO uint32_t P3_6;
+ __IO uint32_t P3_7;
+
+ __IO uint32_t P3_8; /* 0x1A0 */
+ __IO uint32_t P3_9;
+ __IO uint32_t P3_10;
+ __IO uint32_t P3_11;
+ __IO uint32_t P3_12;
+ __IO uint32_t P3_13;
+ __IO uint32_t P3_14;
+ __IO uint32_t P3_15;
+
+ __IO uint32_t P3_16; /* 0x1C0 */
+ __IO uint32_t P3_17;
+ __IO uint32_t P3_18;
+ __IO uint32_t P3_19;
+ __IO uint32_t P3_20;
+ __IO uint32_t P3_21;
+ __IO uint32_t P3_22;
+ __IO uint32_t P3_23;
+
+ __IO uint32_t P3_24; /* 0x1E0 */
+ __IO uint32_t P3_25;
+ __IO uint32_t P3_26;
+ __IO uint32_t P3_27;
+ __IO uint32_t P3_28;
+ __IO uint32_t P3_29;
+ __IO uint32_t P3_30;
+ __IO uint32_t P3_31;
+
+ __IO uint32_t P4_0; /* 0x200 */
+ __IO uint32_t P4_1;
+ __IO uint32_t P4_2;
+ __IO uint32_t P4_3;
+ __IO uint32_t P4_4;
+ __IO uint32_t P4_5;
+ __IO uint32_t P4_6;
+ __IO uint32_t P4_7;
+
+ __IO uint32_t P4_8; /* 0x220 */
+ __IO uint32_t P4_9;
+ __IO uint32_t P4_10;
+ __IO uint32_t P4_11;
+ __IO uint32_t P4_12;
+ __IO uint32_t P4_13;
+ __IO uint32_t P4_14;
+ __IO uint32_t P4_15;
+
+ __IO uint32_t P4_16; /* 0x240 */
+ __IO uint32_t P4_17;
+ __IO uint32_t P4_18;
+ __IO uint32_t P4_19;
+ __IO uint32_t P4_20;
+ __IO uint32_t P4_21;
+ __IO uint32_t P4_22;
+ __IO uint32_t P4_23;
+
+ __IO uint32_t P4_24; /* 0x260 */
+ __IO uint32_t P4_25;
+ __IO uint32_t P4_26;
+ __IO uint32_t P4_27;
+ __IO uint32_t P4_28;
+ __IO uint32_t P4_29;
+ __IO uint32_t P4_30;
+ __IO uint32_t P4_31;
+
+ __IO uint32_t P5_0; /* 0x280 */
+ __IO uint32_t P5_1;
+ __IO uint32_t P5_2;
+ __IO uint32_t P5_3;
+ __IO uint32_t P5_4; /* 0x290 */
+} LPC_IOCON_TypeDef;
+
+
+
+
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
+ __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ ///Offset: 0x00000000 - Acceptance Filter Register
+ __IO uint32_t AFMR;
+
+ ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
+ __IO uint32_t SFF_sa;
+
+ ///Offset: 0x00000008 - Standard Frame Group Start Address Register
+ __IO uint32_t SFF_GRP_sa;
+
+ ///Offset: 0x0000000C - Extended Frame Start Address Register
+ __IO uint32_t EFF_sa;
+
+ ///Offset: 0x00000010 - Extended Frame Group Start Address Register
+ __IO uint32_t EFF_GRP_sa;
+
+ ///Offset: 0x00000014 - End of AF Tables register
+ __IO uint32_t ENDofTable;
+
+ ///Offset: 0x00000018 - LUT Error Address register
+ __I uint32_t LUTerrAd;
+
+ ///Offset: 0x0000001C - LUT Error Register
+ __I uint32_t LUTerr;
+
+ ///Offset: 0x00000020 - CAN Central Transmit Status Register
+ __IO uint32_t FCANIE;
+
+ ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
+ __IO uint32_t FCANIC0;
+
+ ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t TxSR;
+ __I uint32_t RxSR;
+ __I uint32_t MSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
+ __IO uint32_t MOD;
+
+ ///Offset: 0x00000004 - Command bits that affect the state
+ __O uint32_t CMR;
+
+ ///Offset: 0x00000008 - Global Controller Status and Error Counters
+ __IO uint32_t GSR;
+
+ ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
+ __I uint32_t ICR;
+
+ ///Offset: 0x00000010 - Interrupt Enable Register
+ __IO uint32_t IER;
+
+ ///Offset: 0x00000014 - Bus Timing Register
+ __IO uint32_t BTR;
+
+ ///Offset: 0x00000018 - Error Warning Limit
+ __IO uint32_t EWL;
+
+ ///Offset: 0x0000001C - Status Register
+ __I uint32_t SR;
+
+ ///Offset: 0x00000020 - Receive frame status
+ __IO uint32_t RFS;
+
+ ///Offset: 0x00000024 - Received Identifier
+ __IO uint32_t RID;
+
+ ///Offset: 0x00000028 - Received data bytes 1-4
+ __IO uint32_t RDA;
+
+ ///Offset: 0x0000002C - Received data bytes 5-8
+ __IO uint32_t RDB;
+
+ ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
+ __IO uint32_t TFI1;
+
+ ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
+ __IO uint32_t TID1;
+
+ ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
+ __IO uint32_t TDA1;
+
+ ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
+ __IO uint32_t TDB1;
+
+ ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
+ __IO uint32_t TFI2;
+
+ ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
+ __IO uint32_t TID2;
+
+ ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
+ __IO uint32_t TDA2;
+
+ ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
+ __IO uint32_t TDB2;
+
+ ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
+ __IO uint32_t TFI3;
+
+ ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
+ __IO uint32_t TID3;
+
+ ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
+ __IO uint32_t TDA3;
+
+ ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CTRL;
+ __IO uint32_t CNTVAL;
+} LPC_DAC_TypeDef;
+
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t DAO;
+ __IO uint32_t DAI;
+ __O uint32_t TXFIFO;
+ __I uint32_t RXFIFO;
+ __I uint32_t STATE;
+ __IO uint32_t DMA1;
+ __IO uint32_t DMA2;
+ __IO uint32_t IRQ;
+ __IO uint32_t TXRATE;
+ __IO uint32_t RXRATE;
+ __IO uint32_t TXBITRATE;
+ __IO uint32_t RXBITRATE;
+ __IO uint32_t TXMODE;
+ __IO uint32_t RXMODE;
+} LPC_I2S_TypeDef;
+
+
+
+
+
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t CON;
+ __O uint32_t CON_SET;
+ __O uint32_t CON_CLR;
+ __I uint32_t CAPCON;
+ __O uint32_t CAPCON_SET;
+ __O uint32_t CAPCON_CLR;
+ __IO uint32_t TC0;
+ __IO uint32_t TC1;
+ __IO uint32_t TC2;
+ __IO uint32_t LIM0;
+ __IO uint32_t LIM1;
+ __IO uint32_t LIM2;
+ __IO uint32_t MAT0;
+ __IO uint32_t MAT1;
+ __IO uint32_t MAT2;
+ __IO uint32_t DT;
+ __IO uint32_t CP;
+ __IO uint32_t CAP0;
+ __IO uint32_t CAP1;
+ __IO uint32_t CAP2;
+ __I uint32_t INTEN;
+ __O uint32_t INTEN_SET;
+ __O uint32_t INTEN_CLR;
+ __I uint32_t CNTCON;
+ __O uint32_t CNTCON_SET;
+ __O uint32_t CNTCON_CLR;
+ __I uint32_t INTF;
+ __O uint32_t INTF_SET;
+ __O uint32_t INTF_CLR;
+ __O uint32_t CAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t CON;
+ __I uint32_t STAT;
+ __IO uint32_t CONF;
+ __I uint32_t POS;
+ __IO uint32_t MAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP0;
+ __IO uint32_t LOAD;
+ __I uint32_t TIME;
+ __I uint32_t VEL;
+ __I uint32_t CAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTERPHA;
+ __IO uint32_t FILTERPHB;
+ __IO uint32_t FILTERINX;
+ __IO uint32_t WINDOW;
+ __IO uint32_t INXCMP1;
+ __IO uint32_t INXCMP2;
+ uint32_t RESERVED0[993];
+ __O uint32_t IEC;
+ __O uint32_t IES;
+ __I uint32_t INTSTAT;
+ __I uint32_t IE;
+ __O uint32_t CLR;
+ __O uint32_t SET;
+} LPC_QEI_TypeDef;
+
+/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLOCK;
+ __IO uint32_t ARGUMENT;
+ __IO uint32_t COMMAND;
+ __I uint32_t RESP_CMD;
+ __I uint32_t RESP0;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __IO uint32_t DATATMR;
+ __IO uint32_t DATALEN;
+ __IO uint32_t DATACTRL;
+ __I uint32_t DATACNT;
+ __I uint32_t STATUS;
+ __O uint32_t CLEAR;
+ __IO uint32_t MASK0;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO[16];
+} LPC_MCI_TypeDef;
+
+
+
+
+
+
+
+
+
+
+/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t CMD; /* 0x0080 */
+ __IO uint32_t ADDR;
+ __IO uint32_t WDATA;
+ __IO uint32_t RDATA;
+ __IO uint32_t WSTATE; /* 0x0090 */
+ __IO uint32_t CLKDIV;
+ __IO uint32_t PWRDWN; /* 0x0098 */
+ uint32_t RESERVED0[975];
+ __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
+ __IO uint32_t INT_SET_ENABLE;
+ __IO uint32_t INT_STATUS; /* 0x0FE0 */
+ __IO uint32_t INT_ENABLE;
+ __IO uint32_t INT_CLR_STATUS;
+ __IO uint32_t INT_SET_STATUS;
+} LPC_EEPROM_TypeDef;
+
+
+/*------------- COMPARATOR ----------------------------------------------------*/
+
+typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
+ __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
+ __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
+} LPC_COMPARATOR_Type;
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_PERI_RAM_BASE (0x20000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHBRAM1_BASE (0x20004000UL)
+#define LPC_AHB_BASE (0x20080000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
+#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
+#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
+#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
+
+#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
+#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
+#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
+
+
+
+#endif // __LPC407x_8x_177x_8x_H__
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct
new file mode 100644
index 000000000..e24f8b1c0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct
@@ -0,0 +1,31 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ *.o (+RO-CODE) ; prioritizes CODE in IFLASH before SPIFI
+ .ANY2 (+RO-DATA) ; prioritizes DATA in IFLASH before SPIFI
+ .ANY (+RO) ; remaining RO
+ }
+ RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x00004000 {
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20004000 0x00004000 {
+ .ANY (AHBSRAM1)
+ }
+}
+
+LR_IROM2 0x28000000 0x01000000 {
+ ER_IROM2 0x28000000 0x01000000 { ; load address = execution address
+ .ANY1 (+RO-DATA) ; all DATA not fitting in IFLASH
+ .ANY (SPIFI_MEM) ; DATA tagged as SPIFI_MEM
+ *.o (SPIFI_MEM) ; CODE tagged as SPIFI_MEM
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.s
new file mode 100644
index 000000000..192f76842
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.s
@@ -0,0 +1,254 @@
+;/*****************************************************************************
+; * @file: startup_LPC407x_8x.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+; * for the NXP LPC407x_8x Device Series
+; * @version: V1.20
+; * @date: 16. January 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+
+__initial_sp EQU 0x10010000 ; Top of RAM from LPC4088
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ ; DCD 0xEFFFF5D6 ; Reserved- vector sum
+ DCD 0xEFFFF39E ; Reserved- vector sum
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD 0 ; 29: reserved, not for SPIFI anymore
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD MCI_IRQHandler ; 45: SD/MMC card I/F
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+ DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
+ DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
+ DCD UART4_IRQHandler ; 51: UART4
+ DCD SSP2_IRQHandler ; 52: SSP2
+ DCD LCD_IRQHandler ; 53: LCD
+ DCD GPIO_IRQHandler ; 54: GPIO
+ DCD PWM0_IRQHandler ; 55: PWM0
+ DCD EEPROM_IRQHandler ; 56: EEPROM
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ ;EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT MCI_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+ EXPORT USBActivity_IRQHandler [WEAK]
+ EXPORT CANActivity_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT SSP2_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT GPIO_IRQHandler [WEAK]
+ EXPORT PWM0_IRQHandler [WEAK]
+ EXPORT EEPROM_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+;SPIFI_IRQHandler ;not used
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+MCI_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+USBActivity_IRQHandler
+CANActivity_IRQHandler
+UART4_IRQHandler
+SSP2_IRQHandler
+LCD_IRQHandler
+GPIO_IRQHandler
+PWM0_IRQHandler
+EEPROM_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..ad00bc43c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+#include "sys_helper.h"
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit - __reserved_stack_size();
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.cpp
new file mode 100644
index 000000000..eb31c5ed9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.cpp
@@ -0,0 +1,19 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ */
+
+#include "sys_helper.h"
+
+/* This function specifies the amount of memory of the internal RAM to
+ reserve for the stack. The default implementation will reserve 0 bytes
+ which gives the normal behaviour where the stack and heap share all the
+ internal RAM.
+
+ You can override this function in your code to reserve a number of bytes
+ for the stack.
+*/
+extern "C" __attribute__((weak)) uint32_t __reserved_stack_size();
+extern "C" __attribute__((weak)) uint32_t __reserved_stack_size() {
+ return 0; // return 0 to indicate that nothing is reserved
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.h
new file mode 100644
index 000000000..4ba0770b4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.h
@@ -0,0 +1,16 @@
+#ifndef SYS_HELPER_H
+#define SYS_HELPER_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t __reserved_stack_size();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/LPC4088.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/LPC4088.ld
new file mode 100644
index 000000000..226e6baf4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/LPC4088.ld
@@ -0,0 +1,172 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x100000E8, LENGTH = (64K - 0xE8)
+
+ USB_RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+ ETH_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > USB_RAM
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > ETH_RAM
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.s
new file mode 100644
index 000000000..0377b2ba5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.s
@@ -0,0 +1,235 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x800
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 16: Watchdog Timer */
+ .long TIMER0_IRQHandler /* 17: Timer0 */
+ .long TIMER1_IRQHandler /* 18: Timer1 */
+ .long TIMER2_IRQHandler /* 19: Timer2 */
+ .long TIMER3_IRQHandler /* 20: Timer3 */
+ .long UART0_IRQHandler /* 21: UART0 */
+ .long UART1_IRQHandler /* 22: UART1 */
+ .long UART2_IRQHandler /* 23: UART2 */
+ .long UART3_IRQHandler /* 24: UART3 */
+ .long PWM1_IRQHandler /* 25: PWM1 */
+ .long I2C0_IRQHandler /* 26: I2C0 */
+ .long I2C1_IRQHandler /* 27: I2C1 */
+ .long I2C2_IRQHandler /* 28: I2C2 */
+ .long 0 /* 29: Reserved */
+ .long SSP0_IRQHandler /* 30: SSP0 */
+ .long SSP1_IRQHandler /* 31: SSP1 */
+ .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
+ .long RTC_IRQHandler /* 33: Real Time Clock */
+ .long EINT0_IRQHandler /* 34: External Interrupt 0 */
+ .long EINT1_IRQHandler /* 35: External Interrupt 1 */
+ .long EINT2_IRQHandler /* 36: External Interrupt 2 */
+ .long EINT3_IRQHandler /* 37: External Interrupt 3 */
+ .long ADC_IRQHandler /* 38: A/D Converter */
+ .long BOD_IRQHandler /* 39: Brown-Out Detect */
+ .long USB_IRQHandler /* 40: USB */
+ .long CAN_IRQHandler /* 41: CAN */
+ .long DMA_IRQHandler /* 42: General Purpose DMA */
+ .long I2S_IRQHandler /* 43: I2S */
+ .long ENET_IRQHandler /* 44: Ethernet */
+ .long MCI_IRQHandler /* 45: SD/MMC carf I/F */
+ .long MCPWM_IRQHandler /* 46: Motor Control PWM */
+ .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
+ .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
+ .long USBActivity_IRQHandler /* 49: USB Activity */
+ .long CANActivity_IRQHandler /* 50: CAN Activity */
+ .long UART4_IRQHandler /* 51: UART4 */
+ .long SSP2_IRQHandler /* 52: SSP2 */
+ .long LCD_IRQHandler /* 53: LCD */
+ .long GPIO_IRQHandler /* 54: GPIO */
+ .long PWM0_IRQHandler /* 55: PWM0 */
+ .long EEPROM_IRQHandler /* 56: EEPROM */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler TIMER0_IRQHandler
+ def_irq_default_handler TIMER1_IRQHandler
+ def_irq_default_handler TIMER2_IRQHandler
+ def_irq_default_handler TIMER3_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler UART3_IRQHandler
+ def_irq_default_handler PWM1_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+/* def_irq_default_handler SPI_IRQHandler */
+ def_irq_default_handler SSP0_IRQHandler
+ def_irq_default_handler SSP1_IRQHandler
+ def_irq_default_handler PLL0_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler EINT0_IRQHandler
+ def_irq_default_handler EINT1_IRQHandler
+ def_irq_default_handler EINT2_IRQHandler
+ def_irq_default_handler EINT3_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler USB_IRQHandler
+ def_irq_default_handler CAN_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler I2S_IRQHandler
+ def_irq_default_handler ENET_IRQHandler
+ def_irq_default_handler MCI_IRQHandler
+ def_irq_default_handler MCPWM_IRQHandler
+ def_irq_default_handler QEI_IRQHandler
+ def_irq_default_handler PLL1_IRQHandler
+ def_irq_default_handler USBActivity_IRQHandler
+ def_irq_default_handler CANActivity_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler SSP2_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler GPIO_IRQHandler
+ def_irq_default_handler PWM0_IRQHandler
+ def_irq_default_handler EEPROM_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld
new file mode 100644
index 000000000..8da20f62a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld
@@ -0,0 +1,181 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2013
+ * Generated linker script file for LPC4088
+ * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
+ * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20] on Wed Apr 17 14:50:07 CEST 2013
+ */
+
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
+ RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc64 = 0x10000000 + 0x10000;
+ __top_RamPeriph32 = 0x20000000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamPeriph32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc64
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc64 AT>MFlash512
+
+ /* BSS section for RamPeriph32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc64
+
+ /* NOINIT section for RamPeriph32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc64
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc64 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp
new file mode 100644
index 000000000..122f8abc8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp
@@ -0,0 +1,438 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
+//
+// LPC407x_8x Microcontroller Startup code for use with Red Suite
+//
+// Version : 120624
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//#if defined (__USE_CMSIS)
+#include "LPC407x_8x_177x_8x.h"
+//#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC17
+ WDT_IRQHandler, // 16, 0x40 - WDT
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3
+ UART0_IRQHandler, // 21, 0x54 - UART0
+ UART1_IRQHandler, // 22, 0x58 - UART1
+ UART2_IRQHandler, // 23, 0x5c - UART2
+ UART3_IRQHandler, // 24, 0x60 - UART3
+ PWM1_IRQHandler, // 25, 0x64 - PWM1
+ I2C0_IRQHandler, // 26, 0x68 - I2C0
+ I2C1_IRQHandler, // 27, 0x6c - I2C1
+ I2C2_IRQHandler, // 28, 0x70 - I2C2
+ IntDefaultHandler, // 29, Not used
+ SSP0_IRQHandler, // 30, 0x78 - SSP0
+ SSP1_IRQHandler, // 31, 0x7c - SSP1
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
+ RTC_IRQHandler, // 33, 0x84 - RTC
+ EINT0_IRQHandler, // 34, 0x88 - EINT0
+ EINT1_IRQHandler, // 35, 0x8c - EINT1
+ EINT2_IRQHandler, // 36, 0x90 - EINT2
+ EINT3_IRQHandler, // 37, 0x94 - EINT3
+ ADC_IRQHandler, // 38, 0x98 - ADC
+ BOD_IRQHandler, // 39, 0x9c - BOD
+ USB_IRQHandler, // 40, 0xA0 - USB
+ CAN_IRQHandler, // 41, 0xa4 - CAN
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA
+ I2S_IRQHandler, // 43, 0xac - I2S
+ ENET_IRQHandler, // 44, 0xb0 - Ethernet
+ MCI_IRQHandler, // 45, 0xb4 - SD/MMC card I/F
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
+ USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
+ CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
+ UART4_IRQHandler, // 51, 0xcc - UART4
+
+ SSP2_IRQHandler, // 52, 0xd0 - SSP2
+ LCD_IRQHandler, // 53, 0xd4 - LCD
+ GPIO_IRQHandler, // 54, 0xd8 - GPIO
+ PWM0_IRQHandler, // 55, 0xdc - PWM0
+ EEPROM_IRQHandler, // 56, 0xe0 - EEPROM
+
+};
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+
+extern "C" void software_init_hook(void) __attribute__((weak));
+
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+/*
+ * Code to enable the Cortex-M4 FPU only included
+ * if appropriate build options have been selected.
+ * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ */
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+
+//#ifdef __USE_CMSIS
+ SystemInit();
+//#endif
+ if (software_init_hook) // give control to the RTOS
+ software_init_hook(); // this will also call __libc_init_array
+ else {
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+ }
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{
+ while(1)
+ {
+ }
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf
new file mode 100644
index 000000000..97484feaa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf
@@ -0,0 +1,42 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000E7;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000E8;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFDF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__ = 0x4000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define symbol __RAM1_start__ = 0x20000000;
+define symbol __RAM1_end__ = 0x20007FFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
+place in RAM1_region { section .sram };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s
new file mode 100644
index 000000000..9fc5ec6fb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.s
@@ -0,0 +1,256 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0xEFFFF39E ; Reserved- vector sum
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD 0 ; 29: reserved, not for SPIFI anymore
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD MCI_IRQHandler ; 45: SD/MMC card I/F
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+ DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
+ DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
+ DCD UART4_IRQHandler ; 51: UART4
+ DCD SSP2_IRQHandler ; 52: SSP2
+ DCD LCD_IRQHandler ; 53: LCD
+ DCD GPIO_IRQHandler ; 54: GPIO
+ DCD PWM0_IRQHandler ; 55: PWM0
+ DCD EEPROM_IRQHandler ; 56: EEPROM
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK TIMER0_IRQHandler
+ PUBWEAK TIMER1_IRQHandler
+ PUBWEAK TIMER2_IRQHandler
+ PUBWEAK TIMER3_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART3_IRQHandler
+ PUBWEAK PWM1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK I2C2_IRQHandler
+;SPIFI_IRQHandler ;not used
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK PLL0_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK EINT0_IRQHandler
+ PUBWEAK EINT1_IRQHandler
+ PUBWEAK EINT2_IRQHandler
+ PUBWEAK EINT3_IRQHandler
+ PUBWEAK ADC_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK USB_IRQHandler
+ PUBWEAK CAN_IRQHandler
+ PUBWEAK DMA_IRQHandler
+ PUBWEAK I2S_IRQHandler
+ PUBWEAK ENET_IRQHandler
+ PUBWEAK MCI_IRQHandler
+ PUBWEAK MCPWM_IRQHandler
+ PUBWEAK QEI_IRQHandler
+ PUBWEAK PLL1_IRQHandler
+ PUBWEAK USBActivity_IRQHandler
+ PUBWEAK CANActivity_IRQHandler
+ PUBWEAK UART4_IRQHandler
+ PUBWEAK SSP2_IRQHandler
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK GPIO_IRQHandler
+ PUBWEAK PWM0_IRQHandler
+ PUBWEAK EEPROM_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+;SPIFI_IRQHandler ;not used
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+MCI_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+USBActivity_IRQHandler
+CANActivity_IRQHandler
+UART4_IRQHandler
+SSP2_IRQHandler
+LCD_IRQHandler
+GPIO_IRQHandler
+PWM0_IRQHandler
+EEPROM_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h
new file mode 100644
index 000000000..e4a5ba35b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC407x_8x specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC407x_8x_177x_8x.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c
new file mode 100644
index 000000000..c057a64d9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h
new file mode 100644
index 000000000..4f773ecdf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c
new file mode 100644
index 000000000..fbfe88bb2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c
@@ -0,0 +1,571 @@
+/**********************************************************************
+* $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
+*//**
+* @file system_LPC407x_8x_177x_8x.c
+* @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
+* for the NXP LPC407x_8x_177x_8x Device Series
+*
+* ARM Limited (ARM) is supplying this software for use with
+* Cortex-M processor based microcontrollers. This file can be
+* freely distributed within development tools that are supporting
+* such ARM based processors.
+*
+* @version 1.2
+* @date 20. June. 2012
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2012, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#include <stdint.h>
+#include "LPC407x_8x_177x_8x.h"
+#include "system_LPC407x_8x_177x_8x.h"
+
+#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS - address 0x400F C1A0)
+// <o1.0> EMC Shift Control Bit
+// <i> Controls how addresses are output on the EMC address pins for static memories
+// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
+// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
+//
+// <o1.1> EMC Reset Disable Bit
+// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
+// <i> If 1, EMC is still retained its state through a warm reset
+// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
+// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
+//
+// <o1.2> EMC Burst Control
+// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
+// <0=> Burst enabled (Bit 2 is 0)
+// <1=> Bust disbled (Bit 2 is 1)
+//
+// <o1.3> MCIPWR Active Level
+// <i> Selects the active level for the SD card interface signal SD_PWR
+// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
+// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
+//
+// <o1.4> Main Oscillator Range Select
+// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
+// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
+//
+// <o1.5> Main Oscillator enable
+// <i> 0 (zero) means disabled, 1 means enable
+//
+// <o1.6> Main Oscillator status (Read-Only)
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
+// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
+// <0=> Internal RC oscillator (Bit 0 is 0)
+// <1=> Main oscillator (Bit 0 is 1)
+// </h>
+//
+// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
+// <i> F_in is in the range of 1 MHz to 25 MHz
+// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
+// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
+//
+// <o4.0..4> MSEL: PLL Multiplier Value
+// <i> M Value
+// <1-32><#-1>
+//
+// <o4.5..6> PSEL: PLL Divider Value
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </e>
+//
+// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
+// <i> F_in is in the range of 1 MHz to 25 MHz
+// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
+// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
+//
+// <o6.0..4> MSEL: PLL Multiplier Value
+// <i> M Value
+// <1-32><#-1>
+//
+// <o6.5..6> PSEL: PLL Divider Value
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </e>
+//
+// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
+// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
+// <i> 0: The divider is turned off. No clock will be provided to the CPU
+// <i> n: The input clock is divided by n to produce the CPU clock
+// <0-31>
+//
+// <o7.8> CCLKSEL: Select the input to the divider of CPU clock
+// <0=> sysclk clock is used
+// <1=> Main PLL0 clock is used
+// </h>
+//
+// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
+// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
+// <0=> Divider is off and no clock provides to USB subsystem
+// <4=> Divider value is 4 (The source clock is divided by 4)
+// <6=> Divider value is 6 (The source clock is divided by 6)
+//
+// <o8.8..9> USBSEL: Select the source for USB clock divider
+// <i> When CPU clock is selected, the USB can be accessed
+// <i> by software but cannot perform USB functions
+// <0=> sysclk clock (the clock input to PLL0)
+// <1=> The clock output from PLL0
+// <2=> The clock output from PLL1
+// </h>
+//
+// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
+// <o9.0> EMCDIV: Set the divider for EMC clock
+// <0=> Divider value is 1
+// <1=> Divider value is 2 (EMC clock is equal a half of input clock)
+// </h>
+//
+// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
+// <o10.0..4> PCLKDIV: APB Peripheral clock divider
+// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
+// <i> n: The input clock is divided by n to produce the APB peripheral clock
+// <0-31>
+// </h>
+//
+// <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
+// <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
+// <i> 0: The divider is turned off. No clock will be provided to the SPIFI
+// <i> n: The input clock is divided by n to produce the SPIFI clock
+// <0-31>
+//
+// <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
+// <0=> sysclk clock (the clock input to PLL0)
+// <1=> The clock output from PLL0
+// <2=> The clock output from PLL1
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
+// <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
+// <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
+// <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
+// <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
+// <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
+// <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
+// <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
+// <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
+// <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
+// <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
+// <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
+// <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
+// <o12.12> PCADC: A/D converter power/clock enable (bit 12)
+// <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
+// <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
+// <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
+// <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
+// <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
+// <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
+// <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
+// <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
+// <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
+// <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
+// <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
+// <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
+// <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
+// <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
+// <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
+// <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
+// <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
+// <o12.31> PCUSB: USB interface power/clock enable (bit 31)
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
+// <0=> CPU clock
+// <1=> Main Oscillator
+// <2=> Internal RC Oscillator
+// <3=> USB clock
+// <4=> RTC Oscillator
+// <5=> unused
+// <6=> Watchdog Oscillator
+//
+// <o13.4..7> CLKOUTDIV: Output Clock Divider
+// <1-16><#-1>
+//
+// <o13.8> CLKOUT_EN: CLKOUT enable
+// </h>
+//
+// </e>
+*/
+
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00000009
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKSEL_Val 0x00000101
+#define USBCLKSEL_Val 0x00000201
+#define EMCCLKSEL_Val 0x00000001
+#define PCLKSEL_Val 0x00000002
+#define SPIFICLKSEL_Val 0x00000002
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000100
+
+#ifdef CORE_M4
+#define LPC_CPACR 0xE000ED88
+
+#define SCB_MVFR0 0xE000EF40
+#define SCB_MVFR0_RESET 0x10110021
+
+#define SCB_MVFR1 0xE000EF44
+#define SCB_MVFR1_RESET 0x11000011
+#endif
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00005000
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
+ #error "CCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
+ #error "USBCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
+ #error "EMCCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
+ #error "PCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #warning "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+/* pll_out_clk = F_cco / (2 � P)
+ F_cco = pll_in_clk � M � 2 � P */
+#define __M ((PLL0CFG_Val & 0x1F) + 1)
+#define __PLL0_CLK(__F_IN) (__F_IN * __M)
+#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
+#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
+#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
+
+/* Determine core clock frequency according to settings */
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
+ #error "Main Oscillator is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
+ #error "Main PLL is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
+ #endif
+ #else /* cclk = pll_clk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
+ #endif
+ #endif
+
+#else
+ #define __CORE_CLK (IRC_OSC)
+ #define __PER_CLK (IRC_OSC)
+ #define __EMC_CLK (__CORE_CLK)
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
+uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
+uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
+ be updated after call SystemCoreClockUpdate, should be 48MHz*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ else { /* cclk = pll_clk */
+ if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
+ uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
+ uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
+ SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
+ PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
+ EMCClock = SystemCoreClock / emc_div;
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
+ uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
+ uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
+ SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
+ PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
+ EMCClock = SystemCoreClock / emc_div;
+ }
+ }
+ }
+ }
+ /* ---update USBClock------------------*/
+ if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
+ {
+ switch (LPC_SC->USBCLKSEL & 0x1F)
+ {
+ case 0:
+ USBClock = 0; //no clock will be provided to the USB subsystem
+ break;
+ case 4:
+ case 6:
+ {
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
+ USBClock = OSC_CLK * mul / usb_div;
+ else //pll_clk_in = irc_clk
+ USBClock = IRC_OSC * mul / usb_div;
+ }
+ break;
+ default:
+ USBClock = 0; /* this should never happen! */
+ }
+ }
+ else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
+ {
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
+ else //pll1_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
+ }
+ else
+ USBClock = 0; /* this should never happen! */
+}
+
+ /* Determine clock frequency according to clock register values */
+
+#ifdef CORE_M4
+
+void fpu_init(void)
+{
+ // from arm trm manual:
+// ; CPACR is located at address 0xE000ED88
+// LDR.W R0, =0xE000ED88
+// ; Read CPACR
+// LDR R1, [R0]
+// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+// ORR R1, R1, #(0xF << 20)
+// ; Write back the modified value to the CPACR
+// STR R1, [R0]
+
+
+ volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
+ volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
+ volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
+ volatile uint32_t Cpacr;
+ volatile uint32_t Mvfr0;
+ volatile uint32_t Mvfr1;
+ char vfpPresent = 0;
+
+ Mvfr0 = *regMvfr0;
+ Mvfr1 = *regMvfr1;
+
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+ if(vfpPresent)
+ {
+ Cpacr = *regCpacr;
+ Cpacr |= (0xF << 20);
+ *regCpacr = Cpacr; // enable CP10 and CP11 for full access
+ }
+
+}
+#endif
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#ifndef __CODE_RED
+#ifdef CORE_M4
+fpu_init();
+#endif
+#endif
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+#endif
+
+ LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
+ LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
+ LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
+ LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
+ LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+ LPC_SC->PBOOST |= 0x03; /* Power Boost control */
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
+#endif
+#ifndef __CODE_RED
+#ifdef __RAM_MODE__
+ SCB->VTOR = 0x10000000 & 0x3FFFFF80;
+#else
+ SCB->VTOR = 0x00000000 & 0x3FFFFF80;
+#endif
+#endif
+ SystemCoreClockUpdate();
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.h
new file mode 100644
index 000000000..ddaeaae6b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.h
@@ -0,0 +1,89 @@
+/**********************************************************************
+* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
+*//**
+* @file system_LPC407x_8x_177x_8x.h
+* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+* for the NXP LPC Device Series
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
+#define __SYSTEM_LPC407x_8x_177x_8x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
+extern uint32_t EMCClock; /*!< EMC Clock */
+extern uint32_t USBClock; /*!< USB Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
+#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
+#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
+
+
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h
new file mode 100644
index 000000000..2b8072914
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h
@@ -0,0 +1,2113 @@
+/*
+ * LPC43xx/LPC18xx MCU header
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ *
+ * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
+ * 05/15/13 Micromint USA <support@micromint.com>
+ */
+
+#ifndef __LPC43XX_H
+#define __LPC43XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Treat __CORE_Mx as CORE_Mx */
+#if defined(__CORTEX_M0) && !defined(CORE_M0)
+ #define CORE_M0
+#endif
+#if defined(__CORTEX_M3) && !defined(CORE_M3)
+ #define CORE_M3
+#endif
+/* Default to M4 core if no core explicitly declared */
+#if !defined(CORE_M0) && !defined(CORE_M3)
+ #define CORE_M4
+#endif
+
+/* Define LPC18XX or LPC43XX according to core type */
+#if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
+ #define __LPC43XX__
+#endif
+#if defined(CORE_M3) && !defined(__LPC18XX__)
+ #define __LPC18XX__
+#endif
+
+/* Start of section using anonymous unions */
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+ #pragma diag_suppress 2525
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__IAR_SYSTEMS_ICC__)
+ //#pragma push // FIXME not usable for IAR
+ #pragma language=extended
+#else /* defined(__GNUC__) and others */
+ /* Assume anonymous unions are enabled by default */
+#endif
+
+#if defined(CORE_M4)
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M4 Core) Cortex CMSIS definitions
+ */
+
+#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
+} IRQn_Type;
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+
+#elif defined(CORE_M3)
+/* ---------------------------------------------------------------------------
+ * LPC18xx (M3 Core) Cortex CMSIS definitions
+ */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC18XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC18xx peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ RESERVED0_IRQn = 1,
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ RESERVED3_IRQn = 20,
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ RESERVED5_IRQn = 31,
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
+} IRQn_Type;
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+
+#elif defined(CORE_M0)
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) Cortex CMSIS definitions
+ */
+
+#define __MPU_PRESENT 0 /* MPU present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0_M4CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA r */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ GINT1_IRQn = 13,/* 13 GINT1 */
+ PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
+ SGPIO_INT_IRQn = 19,/* 19 SGPIO */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
+ EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
+ C_CAN0_IRQn = 29,/* 29 C_CAN0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED2_IRQn = 30,
+ RESERVED3_IRQn = 31,
+} IRQn_Type;
+
+#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0, CORE_M3 or CORE_M4
+#endif
+
+#include "system_LPC43xx.h"
+
+/* ---------------------------------------------------------------------------
+ * State Configurable Timer register block structure
+ */
+#define LPC_SCT_BASE 0x40000000
+#define CONFIG_SCT_nEV (16) /* Number of events */
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (16) /* Number of outputs */
+
+typedef struct {
+ __IO uint32_t CONFIG; /* Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* Low control register */
+ __IO uint16_t CTRL_H; /* High control register */
+ };
+
+ };
+
+ __IO uint16_t LIMIT_L; /* limit register for counter L */
+ __IO uint16_t LIMIT_H; /* limit register for counter H */
+ __IO uint16_t HALT_L; /* halt register for counter L */
+ __IO uint16_t HALT_H; /* halt register for counter H */
+ __IO uint16_t STOP_L; /* stop register for counter L */
+ __IO uint16_t STOP_H; /* stop register for counter H */
+ __IO uint16_t START_L; /* start register for counter L */
+ __IO uint16_t START_H; /* start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* counter register for counter L */
+ __IO uint16_t COUNT_H; /* counter register for counter H */
+ };
+
+ };
+
+ __IO uint16_t STATE_L; /* state register for counter L */
+ __IO uint16_t STATE_H; /* state register for counter H */
+ __I uint32_t INPUT; /* input register */
+ __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
+ __IO uint32_t RES; /* conflict resolution register */
+ __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
+ __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
+ uint32_t RESERVED2[35];
+ __IO uint32_t EVEN; /* event enable register */
+ __IO uint32_t EVFLAG; /* event flag register */
+ __IO uint32_t CONEN; /* conflict enable register */
+ __IO uint32_t CONFLAG; /* conflict flag register */
+ union {
+ __IO union { /* ... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+
+ } MATCH[CONFIG_SCT_nRG];
+
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to L value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+
+ } CAP[CONFIG_SCT_nRG];
+
+ };
+
+ uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+
+ uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+
+ uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+
+ } MATCHREL[CONFIG_SCT_nRG];
+
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+
+ } CAPCTRL[CONFIG_SCT_nRG];
+
+ };
+
+ uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+
+ uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+
+ uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+} LPC_SCT_T;
+
+/* Macro defines for SCT configuration register */
+#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
+#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
+
+#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
+#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
+#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
+#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
+
+#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
+#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
+
+/* Macro defines for SCT control register */
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+
+#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
+#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
+#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
+#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
+#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
+
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
+#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
+#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
+#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
+#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
+
+/* Macro defines for SCT Conflict resolution register */
+#define SCT_RES_NOCHANGE (0)
+#define SCT_RES_SET_OUTPUT (1)
+#define SCT_RES_CLEAR_OUTPUT (2)
+#define SCT_RES_TOGGLE_OUTPUT (3)
+
+/* ---------------------------------------------------------------------------
+ * GPDMA Channel register block structure
+ */
+#define LPC_GPDMA_BASE 0x40002000
+
+typedef struct {
+ __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
+ __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
+ __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
+ __IO uint32_t CONTROL; /* DMA Channel Control Register */
+ __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
+ __I uint32_t RESERVED1[3];
+} LPC_GPDMA_CH_T;
+
+#define GPDMA_CHANNELS 8
+
+/* ---------------------------------------------------------------------------
+ * GPDMA register block
+ */
+typedef struct { /* GPDMA Structure */
+ __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
+ __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
+ __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
+ __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
+ __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
+ __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
+ __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
+ __IO uint32_t CONFIG; /* DMA Configuration Register */
+ __IO uint32_t SYNC; /* DMA Synchronization Register */
+ __I uint32_t RESERVED0[50];
+ LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
+} LPC_GPDMA_T;
+
+/* ---------------------------------------------------------------------------
+ * SPIFI register block structure
+ */
+#define LPC_SPIFI_BASE 0x40003000
+
+typedef struct { /* SPIFI Structure */
+ __IO uint32_t CTRL; /* Control register */
+ __IO uint32_t CMD; /* Command register */
+ __IO uint32_t ADDR; /* Address register */
+ __IO uint32_t IDATA; /* Intermediate data register */
+ __IO uint32_t CLIMIT; /* Cache limit register */
+ union {
+ __IO uint32_t DATA;
+ __IO uint16_t DATA_HWORD;
+ __IO uint8_t DATA_BYTE;
+ }; /* Data register */
+ __IO uint32_t MCMD; /* Memory command register */
+ __IO uint32_t STAT; /* Status register */
+} LPC_SPIFI_T;
+
+/* ---------------------------------------------------------------------------
+ * SD/MMC & SDIO register block structure
+ */
+#define LPC_SDMMC_BASE 0x40004000
+
+typedef struct { /* SDMMC Structure */
+ __IO uint32_t CTRL; /* Control Register */
+ __IO uint32_t PWREN; /* Power Enable Register */
+ __IO uint32_t CLKDIV; /* Clock Divider Register */
+ __IO uint32_t CLKSRC; /* SD Clock Source Register */
+ __IO uint32_t CLKENA; /* Clock Enable Register */
+ __IO uint32_t TMOUT; /* Timeout Register */
+ __IO uint32_t CTYPE; /* Card Type Register */
+ __IO uint32_t BLKSIZ; /* Block Size Register */
+ __IO uint32_t BYTCNT; /* Byte Count Register */
+ __IO uint32_t INTMASK; /* Interrupt Mask Register */
+ __IO uint32_t CMDARG; /* Command Argument Register */
+ __IO uint32_t CMD; /* Command Register */
+ __I uint32_t RESP0; /* Response Register 0 */
+ __I uint32_t RESP1; /* Response Register 1 */
+ __I uint32_t RESP2; /* Response Register 2 */
+ __I uint32_t RESP3; /* Response Register 3 */
+ __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
+ __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
+ __I uint32_t STATUS; /* Status Register */
+ __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
+ __I uint32_t CDETECT; /* Card Detect Register */
+ __I uint32_t WRTPRT; /* Write Protect Register */
+ __IO uint32_t GPIO; /* General Purpose Input/Output Register */
+ __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
+ __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
+ __IO uint32_t DEBNCE; /* Debounce Count Register */
+ __IO uint32_t USRID; /* User ID Register */
+ __I uint32_t VERID; /* Version ID Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UHS_REG; /* UHS-1 Register */
+ __IO uint32_t RST_N; /* Hardware Reset */
+ __I uint32_t RESERVED1;
+ __IO uint32_t BMOD; /* Bus Mode Register */
+ __O uint32_t PLDMND; /* Poll Demand Register */
+ __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
+ __IO uint32_t IDSTS; /* Internal DMAC Status Register */
+ __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
+ __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
+ __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
+} LPC_SDMMC_T;
+
+/* ---------------------------------------------------------------------------
+ * External Memory Controller (EMC) register block structure
+ */
+#define LPC_EMC_BASE 0x40005000
+
+typedef struct { /* EMC Structure */
+ __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
+ __I uint32_t STATUS; /* Provides EMC status information. */
+ __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
+ __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
+ __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
+ __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
+ __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
+ __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
+ __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
+ __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
+ __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
+ __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
+ __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
+ __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
+ __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
+ __I uint32_t RESERVED2[9];
+ __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED7[38];
+ __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED8;
+ __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED9;
+ __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED10;
+ __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
+} LPC_EMC_T;
+
+/* ---------------------------------------------------------------------------
+ * USB High-Speed register block structure
+ */
+#define LPC_USB0_BASE 0x40006000
+#define LPC_USB1_BASE 0x40007000
+
+typedef struct { /* USB Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /* Capability register length */
+ __I uint32_t HCSPARAMS; /* Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /* Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /* Device interface version number */
+ __I uint32_t RESERVED2[7];
+ union {
+ __IO uint32_t USBCMD_H; /* USB command (host mode) */
+ __IO uint32_t USBCMD_D; /* USB command (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBSTS_H; /* USB status (host mode) */
+ __IO uint32_t USBSTS_D; /* USB status (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
+ };
+
+ union {
+ __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
+ __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
+ };
+
+ __I uint32_t RESERVED3;
+ union {
+ __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
+ __IO uint32_t DEVICEADDR; /* USB device address */
+ };
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
+ __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
+ };
+
+ __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /* Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
+ __IO uint32_t BINTERVAL; /* Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+ union {
+ __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
+ };
+
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t OTGSC; /* OTG status and control */
+ union {
+ __IO uint32_t USBMODE_H; /* USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /* USB mode (device mode) */
+ };
+
+ __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /* Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
+ __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
+} LPC_USBHS_T;
+
+/* ---------------------------------------------------------------------------
+ * LCD Controller register block structure
+ */
+#define LPC_LCD_BASE 0x40008000
+
+typedef struct { /* LCD Structure */
+ __IO uint32_t TIMH; /* Horizontal Timing Control register */
+ __IO uint32_t TIMV; /* Vertical Timing Control register */
+ __IO uint32_t POL; /* Clock and Signal Polarity Control register */
+ __IO uint32_t LE; /* Line End Control register */
+ __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
+ __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
+ __IO uint32_t CTRL; /* LCD Control register */
+ __IO uint32_t INTMSK; /* Interrupt Mask register */
+ __I uint32_t INTRAW; /* Raw Interrupt Status register */
+ __I uint32_t INTSTAT; /* Masked Interrupt Status register */
+ __O uint32_t INTCLR; /* Interrupt Clear register */
+ __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
+ __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
+ __I uint32_t RESERVED0[115];
+ __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
+ __I uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
+ __IO uint32_t CRSR_CTRL; /* Cursor Control register */
+ __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
+ __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
+ __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
+ __IO uint32_t CRSR_XY; /* Cursor XY Position register */
+ __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
+ __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
+ __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
+ __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
+} LPC_LCD_T;
+
+/* ---------------------------------------------------------------------------
+ * EEPROM register block structure
+ */
+#define LPC_EEPROM_BASE 0x4000E000
+
+typedef struct { /* EEPROM Structure */
+ __IO uint32_t CMD; /* EEPROM command register */
+ uint32_t RESERVED0;
+ __IO uint32_t RWSTATE; /* EEPROM read wait state register */
+ __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
+ __IO uint32_t WSTATE; /* EEPROM wait state register */
+ __IO uint32_t CLKDIV; /* EEPROM clock divider register */
+ __IO uint32_t PWRDWN; /* EEPROM power-down register */
+ uint32_t RESERVED2[1007];
+ __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
+ __O uint32_t INTENSET; /* EEPROM interrupt enable set */
+ __I uint32_t INTSTAT; /* EEPROM interrupt status */
+ __I uint32_t INTEN; /* EEPROM interrupt enable */
+ __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
+ __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
+} LPC_EEPROM_T;
+
+/* ---------------------------------------------------------------------------
+ * 10/100 MII & RMII Ethernet with timestamping register block structure
+ */
+#define LPC_ETHERNET_BASE 0x40010000
+
+typedef struct { /* ETHERNET Structure */
+ __IO uint32_t MAC_CONFIG; /* MAC configuration register */
+ __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
+ __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
+ __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
+ __IO uint32_t MAC_MII_ADDR; /* MII address register */
+ __IO uint32_t MAC_MII_DATA; /* MII data register */
+ __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
+ __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
+ __I uint32_t RESERVED0;
+ __I uint32_t MAC_DEBUG; /* Debug register */
+ __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
+ __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t MAC_INTR; /* Interrupt status register */
+ __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
+ __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
+ __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
+ __I uint32_t RESERVED2[430];
+ __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
+ __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
+ __I uint32_t SECONDS; /* System time seconds register */
+ __I uint32_t NANOSECONDS; /* System time nanoseconds register */
+ __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
+ __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
+ __IO uint32_t ADDEND; /* Time stamp addend register */
+ __IO uint32_t TARGETSECONDS; /* Target time seconds register */
+ __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
+ __IO uint32_t HIGHWORD; /* System time higher word seconds register */
+ __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
+ __IO uint32_t PPSCTRL; /* PPS control register */
+ __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
+ __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
+ __I uint32_t RESERVED3[562];
+ __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
+ __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
+ __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
+ __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
+ __IO uint32_t DMA_STAT; /* Status register */
+ __IO uint32_t DMA_OP_MODE; /* Operation mode register */
+ __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
+ __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
+ __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
+ __I uint32_t RESERVED4[8];
+ __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
+ __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
+ __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
+ __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
+} LPC_ENET_T;
+
+/* ---------------------------------------------------------------------------
+ * Alarm Timer register block structure
+ */
+#define LPC_ATIMER_BASE 0x40040000
+
+typedef struct { /* ATIMER Structure */
+ __IO uint32_t DOWNCOUNTER; /* Downcounter register */
+ __IO uint32_t PRESET; /* Preset value register */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Interrupt clear enable register */
+ __O uint32_t SET_EN; /* Interrupt set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
+} LPC_ATIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * Register File register block structure
+ */
+#define LPC_REGFILE_BASE 0x40041000
+
+typedef struct {
+ __IO uint32_t REGFILE[64]; /* General purpose storage register */
+} LPC_REGFILE_T;
+
+/* ---------------------------------------------------------------------------
+ * Power Management Controller register block structure
+ */
+#define LPC_PMC_BASE 0x40042000
+
+typedef struct { /* PMC Structure */
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
+} LPC_PMC_T;
+
+/* ---------------------------------------------------------------------------
+ * CREG Register Block
+ */
+#define LPC_CREG_BASE 0x40043000
+
+typedef struct { /* CREG Structure */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED2[5];
+#else
+ __I uint32_t RESERVED2;
+ __I uint32_t CREG1; /* Configuration Register 1 */
+ __I uint32_t CREG2; /* Configuration Register 2 */
+ __I uint32_t CREG3; /* Configuration Register 3 */
+ __I uint32_t CREG4; /* Configuration Register 4 */
+#endif
+ __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
+ __IO uint32_t DMAMUX; /* DMA muxing control */
+ __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
+ __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
+ __IO uint32_t ETBCFG; /* ETB RAM configuration */
+ __IO uint32_t CREG6; /* Chip configuration register 6. */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED4[52];
+#else
+ __IO uint32_t M4TXEVENT; /* M4 IPC event register */
+ __I uint32_t RESERVED4[51];
+#endif
+ __I uint32_t CHIPID; /* Part ID */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED5[191];
+#else
+ __I uint32_t RESERVED5[127];
+ __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
+ __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
+ __I uint32_t RESERVED6[62];
+#endif
+ __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
+ __I uint32_t RESERVED7[63];
+ __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
+} LPC_CREG_T;
+
+/* ---------------------------------------------------------------------------
+ * Event Router register structure
+ */
+#define LPC_EVRT_BASE 0x40044000
+
+typedef struct { /* EVENTROUTER Structure */
+ __IO uint32_t HILO; /* Level configuration register */
+ __IO uint32_t EDGE; /* Edge configuration */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Event clear enable register */
+ __O uint32_t SET_EN; /* Event set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
+} LPC_EVRT_T;
+
+/* ---------------------------------------------------------------------------
+ * Real Time Clock register block structure
+ */
+#define LPC_RTC_BASE 0x40046000
+#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
+
+typedef enum RTC_TIMEINDEX {
+ RTC_TIMETYPE_SECOND, /* Second */
+ RTC_TIMETYPE_MINUTE, /* Month */
+ RTC_TIMETYPE_HOUR, /* Hour */
+ RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
+ RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
+ RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
+ RTC_TIMETYPE_MONTH, /* Month */
+ RTC_TIMETYPE_YEAR, /* Year */
+ RTC_TIMETYPE_LAST
+} RTC_TIMEINDEX_T;
+
+#if RTC_EV_SUPPORT
+typedef enum LPC_RTC_EV_CHANNEL {
+ RTC_EV_CHANNEL_1 = 0,
+ RTC_EV_CHANNEL_2,
+ RTC_EV_CHANNEL_3,
+ RTC_EV_CHANNEL_NUM,
+} LPC_RTC_EV_CHANNEL_T;
+#endif /*RTC_EV_SUPPORT*/
+
+typedef struct { /* RTC Structure */
+ __IO uint32_t ILR; /* Interrupt Location Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CCR; /* Clock Control Register */
+ __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
+ __IO uint32_t AMR; /* Alarm Mask Register */
+ __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
+ __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
+ __IO uint32_t CALIBRATION; /* Calibration Value Register */
+ __I uint32_t RESERVED1[7];
+ __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
+#if RTC_EV_SUPPORT
+ __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
+ __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
+ __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
+ __I uint32_t RESERVED2;
+ __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
+ __I uint32_t RESERVED3;
+ __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
+#endif /*RTC_EV_SUPPORT*/
+} LPC_RTC_T;
+
+/* ---------------------------------------------------------------------------
+ * LPC18XX/43XX CGU register block structure
+ */
+#define LPC_CGU_BASE 0x40050000
+#define LPC_CCU1_BASE 0x40051000
+#define LPC_CCU2_BASE 0x40052000
+/*
+ * Input clocks for the CGU and can come from both external (crystal) and
+ * internal (PLL) sources. Can be routed to the base clocks.
+ */
+typedef enum CGU_CLKIN {
+ CLKIN_32K, /* External 32KHz input */
+ CLKIN_IRC, /* Internal IRC (12MHz) input */
+ CLKIN_ENET_RX, /* External ENET_RX pin input */
+ CLKIN_ENET_TX, /* External ENET_TX pin input */
+ CLKIN_CLKIN, /* External GPCLKIN pin input */
+ CLKIN_RESERVED1,
+ CLKIN_CRYSTAL, /* External (main) crystal pin input */
+ CLKIN_USBPLL, /* Internal USB PLL input */
+ CLKIN_AUDIOPLL, /* Internal Audio PLL input */
+ CLKIN_MAINPLL, /* Internal Main PLL input */
+ CLKIN_RESERVED2,
+ CLKIN_RESERVED3,
+ CLKIN_IDIVA, /* Internal divider A input */
+ CLKIN_IDIVB, /* Internal divider B input */
+ CLKIN_IDIVC, /* Internal divider C input */
+ CLKIN_IDIVD, /* Internal divider D input */
+ CLKIN_IDIVE, /* Internal divider E input */
+ CLKINPUT_PD /* External 32KHz input */
+} CGU_CLKIN_T;
+
+#define CLKIN_PLL0USB CLKIN_USBPLL
+#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
+#define CLKIN_PLL1 CLKIN_MAINPLL
+
+/*
+ * CGU base clocks are clocks that are associated with a single input clock
+ * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
+ * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
+ * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
+ * CLK_PERIPH_SGPIO periphral clocks.
+ */
+typedef enum CGU_BASE_CLK {
+ CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
+ CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_PERIPH, /* Base clock for SGPIO */
+#else
+ CLK_BASE_RESERVED1,
+#endif
+ CLK_BASE_USB1, /* Base USB clock for USB1 */
+ CLK_BASE_MX, /* Base clock for CPU core */
+ CLK_BASE_SPIFI, /* Base clock for SPIFI */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_SPI, /* Base clock for SPI */
+#else
+ CLK_BASE_RESERVED2,
+#endif
+ CLK_BASE_PHY_RX, /* Base clock for PHY RX */
+ CLK_BASE_PHY_TX, /* Base clock for PHY TX */
+ CLK_BASE_APB1, /* Base clock for APB1 group */
+ CLK_BASE_APB3, /* Base clock for APB3 group */
+ CLK_BASE_LCD, /* Base clock for LCD pixel clock */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_VADC, /* Base clock for VADC */
+#else
+ CLK_BASE_RESERVED3,
+#endif
+ CLK_BASE_SDIO, /* Base clock for SDIO */
+ CLK_BASE_SSP0, /* Base clock for SSP0 */
+ CLK_BASE_SSP1, /* Base clock for SSP1 */
+ CLK_BASE_UART0, /* Base clock for UART0 */
+ CLK_BASE_UART1, /* Base clock for UART1 */
+ CLK_BASE_UART2, /* Base clock for UART2 */
+ CLK_BASE_UART3, /* Base clock for UART3 */
+ CLK_BASE_OUT, /* Base clock for CLKOUT pin */
+ CLK_BASE_RESERVED4,
+ CLK_BASE_RESERVED5,
+ CLK_BASE_RESERVED6,
+ CLK_BASE_RESERVED7,
+ CLK_BASE_APLL, /* Base clock for audio PLL */
+ CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
+ CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
+ CLK_BASE_LAST,
+ CLK_BASE_NONE = CLK_BASE_LAST
+} CGU_BASE_CLK_T;
+
+/*
+ * CGU dividers provide an extra clock state where a specific clock can be
+ * divided before being routed to a peripheral group. A divider accepts an
+ * input clock and then divides it. To use the divided clock for a base clock
+ * group, use the divider as the input clock for the base clock (for example,
+ * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
+ */
+typedef enum CGU_IDIV {
+ CLK_IDIV_A, /* CGU clock divider A */
+ CLK_IDIV_B, /* CGU clock divider B */
+ CLK_IDIV_C, /* CGU clock divider A */
+ CLK_IDIV_D, /* CGU clock divider D */
+ CLK_IDIV_E, /* CGU clock divider E */
+ CLK_IDIV_LAST
+} CGU_IDIV_T;
+
+/*
+ * Peripheral clocks are individual clocks routed to peripherals. Although
+ * multiple peripherals may share a same base clock, each peripheral's clock
+ * can be enabled or disabled individually. Some peripheral clocks also have
+ * additional dividers associated with them.
+ */
+typedef enum CCU_CLK {
+ /* CCU1 clocks */
+ CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
+ CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
+ CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
+ CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
+ CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
+ CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
+ CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
+ RESERVED_ALIGN = CLK_MX_MXCORE + 3,
+ CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+ CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
+ CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
+#else
+ CLK_RESERVED1,
+ CLK_RESERVED2,
+#endif
+ CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
+ CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
+ CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+ CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
+ CLK_RESERVED3,
+ CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
+ CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
+#else
+ CLK_RESERVED3 = 192,
+ CLK_RESERVED3A,
+ CLK_RESERVED4,
+ CLK_RESERVED5,
+#endif
+ CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
+ CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
+#if defined(CHIP_LPC43XX)
+ CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
+ CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
+#else
+ CLK_RESERVED7 = 320,
+ CLK_RESERVED8,
+#endif
+ CLK_CCU1_LAST,
+
+ /* CCU2 clocks */
+ CLK_CCU2_START,
+ CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
+ RESERVED_ALIGNB = CLK_CCU2_START + 31,
+ CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
+ RESERVED_ALIGNC = CLK_CCU2_START + 63,
+ CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
+ RESERVED_ALIGND = CLK_CCU2_START + 95,
+ CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
+ RESERVED_ALIGNE = CLK_CCU2_START + 127,
+ CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
+ RESERVED_ALIGNF = CLK_CCU2_START + 159,
+ CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
+ RESERVED_ALIGNG = CLK_CCU2_START + 191,
+ CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
+ RESERVED_ALIGNH = CLK_CCU2_START + 223,
+ CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
+ CLK_CCU2_LAST
+} CCU_CLK_T;
+
+/*
+ * Audio or USB PLL selection
+ */
+typedef enum CGU_USB_AUDIO_PLL {
+ CGU_USB_PLL,
+ CGU_AUDIO_PLL
+} CGU_USB_AUDIO_PLL_T;
+
+/*
+ * PLL register block
+ */
+typedef struct {
+ __I uint32_t PLL_STAT; /* PLL status register */
+ __IO uint32_t PLL_CTRL; /* PLL control register */
+ __IO uint32_t PLL_MDIV; /* PLL M-divider register */
+ __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
+} CGU_PLL_REG_T;
+
+typedef struct { /* (@ 0x40050000) CGU Structure */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
+ __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
+ CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
+ __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
+ __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
+ __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
+ __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
+ __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
+} LPC_CGU_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU clock config/status register pair
+ */
+typedef struct {
+ __IO uint32_t CFG; /* CCU clock configuration register */
+ __I uint32_t STAT; /* CCU clock status register */
+} CCU_CFGSTAT_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU1 register block structure
+ */
+typedef struct { /* (@ 0x40051000) CCU1 Structure */
+ __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
+} LPC_CCU1_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU2 register block structure
+ */
+typedef struct { /* (@ 0x40052000) CCU2 Structure */
+ __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
+} LPC_CCU2_T;
+
+/* ---------------------------------------------------------------------------
+ * RGU register structure
+ */
+#define LPC_RGU_BASE 0x40053000
+
+typedef enum RGU_RST {
+ RGU_CORE_RST,
+ RGU_PERIPH_RST,
+ RGU_MASTER_RST,
+ RGU_WWDT_RST = 4,
+ RGU_CREG_RST,
+ RGU_BUS_RST = 8,
+ RGU_SCU_RST,
+ RGU_M3_RST = 13,
+ RGU_LCD_RST = 16,
+ RGU_USB0_RST,
+ RGU_USB1_RST,
+ RGU_DMA_RST,
+ RGU_SDIO_RST,
+ RGU_EMC_RST,
+ RGU_ETHERNET_RST,
+ RGU_FLASHA_RST = 25,
+ RGU_EEPROM_RST = 27,
+ RGU_GPIO_RST,
+ RGU_FLASHB_RST,
+ RGU_TIMER0_RST = 32,
+ RGU_TIMER1_RST,
+ RGU_TIMER2_RST,
+ RGU_TIMER3_RST,
+ RGU_RITIMER_RST,
+ RGU_SCT_RST,
+ RGU_MOTOCONPWM_RST,
+ RGU_QEI_RST,
+ RGU_ADC0_RST,
+ RGU_ADC1_RST,
+ RGU_DAC_RST,
+ RGU_UART0_RST = 44,
+ RGU_UART1_RST,
+ RGU_UART2_RST,
+ RGU_UART3_RST,
+ RGU_I2C0_RST,
+ RGU_I2C1_RST,
+ RGU_SSP0_RST,
+ RGU_SSP1_RST,
+ RGU_I2S_RST,
+ RGU_SPIFI_RST,
+ RGU_CAN1_RST,
+ RGU_CAN0_RST,
+#ifdef CHIP_LPC43XX
+ RGU_M0APP_RST,
+ RGU_SGPIO_RST,
+ RGU_SPI_RST,
+#endif
+ RGU_LAST_RST = 63,
+} RGU_RST_T;
+
+typedef struct { /* RGU Structure */
+ __I uint32_t RESERVED0[64];
+ __O uint32_t RESET_CTRL0; /* Reset control register 0 */
+ __O uint32_t RESET_CTRL1; /* Reset control register 1 */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
+ __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
+ __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
+ __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
+ __I uint32_t RESERVED2[12];
+ __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
+ __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
+ __I uint32_t RESERVED3[170];
+ __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
+} LPC_RGU_T;
+
+/* ---------------------------------------------------------------------------
+ * Windowed Watchdog register block structure
+ */
+#define LPC_WWDT_BASE 0x40080000
+
+typedef struct { /* WWDT Structure */
+ __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
+ __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+#ifdef WATCHDOG_CLKSEL_SUPPORT
+ __IO uint32_t CLKSEL; /* Watchdog clock select register. */
+#else
+ __I uint32_t RESERVED0;
+#endif
+#ifdef WATCHDOG_WINDOW_SUPPORT
+ __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+ __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
+#endif
+} LPC_WWDT_T;
+
+/* ---------------------------------------------------------------------------
+ * USART register block structure
+ */
+#define LPC_USART0_BASE 0x40081000
+#define LPC_UART1_BASE 0x40082000
+#define LPC_USART2_BASE 0x400C1000
+#define LPC_USART3_BASE 0x400C2000
+
+typedef struct { /* USARTn Structure */
+
+ union {
+ __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+ __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+ };
+
+ union {
+ __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+ __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ };
+
+ union {
+ __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
+ __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+
+ __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
+ __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
+ __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
+ __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
+ __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
+ __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
+ union {
+ __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
+ __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+ };
+
+ __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
+} LPC_USART_T;
+
+/* ---------------------------------------------------------------------------
+ * SSP register block structure
+ */
+#define LPC_SSP0_BASE 0x40083000
+#define LPC_SSP1_BASE 0x400C5000
+
+typedef struct { /* SSPn Structure */
+ __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /* Status Register */
+ __IO uint32_t CPSR; /* Clock Prescale Register */
+ __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /* Raw Interrupt Status Register */
+ __I uint32_t MIS; /* Masked Interrupt Status Register */
+ __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
+ __IO uint32_t DMACR; /* SSPn DMA control register */
+} LPC_SSP_T;
+
+/* ---------------------------------------------------------------------------
+ * 32-bit Standard timer register block structure
+ */
+#define LPC_TIMER0_BASE 0x40084000
+#define LPC_TIMER1_BASE 0x40085000
+#define LPC_TIMER2_BASE 0x400C3000
+#define LPC_TIMER3_BASE 0x400C4000
+
+typedef struct { /* TIMERn Structure */
+ __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+ __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * System Control Unit register block
+ */
+#define LPC_SCU_BASE 0x40086000
+
+typedef struct {
+ __IO uint32_t SFSP[16][32];
+ __I uint32_t RESERVED0[256];
+ __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
+ __I uint32_t RESERVED16[28];
+ __IO uint32_t SFSUSB; /* Pin configuration register for USB */
+ __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
+ __IO uint32_t ENAIO[3]; /* Analog function select registers */
+ __I uint32_t RESERVED17[27];
+ __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
+ __I uint32_t RESERVED18[63];
+ __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
+ __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_T;
+
+/*
+ * SCU function and mode selection definitions
+ * See the User Manual for specific modes and functions supoprted by the
+ * various LPC18xx/43xx devices. Functionality can vary per device.
+ */
+#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
+#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
+#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
+#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
+#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
+#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
+#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
+
+#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
+#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
+#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
+#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
+#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
+#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
+#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
+#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
+
+/* Common SCU configurations */
+#define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
+#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
+
+/* Calculate SCU offset and register address from group and pin number */
+#define SCU_OFF(group, num) ((group << 7) + (num << 2))
+#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
+
+/**
+ * SCU function and mode selection definitions (old)
+ * For backwards compatibility.
+ */
+#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
+#define MD_EZI (0x1 << 6) /* Input buffer enable */
+#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
+#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
+#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
+
+#define FUNC0 0x0 /* Pin function 0 */
+#define FUNC1 0x1 /* Pin function 1 */
+#define FUNC2 0x2 /* Pin function 2 */
+#define FUNC3 0x3 /* Pin function 3 */
+#define FUNC4 0x4 /* Pin function 4 */
+#define FUNC5 0x5 /* Pin function 5 */
+#define FUNC6 0x6 /* Pin function 6 */
+#define FUNC7 0x7 /* Pin function 7 */
+
+#define PORT_OFFSET 0x80 /* Port offset definition */
+#define PIN_OFFSET 0x04 /* Pin offset definition */
+
+/* Returns the SFSP register address in the SCU for a pin and port,
+ recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
+ (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
+
+/* Returns the address in the SCU for a SFSCLK clock register,
+ recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
+ (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
+
+/* ---------------------------------------------------------------------------
+ * GPIO pin interrupt register block structure
+ */
+#define LPC_GPIO_PIN_INT_BASE 0x40087000
+
+typedef struct { /* GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /* Pin Interrupt Mode register */
+ __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /* Pin Interrupt Status register */
+} LPC_GPIOPININT_T;
+
+typedef enum LPC_GPIOPININT_MODE {
+ GPIOPININT_RISING_EDGE = 0x01,
+ GPIOPININT_FALLING_EDGE = 0x02,
+ GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
+ GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
+} LPC_GPIOPININT_MODE_T;
+
+/* ---------------------------------------------------------------------------
+ * GPIO grouped interrupt register block structure
+ */
+#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
+
+typedef struct { /* GPIO_GROUP_INTn Structure */
+ __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
+} LPC_GPIOGROUPINT_T;
+
+/* ---------------------------------------------------------------------------
+ * Motor Control PWM register block structure
+ */
+#define LPC_MCPWM_BASE 0x400A0000
+
+typedef struct { /* MCPWM Structure */
+ __I uint32_t CON; /* PWM Control read address */
+ __O uint32_t CON_SET; /* PWM Control set address */
+ __O uint32_t CON_CLR; /* PWM Control clear address */
+ __I uint32_t CAPCON; /* Capture Control read address */
+ __O uint32_t CAPCON_SET; /* Capture Control set address */
+ __O uint32_t CAPCON_CLR; /* Event Control clear address */
+ __IO uint32_t TC[3]; /* Timer Counter register */
+ __IO uint32_t LIM[3]; /* Limit register */
+ __IO uint32_t MAT[3]; /* Match register */
+ __IO uint32_t DT; /* Dead time register */
+ __IO uint32_t CCP; /* Communication Pattern register */
+ __I uint32_t CAP[3]; /* Capture register */
+ __I uint32_t INTEN; /* Interrupt Enable read address */
+ __O uint32_t INTEN_SET; /* Interrupt Enable set address */
+ __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
+ __I uint32_t CNTCON; /* Count Control read address */
+ __O uint32_t CNTCON_SET; /* Count Control set address */
+ __O uint32_t CNTCON_CLR; /* Count Control clear address */
+ __I uint32_t INTF; /* Interrupt flags read address */
+ __O uint32_t INTF_SET; /* Interrupt flags set address */
+ __O uint32_t INTF_CLR; /* Interrupt flags clear address */
+ __O uint32_t CAP_CLR; /* Capture clear address */
+} LPC_MCPWM_T;
+
+/* ---------------------------------------------------------------------------
+ * I2C register block structure
+ */
+#define LPC_I2C0_BASE 0x400A1000
+#define LPC_I2C1_BASE 0x400E0000
+
+typedef struct { /* I2C0 Structure */
+ __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /* Monitor mode control register. */
+ __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ __IO uint32_t MASK[4]; /* I2C Slave address mask register */
+} LPC_I2C_T;
+
+/* ---------------------------------------------------------------------------
+ * I2S register block structure
+ */
+#define LPC_I2S0_BASE 0x400A2000
+#define LPC_I2S1_BASE 0x400A3000
+
+typedef struct { /* I2S Structure */
+ __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
+ __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
+ __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
+ __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
+ __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
+ __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
+ __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
+ __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
+ __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
+ __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
+ __IO uint32_t TXMODE; /* I2S Transmit mode control */
+ __IO uint32_t RXMODE; /* I2S Receive mode control */
+} LPC_I2S_T;
+
+/* ---------------------------------------------------------------------------
+ * CCAN Controller Area Network register block structure
+ */
+#define LPC_C_CAN1_BASE 0x400A4000
+#define LPC_C_CAN0_BASE 0x400E2000
+
+typedef struct { /* C_CAN message interface Structure */
+ __IO uint32_t IF_CMDREQ; /* Message interface command request */
+ union {
+ __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
+ __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
+ };
+
+ __IO uint32_t IF_MSK1; /* Message interface mask 1 */
+ __IO uint32_t IF_MSK2; /* Message interface mask 2 */
+ __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
+ __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
+ __IO uint32_t IF_MCTRL; /* Message interface message control */
+ __IO uint32_t IF_DA1; /* Message interface data A1 */
+ __IO uint32_t IF_DA2; /* Message interface data A2 */
+ __IO uint32_t IF_DB1; /* Message interface data B1 */
+ __IO uint32_t IF_DB2; /* Message interface data B2 */
+ __I uint32_t RESERVED[13];
+} LPC_CCAN_IF_T;
+
+typedef struct { /* C_CAN Structure */
+ __IO uint32_t CNTL; /* CAN control */
+ __IO uint32_t STAT; /* Status register */
+ __I uint32_t EC; /* Error counter */
+ __IO uint32_t BT; /* Bit timing register */
+ __I uint32_t INT; /* Interrupt register */
+ __IO uint32_t TEST; /* Test register */
+ __IO uint32_t BRPE; /* Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ LPC_CCAN_IF_T IF[2];
+ __I uint32_t RESERVED2[8];
+ __I uint32_t TXREQ1; /* Transmission request 1 */
+ __I uint32_t TXREQ2; /* Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t ND1; /* New data 1 */
+ __I uint32_t ND2; /* New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t IR1; /* Interrupt pending 1 */
+ __I uint32_t IR2; /* Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /* Message valid 1 */
+ __I uint32_t MSGV2; /* Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /* CAN clock divider register */
+} LPC_CCAN_T;
+
+/* ---------------------------------------------------------------------------
+ * Repetitive Interrupt Timer register block structure
+ */
+#define LPC_RITIMER_BASE 0x400C0000
+
+typedef struct { /* RITIMER Structure */
+ __IO uint32_t COMPVAL; /* Compare register */
+ __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+ __IO uint32_t CTRL; /* Control register. */
+ __IO uint32_t COUNTER; /* 32-bit counter */
+} LPC_RITIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * Quadrature Encoder Interface register block structure
+ */
+#define LPC_QEI_BASE 0x400C6000
+
+typedef struct { /* QEI Structure */
+ __O uint32_t CON; /* Control register */
+ __I uint32_t STAT; /* Encoder status register */
+ __IO uint32_t CONF; /* Configuration register */
+ __I uint32_t POS; /* Position register */
+ __IO uint32_t MAXPOS; /* Maximum position register */
+ __IO uint32_t CMPOS0; /* position compare register 0 */
+ __IO uint32_t CMPOS1; /* position compare register 1 */
+ __IO uint32_t CMPOS2; /* position compare register 2 */
+ __I uint32_t INXCNT; /* Index count register */
+ __IO uint32_t INXCMP0; /* Index compare register 0 */
+ __IO uint32_t LOAD; /* Velocity timer reload register */
+ __I uint32_t TIME; /* Velocity timer register */
+ __I uint32_t VEL; /* Velocity counter register */
+ __I uint32_t CAP; /* Velocity capture register */
+ __IO uint32_t VELCOMP; /* Velocity compare register */
+ __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /* Index acceptance window register */
+ __IO uint32_t INXCMP1; /* Index compare register 1 */
+ __IO uint32_t INXCMP2; /* Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /* Interrupt enable clear register */
+ __O uint32_t IES; /* Interrupt enable set register */
+ __I uint32_t INTSTAT; /* Interrupt status register */
+ __I uint32_t IE; /* Interrupt enable register */
+ __O uint32_t CLR; /* Interrupt status clear register */
+ __O uint32_t SET; /* Interrupt status set register */
+} LPC_QEI_T;
+
+/* ---------------------------------------------------------------------------
+ * Global Input Multiplexer Array (GIMA) register block structure
+ */
+#define LPC_GIMA_BASE 0x400C7000
+
+typedef struct { /* GIMA Structure */
+ __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
+ __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
+ __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
+ __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
+ __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
+ __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
+ __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
+ __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_T;
+
+/* ---------------------------------------------------------------------------
+ * DAC register block structure
+ */
+#define LPC_DAC_BASE 0x400E1000
+
+typedef struct { /* DAC Structure */
+ __IO uint32_t CR; /* DAC register. Holds the conversion data. */
+ __IO uint32_t CTRL; /* DAC control register. */
+ __IO uint32_t CNTVAL; /* DAC counter value register. */
+} LPC_DAC_T;
+
+/* After the selected settling time after this field is written with a
+ * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+ * is VALUE/1024 ? VREF
+ */
+#define DAC_RANGE 0x3FF
+#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
+#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
+#define DAC_VALUE(n) DAC_SET(n)
+/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere
+ */
+#define DAC_BIAS_EN ((uint32_t) (1 << 16))
+/* Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
+
+#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
+#define DAC_CNT_ENA ((uint32_t) (1 << 2))
+#define DAC_DMA_ENA ((uint32_t) (1 << 3))
+#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
+
+/* Current option in DAC configuration option */
+typedef enum DAC_CURRENT_OPT {
+ DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
+ allows for a maximum update rate of 1 MHz */
+ DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
+ allows for a maximum update rate of 400 kHz */
+} DAC_CURRENT_OPT_T;
+
+/* ---------------------------------------------------------------------------
+ * ADC register block structure
+ */
+#define LPC_ADC0_BASE 0x400E3000
+#define LPC_ADC1_BASE 0x400E4000
+#define ADC_ACC_10BITS
+
+/* ---------------------------------------------------------------------------
+ * 10 or 12-bit ADC register block structure
+ */
+typedef struct { /* ADCn Structure */
+ __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+ __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+ __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADC_T;
+
+/* ADC register support bitfields and mask */
+#define ADC_RANGE 0x3FF
+#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
+#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
+#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
+#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
+#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
+#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
+#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
+
+/* ADC status register used for IP drivers */
+typedef enum ADC_STATUS {
+ ADC_DR_DONE_STAT, /* ADC data register staus */
+ ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
+ ADC_DR_ADINT_STAT /* ADC interrupt status */
+} ADC_STATUS_T;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum ADC_START_MODE {
+ ADC_NO_START = 0,
+ ADC_START_NOW, /* Start conversion now */
+ ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+ ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+ ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+ ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+ ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_MODE_T;
+
+/* ---------------------------------------------------------------------------
+ * GPIO port register block structure
+ */
+#define LPC_GPIO_PORT_BASE 0x400F4000
+#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
+#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
+#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
+#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
+#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
+#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
+#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
+#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
+
+typedef struct { /* GPIO_PORT Structure */
+ __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
+ __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
+ __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
+ __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
+ __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
+ __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
+ __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
+ __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
+ __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
+} LPC_GPIO_T;
+
+/* Calculate GPIO offset and port register address from group and pin number */
+#define GPIO_OFF(port, pin) ((port << 5) + pin)
+#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
+
+/* ---------------------------------------------------------------------------
+ * SPI register block structure
+ */
+#define LPC_SPI_BASE 0x40100000
+
+typedef struct { /* SPI Structure */
+ __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
+ __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
+ __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
+ __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_T;
+
+/* SPI CFG Register BitMask */
+#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
+/* Enable of controlling the number of bits per transfer */
+#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
+/* Mask of field of bit controlling */
+#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
+/* Set the number of bits per a transfer */
+#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
+/* SPI Clock Phase Select*/
+#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
+#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
+/* SPI Clock Polarity Select*/
+#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
+#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
+/* SPI Slave Mode Select */
+#define SPI_CR_SLAVE_EN ((uint32_t) 0)
+/* SPI Master Mode Select */
+#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
+/* SPI MSB First mode enable */
+#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
+/* SPI LSB First mode enable */
+#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
+/* SPI interrupt enable */
+#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
+/* SPI STAT Register BitMask */
+#define SPI_SR_BITMASK ((uint32_t) 0xF8)
+/* Slave abort Flag */
+#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
+/* Mode fault Flag */
+#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
+/* Read overrun flag*/
+#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
+/* Write collision flag. */
+#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
+/* SPI transfer complete flag. */
+#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
+/* SPI error flag */
+#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
+/* Enable SPI Test Mode */
+#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
+/* SPI interrupt flag */
+#define SPI_INT_SPIF ((uint32_t) (1 << 0))
+/* Receiver Data */
+#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
+
+/* SPI Mode*/
+typedef enum LPC_SPI_MODE {
+ SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
+ SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
+} LPC_SPI_MODE_T;
+
+/* SPI Clock Mode*/
+typedef enum LPC_SPI_CLOCK_MODE {
+ SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
+ SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
+ SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
+ SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
+ SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
+ SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
+ SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
+ SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
+} LPC_SPI_CLOCK_MODE_T;
+
+/* SPI Data Order Mode*/
+typedef enum LPC_SPI_DATA_ORDER {
+ SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
+ SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
+} LPC_SPI_DATA_ORDER_T;
+
+/* ---------------------------------------------------------------------------
+ * Serial GPIO register block structure
+ */
+#define LPC_SGPIO_BASE 0x40101000
+
+typedef struct { /* SGPIO Structure */
+ __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
+ __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
+ __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
+ __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+ __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+ __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+ __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
+ __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
+ __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
+ __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
+ __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
+ __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
+ __I uint32_t GPIO_INREG; /* GPIO input status register */
+ __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
+ __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
+ __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
+ __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
+ __I uint32_t RESERVED0[823];
+ __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
+ __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
+ __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
+ __I uint32_t STATUS_0; /* Shift clock interrupt status */
+ __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
+ __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
+ __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
+ __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
+ __I uint32_t STATUS_1; /* Capture clock interrupt status */
+ __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
+ __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
+ __I uint32_t RESERVED2[2];
+ __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
+ __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
+ __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
+ __I uint32_t STATUS_2; /* Pattern match interrupt status */
+ __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
+ __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
+ __I uint32_t RESERVED3[2];
+ __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
+ __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
+ __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
+ __I uint32_t STATUS_3; /* Input bit match interrupt status */
+ __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
+ __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
+} LPC_SGPIO_T;
+
+/* End of section using anonymous unions */
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__IAR_SYSTEMS_ICC__)
+ //#pragma pop // FIXME not usable for IAR
+#else /* defined(__GNUC__) and others */
+ /* Leave anonymous unions enabled */
+#endif
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx Peripheral register set declarations
+ */
+#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
+#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
+#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
+#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
+#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
+#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
+#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
+#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
+#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
+#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
+#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
+#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
+#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
+#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
+#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
+#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
+#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
+#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
+#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
+#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
+#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
+#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
+#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
+#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
+#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
+#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
+#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
+#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
+#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
+#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
+#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
+#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
+#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
+#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
+#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
+#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
+#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
+#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
+#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
+#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
+#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
+#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
+#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
+#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
+#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
+#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
+#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC43XX_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini
new file mode 100644
index 000000000..a5c3700b6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini
@@ -0,0 +1,12 @@
+
+FUNC void Setup (unsigned int region) {
+ region &= 0xFF000000;
+ _WDWORD(0x40043100, region); // Set the shadow pointer
+ _WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
+ SP = _RDWORD(0); // Setup Stack Pointer
+ PC = _RDWORD(4); // Setup Program Counter
+}
+
+LOAD %L INCREMENTAL
+Setup(0x14000000); // Get ready to execute image in QSPI
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/LPC43xx.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/LPC43xx.sct
new file mode 100644
index 000000000..8d39f7c81
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/LPC43xx.sct
@@ -0,0 +1,25 @@
+
+LR_IROM1 0x14000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x14000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118
+ ; 128KB - 0x0118 = 0x0001FEE8
+ RW_IRAM1 0x10000118 0x1FEE8 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x10080000 0x12000 { ; RW data
+ .ANY (IRAM2)
+ }
+ RW_IRAM3 0x20000000 0x8000 { ; RW data
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM4 0x20008000 0x4000 { ; RW data
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM5 0x2000C000 0x4000 { ; RW data
+ .ANY (AHBSRAM2)
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/startup_LPC43xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/startup_LPC43xx.s
new file mode 100644
index 000000000..1a51c7fbe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/startup_LPC43xx.s
@@ -0,0 +1,294 @@
+;/***********************************************************************
+; * @brief: LPC18xx/43xx M3/M4 startup code
+; *
+; * @note
+; * Copyright(C) NXP Semiconductors, 2012
+; * All rights reserved.
+; *
+; * @par
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * LPC products. This software is supplied "AS IS" without any warranties of
+; * any kind, and NXP Semiconductors and its licensor disclaim any and
+; * all warranties, express or implied, including all implied warranties of
+; * merchantability, fitness for a particular purpose and non-infringement of
+; * intellectual property rights. NXP Semiconductors assumes no responsibility
+; * or liability for the use of the software, conveys no license or rights under any
+; * patent, copyright, mask work right, or any other intellectual property rights in
+; * or to any products. NXP Semiconductors reserves the right to make changes
+; * in the software without notification. NXP Semiconductors also makes no
+; * representation or warranty that such application will be suitable for the
+; * specified use without further testing or modification.
+; *
+; * @par
+; * Permission to use, copy, modify, and distribute this software and its
+; * documentation is hereby granted, under NXP Semiconductors' and its
+; * licensor's relevant copyrights in the software, without fee, provided that it
+; * is used in conjunction with NXP Semiconductors microcontrollers. This
+; * copyright, permission, and disclaimer notice must appear in all copies of
+; * this code.
+; */
+
+; __initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX (IRAM1)
+__initial_sp EQU 0x10092000 ; Top of first RAM segment for LPC43XX (IRAM2)
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+Sign_Value EQU 0x5A5A5A5A
+
+__Vectors DCD __initial_sp ; 0 Top of Stack
+ DCD Reset_Handler ; 1 Reset Handler
+ DCD NMI_Handler ; 2 NMI Handler
+ DCD HardFault_Handler ; 3 Hard Fault Handler
+ DCD MemManage_Handler ; 4 MPU Fault Handler
+ DCD BusFault_Handler ; 5 Bus Fault Handler
+ DCD UsageFault_Handler ; 6 Usage Fault Handler
+ DCD Sign_Value ; 7 Reserved
+ DCD UnHandled_Vector ; 8 Reserved
+ DCD UnHandled_Vector ; 9 Reserved
+ DCD UnHandled_Vector ; 10 Reserved
+ DCD SVC_Handler ; 11 SVCall Handler
+ DCD DebugMon_Handler ; 12 Debug Monitor Handler
+ DCD UnHandled_Vector ; 13 Reserved
+ DCD PendSV_Handler ; 14 PendSV Handler
+ DCD SysTick_Handler ; 15 SysTick Handler
+
+ ; External Interrupts
+ DCD DAC_IRQHandler ; 16 D/A Converter
+ DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
+ DCD DMA_IRQHandler ; 18 General Purpose DMA
+ DCD UnHandled_Vector ; 19 Reserved
+ DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
+ DCD ETH_IRQHandler ; 21 Ethernet
+ DCD SDIO_IRQHandler ; 22 SD/MMC
+ DCD LCD_IRQHandler ; 23 LCD
+ DCD USB0_IRQHandler ; 24 USB0
+ DCD USB1_IRQHandler ; 25 USB1
+ DCD SCT_IRQHandler ; 26 State Configurable Timer
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
+ DCD TIMER0_IRQHandler ; 28 Timer0
+ DCD TIMER1_IRQHandler ; 29 Timer1
+ DCD TIMER2_IRQHandler ; 30 Timer2
+ DCD TIMER3_IRQHandler ; 31 Timer3
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0
+ DCD I2C0_IRQHandler ; 34 I2C0
+ DCD I2C1_IRQHandler ; 35 I2C1
+ DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1
+ DCD SSP0_IRQHandler ; 38 SSP0
+ DCD SSP1_IRQHandler ; 39 SSP1
+ DCD UART0_IRQHandler ; 40 UART0
+ DCD UART1_IRQHandler ; 41 UART1
+ DCD UART2_IRQHandler ; 42 UART2
+ DCD UART3_IRQHandler ; 43 UART3
+ DCD I2S0_IRQHandler ; 44 I2S0
+ DCD I2S1_IRQHandler ; 45 I2S1
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
+ DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
+ DCD GPIO0_IRQHandler ; 48 GPIO0
+ DCD GPIO1_IRQHandler ; 49 GPIO1
+ DCD GPIO2_IRQHandler ; 50 GPIO2
+ DCD GPIO3_IRQHandler ; 51 GPIO3
+ DCD GPIO4_IRQHandler ; 52 GPIO4
+ DCD GPIO5_IRQHandler ; 53 GPIO5
+ DCD GPIO6_IRQHandler ; 54 GPIO6
+ DCD GPIO7_IRQHandler ; 55 GPIO7
+ DCD GINT0_IRQHandler ; 56 GINT0
+ DCD GINT1_IRQHandler ; 57 GINT1
+ DCD EVRT_IRQHandler ; 58 Event Router
+ DCD CAN1_IRQHandler ; 59 C_CAN1
+ DCD UnHandled_Vector ; 60 Reserved
+ DCD VADC_IRQHandler ; 61 VADC
+ DCD ATIMER_IRQHandler ; 62 ATIMER
+ DCD RTC_IRQHandler ; 63 RTC
+ DCD UnHandled_Vector ; 64 Reserved
+ DCD WDT_IRQHandler ; 65 WDT
+ DCD UnHandled_Vector ; 66 M0s
+ DCD CAN0_IRQHandler ; 67 C_CAN0
+ DCD QEI_IRQHandler ; 68 QEI
+
+
+; IF :LNOT::DEF:NO_CRP
+; AREA |.ARM.__at_0x02FC|, CODE, READONLY
+;CRP_Key DCD 0xFFFFFFFF
+; ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+UnHandled_Vector PROC
+ EXPORT UnHandled_Vector [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT MX_CORE_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT FLASHEEPROM_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USB1_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT I2S1_IRQHandler [WEAK]
+ EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SGPIO_IRQHandler [WEAK]
+ EXPORT GPIO0_IRQHandler [WEAK]
+ EXPORT GPIO1_IRQHandler [WEAK]
+ EXPORT GPIO2_IRQHandler [WEAK]
+ EXPORT GPIO3_IRQHandler [WEAK]
+ EXPORT GPIO4_IRQHandler [WEAK]
+ EXPORT GPIO5_IRQHandler [WEAK]
+ EXPORT GPIO6_IRQHandler [WEAK]
+ EXPORT GPIO7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT EVRT_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT VADC_IRQHandler [WEAK]
+ EXPORT ATIMER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+
+DAC_IRQHandler
+MX_CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct
new file mode 100644
index 000000000..faba17a30
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x1A000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x1A000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+; ER_IROM2 0x1B000000 0x00080000 { ; load address = execution address
+; .ANY (+RO)
+; }
+
+ ; 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118
+ RW_IRAM1 0x10000000+0x118 0x8000-0x118 {
+ .ANY (+RW +ZI)
+ }
+; RW_IRAM2 0x10080000 0xA000 { ; RW data
+; .ANY (IRAM2)
+; }
+; RW_IRAM3 0x20000000 0x10000 { ; RW data
+; .ANY (AHBSRAM)
+; }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.s
new file mode 100644
index 000000000..a2a503d98
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.s
@@ -0,0 +1,291 @@
+;/***********************************************************************
+; * @brief: LPC18xx/43xx M3/M4 startup code
+; *
+; * @note
+; * Copyright(C) NXP Semiconductors, 2012
+; * All rights reserved.
+; *
+; * @par
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * LPC products. This software is supplied "AS IS" without any warranties of
+; * any kind, and NXP Semiconductors and its licensor disclaim any and
+; * all warranties, express or implied, including all implied warranties of
+; * merchantability, fitness for a particular purpose and non-infringement of
+; * intellectual property rights. NXP Semiconductors assumes no responsibility
+; * or liability for the use of the software, conveys no license or rights under any
+; * patent, copyright, mask work right, or any other intellectual property rights in
+; * or to any products. NXP Semiconductors reserves the right to make changes
+; * in the software without notification. NXP Semiconductors also makes no
+; * representation or warranty that such application will be suitable for the
+; * specified use without further testing or modification.
+; *
+; * @par
+; * Permission to use, copy, modify, and distribute this software and its
+; * documentation is hereby granted, under NXP Semiconductors' and its
+; * licensor's relevant copyrights in the software, without fee, provided that it
+; * is used in conjunction with NXP Semiconductors microcontrollers. This
+; * copyright, permission, and disclaimer notice must appear in all copies of
+; * this code.
+; */
+
+;__initial_sp EQU 0x1008A000 ; Top of 2nd RAM segment for LPC4337
+__initial_sp EQU 0x10008000 ; Top of 1st RAM segment for LPC4337
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+Sign_Value EQU 0x5A5A5A5A
+
+__Vectors DCD __initial_sp ; 0 Top of Stack
+ DCD Reset_Handler ; 1 Reset Handler
+ DCD NMI_Handler ; 2 NMI Handler
+ DCD HardFault_Handler ; 3 Hard Fault Handler
+ DCD MemManage_Handler ; 4 MPU Fault Handler
+ DCD BusFault_Handler ; 5 Bus Fault Handler
+ DCD UsageFault_Handler ; 6 Usage Fault Handler
+ DCD Sign_Value ; 7 Reserved
+ DCD UnHandled_Vector ; 8 Reserved
+ DCD UnHandled_Vector ; 9 Reserved
+ DCD UnHandled_Vector ; 10 Reserved
+ DCD SVC_Handler ; 11 SVCall Handler
+ DCD DebugMon_Handler ; 12 Debug Monitor Handler
+ DCD UnHandled_Vector ; 13 Reserved
+ DCD PendSV_Handler ; 14 PendSV Handler
+ DCD SysTick_Handler ; 15 SysTick Handler
+
+ ; External Interrupts
+ DCD DAC_IRQHandler ; 16 D/A Converter
+ DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
+ DCD DMA_IRQHandler ; 18 General Purpose DMA
+ DCD UnHandled_Vector ; 19 Reserved
+ DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
+ DCD ETH_IRQHandler ; 21 Ethernet
+ DCD SDIO_IRQHandler ; 22 SD/MMC
+ DCD LCD_IRQHandler ; 23 LCD
+ DCD USB0_IRQHandler ; 24 USB0
+ DCD USB1_IRQHandler ; 25 USB1
+ DCD SCT_IRQHandler ; 26 State Configurable Timer
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
+ DCD TIMER0_IRQHandler ; 28 Timer0
+ DCD TIMER1_IRQHandler ; 29 Timer1
+ DCD TIMER2_IRQHandler ; 30 Timer2
+ DCD TIMER3_IRQHandler ; 31 Timer3
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0
+ DCD I2C0_IRQHandler ; 34 I2C0
+ DCD I2C1_IRQHandler ; 35 I2C1
+ DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1
+ DCD SSP0_IRQHandler ; 38 SSP0
+ DCD SSP1_IRQHandler ; 39 SSP1
+ DCD UART0_IRQHandler ; 40 UART0
+ DCD UART1_IRQHandler ; 41 UART1
+ DCD UART2_IRQHandler ; 42 UART2
+ DCD UART3_IRQHandler ; 43 UART3
+ DCD I2S0_IRQHandler ; 44 I2S0
+ DCD I2S1_IRQHandler ; 45 I2S1
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
+ DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
+ DCD GPIO0_IRQHandler ; 48 GPIO0
+ DCD GPIO1_IRQHandler ; 49 GPIO1
+ DCD GPIO2_IRQHandler ; 50 GPIO2
+ DCD GPIO3_IRQHandler ; 51 GPIO3
+ DCD GPIO4_IRQHandler ; 52 GPIO4
+ DCD GPIO5_IRQHandler ; 53 GPIO5
+ DCD GPIO6_IRQHandler ; 54 GPIO6
+ DCD GPIO7_IRQHandler ; 55 GPIO7
+ DCD GINT0_IRQHandler ; 56 GINT0
+ DCD GINT1_IRQHandler ; 57 GINT1
+ DCD EVRT_IRQHandler ; 58 Event Router
+ DCD CAN1_IRQHandler ; 59 C_CAN1
+ DCD UnHandled_Vector ; 60 Reserved
+ DCD VADC_IRQHandler ; 61 VADC
+ DCD ATIMER_IRQHandler ; 62 ATIMER
+ DCD RTC_IRQHandler ; 63 RTC
+ DCD UnHandled_Vector ; 64 Reserved
+ DCD WDT_IRQHandler ; 65 WDT
+ DCD UnHandled_Vector ; 66 M0s
+ DCD CAN0_IRQHandler ; 67 C_CAN0
+ DCD QEI_IRQHandler ; 68 QEI
+
+; IF :LNOT::DEF:NO_CRP
+; AREA |.ARM.__at_0x02FC|, CODE, READONLY
+;CRP_Key DCD 0xFFFFFFFF
+; ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+UnHandled_Vector PROC
+ EXPORT UnHandled_Vector [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT MX_CORE_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT FLASHEEPROM_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USB1_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT I2S1_IRQHandler [WEAK]
+ EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SGPIO_IRQHandler [WEAK]
+ EXPORT GPIO0_IRQHandler [WEAK]
+ EXPORT GPIO1_IRQHandler [WEAK]
+ EXPORT GPIO2_IRQHandler [WEAK]
+ EXPORT GPIO3_IRQHandler [WEAK]
+ EXPORT GPIO4_IRQHandler [WEAK]
+ EXPORT GPIO5_IRQHandler [WEAK]
+ EXPORT GPIO6_IRQHandler [WEAK]
+ EXPORT GPIO7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT EVRT_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT VADC_IRQHandler [WEAK]
+ EXPORT ATIMER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+
+DAC_IRQHandler
+MX_CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/LPC4330.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/LPC4330.ld
new file mode 100644
index 000000000..42c5f60be
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/LPC4330.ld
@@ -0,0 +1,174 @@
+/* Linker script for mbed LPC4330 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ RAM0 (rwx) : ORIGIN = 0x10000114, LENGTH = (128K - 0x114)
+ RAM1 (rwx) : ORIGIN = 0x10080000, LENGTH = 72K
+
+ RAM_AHB0 (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+ RAM_AHB1 (rwx) : ORIGIN = 0x20008000, LENGTH = 32K
+
+ SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 32M
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > SPIFI
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SPIFI
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SPIFI
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM0
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM1
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM1
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM1
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM1) + LENGTH(RAM1);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > RAM_AHB0
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > RAM_AHB1
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s
new file mode 100644
index 000000000..f137dc05b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s
@@ -0,0 +1,260 @@
+/* File: startup_ARMCM4.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 20 Dezember 2012
+ *
+ */
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+.ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+.else
+ .equ Stack_Size, 0x00000400
+.endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+.ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+.else
+ .equ Heap_Size, 0x00000C00
+.endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DAC_IRQHandler /* 0: DAC */
+ .long M0CORE_IRQHandler /* 1: M4-M0 communication */
+ .long DMA_IRQHandler /* 2: - */
+ .long 0 /* 3: Reserved */
+ .long FLASHEEPROM_IRQHandler/* 4: ORed flash bank A/B, EEPROM int */
+ .long ETHERNET_IRQHandler /* 5: Ethernet interrupt */
+ .long SDIO_IRQHandler /* 6: SD/MMC interrupt */
+ .long LCD_IRQHandler /* 7: - */
+ .long USB0_IRQHandler /* 8: OTG interrupt */
+ .long USB1_IRQHandler /* 9: - */
+ .long SCT_IRQHandler /* 10: SCT combined interrupt */
+ .long RITIMER_IRQHandler /* 11: - */
+ .long TIMER0_IRQHandler /* 12: - */
+ .long TIMER1_IRQHandler /* 13: - */
+ .long TIMER2_IRQHandler /* 14: - */
+ .long TIMER3_IRQHandler /* 15: - */
+ .long MCPWM_IRQHandler /* 16: Motor control PWM */
+ .long ADC0_IRQHandler /* 17: - */
+ .long I2C0_IRQHandler /* 18: - */
+ .long I2C1_IRQHandler /* 19: - */
+ .long SPI_IRQHandler /* 20: - */
+ .long ADC1_IRQHandler /* 21: - */
+ .long SSP0_IRQHandler /* 22: - */
+ .long SSP1_IRQHandler /* 23: - */
+ .long USART0_IRQHandler /* 24: - */
+ .long UART1_IRQHandler /* 25: Combined UART int w Modem int */
+ .long USART2_IRQHandler /* 26: - */
+ .long USART3_IRQHandler /* 27: combined USART int w IrDA int */
+ .long I2S0_IRQHandler /* 28: - */
+ .long I2S1_IRQHandler /* 29: - */
+ .long SPIFI_IRQHandler /* 30: - */
+ .long SGPIO_IRQHandler /* 31: - */
+ .long PIN_INT0_IRQHandler /* 32: GPIO pin interrupt 0 */
+ .long PIN_INT1_IRQHandler /* 33: GPIO pin interrupt 1 */
+ .long PIN_INT2_IRQHandler /* 34: GPIO pin interrupt 2 */
+ .long PIN_INT3_IRQHandler /* 35: GPIO pin interrupt 3 */
+ .long PIN_INT4_IRQHandler /* 36: GPIO pin interrupt 4 */
+ .long PIN_INT5_IRQHandler /* 37: GPIO pin interrupt 5 */
+ .long PIN_INT6_IRQHandler /* 38: GPIO pin interrupt 6 */
+ .long PIN_INT7_IRQHandler /* 39: GPIO pin interrupt 7 */
+ .long GINT0_IRQHandler /* 40: GPIO global interrupt 0 */
+ .long GINT1_IRQHandler /* 41: GPIO global interrupt 1 */
+ .long EVENTROUTER_IRQHandler/* 42: Event router interrupt */
+ .long C_CAN1_IRQHandler /* 43: - */
+ .long 0 /* 44: Reserved */
+ .long 0 /* 45: Reserved */
+ .long ATIMER_IRQHandler /* 46: Alarm timer interuupt */
+ .long RTC_IRQHandler /* 47: - */
+ .long 0 /* 48: Reserved */
+ .long WWDT_IRQHandler /* 49: - */
+ .long 0 /* 50: Reserved */
+ .long C_CAN0_IRQHandler /* 51: - */
+ .long QEI_IRQHandler /* 52: - */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DAC_IRQHandler
+ def_irq_default_handler M0CORE_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler FLASHEEPROM_IRQHandler
+ def_irq_default_handler ETHERNET_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USB1_IRQHandler
+ def_irq_default_handler SCT_IRQHandler
+ def_irq_default_handler RITIMER_IRQHandler
+ def_irq_default_handler TIMER0_IRQHandler
+ def_irq_default_handler TIMER1_IRQHandler
+ def_irq_default_handler TIMER2_IRQHandler
+ def_irq_default_handler TIMER3_IRQHandler
+ def_irq_default_handler MCPWM_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler SSP0_IRQHandler
+ def_irq_default_handler SSP1_IRQHandler
+ def_irq_default_handler USART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler I2S0_IRQHandler
+ def_irq_default_handler I2S1_IRQHandler
+ def_irq_default_handler SPIFI_IRQHandler
+ def_irq_default_handler SGPIO_IRQHandler
+ def_irq_default_handler PIN_INT0_IRQHandler
+ def_irq_default_handler PIN_INT1_IRQHandler
+ def_irq_default_handler PIN_INT2_IRQHandler
+ def_irq_default_handler PIN_INT3_IRQHandler
+ def_irq_default_handler PIN_INT4_IRQHandler
+ def_irq_default_handler PIN_INT5_IRQHandler
+ def_irq_default_handler PIN_INT6_IRQHandler
+ def_irq_default_handler PIN_INT7_IRQHandler
+ def_irq_default_handler GINT0_IRQHandler
+ def_irq_default_handler GINT1_IRQHandler
+ def_irq_default_handler EVENTROUTER_IRQHandler
+ def_irq_default_handler C_CAN1_IRQHandler
+ def_irq_default_handler ATIMER_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler WWDT_IRQHandler
+ def_irq_default_handler C_CAN0_IRQHandler
+ def_irq_default_handler QEI_IRQHandler
+
+ .end
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld
new file mode 100644
index 000000000..12d97fa88
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld
@@ -0,0 +1,281 @@
+/* mbed - LPC4330_M4 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 7.0
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */
+ RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */
+ SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_RamLoc128 = 0x10000000 + 0x20000;
+ __top_RamLoc72 = 0x10080000 + 0x12000;
+ __top_RamAHB32 = 0x20000000 + 0x8000;
+ __top_RamAHB16 = 0x20008000 + 0x4000;
+ __top_RamAHB_ETB16 = 0x2000c000 + 0x4000;
+ __top_SPIFI = 0x14000000 + 0x400000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ LONG(LOADADDR(.data_RAM4));
+ LONG( ADDR(.data_RAM4));
+ LONG( SIZEOF(.data_RAM4));
+ LONG(LOADADDR(.data_RAM5));
+ LONG( ADDR(.data_RAM5));
+ LONG( SIZEOF(.data_RAM5));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ LONG( ADDR(.bss_RAM4));
+ LONG( SIZEOF(.bss_RAM4));
+ LONG( ADDR(.bss_RAM5));
+ LONG( SIZEOF(.bss_RAM5));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ } >SPIFI
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > SPIFI
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SPIFI
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SPIFI
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamLoc72 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamLoc72)
+ *(.data.$RAM2*)
+ *(.data.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72 AT>SPIFI
+
+ /* DATA section for RamAHB32 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM3*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>SPIFI
+
+ /* DATA section for RamAHB16 */
+ .data_RAM4 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM4)
+ *(.ramfunc.$RamAHB16)
+ *(.data.$RAM4*)
+ *(.data.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16 AT>SPIFI
+
+ /* DATA section for RamAHB_ETB16 */
+ .data_RAM5 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM5)
+ *(.ramfunc.$RamAHB_ETB16)
+ *(.data.$RAM5*)
+ *(.data.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16 AT>SPIFI
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc128
+
+
+ /* Main DATA section (RamLoc128) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc128 AT>SPIFI
+
+ /* BSS section for RamLoc72 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72
+ /* BSS section for RamAHB32 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ *(.bss.$RAM3*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* BSS section for RamAHB16 */
+ .bss_RAM4 : ALIGN(4)
+ {
+ *(.bss.$RAM4*)
+ *(.bss.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16
+ /* BSS section for RamAHB_ETB16 */
+ .bss_RAM5 : ALIGN(4)
+ {
+ *(.bss.$RAM5*)
+ *(.bss.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc128
+
+ /* NOINIT section for RamLoc72 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* NOINIT section for RamAHB16 */
+ .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM4*)
+ *(.noinit.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16
+ /* NOINIT section for RamAHB_ETB16 */
+ .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM5*)
+ *(.noinit.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc128
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc128 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp
new file mode 100644
index 000000000..d692c94e7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp
@@ -0,0 +1,500 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.
+//
+// LPC43xx Microcontroller Startup code for use with Red Suite
+//
+// Version : 120430
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+// Code Red - if CMSIS is being used, then SystemInit() routine
+// will be called by startup code rather than in application's main()
+#if defined (__USE_CMSIS)
+#include "LPC43xx.h"
+#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EZH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0s_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC43
+ DAC_IRQHandler, // 16
+ M0CORE_IRQHandler, // 17
+ DMA_IRQHandler, // 18
+ EZH_IRQHandler, // 19
+ FLASH_EEPROM_IRQHandler, // 20
+ ETH_IRQHandler, // 21
+ SDIO_IRQHandler, // 22
+ LCD_IRQHandler, // 23
+ USB0_IRQHandler, // 24
+ USB1_IRQHandler, // 25
+ SCT_IRQHandler, // 26
+ RIT_IRQHandler, // 27
+ TIMER0_IRQHandler, // 28
+ TIMER1_IRQHandler, // 29
+ TIMER2_IRQHandler, // 30
+ TIMER3_IRQHandler, // 31
+ MCPWM_IRQHandler, // 32
+ ADC0_IRQHandler, // 33
+ I2C0_IRQHandler, // 34
+ I2C1_IRQHandler, // 35
+ SPI_IRQHandler, // 36
+ ADC1_IRQHandler, // 37
+ SSP0_IRQHandler, // 38
+ SSP1_IRQHandler, // 39
+ UART0_IRQHandler, // 40
+ UART1_IRQHandler, // 41
+ UART2_IRQHandler, // 42
+ UART3_IRQHandler, // 43
+ I2S0_IRQHandler, // 44
+ I2S1_IRQHandler, // 45
+ SPIFI_IRQHandler, // 46
+ SGPIO_IRQHandler, // 47
+ GPIO0_IRQHandler, // 48
+ GPIO1_IRQHandler, // 49
+ GPIO2_IRQHandler, // 50
+ GPIO3_IRQHandler, // 51
+ GPIO4_IRQHandler, // 52
+ GPIO5_IRQHandler, // 53
+ GPIO6_IRQHandler, // 54
+ GPIO7_IRQHandler, // 55
+ GINT0_IRQHandler, // 56
+ GINT1_IRQHandler, // 57
+ EVRT_IRQHandler, // 58
+ CAN1_IRQHandler, // 59
+ 0, // 60
+ VADC_IRQHandler, // 61
+ ATIMER_IRQHandler, // 62
+ RTC_IRQHandler, // 63
+ 0, // 64
+ WDT_IRQHandler, // 65
+ M0s_IRQHandler, // 66
+ CAN0_IRQHandler, // 67
+ QEI_IRQHandler, // 68
+ };
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//
+//*****************************************************************************
+void
+ResetISR(void) {
+
+// *************************************************************
+// The following conditional block of code manually resets as
+// much of the peripheral set of the LPC43 as possible. This is
+// done because the LPC43 does not provide a means of triggering
+// a full system reset under debugger control, which can cause
+// problems in certain circumstances when debugging.
+//
+// You can prevent this code block being included if you require
+// (for example when creating a final executable which you will
+// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
+//
+#ifndef DONT_RESET_ON_RESTART
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+ // equivalent to CMSIS '__disable_irq()' function
+
+ unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
+ // LPC_RGU->RESET_CTRL0 @ 0x40053100
+ // LPC_RGU->RESET_CTRL1 @ 0x40053104
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+
+ // Write to LPC_RGU->RESET_CTRL0
+ *(RESET_CONTROL+0) = 0x10DF0000;
+ // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
+ // USB1_RST|USB0_RST|LCD_RST
+
+ // Write to LPC_RGU->RESET_CTRL1
+ *(RESET_CONTROL+1) = 0x01DFF7FF;
+ // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
+ // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
+ // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
+ // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
+
+ // Clear all pending interrupts in the NVIC
+ volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
+ unsigned int irqpendloop;
+ for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
+ *(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
+ }
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+ // equivalent to CMSIS '__enable_irq()' function
+
+#endif // ifndef DONT_RESET_ON_RESTART
+// *************************************************************
+
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+/*
+ * Code to enable the Cortex-M4 FPU only included
+ * if appropriate build options have been selected.
+ * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ */
+ // CPACR is located at address 0xE000ED88
+ asm("LDR.W R0, =0xE000ED88");
+ // Read CPACR
+ asm("LDR R1, [R0]");
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ asm(" ORR R1, R1, #(0xF << 20)");
+ // Write back the modified value to the CPACR
+ asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+
+ // ******************************
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+
+#ifdef __USE_CMSIS
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{
+ while(1)
+ {
+ }
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf
new file mode 100644
index 000000000..cc12f1bad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf
@@ -0,0 +1,36 @@
+/* [ROM] */
+define symbol __intvec_start__ = 0x14000000;
+define symbol __region_ROM_start__ = 0x14000000;
+define symbol __region_ROM_end__ = 0x143FFFFF;
+
+/* [RAM] Vector table dynamic copy: 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118*/
+define symbol __NVIC_start__ = 0x10000000;
+define symbol __NVIC_end__ = 0x10000117;
+define symbol __region_RAM_start__ = 0x10000118;
+define symbol __region_RAM_end__ = 0x1001FFDF;
+define symbol _AHB_RAM_start__ = 0x20000000;
+define symbol _AHB_RAM_end__ = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
+place in AHB_RAM_region { section USB_RAM };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/startup_LPC43xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/startup_LPC43xx.s
new file mode 100644
index 000000000..5bcb0670a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/startup_LPC43xx.s
@@ -0,0 +1,292 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD DAC_IRQHandler ; 16 D/A Converter
+ DCD MX_CORE_IRQHandler ; 17 CortexM0 (LPC43XX ONLY)
+ DCD DMA_IRQHandler ; 18 General Purpose DMA
+ DCD 0 ; 19 Reserved
+ DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
+ DCD ETH_IRQHandler ; 21 Ethernet
+ DCD SDIO_IRQHandler ; 22 SD/MMC
+ DCD LCD_IRQHandler ; 23 LCD
+ DCD USB0_IRQHandler ; 24 USB0
+ DCD USB1_IRQHandler ; 25 USB1
+ DCD SCT_IRQHandler ; 26 State Configurable Timer
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
+ DCD TIMER0_IRQHandler ; 28 Timer0
+ DCD TIMER1_IRQHandler ; 29 Timer1
+ DCD TIMER2_IRQHandler ; 30 Timer2
+ DCD TIMER3_IRQHandler ; 31 Timer3
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0
+ DCD I2C0_IRQHandler ; 34 I2C0
+ DCD I2C1_IRQHandler ; 35 I2C1
+ DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1
+ DCD SSP0_IRQHandler ; 38 SSP0
+ DCD SSP1_IRQHandler ; 39 SSP1
+ DCD UART0_IRQHandler ; 40 UART0
+ DCD UART1_IRQHandler ; 41 UART1
+ DCD UART2_IRQHandler ; 42 UART2
+ DCD UART3_IRQHandler ; 43 UART3
+ DCD I2S0_IRQHandler ; 44 I2S0
+ DCD I2S1_IRQHandler ; 45 I2S1
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
+ DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
+ DCD GPIO0_IRQHandler ; 48 GPIO0
+ DCD GPIO1_IRQHandler ; 49 GPIO1
+ DCD GPIO2_IRQHandler ; 50 GPIO2
+ DCD GPIO3_IRQHandler ; 51 GPIO3
+ DCD GPIO4_IRQHandler ; 52 GPIO4
+ DCD GPIO5_IRQHandler ; 53 GPIO5
+ DCD GPIO6_IRQHandler ; 54 GPIO6
+ DCD GPIO7_IRQHandler ; 55 GPIO7
+ DCD GINT0_IRQHandler ; 56 GINT0
+ DCD GINT1_IRQHandler ; 57 GINT1
+ DCD EVRT_IRQHandler ; 58 Event Router
+ DCD CAN1_IRQHandler ; 59 C_CAN1
+ DCD 0
+ DCD 0
+ DCD ATIMER_IRQHandler ; 62 ATIMER
+ DCD RTC_IRQHandler ; 63 RTC
+ DCD 0
+ DCD WDT_IRQHandler ; 65 WDT
+ DCD 0
+ DCD CAN0_IRQHandler ; 67 C_CAN0
+ DCD QEI_IRQHandler ; 68 QEI
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DAC_IRQHandler
+ PUBWEAK MX_CORE_IRQHandler
+ PUBWEAK DMA_IRQHandler
+ PUBWEAK FLASHEEPROM_IRQHandler
+ PUBWEAK ETH_IRQHandler
+ PUBWEAK SDIO_IRQHandler
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USB1_IRQHandler
+ PUBWEAK SCT_IRQHandler
+ PUBWEAK RIT_IRQHandler
+ PUBWEAK TIMER0_IRQHandler
+ PUBWEAK TIMER1_IRQHandler
+ PUBWEAK TIMER2_IRQHandler
+ PUBWEAK TIMER3_IRQHandler
+ PUBWEAK MCPWM_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI_IRQHandler
+ PUBWEAK ADC1_IRQHandler
+ PUBWEAK SSP0_IRQHandler
+ PUBWEAK SSP1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART3_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK I2S1_IRQHandler
+ PUBWEAK SPIFI_IRQHandler
+ PUBWEAK SGPIO_IRQHandler
+ PUBWEAK GPIO0_IRQHandler
+ PUBWEAK GPIO1_IRQHandler
+ PUBWEAK GPIO2_IRQHandler
+ PUBWEAK GPIO3_IRQHandler
+ PUBWEAK GPIO4_IRQHandler
+ PUBWEAK GPIO5_IRQHandler
+ PUBWEAK GPIO6_IRQHandler
+ PUBWEAK GPIO7_IRQHandler
+ PUBWEAK GINT0_IRQHandler
+ PUBWEAK GINT1_IRQHandler
+ PUBWEAK EVRT_IRQHandler
+ PUBWEAK CAN1_IRQHandler
+ PUBWEAK ATIMER_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK CAN0_IRQHandler
+ PUBWEAK QEI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+SVC_Handler
+ B SVC_Handler
+DebugMon_Handler
+ B DebugMon_Handler
+PendSV_Handler
+ B PendSV_Handler
+SysTick_Handler
+ B SysTick_Handler
+HardFault_Handler
+ B HardFault_Handler
+MemManage_Handler
+ B MemManage_Handler
+BusFault_Handler
+ B BusFault_Handler
+UsageFault_Handler
+DAC_IRQHandler
+MX_CORE_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+/* CRP Section - not needed for flashless devices */
+
+;;; SECTION .crp:CODE:ROOT(2)
+;;; DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+;;; DCD 0xFFFFFFFF
+;;;
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis.h
new file mode 100644
index 000000000..40d5b86a6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis.h
@@ -0,0 +1,15 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC43xx specifics
+ *
+ * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC43xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.c
new file mode 100644
index 000000000..fe3e253f5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+
+// The LPC43xx can boot from multiple memories (internal Flash, external NOR,
+// external SPIFI) so we don't know the initial value of VTOR. Thus we use
+// a variable to keep track if the vector table was relocated or not
+static unsigned char vtor_relocated;
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (!vtor_relocated) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ vtor_relocated = 1;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.h
new file mode 100644
index 000000000..b4ec7704a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 53) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c
new file mode 100644
index 000000000..e8d591a51
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c
@@ -0,0 +1,373 @@
+/*
+ * @brief LPC43xx System Initialization
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ *
+ * Modified by Micromint USA <support@micromint.com>
+ */
+#include "LPC43xx.h"
+
+#define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
+
+/* Clock variables */
+#if (CLOCK_SETUP)
+uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
+#else
+uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
+#endif
+
+#if !defined(CORE_M0)
+/* SCU pin definitions for pin muxing */
+typedef struct {
+ __IO uint32_t *reg; /* SCU register address */
+ uint16_t mode; /* SCU pin mode and function */
+} PINMUX_GRP_T;
+
+/* Pins to initialize before clocks are configured */
+static const PINMUX_GRP_T pre_clock_mux[] = {
+ /* SPIFI pins */
+ {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
+ {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
+ {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
+ {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
+ {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
+ {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
+};
+
+/* Pins to initialize after clocks are configured */
+static const PINMUX_GRP_T post_clock_mux[] = {
+ /* Boot pins */
+ {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
+ {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
+ {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
+ {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
+ /* Micromint Bambino 200/210 */
+ {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
+ {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
+ {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
+ /* Micromint Bambino 210 */
+ {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
+ {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
+};
+
+#if (CLOCK_SETUP)
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+ CGU_BASE_CLK_T clk; /* Base clock */
+ CGU_CLKIN_T clkin; /* Base clock source */
+ uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+static const struct CLK_BASE_STATES clock_states[] = {
+ {CLK_BASE_SAFE, CLKIN_IRC, 0},
+ {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
+ {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
+ {CLK_BASE_USB0, CLKIN_USBPLL, 1},
+ {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
+ {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
+ {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
+#if defined(USE_RMII)
+ {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
+#else
+ {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
+#endif
+ {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
+ {CLK_BASE_SSP0, CLKIN_IDIVC, 0},
+ {CLK_BASE_SSP1, CLKIN_IDIVC, 0},
+ {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
+ {CLK_BASE_OUT, CLKINPUT_PD, 0},
+ {CLK_BASE_APLL, CLKINPUT_PD, 0},
+ {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
+ {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
+
+ /* Clocks derived from dividers */
+ {CLK_BASE_LCD, CLKIN_IDIVC, 0},
+ {CLK_BASE_USB1, CLKIN_IDIVD, 1}
+};
+#endif /* defined(CLOCK_SETUP) */
+
+/* Local functions */
+static uint32_t SystemGetMainPLLHz(void);
+static void SystemSetupClock(void);
+static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
+static void SystemSetupMemory(void);
+static void WaitUs(uint32_t us);
+
+#endif /* !defined(CORE_M0) */
+
+/*
+ * SystemInit() - Initialize the system
+ */
+void SystemInit(void)
+{
+#if !defined(CORE_M0)
+
+ /* Initialize vector table in flash */
+#if defined(__ARMCC_VERSION)
+ extern void *__Vectors;
+
+ SCB->VTOR = (unsigned int) &__Vectors;
+#elif defined(__IAR_SYSTEMS_ICC__)
+ extern void *__vector_table;
+
+ SCB->VTOR = (unsigned int) &__vector_table;
+#elif defined(TOOLCHAIN_GCC_ARM)
+ extern void *__isr_vector;
+
+ SCB->VTOR = (unsigned int) &__isr_vector;
+#else /* defined(__GNUC__) and others */
+ extern void *g_pfnVectors;
+
+ SCB->VTOR = (unsigned int) &g_pfnVectors;
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+ /* Initialize floating point */
+ fpuInit();
+#endif
+
+ SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
+ SystemSetupClock(); /* Configure processor and peripheral clocks */
+ SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
+ SystemSetupMemory(); /* Configure external memory */
+#endif /* !defined(CORE_M0) */
+
+ SystemCoreClockUpdate(); /* Update SystemCoreClock variable */
+}
+
+/*
+ * SystemCoreClockUpdate() - Update SystemCoreClock variable
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t reg, div, rate;
+
+ /* Get main PLL rate */
+ rate = SystemGetMainPLLHz();
+
+ /* Get clock divider */
+ reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
+ if (((reg >> 5) & 0x7) == 0) {
+ div = 1;
+ }
+ else {
+ div = 2;
+ }
+ rate = rate / div;
+
+ SystemCoreClock = rate;
+}
+
+/* Returns the frequency of the main PLL */
+uint32_t SystemGetMainPLLHz(void)
+{
+ uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
+ uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
+ uint32_t msel, nsel, psel, direct, fbsel;
+ uint32_t m, n, p;
+ const uint8_t ptab[] = {1, 2, 4, 8};
+
+ msel = (PLLReg >> 16) & 0xFF;
+ nsel = (PLLReg >> 12) & 0x3;
+ psel = (PLLReg >> 8) & 0x3;
+ direct = (PLLReg >> 7) & 0x1;
+ fbsel = (PLLReg >> 6) & 0x1;
+
+ m = msel + 1;
+ n = nsel + 1;
+ p = ptab[psel];
+
+ if (direct || fbsel) {
+ return m * (freq / n);
+ }
+
+ return (m / (2 * p)) * (freq / n);
+}
+
+#if !defined(CORE_M0)
+/*
+ * SystemSetupClock() - Set processor and peripheral clocks
+ *
+ * Clock Frequency Source
+ * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
+ * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
+ * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
+ * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
+ * 120 MHz CLKIN_IDIVD (Disabled)
+ *
+ * 12 MHz CLKIN_IDIVB
+ * 12 MHz CLKIN_IDIVC
+ *
+ */
+void SystemSetupClock(void)
+{
+#if (CLOCK_SETUP)
+ uint32_t i;
+
+ /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
+ LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
+ /* Set prescaler/divider on SSP1 assuming 204 MHz clock */
+ LPC_SSP1->CR1 &= ~(1 << 1);
+ LPC_SSP1->CPSR = 0x0002;
+ LPC_SSP1->CR0 = 0x00006507;
+ LPC_SSP1->CR1 |= (1 << 1);
+
+ /* Enable the oscillator and wait 100 us */
+ LPC_CGU->XTAL_OSC_CTRL = 0;
+ WaitUs(100);
+
+#if (SPIFI_INIT)
+ /* Setup SPIFI control register and no-opcode mode */
+ LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
+ LPC_SPIFI->IDATA = 0xA5;
+ /* Switch IDIVE clock to IRC and connect to SPIFI clock */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
+ LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
+#endif /* SPIFI_INIT */
+
+ /* Configure PLL1 (MAINPLL) for main clock */
+ LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
+
+ /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
+ LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
+ | (CLKIN_MAINPLL << 24);
+ while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
+ WaitUs(100);
+
+ /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
+ LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
+ | (CLKIN_MAINPLL << 24);
+ while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
+
+ /* Connect main clock to PLL1 */
+ LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
+
+ /* Set USB PLL dividers for 480 MHz (for USB0) */
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
+
+ /* Set IDIVE clock to PLL1/2 = 102 MHz */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
+
+ /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
+
+ /* Configure remaining integer dividers */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
+
+ /* Connect base clocks */
+ for (i = 0; i < COUNT_OF(clock_states); i++) {
+ LPC_CGU->BASE_CLK[clock_states[i].clk] =
+ ( clock_states[i].powerdn << 0)
+ | (1 << 11) | (clock_states[i].clkin << 24);
+ }
+#endif /* CLOCK_SETUP */
+ /* Reset peripherals */
+ LPC_RGU->RESET_CTRL0 = 0x105F0000;
+ LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
+}
+
+/*
+ * SystemSetupPins() - Configure MCU pins
+ */
+void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
+{
+ uint32_t i;
+
+ for (i = 0; i < n; i++) {
+ *(mux[i].reg) = mux[i].mode;
+ }
+}
+
+/*
+ * SystemSetupMemory() - Configure external memory
+ */
+void SystemSetupMemory(void)
+{
+#if (MEMORY_SETUP)
+ /* None required for boards without external memory */
+#endif /* MEMORY_SETUP */
+}
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+/*
+ * fpuInit() - Early initialization of the FPU
+ */
+void fpuInit(void)
+{
+ /*
+ * from ARM TRM manual:
+ * ; CPACR is located at address 0xE000ED88
+ * LDR.W R0, =0xE000ED88
+ * ; Read CPACR
+ * LDR R1, [R0]
+ * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+ * ORR R1, R1, #(0xF << 20)
+ * ; Write back the modified value to the CPACR
+ * STR R1, [R0]
+ */
+
+ volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+ volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+ volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+ volatile uint32_t Cpacr;
+ volatile uint32_t Mvfr0;
+ volatile uint32_t Mvfr1;
+ char vfpPresent = 0;
+
+ Mvfr0 = *regMvfr0;
+ Mvfr1 = *regMvfr1;
+
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+ if (vfpPresent) {
+ Cpacr = *regCpacr;
+ Cpacr |= (0xF << 20);
+ *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
+ }
+}
+#endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
+
+/* Approximate delay function */
+#define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000)
+
+static void WaitUs(uint32_t us)
+{
+ volatile uint32_t cyc = us * CPU_NANOSEC(1000) / 4;
+ while (cyc--)
+ ;
+}
+
+#endif /* !defined(CORE_M0) */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h
new file mode 100644
index 000000000..dcea2ffd4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h
@@ -0,0 +1,90 @@
+/*
+ * @brief LPC43xx/LPC18xx mcu header
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYSTEM_LPC43XX_H
+#define __SYSTEM_LPC43XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System initialization options */
+#define PIN_SETUP 1 /* Configure pins during initialization */
+#define CLOCK_SETUP 1 /* Configure clocks during initialization */
+#define MEMORY_SETUP 0 /* Configure external memory during init */
+#define SPIFI_INIT 1 /* Initialize SPIFI */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Default CPU clock frequency */
+#if defined(CHIP_LPC43XX)
+#define MAX_CLOCK_FREQ (204000000)
+#else
+#define MAX_CLOCK_FREQ (180000000)
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+ /* FPU declarations */
+ #define LPC_CPACR 0xE000ED88
+
+ #define SCB_MVFR0 0xE000EF40
+ #define SCB_MVFR0_RESET 0x10110021
+
+ #define SCB_MVFR1 0xE000EF44
+ #define SCB_MVFR1_RESET 0x11000011
+
+ #if defined(__ARMCC_VERSION)
+ void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE")));
+ #else
+ extern void fpuInit(void);
+ #endif
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC43XX_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h
new file mode 100644
index 000000000..a6df8ea12
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h
@@ -0,0 +1,710 @@
+/****************************************************************************
+ * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
+ * Project: NXP LPC8xx software example
+ *
+ * Description:
+ * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
+ * NXP LPC800 Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors'
+ * relevant copyright in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+****************************************************************************/
+#ifndef __LPC8xx_H__
+#define __LPC8xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
+ This file defines all structures and symbols for LPC8xx:
+ - Registers and bitfields
+ - peripheral base address
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
+ Configuration of the Cortex-M0+ Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC8xx Specific Interrupt Numbers ********************************************************/
+ SPI0_IRQn = 0, /*!< SPI0 */
+ SPI1_IRQn = 1, /*!< SPI1 */
+ Reserved0_IRQn = 2, /*!< Reserved Interrupt */
+ UART0_IRQn = 3, /*!< USART0 */
+ UART1_IRQn = 4, /*!< USART1 */
+ UART2_IRQn = 5, /*!< USART2 */
+ Reserved1_IRQn = 6, /*!< Reserved Interrupt */
+ Reserved2_IRQn = 7, /*!< Reserved Interrupt */
+ I2C_IRQn = 8, /*!< I2C */
+ SCT_IRQn = 9, /*!< SCT */
+ MRT_IRQn = 10, /*!< MRT */
+ CMP_IRQn = 11, /*!< CMP */
+ WDT_IRQn = 12, /*!< WDT */
+ BOD_IRQn = 13, /*!< BOD */
+ Reserved3_IRQn = 14, /*!< Reserved Interrupt */
+ WKT_IRQn = 15, /*!< WKT Interrupt */
+ Reserved4_IRQn = 16, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 17, /*!< Reserved Interrupt */
+ Reserved6_IRQn = 18, /*!< Reserved Interrupt */
+ Reserved7_IRQn = 19, /*!< Reserved Interrupt */
+ Reserved8_IRQn = 20, /*!< Reserved Interrupt */
+ Reserved9_IRQn = 21, /*!< Reserved Interrupt */
+ Reserved10_IRQn = 22, /*!< Reserved Interrupt */
+ Reserved11_IRQn = 23, /*!< Reserved Interrupt */
+ PININT0_IRQn = 24, /*!< External Interrupt 0 */
+ PININT1_IRQn = 25, /*!< External Interrupt 1 */
+ PININT2_IRQn = 26, /*!< External Interrupt 2 */
+ PININT3_IRQn = 27, /*!< External Interrupt 3 */
+ PININT4_IRQn = 28, /*!< External Interrupt 4 */
+ PININT5_IRQn = 29, /*!< External Interrupt 5 */
+ PININT6_IRQn = 30, /*!< External Interrupt 6 */
+ PININT7_IRQn = 31, /*!< External Interrupt 7 */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC8xx_CMSIS */
+
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_LPC8xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
+ uint32_t RESERVED6[18];
+
+ __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
+ __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
+ uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ uint32_t RESERVED11[27];
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_SYSCON */
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
+ __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_IOCON */
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0;
+} LPC_FLASHCTRL_TypeDef;
+/*@}*/ /* end of group LPC8xx_FLASHCTRL */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC8xx_PMU */
+
+
+/*------------- Switch Matrix Port --------------------------*/
+/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t PINASSIGN[9];
+ struct {
+ __IO uint32_t PINASSIGN0;
+ __IO uint32_t PINASSIGN1;
+ __IO uint32_t PINASSIGN2;
+ __IO uint32_t PINASSIGN3;
+ __IO uint32_t PINASSIGN4;
+ __IO uint32_t PINASSIGN5;
+ __IO uint32_t PINASSIGN6;
+ __IO uint32_t PINASSIGN7;
+ __IO uint32_t PINASSIGN8;
+ };
+ };
+ __I uint32_t RESERVED0[103];
+ __IO uint32_t PINENABLE0;
+} LPC_SWM_TypeDef;
+/*@}*/ /* end of group LPC8xx_SWM */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
+ __I uint16_t RESERVED0[2039];
+ __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ uint32_t RESERVED1[1006];
+ __IO uint32_t DIR0; /* 0x2000 */
+ uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /* 0x2080 */
+ uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /* 0x2100 */
+ uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /* 0x2180 */
+ uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /* 0x2200 */
+ uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /* 0x2280 */
+ uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /* 0x2300 */
+
+} LPC_GPIO_PORT_TypeDef;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
+} LPC_PIN_INT_TypeDef;
+
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+/** @addtogroup LPC8xx_CRC
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ __O uint32_t WR_DATA_DWORD;
+ __O uint16_t WR_DATA_WORD;
+ uint16_t RESERVED_WORD;
+ __O uint8_t WR_DATA_BYTE;
+ uint8_t RESERVED_BYTE[3];
+ };
+} LPC_CRC_TypeDef;
+/*@}*/ /* end of group LPC8xx_CRC */
+
+/*------------- Comparator (CMP) --------------------------------------------------*/
+/** @addtogroup LPC8xx_CMP LPC8xx Comparator
+ @{
+*/
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_TypeDef;
+/*@}*/ /* end of group LPC8xx_CMP */
+
+
+/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
+/** @addtogroup LPC8xx_WKT
+ @{
+*/
+typedef struct { /*!< (@ 0x40028000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
+ uint32_t Reserved[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
+} LPC_WKT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WKT */
+
+/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
+//New, Copied from lpc824
+/**
+ * @brief Multi-Rate Timer (MRT) (MRT)
+ */
+typedef struct { /*!< (@ 0x40004000) MRT Structure */
+ __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
+ __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
+ __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
+ __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
+ __I uint32_t RESERVED0[45];
+ __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
+ the number of the first idle channel. */
+ __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
+} LPC_MRT_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
+/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+/**
+ * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
+ */
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t CTRL;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDATA;
+ __I uint32_t RXDATA_STAT;
+ __IO uint32_t TXDATA;
+ __IO uint32_t BRG; /* 0x20 */
+ __IO uint32_t INTSTAT;
+} LPC_USART_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_USART */
+
+
+/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
+/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t DLY;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDAT;
+ __IO uint32_t TXDATCTL;
+ __IO uint32_t TXDAT;
+ __IO uint32_t TXCTRL; /* 0x20 */
+ __IO uint32_t DIV;
+ __I uint32_t INTSTAT;
+} LPC_SPI_TypeDef;
+/*@}*/ /* end of group LPC8xx_SPI */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC8xx_I2C I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR;
+ __IO uint32_t TIMEOUT; /* 0x10 */
+ __IO uint32_t DIV;
+ __IO uint32_t INTSTAT;
+ uint32_t Reserved0[1];
+ __IO uint32_t MSTCTL; /* 0x20 */
+ __IO uint32_t MSTTIME;
+ __IO uint32_t MSTDAT;
+ uint32_t Reserved1[5];
+ __IO uint32_t SLVCTL; /* 0x40 */
+ __IO uint32_t SLVDAT;
+ __IO uint32_t SLVADR0;
+ __IO uint32_t SLVADR1;
+ __IO uint32_t SLVADR2; /* 0x50 */
+ __IO uint32_t SLVADR3;
+ __IO uint32_t SLVQUAL0;
+ uint32_t Reserved2[9];
+ __I uint32_t MONRXDAT; /* 0x80 */
+} LPC_I2C_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_I2C */
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
+ */
+
+#define CONFIG_SCT_nEV (6) /* Number of events */
+#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (4) /* Number of outputs */
+
+typedef struct
+{
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* 0x004 low control register */
+ __IO uint16_t CTRL_H; /* 0x006 high control register */
+ };
+ };
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
+ __IO uint16_t START_L; /* 0x014 start register for counter L */
+ __IO uint16_t START_H; /* 0x016 start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* 0x040 counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
+ };
+ };
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */
+ __I uint32_t INPUT; /* 0x048 input register */
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* 0x050 output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
+ __IO uint32_t RES; /* 0x058 conflict resolution register */
+ uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
+
+ union {
+ __IO union { /* 0x100-... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+ } MATCH[CONFIG_SCT_nRG];
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to H value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+ } CAP[CONFIG_SCT_nRG];
+ };
+
+
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+
+
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+ } MATCHREL[CONFIG_SCT_nRG];
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+ } CAPCTRL[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+
+} LPC_SCT_TypeDef;
+/*@}*/ /* end of group LPC8xx_SCT */
+
+
+/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
+/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
+ uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
+ __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+ __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WWDT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WDT */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_ROM_BASE (0x1FFF0000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
+
+#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
+#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
+#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
+#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
+#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
+#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
+
+/* AHB peripherals */
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
+
+#define LPC_GPIO_PORT_BASE (0xA0000000)
+#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
+#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
+
+
+#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
+#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
+
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
+#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
+#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
+#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
+#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
+
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
+
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
+#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC8xx_H__ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct
new file mode 100644
index 000000000..84f5f32f5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x1000 { ; load region size_region (4k)
+ ER_IROM1 0x00000000 0x1000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 0xC0
+ ; 1KB(0x0400) - 0xC0 = 0x340
+ RW_IRAM1 (0x10000000+0xC0) (0x400-0xC0) {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 000000000..816264f05
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,211 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10000400
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C_IRQHandler ; I2C controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD 0 ; Reserved
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+
+ EXPORT WKT_IRQHandler [WEAK]
+
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf
new file mode 100644
index 000000000..4edf56832
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00000FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x100003FF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s
new file mode 100644
index 000000000..5ab319685
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.s
@@ -0,0 +1,197 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C_IRQHandler ; I2C controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD 0 ; Reserved
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK SCT_IRQHandler
+ PUBWEAK MRT_IRQHandler
+ PUBWEAK CMP_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK WKT_IRQHandler
+ PUBWEAK PININT0_IRQHandler
+ PUBWEAK PININT1_IRQHandler
+ PUBWEAK PININT2_IRQHandler
+ PUBWEAK PININT3_IRQHandler
+ PUBWEAK PININT4_IRQHandler
+ PUBWEAK PININT5_IRQHandler
+ PUBWEAK PININT6_IRQHandler
+ PUBWEAK PININT7_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c
new file mode 100644
index 000000000..e107ed2eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c
@@ -0,0 +1,372 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC8xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> CLKIN pin
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+
+// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
+#define CLOCK_SETUP 1
+//use PLL for IRC
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
+//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
+//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+
+//Replaced SystemCoreClock with MainClock
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ MainClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ MainClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ MainClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ MainClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ MainClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct
new file mode 100644
index 000000000..59bde7510
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x4000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x4000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0xF40
+ RW_IRAM1 0x100000C0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 000000000..967a3c4db
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,211 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10001000
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C_IRQHandler ; I2C controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD 0 ; Reserved
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+
+ EXPORT WKT_IRQHandler [WEAK]
+
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf
new file mode 100644
index 000000000..328cbc30c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00003FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s
new file mode 100644
index 000000000..48ead87f4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s
@@ -0,0 +1,198 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C_IRQHandler ; I2C controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD 0 ; Reserved
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK I2C_IRQHandler
+ PUBWEAK SCT_IRQHandler
+ PUBWEAK MRT_IRQHandler
+ PUBWEAK CMP_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK WKT_IRQHandler
+ PUBWEAK PININT0_IRQHandler
+ PUBWEAK PININT1_IRQHandler
+ PUBWEAK PININT2_IRQHandler
+ PUBWEAK PININT3_IRQHandler
+ PUBWEAK PININT4_IRQHandler
+ PUBWEAK PININT5_IRQHandler
+ PUBWEAK PININT6_IRQHandler
+ PUBWEAK PININT7_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c
new file mode 100644
index 000000000..c96d6c446
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c
@@ -0,0 +1,381 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC8xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> CLKIN pin
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+//Fixed to use PLL
+#if (CLOCK_SETUP == 1)
+//use PLL for IRC
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
+ #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
+ #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
+
+#elif (CLOCK_SETUP == 2)
+//use PLL for XTAL
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
+ #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
+#endif
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+//Replaced SystemCoreClock with MainClock
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ MainClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ MainClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ MainClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ MainClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ MainClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h
new file mode 100644
index 000000000..12302cc3a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC8xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c
new file mode 100644
index 000000000..ee0e4a718
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h
new file mode 100644
index 000000000..e95975d0a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t MainClock; /*!< Main Clock Frequency */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
new file mode 100644
index 000000000..fee91c063
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h
@@ -0,0 +1,1308 @@
+
+/****************************************************************************************************//**
+ * @file LPC82x.h
+ *
+ * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
+ * LPC82x from .
+ *
+ * @version V0.4
+ * @date 17. June 2014
+ *
+ * @note Generated with SVDConv V2.80
+ * from CMSIS SVD File 'LPC82x.svd' Version 0.4,
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC82x
+ * @{
+ */
+
+#ifndef LPC82X_H
+#define LPC82X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
+ SPI0_IRQn = 0, /*!< 0 SPI0 */
+ SPI1_IRQn = 1, /*!< 1 SPI1 */
+ UART0_IRQn = 3, /*!< 3 UART0 */
+ UART1_IRQn = 4, /*!< 4 UART1 */
+ UART2_IRQn = 5, /*!< 5 UART2 */
+ I2C1_IRQn = 7, /*!< 7 I2C1 */
+ I2C0_IRQn = 8, /*!< 8 I2C0 */
+ SCT_IRQn = 9, /*!< 9 SCT */
+ MRT_IRQn = 10, /*!< 10 MRT */
+ CMP_IRQn = 11, /*!< 11 CMP */
+ WDT_IRQn = 12, /*!< 12 WDT */
+ BOD_IRQn = 13, /*!< 13 BOD */
+ FLASH_IRQn = 14, /*!< 14 FLASH */
+ WKT_IRQn = 15, /*!< 15 WKT */
+ ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */
+ ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */
+ ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */
+ ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */
+ DMA_IRQn = 20, /*!< 20 DMA */
+ I2C2_IRQn = 21, /*!< 21 I2C2 */
+ I2C3_IRQn = 22, /*!< 22 I2C3 */
+ PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */
+ PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */
+ PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */
+ PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */
+ PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */
+ PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */
+ PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */
+ PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
+#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
+#include "system_LPC82x.h" /*!< LPC82x System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ WWDT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Windowed Watchdog Timer (WWDT) (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40000000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
+ the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
+ register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
+ followed by 0x55 to this register reloads the Watchdog timer
+ with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
+ reads out the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+/* ================================================================================ */
+/* ================ MRT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Multi-Rate Timer (MRT) (MRT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) MRT Structure */
+ __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
+ __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
+ __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
+ __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
+ is loaded into the TIMER0 register. */
+ __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
+ value of the down-counter. */
+ __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
+ the MRT0 modes. */
+ __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
+ __I uint32_t RESERVED0[45];
+ __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
+ the number of the first idle channel. */
+ __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
+} LPC_MRT_Type;
+
+
+/* ================================================================================ */
+/* ================ WKT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Self wake-up timer (WKT) (WKT)
+ */
+
+typedef struct { /*!< (@ 0x40008000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */
+} LPC_WKT_Type;
+
+
+/* ================================================================================ */
+/* ================ SWM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Switch matrix (SWM) (SWM)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) SWM Structure */
+ union {
+ __IO uint32_t PINASSIGN[12];
+ struct {
+ __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
+ U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
+ __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
+ U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
+ __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
+ U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
+ __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
+ U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
+ __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
+ SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
+ __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
+ SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
+ __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
+ SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
+ __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
+ SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
+ __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
+ SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
+ __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
+ SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
+ __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
+ I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
+ __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
+ ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
+ };
+ };
+ __I uint32_t RESERVED0[100];
+ __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
+ ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
+ VDDCMP. */
+} LPC_SWM_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
+ value, enable bits for each sequence and the A/D power-down
+ bit. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
+ triggering and channel selection for conversion sequence-A.
+ Also specifies interrupt mode for sequence-A. */
+ __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
+ triggering and channel selection for conversion sequence-B.
+ Also specifies interrupt mode for sequence-B. */
+ __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-A */
+ __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
+ contains the result of the most recent A/D conversion performed
+ under sequence-B */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
+ the result of the most recent conversion completed on channel
+ 0. */
+ __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
+ the lower threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 0. */
+ __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
+ the upper threshold level for automatic threshold comparison
+ for any channels linked to threshold pair 1. */
+ __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
+ which set of threshold compare registers are to be used for
+ each channel */
+ __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
+ contains enable bits that enable the sequence-A, sequence-B,
+ threshold compare and data overrun interrupts to be generated. */
+ __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
+ request flags and the individual component overrun and threshold-compare
+ flags. (The overrun bits replicate information stored in the
+ result registers). */
+ __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */
+} LPC_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================ PMU ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power Management Unit (PMU) (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */
+ __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */
+ __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
+ bits for general purpose storage. */
+} LPC_PMU_Type;
+
+
+/* ================================================================================ */
+/* ================ CMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Analog comparator (CMP)
+ */
+
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_Type;
+
+
+/* ================================================================================ */
+/* ================ DMATRIGMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA trigger mux (DMATRIGMUX)
+ */
+
+typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */
+ __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+ __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
+ connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
+ interrupts, and DMA requests. */
+} LPC_DMATRIGMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ INPUTMUX ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Input multiplexing (INPUTMUX)
+ */
+
+typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */
+ __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
+ Selects from 18 DMA trigger outputs. */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */
+ __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */
+} LPC_INPUTMUX_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASHCTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Flash controller (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
+} LPC_FLASHCTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ IOCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I/O configuration (IOCON) (IOCON)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCON Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
+ pin configuration for the true open-drain pin. */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+ __I uint32_t RESERVED1;
+ __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */
+ __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */
+ __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */
+ __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */
+ __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */
+} LPC_IOCON_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCON ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief System configuration (SYSCON) (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __I uint32_t RESERVED3[10];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */
+ __I uint32_t RESERVED6[18];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
+ divider value */
+ __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
+ multiplier value */
+ __I uint32_t RESERVED8;
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
+ glitch filter */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED11[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
+ latency and determinism. */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ union {
+ __IO uint32_t PINTSEL[8];
+ struct {
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */
+ };
+ };
+ __I uint32_t RESERVED12[27];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */
+ __I uint32_t RESERVED14[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED15[111];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
+} LPC_SYSCON_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C0-bus interface (I2C0)
+ */
+
+typedef struct { /*!< (@ 0x40050000) I2C0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */
+ __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
+ functions. */
+ __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */
+ __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */
+ __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */
+ __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
+ determines what time increments are used for the MSTTIME and
+ SLVTIME registers. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
+ and Monitor functions. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */
+ __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */
+ __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
+ register. */
+ __I uint32_t RESERVED1[5];
+ __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */
+ __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
+ register. */
+ union {
+ __IO uint32_t SLVADR[4];
+ struct {
+ __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */
+ __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */
+ __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */
+ __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */
+ };
+ };
+ __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */
+ __I uint32_t RESERVED2[9];
+ __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */
+} LPC_I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ SPI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40058000) SPI0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */
+ __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */
+ __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
+ by writing a 1 to that bit position */
+ __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
+ value may be read from this register. Writing a 1 to any implemented
+ bit position causes that bit to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
+ implemented bit position causes the corresponding bit in INTENSET
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */
+ __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */
+ __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */
+ __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */
+ __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */
+ __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */
+} LPC_SPI0_Type;
+
+
+/* ================================================================================ */
+/* ================ USART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief USART0 (USART0)
+ */
+
+typedef struct { /*!< (@ 0x40064000) USART0 Structure */
+ __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
+ settings that typically are not changed during operation. */
+ __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
+ that are more likely to change during operation. */
+ __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
+ can be read here. Writing ones clears some bits in the register.
+ Some bits can be cleared by writing a 1 to them. */
+ __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
+ an individual interrupt enable bit for each potential USART
+ interrupt. A complete value may be read from this register.
+ Writing a 1 to any implemented bit position causes that bit
+ to be set. */
+ __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
+ any combination of bits in the INTENSET register. Writing a
+ 1 to any implemented bit position causes the corresponding bit
+ to be cleared. */
+ __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
+ received. */
+ __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
+ the last character received with the current USART receive status.
+ Allows DMA or software to recover incoming data and status together. */
+ __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
+ is written here. */
+ __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
+ baud rate divisor value. */
+ __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
+ that are currently enabled. */
+ __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
+ communication. */
+ __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */
+} LPC_USART0_Type;
+
+
+/* ================================================================================ */
+/* ================ CRC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) engine (CRC)
+ */
+
+typedef struct { /*!< (@ 0x50000000) CRC Structure */
+ __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */
+ __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */
+
+ union {
+ __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */
+ __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */
+ };
+} LPC_CRC_Type;
+
+
+/* ================================================================================ */
+/* ================ SCT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+typedef struct { /*!< (@ 0x50004000) SCT Structure */
+ __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */
+ __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */
+ __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */
+ __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */
+ __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */
+ __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */
+ __I uint32_t RESERVED0[10];
+ __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */
+ __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */
+ __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */
+ __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */
+ __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */
+ __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */
+ __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */
+ __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */
+ __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */
+ __I uint32_t RESERVED1[35];
+ __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */
+ __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */
+ __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */
+ __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */
+
+union {
+ union {
+ __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
+ 7; REGMOD0 to REGMODE7 = 1 */
+ __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
+ to 7; REGMOD0 to REGMODE7 = 0 */
+ };
+ __IO uint32_t CAP[8];
+ __IO uint32_t MATCH[8];
+};
+ __I uint32_t RESERVED2[56];
+
+ union {
+ struct {
+ union {
+ __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+
+ union {
+ __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
+ = 1 to REGMODE7 = 1 */
+ __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
+ = 0 to REGMODE7 = 0 */
+ };
+ };
+ __IO uint32_t MATCHREL[8];
+ };
+ __I uint32_t RESERVED3[56];
+
+ union {
+ struct {
+ __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */
+ __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */
+ __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */
+ __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */
+ __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */
+ __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */
+ __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */
+ __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */
+ __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */
+ __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */
+ __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */
+ __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */
+ __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */
+ __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */
+ __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */
+ __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */
+ };
+ __IO struct {
+ uint32_t STATE;
+ uint32_t CTRL;
+ } EVENT[8];
+ };
+
+ __I uint32_t RESERVED4[112];
+
+ union {
+ struct {
+ __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */
+ __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */
+ __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */
+ __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */
+ __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */
+ __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */
+ __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */
+ __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */
+ __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */
+ __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */
+ __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */
+ __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */
+ };
+ __IO struct {
+ uint32_t SET;
+ uint32_t CLR;
+ } OUT[6];
+};
+
+} LPC_SCT_Type;
+
+
+/* ================================================================================ */
+/* ================ DMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief DMA controller (DMA)
+ */
+
+typedef struct { /*!< (@ 0x50008000) DMA Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */
+ __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */
+ __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED1;
+ __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED2;
+ __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */
+ __I uint32_t RESERVED3;
+ __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */
+ __I uint32_t RESERVED6;
+ __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */
+ __I uint32_t RESERVED8;
+ __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */
+ __I uint32_t RESERVED9;
+ __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */
+ __I uint32_t RESERVED10;
+ __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */
+ __I uint32_t RESERVED11;
+ __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */
+ __I uint32_t RESERVED12[225];
+ __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED13;
+ __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED14;
+ __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED16;
+ __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED17;
+ __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED18;
+ __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED19;
+ __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED20;
+ __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED21;
+ __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED22;
+ __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED23;
+ __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED24;
+ __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED25;
+ __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED26;
+ __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED27;
+ __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED28;
+ __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
+ 0. */
+ __I uint32_t RESERVED29;
+ __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */
+ __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */
+ __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
+ 0. */
+} LPC_DMA_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIO_PORT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief General Purpose I/O port (GPIO) (GPIO_PORT)
+ */
+
+typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */
+ __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
+ __I uint8_t RESERVED0[4067];
+ __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */
+ __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */
+ __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */
+ __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */
+ __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */
+ __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */
+ __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */
+ __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */
+ __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */
+ __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */
+ __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */
+ __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */
+ __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */
+ __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */
+ __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */
+ __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */
+ __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */
+ __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */
+ __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */
+ __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */
+ __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */
+ __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */
+ __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */
+ __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */
+ __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */
+ __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */
+ __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */
+ __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */
+ __I uint32_t RESERVED1[995];
+ __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */
+ __I uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */
+ __I uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */
+ __I uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
+ for port 0 */
+ __I uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */
+ __I uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */
+ __I uint32_t RESERVED8[31];
+ __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */
+ __I uint32_t RESERVED9[31];
+ __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */
+ __I uint32_t RESERVED10[31];
+ __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */
+} LPC_GPIO_PORT_Type;
+
+
+/* ================================================================================ */
+/* ================ PIN_INT ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Pin interrupt and pattern match engine (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
+ enable register */
+ __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
+ register */
+ __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
+ clear register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
+ enable register */
+ __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
+ set register */
+ __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
+ clear register */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
+ register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
+ register */
+} LPC_PIN_INT_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT_BASE 0x40000000UL
+#define LPC_MRT_BASE 0x40004000UL
+#define LPC_WKT_BASE 0x40008000UL
+#define LPC_SWM_BASE 0x4000C000UL
+#define LPC_ADC_BASE 0x4001C000UL
+#define LPC_PMU_BASE 0x40020000UL
+#define LPC_CMP_BASE 0x40024000UL
+#define LPC_DMATRIGMUX_BASE 0x40028000UL
+#define LPC_INPUTMUX_BASE 0x4002C000UL
+#define LPC_FLASHCTRL_BASE 0x40040000UL
+#define LPC_IOCON_BASE 0x40044000UL
+#define LPC_SYSCON_BASE 0x40048000UL
+#define LPC_I2C0_BASE 0x40050000UL
+#define LPC_I2C1_BASE 0x40054000UL
+#define LPC_SPI0_BASE 0x40058000UL
+#define LPC_SPI1_BASE 0x4005C000UL
+#define LPC_USART0_BASE 0x40064000UL
+#define LPC_USART1_BASE 0x40068000UL
+#define LPC_USART2_BASE 0x4006C000UL
+#define LPC_I2C2_BASE 0x40070000UL
+#define LPC_I2C3_BASE 0x40074000UL
+#define LPC_CRC_BASE 0x50000000UL
+#define LPC_SCT_BASE 0x50004000UL
+#define LPC_DMA_BASE 0x50008000UL
+#define LPC_GPIO_PORT_BASE 0xA0000000UL
+#define LPC_PIN_INT_BASE 0xA0004000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
+#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
+#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
+#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
+#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
+#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
+#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
+#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
+#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
+#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
+#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
+#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
+#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
+#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
+#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC82x */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC82x_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
new file mode 100644
index 000000000..310aa8219
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 000000000..a90d8d290
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,218 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10002000
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT Flash_IRQHandler [WEAK]
+ EXPORT WKT_IRQHandler [WEAK]
+ EXPORT ADC_SEQA_IRQHandler [WEAK]
+ EXPORT ADC_SEQB_IRQHandler [WEAK]
+ EXPORT ADC_THCMP_IRQHandler [WEAK]
+ EXPORT ADC_OVR_IRQHandler [WEAK]
+ EXPORT DMA__RQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT I2C3_IRQHandler [WEAK]
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld
new file mode 100644
index 000000000..be901736a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld
@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
new file mode 100644
index 000000000..c4273d680
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC824 interrupts */
+ .long SPI0_IRQHandler // SPI0 controller
+ .long SPI1_IRQHandler // SPI1 controller
+ .long 0 // Reserved
+ .long UART0_IRQHandler // UART0
+ .long UART1_IRQHandler // UART1
+ .long UART2_IRQHandler // UART2
+ .long 0 // Reserved
+ .long I2C1_IRQHandler // I2C ch1 controller
+ .long I2C0_IRQHandler // I2C ch0 controller
+ .long SCT_IRQHandler // Smart Counter Timer
+ .long MRT_IRQHandler // Multi-Rate Timer
+ .long CMP_IRQHandler // Comparator
+ .long WDT_IRQHandler // PIO1 (0:11)
+ .long BOD_IRQHandler // Brown Out Detect
+ .long Flash_IRQHandler // Flash interrupt
+ .long WKT_IRQHandler // Wakeup timer
+ .long ADC_SEQA_IRQHandler // ADC sequence A completion
+ .long ADC_SEQB_IRQHandler // ADC sequence B completion
+ .long ADC_THCMP_IRQHandler // ADC threshold compare
+ .long ADC_OVR_IRQHandler // ADC overrun
+ .long DMA_IRQHandler // DMA interrupt
+ .long I2C2_IRQHandler // I2C2 controller
+ .long I2C3_IRQHandler // I2C3 controller
+ .long 0 // Reserved
+ .long PININT0_IRQHandler // PIO INT0
+ .long PININT1_IRQHandler // PIO INT1
+ .long PININT2_IRQHandler // PIO INT2
+ .long PININT3_IRQHandler // PIO INT3
+ .long PININT4_IRQHandler // PIO INT4
+ .long PININT5_IRQHandler // PIO INT5
+ .long PININT6_IRQHandler // PIO INT6
+ .long PININT7_IRQHandler // PIO INT7
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler I2C3_IRQHandler
+ def_irq_default_handler SCT_IRQHandler
+ def_irq_default_handler MRT_IRQHandler
+ def_irq_default_handler CMP_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler Flash_IRQHandler
+ def_irq_default_handler WKT_IRQHandler
+ def_irq_default_handler ADC_SEQA_IRQHandler
+ def_irq_default_handler ADC_SEQB_IRQHandler
+ def_irq_default_handler ADC_THCMP_IRQHandler
+ def_irq_default_handler ADC_OVR_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler PININT0_IRQHandler
+ def_irq_default_handler PININT1_IRQHandler
+ def_irq_default_handler PININT2_IRQHandler
+ def_irq_default_handler PININT3_IRQHandler
+ def_irq_default_handler PININT4_IRQHandler
+ def_irq_default_handler PININT5_IRQHandler
+ def_irq_default_handler PININT6_IRQHandler
+ def_irq_default_handler PININT7_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld
new file mode 100644
index 000000000..8774dea29
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld
@@ -0,0 +1,199 @@
+/*Based on following file
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC824
+ * Created from generic_c.ld (LPCXpresso v7.4 (0 [Build 229] [2014-09-16] ))
+ * By LPCXpresso v7.4.0 [Build 229] [2014-09-16] on Fri Jan 02 03:36:48 JST 2015
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RamLoc8 (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x8000;
+ __top_RamLoc8 = 0x10000000 + 0x2000;
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+/*GROUP(libcr_nohost.a libcr_c.a libcr_eabihelpers.a libm.a)*/
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+ } >MFlash32
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+
+
+
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* MAIN DATA SECTION */
+
+ /* Default MTB section */
+ .mtb_buffer_default (NOLOAD) :
+ {
+ KEEP(*(.mtb*))
+ } > RamLoc8
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc8
+
+
+ /* Main DATA section (RamLoc8) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc8 AT>MFlash32
+
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc8
+
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp
new file mode 100644
index 000000000..e40d1ada2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp
@@ -0,0 +1,351 @@
+//*****************************************************************************
+// LPC82x Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 140901
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products. This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+// Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+// Location in memory that holds the address of the ROM Driver table
+#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
+// Variables to store addresses of idiv and udiv functions within MCU ROM
+unsigned int *pDivRom_idiv;
+unsigned int *pDivRom_uidiv;
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void WKT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#else
+extern int main(void);
+#endif
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM0plus
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ 0, // Reserved
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC82x
+ SPI0_IRQHandler, // SPI0 controller
+ SPI1_IRQHandler, // SPI1 controller
+ 0, // Reserved
+ UART0_IRQHandler, // UART0
+ UART1_IRQHandler, // UART1
+ UART2_IRQHandler, // UART2
+ 0, // Reserved
+ I2C1_IRQHandler, // I2C1 controller
+ I2C0_IRQHandler, // I2C0 controller
+ SCT_IRQHandler, // Smart Counter Timer
+ MRT_IRQHandler, // Multi-Rate Timer
+ CMP_IRQHandler, // Comparator
+ WDT_IRQHandler, // Watchdog
+ BOD_IRQHandler, // Brown Out Detect
+ FLASH_IRQHandler, // Flash Interrupt
+ WKT_IRQHandler, // Wakeup timer
+ ADC_SEQA_IRQHandler, // ADC sequence A completion
+ ADC_SEQB_IRQHandler, // ADC sequence B completion
+ ADC_THCMP_IRQHandler, // ADC threshold compare
+ ADC_OVR_IRQHandler, // ADC overrun
+ DMA_IRQHandler, // DMA
+ I2C2_IRQHandler, // I2C2 controller
+ I2C3_IRQHandler, // I2C3 controller
+ 0, // Reserved
+ PIN_INT0_IRQHandler, // PIO INT0
+ PIN_INT1_IRQHandler, // PIO INT1
+ PIN_INT2_IRQHandler, // PIO INT2
+ PIN_INT3_IRQHandler, // PIO INT3
+ PIN_INT4_IRQHandler, // PIO INT4
+ PIN_INT5_IRQHandler, // PIO INT5
+ PIN_INT6_IRQHandler, // PIO INT6
+ PIN_INT7_IRQHandler, // PIO INT7
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+ // Patch the AEABI integer divide functions to use MCU's romdivide library
+#ifdef __USE_ROMDIVIDE
+ // Get address of Integer division routines function table in ROM
+ unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
+ // Get addresses of integer divide routines in ROM
+ // These address are then used by the code in aeabi_romdiv_patch.s
+ pDivRom_idiv = (unsigned int *)div_ptr[0];
+ pDivRom_uidiv = (unsigned int *)div_ptr[1];
+#endif
+
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{ while(1) {}
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf
new file mode 100644
index 000000000..16aac8518
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0xA00;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK };
+place in CRP_region { section .crp };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s
new file mode 100644
index 000000000..e02868b54
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s
@@ -0,0 +1,216 @@
+/**************************************************
+ *
+ * Part one of the system initialization code, contains low-level
+ * initialization, plain thumb variant.
+ *
+ * Copyright 2011 IAR Systems. All rights reserved.
+ *
+ * $Revision: 47876 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SCT_IRQHandler
+ PUBWEAK MRT_IRQHandler
+ PUBWEAK CMP_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK Flash_IRQHandler
+ PUBWEAK WKT_IRQHandler
+ PUBWEAK ADC_SEQA_IRQHandler
+ PUBWEAK ADC_SEQB_IRQHandler
+ PUBWEAK ADC_THCMP_IRQHandler
+ PUBWEAK ADC_OVR_IRQHandler
+ PUBWEAK DMA__RQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK I2C3_IRQHandler
+ PUBWEAK PININT0_IRQHandler
+ PUBWEAK PININT1_IRQHandler
+ PUBWEAK PININT2_IRQHandler
+ PUBWEAK PININT3_IRQHandler
+ PUBWEAK PININT4_IRQHandler
+ PUBWEAK PININT5_IRQHandler
+ PUBWEAK PININT6_IRQHandler
+ PUBWEAK PININT7_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+Default_IRQHandler
+ B Default_IRQHandler
+
+ SECTION .crp:CODE:ROOT(2)
+ DATA
+/* Code Read Protection
+NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
+CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
+ - Copy RAM to flash command can not write to Sector 0.
+ - Erase command can erase Sector 0 only when all sectors
+ are selected for erase.
+ - Compare command is disabled.
+ - Read Memory command is disabled.
+CRP2 0x87654321 - Read Memory is disabled.
+ - Write to RAM is disabled.
+ - "Go" command is disabled.
+ - Copy RAM to flash is disabled.
+ - Compare is disabled.
+CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+ by pulling PIO0_1 LOW is disabled if a valid user code is
+ present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+ DCD 0xFFFFFFFF
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
new file mode 100644
index 000000000..3deb912eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC82x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------*/
+//
+// <e> Clock Configuration
+#define CLOCK_SETUP 1
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.6 MHz
+// <2=> 1.05 MHz
+// <3=> 1.4 MHz
+// <4=> 1.75 MHz
+// <5=> 2.1 MHz
+// <6=> 2.4 MHz
+// <7=> 2.7 MHz
+// <8=> 3.0 MHz
+// <9=> 3.25 MHz
+// <10=> 3.5 MHz
+// <11=> 3.75 MHz
+// <12=> 4.0 MHz
+// <13=> 4.2 MHz
+// <14=> 4.4 MHz
+// <15=> 4.6 MHz
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+// </h>
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o.0..1> SEL: System PLL Clock Source
+// <0=> IRC
+// <1=> Crystal Oscillator
+// <2=> Reserved
+// <3=> CLKIN. External clock input.
+// </h>
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> PLL input
+// <2=> Watchdog Oscillator
+// <3=> PLL output
+// </h>
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
+// </e>
+
+//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+/*
+#if (CLOCK_SETUP == 0)
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#elif (CLOCK_SETUP == 2)
+// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#endif
+*/
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ volatile uint32_t i;
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ for (i = 0; i < 200; i++) __NOP();
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct
new file mode 100644
index 000000000..310aa8219
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 000000000..a90d8d290
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,218 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+__initial_sp EQU 0x10002000
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD I2C1_IRQHandler ; I2C1 controller
+ DCD I2C0_IRQHandler ; I2C0 controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD Flash_IRQHandler ; Flash interrupt
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
+ DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
+ DCD ADC_THCMP_IRQHandler ; ADC threshold compare
+ DCD ADC_OVR_IRQHandler ; ADC overrun
+ DCD DMA__RQHandler ; DMA interrupt
+ DCD I2C2_IRQHandler ; I2C2 controller
+ DCD I2C3_IRQHandler ; I2C3 controller
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT Flash_IRQHandler [WEAK]
+ EXPORT WKT_IRQHandler [WEAK]
+ EXPORT ADC_SEQA_IRQHandler [WEAK]
+ EXPORT ADC_SEQB_IRQHandler [WEAK]
+ EXPORT ADC_THCMP_IRQHandler [WEAK]
+ EXPORT ADC_OVR_IRQHandler [WEAK]
+ EXPORT DMA__RQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT I2C3_IRQHandler [WEAK]
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C1_IRQHandler
+I2C0_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+Flash_IRQHandler
+WKT_IRQHandler
+ADC_SEQA_IRQHandler
+ADC_SEQB_IRQHandler
+ADC_THCMP_IRQHandler
+ADC_OVR_IRQHandler
+DMA__RQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld
new file mode 100644
index 000000000..be901736a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld
@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ /* Define each memory region */
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+ RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = 0x200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
new file mode 100644
index 000000000..c4273d680
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s
@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+/* LPC824 interrupts */
+ .long SPI0_IRQHandler // SPI0 controller
+ .long SPI1_IRQHandler // SPI1 controller
+ .long 0 // Reserved
+ .long UART0_IRQHandler // UART0
+ .long UART1_IRQHandler // UART1
+ .long UART2_IRQHandler // UART2
+ .long 0 // Reserved
+ .long I2C1_IRQHandler // I2C ch1 controller
+ .long I2C0_IRQHandler // I2C ch0 controller
+ .long SCT_IRQHandler // Smart Counter Timer
+ .long MRT_IRQHandler // Multi-Rate Timer
+ .long CMP_IRQHandler // Comparator
+ .long WDT_IRQHandler // PIO1 (0:11)
+ .long BOD_IRQHandler // Brown Out Detect
+ .long Flash_IRQHandler // Flash interrupt
+ .long WKT_IRQHandler // Wakeup timer
+ .long ADC_SEQA_IRQHandler // ADC sequence A completion
+ .long ADC_SEQB_IRQHandler // ADC sequence B completion
+ .long ADC_THCMP_IRQHandler // ADC threshold compare
+ .long ADC_OVR_IRQHandler // ADC overrun
+ .long DMA_IRQHandler // DMA interrupt
+ .long I2C2_IRQHandler // I2C2 controller
+ .long I2C3_IRQHandler // I2C3 controller
+ .long 0 // Reserved
+ .long PININT0_IRQHandler // PIO INT0
+ .long PININT1_IRQHandler // PIO INT1
+ .long PININT2_IRQHandler // PIO INT2
+ .long PININT3_IRQHandler // PIO INT3
+ .long PININT4_IRQHandler // PIO INT4
+ .long PININT5_IRQHandler // PIO INT5
+ .long PININT6_IRQHandler // PIO INT6
+ .long PININT7_IRQHandler // PIO INT7
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler I2C2_IRQHandler
+ def_irq_default_handler I2C3_IRQHandler
+ def_irq_default_handler SCT_IRQHandler
+ def_irq_default_handler MRT_IRQHandler
+ def_irq_default_handler CMP_IRQHandler
+ def_irq_default_handler WDT_IRQHandler
+ def_irq_default_handler BOD_IRQHandler
+ def_irq_default_handler Flash_IRQHandler
+ def_irq_default_handler WKT_IRQHandler
+ def_irq_default_handler ADC_SEQA_IRQHandler
+ def_irq_default_handler ADC_SEQB_IRQHandler
+ def_irq_default_handler ADC_THCMP_IRQHandler
+ def_irq_default_handler ADC_OVR_IRQHandler
+ def_irq_default_handler DMA_IRQHandler
+ def_irq_default_handler PININT0_IRQHandler
+ def_irq_default_handler PININT1_IRQHandler
+ def_irq_default_handler PININT2_IRQHandler
+ def_irq_default_handler PININT3_IRQHandler
+ def_irq_default_handler PININT4_IRQHandler
+ def_irq_default_handler PININT5_IRQHandler
+ def_irq_default_handler PININT6_IRQHandler
+ def_irq_default_handler PININT7_IRQHandler
+
+ .end
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c
new file mode 100644
index 000000000..e2b412349
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC82x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------*/
+//
+// <e> Clock Configuration
+#define CLOCK_SETUP 1
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o.1> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.6 MHz
+// <2=> 1.05 MHz
+// <3=> 1.4 MHz
+// <4=> 1.75 MHz
+// <5=> 2.1 MHz
+// <6=> 2.4 MHz
+// <7=> 2.7 MHz
+// <8=> 3.0 MHz
+// <9=> 3.25 MHz
+// <10=> 3.5 MHz
+// <11=> 3.75 MHz
+// <12=> 4.0 MHz
+// <13=> 4.2 MHz
+// <14=> 4.4 MHz
+// <15=> 4.6 MHz
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+// </h>
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o.0..1> SEL: System PLL Clock Source
+// <0=> IRC
+// <1=> Crystal Oscillator
+// <2=> Reserved
+// <3=> CLKIN. External clock input.
+// </h>
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> PLL input
+// <2=> Watchdog Oscillator
+// <3=> PLL output
+// </h>
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
+// </e>
+
+//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+
+/*
+#if (CLOCK_SETUP == 0)
+ #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#elif (CLOCK_SETUP == 2)
+// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+ #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+ #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#endif
+*/
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ for (i = 0; i < 200; i++) __NOP();
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+#endif
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
new file mode 100644
index 000000000..dc68e3933
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC82x.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
new file mode 100644
index 000000000..ee0e4a718
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
new file mode 100644
index 000000000..a80f83290
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t MainClock; /*!< Main Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h
new file mode 100644
index 000000000..d60ea4484
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h
@@ -0,0 +1,1057 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file MBRZA1H.h
+ * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
+ * Renesas MBRZA1H Device Series
+ * @version
+ * @date 19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef __MBRZA1H_H__
+#define __MBRZA1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** SGI Interrupts Numbers ****************************************/
+ SGI0_IRQn = 0,
+ SGI1_IRQn = 1,
+ SGI2_IRQn = 2,
+ SGI3_IRQn = 3,
+ SGI4_IRQn = 4,
+ SGI5_IRQn = 5,
+ SGI6_IRQn = 6,
+ SGI7_IRQn = 7,
+ SGI8_IRQn = 8,
+ SGI9_IRQn = 9,
+ SGI10_IRQn = 10,
+ SGI11_IRQn = 11,
+ SGI12_IRQn = 12,
+ SGI13_IRQn = 13,
+ SGI14_IRQn = 14,
+ SGI15_IRQn = 15,
+
+/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
+ /* 16 - 578 */
+ PMUIRQ0_IRQn = 16,
+ COMMRX0_IRQn = 17,
+ COMMTX0_IRQn = 18,
+ CTIIRQ0_IRQn = 19,
+
+ IRQ0_IRQn = 32,
+ IRQ1_IRQn = 33,
+ IRQ2_IRQn = 34,
+ IRQ3_IRQn = 35,
+ IRQ4_IRQn = 36,
+ IRQ5_IRQn = 37,
+ IRQ6_IRQn = 38,
+ IRQ7_IRQn = 39,
+
+ PL310ERR_IRQn = 40,
+
+ DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
+ DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
+ DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
+ DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
+ DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
+ DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
+ DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
+ DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
+ DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
+ DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
+ DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
+ DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
+ DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
+ DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
+ DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
+ DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
+ DMAERR_IRQn = 57, /*!< DMAC Interrupt */
+
+ /* 58-72 Reserved */
+
+ USBI0_IRQn = 73,
+ USBI1_IRQn = 74,
+
+ S0_VI_VSYNC0_IRQn = 75,
+ S0_LO_VSYNC0_IRQn = 76,
+ S0_VSYNCERR0_IRQn = 77,
+ GR3_VLINE0_IRQn = 78,
+ S0_VFIELD0_IRQn = 79,
+ IV1_VBUFERR0_IRQn = 80,
+ IV3_VBUFERR0_IRQn = 81,
+ IV5_VBUFERR0_IRQn = 82,
+ IV6_VBUFERR0_IRQn = 83,
+ S0_WLINE0_IRQn = 84,
+ S1_VI_VSYNC0_IRQn = 85,
+ S1_LO_VSYNC0_IRQn = 86,
+ S1_VSYNCERR0_IRQn = 87,
+ S1_VFIELD0_IRQn = 88,
+ IV2_VBUFERR0_IRQn = 89,
+ IV4_VBUFERR0_IRQn = 90,
+ S1_WLINE0_IRQn = 91,
+ OIR_VI_VSYNC0_IRQn = 92,
+ OIR_LO_VSYNC0_IRQn = 93,
+ OIR_VSYNCERR0_IRQn = 94,
+ OIR_VFIELD0_IRQn = 95,
+ IV7_VBUFERR0_IRQn = 96,
+ IV8_VBUFERR0_IRQn = 97,
+ /* 98 Reserved */
+ S0_VI_VSYNC1_IRQn = 99,
+ S0_LO_VSYNC1_IRQn = 100,
+ S0_VSYNCERR1_IRQn = 101,
+ GR3_VLINE1_IRQn = 102,
+ S0_VFIELD1_IRQn = 103,
+ IV1_VBUFERR1_IRQn = 104,
+ IV3_VBUFERR1_IRQn = 105,
+ IV5_VBUFERR1_IRQn = 106,
+ IV6_VBUFERR1_IRQn = 107,
+ S0_WLINE1_IRQn = 108,
+ S1_VI_VSYNC1_IRQn = 109,
+ S1_LO_VSYNC1_IRQn = 110,
+ S1_VSYNCERR1_IRQn = 111,
+ S1_VFIELD1_IRQn = 112,
+ IV2_VBUFERR1_IRQn = 113,
+ IV4_VBUFERR1_IRQn = 114,
+ S1_WLINE1_IRQn = 115,
+ OIR_VI_VSYNC1_IRQn = 116,
+ OIR_LO_VSYNC1_IRQn = 117,
+ OIR_VSYNCERR1_IRQn = 118,
+ OIR_VFIELD1_IRQn = 119,
+ IV7_VBUFERR1_IRQn = 120,
+ IV8_VBUFERR1_IRQn = 121,
+ /* Reserved = 122 */
+
+ IMRDI_IRQn = 123,
+ IMR2I0_IRQn = 124,
+ IMR2I1_IRQn = 125,
+
+ JEDI_IRQn = 126,
+ JDTI_IRQn = 127,
+
+ CMP0_IRQn = 128,
+ CMP1_IRQn = 129,
+
+ INT0_IRQn = 130,
+ INT1_IRQn = 131,
+ INT2_IRQn = 132,
+ INT3_IRQn = 133,
+
+ OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
+ OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
+
+ CMI_IRQn = 136,
+ WTOUT_IRQn = 137,
+
+ ITI_IRQn = 138,
+
+ TGI0A_IRQn = 139,
+ TGI0B_IRQn = 140,
+ TGI0C_IRQn = 141,
+ TGI0D_IRQn = 142,
+ TGI0V_IRQn = 143,
+ TGI0E_IRQn = 144,
+ TGI0F_IRQn = 145,
+ TGI1A_IRQn = 146,
+ TGI1B_IRQn = 147,
+ TGI1V_IRQn = 148,
+ TGI1U_IRQn = 149,
+ TGI2A_IRQn = 150,
+ TGI2B_IRQn = 151,
+ TGI2V_IRQn = 152,
+ TGI2U_IRQn = 153,
+ TGI3A_IRQn = 154,
+ TGI3B_IRQn = 155,
+ TGI3C_IRQn = 156,
+ TGI3D_IRQn = 157,
+ TGI3V_IRQn = 158,
+ TGI4A_IRQn = 159,
+ TGI4B_IRQn = 160,
+ TGI4C_IRQn = 161,
+ TGI4D_IRQn = 162,
+ TGI4V_IRQn = 163,
+
+ CMI1_IRQn = 164,
+ CMI2_IRQn = 165,
+
+ SGDEI0_IRQn = 166,
+ SGDEI1_IRQn = 167,
+ SGDEI2_IRQn = 168,
+ SGDEI3_IRQn = 169,
+
+ ADI_IRQn = 170,
+ LMTI_IRQn = 171,
+
+ SSII0_IRQn = 172, /*!< SSIF Interrupt */
+ SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
+ SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
+ SSII1_IRQn = 175, /*!< SSIF Interrupt */
+ SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
+ SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
+ SSII2_IRQn = 178, /*!< SSIF Interrupt */
+ SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
+ SSII3_IRQn = 180, /*!< SSIF Interrupt */
+ SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
+ SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
+ SSII4_IRQn = 183, /*!< SSIF Interrupt */
+ SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
+ SSII5_IRQn = 185, /*!< SSIF Interrupt */
+ SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
+ SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
+
+ SPDIFI_IRQn = 188,
+
+ INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
+ INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
+ INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
+ INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
+ INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
+ INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
+ INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
+ INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
+ INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
+ INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
+ INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
+ INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
+ INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
+ INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
+ INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
+ INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
+ INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
+ INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
+ INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
+ INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
+ INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
+ INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
+ INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
+ INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
+ INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
+ INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
+ INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
+ INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
+ INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
+ INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
+ INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
+ INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
+
+ SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
+ SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
+ SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
+ SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
+ SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
+ SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
+ SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
+ SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
+ SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
+ SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
+ SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
+ SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
+ SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
+ SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
+ SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
+ SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
+ SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
+ SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
+ SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
+ SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
+ SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
+ SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
+ SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
+ SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
+ SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
+ SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
+ SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
+ SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
+ SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
+ SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
+ SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
+ SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
+
+ INTRCANGERR_IRQn = 253,
+ INTRCANGRECC_IRQn = 254,
+ INTRCAN0REC_IRQn = 255,
+ INTRCAN0ERR_IRQn = 256,
+ INTRCAN0TRX_IRQn = 257,
+ INTRCAN1REC_IRQn = 258,
+ INTRCAN1ERR_IRQn = 259,
+ INTRCAN1TRX_IRQn = 260,
+ INTRCAN2REC_IRQn = 261,
+ INTRCAN2ERR_IRQn = 262,
+ INTRCAN2TRX_IRQn = 263,
+ INTRCAN3REC_IRQn = 264,
+ INTRCAN3ERR_IRQn = 265,
+ INTRCAN3TRX_IRQn = 266,
+ INTRCAN4REC_IRQn = 267,
+ INTRCAN4ERR_IRQn = 268,
+ INTRCAN4TRX_IRQn = 269,
+
+ RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
+ RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
+ RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
+ RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
+ RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
+ RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
+ RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
+ RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
+ RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
+ RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
+ RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
+ RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
+ RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
+ RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
+ RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
+
+ IEBBTD_IRQn = 285,
+ IEBBTERR_IRQn = 286,
+ IEBBTSTA_IRQn = 287,
+ IEBBTV_IRQn = 288,
+
+ ISY_IRQn = 289,
+ IERR_IRQn = 290,
+ ITARG_IRQn = 291,
+ ISEC_IRQn = 292,
+ IBUF_IRQn = 293,
+ IREADY_IRQn = 294,
+
+ STERB_IRQn = 295,
+ FLTENDI_IRQn = 296,
+ FLTREQ0I_IRQn = 297,
+ FLTREQ1I_IRQn = 298,
+
+ MMC0_IRQn = 299,
+ MMC1_IRQn = 300,
+ MMC2_IRQn = 301,
+
+ SCHI0_3_IRQn = 302,
+ SDHI0_0_IRQn = 303,
+ SDHI0_1_IRQn = 304,
+ SCHI1_3_IRQn = 305,
+ SDHI1_0_IRQn = 306,
+ SDHI1_1_IRQn = 307,
+
+ ARM_IRQn = 308,
+ PRD_IRQn = 309,
+ CUP_IRQn = 310,
+
+ SCUAI0_IRQn = 311,
+ SCUAI1_IRQn = 312,
+ SCUFDI0_IRQn = 313,
+ SCUFDI1_IRQn = 314,
+ SCUFDI2_IRQn = 315,
+ SCUFDI3_IRQn = 316,
+ SCUFUI0_IRQn = 317,
+ SCUFUI1_IRQn = 318,
+ SCUFUI2_IRQn = 319,
+ SCUFUI3_IRQn = 320,
+ SCUDVI0_IRQn = 321,
+ SCUDVI1_IRQn = 322,
+ SCUDVI2_IRQn = 323,
+ SCUDVI3_IRQn = 324,
+
+ MLB_CINT_IRQn = 325,
+ MLB_SINT_IRQn = 326,
+
+ DRC10_IRQn = 327,
+ DRC11_IRQn = 328,
+
+ /* 329-330 Reserved */
+
+ LINI0_INT_T_IRQn = 331,
+ LINI0_INT_R_IRQn = 332,
+ LINI0_INT_S_IRQn = 333,
+ LINI0_INT_M_IRQn = 334,
+ LINI1_INT_T_IRQn = 335,
+ LINI1_INT_R_IRQn = 336,
+ LINI1_INT_S_IRQn = 337,
+ LINI1_INT_M_IRQn = 338,
+
+ /* 339-346 Reserved */
+
+ SCIERI0_IRQn = 347,
+ SCIRXI0_IRQn = 348,
+ SCITXI0_IRQn = 349,
+ SCITEI0_IRQn = 350,
+ SCIERI1_IRQn = 351,
+ SCIRXI1_IRQn = 352,
+ SCITXI1_IRQn = 353,
+ SCITEI1_IRQn = 354,
+
+ AVBI_DATA = 355,
+ AVBI_ERROR = 356,
+ AVBI_MANAGE = 357,
+ AVBI_MAC = 358,
+
+ ETHERI_IRQn = 359,
+
+ /* 360-363 Reserved */
+
+ CEUI_IRQn = 364,
+
+ /* 365-380 Reserved */
+
+
+ H2XMLB_ERRINT_IRQn = 381,
+ H2XIC1_ERRINT_IRQn = 382,
+ X2HPERI1_ERRINT_IRQn = 383,
+ X2HPERR2_ERRINT_IRQn = 384,
+ X2HPERR34_ERRINT_IRQn= 385,
+ X2HPERR5_ERRINT_IRQn = 386,
+ X2HPERR67_ERRINT_IRQn= 387,
+ X2HDBGR_ERRINT_IRQn = 388,
+ X2HBSC_ERRINT_IRQn = 389,
+ X2HSPI1_ERRINT_IRQn = 390,
+ X2HSPI2_ERRINT_IRQn = 391,
+ PRRI_IRQn = 392,
+
+ IFEI0_IRQn = 393,
+ OFFI0_IRQn = 394,
+ PFVEI0_IRQn = 395,
+ IFEI1_IRQn = 396,
+ OFFI1_IRQn = 397,
+ PFVEI1_IRQn = 398,
+
+ /* 399-415 Reserved */
+ TINT0_IRQn = 416,
+ TINT1_IRQn = 417,
+ TINT2_IRQn = 418,
+ TINT3_IRQn = 419,
+ TINT4_IRQn = 420,
+ TINT5_IRQn = 421,
+ TINT6_IRQn = 422,
+ TINT7_IRQn = 423,
+ TINT8_IRQn = 424,
+ TINT9_IRQn = 425,
+ TINT10_IRQn = 426,
+ TINT11_IRQn = 427,
+ TINT12_IRQn = 428,
+ TINT13_IRQn = 429,
+ TINT14_IRQn = 430,
+ TINT15_IRQn = 431,
+ TINT16_IRQn = 432,
+ TINT17_IRQn = 433,
+ TINT18_IRQn = 434,
+ TINT19_IRQn = 435,
+ TINT20_IRQn = 436,
+ TINT21_IRQn = 437,
+ TINT22_IRQn = 438,
+ TINT23_IRQn = 439,
+ TINT24_IRQn = 440,
+ TINT25_IRQn = 441,
+ TINT26_IRQn = 442,
+ TINT27_IRQn = 443,
+ TINT28_IRQn = 444,
+ TINT29_IRQn = 445,
+ TINT30_IRQn = 446,
+ TINT31_IRQn = 447,
+ TINT32_IRQn = 448,
+ TINT33_IRQn = 449,
+ TINT34_IRQn = 450,
+ TINT35_IRQn = 451,
+ TINT36_IRQn = 452,
+ TINT37_IRQn = 453,
+ TINT38_IRQn = 454,
+ TINT39_IRQn = 455,
+ TINT40_IRQn = 456,
+ TINT41_IRQn = 457,
+ TINT42_IRQn = 458,
+ TINT43_IRQn = 459,
+ TINT44_IRQn = 460,
+ TINT45_IRQn = 461,
+ TINT46_IRQn = 462,
+ TINT47_IRQn = 463,
+ TINT48_IRQn = 464,
+ TINT49_IRQn = 465,
+ TINT50_IRQn = 466,
+ TINT51_IRQn = 467,
+ TINT52_IRQn = 468,
+ TINT53_IRQn = 469,
+ TINT54_IRQn = 470,
+ TINT55_IRQn = 471,
+ TINT56_IRQn = 472,
+ TINT57_IRQn = 473,
+ TINT58_IRQn = 474,
+ TINT59_IRQn = 475,
+ TINT60_IRQn = 476,
+ TINT61_IRQn = 477,
+ TINT62_IRQn = 478,
+ TINT63_IRQn = 479,
+ TINT64_IRQn = 480,
+ TINT65_IRQn = 481,
+ TINT66_IRQn = 482,
+ TINT67_IRQn = 483,
+ TINT68_IRQn = 484,
+ TINT69_IRQn = 485,
+ TINT70_IRQn = 486,
+ TINT71_IRQn = 487,
+ TINT72_IRQn = 488,
+ TINT73_IRQn = 489,
+ TINT74_IRQn = 490,
+ TINT75_IRQn = 491,
+ TINT76_IRQn = 492,
+ TINT77_IRQn = 493,
+ TINT78_IRQn = 494,
+ TINT79_IRQn = 495,
+ TINT80_IRQn = 496,
+ TINT81_IRQn = 497,
+ TINT82_IRQn = 498,
+ TINT83_IRQn = 499,
+ TINT84_IRQn = 500,
+ TINT85_IRQn = 501,
+ TINT86_IRQn = 502,
+ TINT87_IRQn = 503,
+ TINT88_IRQn = 504,
+ TINT89_IRQn = 505,
+ TINT90_IRQn = 506,
+ TINT91_IRQn = 507,
+ TINT92_IRQn = 508,
+ TINT93_IRQn = 509,
+ TINT94_IRQn = 510,
+ TINT95_IRQn = 511,
+ TINT96_IRQn = 512,
+ TINT97_IRQn = 513,
+ TINT98_IRQn = 514,
+ TINT99_IRQn = 515,
+ TINT100_IRQn = 516,
+ TINT101_IRQn = 517,
+ TINT102_IRQn = 518,
+ TINT103_IRQn = 519,
+ TINT104_IRQn = 520,
+ TINT105_IRQn = 521,
+ TINT106_IRQn = 522,
+ TINT107_IRQn = 523,
+ TINT108_IRQn = 524,
+ TINT109_IRQn = 525,
+ TINT110_IRQn = 526,
+ TINT111_IRQn = 527,
+ TINT112_IRQn = 528,
+ TINT113_IRQn = 529,
+ TINT114_IRQn = 530,
+ TINT115_IRQn = 531,
+ TINT116_IRQn = 532,
+ TINT117_IRQn = 533,
+ TINT118_IRQn = 534,
+ TINT119_IRQn = 535,
+ TINT120_IRQn = 536,
+ TINT121_IRQn = 537,
+ TINT122_IRQn = 538,
+ TINT123_IRQn = 539,
+ TINT124_IRQn = 540,
+ TINT125_IRQn = 541,
+ TINT126_IRQn = 542,
+ TINT127_IRQn = 543,
+ TINT128_IRQn = 544,
+ TINT129_IRQn = 545,
+ TINT130_IRQn = 546,
+ TINT131_IRQn = 547,
+ TINT132_IRQn = 548,
+ TINT133_IRQn = 549,
+ TINT134_IRQn = 550,
+ TINT135_IRQn = 551,
+ TINT136_IRQn = 552,
+ TINT137_IRQn = 553,
+ TINT138_IRQn = 554,
+ TINT139_IRQn = 555,
+ TINT140_IRQn = 556,
+ TINT141_IRQn = 557,
+ TINT142_IRQn = 558,
+ TINT143_IRQn = 559,
+ TINT144_IRQn = 560,
+ TINT145_IRQn = 561,
+ TINT146_IRQn = 562,
+ TINT147_IRQn = 563,
+ TINT148_IRQn = 564,
+ TINT149_IRQn = 565,
+ TINT150_IRQn = 566,
+ TINT151_IRQn = 567,
+ TINT152_IRQn = 568,
+ TINT153_IRQn = 569,
+ TINT154_IRQn = 570,
+ TINT155_IRQn = 571,
+ TINT156_IRQn = 572,
+ TINT157_IRQn = 573,
+ TINT158_IRQn = 574,
+ TINT159_IRQn = 575,
+ TINT160_IRQn = 576,
+ TINT161_IRQn = 577,
+ TINT162_IRQn = 578,
+ TINT163_IRQn = 579,
+ TINT164_IRQn = 580,
+ TINT165_IRQn = 581,
+ TINT166_IRQn = 582,
+ TINT167_IRQn = 583,
+ TINT168_IRQn = 584,
+ TINT169_IRQn = 585,
+ TINT170_IRQn = 586
+
+} IRQn_Type;
+
+#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
+
+/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
+#define __CA9_REV 0x0000 /*!< Core revision r0 */
+
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include <core_ca9.h>
+#include "system_MBRZA1H.h"
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Section */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
+ Renesas_RZ_A1 Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+#include "pl310.h"
+#include "gic.h"
+#include "nvic_wrapper.h"
+#include "cmsis_nvic.h"
+
+#include "ostm_iodefine.h"
+#include "gpio_iodefine.h"
+#include "cpg_iodefine.h"
+#include "l2c_iodefine.h"
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
+ @{
+*/
+
+/* R7S72100 CPU board */
+#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
+#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
+#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
+#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
+#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
+#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
+#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
+#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
+#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
+
+//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
+#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
+
+/******************************************************************************/
+/* Clock Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
+ @{
+*/
+
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ * GFC[1:0] =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/*@}*/ /* end of group Renesas_RZ_A1_Clocks */
+
+/******************************************************************************/
+/* CPG Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
+ @{
+*/
+
+#define CPG_FRQCR_SHIFT_CKOEN2 (14)
+#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0 (12)
+#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC (8)
+#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC (0)
+#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY (0x80u)
+#define CPG_STBCR1_BIT_DEEP (0x40u)
+#define CPG_STBCR2_BIT_HIZ (0x80u)
+#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
+#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
+#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
+#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
+#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
+#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
+#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
+#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
+#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
+#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
+#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
+#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
+#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
+#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
+#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
+#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
+#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
+
+/*@}*/ /* end of group Renesas_RZ_A1_CPG */
+
+/******************************************************************************/
+/* GPIO Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
+ @{
+*/
+
+#define GPIO_BIT_N0 (1u << 0)
+#define GPIO_BIT_N1 (1u << 1)
+#define GPIO_BIT_N2 (1u << 2)
+#define GPIO_BIT_N3 (1u << 3)
+#define GPIO_BIT_N4 (1u << 4)
+#define GPIO_BIT_N5 (1u << 5)
+#define GPIO_BIT_N6 (1u << 6)
+#define GPIO_BIT_N7 (1u << 7)
+#define GPIO_BIT_N8 (1u << 8)
+#define GPIO_BIT_N9 (1u << 9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+
+#define MD_BOOT10_MASK (0x3)
+
+#define MD_BOOT10_BM0 (0x0)
+#define MD_BOOT10_BM1 (0x2)
+#define MD_BOOT10_BM3 (0x1)
+#define MD_BOOT10_BM4_5 (0x3)
+
+#define MD_CLK (1u << 2)
+#define MD_CLKS (1u << 3)
+
+/*@}*/ /* end of group Renesas_RZ_A1_GPIO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __MBRZA1H_H__
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c
new file mode 100644
index 000000000..243d7d35d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file RZ_A1_Init.c
+* $Rev: 624 $
+* $Date:: 2013-04-24 13:37:48 +0900#$
+* @brief RZ_A1 Initialize
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "RZ_A1_Init.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: RZ_A1_SetSramWriteEnable
+* @brief Initialize Board settings
+*
+* Description:<br>
+* Set SRAM write enable
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_SetSramWriteEnable(void)
+{
+ /* Enable SRAM write access */
+ CPG.SYSCR3 = 0x0F;
+
+ return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitClock
+* @brief Initialize Board settings
+*
+* Description:<br>
+* Initialize Clock
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_InitClock(void)
+{
+ /* Cancel L2C standby status before clock change */
+ L2CREG15_POWER_CTRL = 0x00000001;
+
+ /* Clock settings */
+ /* ClockMode0 */
+ CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */
+ CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */
+
+ return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_IsClockMode0
+* @brief Query Clock Mode
+*
+* Description:<br>
+* Answer ClockMode0 or not
+* @param none
+* @retval true : clock mode 0
+* @retval false : clock mode 1
+******************************************************************************/
+int RZ_A1_IsClockMode0(void)
+{
+ /* ClockMode0 */
+ return true;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitBus
+* @brief Initialize Bus
+*
+* Description:<br>
+* Initialize Pin Setting
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_InitBus(void)
+{
+ /*************************************************************************/
+ /* If need Pin Setting before run program, the setting will be wrote here*/
+ /*************************************************************************/
+
+ return;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h
new file mode 100644
index 000000000..323884e05
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file RZ_A1_Init.h
+* $Rev: 531 $
+* $Date:: 2013-04-16 13:07:35 +0900#$
+* @brief RZ_A1 Initialize
+******************************************************************************/
+
+#ifndef RZ_A1_INIT_H
+#define RZ_A1_INIT_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdbool.h>
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void RZ_A1_SetSramWriteEnable(void);
+void RZ_A1_InitClock(void);
+int RZ_A1_IsClockMode0(void);
+void RZ_A1_InitBus(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RZ_A1_INIT_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct
new file mode 100644
index 000000000..9ae88afad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct
@@ -0,0 +1,43 @@
+
+
+LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+ TTB +0 EMPTY 0x4000
+ { } ; Level-1 Translation Table for MMU
+}
+
+SFLASH 0x18000000 (0x08000000)
+{
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; S-Flash ROM : Executable cached region
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ BOOT_LOADER_BEGIN 0x18000000 FIXED
+ {
+ * ( BOOT_LOADER )
+ }
+
+ VECTORS 0x18004000 FIXED
+ {
+ * (RESET, +FIRST) ; Vector table and other (assembler) startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ }
+
+ RO_DATA +0
+ { * (+RO-DATA) } ; Application RO data (.constdata)
+
+ RW_DATA 0x20020000
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA +0 ALIGN 0x400
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ RW_DATA_NC 0x60900000 0x00100000
+ { * (NC_DATA) } ; Application RW data Non cached area
+
+ ZI_DATA_NC +0
+ { * (NC_BSS) } ; Application ZI data Non cached area
+}
+
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s
new file mode 100644
index 000000000..bf399f592
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s
@@ -0,0 +1,454 @@
+;/*****************************************************************************
+; * @file: startup_MBRZA1H.s
+; * @purpose: CMSIS Cortex-A9 Core Device Startup File
+; * for the NXP MBRZA1H Device Series
+; * @version: V1.02, modified for mbed
+; * @date: 27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+GICI_BASE EQU 0xe8202000
+ICCIAR_OFFSET EQU 0x0000000C
+ICCEOIR_OFFSET EQU 0x00000010
+ICCHPIR_OFFSET EQU 0x00000018
+
+GICD_BASE EQU 0xe8201000
+ICDISER0_OFFSET EQU 0x00000100
+ICDICER0_OFFSET EQU 0x00000180
+ICDISPR0_OFFSET EQU 0x00000200
+ICDABR0_OFFSET EQU 0x00000300
+ICDIPR0_OFFSET EQU 0x00000400
+
+Mode_USR EQU 0x10
+Mode_FIQ EQU 0x11
+Mode_IRQ EQU 0x12
+Mode_SVC EQU 0x13
+Mode_ABT EQU 0x17
+Mode_UND EQU 0x1B
+Mode_SYS EQU 0x1F
+
+I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
+F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
+T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state
+
+GIC_ERRATA_CHECK_1 EQU 0x000003FE
+GIC_ERRATA_CHECK_2 EQU 0x000003FF
+
+
+Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable
+Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
+Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
+Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable
+Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
+
+RAM_BASE EQU 0x80000000
+VRAM_BASE EQU 0x18000000
+SRAM_BASE EQU 0x2e000000
+ETHERNET EQU 0x1a000000
+CS3_PERIPHERAL_BASE EQU 0x1c000000
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
+; </h>
+
+UND_Stack_Size EQU 0x00000100
+SVC_Stack_Size EQU 0x00008000
+ABT_Stack_Size EQU 0x00000100
+FIQ_Stack_Size EQU 0x00000100
+IRQ_Stack_Size EQU 0x00008000
+USR_Stack_Size EQU 0x00004000
+
+ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+ FIQ_Stack_Size + IRQ_Stack_Size)
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE USR_Stack_Size
+__initial_sp SPACE ISR_Stack_Size
+
+Stack_Top
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00080000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ ARM
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, CODE, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors LDR PC, Reset_Addr ; Address of Reset Handler
+ LDR PC, Undef_Addr ; Address of Undef Handler
+ LDR PC, SVC_Addr ; Address of SVC Handler
+ LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler
+ LDR PC, DAbt_Addr ; Address of Data Abort Handler
+ NOP ; Reserved Vector
+ LDR PC, IRQ_Addr ; Address of IRQ Handler
+ LDR PC, FIQ_Addr ; Address of FIQ Handler
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+Reset_Addr DCD Reset_Handler
+Undef_Addr DCD Undef_Handler
+SVC_Addr DCD SVC_Handler
+PAbt_Addr DCD PAbt_Handler
+DAbt_Addr DCD DAbt_Handler
+IRQ_Addr DCD IRQ_Handler
+FIQ_Addr DCD FIQ_Handler
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT InitMemorySubsystem
+ IMPORT __main
+ IMPORT RZ_A1_SetSramWriteEnable
+
+ ; Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+; Enables Full Access i.e. in both privileged and non privileged modes
+ MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR)
+ ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11
+ MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR)
+ ISB
+
+; Switch on the VFP and NEON hardware
+ MOV r0, #0x40000000
+ VMSR FPEXC, r0 ; Write FPEXC register, EN bit set
+
+ MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
+ ISB
+
+; Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =__Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+; Setup Stack for each exceptional mode
+ LDR R0, =Stack_Top
+
+; Enter Undefined Instruction Mode and set its Stack Pointer
+ MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #UND_Stack_Size
+
+; Enter Abort Mode and set its Stack Pointer
+ MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #ABT_Stack_Size
+
+; Enter FIQ Mode and set its Stack Pointer
+ MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #FIQ_Stack_Size
+
+; Enter IRQ Mode and set its Stack Pointer
+ MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #IRQ_Stack_Size
+
+; Enter Supervisor Mode and set its Stack Pointer
+ MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+
+; Enter System Mode to complete initialization and enter kernel
+ MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+
+ ISB
+
+ LDR R0, =RZ_A1_SetSramWriteEnable
+ BLX R0
+
+ IMPORT create_translation_table
+ BL create_translation_table
+
+; USR/SYS stack pointer will be set during kernel init
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =InitMemorySubsystem
+ BLX R0
+ LDR R0, =__main
+ BLX R0
+
+ ENDP
+
+Undef_Handler\
+ PROC
+ EXPORT Undef_Handler [WEAK]
+ IMPORT CUndefHandler
+ SRSFD SP!, #Mode_UND
+ PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
+
+ MRS R0, SPSR
+ TST R0, #T_Bit ; Check mode
+ MOVEQ R1, #4 ; R1 = 4 ARM mode
+ MOVNE R1, #2 ; R1 = 2 Thumb mode
+ SUB R0, LR, R1
+ LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
+ BEQ undef_cont
+
+ ;Thumb instruction
+ ;Determine if it is a 32-bit Thumb instruction
+ LDRH R0, [R0]
+ MOV R2, #0x1c
+ CMP R2, R0, LSR #11
+ BHS undef_cont ;16-bit Thumb instruction
+
+ ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
+ LDRH R2, [LR]
+ ORR R0, R2, R0, LSL #16
+undef_cont
+ MOV R2, LR ; Set LR to third argument
+
+; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
+ MOV R3, SP ; Ensure stack is 8-byte aligned
+ AND R12, R3, #4
+ SUB SP, SP, R12 ; Adjust stack
+ PUSH {R12, LR} ; Store stack adjustment and dummy LR
+
+ ;R0 Offending instruction
+ ;R1 =2 (Thumb) or =4 (ARM)
+ BL CUndefHandler
+
+ POP {R12, LR} ; Get stack adjustment & discard dummy LR
+ ADD SP, SP, R12 ; Unadjust stack
+
+ LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
+ SUB LR, LR, R0
+ LDR R0, [SP, #28] ; Restore stacked SPSR
+ MSR SPSR_CXSF, R0
+ POP {R0-R4, R12} ; Restore stacked APCS registers
+ ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
+ MOVS PC, LR
+ ENDP
+
+PAbt_Handler\
+ PROC
+ EXPORT PAbt_Handler [WEAK]
+ IMPORT CPAbtHandler
+ SUB LR, LR, #4 ; Pre-adjust LR
+ SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
+ PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
+ MRC p15, 0, R0, c5, c0, 1 ; IFSR
+ MRC p15, 0, R1, c6, c0, 2 ; IFAR
+
+ MOV R2, LR ; Set LR to third argument
+
+; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
+ MOV R3, SP ; Ensure stack is 8-byte aligned
+ AND R12, R3, #4
+ SUB SP, SP, R12 ; Adjust stack
+ PUSH {R12, LR} ; Store stack adjustment and dummy LR
+
+ BL CPAbtHandler
+
+ POP {R12, LR} ; Get stack adjustment & discard dummy LR
+ ADD SP, SP, R12 ; Unadjust stack
+
+ POP {R0-R4, R12} ; Restore stack APCS registers
+ RFEFD SP! ; Return from exception
+ ENDP
+
+
+DAbt_Handler\
+ PROC
+ EXPORT DAbt_Handler [WEAK]
+ IMPORT CDAbtHandler
+ SUB LR, LR, #8 ; Pre-adjust LR
+ SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
+ PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
+ CLREX ; State of exclusive monitors unknown after taken data abort
+ MRC p15, 0, R0, c5, c0, 0 ; DFSR
+ MRC p15, 0, R1, c6, c0, 0 ; DFAR
+
+ MOV R2, LR ; Set LR to third argument
+
+; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
+ MOV R3, SP ; Ensure stack is 8-byte aligned
+ AND R12, R3, #4
+ SUB SP, SP, R12 ; Adjust stack
+ PUSH {R12, LR} ; Store stack adjustment and dummy LR
+
+ BL CDAbtHandler
+
+ POP {R12, LR} ; Get stack adjustment & discard dummy LR
+ ADD SP, SP, R12 ; Unadjust stack
+
+ POP {R0-R4, R12} ; Restore stacked APCS registers
+ RFEFD SP! ; Return from exception
+ ENDP
+
+FIQ_Handler\
+ PROC
+ EXPORT FIQ_Handler [WEAK]
+ ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+ ;; so if a real FIQ Handler is implemented, this will be needed before returning:
+ ;; LDR R1, =GICI_BASE
+ ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+ B .
+ ENDP
+
+SVC_Handler\
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+IRQ_Handler\
+ PROC
+ EXPORT IRQ_Handler [WEAK]
+ IMPORT IRQCount
+ IMPORT IRQTable
+ IMPORT IRQNestLevel
+
+ ;prologue
+ SUB LR, LR, #4 ; Pre-adjust LR
+ SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
+ CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
+ PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack
+
+; AND R1, SP, #4 ; Ensure stack is 8-byte aligned
+ MOV R3, SP ; Ensure stack is 8-byte aligned
+ AND R1, R3, #4
+ SUB SP, SP, R1 ; Adjust stack
+ PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack
+
+ LDR R0, =IRQNestLevel ; Get address of nesting counter
+ LDR R1, [R0]
+ ADD R1, R1, #1 ; Increment nesting counter
+ STR R1, [R0]
+
+ ;identify and acknowledge interrupt
+ LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+ LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register)
+ DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts
+
+ ; Workaround GIC 390 errata 733075
+ ; If the ID is not 0, then service the interrupt as normal.
+ ; If the ID is 0 and active, then service interrupt ID 0 as normal.
+ ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+ ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
+ ;
+ LDR R2, =GICD_BASE
+ LDR R3, =GIC_ERRATA_CHECK_1
+ CMP R0, R3
+ BEQ unlock_cpu
+ LDR R3, =GIC_ERRATA_CHECK_2
+ CMP R0, R3
+ BEQ unlock_cpu
+ CMP R0, #0
+ BNE int_active ; If the ID is not 0, then service the interrupt
+ LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state
+ TST R3, #1
+ BNE int_active ; If active, then service the interrupt
+unlock_cpu
+ LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface
+ STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write
+ DSB ; Ensure the write completes before continuing
+ B ret_irq ; Do not service the spurious interrupt
+ ; End workaround
+
+int_active
+ LDR R2, =IRQCount ; Read number of IRQs
+ LDR R2, [R2]
+ CMP R0, R2 ; Clean up and return if no handler
+ BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
+ LDR R2, =IRQTable ; Get address of handler
+ LDR R2, [R2, R0, LSL #2]
+ CMP R2, #0 ; Clean up and return if handler address is 0
+ BEQ ret_irq
+ PUSH {R0,R1}
+
+ CPSIE i ; Now safe to re-enable interrupts
+ BLX R2 ; Call handler. R0 will be IRQ number
+ CPSID i ; Disable interrupts again
+
+ ;write EOIR (GIC CPU Interface register)
+ POP {R0,R1}
+ DSB ; Ensure that interrupt source is cleared before we write the EOIR
+ret_irq
+ ;epilogue
+ STR R0, [R1, #ICCEOIR_OFFSET]
+
+ LDR R0, =IRQNestLevel ; Get address of nesting counter
+ LDR R1, [R0]
+ SUB R1, R1, #1 ; Decrement nesting counter
+ STR R1, [R0]
+
+ POP {R1, LR} ; Get stack adjustment and restore LR_SVC
+ ADD SP, SP, R1 ; Unadjust stack
+
+ POP {R0-R3,R12} ; Restore stacked APCS registers
+ RFEFD SP! ; Return from exception
+ ENDP
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + USR_Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ENDIF
+
+
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld
new file mode 100644
index 000000000..3a27d14fe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld
@@ -0,0 +1,227 @@
+/* Linker script for mbed RZ_A1H */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000
+ BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000
+ SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000
+ L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+ RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
+ RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .boot :
+ {
+ KEEP(*(.boot_loader))
+ } > BOOT_LOADER
+
+ .text :
+ {
+
+ Image$$VECTORS$$Base = .;
+ * (RESET)
+ Image$$VECTORS$$Limit = .;
+ . += 0x00000400;
+
+ KEEP(*(.isr_vector))
+ *(SVC_TABLE)
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ Image$$RO_DATA$$Base = .;
+ *(.rodata*)
+ Image$$RO_DATA$$Limit = .;
+
+ KEEP(*(.eh_frame*))
+ } > SFLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SFLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SFLASH
+ __exidx_end = .;
+
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__nc_data_start)
+ LONG (__nc_data_end - __nc_data_start)
+ __copy_table_end__ = .;
+ } > SFLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__nc_bss_start)
+ LONG (__nc_bss_end - __nc_bss_start)
+ __zero_table_end__ = .;
+ } > SFLASH
+
+ __etext = .;
+
+ .ttb :
+ {
+ Image$$TTB$$ZI$$Base = .;
+ . += 0x00004000;
+ Image$$TTB$$ZI$$Limit = .;
+ } > L_TTB
+
+ .data : AT (__etext)
+ {
+ Image$$RW_DATA$$Base = .;
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ Image$$RW_DATA$$Limit = .;
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss ALIGN(0x400):
+ {
+ Image$$ZI_DATA$$Base = .;
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$ZI_DATA$$Limit = .;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ __etext2 = __etext + SIZEOF(.data);
+ .nc_data : AT (__etext2)
+ {
+ Image$$RW_DATA_NC$$Base = .;
+ __nc_data_start = .;
+ *(NC_DATA)
+
+ . = ALIGN(4);
+ __nc_data_end = .;
+ Image$$RW_DATA_NC$$Limit = .;
+ } > RAM_NC
+
+ .nc_bss (NOLOAD) :
+ {
+ Image$$ZI_DATA_NC$$Base = .;
+ __nc_bss_start = .;
+ *(NC_BSS)
+
+ . = ALIGN(4);
+ __nc_bss_end = .;
+ Image$$ZI_DATA_NC$$Limit = .;
+ } > RAM_NC
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s
new file mode 100644
index 000000000..f6cf2082b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s
@@ -0,0 +1,532 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .extern _start
+
+@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+ .equ USR_MODE , 0x10
+ .equ FIQ_MODE , 0x11
+ .equ IRQ_MODE , 0x12
+ .equ SVC_MODE , 0x13
+ .equ ABT_MODE , 0x17
+ .equ UND_MODE , 0x1b
+ .equ SYS_MODE , 0x1f
+ .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
+
+ .equ GICI_BASE , 0xe8202000
+ .equ ICCIAR_OFFSET , 0x0000000C
+ .equ ICCEOIR_OFFSET , 0x00000010
+ .equ ICCHPIR_OFFSET , 0x00000018
+ .equ GICD_BASE , 0xe8201000
+ .equ ICDISER0_OFFSET , 0x00000100
+ .equ ICDICER0_OFFSET , 0x00000180
+ .equ ICDISPR0_OFFSET , 0x00000200
+ .equ ICDABR0_OFFSET , 0x00000300
+ .equ ICDIPR0_OFFSET , 0x00000400
+
+ .equ Mode_USR , 0x10
+ .equ Mode_FIQ , 0x11
+ .equ Mode_IRQ , 0x12
+ .equ Mode_SVC , 0x13
+ .equ Mode_ABT , 0x17
+ .equ Mode_UND , 0x1B
+ .equ Mode_SYS , 0x1F
+
+ .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
+ .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
+ .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
+
+ .equ GIC_ERRATA_CHECK_1, 0x000003FE
+ .equ GIC_ERRATA_CHECK_2, 0x000003FF
+
+ .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+ .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+ .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
+ .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
+ .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+ .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
+ .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
+ .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
+
+ .equ RAM_BASE , 0x80000000
+ .equ VRAM_BASE , 0x18000000
+ .equ SRAM_BASE , 0x2e000000
+ .equ ETHERNET , 0x1a000000
+ .equ CS3_PERIPHERAL_BASE, 0x1c000000
+
+
+@ Stack Configuration
+
+ .EQU UND_Stack_Size , 0x00000100
+ .EQU SVC_Stack_Size , 0x00008000
+ .EQU ABT_Stack_Size , 0x00000100
+ .EQU FIQ_Stack_Size , 0x00000100
+ .EQU IRQ_Stack_Size , 0x00008000
+ .EQU USR_Stack_Size , 0x00004000
+
+ .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space ISR_Stack_Size
+__initial_sp:
+ .space USR_Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+
+@ Heap Configuration
+
+ .EQU Heap_Size , 0x00080000
+
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long 0xe59ff018 /* 0x00 */
+ .long 0xe59ff018 /* 0x04 */
+ .long 0xe59ff018 /* 0x08 */
+ .long 0xe59ff018 /* 0x0c */
+ .long 0xe59ff018 /* 0x10 */
+ .long 0xe59ff018 /* 0x14 */
+ .long 0xe59ff018 /* 0x18 */
+ .long 0xe59ff018 /* 0x1c */
+
+ .long Reset_Handler /* 0x20 */
+ .long Undef_Handler /* 0x24 */
+ .long SVC_Handler /* 0x28 */
+ .long PAbt_Handler /* 0x2c */
+ .long DAbt_Handler /* 0x30 */
+ .long 0 /* Reserved */
+ .long IRQ_Handler /* IRQ */
+ .long FIQ_Handler /* FIQ */
+
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ @ Put any cores other than 0 to sleep
+ mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
+ ands r0, r0, #3
+
+goToSleep:
+ wfine
+ bne goToSleep
+
+@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+@ Enables Full Access i.e. in both privileged and non privileged modes
+ mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
+ orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
+ mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
+ isb
+
+@ Switch on the VFP and NEON hardware
+ mov r0, #0x40000000
+ vmsr fpexc, r0 @ Write FPEXC register, EN bit set
+
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
+ bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
+ bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
+ bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
+ bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
+ bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
+ mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
+ isb
+
+@ Set Vector Base Address Register (VBAR) to point to this application's vector table
+ ldr r0, =__isr_vector
+ mcr p15, 0, r0, c12, c0, 0
+
+@ Setup Stack for each exceptional mode
+/* ldr r0, =__StackTop */
+ ldr r0, =(__StackTop - USR_Stack_Size)
+
+@ Enter Undefined Instruction Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #UND_Stack_Size
+
+@ Enter Abort Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #ABT_Stack_Size
+
+@ Enter FIQ Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #FIQ_Stack_Size
+
+@ Enter IRQ Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #IRQ_Stack_Size
+
+@ Enter Supervisor Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
+ mov sp, r0
+
+@ Enter System Mode to complete initialization and enter kernel
+ msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
+ mov sp, r0
+
+ isb
+ ldr r0, =RZ_A1_SetSramWriteEnable
+ blx r0
+
+ .extern create_translation_table
+ bl create_translation_table
+
+@ USR/SYS stack pointer will be set during kernel init
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =InitMemorySubsystem
+ blx r0
+
+@ fp_init
+ mov r0, #0x3000000
+ vmsr fpscr, r0
+
+
+@ data sections copy
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+
+@ bss sections clear
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+
+
+ ldr r0, =_start
+ bx r0
+
+ ldr r0, sf_boot @ dummy to keep boot loader area
+loop_here:
+ b loop_here
+
+sf_boot:
+ .word boot_loader
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .text
+
+Undef_Handler:
+ .global Undef_Handler
+ .func Undef_Handler
+ .extern CUndefHandler
+ SRSDB SP!, #Mode_UND
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
+
+ MRS R0, SPSR
+ TST R0, #T_Bit /* Check mode */
+ MOVEQ R1, #4 /* R1 = 4 ARM mode */
+ MOVNE R1, #2 /* R1 = 2 Thumb mode */
+ SUB R0, LR, R1
+ LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
+ BEQ undef_cont
+
+ /* Thumb instruction */
+ /* Determine if it is a 32-bit Thumb instruction */
+ LDRH R0, [R0]
+ MOV R2, #0x1c
+ CMP R2, R0, LSR #11
+ BHS undef_cont /* 16-bit Thumb instruction */
+
+ /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
+ LDRH R2, [LR]
+ ORR R0, R2, R0, LSL #16
+undef_cont:
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ /* R0 Offending instruction */
+ /* R1 =2 (Thumb) or =4 (ARM) */
+ BL CUndefHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
+ SUB LR, LR, R0
+ LDR R0, [SP, #28] /* Restore stacked SPSR */
+ MSR SPSR_cxsf, R0
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
+ MOVS PC, LR
+ .endfunc
+
+PAbt_Handler:
+ .global PAbt_Handler
+ .func PAbt_Handler
+ .extern CPAbtHandler
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ MRC p15, 0, R0, c5, c0, 1 /* IFSR */
+ MRC p15, 0, R1, c6, c0, 2 /* IFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CPAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stack APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+DAbt_Handler:
+ .global DAbt_Handler
+ .func DAbt_Handler
+ .extern CDAbtHandler
+ SUB LR, LR, #8 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ CLREX /* State of exclusive monitors unknown after taken data abort */
+ MRC p15, 0, R0, c5, c0, 0 /* DFSR */
+ MRC p15, 0, R1, c6, c0, 0 /* DFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CDAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+FIQ_Handler:
+ .global FIQ_Handler
+ .func FIQ_Handler
+ /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+ * so if a real FIQ Handler is implemented, this will be needed before returning:
+ */
+ /* LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+ */
+ B .
+ .endfunc
+
+ .extern SVC_Handler /* refer RTX function */
+
+IRQ_Handler:
+ .global IRQ_Handler
+ .func IRQ_Handler
+ .extern IRQCount
+ .extern IRQTable
+ .extern IRQNestLevel
+
+ /* prologue */
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
+ CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
+ PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
+
+/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R1, R3, #4
+ SUB SP, SP, R1 /* Adjust stack */
+ PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ ADD R1, R1, #1 /* Increment nesting counter */
+ STR R1, [R0]
+
+ /* identify and acknowledge interrupt */
+ LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
+ LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
+ DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
+
+ /* Workaround GIC 390 errata 733075
+ * If the ID is not 0, then service the interrupt as normal.
+ * If the ID is 0 and active, then service interrupt ID 0 as normal.
+ * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+ * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
+ */
+ LDR R2, =GICD_BASE
+ LDR R3, =GIC_ERRATA_CHECK_1
+ CMP R0, R3
+ BEQ unlock_cpu
+ LDR R3, =GIC_ERRATA_CHECK_2
+ CMP R0, R3
+ BEQ unlock_cpu
+ CMP R0, #0
+ BNE int_active /* If the ID is not 0, then service the interrupt */
+ LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
+ TST R3, #1
+ BNE int_active /* If active, then service the interrupt */
+unlock_cpu:
+ LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
+ STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
+ DSB /* Ensure the write completes before continuing */
+ B ret_irq /* Do not service the spurious interrupt */
+ /* End workaround */
+
+int_active:
+ LDR R2, =IRQCount /* Read number of IRQs */
+ LDR R2, [R2]
+ CMP R0, R2 /* Clean up and return if no handler */
+ BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
+ LDR R2, =IRQTable /* Get address of handler */
+ LDR R2, [R2, R0, LSL #2]
+ CMP R2, #0 /* Clean up and return if handler address is 0 */
+ BEQ ret_irq
+ PUSH {R0,R1}
+
+ CPSIE i /* Now safe to re-enable interrupts */
+ BLX R2 /* Call handler. R0 will be IRQ number */
+ CPSID i /* Disable interrupts again */
+
+ /* write EOIR (GIC CPU Interface register) */
+ POP {R0,R1}
+ DSB /* Ensure that interrupt source is cleared before we write the EOIR */
+ret_irq:
+ /* epilogue */
+ STR R0, [R1, #ICCEOIR_OFFSET]
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ SUB R1, R1, #1 /* Decrement nesting counter */
+ STR R1, [R0]
+
+ POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
+ ADD SP, SP, R1 /* Unadjust stack */
+
+ POP {R0-R3,R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler SVC_Handler
+
+
+/* User Initial Stack & Heap */
+
+ .ifdef __MICROLIB
+
+ .global __initial_sp
+ .global __heap_base
+ .global __heap_limit
+
+ .else
+
+ .extern __use_two_region_memory
+ .global __user_initial_stackheap
+__user_initial_stackheap:
+
+ LDR R0, = __HeapBase
+ LDR R1, =(__StackTop)
+ LDR R2, = (__HeapBase + Heap_Size)
+ LDR R3, = (__StackTop - USR_Stack_Size)
+ BX LR
+
+ .endif
+
+
+ .END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h
new file mode 100644
index 000000000..0f9a540cd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h
@@ -0,0 +1,12 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MBRZA1H.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c
new file mode 100644
index 000000000..052c30c74
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "MBRZA1H.h"
+
+extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t vectors = (uint32_t)IRQTable[IRQn];
+ return vectors;
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h
new file mode 100644
index 000000000..2ded075db
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h
new file mode 100644
index 000000000..deb2ebbc1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : dev_drv.h
+* $Rev: 809 $
+* $Date:: 2014-04-09 15:06:36 +0900#$
+* Description : Device driver header
+******************************************************************************/
+#ifndef DEV_DRV_H
+#define DEV_DRV_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== Arguments, Return values ==== */
+#define DEVDRV_SUCCESS (0) /* Success */
+#define DEVDRV_ERROR (-1) /* Failure */
+
+/* ==== Flags ==== */
+#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
+#define DEVDRV_FLAG_ON (1) /* Flag ON */
+
+/* ==== Channels ==== */
+typedef enum devdrv_ch
+{
+ DEVDRV_CH_0, /* Channel 0 */
+ DEVDRV_CH_1, /* Channel 1 */
+ DEVDRV_CH_2, /* Channel 2 */
+ DEVDRV_CH_3, /* Channel 3 */
+ DEVDRV_CH_4, /* Channel 4 */
+ DEVDRV_CH_5, /* Channel 5 */
+ DEVDRV_CH_6, /* Channel 6 */
+ DEVDRV_CH_7, /* Channel 7 */
+ DEVDRV_CH_8, /* Channel 8 */
+ DEVDRV_CH_9, /* Channel 9 */
+ DEVDRV_CH_10, /* Channel 10 */
+ DEVDRV_CH_11, /* Channel 11 */
+ DEVDRV_CH_12, /* Channel 12 */
+ DEVDRV_CH_13, /* Channel 13 */
+ DEVDRV_CH_14, /* Channel 14 */
+ DEVDRV_CH_15 /* Channel 15 */
+} devdrv_ch_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif /* DEV_DRV_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c
new file mode 100644
index 000000000..e33b11122
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c
@@ -0,0 +1,305 @@
+/**************************************************************************//**
+ * @file gic.c
+ * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date 19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#include "MBRZA1H.h"
+
+#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
+#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
+
+/* Globals for use of post-scatterloading code that must access GIC */
+const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
+const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
+
+void GIC_EnableDistributor(void)
+{
+ GICDistributor->ICDDCR |= 1; //enable distributor
+}
+
+void GIC_DisableDistributor(void)
+{
+ GICDistributor->ICDDCR &=~1; //disable distributor
+}
+
+uint32_t GIC_DistributorInfo(void)
+{
+ return (uint32_t)(GICDistributor->ICDICTR);
+}
+
+uint32_t GIC_DistributorImplementer(void)
+{
+ return (uint32_t)(GICDistributor->ICDIIDR);
+}
+
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+ field += IRQn % 4;
+ *field = (uint8_t)cpu_target & 0xf;
+}
+
+void GIC_SetICDICFR (const uint32_t *ICDICFRn)
+{
+ uint32_t i, num_irq;
+
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+ for (i = 0; i < (num_irq/16); i++)
+ {
+ GICDistributor->ICDISPR[i] = *ICDICFRn++;
+ }
+}
+
+uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+ field += IRQn % 4;
+ return ((uint32_t)*field & 0xf);
+}
+
+void GIC_EnableInterface(void)
+{
+ GICInterface->ICCICR |= 1; //enable interface
+}
+
+void GIC_DisableInterface(void)
+{
+ GICInterface->ICCICR &=~1; //disable distributor
+}
+
+IRQn_Type GIC_AcknowledgePending(void)
+{
+ return (IRQn_Type)(GICInterface->ICCIAR);
+}
+
+void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+ GICInterface->ICCEOIR = IRQn;
+}
+
+void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
+ int bit_shift = (IRQn % 16)<<1;
+ uint8_t save_byte;
+
+ field += (bit_shift / 8);
+ bit_shift %= 8;
+
+ save_byte = *field;
+ save_byte &= ((uint8_t)~(3u << bit_shift));
+
+ *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
+}
+
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+ field += (IRQn % 4);
+ *field = (uint8_t)priority;
+}
+
+uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+ field += (IRQn % 4);
+ return (uint32_t)*field;
+}
+
+void GIC_InterfacePriorityMask(uint32_t priority)
+{
+ GICInterface->ICCPMR = priority & 0xff; //set priority mask
+}
+
+void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+ GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+}
+
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+{
+ return (uint32_t)GICInterface->ICCBPR;
+}
+
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+ uint32_t pending, active;
+
+ active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+ pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+
+ return ((active<<1) | pending);
+}
+
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+ GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+}
+
+void GIC_DistInit(void)
+{
+ //IRQn_Type i;
+ uint32_t i;
+ uint32_t num_irq = 0;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableDistributor();
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0, 0xff);
+ priority_field = GIC_GetPriority((IRQn_Type)0);
+
+ for (i = 32; i < num_irq; i++)
+ {
+ //Disable all SPI the interrupts
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set level-sensitive and N-N model
+ //GIC_SetLevelModel(i, 0, 0);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2);
+ //Set target list to "all cpus"
+ GIC_SetTarget((IRQn_Type)i, 0xff);
+ }
+ /* Set level-edge and 1-N model */
+ /* GICDistributor->ICDICFR[ 0] is read only */
+ GICDistributor->ICDICFR[ 1] = 0x00000055;
+ GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
+ GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
+ GICDistributor->ICDICFR[ 4] = 0x55555555;
+ GICDistributor->ICDICFR[ 5] = 0x55555555;
+ GICDistributor->ICDICFR[ 6] = 0x55555555;
+ GICDistributor->ICDICFR[ 7] = 0x55555555;
+ GICDistributor->ICDICFR[ 8] = 0x5555F555;
+ GICDistributor->ICDICFR[ 9] = 0x55555555;
+ GICDistributor->ICDICFR[10] = 0x55555555;
+ GICDistributor->ICDICFR[11] = 0xF5555555;
+ GICDistributor->ICDICFR[12] = 0xF555F555;
+ GICDistributor->ICDICFR[13] = 0x5555F555;
+ GICDistributor->ICDICFR[14] = 0x55555555;
+ GICDistributor->ICDICFR[15] = 0x55555555;
+ GICDistributor->ICDICFR[16] = 0x55555555;
+ GICDistributor->ICDICFR[17] = 0xFD555555;
+ GICDistributor->ICDICFR[18] = 0x55555557;
+ GICDistributor->ICDICFR[19] = 0x55555555;
+ GICDistributor->ICDICFR[20] = 0xFFD55555;
+ GICDistributor->ICDICFR[21] = 0x5F55557F;
+ GICDistributor->ICDICFR[22] = 0xFD55555F;
+ GICDistributor->ICDICFR[23] = 0x55555557;
+ GICDistributor->ICDICFR[24] = 0x55555555;
+ GICDistributor->ICDICFR[25] = 0x55555555;
+ GICDistributor->ICDICFR[26] = 0x55555555;
+ GICDistributor->ICDICFR[27] = 0x55555555;
+ GICDistributor->ICDICFR[28] = 0x55555555;
+ GICDistributor->ICDICFR[29] = 0x55555555;
+ GICDistributor->ICDICFR[30] = 0x55555555;
+ GICDistributor->ICDICFR[31] = 0x55555555;
+ GICDistributor->ICDICFR[32] = 0x55555555;
+ GICDistributor->ICDICFR[33] = 0x55555555;
+
+ //Enable distributor
+ GIC_EnableDistributor();
+}
+
+void GIC_CPUInterfaceInit(void)
+{
+ IRQn_Type i;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableInterface();
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0, 0xff);
+ priority_field = GIC_GetPriority((IRQn_Type)0);
+
+ //SGI and PPI
+ for (i = (IRQn_Type)0; i < 32; i++)
+ {
+ //Set level-sensitive and N-N model for PPI
+ //if(i > 15)
+ //GIC_SetLevelModel(i, 0, 0);
+ //Disable SGI and PPI interrupts
+ GIC_DisableIRQ(i);
+ //Set priority
+ GIC_SetPriority(i, priority_field/2);
+ }
+ //Enable interface
+ GIC_EnableInterface();
+ //Set binary point to 0
+ GIC_SetBinaryPoint(0);
+ //Set priority mask
+ GIC_InterfacePriorityMask(0xff);
+}
+
+void GIC_Enable(void)
+{
+ GIC_DistInit();
+ GIC_CPUInterfaceInit(); //per CPU
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h
new file mode 100644
index 000000000..d4cbfd81a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h
@@ -0,0 +1,316 @@
+/**************************************************************************//**
+ * @file gic.h
+ * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date 29 August 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#ifndef GIC_H_
+#define GIC_H_
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
+ */
+typedef struct
+{
+ __IO uint32_t ICDDCR;
+ __I uint32_t ICDICTR;
+ __I uint32_t ICDIIDR;
+ uint32_t RESERVED0[29];
+ __IO uint32_t ICDISR[32];
+ __IO uint32_t ICDISER[32];
+ __IO uint32_t ICDICER[32];
+ __IO uint32_t ICDISPR[32];
+ __IO uint32_t ICDICPR[32];
+ __I uint32_t ICDABR[32];
+ uint32_t RESERVED1[32];
+ __IO uint32_t ICDIPR[256];
+ __IO uint32_t ICDIPTR[256];
+ __IO uint32_t ICDICFR[64];
+ uint32_t RESERVED2[128];
+ __IO uint32_t ICDSGIR;
+} GICDistributor_Type;
+
+/** \brief Structure type to access the Controller Interface (GICC)
+ */
+typedef struct
+{
+ __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
+ __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
+ __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
+ __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
+ __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
+ __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
+ __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
+ __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
+
+ uint32_t RESERVED[55];
+
+ __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
+} GICInterface_Type;
+
+/*@} end of GICD */
+
+/* ########################## GIC functions #################################### */
+/** \brief Functions that manage interrupts via the GIC.
+ @{
+ */
+
+/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
+
+ Enables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_EnableDistributor(void);
+
+/** \brief Disable Distributor
+
+ Disables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_DisableDistributor(void);
+
+/** \brief Provides information about the configuration of the GIC.
+ Provides information about the configuration of the GIC.
+ - whether the GIC implements the Security Extensions
+ - the maximum number of interrupt IDs that the GIC supports
+ - the number of CPU interfaces implemented
+ - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
+
+ \return Distributor Information.
+ */
+uint32_t GIC_DistributorInfo(void);
+
+/** \brief Distributor Implementer Identification Register.
+
+ Distributor Implementer Identification Register
+
+ \return Implementer Information.
+ */
+uint32_t GIC_DistributorImplementer(void);
+
+/** \brief Set list of processors that the interrupt is sent to if it is asserted.
+
+ The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+ This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] target CPU target
+ */
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
+
+/** \brief Get list of processors that the interrupt is sent to if it is asserted.
+
+ The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+ This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] target CPU target
+*/
+uint32_t GIC_GetTarget(IRQn_Type IRQn);
+
+/** \brief Enable Interface
+
+ Enables the signalling of interrupts to the target processors.
+
+ */
+void GIC_EnableInterface(void);
+
+/** \brief Disable Interface
+
+ Disables the signalling of interrupts to the target processors.
+
+ */
+void GIC_DisableInterface(void);
+
+/** \brief Acknowledge Interrupt
+
+ The function acknowledges the highest priority pending interrupt and returns its IRQ number.
+
+ \return Interrupt number
+ */
+IRQn_Type GIC_AcknowledgePending(void);
+
+/** \brief End Interrupt
+
+ The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
+
+ \param [in] IRQn Interrupt number.
+ */
+void GIC_EndInterrupt(IRQn_Type IRQn);
+
+
+/** \brief Enable Interrupt
+
+ Set-enable bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn External interrupt number.
+ */
+void GIC_EnableIRQ(IRQn_Type IRQn);
+
+/** \brief Disable Interrupt
+
+ Clear-enable bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+void GIC_DisableIRQ(IRQn_Type IRQn);
+
+/** \brief Set Pending Interrupt
+
+ Set-pending bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn Interrupt number.
+ */
+void GIC_SetPendingIRQ(IRQn_Type IRQn);
+
+/** \brief Clear Pending Interrupt
+
+ Clear-pending bit for each interrupt supported by the GIC
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+void GIC_ClearPendingIRQ(IRQn_Type IRQn);
+
+/** \brief Int_config field for each interrupt supported by the GIC.
+
+ This field identifies whether the corresponding interrupt is:
+ (1) edge-triggered or (0) level-sensitive
+ (1) 1-N model or (0) N-N model
+
+ \param [in] IRQn Interrupt number.
+ \param [in] edge_level (1) edge-triggered or (0) level-sensitive
+ \param [in] model (1) 1-N model or (0) N-N model
+ */
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ */
+uint32_t GIC_GetPriority(IRQn_Type IRQn);
+
+/** \brief CPU Interface Priority Mask Register
+
+ The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
+ value indicated by this field, the interface signals the interrupt to the processor.
+
+ \param [in] Mask.
+ */
+void GIC_InterfacePriorityMask(uint32_t priority);
+
+/** \brief Set the binary point.
+
+ Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+ \param [in] Mask.
+ */
+void GIC_SetBinaryPoint(uint32_t binary_point);
+
+/** \brief Get the binary point.
+
+ Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+ \return Binary point.
+ */
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
+
+/** \brief Get Interrupt state.
+
+ Get the interrupt state, whether pending and/or active
+
+ \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
+ */
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
+
+/** \brief Send Software Generated interrupt
+
+ Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
+GIC_InterfacePriorityMask
+ \param [in] IRQn The Interrupt ID of the SGI.
+ \param [in] target_list CPUTargetList
+ \param [in] filter_list TargetListFilter
+ */
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
+
+/** \brief API call to initialise the interrupt distributor
+
+ API call to initialise the interrupt distributor
+
+ */
+void GIC_DistInit(void);
+
+/** \brief API call to initialise the CPU interface
+
+ API call to initialise the CPU interface
+
+ */
+void GIC_CPUInterfaceInit(void);
+
+/** \brief API call to set the Interrupt Configuration Registers
+
+ API call to initialise the Interrupt Configuration Registers
+
+ */
+void GIC_SetICDICFR (const uint32_t *ICDICFRn);
+
+/** \brief API call to Enable the GIC
+
+ API call to Enable the GIC
+
+ */
+void GIC_Enable(void);
+
+#endif /* GIC_H_ */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h
new file mode 100644
index 000000000..1f016294b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h
@@ -0,0 +1,357 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : BSC register define header
+*******************************************************************************/
+#ifndef BSC_IOBITMASK_H
+#define BSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT (0x00000001uL)
+#define BSC_CMNCR_HIZMEM (0x00000002uL)
+#define BSC_CMNCR_DPRTY (0x00000600uL)
+#define BSC_CMNCR_AL0 (0x01000000uL)
+#define BSC_CMNCR_TL0 (0x10000000uL)
+
+#define BSC_CS0BCR_BSZ (0x00000600uL)
+#define BSC_CS0BCR_TYPE (0x00007000uL)
+#define BSC_CS0BCR_IWRRS (0x00070000uL)
+#define BSC_CS0BCR_IWRRD (0x00380000uL)
+#define BSC_CS0BCR_IWRWS (0x01C00000uL)
+#define BSC_CS0BCR_IWRWD (0x0E000000uL)
+#define BSC_CS0BCR_IWW (0x70000000uL)
+
+#define BSC_CS1BCR_BSZ (0x00000600uL)
+#define BSC_CS1BCR_TYPE (0x00007000uL)
+#define BSC_CS1BCR_IWRRS (0x00070000uL)
+#define BSC_CS1BCR_IWRRD (0x00380000uL)
+#define BSC_CS1BCR_IWRWS (0x01C00000uL)
+#define BSC_CS1BCR_IWRWD (0x0E000000uL)
+#define BSC_CS1BCR_IWW (0x70000000uL)
+
+#define BSC_CS2BCR_BSZ (0x00000600uL)
+#define BSC_CS2BCR_TYPE (0x00007000uL)
+#define BSC_CS2BCR_IWRRS (0x00070000uL)
+#define BSC_CS2BCR_IWRRD (0x00380000uL)
+#define BSC_CS2BCR_IWRWS (0x01C00000uL)
+#define BSC_CS2BCR_IWRWD (0x0E000000uL)
+#define BSC_CS2BCR_IWW (0x70000000uL)
+
+#define BSC_CS3BCR_BSZ (0x00000600uL)
+#define BSC_CS3BCR_TYPE (0x00007000uL)
+#define BSC_CS3BCR_IWRRS (0x00070000uL)
+#define BSC_CS3BCR_IWRRD (0x00380000uL)
+#define BSC_CS3BCR_IWRWS (0x01C00000uL)
+#define BSC_CS3BCR_IWRWD (0x0E000000uL)
+#define BSC_CS3BCR_IWW (0x70000000uL)
+
+#define BSC_CS4BCR_BSZ (0x00000600uL)
+#define BSC_CS4BCR_TYPE (0x00007000uL)
+#define BSC_CS4BCR_IWRRS (0x00070000uL)
+#define BSC_CS4BCR_IWRRD (0x00380000uL)
+#define BSC_CS4BCR_IWRWS (0x01C00000uL)
+#define BSC_CS4BCR_IWRWD (0x0E000000uL)
+#define BSC_CS4BCR_IWW (0x70000000uL)
+
+#define BSC_CS5BCR_BSZ (0x00000600uL)
+#define BSC_CS5BCR_TYPE (0x00007000uL)
+#define BSC_CS5BCR_IWRRS (0x00070000uL)
+#define BSC_CS5BCR_IWRRD (0x00380000uL)
+#define BSC_CS5BCR_IWRWS (0x01C00000uL)
+#define BSC_CS5BCR_IWRWD (0x0E000000uL)
+#define BSC_CS5BCR_IWW (0x70000000uL)
+
+#define BSC_CS0WCR_NORMAL_HW (0x00000003uL)
+#define BSC_CS0WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS0WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS0WCR_NORMAL_SW (0x00001800uL)
+#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL)
+
+#define BSC_CS1WCR_NORMAL_HW (0x00000003uL)
+#define BSC_CS1WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS1WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS1WCR_NORMAL_SW (0x00001800uL)
+#define BSC_CS1WCR_NORMAL_WW (0x00070000uL)
+#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL)
+
+#define BSC_CS2WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS2WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL)
+
+#define BSC_CS3WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS3WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL)
+
+#define BSC_CS4WCR_NORMAL_HW (0x00000003uL)
+#define BSC_CS4WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS4WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS4WCR_NORMAL_SW (0x00001800uL)
+#define BSC_CS4WCR_NORMAL_WW (0x00070000uL)
+#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL)
+
+#define BSC_CS5WCR_NORMAL_HW (0x00000003uL)
+#define BSC_CS5WCR_NORMAL_WM (0x00000040uL)
+#define BSC_CS5WCR_NORMAL_WR (0x00000780uL)
+#define BSC_CS5WCR_NORMAL_SW (0x00001800uL)
+#define BSC_CS5WCR_NORMAL_WW (0x00070000uL)
+#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL)
+#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL)
+
+#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL)
+#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL)
+#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL)
+#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL)
+
+#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL)
+#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL)
+#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL)
+#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL)
+#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL)
+#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL)
+
+#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL)
+
+#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL)
+#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL)
+#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL)
+#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL)
+#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL)
+
+#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL)
+#define BSC_CS0WCR_BROM_SY_W (0x00000780uL)
+#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL)
+
+#define BSC_SDCR_A3COL (0x00000003uL)
+#define BSC_SDCR_A3ROW (0x00000018uL)
+#define BSC_SDCR_BACTV (0x00000100uL)
+#define BSC_SDCR_PDOWN (0x00000200uL)
+#define BSC_SDCR_RMODE (0x00000400uL)
+#define BSC_SDCR_RFSH (0x00000800uL)
+#define BSC_SDCR_DEEP (0x00002000uL)
+#define BSC_SDCR_A2COL (0x00030000uL)
+#define BSC_SDCR_A2ROW (0x00180000uL)
+
+#define BSC_RTCSR_RRC (0x00000007uL)
+#define BSC_RTCSR_CKS (0x00000038uL)
+#define BSC_RTCSR_CMIE (0x00000040uL)
+#define BSC_RTCSR_CMF (0x00000080uL)
+
+#define BSC_RTCNT_D (0xFFFFFFFFuL)
+
+#define BSC_RTCOR_D (0xFFFFFFFFuL)
+
+#define BSC_TOSCOR0_D (0x0000FFFFuL)
+
+#define BSC_TOSCOR1_D (0x0000FFFFuL)
+
+#define BSC_TOSCOR2_D (0x0000FFFFuL)
+
+#define BSC_TOSCOR3_D (0x0000FFFFuL)
+
+#define BSC_TOSCOR4_D (0x0000FFFFuL)
+
+#define BSC_TOSCOR5_D (0x0000FFFFuL)
+
+#define BSC_TOSTR_CS0TOSTF (0x00000001uL)
+#define BSC_TOSTR_CS1TOSTF (0x00000002uL)
+#define BSC_TOSTR_CS2TOSTF (0x00000004uL)
+#define BSC_TOSTR_CS3TOSTF (0x00000008uL)
+#define BSC_TOSTR_CS4TOSTF (0x00000010uL)
+#define BSC_TOSTR_CS5TOSTF (0x00000020uL)
+
+#define BSC_TOENR_CS0TOEN (0x00000001uL)
+#define BSC_TOENR_CS1TOEN (0x00000002uL)
+#define BSC_TOENR_CS2TOEN (0x00000004uL)
+#define BSC_TOENR_CS3TOEN (0x00000008uL)
+#define BSC_TOENR_CS4TOEN (0x00000010uL)
+#define BSC_TOENR_CS5TOEN (0x00000020uL)
+
+
+/* ==== Shift values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT_SHIFT (0u)
+#define BSC_CMNCR_HIZMEM_SHIFT (1u)
+#define BSC_CMNCR_DPRTY_SHIFT (9u)
+#define BSC_CMNCR_AL0_SHIFT (24u)
+#define BSC_CMNCR_TL0_SHIFT (28u)
+
+#define BSC_CS0BCR_BSZ_SHIFT (9u)
+#define BSC_CS0BCR_TYPE_SHIFT (12u)
+#define BSC_CS0BCR_IWRRS_SHIFT (16u)
+#define BSC_CS0BCR_IWRRD_SHIFT (19u)
+#define BSC_CS0BCR_IWRWS_SHIFT (22u)
+#define BSC_CS0BCR_IWRWD_SHIFT (25u)
+#define BSC_CS0BCR_IWW_SHIFT (28u)
+
+#define BSC_CS1BCR_BSZ_SHIFT (9u)
+#define BSC_CS1BCR_TYPE_SHIFT (12u)
+#define BSC_CS1BCR_IWRRS_SHIFT (16u)
+#define BSC_CS1BCR_IWRRD_SHIFT (19u)
+#define BSC_CS1BCR_IWRWS_SHIFT (22u)
+#define BSC_CS1BCR_IWRWD_SHIFT (25u)
+#define BSC_CS1BCR_IWW_SHIFT (28u)
+
+#define BSC_CS2BCR_BSZ_SHIFT (9u)
+#define BSC_CS2BCR_TYPE_SHIFT (12u)
+#define BSC_CS2BCR_IWRRS_SHIFT (16u)
+#define BSC_CS2BCR_IWRRD_SHIFT (19u)
+#define BSC_CS2BCR_IWRWS_SHIFT (22u)
+#define BSC_CS2BCR_IWRWD_SHIFT (25u)
+#define BSC_CS2BCR_IWW_SHIFT (28u)
+
+#define BSC_CS3BCR_BSZ_SHIFT (9u)
+#define BSC_CS3BCR_TYPE_SHIFT (12u)
+#define BSC_CS3BCR_IWRRS_SHIFT (16u)
+#define BSC_CS3BCR_IWRRD_SHIFT (19u)
+#define BSC_CS3BCR_IWRWS_SHIFT (22u)
+#define BSC_CS3BCR_IWRWD_SHIFT (25u)
+#define BSC_CS3BCR_IWW_SHIFT (28u)
+
+#define BSC_CS4BCR_BSZ_SHIFT (9u)
+#define BSC_CS4BCR_TYPE_SHIFT (12u)
+#define BSC_CS4BCR_IWRRS_SHIFT (16u)
+#define BSC_CS4BCR_IWRRD_SHIFT (19u)
+#define BSC_CS4BCR_IWRWS_SHIFT (22u)
+#define BSC_CS4BCR_IWRWD_SHIFT (25u)
+#define BSC_CS4BCR_IWW_SHIFT (28u)
+
+#define BSC_CS5BCR_BSZ_SHIFT (9u)
+#define BSC_CS5BCR_TYPE_SHIFT (12u)
+#define BSC_CS5BCR_IWRRS_SHIFT (16u)
+#define BSC_CS5BCR_IWRRD_SHIFT (19u)
+#define BSC_CS5BCR_IWRWS_SHIFT (22u)
+#define BSC_CS5BCR_IWRWD_SHIFT (25u)
+#define BSC_CS5BCR_IWW_SHIFT (28u)
+
+#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u)
+#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u)
+#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u)
+
+#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u)
+#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u)
+#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u)
+#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u)
+
+#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u)
+
+#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u)
+
+#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u)
+#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u)
+#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u)
+#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u)
+
+#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u)
+#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u)
+#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u)
+#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u)
+#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u)
+#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
+#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u)
+
+#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u)
+#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u)
+#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u)
+#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u)
+
+#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u)
+#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u)
+#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u)
+#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u)
+#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u)
+#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u)
+
+#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u)
+
+#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u)
+#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u)
+#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u)
+#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u)
+#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u)
+
+#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u)
+#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u)
+#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u)
+
+#define BSC_SDCR_A3COL_SHIFT (0u)
+#define BSC_SDCR_A3ROW_SHIFT (3u)
+#define BSC_SDCR_BACTV_SHIFT (8u)
+#define BSC_SDCR_PDOWN_SHIFT (9u)
+#define BSC_SDCR_RMODE_SHIFT (10u)
+#define BSC_SDCR_RFSH_SHIFT (11u)
+#define BSC_SDCR_DEEP_SHIFT (13u)
+#define BSC_SDCR_A2COL_SHIFT (16u)
+#define BSC_SDCR_A2ROW_SHIFT (19u)
+
+#define BSC_RTCSR_RRC_SHIFT (0u)
+#define BSC_RTCSR_CKS_SHIFT (3u)
+#define BSC_RTCSR_CMIE_SHIFT (6u)
+#define BSC_RTCSR_CMF_SHIFT (7u)
+
+#define BSC_RTCNT_D_SHIFT (0u)
+
+#define BSC_RTCOR_D_SHIFT (0u)
+
+#define BSC_TOSCOR0_D_SHIFT (0u)
+
+#define BSC_TOSCOR1_D_SHIFT (0u)
+
+#define BSC_TOSCOR2_D_SHIFT (0u)
+
+#define BSC_TOSCOR3_D_SHIFT (0u)
+
+#define BSC_TOSCOR4_D_SHIFT (0u)
+
+#define BSC_TOSCOR5_D_SHIFT (0u)
+
+#define BSC_TOSTR_CS0TOSTF_SHIFT (0u)
+#define BSC_TOSTR_CS1TOSTF_SHIFT (1u)
+#define BSC_TOSTR_CS2TOSTF_SHIFT (2u)
+#define BSC_TOSTR_CS3TOSTF_SHIFT (3u)
+#define BSC_TOSTR_CS4TOSTF_SHIFT (4u)
+#define BSC_TOSTR_CS5TOSTF_SHIFT (5u)
+
+#define BSC_TOENR_CS0TOEN_SHIFT (0u)
+#define BSC_TOENR_CS1TOEN_SHIFT (1u)
+#define BSC_TOENR_CS2TOEN_SHIFT (2u)
+#define BSC_TOENR_CS3TOEN_SHIFT (3u)
+#define BSC_TOENR_CS4TOEN_SHIFT (4u)
+#define BSC_TOENR_CS5TOEN_SHIFT (5u)
+
+
+#endif /* BSC_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h
new file mode 100644
index 000000000..d1a7717f8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h
@@ -0,0 +1,461 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : CPG register define header
+*******************************************************************************/
+#ifndef CPG_IOBITMASK_H
+#define CPG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define CPG_FRQCR_IFC (0x0300u)
+#define CPG_FRQCR_CKOEN (0x3000u)
+#define CPG_FRQCR_CKOEN2 (0x4000u)
+
+#define CPG_FRQCR2_GFC (0x0003u)
+
+#define CPG_CPUSTS_ISBUSY (0x10u)
+
+#define CPG_STBCR1_DEEP (0x40u)
+#define CPG_STBCR1_STBY (0x80u)
+
+#define CPG_STBCR2_MSTP20 (0x01u)
+#define CPG_STBCR2_HIZ (0x80u)
+
+#define CPG_STBREQ1_STBRQ10 (0x01u)
+#define CPG_STBREQ1_STBRQ12 (0x04u)
+#define CPG_STBREQ1_STBRQ13 (0x08u)
+#define CPG_STBREQ1_STBRQ15 (0x20u)
+
+#define CPG_STBREQ2_STBRQ20 (0x01u)
+#define CPG_STBREQ2_STBRQ21 (0x02u)
+#define CPG_STBREQ2_STBRQ22 (0x04u)
+#define CPG_STBREQ2_STBRQ23 (0x08u)
+#define CPG_STBREQ2_STBRQ24 (0x10u)
+#define CPG_STBREQ2_STBRQ25 (0x20u)
+#define CPG_STBREQ2_STBRQ26 (0x40u)
+#define CPG_STBREQ2_STBRQ27 (0x80u)
+
+#define CPG_STBACK1_STBAK10 (0x01u)
+#define CPG_STBACK1_STBAK12 (0x04u)
+#define CPG_STBACK1_STBAK13 (0x08u)
+#define CPG_STBACK1_STBAK15 (0x20u)
+
+#define CPG_STBACK2_STBAK20 (0x01u)
+#define CPG_STBACK2_STBAK21 (0x02u)
+#define CPG_STBACK2_STBAK22 (0x04u)
+#define CPG_STBACK2_STBAK23 (0x08u)
+#define CPG_STBACK2_STBAK24 (0x10u)
+#define CPG_STBACK2_STBAK25 (0x20u)
+#define CPG_STBACK2_STBAK26 (0x40u)
+#define CPG_STBACK2_STBAK27 (0x80u)
+
+#define CPG_SYSCR1_VRAME0 (0x01u)
+#define CPG_SYSCR1_VRAME1 (0x02u)
+#define CPG_SYSCR1_VRAME2 (0x04u)
+#define CPG_SYSCR1_VRAME3 (0x08u)
+#define CPG_SYSCR1_VRAME4 (0x10u)
+
+#define CPG_SYSCR2_VRAMWE0 (0x01u)
+#define CPG_SYSCR2_VRAMWE1 (0x02u)
+#define CPG_SYSCR2_VRAMWE2 (0x04u)
+#define CPG_SYSCR2_VRAMWE3 (0x08u)
+#define CPG_SYSCR2_VRAMWE4 (0x10u)
+
+#define CPG_SYSCR3_RRAMWE0 (0x01u)
+#define CPG_SYSCR3_RRAMWE1 (0x02u)
+#define CPG_SYSCR3_RRAMWE2 (0x04u)
+#define CPG_SYSCR3_RRAMWE3 (0x08u)
+
+#define CPG_STBCR3_MSTP30 (0x01u)
+#define CPG_STBCR3_MSTP31 (0x02u)
+#define CPG_STBCR3_MSTP32 (0x04u)
+#define CPG_STBCR3_MSTP33 (0x08u)
+#define CPG_STBCR3_MSTP34 (0x10u)
+#define CPG_STBCR3_MSTP35 (0x20u)
+#define CPG_STBCR3_MSTP36 (0x40u)
+#define CPG_STBCR3_MSTP37 (0x80u)
+
+#define CPG_STBCR4_MSTP40 (0x01u)
+#define CPG_STBCR4_MSTP41 (0x02u)
+#define CPG_STBCR4_MSTP42 (0x04u)
+#define CPG_STBCR4_MSTP43 (0x08u)
+#define CPG_STBCR4_MSTP44 (0x10u)
+#define CPG_STBCR4_MSTP45 (0x20u)
+#define CPG_STBCR4_MSTP46 (0x40u)
+#define CPG_STBCR4_MSTP47 (0x80u)
+
+#define CPG_STBCR5_MSTP50 (0x01u)
+#define CPG_STBCR5_MSTP51 (0x02u)
+#define CPG_STBCR5_MSTP52 (0x04u)
+#define CPG_STBCR5_MSTP53 (0x08u)
+#define CPG_STBCR5_MSTP54 (0x10u)
+#define CPG_STBCR5_MSTP55 (0x20u)
+#define CPG_STBCR5_MSTP56 (0x40u)
+#define CPG_STBCR5_MSTP57 (0x80u)
+
+#define CPG_STBCR6_MSTP60 (0x01u)
+#define CPG_STBCR6_MSTP61 (0x02u)
+#define CPG_STBCR6_MSTP62 (0x04u)
+#define CPG_STBCR6_MSTP63 (0x08u)
+#define CPG_STBCR6_MSTP64 (0x10u)
+#define CPG_STBCR6_MSTP65 (0x20u)
+#define CPG_STBCR6_MSTP66 (0x40u)
+#define CPG_STBCR6_MSTP67 (0x80u)
+
+#define CPG_STBCR7_MSTP70 (0x01u)
+#define CPG_STBCR7_MSTP71 (0x02u)
+#define CPG_STBCR7_MSTP73 (0x08u)
+#define CPG_STBCR7_MSTP74 (0x10u)
+#define CPG_STBCR7_MSTP76 (0x40u)
+#define CPG_STBCR7_MSTP77 (0x80u)
+
+#define CPG_STBCR8_MSTP81 (0x02u)
+#define CPG_STBCR8_MSTP82 (0x04u)
+#define CPG_STBCR8_MSTP83 (0x08u)
+#define CPG_STBCR8_MSTP84 (0x10u)
+#define CPG_STBCR8_MSTP85 (0x20u)
+#define CPG_STBCR8_MSTP86 (0x40u)
+#define CPG_STBCR8_MSTP87 (0x80u)
+
+#define CPG_STBCR9_MSTP90 (0x01u)
+#define CPG_STBCR9_MSTP91 (0x02u)
+#define CPG_STBCR9_MSTP92 (0x04u)
+#define CPG_STBCR9_MSTP93 (0x08u)
+#define CPG_STBCR9_MSTP94 (0x10u)
+#define CPG_STBCR9_MSTP95 (0x20u)
+#define CPG_STBCR9_MSTP96 (0x40u)
+#define CPG_STBCR9_MSTP97 (0x80u)
+
+#define CPG_STBCR10_MSTP100 (0x01u)
+#define CPG_STBCR10_MSTP101 (0x02u)
+#define CPG_STBCR10_MSTP102 (0x04u)
+#define CPG_STBCR10_MSTP103 (0x08u)
+#define CPG_STBCR10_MSTP104 (0x10u)
+#define CPG_STBCR10_MSTP105 (0x20u)
+#define CPG_STBCR10_MSTP106 (0x40u)
+#define CPG_STBCR10_MSTP107 (0x80u)
+
+#define CPG_STBCR11_MSTP110 (0x01u)
+#define CPG_STBCR11_MSTP111 (0x02u)
+#define CPG_STBCR11_MSTP112 (0x04u)
+#define CPG_STBCR11_MSTP113 (0x08u)
+#define CPG_STBCR11_MSTP114 (0x10u)
+#define CPG_STBCR11_MSTP115 (0x20u)
+
+#define CPG_STBCR12_MSTP120 (0x01u)
+#define CPG_STBCR12_MSTP121 (0x02u)
+#define CPG_STBCR12_MSTP122 (0x04u)
+#define CPG_STBCR12_MSTP123 (0x08u)
+
+#define CPG_STBCR13_MSTP131 (0x02u)
+#define CPG_STBCR13_MSTP132 (0x04u)
+
+#define CPG_SWRSTCR1_SRST11 (0x02u)
+#define CPG_SWRSTCR1_SRST12 (0x04u)
+#define CPG_SWRSTCR1_SRST13 (0x08u)
+#define CPG_SWRSTCR1_SRST14 (0x10u)
+#define CPG_SWRSTCR1_SRST15 (0x20u)
+#define CPG_SWRSTCR1_SRST16 (0x40u)
+#define CPG_SWRSTCR1_AXTALE (0x80u)
+
+#define CPG_SWRSTCR2_SRST21 (0x02u)
+
+#define CPG_SWRSTCR3_SRST32 (0x04u)
+
+#define CPG_RRAMKP_RRAMKP0 (0x01u)
+#define CPG_RRAMKP_RRAMKP1 (0x02u)
+#define CPG_RRAMKP_RRAMKP2 (0x04u)
+#define CPG_RRAMKP_RRAMKP3 (0x08u)
+
+#define CPG_DSCTR_RAMBOOT (0x40u)
+#define CPG_DSCTR_EBUSKEEPE (0x80u)
+
+#define CPG_DSSSR_P8_2 (0x0001u)
+#define CPG_DSSSR_P9_1 (0x0002u)
+#define CPG_DSSSR_P2_15 (0x0004u)
+#define CPG_DSSSR_P7_8 (0x0008u)
+#define CPG_DSSSR_P5_9 (0x0010u)
+#define CPG_DSSSR_P6_4 (0x0020u)
+#define CPG_DSSSR_RTCAR (0x0040u)
+#define CPG_DSSSR_NMI (0x0100u)
+#define CPG_DSSSR_P3_3 (0x0200u)
+#define CPG_DSSSR_P8_7 (0x0400u)
+#define CPG_DSSSR_P2_12 (0x0800u)
+#define CPG_DSSSR_P3_1 (0x1000u)
+#define CPG_DSSSR_P3_9 (0x2000u)
+#define CPG_DSSSR_P6_2 (0x4000u)
+
+#define CPG_DSESR_P8_2E (0x0001u)
+#define CPG_DSESR_P9_1E (0x0002u)
+#define CPG_DSESR_P2_15E (0x0004u)
+#define CPG_DSESR_P7_8E (0x0008u)
+#define CPG_DSESR_P5_9E (0x0010u)
+#define CPG_DSESR_P6_4E (0x0020u)
+#define CPG_DSESR_NMIE (0x0100u)
+#define CPG_DSESR_P3_3E (0x0200u)
+#define CPG_DSESR_P8_7E (0x0400u)
+#define CPG_DSESR_P2_12E (0x0800u)
+#define CPG_DSESR_P3_1E (0x1000u)
+#define CPG_DSESR_P3_9E (0x2000u)
+#define CPG_DSESR_P6_2E (0x4000u)
+
+#define CPG_DSFR_P8_2F (0x0001u)
+#define CPG_DSFR_P9_1F (0x0002u)
+#define CPG_DSFR_P2_15F (0x0004u)
+#define CPG_DSFR_P7_8F (0x0008u)
+#define CPG_DSFR_P5_9F (0x0010u)
+#define CPG_DSFR_P6_4F (0x0020u)
+#define CPG_DSFR_RTCARF (0x0040u)
+#define CPG_DSFR_NMIF (0x0100u)
+#define CPG_DSFR_P3_3F (0x0200u)
+#define CPG_DSFR_P8_7F (0x0400u)
+#define CPG_DSFR_P2_12F (0x0800u)
+#define CPG_DSFR_P3_1F (0x1000u)
+#define CPG_DSFR_P3_9F (0x2000u)
+#define CPG_DSFR_P6_2F (0x4000u)
+#define CPG_DSFR_IOKEEP (0x8000u)
+
+#define CPG_XTALCTR_GAIN0 (0x01u)
+#define CPG_XTALCTR_GAIN1 (0x02u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define CPG_FRQCR_IFC_SHIFT (8u)
+#define CPG_FRQCR_CKOEN_SHIFT (12u)
+#define CPG_FRQCR_CKOEN2_SHIFT (14u)
+
+#define CPG_FRQCR2_GFC_SHIFT (0u)
+
+#define CPG_CPUSTS_ISBUSY_SHIFT (4u)
+
+#define CPG_STBCR1_DEEP_SHIFT (6u)
+#define CPG_STBCR1_STBY_SHIFT (7u)
+
+#define CPG_STBCR2_MSTP20_SHIFT (0u)
+#define CPG_STBCR2_HIZ_SHIFT (7u)
+
+#define CPG_STBREQ1_STBRQ10_SHIFT (0u)
+#define CPG_STBREQ1_STBRQ12_SHIFT (2u)
+#define CPG_STBREQ1_STBRQ13_SHIFT (3u)
+#define CPG_STBREQ1_STBRQ15_SHIFT (5u)
+
+#define CPG_STBREQ2_STBRQ20_SHIFT (0u)
+#define CPG_STBREQ2_STBRQ21_SHIFT (1u)
+#define CPG_STBREQ2_STBRQ22_SHIFT (2u)
+#define CPG_STBREQ2_STBRQ23_SHIFT (3u)
+#define CPG_STBREQ2_STBRQ24_SHIFT (4u)
+#define CPG_STBREQ2_STBRQ25_SHIFT (5u)
+#define CPG_STBREQ2_STBRQ26_SHIFT (6u)
+#define CPG_STBREQ2_STBRQ27_SHIFT (7u)
+
+#define CPG_STBACK1_STBAK10_SHIFT (0u)
+#define CPG_STBACK1_STBAK12_SHIFT (2u)
+#define CPG_STBACK1_STBAK13_SHIFT (3u)
+#define CPG_STBACK1_STBAK15_SHIFT (5u)
+
+#define CPG_STBACK2_STBAK20_SHIFT (0u)
+#define CPG_STBACK2_STBAK21_SHIFT (1u)
+#define CPG_STBACK2_STBAK22_SHIFT (2u)
+#define CPG_STBACK2_STBAK23_SHIFT (3u)
+#define CPG_STBACK2_STBAK24_SHIFT (4u)
+#define CPG_STBACK2_STBAK25_SHIFT (5u)
+#define CPG_STBACK2_STBAK26_SHIFT (6u)
+#define CPG_STBACK2_STBAK27_SHIFT (7u)
+
+#define CPG_SYSCR1_VRAME0_SHIFT (0u)
+#define CPG_SYSCR1_VRAME1_SHIFT (1u)
+#define CPG_SYSCR1_VRAME2_SHIFT (2u)
+#define CPG_SYSCR1_VRAME3_SHIFT (3u)
+#define CPG_SYSCR1_VRAME4_SHIFT (4u)
+
+#define CPG_SYSCR2_VRAMWE0_SHIFT (0u)
+#define CPG_SYSCR2_VRAMWE1_SHIFT (1u)
+#define CPG_SYSCR2_VRAMWE2_SHIFT (2u)
+#define CPG_SYSCR2_VRAMWE3_SHIFT (3u)
+#define CPG_SYSCR2_VRAMWE4_SHIFT (4u)
+
+#define CPG_SYSCR3_RRAMWE0_SHIFT (0u)
+#define CPG_SYSCR3_RRAMWE1_SHIFT (1u)
+#define CPG_SYSCR3_RRAMWE2_SHIFT (2u)
+#define CPG_SYSCR3_RRAMWE3_SHIFT (3u)
+
+#define CPG_STBCR3_MSTP30_SHIFT (0u)
+#define CPG_STBCR3_MSTP31_SHIFT (1u)
+#define CPG_STBCR3_MSTP32_SHIFT (2u)
+#define CPG_STBCR3_MSTP33_SHIFT (3u)
+#define CPG_STBCR3_MSTP34_SHIFT (4u)
+#define CPG_STBCR3_MSTP35_SHIFT (5u)
+#define CPG_STBCR3_MSTP36_SHIFT (6u)
+#define CPG_STBCR3_MSTP37_SHIFT (7u)
+
+#define CPG_STBCR4_MSTP40_SHIFT (0u)
+#define CPG_STBCR4_MSTP41_SHIFT (1u)
+#define CPG_STBCR4_MSTP42_SHIFT (2u)
+#define CPG_STBCR4_MSTP43_SHIFT (3u)
+#define CPG_STBCR4_MSTP44_SHIFT (4u)
+#define CPG_STBCR4_MSTP45_SHIFT (5u)
+#define CPG_STBCR4_MSTP46_SHIFT (6u)
+#define CPG_STBCR4_MSTP47_SHIFT (7u)
+
+#define CPG_STBCR5_MSTP50_SHIFT (0u)
+#define CPG_STBCR5_MSTP51_SHIFT (1u)
+#define CPG_STBCR5_MSTP52_SHIFT (2u)
+#define CPG_STBCR5_MSTP53_SHIFT (3u)
+#define CPG_STBCR5_MSTP54_SHIFT (4u)
+#define CPG_STBCR5_MSTP55_SHIFT (5u)
+#define CPG_STBCR5_MSTP56_SHIFT (6u)
+#define CPG_STBCR5_MSTP57_SHIFT (7u)
+
+#define CPG_STBCR6_MSTP60_SHIFT (0u)
+#define CPG_STBCR6_MSTP61_SHIFT (1u)
+#define CPG_STBCR6_MSTP62_SHIFT (2u)
+#define CPG_STBCR6_MSTP63_SHIFT (3u)
+#define CPG_STBCR6_MSTP64_SHIFT (4u)
+#define CPG_STBCR6_MSTP65_SHIFT (5u)
+#define CPG_STBCR6_MSTP66_SHIFT (6u)
+#define CPG_STBCR6_MSTP67_SHIFT (7u)
+
+#define CPG_STBCR7_MSTP70_SHIFT (0u)
+#define CPG_STBCR7_MSTP71_SHIFT (1u)
+#define CPG_STBCR7_MSTP73_SHIFT (3u)
+#define CPG_STBCR7_MSTP74_SHIFT (4u)
+#define CPG_STBCR7_MSTP76_SHIFT (6u)
+#define CPG_STBCR7_MSTP77_SHIFT (7u)
+
+#define CPG_STBCR8_MSTP81_SHIFT (1u)
+#define CPG_STBCR8_MSTP82_SHIFT (2u)
+#define CPG_STBCR8_MSTP83_SHIFT (3u)
+#define CPG_STBCR8_MSTP84_SHIFT (4u)
+#define CPG_STBCR8_MSTP85_SHIFT (5u)
+#define CPG_STBCR8_MSTP86_SHIFT (6u)
+#define CPG_STBCR8_MSTP87_SHIFT (7u)
+
+#define CPG_STBCR9_MSTP90_SHIFT (0u)
+#define CPG_STBCR9_MSTP91_SHIFT (1u)
+#define CPG_STBCR9_MSTP92_SHIFT (2u)
+#define CPG_STBCR9_MSTP93_SHIFT (3u)
+#define CPG_STBCR9_MSTP94_SHIFT (4u)
+#define CPG_STBCR9_MSTP95_SHIFT (5u)
+#define CPG_STBCR9_MSTP96_SHIFT (6u)
+#define CPG_STBCR9_MSTP97_SHIFT (7u)
+
+#define CPG_STBCR10_MSTP100_SHIFT (0u)
+#define CPG_STBCR10_MSTP101_SHIFT (1u)
+#define CPG_STBCR10_MSTP102_SHIFT (2u)
+#define CPG_STBCR10_MSTP103_SHIFT (3u)
+#define CPG_STBCR10_MSTP104_SHIFT (4u)
+#define CPG_STBCR10_MSTP105_SHIFT (5u)
+#define CPG_STBCR10_MSTP106_SHIFT (6u)
+#define CPG_STBCR10_MSTP107_SHIFT (7u)
+
+#define CPG_STBCR11_MSTP110_SHIFT (0u)
+#define CPG_STBCR11_MSTP111_SHIFT (1u)
+#define CPG_STBCR11_MSTP112_SHIFT (2u)
+#define CPG_STBCR11_MSTP113_SHIFT (3u)
+#define CPG_STBCR11_MSTP114_SHIFT (4u)
+#define CPG_STBCR11_MSTP115_SHIFT (5u)
+
+#define CPG_STBCR12_MSTP120_SHIFT (0u)
+#define CPG_STBCR12_MSTP121_SHIFT (1u)
+#define CPG_STBCR12_MSTP122_SHIFT (2u)
+#define CPG_STBCR12_MSTP123_SHIFT (3u)
+
+#define CPG_STBCR13_MSTP131_SHIFT (1u)
+#define CPG_STBCR13_MSTP132_SHIFT (2u)
+
+#define CPG_SWRSTCR1_SRST11_SHIFT (1u)
+#define CPG_SWRSTCR1_SRST12_SHIFT (2u)
+#define CPG_SWRSTCR1_SRST13_SHIFT (3u)
+#define CPG_SWRSTCR1_SRST14_SHIFT (4u)
+#define CPG_SWRSTCR1_SRST15_SHIFT (5u)
+#define CPG_SWRSTCR1_SRST16_SHIFT (6u)
+#define CPG_SWRSTCR1_AXTALE_SHIFT (7u)
+
+#define CPG_SWRSTCR2_SRST21_SHIFT (1u)
+
+#define CPG_SWRSTCR3_SRST32_SHIFT (2u)
+
+#define CPG_RRAMKP_RRAMKP0_SHIFT (0u)
+#define CPG_RRAMKP_RRAMKP1_SHIFT (1u)
+#define CPG_RRAMKP_RRAMKP2_SHIFT (2u)
+#define CPG_RRAMKP_RRAMKP3_SHIFT (3u)
+
+#define CPG_DSCTR_RAMBOOT_SHIFT (6u)
+#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u)
+
+#define CPG_DSSSR_P8_2_SHIFT (0u)
+#define CPG_DSSSR_P9_1_SHIFT (1u)
+#define CPG_DSSSR_P2_15_SHIFT (2u)
+#define CPG_DSSSR_P7_8_SHIFT (3u)
+#define CPG_DSSSR_P5_9_SHIFT (4u)
+#define CPG_DSSSR_P6_4_SHIFT (5u)
+#define CPG_DSSSR_RTCAR_SHIFT (6u)
+#define CPG_DSSSR_NMI_SHIFT (8u)
+#define CPG_DSSSR_P3_3_SHIFT (9u)
+#define CPG_DSSSR_P8_7_SHIFT (10u)
+#define CPG_DSSSR_P2_12_SHIFT (11u)
+#define CPG_DSSSR_P3_1_SHIFT (12u)
+#define CPG_DSSSR_P3_9_SHIFT (13u)
+#define CPG_DSSSR_P6_2_SHIFT (14u)
+
+#define CPG_DSESR_P8_2E_SHIFT (0u)
+#define CPG_DSESR_P9_1E_SHIFT (1u)
+#define CPG_DSESR_P2_15E_SHIFT (2u)
+#define CPG_DSESR_P7_8E_SHIFT (3u)
+#define CPG_DSESR_P5_9E_SHIFT (4u)
+#define CPG_DSESR_P6_4E_SHIFT (5u)
+#define CPG_DSESR_NMIE_SHIFT (8u)
+#define CPG_DSESR_P3_3E_SHIFT (9u)
+#define CPG_DSESR_P8_7E_SHIFT (10u)
+#define CPG_DSESR_P2_12E_SHIFT (11u)
+#define CPG_DSESR_P3_1E_SHIFT (12u)
+#define CPG_DSESR_P3_9E_SHIFT (13u)
+#define CPG_DSESR_P6_2E_SHIFT (14u)
+
+#define CPG_DSFR_P8_2F_SHIFT (0u)
+#define CPG_DSFR_P9_1F_SHIFT (1u)
+#define CPG_DSFR_P2_15F_SHIFT (2u)
+#define CPG_DSFR_P7_8F_SHIFT (3u)
+#define CPG_DSFR_P5_9F_SHIFT (4u)
+#define CPG_DSFR_P6_4F_SHIFT (5u)
+#define CPG_DSFR_RTCARF_SHIFT (6u)
+#define CPG_DSFR_NMIF_SHIFT (8u)
+#define CPG_DSFR_P3_3F_SHIFT (9u)
+#define CPG_DSFR_P8_7F_SHIFT (10u)
+#define CPG_DSFR_P2_12F_SHIFT (11u)
+#define CPG_DSFR_P3_1F_SHIFT (12u)
+#define CPG_DSFR_P3_9F_SHIFT (13u)
+#define CPG_DSFR_P6_2F_SHIFT (14u)
+#define CPG_DSFR_IOKEEP_SHIFT (15u)
+
+#define CPG_XTALCTR_GAIN0_SHIFT (0u)
+#define CPG_XTALCTR_GAIN1_SHIFT (1u)
+
+
+#endif /* CPG_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h
new file mode 100644
index 000000000..559a060a5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h
@@ -0,0 +1,2675 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dmac_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : DMAC register define header
+*******************************************************************************/
+#ifndef DMAC_IOBITMASK_H
+#define DMAC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC0_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC0_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC0_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC0_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC0_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC0_CHSTAT_n_EN (0x00000001uL)
+#define DMAC0_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC0_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC0_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC0_CHSTAT_n_ER (0x00000010uL)
+#define DMAC0_CHSTAT_n_END (0x00000020uL)
+#define DMAC0_CHSTAT_n_TC (0x00000040uL)
+#define DMAC0_CHSTAT_n_SR (0x00000080uL)
+#define DMAC0_CHSTAT_n_DL (0x00000100uL)
+#define DMAC0_CHSTAT_n_DW (0x00000200uL)
+#define DMAC0_CHSTAT_n_DER (0x00000400uL)
+#define DMAC0_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC0_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC0_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC0_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC0_CHCTRL_n_STG (0x00000004uL)
+#define DMAC0_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC0_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC0_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC0_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC0_CHCFG_n_SEL (0x00000007uL)
+#define DMAC0_CHCFG_n_REQD (0x00000008uL)
+#define DMAC0_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC0_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC0_CHCFG_n_LVL (0x00000040uL)
+#define DMAC0_CHCFG_n_AM (0x00000700uL)
+#define DMAC0_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC0_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC0_CHCFG_n_SAD (0x00100000uL)
+#define DMAC0_CHCFG_n_DAD (0x00200000uL)
+#define DMAC0_CHCFG_n_TM (0x00400000uL)
+#define DMAC0_CHCFG_n_DEM (0x01000000uL)
+#define DMAC0_CHCFG_n_TCM (0x02000000uL)
+#define DMAC0_CHCFG_n_SBE (0x08000000uL)
+#define DMAC0_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC0_CHCFG_n_RSW (0x20000000uL)
+#define DMAC0_CHCFG_n_REN (0x40000000uL)
+#define DMAC0_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC0_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC0_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC1_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC1_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC1_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC1_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC1_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC1_CHSTAT_n_EN (0x00000001uL)
+#define DMAC1_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC1_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC1_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC1_CHSTAT_n_ER (0x00000010uL)
+#define DMAC1_CHSTAT_n_END (0x00000020uL)
+#define DMAC1_CHSTAT_n_TC (0x00000040uL)
+#define DMAC1_CHSTAT_n_SR (0x00000080uL)
+#define DMAC1_CHSTAT_n_DL (0x00000100uL)
+#define DMAC1_CHSTAT_n_DW (0x00000200uL)
+#define DMAC1_CHSTAT_n_DER (0x00000400uL)
+#define DMAC1_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC1_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC1_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC1_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC1_CHCTRL_n_STG (0x00000004uL)
+#define DMAC1_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC1_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC1_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC1_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC1_CHCFG_n_SEL (0x00000007uL)
+#define DMAC1_CHCFG_n_REQD (0x00000008uL)
+#define DMAC1_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC1_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC1_CHCFG_n_LVL (0x00000040uL)
+#define DMAC1_CHCFG_n_AM (0x00000700uL)
+#define DMAC1_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC1_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC1_CHCFG_n_SAD (0x00100000uL)
+#define DMAC1_CHCFG_n_DAD (0x00200000uL)
+#define DMAC1_CHCFG_n_TM (0x00400000uL)
+#define DMAC1_CHCFG_n_DEM (0x01000000uL)
+#define DMAC1_CHCFG_n_TCM (0x02000000uL)
+#define DMAC1_CHCFG_n_SBE (0x08000000uL)
+#define DMAC1_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC1_CHCFG_n_RSW (0x20000000uL)
+#define DMAC1_CHCFG_n_REN (0x40000000uL)
+#define DMAC1_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC1_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC1_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC2_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC2_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC2_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC2_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC2_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC2_CHSTAT_n_EN (0x00000001uL)
+#define DMAC2_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC2_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC2_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC2_CHSTAT_n_ER (0x00000010uL)
+#define DMAC2_CHSTAT_n_END (0x00000020uL)
+#define DMAC2_CHSTAT_n_TC (0x00000040uL)
+#define DMAC2_CHSTAT_n_SR (0x00000080uL)
+#define DMAC2_CHSTAT_n_DL (0x00000100uL)
+#define DMAC2_CHSTAT_n_DW (0x00000200uL)
+#define DMAC2_CHSTAT_n_DER (0x00000400uL)
+#define DMAC2_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC2_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC2_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC2_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC2_CHCTRL_n_STG (0x00000004uL)
+#define DMAC2_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC2_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC2_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC2_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC2_CHCFG_n_SEL (0x00000007uL)
+#define DMAC2_CHCFG_n_REQD (0x00000008uL)
+#define DMAC2_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC2_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC2_CHCFG_n_LVL (0x00000040uL)
+#define DMAC2_CHCFG_n_AM (0x00000700uL)
+#define DMAC2_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC2_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC2_CHCFG_n_SAD (0x00100000uL)
+#define DMAC2_CHCFG_n_DAD (0x00200000uL)
+#define DMAC2_CHCFG_n_TM (0x00400000uL)
+#define DMAC2_CHCFG_n_DEM (0x01000000uL)
+#define DMAC2_CHCFG_n_TCM (0x02000000uL)
+#define DMAC2_CHCFG_n_SBE (0x08000000uL)
+#define DMAC2_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC2_CHCFG_n_RSW (0x20000000uL)
+#define DMAC2_CHCFG_n_REN (0x40000000uL)
+#define DMAC2_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC2_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC2_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC3_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC3_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC3_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC3_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC3_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC3_CHSTAT_n_EN (0x00000001uL)
+#define DMAC3_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC3_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC3_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC3_CHSTAT_n_ER (0x00000010uL)
+#define DMAC3_CHSTAT_n_END (0x00000020uL)
+#define DMAC3_CHSTAT_n_TC (0x00000040uL)
+#define DMAC3_CHSTAT_n_SR (0x00000080uL)
+#define DMAC3_CHSTAT_n_DL (0x00000100uL)
+#define DMAC3_CHSTAT_n_DW (0x00000200uL)
+#define DMAC3_CHSTAT_n_DER (0x00000400uL)
+#define DMAC3_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC3_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC3_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC3_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC3_CHCTRL_n_STG (0x00000004uL)
+#define DMAC3_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC3_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC3_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC3_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC3_CHCFG_n_SEL (0x00000007uL)
+#define DMAC3_CHCFG_n_REQD (0x00000008uL)
+#define DMAC3_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC3_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC3_CHCFG_n_LVL (0x00000040uL)
+#define DMAC3_CHCFG_n_AM (0x00000700uL)
+#define DMAC3_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC3_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC3_CHCFG_n_SAD (0x00100000uL)
+#define DMAC3_CHCFG_n_DAD (0x00200000uL)
+#define DMAC3_CHCFG_n_TM (0x00400000uL)
+#define DMAC3_CHCFG_n_DEM (0x01000000uL)
+#define DMAC3_CHCFG_n_TCM (0x02000000uL)
+#define DMAC3_CHCFG_n_SBE (0x08000000uL)
+#define DMAC3_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC3_CHCFG_n_RSW (0x20000000uL)
+#define DMAC3_CHCFG_n_REN (0x40000000uL)
+#define DMAC3_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC3_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC3_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC4_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC4_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC4_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC4_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC4_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC4_CHSTAT_n_EN (0x00000001uL)
+#define DMAC4_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC4_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC4_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC4_CHSTAT_n_ER (0x00000010uL)
+#define DMAC4_CHSTAT_n_END (0x00000020uL)
+#define DMAC4_CHSTAT_n_TC (0x00000040uL)
+#define DMAC4_CHSTAT_n_SR (0x00000080uL)
+#define DMAC4_CHSTAT_n_DL (0x00000100uL)
+#define DMAC4_CHSTAT_n_DW (0x00000200uL)
+#define DMAC4_CHSTAT_n_DER (0x00000400uL)
+#define DMAC4_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC4_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC4_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC4_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC4_CHCTRL_n_STG (0x00000004uL)
+#define DMAC4_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC4_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC4_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC4_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC4_CHCFG_n_SEL (0x00000007uL)
+#define DMAC4_CHCFG_n_REQD (0x00000008uL)
+#define DMAC4_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC4_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC4_CHCFG_n_LVL (0x00000040uL)
+#define DMAC4_CHCFG_n_AM (0x00000700uL)
+#define DMAC4_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC4_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC4_CHCFG_n_SAD (0x00100000uL)
+#define DMAC4_CHCFG_n_DAD (0x00200000uL)
+#define DMAC4_CHCFG_n_TM (0x00400000uL)
+#define DMAC4_CHCFG_n_DEM (0x01000000uL)
+#define DMAC4_CHCFG_n_TCM (0x02000000uL)
+#define DMAC4_CHCFG_n_SBE (0x08000000uL)
+#define DMAC4_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC4_CHCFG_n_RSW (0x20000000uL)
+#define DMAC4_CHCFG_n_REN (0x40000000uL)
+#define DMAC4_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC4_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC4_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC5_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC5_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC5_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC5_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC5_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC5_CHSTAT_n_EN (0x00000001uL)
+#define DMAC5_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC5_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC5_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC5_CHSTAT_n_ER (0x00000010uL)
+#define DMAC5_CHSTAT_n_END (0x00000020uL)
+#define DMAC5_CHSTAT_n_TC (0x00000040uL)
+#define DMAC5_CHSTAT_n_SR (0x00000080uL)
+#define DMAC5_CHSTAT_n_DL (0x00000100uL)
+#define DMAC5_CHSTAT_n_DW (0x00000200uL)
+#define DMAC5_CHSTAT_n_DER (0x00000400uL)
+#define DMAC5_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC5_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC5_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC5_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC5_CHCTRL_n_STG (0x00000004uL)
+#define DMAC5_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC5_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC5_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC5_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC5_CHCFG_n_SEL (0x00000007uL)
+#define DMAC5_CHCFG_n_REQD (0x00000008uL)
+#define DMAC5_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC5_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC5_CHCFG_n_LVL (0x00000040uL)
+#define DMAC5_CHCFG_n_AM (0x00000700uL)
+#define DMAC5_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC5_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC5_CHCFG_n_SAD (0x00100000uL)
+#define DMAC5_CHCFG_n_DAD (0x00200000uL)
+#define DMAC5_CHCFG_n_TM (0x00400000uL)
+#define DMAC5_CHCFG_n_DEM (0x01000000uL)
+#define DMAC5_CHCFG_n_TCM (0x02000000uL)
+#define DMAC5_CHCFG_n_SBE (0x08000000uL)
+#define DMAC5_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC5_CHCFG_n_RSW (0x20000000uL)
+#define DMAC5_CHCFG_n_REN (0x40000000uL)
+#define DMAC5_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC5_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC5_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC6_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC6_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC6_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC6_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC6_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC6_CHSTAT_n_EN (0x00000001uL)
+#define DMAC6_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC6_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC6_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC6_CHSTAT_n_ER (0x00000010uL)
+#define DMAC6_CHSTAT_n_END (0x00000020uL)
+#define DMAC6_CHSTAT_n_TC (0x00000040uL)
+#define DMAC6_CHSTAT_n_SR (0x00000080uL)
+#define DMAC6_CHSTAT_n_DL (0x00000100uL)
+#define DMAC6_CHSTAT_n_DW (0x00000200uL)
+#define DMAC6_CHSTAT_n_DER (0x00000400uL)
+#define DMAC6_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC6_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC6_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC6_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC6_CHCTRL_n_STG (0x00000004uL)
+#define DMAC6_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC6_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC6_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC6_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC6_CHCFG_n_SEL (0x00000007uL)
+#define DMAC6_CHCFG_n_REQD (0x00000008uL)
+#define DMAC6_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC6_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC6_CHCFG_n_LVL (0x00000040uL)
+#define DMAC6_CHCFG_n_AM (0x00000700uL)
+#define DMAC6_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC6_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC6_CHCFG_n_SAD (0x00100000uL)
+#define DMAC6_CHCFG_n_DAD (0x00200000uL)
+#define DMAC6_CHCFG_n_TM (0x00400000uL)
+#define DMAC6_CHCFG_n_DEM (0x01000000uL)
+#define DMAC6_CHCFG_n_TCM (0x02000000uL)
+#define DMAC6_CHCFG_n_SBE (0x08000000uL)
+#define DMAC6_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC6_CHCFG_n_RSW (0x20000000uL)
+#define DMAC6_CHCFG_n_REN (0x40000000uL)
+#define DMAC6_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC6_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC6_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC7_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC7_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC7_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC7_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC7_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC7_CHSTAT_n_EN (0x00000001uL)
+#define DMAC7_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC7_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC7_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC7_CHSTAT_n_ER (0x00000010uL)
+#define DMAC7_CHSTAT_n_END (0x00000020uL)
+#define DMAC7_CHSTAT_n_TC (0x00000040uL)
+#define DMAC7_CHSTAT_n_SR (0x00000080uL)
+#define DMAC7_CHSTAT_n_DL (0x00000100uL)
+#define DMAC7_CHSTAT_n_DW (0x00000200uL)
+#define DMAC7_CHSTAT_n_DER (0x00000400uL)
+#define DMAC7_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC7_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC7_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC7_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC7_CHCTRL_n_STG (0x00000004uL)
+#define DMAC7_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC7_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC7_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC7_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC7_CHCFG_n_SEL (0x00000007uL)
+#define DMAC7_CHCFG_n_REQD (0x00000008uL)
+#define DMAC7_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC7_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC7_CHCFG_n_LVL (0x00000040uL)
+#define DMAC7_CHCFG_n_AM (0x00000700uL)
+#define DMAC7_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC7_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC7_CHCFG_n_SAD (0x00100000uL)
+#define DMAC7_CHCFG_n_DAD (0x00200000uL)
+#define DMAC7_CHCFG_n_TM (0x00400000uL)
+#define DMAC7_CHCFG_n_DEM (0x01000000uL)
+#define DMAC7_CHCFG_n_TCM (0x02000000uL)
+#define DMAC7_CHCFG_n_SBE (0x08000000uL)
+#define DMAC7_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC7_CHCFG_n_RSW (0x20000000uL)
+#define DMAC7_CHCFG_n_REN (0x40000000uL)
+#define DMAC7_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC7_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC7_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR (0x00000001uL)
+#define DMAC07_DCTRL_0_7_LVINT (0x00000002uL)
+#define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL)
+#define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL)
+
+#define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL)
+#define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL)
+#define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL)
+#define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL)
+#define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL)
+#define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL)
+#define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL)
+#define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL)
+
+#define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL)
+#define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL)
+#define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL)
+#define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL)
+#define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL)
+#define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL)
+#define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL)
+#define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL)
+
+#define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL)
+#define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL)
+#define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL)
+#define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL)
+#define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL)
+#define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL)
+#define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL)
+#define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL)
+
+#define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL)
+#define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL)
+#define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL)
+#define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL)
+#define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL)
+#define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL)
+#define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL)
+#define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC8_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC8_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC8_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC8_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC8_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC8_CHSTAT_n_EN (0x00000001uL)
+#define DMAC8_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC8_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC8_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC8_CHSTAT_n_ER (0x00000010uL)
+#define DMAC8_CHSTAT_n_END (0x00000020uL)
+#define DMAC8_CHSTAT_n_TC (0x00000040uL)
+#define DMAC8_CHSTAT_n_SR (0x00000080uL)
+#define DMAC8_CHSTAT_n_DL (0x00000100uL)
+#define DMAC8_CHSTAT_n_DW (0x00000200uL)
+#define DMAC8_CHSTAT_n_DER (0x00000400uL)
+#define DMAC8_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC8_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC8_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC8_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC8_CHCTRL_n_STG (0x00000004uL)
+#define DMAC8_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC8_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC8_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC8_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC8_CHCFG_n_SEL (0x00000007uL)
+#define DMAC8_CHCFG_n_REQD (0x00000008uL)
+#define DMAC8_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC8_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC8_CHCFG_n_LVL (0x00000040uL)
+#define DMAC8_CHCFG_n_AM (0x00000700uL)
+#define DMAC8_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC8_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC8_CHCFG_n_SAD (0x00100000uL)
+#define DMAC8_CHCFG_n_DAD (0x00200000uL)
+#define DMAC8_CHCFG_n_TM (0x00400000uL)
+#define DMAC8_CHCFG_n_DEM (0x01000000uL)
+#define DMAC8_CHCFG_n_TCM (0x02000000uL)
+#define DMAC8_CHCFG_n_SBE (0x08000000uL)
+#define DMAC8_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC8_CHCFG_n_RSW (0x20000000uL)
+#define DMAC8_CHCFG_n_REN (0x40000000uL)
+#define DMAC8_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC8_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC8_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC9_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC9_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC9_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC9_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC9_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC9_CHSTAT_n_EN (0x00000001uL)
+#define DMAC9_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC9_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC9_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC9_CHSTAT_n_ER (0x00000010uL)
+#define DMAC9_CHSTAT_n_END (0x00000020uL)
+#define DMAC9_CHSTAT_n_TC (0x00000040uL)
+#define DMAC9_CHSTAT_n_SR (0x00000080uL)
+#define DMAC9_CHSTAT_n_DL (0x00000100uL)
+#define DMAC9_CHSTAT_n_DW (0x00000200uL)
+#define DMAC9_CHSTAT_n_DER (0x00000400uL)
+#define DMAC9_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC9_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC9_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC9_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC9_CHCTRL_n_STG (0x00000004uL)
+#define DMAC9_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC9_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC9_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC9_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC9_CHCFG_n_SEL (0x00000007uL)
+#define DMAC9_CHCFG_n_REQD (0x00000008uL)
+#define DMAC9_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC9_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC9_CHCFG_n_LVL (0x00000040uL)
+#define DMAC9_CHCFG_n_AM (0x00000700uL)
+#define DMAC9_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC9_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC9_CHCFG_n_SAD (0x00100000uL)
+#define DMAC9_CHCFG_n_DAD (0x00200000uL)
+#define DMAC9_CHCFG_n_TM (0x00400000uL)
+#define DMAC9_CHCFG_n_DEM (0x01000000uL)
+#define DMAC9_CHCFG_n_TCM (0x02000000uL)
+#define DMAC9_CHCFG_n_SBE (0x08000000uL)
+#define DMAC9_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC9_CHCFG_n_RSW (0x20000000uL)
+#define DMAC9_CHCFG_n_REN (0x40000000uL)
+#define DMAC9_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC9_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC9_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC10_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC10_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC10_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC10_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC10_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC10_CHSTAT_n_EN (0x00000001uL)
+#define DMAC10_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC10_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC10_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC10_CHSTAT_n_ER (0x00000010uL)
+#define DMAC10_CHSTAT_n_END (0x00000020uL)
+#define DMAC10_CHSTAT_n_TC (0x00000040uL)
+#define DMAC10_CHSTAT_n_SR (0x00000080uL)
+#define DMAC10_CHSTAT_n_DL (0x00000100uL)
+#define DMAC10_CHSTAT_n_DW (0x00000200uL)
+#define DMAC10_CHSTAT_n_DER (0x00000400uL)
+#define DMAC10_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC10_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC10_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC10_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC10_CHCTRL_n_STG (0x00000004uL)
+#define DMAC10_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC10_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC10_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC10_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC10_CHCFG_n_SEL (0x00000007uL)
+#define DMAC10_CHCFG_n_REQD (0x00000008uL)
+#define DMAC10_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC10_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC10_CHCFG_n_LVL (0x00000040uL)
+#define DMAC10_CHCFG_n_AM (0x00000700uL)
+#define DMAC10_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC10_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC10_CHCFG_n_SAD (0x00100000uL)
+#define DMAC10_CHCFG_n_DAD (0x00200000uL)
+#define DMAC10_CHCFG_n_TM (0x00400000uL)
+#define DMAC10_CHCFG_n_DEM (0x01000000uL)
+#define DMAC10_CHCFG_n_TCM (0x02000000uL)
+#define DMAC10_CHCFG_n_SBE (0x08000000uL)
+#define DMAC10_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC10_CHCFG_n_RSW (0x20000000uL)
+#define DMAC10_CHCFG_n_REN (0x40000000uL)
+#define DMAC10_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC10_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC10_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC11_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC11_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC11_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC11_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC11_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC11_CHSTAT_n_EN (0x00000001uL)
+#define DMAC11_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC11_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC11_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC11_CHSTAT_n_ER (0x00000010uL)
+#define DMAC11_CHSTAT_n_END (0x00000020uL)
+#define DMAC11_CHSTAT_n_TC (0x00000040uL)
+#define DMAC11_CHSTAT_n_SR (0x00000080uL)
+#define DMAC11_CHSTAT_n_DL (0x00000100uL)
+#define DMAC11_CHSTAT_n_DW (0x00000200uL)
+#define DMAC11_CHSTAT_n_DER (0x00000400uL)
+#define DMAC11_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC11_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC11_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC11_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC11_CHCTRL_n_STG (0x00000004uL)
+#define DMAC11_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC11_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC11_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC11_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC11_CHCFG_n_SEL (0x00000007uL)
+#define DMAC11_CHCFG_n_REQD (0x00000008uL)
+#define DMAC11_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC11_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC11_CHCFG_n_LVL (0x00000040uL)
+#define DMAC11_CHCFG_n_AM (0x00000700uL)
+#define DMAC11_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC11_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC11_CHCFG_n_SAD (0x00100000uL)
+#define DMAC11_CHCFG_n_DAD (0x00200000uL)
+#define DMAC11_CHCFG_n_TM (0x00400000uL)
+#define DMAC11_CHCFG_n_DEM (0x01000000uL)
+#define DMAC11_CHCFG_n_TCM (0x02000000uL)
+#define DMAC11_CHCFG_n_SBE (0x08000000uL)
+#define DMAC11_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC11_CHCFG_n_RSW (0x20000000uL)
+#define DMAC11_CHCFG_n_REN (0x40000000uL)
+#define DMAC11_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC11_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC11_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC12_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC12_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC12_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC12_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC12_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC12_CHSTAT_n_EN (0x00000001uL)
+#define DMAC12_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC12_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC12_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC12_CHSTAT_n_ER (0x00000010uL)
+#define DMAC12_CHSTAT_n_END (0x00000020uL)
+#define DMAC12_CHSTAT_n_TC (0x00000040uL)
+#define DMAC12_CHSTAT_n_SR (0x00000080uL)
+#define DMAC12_CHSTAT_n_DL (0x00000100uL)
+#define DMAC12_CHSTAT_n_DW (0x00000200uL)
+#define DMAC12_CHSTAT_n_DER (0x00000400uL)
+#define DMAC12_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC12_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC12_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC12_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC12_CHCTRL_n_STG (0x00000004uL)
+#define DMAC12_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC12_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC12_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC12_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC12_CHCFG_n_SEL (0x00000007uL)
+#define DMAC12_CHCFG_n_REQD (0x00000008uL)
+#define DMAC12_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC12_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC12_CHCFG_n_LVL (0x00000040uL)
+#define DMAC12_CHCFG_n_AM (0x00000700uL)
+#define DMAC12_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC12_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC12_CHCFG_n_SAD (0x00100000uL)
+#define DMAC12_CHCFG_n_DAD (0x00200000uL)
+#define DMAC12_CHCFG_n_TM (0x00400000uL)
+#define DMAC12_CHCFG_n_DEM (0x01000000uL)
+#define DMAC12_CHCFG_n_TCM (0x02000000uL)
+#define DMAC12_CHCFG_n_SBE (0x08000000uL)
+#define DMAC12_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC12_CHCFG_n_RSW (0x20000000uL)
+#define DMAC12_CHCFG_n_REN (0x40000000uL)
+#define DMAC12_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC12_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC12_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC13_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC13_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC13_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC13_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC13_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC13_CHSTAT_n_EN (0x00000001uL)
+#define DMAC13_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC13_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC13_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC13_CHSTAT_n_ER (0x00000010uL)
+#define DMAC13_CHSTAT_n_END (0x00000020uL)
+#define DMAC13_CHSTAT_n_TC (0x00000040uL)
+#define DMAC13_CHSTAT_n_SR (0x00000080uL)
+#define DMAC13_CHSTAT_n_DL (0x00000100uL)
+#define DMAC13_CHSTAT_n_DW (0x00000200uL)
+#define DMAC13_CHSTAT_n_DER (0x00000400uL)
+#define DMAC13_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC13_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC13_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC13_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC13_CHCTRL_n_STG (0x00000004uL)
+#define DMAC13_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC13_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC13_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC13_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC13_CHCFG_n_SEL (0x00000007uL)
+#define DMAC13_CHCFG_n_REQD (0x00000008uL)
+#define DMAC13_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC13_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC13_CHCFG_n_LVL (0x00000040uL)
+#define DMAC13_CHCFG_n_AM (0x00000700uL)
+#define DMAC13_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC13_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC13_CHCFG_n_SAD (0x00100000uL)
+#define DMAC13_CHCFG_n_DAD (0x00200000uL)
+#define DMAC13_CHCFG_n_TM (0x00400000uL)
+#define DMAC13_CHCFG_n_DEM (0x01000000uL)
+#define DMAC13_CHCFG_n_TCM (0x02000000uL)
+#define DMAC13_CHCFG_n_SBE (0x08000000uL)
+#define DMAC13_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC13_CHCFG_n_RSW (0x20000000uL)
+#define DMAC13_CHCFG_n_REN (0x40000000uL)
+#define DMAC13_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC13_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC13_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC14_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC14_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC14_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC14_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC14_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC14_CHSTAT_n_EN (0x00000001uL)
+#define DMAC14_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC14_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC14_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC14_CHSTAT_n_ER (0x00000010uL)
+#define DMAC14_CHSTAT_n_END (0x00000020uL)
+#define DMAC14_CHSTAT_n_TC (0x00000040uL)
+#define DMAC14_CHSTAT_n_SR (0x00000080uL)
+#define DMAC14_CHSTAT_n_DL (0x00000100uL)
+#define DMAC14_CHSTAT_n_DW (0x00000200uL)
+#define DMAC14_CHSTAT_n_DER (0x00000400uL)
+#define DMAC14_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC14_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC14_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC14_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC14_CHCTRL_n_STG (0x00000004uL)
+#define DMAC14_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC14_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC14_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC14_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC14_CHCFG_n_SEL (0x00000007uL)
+#define DMAC14_CHCFG_n_REQD (0x00000008uL)
+#define DMAC14_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC14_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC14_CHCFG_n_LVL (0x00000040uL)
+#define DMAC14_CHCFG_n_AM (0x00000700uL)
+#define DMAC14_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC14_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC14_CHCFG_n_SAD (0x00100000uL)
+#define DMAC14_CHCFG_n_DAD (0x00200000uL)
+#define DMAC14_CHCFG_n_TM (0x00400000uL)
+#define DMAC14_CHCFG_n_DEM (0x01000000uL)
+#define DMAC14_CHCFG_n_TCM (0x02000000uL)
+#define DMAC14_CHCFG_n_SBE (0x08000000uL)
+#define DMAC14_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC14_CHCFG_n_RSW (0x20000000uL)
+#define DMAC14_CHCFG_n_REN (0x40000000uL)
+#define DMAC14_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC14_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC14_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC15_N0DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC15_N0TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC15_N1SA_n_SA (0xFFFFFFFFuL)
+
+#define DMAC15_N1DA_n_DA (0xFFFFFFFFuL)
+
+#define DMAC15_N1TB_n_TB (0xFFFFFFFFuL)
+
+#define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL)
+
+#define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL)
+
+#define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL)
+
+#define DMAC15_CHSTAT_n_EN (0x00000001uL)
+#define DMAC15_CHSTAT_n_RQST (0x00000002uL)
+#define DMAC15_CHSTAT_n_TACT (0x00000004uL)
+#define DMAC15_CHSTAT_n_SUS (0x00000008uL)
+#define DMAC15_CHSTAT_n_ER (0x00000010uL)
+#define DMAC15_CHSTAT_n_END (0x00000020uL)
+#define DMAC15_CHSTAT_n_TC (0x00000040uL)
+#define DMAC15_CHSTAT_n_SR (0x00000080uL)
+#define DMAC15_CHSTAT_n_DL (0x00000100uL)
+#define DMAC15_CHSTAT_n_DW (0x00000200uL)
+#define DMAC15_CHSTAT_n_DER (0x00000400uL)
+#define DMAC15_CHSTAT_n_MODE (0x00000800uL)
+#define DMAC15_CHSTAT_n_INTMSK (0x00010000uL)
+
+#define DMAC15_CHCTRL_n_SETEN (0x00000001uL)
+#define DMAC15_CHCTRL_n_CLREN (0x00000002uL)
+#define DMAC15_CHCTRL_n_STG (0x00000004uL)
+#define DMAC15_CHCTRL_n_SWRST (0x00000008uL)
+#define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL)
+#define DMAC15_CHCTRL_n_CLREND (0x00000020uL)
+#define DMAC15_CHCTRL_n_CLRTC (0x00000040uL)
+#define DMAC15_CHCTRL_n_SETSUS (0x00000100uL)
+#define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL)
+#define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL)
+#define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL)
+
+#define DMAC15_CHCFG_n_SEL (0x00000007uL)
+#define DMAC15_CHCFG_n_REQD (0x00000008uL)
+#define DMAC15_CHCFG_n_LOEN (0x00000010uL)
+#define DMAC15_CHCFG_n_HIEN (0x00000020uL)
+#define DMAC15_CHCFG_n_LVL (0x00000040uL)
+#define DMAC15_CHCFG_n_AM (0x00000700uL)
+#define DMAC15_CHCFG_n_SDS (0x0000F000uL)
+#define DMAC15_CHCFG_n_DDS (0x000F0000uL)
+#define DMAC15_CHCFG_n_SAD (0x00100000uL)
+#define DMAC15_CHCFG_n_DAD (0x00200000uL)
+#define DMAC15_CHCFG_n_TM (0x00400000uL)
+#define DMAC15_CHCFG_n_DEM (0x01000000uL)
+#define DMAC15_CHCFG_n_TCM (0x02000000uL)
+#define DMAC15_CHCFG_n_SBE (0x08000000uL)
+#define DMAC15_CHCFG_n_RSEL (0x10000000uL)
+#define DMAC15_CHCFG_n_RSW (0x20000000uL)
+#define DMAC15_CHCFG_n_REN (0x40000000uL)
+#define DMAC15_CHCFG_n_DMS (0x80000000uL)
+
+#define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL)
+
+#define DMAC15_CHEXT_n_SCA (0x000000F0uL)
+#define DMAC15_CHEXT_n_DCA (0x0000F000uL)
+
+#define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL)
+
+#define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR (0x00000001uL)
+#define DMAC815_DCTRL_8_15_LVINT (0x00000002uL)
+#define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL)
+#define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL)
+
+#define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL)
+#define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL)
+#define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL)
+#define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL)
+#define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL)
+#define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL)
+#define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL)
+#define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL)
+
+#define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL)
+#define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL)
+#define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL)
+#define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL)
+#define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL)
+#define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL)
+#define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL)
+#define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL)
+
+#define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL)
+#define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL)
+#define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL)
+#define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL)
+#define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL)
+#define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL)
+#define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL)
+#define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL)
+
+#define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL)
+#define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL)
+#define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL)
+#define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL)
+#define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL)
+#define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL)
+#define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL)
+#define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID (0x00000003uL)
+#define DMAC01_DMARS_CH0_MID (0x000001FCuL)
+#define DMAC01_DMARS_CH1_RID (0x00030000uL)
+#define DMAC01_DMARS_CH1_MID (0x01FC0000uL)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID (0x00000003uL)
+#define DMAC23_DMARS_CH2_MID (0x000001FCuL)
+#define DMAC23_DMARS_CH3_RID (0x00030000uL)
+#define DMAC23_DMARS_CH3_MID (0x01FC0000uL)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID (0x00000003uL)
+#define DMAC45_DMARS_CH4_MID (0x000001FCuL)
+#define DMAC45_DMARS_CH5_RID (0x00030000uL)
+#define DMAC45_DMARS_CH5_MID (0x01FC0000uL)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID (0x00000003uL)
+#define DMAC67_DMARS_CH6_MID (0x000001FCuL)
+#define DMAC67_DMARS_CH7_RID (0x00030000uL)
+#define DMAC67_DMARS_CH7_MID (0x01FC0000uL)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID (0x00000003uL)
+#define DMAC89_DMARS_CH8_MID (0x000001FCuL)
+#define DMAC89_DMARS_CH9_RID (0x00030000uL)
+#define DMAC89_DMARS_CH9_MID (0x01FC0000uL)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID (0x00000003uL)
+#define DMAC1011_DMARS_CH10_MID (0x000001FCuL)
+#define DMAC1011_DMARS_CH11_RID (0x00030000uL)
+#define DMAC1011_DMARS_CH11_MID (0x01FC0000uL)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID (0x00000003uL)
+#define DMAC1213_DMARS_CH12_MID (0x000001FCuL)
+#define DMAC1213_DMARS_CH13_RID (0x00030000uL)
+#define DMAC1213_DMARS_CH13_MID (0x01FC0000uL)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID (0x00000003uL)
+#define DMAC1415_DMARS_CH14_MID (0x000001FCuL)
+#define DMAC1415_DMARS_CH15_RID (0x00030000uL)
+#define DMAC1415_DMARS_CH15_MID (0x01FC0000uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC0_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC0_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC0_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC0_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC0_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC0_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC0_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC0_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC0_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC0_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC0_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC0_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC0_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC0_CHSTAT_n_END_SHIFT (5u)
+#define DMAC0_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC0_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC0_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC0_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC0_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC0_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC0_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC0_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC0_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC0_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC0_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC0_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC0_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC0_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC0_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC0_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC0_CHCFG_n_AM_SHIFT (8u)
+#define DMAC0_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC0_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC0_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC0_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC0_CHCFG_n_TM_SHIFT (22u)
+#define DMAC0_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC0_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC0_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC0_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC0_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC0_CHCFG_n_REN_SHIFT (30u)
+#define DMAC0_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC0_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC0_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC0_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC0_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC0_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC1_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC1_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC1_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC1_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC1_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC1_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC1_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC1_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC1_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC1_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC1_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC1_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC1_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC1_CHSTAT_n_END_SHIFT (5u)
+#define DMAC1_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC1_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC1_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC1_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC1_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC1_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC1_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC1_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC1_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC1_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC1_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC1_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC1_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC1_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC1_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC1_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC1_CHCFG_n_AM_SHIFT (8u)
+#define DMAC1_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC1_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC1_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC1_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC1_CHCFG_n_TM_SHIFT (22u)
+#define DMAC1_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC1_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC1_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC1_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC1_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC1_CHCFG_n_REN_SHIFT (30u)
+#define DMAC1_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC1_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC1_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC1_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC1_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC1_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC2_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC2_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC2_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC2_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC2_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC2_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC2_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC2_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC2_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC2_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC2_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC2_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC2_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC2_CHSTAT_n_END_SHIFT (5u)
+#define DMAC2_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC2_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC2_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC2_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC2_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC2_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC2_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC2_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC2_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC2_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC2_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC2_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC2_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC2_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC2_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC2_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC2_CHCFG_n_AM_SHIFT (8u)
+#define DMAC2_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC2_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC2_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC2_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC2_CHCFG_n_TM_SHIFT (22u)
+#define DMAC2_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC2_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC2_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC2_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC2_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC2_CHCFG_n_REN_SHIFT (30u)
+#define DMAC2_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC2_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC2_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC2_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC2_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC2_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC3_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC3_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC3_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC3_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC3_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC3_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC3_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC3_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC3_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC3_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC3_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC3_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC3_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC3_CHSTAT_n_END_SHIFT (5u)
+#define DMAC3_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC3_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC3_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC3_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC3_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC3_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC3_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC3_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC3_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC3_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC3_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC3_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC3_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC3_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC3_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC3_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC3_CHCFG_n_AM_SHIFT (8u)
+#define DMAC3_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC3_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC3_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC3_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC3_CHCFG_n_TM_SHIFT (22u)
+#define DMAC3_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC3_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC3_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC3_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC3_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC3_CHCFG_n_REN_SHIFT (30u)
+#define DMAC3_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC3_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC3_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC3_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC3_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC3_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC4_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC4_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC4_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC4_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC4_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC4_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC4_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC4_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC4_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC4_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC4_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC4_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC4_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC4_CHSTAT_n_END_SHIFT (5u)
+#define DMAC4_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC4_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC4_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC4_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC4_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC4_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC4_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC4_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC4_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC4_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC4_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC4_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC4_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC4_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC4_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC4_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC4_CHCFG_n_AM_SHIFT (8u)
+#define DMAC4_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC4_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC4_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC4_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC4_CHCFG_n_TM_SHIFT (22u)
+#define DMAC4_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC4_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC4_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC4_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC4_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC4_CHCFG_n_REN_SHIFT (30u)
+#define DMAC4_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC4_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC4_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC4_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC4_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC4_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC5_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC5_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC5_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC5_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC5_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC5_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC5_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC5_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC5_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC5_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC5_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC5_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC5_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC5_CHSTAT_n_END_SHIFT (5u)
+#define DMAC5_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC5_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC5_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC5_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC5_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC5_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC5_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC5_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC5_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC5_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC5_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC5_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC5_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC5_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC5_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC5_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC5_CHCFG_n_AM_SHIFT (8u)
+#define DMAC5_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC5_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC5_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC5_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC5_CHCFG_n_TM_SHIFT (22u)
+#define DMAC5_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC5_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC5_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC5_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC5_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC5_CHCFG_n_REN_SHIFT (30u)
+#define DMAC5_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC5_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC5_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC5_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC5_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC5_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC6_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC6_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC6_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC6_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC6_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC6_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC6_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC6_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC6_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC6_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC6_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC6_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC6_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC6_CHSTAT_n_END_SHIFT (5u)
+#define DMAC6_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC6_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC6_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC6_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC6_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC6_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC6_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC6_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC6_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC6_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC6_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC6_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC6_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC6_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC6_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC6_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC6_CHCFG_n_AM_SHIFT (8u)
+#define DMAC6_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC6_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC6_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC6_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC6_CHCFG_n_TM_SHIFT (22u)
+#define DMAC6_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC6_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC6_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC6_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC6_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC6_CHCFG_n_REN_SHIFT (30u)
+#define DMAC6_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC6_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC6_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC6_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC6_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC6_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC7_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC7_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC7_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC7_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC7_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC7_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC7_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC7_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC7_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC7_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC7_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC7_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC7_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC7_CHSTAT_n_END_SHIFT (5u)
+#define DMAC7_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC7_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC7_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC7_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC7_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC7_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC7_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC7_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC7_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC7_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC7_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC7_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC7_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC7_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC7_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC7_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC7_CHCFG_n_AM_SHIFT (8u)
+#define DMAC7_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC7_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC7_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC7_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC7_CHCFG_n_TM_SHIFT (22u)
+#define DMAC7_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC7_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC7_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC7_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC7_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC7_CHCFG_n_REN_SHIFT (30u)
+#define DMAC7_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC7_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC7_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC7_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC7_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC7_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR_SHIFT (0u)
+#define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u)
+#define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u)
+#define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u)
+
+#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u)
+#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u)
+#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u)
+#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u)
+#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u)
+#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u)
+#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u)
+#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u)
+
+#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u)
+#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u)
+#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u)
+#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u)
+#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u)
+#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u)
+#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u)
+#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u)
+
+#define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u)
+#define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u)
+#define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u)
+#define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u)
+#define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u)
+#define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u)
+#define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u)
+#define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u)
+
+#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u)
+#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u)
+#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u)
+#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u)
+#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u)
+#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u)
+#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u)
+#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u)
+#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u)
+#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u)
+#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u)
+#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u)
+#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u)
+#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u)
+#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC8_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC8_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC8_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC8_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC8_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC8_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC8_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC8_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC8_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC8_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC8_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC8_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC8_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC8_CHSTAT_n_END_SHIFT (5u)
+#define DMAC8_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC8_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC8_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC8_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC8_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC8_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC8_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC8_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC8_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC8_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC8_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC8_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC8_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC8_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC8_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC8_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC8_CHCFG_n_AM_SHIFT (8u)
+#define DMAC8_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC8_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC8_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC8_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC8_CHCFG_n_TM_SHIFT (22u)
+#define DMAC8_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC8_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC8_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC8_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC8_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC8_CHCFG_n_REN_SHIFT (30u)
+#define DMAC8_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC8_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC8_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC8_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC8_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC8_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC9_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC9_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC9_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC9_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC9_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC9_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC9_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC9_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC9_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC9_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC9_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC9_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC9_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC9_CHSTAT_n_END_SHIFT (5u)
+#define DMAC9_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC9_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC9_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC9_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC9_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC9_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC9_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC9_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC9_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC9_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC9_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC9_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC9_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC9_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC9_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC9_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC9_CHCFG_n_AM_SHIFT (8u)
+#define DMAC9_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC9_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC9_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC9_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC9_CHCFG_n_TM_SHIFT (22u)
+#define DMAC9_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC9_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC9_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC9_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC9_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC9_CHCFG_n_REN_SHIFT (30u)
+#define DMAC9_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC9_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC9_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC9_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC9_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC9_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC10_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC10_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC10_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC10_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC10_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC10_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC10_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC10_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC10_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC10_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC10_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC10_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC10_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC10_CHSTAT_n_END_SHIFT (5u)
+#define DMAC10_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC10_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC10_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC10_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC10_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC10_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC10_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC10_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC10_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC10_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC10_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC10_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC10_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC10_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC10_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC10_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC10_CHCFG_n_AM_SHIFT (8u)
+#define DMAC10_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC10_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC10_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC10_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC10_CHCFG_n_TM_SHIFT (22u)
+#define DMAC10_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC10_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC10_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC10_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC10_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC10_CHCFG_n_REN_SHIFT (30u)
+#define DMAC10_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC10_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC10_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC10_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC10_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC10_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC11_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC11_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC11_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC11_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC11_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC11_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC11_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC11_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC11_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC11_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC11_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC11_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC11_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC11_CHSTAT_n_END_SHIFT (5u)
+#define DMAC11_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC11_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC11_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC11_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC11_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC11_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC11_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC11_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC11_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC11_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC11_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC11_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC11_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC11_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC11_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC11_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC11_CHCFG_n_AM_SHIFT (8u)
+#define DMAC11_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC11_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC11_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC11_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC11_CHCFG_n_TM_SHIFT (22u)
+#define DMAC11_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC11_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC11_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC11_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC11_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC11_CHCFG_n_REN_SHIFT (30u)
+#define DMAC11_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC11_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC11_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC11_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC11_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC11_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC12_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC12_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC12_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC12_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC12_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC12_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC12_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC12_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC12_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC12_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC12_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC12_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC12_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC12_CHSTAT_n_END_SHIFT (5u)
+#define DMAC12_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC12_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC12_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC12_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC12_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC12_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC12_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC12_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC12_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC12_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC12_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC12_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC12_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC12_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC12_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC12_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC12_CHCFG_n_AM_SHIFT (8u)
+#define DMAC12_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC12_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC12_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC12_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC12_CHCFG_n_TM_SHIFT (22u)
+#define DMAC12_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC12_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC12_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC12_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC12_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC12_CHCFG_n_REN_SHIFT (30u)
+#define DMAC12_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC12_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC12_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC12_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC12_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC12_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC13_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC13_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC13_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC13_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC13_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC13_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC13_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC13_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC13_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC13_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC13_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC13_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC13_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC13_CHSTAT_n_END_SHIFT (5u)
+#define DMAC13_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC13_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC13_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC13_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC13_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC13_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC13_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC13_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC13_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC13_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC13_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC13_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC13_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC13_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC13_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC13_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC13_CHCFG_n_AM_SHIFT (8u)
+#define DMAC13_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC13_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC13_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC13_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC13_CHCFG_n_TM_SHIFT (22u)
+#define DMAC13_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC13_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC13_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC13_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC13_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC13_CHCFG_n_REN_SHIFT (30u)
+#define DMAC13_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC13_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC13_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC13_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC13_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC13_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC14_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC14_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC14_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC14_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC14_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC14_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC14_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC14_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC14_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC14_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC14_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC14_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC14_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC14_CHSTAT_n_END_SHIFT (5u)
+#define DMAC14_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC14_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC14_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC14_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC14_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC14_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC14_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC14_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC14_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC14_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC14_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC14_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC14_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC14_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC14_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC14_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC14_CHCFG_n_AM_SHIFT (8u)
+#define DMAC14_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC14_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC14_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC14_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC14_CHCFG_n_TM_SHIFT (22u)
+#define DMAC14_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC14_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC14_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC14_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC14_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC14_CHCFG_n_REN_SHIFT (30u)
+#define DMAC14_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC14_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC14_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC14_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC14_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC14_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA_SHIFT (0u)
+
+#define DMAC15_N0DA_n_DA_SHIFT (0u)
+
+#define DMAC15_N0TB_n_TB_SHIFT (0u)
+
+#define DMAC15_N1SA_n_SA_SHIFT (0u)
+
+#define DMAC15_N1DA_n_DA_SHIFT (0u)
+
+#define DMAC15_N1TB_n_TB_SHIFT (0u)
+
+#define DMAC15_CRSA_n_CRSA_SHIFT (0u)
+
+#define DMAC15_CRDA_n_CRDA_SHIFT (0u)
+
+#define DMAC15_CRTB_n_CRTB_SHIFT (0u)
+
+#define DMAC15_CHSTAT_n_EN_SHIFT (0u)
+#define DMAC15_CHSTAT_n_RQST_SHIFT (1u)
+#define DMAC15_CHSTAT_n_TACT_SHIFT (2u)
+#define DMAC15_CHSTAT_n_SUS_SHIFT (3u)
+#define DMAC15_CHSTAT_n_ER_SHIFT (4u)
+#define DMAC15_CHSTAT_n_END_SHIFT (5u)
+#define DMAC15_CHSTAT_n_TC_SHIFT (6u)
+#define DMAC15_CHSTAT_n_SR_SHIFT (7u)
+#define DMAC15_CHSTAT_n_DL_SHIFT (8u)
+#define DMAC15_CHSTAT_n_DW_SHIFT (9u)
+#define DMAC15_CHSTAT_n_DER_SHIFT (10u)
+#define DMAC15_CHSTAT_n_MODE_SHIFT (11u)
+#define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u)
+
+#define DMAC15_CHCTRL_n_SETEN_SHIFT (0u)
+#define DMAC15_CHCTRL_n_CLREN_SHIFT (1u)
+#define DMAC15_CHCTRL_n_STG_SHIFT (2u)
+#define DMAC15_CHCTRL_n_SWRST_SHIFT (3u)
+#define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u)
+#define DMAC15_CHCTRL_n_CLREND_SHIFT (5u)
+#define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u)
+#define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u)
+#define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u)
+#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u)
+#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u)
+
+#define DMAC15_CHCFG_n_SEL_SHIFT (0u)
+#define DMAC15_CHCFG_n_REQD_SHIFT (3u)
+#define DMAC15_CHCFG_n_LOEN_SHIFT (4u)
+#define DMAC15_CHCFG_n_HIEN_SHIFT (5u)
+#define DMAC15_CHCFG_n_LVL_SHIFT (6u)
+#define DMAC15_CHCFG_n_AM_SHIFT (8u)
+#define DMAC15_CHCFG_n_SDS_SHIFT (12u)
+#define DMAC15_CHCFG_n_DDS_SHIFT (16u)
+#define DMAC15_CHCFG_n_SAD_SHIFT (20u)
+#define DMAC15_CHCFG_n_DAD_SHIFT (21u)
+#define DMAC15_CHCFG_n_TM_SHIFT (22u)
+#define DMAC15_CHCFG_n_DEM_SHIFT (24u)
+#define DMAC15_CHCFG_n_TCM_SHIFT (25u)
+#define DMAC15_CHCFG_n_SBE_SHIFT (27u)
+#define DMAC15_CHCFG_n_RSEL_SHIFT (28u)
+#define DMAC15_CHCFG_n_RSW_SHIFT (29u)
+#define DMAC15_CHCFG_n_REN_SHIFT (30u)
+#define DMAC15_CHCFG_n_DMS_SHIFT (31u)
+
+#define DMAC15_CHITVL_n_ITVL_SHIFT (0u)
+
+#define DMAC15_CHEXT_n_SCA_SHIFT (4u)
+#define DMAC15_CHEXT_n_DCA_SHIFT (12u)
+
+#define DMAC15_NXLA_n_NXLA_SHIFT (0u)
+
+#define DMAC15_CRLA_n_CRLA_SHIFT (0u)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR_SHIFT (0u)
+#define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u)
+#define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u)
+#define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u)
+
+#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u)
+#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u)
+#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u)
+#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u)
+#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u)
+#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u)
+#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u)
+#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u)
+
+#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u)
+#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u)
+#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u)
+#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u)
+#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u)
+#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u)
+#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u)
+#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u)
+
+#define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u)
+#define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u)
+#define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u)
+#define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u)
+#define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u)
+#define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u)
+#define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u)
+#define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u)
+
+#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u)
+#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u)
+#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u)
+#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u)
+#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u)
+#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u)
+#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u)
+#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u)
+#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u)
+#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u)
+#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u)
+#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u)
+#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u)
+#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u)
+#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID_SHIFT (0u)
+#define DMAC01_DMARS_CH0_MID_SHIFT (2u)
+#define DMAC01_DMARS_CH1_RID_SHIFT (16u)
+#define DMAC01_DMARS_CH1_MID_SHIFT (18u)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID_SHIFT (0u)
+#define DMAC23_DMARS_CH2_MID_SHIFT (2u)
+#define DMAC23_DMARS_CH3_RID_SHIFT (16u)
+#define DMAC23_DMARS_CH3_MID_SHIFT (18u)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID_SHIFT (0u)
+#define DMAC45_DMARS_CH4_MID_SHIFT (2u)
+#define DMAC45_DMARS_CH5_RID_SHIFT (16u)
+#define DMAC45_DMARS_CH5_MID_SHIFT (18u)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID_SHIFT (0u)
+#define DMAC67_DMARS_CH6_MID_SHIFT (2u)
+#define DMAC67_DMARS_CH7_RID_SHIFT (16u)
+#define DMAC67_DMARS_CH7_MID_SHIFT (18u)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID_SHIFT (0u)
+#define DMAC89_DMARS_CH8_MID_SHIFT (2u)
+#define DMAC89_DMARS_CH9_RID_SHIFT (16u)
+#define DMAC89_DMARS_CH9_MID_SHIFT (18u)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID_SHIFT (0u)
+#define DMAC1011_DMARS_CH10_MID_SHIFT (2u)
+#define DMAC1011_DMARS_CH11_RID_SHIFT (16u)
+#define DMAC1011_DMARS_CH11_MID_SHIFT (18u)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID_SHIFT (0u)
+#define DMAC1213_DMARS_CH12_MID_SHIFT (2u)
+#define DMAC1213_DMARS_CH13_RID_SHIFT (16u)
+#define DMAC1213_DMARS_CH13_MID_SHIFT (18u)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID_SHIFT (0u)
+#define DMAC1415_DMARS_CH14_MID_SHIFT (2u)
+#define DMAC1415_DMARS_CH15_RID_SHIFT (16u)
+#define DMAC1415_DMARS_CH15_MID_SHIFT (18u)
+
+
+#endif /* DMAC_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h
new file mode 100644
index 000000000..94ba61954
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h
@@ -0,0 +1,5793 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : gpio_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : General purpose I/O ports register define header
+*******************************************************************************/
+#ifndef GPIO_IOBITMASK_H
+#define GPIO_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00 (0x0001u)
+#define GPIO_PPR0_PPR01 (0x0002u)
+#define GPIO_PPR0_PPR02 (0x0004u)
+#define GPIO_PPR0_PPR03 (0x0008u)
+#define GPIO_PPR0_PPR04 (0x0010u)
+#define GPIO_PPR0_PPR05 (0x0020u)
+
+#define GPIO_PMC0_PMC04 (0x0010u)
+#define GPIO_PMC0_PMC05 (0x0020u)
+
+#define GPIO_PMCSR0_PMCSR04 (0x00000010uL)
+#define GPIO_PMCSR0_PMCSR05 (0x00000020uL)
+
+#define GPIO_PIBC0_PIBC00 (0x0001u)
+#define GPIO_PIBC0_PIBC01 (0x0002u)
+#define GPIO_PIBC0_PIBC02 (0x0004u)
+#define GPIO_PIBC0_PIBC03 (0x0008u)
+#define GPIO_PIBC0_PIBC04 (0x0010u)
+#define GPIO_PIBC0_PIBC05 (0x0020u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10 (0x0001u)
+#define GPIO_P1_P11 (0x0002u)
+#define GPIO_P1_P12 (0x0004u)
+#define GPIO_P1_P13 (0x0008u)
+#define GPIO_P1_P14 (0x0010u)
+#define GPIO_P1_P15 (0x0020u)
+#define GPIO_P1_P16 (0x0040u)
+#define GPIO_P1_P17 (0x0080u)
+
+#define GPIO_PSR1_PSR10 (0x00000001uL)
+#define GPIO_PSR1_PSR11 (0x00000002uL)
+#define GPIO_PSR1_PSR12 (0x00000004uL)
+#define GPIO_PSR1_PSR13 (0x00000008uL)
+#define GPIO_PSR1_PSR14 (0x00000010uL)
+#define GPIO_PSR1_PSR15 (0x00000020uL)
+#define GPIO_PSR1_PSR16 (0x00000040uL)
+#define GPIO_PSR1_PSR17 (0x00000080uL)
+#define GPIO_PSR1_PSR116 (0x00010000uL)
+#define GPIO_PSR1_PSR117 (0x00020000uL)
+#define GPIO_PSR1_PSR118 (0x00040000uL)
+#define GPIO_PSR1_PSR119 (0x00080000uL)
+#define GPIO_PSR1_PSR120 (0x00100000uL)
+#define GPIO_PSR1_PSR121 (0x00200000uL)
+#define GPIO_PSR1_PSR122 (0x00400000uL)
+#define GPIO_PSR1_PSR123 (0x00800000uL)
+
+#define GPIO_PPR1_PPR10 (0x0001u)
+#define GPIO_PPR1_PPR11 (0x0002u)
+#define GPIO_PPR1_PPR12 (0x0004u)
+#define GPIO_PPR1_PPR13 (0x0008u)
+#define GPIO_PPR1_PPR14 (0x0010u)
+#define GPIO_PPR1_PPR15 (0x0020u)
+#define GPIO_PPR1_PPR16 (0x0040u)
+#define GPIO_PPR1_PPR17 (0x0080u)
+#define GPIO_PPR1_PPR18 (0x0100u)
+#define GPIO_PPR1_PPR19 (0x0200u)
+#define GPIO_PPR1_PPR110 (0x0400u)
+#define GPIO_PPR1_PPR111 (0x0800u)
+#define GPIO_PPR1_PPR112 (0x1000u)
+#define GPIO_PPR1_PPR113 (0x2000u)
+#define GPIO_PPR1_PPR114 (0x4000u)
+#define GPIO_PPR1_PPR115 (0x8000u)
+
+#define GPIO_PM1_PM10 (0x0001u)
+#define GPIO_PM1_PM11 (0x0002u)
+#define GPIO_PM1_PM12 (0x0004u)
+#define GPIO_PM1_PM13 (0x0008u)
+#define GPIO_PM1_PM14 (0x0010u)
+#define GPIO_PM1_PM15 (0x0020u)
+#define GPIO_PM1_PM16 (0x0040u)
+#define GPIO_PM1_PM17 (0x0080u)
+
+#define GPIO_PMC1_PMC10 (0x0001u)
+#define GPIO_PMC1_PMC11 (0x0002u)
+#define GPIO_PMC1_PMC12 (0x0004u)
+#define GPIO_PMC1_PMC13 (0x0008u)
+#define GPIO_PMC1_PMC14 (0x0010u)
+#define GPIO_PMC1_PMC15 (0x0020u)
+#define GPIO_PMC1_PMC16 (0x0040u)
+#define GPIO_PMC1_PMC17 (0x0080u)
+#define GPIO_PMC1_PMC18 (0x0100u)
+#define GPIO_PMC1_PMC19 (0x0200u)
+#define GPIO_PMC1_PMC110 (0x0400u)
+#define GPIO_PMC1_PMC111 (0x0800u)
+#define GPIO_PMC1_PMC112 (0x1000u)
+#define GPIO_PMC1_PMC113 (0x2000u)
+#define GPIO_PMC1_PMC114 (0x4000u)
+#define GPIO_PMC1_PMC115 (0x8000u)
+
+#define GPIO_PFC1_PFC10 (0x0001u)
+#define GPIO_PFC1_PFC11 (0x0002u)
+#define GPIO_PFC1_PFC12 (0x0004u)
+#define GPIO_PFC1_PFC13 (0x0008u)
+#define GPIO_PFC1_PFC14 (0x0010u)
+#define GPIO_PFC1_PFC15 (0x0020u)
+#define GPIO_PFC1_PFC16 (0x0040u)
+#define GPIO_PFC1_PFC17 (0x0080u)
+#define GPIO_PFC1_PFC18 (0x0100u)
+#define GPIO_PFC1_PFC19 (0x0200u)
+#define GPIO_PFC1_PFC110 (0x0400u)
+#define GPIO_PFC1_PFC111 (0x0800u)
+#define GPIO_PFC1_PFC112 (0x1000u)
+#define GPIO_PFC1_PFC113 (0x2000u)
+#define GPIO_PFC1_PFC114 (0x4000u)
+#define GPIO_PFC1_PFC115 (0x8000u)
+
+#define GPIO_PFCE1_PFCE10 (0x0001u)
+#define GPIO_PFCE1_PFCE11 (0x0002u)
+#define GPIO_PFCE1_PFCE12 (0x0004u)
+#define GPIO_PFCE1_PFCE13 (0x0008u)
+#define GPIO_PFCE1_PFCE14 (0x0010u)
+#define GPIO_PFCE1_PFCE15 (0x0020u)
+#define GPIO_PFCE1_PFCE16 (0x0040u)
+#define GPIO_PFCE1_PFCE17 (0x0080u)
+#define GPIO_PFCE1_PFCE18 (0x0100u)
+#define GPIO_PFCE1_PFCE19 (0x0200u)
+#define GPIO_PFCE1_PFCE110 (0x0400u)
+#define GPIO_PFCE1_PFCE111 (0x0800u)
+#define GPIO_PFCE1_PFCE112 (0x1000u)
+#define GPIO_PFCE1_PFCE113 (0x2000u)
+#define GPIO_PFCE1_PFCE114 (0x4000u)
+#define GPIO_PFCE1_PFCE115 (0x8000u)
+
+#define GPIO_PNOT1_PNOT10 (0x0001u)
+#define GPIO_PNOT1_PNOT11 (0x0002u)
+#define GPIO_PNOT1_PNOT12 (0x0004u)
+#define GPIO_PNOT1_PNOT13 (0x0008u)
+#define GPIO_PNOT1_PNOT14 (0x0010u)
+#define GPIO_PNOT1_PNOT15 (0x0020u)
+#define GPIO_PNOT1_PNOT16 (0x0040u)
+#define GPIO_PNOT1_PNOT17 (0x0080u)
+
+#define GPIO_PMSR1_PMSR10 (0x00000001uL)
+#define GPIO_PMSR1_PMSR11 (0x00000002uL)
+#define GPIO_PMSR1_PMSR12 (0x00000004uL)
+#define GPIO_PMSR1_PMSR13 (0x00000008uL)
+#define GPIO_PMSR1_PMSR14 (0x00000010uL)
+#define GPIO_PMSR1_PMSR15 (0x00000020uL)
+#define GPIO_PMSR1_PMSR16 (0x00000040uL)
+#define GPIO_PMSR1_PMSR17 (0x00000080uL)
+#define GPIO_PMSR1_PMSR116 (0x00010000uL)
+#define GPIO_PMSR1_PMSR117 (0x00020000uL)
+#define GPIO_PMSR1_PMSR118 (0x00040000uL)
+#define GPIO_PMSR1_PMSR119 (0x00080000uL)
+#define GPIO_PMSR1_PMSR120 (0x00100000uL)
+#define GPIO_PMSR1_PMSR121 (0x00200000uL)
+#define GPIO_PMSR1_PMSR122 (0x00400000uL)
+#define GPIO_PMSR1_PMSR123 (0x00800000uL)
+
+#define GPIO_PMCSR1_PMCSR10 (0x00000001uL)
+#define GPIO_PMCSR1_PMCSR11 (0x00000002uL)
+#define GPIO_PMCSR1_PMCSR12 (0x00000004uL)
+#define GPIO_PMCSR1_PMCSR13 (0x00000008uL)
+#define GPIO_PMCSR1_PMCSR14 (0x00000010uL)
+#define GPIO_PMCSR1_PMCSR15 (0x00000020uL)
+#define GPIO_PMCSR1_PMCSR16 (0x00000040uL)
+#define GPIO_PMCSR1_PMCSR17 (0x00000080uL)
+#define GPIO_PMCSR1_PMCSR116 (0x00010000uL)
+#define GPIO_PMCSR1_PMCSR117 (0x00020000uL)
+#define GPIO_PMCSR1_PMCSR118 (0x00040000uL)
+#define GPIO_PMCSR1_PMCSR119 (0x00080000uL)
+#define GPIO_PMCSR1_PMCSR120 (0x00100000uL)
+#define GPIO_PMCSR1_PMCSR121 (0x00200000uL)
+#define GPIO_PMCSR1_PMCSR122 (0x00400000uL)
+#define GPIO_PMCSR1_PMCSR123 (0x00800000uL)
+
+#define GPIO_PFCAE1_PFCAE10 (0x0001u)
+#define GPIO_PFCAE1_PFCAE11 (0x0002u)
+#define GPIO_PFCAE1_PFCAE12 (0x0004u)
+#define GPIO_PFCAE1_PFCAE13 (0x0008u)
+#define GPIO_PFCAE1_PFCAE14 (0x0010u)
+#define GPIO_PFCAE1_PFCAE15 (0x0020u)
+#define GPIO_PFCAE1_PFCAE16 (0x0040u)
+#define GPIO_PFCAE1_PFCAE17 (0x0080u)
+#define GPIO_PFCAE1_PFCAE18 (0x0100u)
+#define GPIO_PFCAE1_PFCAE19 (0x0200u)
+#define GPIO_PFCAE1_PFCAE110 (0x0400u)
+#define GPIO_PFCAE1_PFCAE111 (0x0800u)
+#define GPIO_PFCAE1_PFCAE112 (0x1000u)
+#define GPIO_PFCAE1_PFCAE113 (0x2000u)
+#define GPIO_PFCAE1_PFCAE114 (0x4000u)
+#define GPIO_PFCAE1_PFCAE115 (0x8000u)
+
+#define GPIO_PIBC1_PIBC10 (0x0001u)
+#define GPIO_PIBC1_PIBC11 (0x0002u)
+#define GPIO_PIBC1_PIBC12 (0x0004u)
+#define GPIO_PIBC1_PIBC13 (0x0008u)
+#define GPIO_PIBC1_PIBC14 (0x0010u)
+#define GPIO_PIBC1_PIBC15 (0x0020u)
+#define GPIO_PIBC1_PIBC16 (0x0040u)
+#define GPIO_PIBC1_PIBC17 (0x0080u)
+#define GPIO_PIBC1_PIBC18 (0x0100u)
+#define GPIO_PIBC1_PIBC19 (0x0200u)
+#define GPIO_PIBC1_PIBC110 (0x0400u)
+#define GPIO_PIBC1_PIBC111 (0x0800u)
+#define GPIO_PIBC1_PIBC112 (0x1000u)
+#define GPIO_PIBC1_PIBC113 (0x2000u)
+#define GPIO_PIBC1_PIBC114 (0x4000u)
+#define GPIO_PIBC1_PIBC115 (0x8000u)
+
+#define GPIO_PBDC1_PBDC10 (0x0001u)
+#define GPIO_PBDC1_PBDC11 (0x0002u)
+#define GPIO_PBDC1_PBDC12 (0x0004u)
+#define GPIO_PBDC1_PBDC13 (0x0008u)
+#define GPIO_PBDC1_PBDC14 (0x0010u)
+#define GPIO_PBDC1_PBDC15 (0x0020u)
+#define GPIO_PBDC1_PBDC16 (0x0040u)
+#define GPIO_PBDC1_PBDC17 (0x0080u)
+#define GPIO_PBDC1_PBDC18 (0x0100u)
+#define GPIO_PBDC1_PBDC19 (0x0200u)
+#define GPIO_PBDC1_PBDC110 (0x0400u)
+#define GPIO_PBDC1_PBDC111 (0x0800u)
+#define GPIO_PBDC1_PBDC112 (0x1000u)
+#define GPIO_PBDC1_PBDC113 (0x2000u)
+#define GPIO_PBDC1_PBDC114 (0x4000u)
+#define GPIO_PBDC1_PBDC115 (0x8000u)
+
+#define GPIO_PIPC1_PIPC10 (0x0001u)
+#define GPIO_PIPC1_PIPC11 (0x0002u)
+#define GPIO_PIPC1_PIPC12 (0x0004u)
+#define GPIO_PIPC1_PIPC13 (0x0008u)
+#define GPIO_PIPC1_PIPC14 (0x0010u)
+#define GPIO_PIPC1_PIPC15 (0x0020u)
+#define GPIO_PIPC1_PIPC16 (0x0040u)
+#define GPIO_PIPC1_PIPC17 (0x0080u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20 (0x0001u)
+#define GPIO_P2_P21 (0x0002u)
+#define GPIO_P2_P22 (0x0004u)
+#define GPIO_P2_P23 (0x0008u)
+#define GPIO_P2_P24 (0x0010u)
+#define GPIO_P2_P25 (0x0020u)
+#define GPIO_P2_P26 (0x0040u)
+#define GPIO_P2_P27 (0x0080u)
+#define GPIO_P2_P28 (0x0100u)
+#define GPIO_P2_P29 (0x0200u)
+#define GPIO_P2_P210 (0x0400u)
+#define GPIO_P2_P211 (0x0800u)
+#define GPIO_P2_P212 (0x1000u)
+#define GPIO_P2_P213 (0x2000u)
+#define GPIO_P2_P214 (0x4000u)
+#define GPIO_P2_P215 (0x8000u)
+
+#define GPIO_PSR2_PSR20 (0x00000001uL)
+#define GPIO_PSR2_PSR21 (0x00000002uL)
+#define GPIO_PSR2_PSR22 (0x00000004uL)
+#define GPIO_PSR2_PSR23 (0x00000008uL)
+#define GPIO_PSR2_PSR24 (0x00000010uL)
+#define GPIO_PSR2_PSR25 (0x00000020uL)
+#define GPIO_PSR2_PSR26 (0x00000040uL)
+#define GPIO_PSR2_PSR27 (0x00000080uL)
+#define GPIO_PSR2_PSR28 (0x00000100uL)
+#define GPIO_PSR2_PSR29 (0x00000200uL)
+#define GPIO_PSR2_PSR210 (0x00000400uL)
+#define GPIO_PSR2_PSR211 (0x00000800uL)
+#define GPIO_PSR2_PSR212 (0x00001000uL)
+#define GPIO_PSR2_PSR213 (0x00002000uL)
+#define GPIO_PSR2_PSR214 (0x00004000uL)
+#define GPIO_PSR2_PSR215 (0x00008000uL)
+#define GPIO_PSR2_PSR216 (0x00010000uL)
+#define GPIO_PSR2_PSR217 (0x00020000uL)
+#define GPIO_PSR2_PSR218 (0x00040000uL)
+#define GPIO_PSR2_PSR219 (0x00080000uL)
+#define GPIO_PSR2_PSR220 (0x00100000uL)
+#define GPIO_PSR2_PSR221 (0x00200000uL)
+#define GPIO_PSR2_PSR222 (0x00400000uL)
+#define GPIO_PSR2_PSR223 (0x00800000uL)
+#define GPIO_PSR2_PSR224 (0x01000000uL)
+#define GPIO_PSR2_PSR225 (0x02000000uL)
+#define GPIO_PSR2_PSR226 (0x04000000uL)
+#define GPIO_PSR2_PSR227 (0x08000000uL)
+#define GPIO_PSR2_PSR228 (0x10000000uL)
+#define GPIO_PSR2_PSR229 (0x20000000uL)
+#define GPIO_PSR2_PSR230 (0x40000000uL)
+#define GPIO_PSR2_PSR231 (0x80000000uL)
+
+#define GPIO_PPR2_PPR20 (0x0001u)
+#define GPIO_PPR2_PPR21 (0x0002u)
+#define GPIO_PPR2_PPR22 (0x0004u)
+#define GPIO_PPR2_PPR23 (0x0008u)
+#define GPIO_PPR2_PPR24 (0x0010u)
+#define GPIO_PPR2_PPR25 (0x0020u)
+#define GPIO_PPR2_PPR26 (0x0040u)
+#define GPIO_PPR2_PPR27 (0x0080u)
+#define GPIO_PPR2_PPR28 (0x0100u)
+#define GPIO_PPR2_PPR29 (0x0200u)
+#define GPIO_PPR2_PPR210 (0x0400u)
+#define GPIO_PPR2_PPR211 (0x0800u)
+#define GPIO_PPR2_PPR212 (0x1000u)
+#define GPIO_PPR2_PPR213 (0x2000u)
+#define GPIO_PPR2_PPR214 (0x4000u)
+#define GPIO_PPR2_PPR215 (0x8000u)
+
+#define GPIO_PM2_PM20 (0x0001u)
+#define GPIO_PM2_PM21 (0x0002u)
+#define GPIO_PM2_PM22 (0x0004u)
+#define GPIO_PM2_PM23 (0x0008u)
+#define GPIO_PM2_PM24 (0x0010u)
+#define GPIO_PM2_PM25 (0x0020u)
+#define GPIO_PM2_PM26 (0x0040u)
+#define GPIO_PM2_PM27 (0x0080u)
+#define GPIO_PM2_PM28 (0x0100u)
+#define GPIO_PM2_PM29 (0x0200u)
+#define GPIO_PM2_PM210 (0x0400u)
+#define GPIO_PM2_PM211 (0x0800u)
+#define GPIO_PM2_PM212 (0x1000u)
+#define GPIO_PM2_PM213 (0x2000u)
+#define GPIO_PM2_PM214 (0x4000u)
+#define GPIO_PM2_PM215 (0x8000u)
+
+#define GPIO_PMC2_PMC20 (0x0001u)
+#define GPIO_PMC2_PMC21 (0x0002u)
+#define GPIO_PMC2_PMC22 (0x0004u)
+#define GPIO_PMC2_PMC23 (0x0008u)
+#define GPIO_PMC2_PMC24 (0x0010u)
+#define GPIO_PMC2_PMC25 (0x0020u)
+#define GPIO_PMC2_PMC26 (0x0040u)
+#define GPIO_PMC2_PMC27 (0x0080u)
+#define GPIO_PMC2_PMC28 (0x0100u)
+#define GPIO_PMC2_PMC29 (0x0200u)
+#define GPIO_PMC2_PMC210 (0x0400u)
+#define GPIO_PMC2_PMC211 (0x0800u)
+#define GPIO_PMC2_PMC212 (0x1000u)
+#define GPIO_PMC2_PMC213 (0x2000u)
+#define GPIO_PMC2_PMC214 (0x4000u)
+#define GPIO_PMC2_PMC215 (0x8000u)
+
+#define GPIO_PFC2_PFC20 (0x0001u)
+#define GPIO_PFC2_PFC21 (0x0002u)
+#define GPIO_PFC2_PFC22 (0x0004u)
+#define GPIO_PFC2_PFC23 (0x0008u)
+#define GPIO_PFC2_PFC24 (0x0010u)
+#define GPIO_PFC2_PFC25 (0x0020u)
+#define GPIO_PFC2_PFC26 (0x0040u)
+#define GPIO_PFC2_PFC27 (0x0080u)
+#define GPIO_PFC2_PFC28 (0x0100u)
+#define GPIO_PFC2_PFC29 (0x0200u)
+#define GPIO_PFC2_PFC210 (0x0400u)
+#define GPIO_PFC2_PFC211 (0x0800u)
+#define GPIO_PFC2_PFC212 (0x1000u)
+#define GPIO_PFC2_PFC213 (0x2000u)
+#define GPIO_PFC2_PFC214 (0x4000u)
+#define GPIO_PFC2_PFC215 (0x8000u)
+
+#define GPIO_PFCE2_PFCE20 (0x0001u)
+#define GPIO_PFCE2_PFCE21 (0x0002u)
+#define GPIO_PFCE2_PFCE22 (0x0004u)
+#define GPIO_PFCE2_PFCE23 (0x0008u)
+#define GPIO_PFCE2_PFCE24 (0x0010u)
+#define GPIO_PFCE2_PFCE25 (0x0020u)
+#define GPIO_PFCE2_PFCE26 (0x0040u)
+#define GPIO_PFCE2_PFCE27 (0x0080u)
+#define GPIO_PFCE2_PFCE28 (0x0100u)
+#define GPIO_PFCE2_PFCE29 (0x0200u)
+#define GPIO_PFCE2_PFCE210 (0x0400u)
+#define GPIO_PFCE2_PFCE211 (0x0800u)
+#define GPIO_PFCE2_PFCE212 (0x1000u)
+#define GPIO_PFCE2_PFCE213 (0x2000u)
+#define GPIO_PFCE2_PFCE214 (0x4000u)
+#define GPIO_PFCE2_PFCE215 (0x8000u)
+
+#define GPIO_PNOT2_PNOT20 (0x0001u)
+#define GPIO_PNOT2_PNOT21 (0x0002u)
+#define GPIO_PNOT2_PNOT22 (0x0004u)
+#define GPIO_PNOT2_PNOT23 (0x0008u)
+#define GPIO_PNOT2_PNOT24 (0x0010u)
+#define GPIO_PNOT2_PNOT25 (0x0020u)
+#define GPIO_PNOT2_PNOT26 (0x0040u)
+#define GPIO_PNOT2_PNOT27 (0x0080u)
+#define GPIO_PNOT2_PNOT28 (0x0100u)
+#define GPIO_PNOT2_PNOT29 (0x0200u)
+#define GPIO_PNOT2_PNOT210 (0x0400u)
+#define GPIO_PNOT2_PNOT211 (0x0800u)
+#define GPIO_PNOT2_PNOT212 (0x1000u)
+#define GPIO_PNOT2_PNOT213 (0x2000u)
+#define GPIO_PNOT2_PNOT214 (0x4000u)
+#define GPIO_PNOT2_PNOT215 (0x8000u)
+
+#define GPIO_PMSR2_PMSR20 (0x00000001uL)
+#define GPIO_PMSR2_PMSR21 (0x00000002uL)
+#define GPIO_PMSR2_PMSR22 (0x00000004uL)
+#define GPIO_PMSR2_PMSR23 (0x00000008uL)
+#define GPIO_PMSR2_PMSR24 (0x00000010uL)
+#define GPIO_PMSR2_PMSR25 (0x00000020uL)
+#define GPIO_PMSR2_PMSR26 (0x00000040uL)
+#define GPIO_PMSR2_PMSR27 (0x00000080uL)
+#define GPIO_PMSR2_PMSR28 (0x00000100uL)
+#define GPIO_PMSR2_PMSR29 (0x00000200uL)
+#define GPIO_PMSR2_PMSR210 (0x00000400uL)
+#define GPIO_PMSR2_PMSR211 (0x00000800uL)
+#define GPIO_PMSR2_PMSR212 (0x00001000uL)
+#define GPIO_PMSR2_PMSR213 (0x00002000uL)
+#define GPIO_PMSR2_PMSR214 (0x00004000uL)
+#define GPIO_PMSR2_PMSR215 (0x00008000uL)
+#define GPIO_PMSR2_PMSR216 (0x00010000uL)
+#define GPIO_PMSR2_PMSR217 (0x00020000uL)
+#define GPIO_PMSR2_PMSR218 (0x00040000uL)
+#define GPIO_PMSR2_PMSR219 (0x00080000uL)
+#define GPIO_PMSR2_PMSR220 (0x00100000uL)
+#define GPIO_PMSR2_PMSR221 (0x00200000uL)
+#define GPIO_PMSR2_PMSR222 (0x00400000uL)
+#define GPIO_PMSR2_PMSR223 (0x00800000uL)
+#define GPIO_PMSR2_PMSR224 (0x01000000uL)
+#define GPIO_PMSR2_PMSR225 (0x02000000uL)
+#define GPIO_PMSR2_PMSR226 (0x04000000uL)
+#define GPIO_PMSR2_PMSR227 (0x08000000uL)
+#define GPIO_PMSR2_PMSR228 (0x10000000uL)
+#define GPIO_PMSR2_PMSR229 (0x20000000uL)
+#define GPIO_PMSR2_PMSR230 (0x40000000uL)
+#define GPIO_PMSR2_PMSR231 (0x80000000uL)
+
+#define GPIO_PMCSR2_PMCSR20 (0x00000001uL)
+#define GPIO_PMCSR2_PMCSR21 (0x00000002uL)
+#define GPIO_PMCSR2_PMCSR22 (0x00000004uL)
+#define GPIO_PMCSR2_PMCSR23 (0x00000008uL)
+#define GPIO_PMCSR2_PMCSR24 (0x00000010uL)
+#define GPIO_PMCSR2_PMCSR25 (0x00000020uL)
+#define GPIO_PMCSR2_PMCSR26 (0x00000040uL)
+#define GPIO_PMCSR2_PMCSR27 (0x00000080uL)
+#define GPIO_PMCSR2_PMCSR28 (0x00000100uL)
+#define GPIO_PMCSR2_PMCSR29 (0x00000200uL)
+#define GPIO_PMCSR2_PMCSR210 (0x00000400uL)
+#define GPIO_PMCSR2_PMCSR211 (0x00000800uL)
+#define GPIO_PMCSR2_PMCSR212 (0x00001000uL)
+#define GPIO_PMCSR2_PMCSR213 (0x00002000uL)
+#define GPIO_PMCSR2_PMCSR214 (0x00004000uL)
+#define GPIO_PMCSR2_PMCSR215 (0x00008000uL)
+#define GPIO_PMCSR2_PMCSR216 (0x00010000uL)
+#define GPIO_PMCSR2_PMCSR217 (0x00020000uL)
+#define GPIO_PMCSR2_PMCSR218 (0x00040000uL)
+#define GPIO_PMCSR2_PMCSR219 (0x00080000uL)
+#define GPIO_PMCSR2_PMCSR220 (0x00100000uL)
+#define GPIO_PMCSR2_PMCSR221 (0x00200000uL)
+#define GPIO_PMCSR2_PMCSR222 (0x00400000uL)
+#define GPIO_PMCSR2_PMCSR223 (0x00800000uL)
+#define GPIO_PMCSR2_PMCSR224 (0x01000000uL)
+#define GPIO_PMCSR2_PMCSR225 (0x02000000uL)
+#define GPIO_PMCSR2_PMCSR226 (0x04000000uL)
+#define GPIO_PMCSR2_PMCSR227 (0x08000000uL)
+#define GPIO_PMCSR2_PMCSR228 (0x10000000uL)
+#define GPIO_PMCSR2_PMCSR229 (0x20000000uL)
+#define GPIO_PMCSR2_PMCSR230 (0x40000000uL)
+#define GPIO_PMCSR2_PMCSR231 (0x80000000uL)
+
+#define GPIO_PFCAE2_PFCAE20 (0x0001u)
+#define GPIO_PFCAE2_PFCAE21 (0x0002u)
+#define GPIO_PFCAE2_PFCAE22 (0x0004u)
+#define GPIO_PFCAE2_PFCAE23 (0x0008u)
+#define GPIO_PFCAE2_PFCAE24 (0x0010u)
+#define GPIO_PFCAE2_PFCAE25 (0x0020u)
+#define GPIO_PFCAE2_PFCAE26 (0x0040u)
+#define GPIO_PFCAE2_PFCAE27 (0x0080u)
+#define GPIO_PFCAE2_PFCAE28 (0x0100u)
+#define GPIO_PFCAE2_PFCAE29 (0x0200u)
+#define GPIO_PFCAE2_PFCAE210 (0x0400u)
+#define GPIO_PFCAE2_PFCAE211 (0x0800u)
+#define GPIO_PFCAE2_PFCAE212 (0x1000u)
+#define GPIO_PFCAE2_PFCAE213 (0x2000u)
+#define GPIO_PFCAE2_PFCAE214 (0x4000u)
+#define GPIO_PFCAE2_PFCAE215 (0x8000u)
+
+#define GPIO_PIBC2_PIBC20 (0x0001u)
+#define GPIO_PIBC2_PIBC21 (0x0002u)
+#define GPIO_PIBC2_PIBC22 (0x0004u)
+#define GPIO_PIBC2_PIBC23 (0x0008u)
+#define GPIO_PIBC2_PIBC24 (0x0010u)
+#define GPIO_PIBC2_PIBC25 (0x0020u)
+#define GPIO_PIBC2_PIBC26 (0x0040u)
+#define GPIO_PIBC2_PIBC27 (0x0080u)
+#define GPIO_PIBC2_PIBC28 (0x0100u)
+#define GPIO_PIBC2_PIBC29 (0x0200u)
+#define GPIO_PIBC2_PIBC210 (0x0400u)
+#define GPIO_PIBC2_PIBC211 (0x0800u)
+#define GPIO_PIBC2_PIBC212 (0x1000u)
+#define GPIO_PIBC2_PIBC213 (0x2000u)
+#define GPIO_PIBC2_PIBC214 (0x4000u)
+#define GPIO_PIBC2_PIBC215 (0x8000u)
+
+#define GPIO_PBDC2_PBDC20 (0x0001u)
+#define GPIO_PBDC2_PBDC21 (0x0002u)
+#define GPIO_PBDC2_PBDC22 (0x0004u)
+#define GPIO_PBDC2_PBDC23 (0x0008u)
+#define GPIO_PBDC2_PBDC24 (0x0010u)
+#define GPIO_PBDC2_PBDC25 (0x0020u)
+#define GPIO_PBDC2_PBDC26 (0x0040u)
+#define GPIO_PBDC2_PBDC27 (0x0080u)
+#define GPIO_PBDC2_PBDC28 (0x0100u)
+#define GPIO_PBDC2_PBDC29 (0x0200u)
+#define GPIO_PBDC2_PBDC210 (0x0400u)
+#define GPIO_PBDC2_PBDC211 (0x0800u)
+#define GPIO_PBDC2_PBDC212 (0x1000u)
+#define GPIO_PBDC2_PBDC213 (0x2000u)
+#define GPIO_PBDC2_PBDC214 (0x4000u)
+#define GPIO_PBDC2_PBDC215 (0x8000u)
+
+#define GPIO_PIPC2_PIPC20 (0x0001u)
+#define GPIO_PIPC2_PIPC21 (0x0002u)
+#define GPIO_PIPC2_PIPC22 (0x0004u)
+#define GPIO_PIPC2_PIPC23 (0x0008u)
+#define GPIO_PIPC2_PIPC24 (0x0010u)
+#define GPIO_PIPC2_PIPC25 (0x0020u)
+#define GPIO_PIPC2_PIPC26 (0x0040u)
+#define GPIO_PIPC2_PIPC27 (0x0080u)
+#define GPIO_PIPC2_PIPC28 (0x0100u)
+#define GPIO_PIPC2_PIPC29 (0x0200u)
+#define GPIO_PIPC2_PIPC210 (0x0400u)
+#define GPIO_PIPC2_PIPC211 (0x0800u)
+#define GPIO_PIPC2_PIPC212 (0x1000u)
+#define GPIO_PIPC2_PIPC213 (0x2000u)
+#define GPIO_PIPC2_PIPC214 (0x4000u)
+#define GPIO_PIPC2_PIPC215 (0x8000u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30 (0x0001u)
+#define GPIO_P3_P31 (0x0002u)
+#define GPIO_P3_P32 (0x0004u)
+#define GPIO_P3_P33 (0x0008u)
+#define GPIO_P3_P34 (0x0010u)
+#define GPIO_P3_P35 (0x0020u)
+#define GPIO_P3_P36 (0x0040u)
+#define GPIO_P3_P37 (0x0080u)
+#define GPIO_P3_P38 (0x0100u)
+#define GPIO_P3_P39 (0x0200u)
+#define GPIO_P3_P310 (0x0400u)
+#define GPIO_P3_P311 (0x0800u)
+#define GPIO_P3_P312 (0x1000u)
+#define GPIO_P3_P313 (0x2000u)
+#define GPIO_P3_P314 (0x4000u)
+#define GPIO_P3_P315 (0x8000u)
+
+#define GPIO_PSR3_PSR30 (0x00000001uL)
+#define GPIO_PSR3_PSR31 (0x00000002uL)
+#define GPIO_PSR3_PSR32 (0x00000004uL)
+#define GPIO_PSR3_PSR33 (0x00000008uL)
+#define GPIO_PSR3_PSR34 (0x00000010uL)
+#define GPIO_PSR3_PSR35 (0x00000020uL)
+#define GPIO_PSR3_PSR36 (0x00000040uL)
+#define GPIO_PSR3_PSR37 (0x00000080uL)
+#define GPIO_PSR3_PSR38 (0x00000100uL)
+#define GPIO_PSR3_PSR39 (0x00000200uL)
+#define GPIO_PSR3_PSR310 (0x00000400uL)
+#define GPIO_PSR3_PSR311 (0x00000800uL)
+#define GPIO_PSR3_PSR312 (0x00001000uL)
+#define GPIO_PSR3_PSR313 (0x00002000uL)
+#define GPIO_PSR3_PSR314 (0x00004000uL)
+#define GPIO_PSR3_PSR315 (0x00008000uL)
+#define GPIO_PSR3_PSR316 (0x00010000uL)
+#define GPIO_PSR3_PSR317 (0x00020000uL)
+#define GPIO_PSR3_PSR318 (0x00040000uL)
+#define GPIO_PSR3_PSR319 (0x00080000uL)
+#define GPIO_PSR3_PSR320 (0x00100000uL)
+#define GPIO_PSR3_PSR321 (0x00200000uL)
+#define GPIO_PSR3_PSR322 (0x00400000uL)
+#define GPIO_PSR3_PSR323 (0x00800000uL)
+#define GPIO_PSR3_PSR324 (0x01000000uL)
+#define GPIO_PSR3_PSR325 (0x02000000uL)
+#define GPIO_PSR3_PSR326 (0x04000000uL)
+#define GPIO_PSR3_PSR327 (0x08000000uL)
+#define GPIO_PSR3_PSR328 (0x10000000uL)
+#define GPIO_PSR3_PSR329 (0x20000000uL)
+#define GPIO_PSR3_PSR330 (0x40000000uL)
+#define GPIO_PSR3_PSR331 (0x80000000uL)
+
+#define GPIO_PPR3_PPR30 (0x0001u)
+#define GPIO_PPR3_PPR31 (0x0002u)
+#define GPIO_PPR3_PPR32 (0x0004u)
+#define GPIO_PPR3_PPR33 (0x0008u)
+#define GPIO_PPR3_PPR34 (0x0010u)
+#define GPIO_PPR3_PPR35 (0x0020u)
+#define GPIO_PPR3_PPR36 (0x0040u)
+#define GPIO_PPR3_PPR37 (0x0080u)
+#define GPIO_PPR3_PPR38 (0x0100u)
+#define GPIO_PPR3_PPR39 (0x0200u)
+#define GPIO_PPR3_PPR310 (0x0400u)
+#define GPIO_PPR3_PPR311 (0x0800u)
+#define GPIO_PPR3_PPR312 (0x1000u)
+#define GPIO_PPR3_PPR313 (0x2000u)
+#define GPIO_PPR3_PPR314 (0x4000u)
+#define GPIO_PPR3_PPR315 (0x8000u)
+
+#define GPIO_PM3_PM30 (0x0001u)
+#define GPIO_PM3_PM31 (0x0002u)
+#define GPIO_PM3_PM32 (0x0004u)
+#define GPIO_PM3_PM33 (0x0008u)
+#define GPIO_PM3_PM34 (0x0010u)
+#define GPIO_PM3_PM35 (0x0020u)
+#define GPIO_PM3_PM36 (0x0040u)
+#define GPIO_PM3_PM37 (0x0080u)
+#define GPIO_PM3_PM38 (0x0100u)
+#define GPIO_PM3_PM39 (0x0200u)
+#define GPIO_PM3_PM310 (0x0400u)
+#define GPIO_PM3_PM311 (0x0800u)
+#define GPIO_PM3_PM312 (0x1000u)
+#define GPIO_PM3_PM313 (0x2000u)
+#define GPIO_PM3_PM314 (0x4000u)
+#define GPIO_PM3_PM315 (0x8000u)
+
+#define GPIO_PMC3_PMC30 (0x0001u)
+#define GPIO_PMC3_PMC31 (0x0002u)
+#define GPIO_PMC3_PMC32 (0x0004u)
+#define GPIO_PMC3_PMC33 (0x0008u)
+#define GPIO_PMC3_PMC34 (0x0010u)
+#define GPIO_PMC3_PMC35 (0x0020u)
+#define GPIO_PMC3_PMC36 (0x0040u)
+#define GPIO_PMC3_PMC37 (0x0080u)
+#define GPIO_PMC3_PMC38 (0x0100u)
+#define GPIO_PMC3_PMC39 (0x0200u)
+#define GPIO_PMC3_PMC310 (0x0400u)
+#define GPIO_PMC3_PMC311 (0x0800u)
+#define GPIO_PMC3_PMC312 (0x1000u)
+#define GPIO_PMC3_PMC313 (0x2000u)
+#define GPIO_PMC3_PMC314 (0x4000u)
+#define GPIO_PMC3_PMC315 (0x8000u)
+
+#define GPIO_PFC3_PFC30 (0x0001u)
+#define GPIO_PFC3_PFC31 (0x0002u)
+#define GPIO_PFC3_PFC32 (0x0004u)
+#define GPIO_PFC3_PFC33 (0x0008u)
+#define GPIO_PFC3_PFC34 (0x0010u)
+#define GPIO_PFC3_PFC35 (0x0020u)
+#define GPIO_PFC3_PFC36 (0x0040u)
+#define GPIO_PFC3_PFC37 (0x0080u)
+#define GPIO_PFC3_PFC38 (0x0100u)
+#define GPIO_PFC3_PFC39 (0x0200u)
+#define GPIO_PFC3_PFC310 (0x0400u)
+#define GPIO_PFC3_PFC311 (0x0800u)
+#define GPIO_PFC3_PFC312 (0x1000u)
+#define GPIO_PFC3_PFC313 (0x2000u)
+#define GPIO_PFC3_PFC314 (0x4000u)
+#define GPIO_PFC3_PFC315 (0x8000u)
+
+#define GPIO_PFCE3_PFCE30 (0x0001u)
+#define GPIO_PFCE3_PFCE31 (0x0002u)
+#define GPIO_PFCE3_PFCE32 (0x0004u)
+#define GPIO_PFCE3_PFCE33 (0x0008u)
+#define GPIO_PFCE3_PFCE34 (0x0010u)
+#define GPIO_PFCE3_PFCE35 (0x0020u)
+#define GPIO_PFCE3_PFCE36 (0x0040u)
+#define GPIO_PFCE3_PFCE37 (0x0080u)
+#define GPIO_PFCE3_PFCE38 (0x0100u)
+#define GPIO_PFCE3_PFCE39 (0x0200u)
+#define GPIO_PFCE3_PFCE310 (0x0400u)
+#define GPIO_PFCE3_PFCE311 (0x0800u)
+#define GPIO_PFCE3_PFCE312 (0x1000u)
+#define GPIO_PFCE3_PFCE313 (0x2000u)
+#define GPIO_PFCE3_PFCE314 (0x4000u)
+#define GPIO_PFCE3_PFCE315 (0x8000u)
+
+#define GPIO_PNOT3_PNOT30 (0x0001u)
+#define GPIO_PNOT3_PNOT31 (0x0002u)
+#define GPIO_PNOT3_PNOT32 (0x0004u)
+#define GPIO_PNOT3_PNOT33 (0x0008u)
+#define GPIO_PNOT3_PNOT34 (0x0010u)
+#define GPIO_PNOT3_PNOT35 (0x0020u)
+#define GPIO_PNOT3_PNOT36 (0x0040u)
+#define GPIO_PNOT3_PNOT37 (0x0080u)
+#define GPIO_PNOT3_PNOT38 (0x0100u)
+#define GPIO_PNOT3_PNOT39 (0x0200u)
+#define GPIO_PNOT3_PNOT310 (0x0400u)
+#define GPIO_PNOT3_PNOT311 (0x0800u)
+#define GPIO_PNOT3_PNOT312 (0x1000u)
+#define GPIO_PNOT3_PNOT313 (0x2000u)
+#define GPIO_PNOT3_PNOT314 (0x4000u)
+#define GPIO_PNOT3_PNOT315 (0x8000u)
+
+#define GPIO_PMSR3_PMSR30 (0x00000001uL)
+#define GPIO_PMSR3_PMSR31 (0x00000002uL)
+#define GPIO_PMSR3_PMSR32 (0x00000004uL)
+#define GPIO_PMSR3_PMSR33 (0x00000008uL)
+#define GPIO_PMSR3_PMSR34 (0x00000010uL)
+#define GPIO_PMSR3_PMSR35 (0x00000020uL)
+#define GPIO_PMSR3_PMSR36 (0x00000040uL)
+#define GPIO_PMSR3_PMSR37 (0x00000080uL)
+#define GPIO_PMSR3_PMSR38 (0x00000100uL)
+#define GPIO_PMSR3_PMSR39 (0x00000200uL)
+#define GPIO_PMSR3_PMSR310 (0x00000400uL)
+#define GPIO_PMSR3_PMSR311 (0x00000800uL)
+#define GPIO_PMSR3_PMSR312 (0x00001000uL)
+#define GPIO_PMSR3_PMSR313 (0x00002000uL)
+#define GPIO_PMSR3_PMSR314 (0x00004000uL)
+#define GPIO_PMSR3_PMSR315 (0x00008000uL)
+#define GPIO_PMSR3_PMSR316 (0x00010000uL)
+#define GPIO_PMSR3_PMSR317 (0x00020000uL)
+#define GPIO_PMSR3_PMSR318 (0x00040000uL)
+#define GPIO_PMSR3_PMSR319 (0x00080000uL)
+#define GPIO_PMSR3_PMSR320 (0x00100000uL)
+#define GPIO_PMSR3_PMSR321 (0x00200000uL)
+#define GPIO_PMSR3_PMSR322 (0x00400000uL)
+#define GPIO_PMSR3_PMSR323 (0x00800000uL)
+#define GPIO_PMSR3_PMSR324 (0x01000000uL)
+#define GPIO_PMSR3_PMSR325 (0x02000000uL)
+#define GPIO_PMSR3_PMSR326 (0x04000000uL)
+#define GPIO_PMSR3_PMSR327 (0x08000000uL)
+#define GPIO_PMSR3_PMSR328 (0x10000000uL)
+#define GPIO_PMSR3_PMSR329 (0x20000000uL)
+#define GPIO_PMSR3_PMSR330 (0x40000000uL)
+#define GPIO_PMSR3_PMSR331 (0x80000000uL)
+
+#define GPIO_PMCSR3_PMCSR30 (0x00000001uL)
+#define GPIO_PMCSR3_PMCSR31 (0x00000002uL)
+#define GPIO_PMCSR3_PMCSR32 (0x00000004uL)
+#define GPIO_PMCSR3_PMCSR33 (0x00000008uL)
+#define GPIO_PMCSR3_PMCSR34 (0x00000010uL)
+#define GPIO_PMCSR3_PMCSR35 (0x00000020uL)
+#define GPIO_PMCSR3_PMCSR36 (0x00000040uL)
+#define GPIO_PMCSR3_PMCSR37 (0x00000080uL)
+#define GPIO_PMCSR3_PMCSR38 (0x00000100uL)
+#define GPIO_PMCSR3_PMCSR39 (0x00000200uL)
+#define GPIO_PMCSR3_PMCSR310 (0x00000400uL)
+#define GPIO_PMCSR3_PMCSR311 (0x00000800uL)
+#define GPIO_PMCSR3_PMCSR312 (0x00001000uL)
+#define GPIO_PMCSR3_PMCSR313 (0x00002000uL)
+#define GPIO_PMCSR3_PMCSR314 (0x00004000uL)
+#define GPIO_PMCSR3_PMCSR315 (0x00008000uL)
+#define GPIO_PMCSR3_PMCSR316 (0x00010000uL)
+#define GPIO_PMCSR3_PMCSR317 (0x00020000uL)
+#define GPIO_PMCSR3_PMCSR318 (0x00040000uL)
+#define GPIO_PMCSR3_PMCSR319 (0x00080000uL)
+#define GPIO_PMCSR3_PMCSR320 (0x00100000uL)
+#define GPIO_PMCSR3_PMCSR321 (0x00200000uL)
+#define GPIO_PMCSR3_PMCSR322 (0x00400000uL)
+#define GPIO_PMCSR3_PMCSR323 (0x00800000uL)
+#define GPIO_PMCSR3_PMCSR324 (0x01000000uL)
+#define GPIO_PMCSR3_PMCSR325 (0x02000000uL)
+#define GPIO_PMCSR3_PMCSR326 (0x04000000uL)
+#define GPIO_PMCSR3_PMCSR327 (0x08000000uL)
+#define GPIO_PMCSR3_PMCSR328 (0x10000000uL)
+#define GPIO_PMCSR3_PMCSR329 (0x20000000uL)
+#define GPIO_PMCSR3_PMCSR330 (0x40000000uL)
+#define GPIO_PMCSR3_PMCSR331 (0x80000000uL)
+
+#define GPIO_PFCAE3_PFCAE30 (0x0001u)
+#define GPIO_PFCAE3_PFCAE31 (0x0002u)
+#define GPIO_PFCAE3_PFCAE32 (0x0004u)
+#define GPIO_PFCAE3_PFCAE33 (0x0008u)
+#define GPIO_PFCAE3_PFCAE34 (0x0010u)
+#define GPIO_PFCAE3_PFCAE35 (0x0020u)
+#define GPIO_PFCAE3_PFCAE36 (0x0040u)
+#define GPIO_PFCAE3_PFCAE37 (0x0080u)
+#define GPIO_PFCAE3_PFCAE38 (0x0100u)
+#define GPIO_PFCAE3_PFCAE39 (0x0200u)
+#define GPIO_PFCAE3_PFCAE310 (0x0400u)
+#define GPIO_PFCAE3_PFCAE311 (0x0800u)
+#define GPIO_PFCAE3_PFCAE312 (0x1000u)
+#define GPIO_PFCAE3_PFCAE313 (0x2000u)
+#define GPIO_PFCAE3_PFCAE314 (0x4000u)
+#define GPIO_PFCAE3_PFCAE315 (0x8000u)
+
+#define GPIO_PIBC3_PIBC30 (0x0001u)
+#define GPIO_PIBC3_PIBC31 (0x0002u)
+#define GPIO_PIBC3_PIBC32 (0x0004u)
+#define GPIO_PIBC3_PIBC33 (0x0008u)
+#define GPIO_PIBC3_PIBC34 (0x0010u)
+#define GPIO_PIBC3_PIBC35 (0x0020u)
+#define GPIO_PIBC3_PIBC36 (0x0040u)
+#define GPIO_PIBC3_PIBC37 (0x0080u)
+#define GPIO_PIBC3_PIBC38 (0x0100u)
+#define GPIO_PIBC3_PIBC39 (0x0200u)
+#define GPIO_PIBC3_PIBC310 (0x0400u)
+#define GPIO_PIBC3_PIBC311 (0x0800u)
+#define GPIO_PIBC3_PIBC312 (0x1000u)
+#define GPIO_PIBC3_PIBC313 (0x2000u)
+#define GPIO_PIBC3_PIBC314 (0x4000u)
+#define GPIO_PIBC3_PIBC315 (0x8000u)
+
+#define GPIO_PBDC3_PBDC30 (0x0001u)
+#define GPIO_PBDC3_PBDC31 (0x0002u)
+#define GPIO_PBDC3_PBDC32 (0x0004u)
+#define GPIO_PBDC3_PBDC33 (0x0008u)
+#define GPIO_PBDC3_PBDC34 (0x0010u)
+#define GPIO_PBDC3_PBDC35 (0x0020u)
+#define GPIO_PBDC3_PBDC36 (0x0040u)
+#define GPIO_PBDC3_PBDC37 (0x0080u)
+#define GPIO_PBDC3_PBDC38 (0x0100u)
+#define GPIO_PBDC3_PBDC39 (0x0200u)
+#define GPIO_PBDC3_PBDC310 (0x0400u)
+#define GPIO_PBDC3_PBDC311 (0x0800u)
+#define GPIO_PBDC3_PBDC312 (0x1000u)
+#define GPIO_PBDC3_PBDC313 (0x2000u)
+#define GPIO_PBDC3_PBDC314 (0x4000u)
+#define GPIO_PBDC3_PBDC315 (0x8000u)
+
+#define GPIO_PIPC3_PIPC30 (0x0001u)
+#define GPIO_PIPC3_PIPC31 (0x0002u)
+#define GPIO_PIPC3_PIPC32 (0x0004u)
+#define GPIO_PIPC3_PIPC33 (0x0008u)
+#define GPIO_PIPC3_PIPC34 (0x0010u)
+#define GPIO_PIPC3_PIPC35 (0x0020u)
+#define GPIO_PIPC3_PIPC36 (0x0040u)
+#define GPIO_PIPC3_PIPC37 (0x0080u)
+#define GPIO_PIPC3_PIPC38 (0x0100u)
+#define GPIO_PIPC3_PIPC39 (0x0200u)
+#define GPIO_PIPC3_PIPC310 (0x0400u)
+#define GPIO_PIPC3_PIPC311 (0x0800u)
+#define GPIO_PIPC3_PIPC312 (0x1000u)
+#define GPIO_PIPC3_PIPC313 (0x2000u)
+#define GPIO_PIPC3_PIPC314 (0x4000u)
+#define GPIO_PIPC3_PIPC315 (0x8000u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40 (0x0001u)
+#define GPIO_P4_P41 (0x0002u)
+#define GPIO_P4_P42 (0x0004u)
+#define GPIO_P4_P43 (0x0008u)
+#define GPIO_P4_P44 (0x0010u)
+#define GPIO_P4_P45 (0x0020u)
+#define GPIO_P4_P46 (0x0040u)
+#define GPIO_P4_P47 (0x0080u)
+#define GPIO_P4_P48 (0x0100u)
+#define GPIO_P4_P49 (0x0200u)
+#define GPIO_P4_P410 (0x0400u)
+#define GPIO_P4_P411 (0x0800u)
+#define GPIO_P4_P412 (0x1000u)
+#define GPIO_P4_P413 (0x2000u)
+#define GPIO_P4_P414 (0x4000u)
+#define GPIO_P4_P415 (0x8000u)
+
+#define GPIO_PSR4_PSR40 (0x00000001uL)
+#define GPIO_PSR4_PSR41 (0x00000002uL)
+#define GPIO_PSR4_PSR42 (0x00000004uL)
+#define GPIO_PSR4_PSR43 (0x00000008uL)
+#define GPIO_PSR4_PSR44 (0x00000010uL)
+#define GPIO_PSR4_PSR45 (0x00000020uL)
+#define GPIO_PSR4_PSR46 (0x00000040uL)
+#define GPIO_PSR4_PSR47 (0x00000080uL)
+#define GPIO_PSR4_PSR48 (0x00000100uL)
+#define GPIO_PSR4_PSR49 (0x00000200uL)
+#define GPIO_PSR4_PSR410 (0x00000400uL)
+#define GPIO_PSR4_PSR411 (0x00000800uL)
+#define GPIO_PSR4_PSR412 (0x00001000uL)
+#define GPIO_PSR4_PSR413 (0x00002000uL)
+#define GPIO_PSR4_PSR414 (0x00004000uL)
+#define GPIO_PSR4_PSR415 (0x00008000uL)
+#define GPIO_PSR4_PSR416 (0x00010000uL)
+#define GPIO_PSR4_PSR417 (0x00020000uL)
+#define GPIO_PSR4_PSR418 (0x00040000uL)
+#define GPIO_PSR4_PSR419 (0x00080000uL)
+#define GPIO_PSR4_PSR420 (0x00100000uL)
+#define GPIO_PSR4_PSR421 (0x00200000uL)
+#define GPIO_PSR4_PSR422 (0x00400000uL)
+#define GPIO_PSR4_PSR423 (0x00800000uL)
+#define GPIO_PSR4_PSR424 (0x01000000uL)
+#define GPIO_PSR4_PSR425 (0x02000000uL)
+#define GPIO_PSR4_PSR426 (0x04000000uL)
+#define GPIO_PSR4_PSR427 (0x08000000uL)
+#define GPIO_PSR4_PSR428 (0x10000000uL)
+#define GPIO_PSR4_PSR429 (0x20000000uL)
+#define GPIO_PSR4_PSR430 (0x40000000uL)
+#define GPIO_PSR4_PSR431 (0x80000000uL)
+
+#define GPIO_PPR4_PPR40 (0x0001u)
+#define GPIO_PPR4_PPR41 (0x0002u)
+#define GPIO_PPR4_PPR42 (0x0004u)
+#define GPIO_PPR4_PPR43 (0x0008u)
+#define GPIO_PPR4_PPR44 (0x0010u)
+#define GPIO_PPR4_PPR45 (0x0020u)
+#define GPIO_PPR4_PPR46 (0x0040u)
+#define GPIO_PPR4_PPR47 (0x0080u)
+#define GPIO_PPR4_PPR48 (0x0100u)
+#define GPIO_PPR4_PPR49 (0x0200u)
+#define GPIO_PPR4_PPR410 (0x0400u)
+#define GPIO_PPR4_PPR411 (0x0800u)
+#define GPIO_PPR4_PPR412 (0x1000u)
+#define GPIO_PPR4_PPR413 (0x2000u)
+#define GPIO_PPR4_PPR414 (0x4000u)
+#define GPIO_PPR4_PPR415 (0x8000u)
+
+#define GPIO_PM4_PM40 (0x0001u)
+#define GPIO_PM4_PM41 (0x0002u)
+#define GPIO_PM4_PM42 (0x0004u)
+#define GPIO_PM4_PM43 (0x0008u)
+#define GPIO_PM4_PM44 (0x0010u)
+#define GPIO_PM4_PM45 (0x0020u)
+#define GPIO_PM4_PM46 (0x0040u)
+#define GPIO_PM4_PM47 (0x0080u)
+#define GPIO_PM4_PM48 (0x0100u)
+#define GPIO_PM4_PM49 (0x0200u)
+#define GPIO_PM4_PM410 (0x0400u)
+#define GPIO_PM4_PM411 (0x0800u)
+#define GPIO_PM4_PM412 (0x1000u)
+#define GPIO_PM4_PM413 (0x2000u)
+#define GPIO_PM4_PM414 (0x4000u)
+#define GPIO_PM4_PM415 (0x8000u)
+
+#define GPIO_PMC4_PMC40 (0x0001u)
+#define GPIO_PMC4_PMC41 (0x0002u)
+#define GPIO_PMC4_PMC42 (0x0004u)
+#define GPIO_PMC4_PMC43 (0x0008u)
+#define GPIO_PMC4_PMC44 (0x0010u)
+#define GPIO_PMC4_PMC45 (0x0020u)
+#define GPIO_PMC4_PMC46 (0x0040u)
+#define GPIO_PMC4_PMC47 (0x0080u)
+#define GPIO_PMC4_PMC48 (0x0100u)
+#define GPIO_PMC4_PMC49 (0x0200u)
+#define GPIO_PMC4_PMC410 (0x0400u)
+#define GPIO_PMC4_PMC411 (0x0800u)
+#define GPIO_PMC4_PMC412 (0x1000u)
+#define GPIO_PMC4_PMC413 (0x2000u)
+#define GPIO_PMC4_PMC414 (0x4000u)
+#define GPIO_PMC4_PMC415 (0x8000u)
+
+#define GPIO_PFC4_PFC40 (0x0001u)
+#define GPIO_PFC4_PFC41 (0x0002u)
+#define GPIO_PFC4_PFC42 (0x0004u)
+#define GPIO_PFC4_PFC43 (0x0008u)
+#define GPIO_PFC4_PFC44 (0x0010u)
+#define GPIO_PFC4_PFC45 (0x0020u)
+#define GPIO_PFC4_PFC46 (0x0040u)
+#define GPIO_PFC4_PFC47 (0x0080u)
+#define GPIO_PFC4_PFC48 (0x0100u)
+#define GPIO_PFC4_PFC49 (0x0200u)
+#define GPIO_PFC4_PFC410 (0x0400u)
+#define GPIO_PFC4_PFC411 (0x0800u)
+#define GPIO_PFC4_PFC412 (0x1000u)
+#define GPIO_PFC4_PFC413 (0x2000u)
+#define GPIO_PFC4_PFC414 (0x4000u)
+#define GPIO_PFC4_PFC415 (0x8000u)
+
+#define GPIO_PFCE4_PFCE40 (0x0001u)
+#define GPIO_PFCE4_PFCE41 (0x0002u)
+#define GPIO_PFCE4_PFCE42 (0x0004u)
+#define GPIO_PFCE4_PFCE43 (0x0008u)
+#define GPIO_PFCE4_PFCE44 (0x0010u)
+#define GPIO_PFCE4_PFCE45 (0x0020u)
+#define GPIO_PFCE4_PFCE46 (0x0040u)
+#define GPIO_PFCE4_PFCE47 (0x0080u)
+#define GPIO_PFCE4_PFCE48 (0x0100u)
+#define GPIO_PFCE4_PFCE49 (0x0200u)
+#define GPIO_PFCE4_PFCE410 (0x0400u)
+#define GPIO_PFCE4_PFCE411 (0x0800u)
+#define GPIO_PFCE4_PFCE412 (0x1000u)
+#define GPIO_PFCE4_PFCE413 (0x2000u)
+#define GPIO_PFCE4_PFCE414 (0x4000u)
+#define GPIO_PFCE4_PFCE415 (0x8000u)
+
+#define GPIO_PNOT4_PNOT40 (0x0001u)
+#define GPIO_PNOT4_PNOT41 (0x0002u)
+#define GPIO_PNOT4_PNOT42 (0x0004u)
+#define GPIO_PNOT4_PNOT43 (0x0008u)
+#define GPIO_PNOT4_PNOT44 (0x0010u)
+#define GPIO_PNOT4_PNOT45 (0x0020u)
+#define GPIO_PNOT4_PNOT46 (0x0040u)
+#define GPIO_PNOT4_PNOT47 (0x0080u)
+#define GPIO_PNOT4_PNOT48 (0x0100u)
+#define GPIO_PNOT4_PNOT49 (0x0200u)
+#define GPIO_PNOT4_PNOT410 (0x0400u)
+#define GPIO_PNOT4_PNOT411 (0x0800u)
+#define GPIO_PNOT4_PNOT412 (0x1000u)
+#define GPIO_PNOT4_PNOT413 (0x2000u)
+#define GPIO_PNOT4_PNOT414 (0x4000u)
+#define GPIO_PNOT4_PNOT415 (0x8000u)
+
+#define GPIO_PMSR4_PMSR40 (0x00000001uL)
+#define GPIO_PMSR4_PMSR41 (0x00000002uL)
+#define GPIO_PMSR4_PMSR42 (0x00000004uL)
+#define GPIO_PMSR4_PMSR43 (0x00000008uL)
+#define GPIO_PMSR4_PMSR44 (0x00000010uL)
+#define GPIO_PMSR4_PMSR45 (0x00000020uL)
+#define GPIO_PMSR4_PMSR46 (0x00000040uL)
+#define GPIO_PMSR4_PMSR47 (0x00000080uL)
+#define GPIO_PMSR4_PMSR48 (0x00000100uL)
+#define GPIO_PMSR4_PMSR49 (0x00000200uL)
+#define GPIO_PMSR4_PMSR410 (0x00000400uL)
+#define GPIO_PMSR4_PMSR411 (0x00000800uL)
+#define GPIO_PMSR4_PMSR412 (0x00001000uL)
+#define GPIO_PMSR4_PMSR413 (0x00002000uL)
+#define GPIO_PMSR4_PMSR414 (0x00004000uL)
+#define GPIO_PMSR4_PMSR415 (0x00008000uL)
+#define GPIO_PMSR4_PMSR416 (0x00010000uL)
+#define GPIO_PMSR4_PMSR417 (0x00020000uL)
+#define GPIO_PMSR4_PMSR418 (0x00040000uL)
+#define GPIO_PMSR4_PMSR419 (0x00080000uL)
+#define GPIO_PMSR4_PMSR420 (0x00100000uL)
+#define GPIO_PMSR4_PMSR421 (0x00200000uL)
+#define GPIO_PMSR4_PMSR422 (0x00400000uL)
+#define GPIO_PMSR4_PMSR423 (0x00800000uL)
+#define GPIO_PMSR4_PMSR424 (0x01000000uL)
+#define GPIO_PMSR4_PMSR425 (0x02000000uL)
+#define GPIO_PMSR4_PMSR426 (0x04000000uL)
+#define GPIO_PMSR4_PMSR427 (0x08000000uL)
+#define GPIO_PMSR4_PMSR428 (0x10000000uL)
+#define GPIO_PMSR4_PMSR429 (0x20000000uL)
+#define GPIO_PMSR4_PMSR430 (0x40000000uL)
+#define GPIO_PMSR4_PMSR431 (0x80000000uL)
+
+#define GPIO_PMCSR4_PMCSR40 (0x00000001uL)
+#define GPIO_PMCSR4_PMCSR41 (0x00000002uL)
+#define GPIO_PMCSR4_PMCSR42 (0x00000004uL)
+#define GPIO_PMCSR4_PMCSR43 (0x00000008uL)
+#define GPIO_PMCSR4_PMCSR44 (0x00000010uL)
+#define GPIO_PMCSR4_PMCSR45 (0x00000020uL)
+#define GPIO_PMCSR4_PMCSR46 (0x00000040uL)
+#define GPIO_PMCSR4_PMCSR47 (0x00000080uL)
+#define GPIO_PMCSR4_PMCSR48 (0x00000100uL)
+#define GPIO_PMCSR4_PMCSR49 (0x00000200uL)
+#define GPIO_PMCSR4_PMCSR410 (0x00000400uL)
+#define GPIO_PMCSR4_PMCSR411 (0x00000800uL)
+#define GPIO_PMCSR4_PMCSR412 (0x00001000uL)
+#define GPIO_PMCSR4_PMCSR413 (0x00002000uL)
+#define GPIO_PMCSR4_PMCSR414 (0x00004000uL)
+#define GPIO_PMCSR4_PMCSR415 (0x00008000uL)
+#define GPIO_PMCSR4_PMCSR416 (0x00010000uL)
+#define GPIO_PMCSR4_PMCSR417 (0x00020000uL)
+#define GPIO_PMCSR4_PMCSR418 (0x00040000uL)
+#define GPIO_PMCSR4_PMCSR419 (0x00080000uL)
+#define GPIO_PMCSR4_PMCSR420 (0x00100000uL)
+#define GPIO_PMCSR4_PMCSR421 (0x00200000uL)
+#define GPIO_PMCSR4_PMCSR422 (0x00400000uL)
+#define GPIO_PMCSR4_PMCSR423 (0x00800000uL)
+#define GPIO_PMCSR4_PMCSR424 (0x01000000uL)
+#define GPIO_PMCSR4_PMCSR425 (0x02000000uL)
+#define GPIO_PMCSR4_PMCSR426 (0x04000000uL)
+#define GPIO_PMCSR4_PMCSR427 (0x08000000uL)
+#define GPIO_PMCSR4_PMCSR428 (0x10000000uL)
+#define GPIO_PMCSR4_PMCSR429 (0x20000000uL)
+#define GPIO_PMCSR4_PMCSR430 (0x40000000uL)
+#define GPIO_PMCSR4_PMCSR431 (0x80000000uL)
+
+#define GPIO_PFCAE4_PFCAE40 (0x0001u)
+#define GPIO_PFCAE4_PFCAE41 (0x0002u)
+#define GPIO_PFCAE4_PFCAE42 (0x0004u)
+#define GPIO_PFCAE4_PFCAE43 (0x0008u)
+#define GPIO_PFCAE4_PFCAE44 (0x0010u)
+#define GPIO_PFCAE4_PFCAE45 (0x0020u)
+#define GPIO_PFCAE4_PFCAE46 (0x0040u)
+#define GPIO_PFCAE4_PFCAE47 (0x0080u)
+#define GPIO_PFCAE4_PFCAE48 (0x0100u)
+#define GPIO_PFCAE4_PFCAE49 (0x0200u)
+#define GPIO_PFCAE4_PFCAE410 (0x0400u)
+#define GPIO_PFCAE4_PFCAE411 (0x0800u)
+#define GPIO_PFCAE4_PFCAE412 (0x1000u)
+#define GPIO_PFCAE4_PFCAE413 (0x2000u)
+#define GPIO_PFCAE4_PFCAE414 (0x4000u)
+#define GPIO_PFCAE4_PFCAE415 (0x8000u)
+
+#define GPIO_PIBC4_PIBC40 (0x0001u)
+#define GPIO_PIBC4_PIBC41 (0x0002u)
+#define GPIO_PIBC4_PIBC42 (0x0004u)
+#define GPIO_PIBC4_PIBC43 (0x0008u)
+#define GPIO_PIBC4_PIBC44 (0x0010u)
+#define GPIO_PIBC4_PIBC45 (0x0020u)
+#define GPIO_PIBC4_PIBC46 (0x0040u)
+#define GPIO_PIBC4_PIBC47 (0x0080u)
+#define GPIO_PIBC4_PIBC48 (0x0100u)
+#define GPIO_PIBC4_PIBC49 (0x0200u)
+#define GPIO_PIBC4_PIBC410 (0x0400u)
+#define GPIO_PIBC4_PIBC411 (0x0800u)
+#define GPIO_PIBC4_PIBC412 (0x1000u)
+#define GPIO_PIBC4_PIBC413 (0x2000u)
+#define GPIO_PIBC4_PIBC414 (0x4000u)
+#define GPIO_PIBC4_PIBC415 (0x8000u)
+
+#define GPIO_PBDC4_PBDC40 (0x0001u)
+#define GPIO_PBDC4_PBDC41 (0x0002u)
+#define GPIO_PBDC4_PBDC42 (0x0004u)
+#define GPIO_PBDC4_PBDC43 (0x0008u)
+#define GPIO_PBDC4_PBDC44 (0x0010u)
+#define GPIO_PBDC4_PBDC45 (0x0020u)
+#define GPIO_PBDC4_PBDC46 (0x0040u)
+#define GPIO_PBDC4_PBDC47 (0x0080u)
+#define GPIO_PBDC4_PBDC48 (0x0100u)
+#define GPIO_PBDC4_PBDC49 (0x0200u)
+#define GPIO_PBDC4_PBDC410 (0x0400u)
+#define GPIO_PBDC4_PBDC411 (0x0800u)
+#define GPIO_PBDC4_PBDC412 (0x1000u)
+#define GPIO_PBDC4_PBDC413 (0x2000u)
+#define GPIO_PBDC4_PBDC414 (0x4000u)
+#define GPIO_PBDC4_PBDC415 (0x8000u)
+
+#define GPIO_PIPC4_PIPC40 (0x0001u)
+#define GPIO_PIPC4_PIPC41 (0x0002u)
+#define GPIO_PIPC4_PIPC42 (0x0004u)
+#define GPIO_PIPC4_PIPC43 (0x0008u)
+#define GPIO_PIPC4_PIPC44 (0x0010u)
+#define GPIO_PIPC4_PIPC45 (0x0020u)
+#define GPIO_PIPC4_PIPC46 (0x0040u)
+#define GPIO_PIPC4_PIPC47 (0x0080u)
+#define GPIO_PIPC4_PIPC48 (0x0100u)
+#define GPIO_PIPC4_PIPC49 (0x0200u)
+#define GPIO_PIPC4_PIPC410 (0x0400u)
+#define GPIO_PIPC4_PIPC411 (0x0800u)
+#define GPIO_PIPC4_PIPC412 (0x1000u)
+#define GPIO_PIPC4_PIPC413 (0x2000u)
+#define GPIO_PIPC4_PIPC414 (0x4000u)
+#define GPIO_PIPC4_PIPC415 (0x8000u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50 (0x0001u)
+#define GPIO_P5_P51 (0x0002u)
+#define GPIO_P5_P52 (0x0004u)
+#define GPIO_P5_P53 (0x0008u)
+#define GPIO_P5_P54 (0x0010u)
+#define GPIO_P5_P55 (0x0020u)
+#define GPIO_P5_P56 (0x0040u)
+#define GPIO_P5_P57 (0x0080u)
+#define GPIO_P5_P58 (0x0100u)
+#define GPIO_P5_P59 (0x0200u)
+#define GPIO_P5_P510 (0x0400u)
+
+#define GPIO_PSR5_PSR50 (0x00000001uL)
+#define GPIO_PSR5_PSR51 (0x00000002uL)
+#define GPIO_PSR5_PSR52 (0x00000004uL)
+#define GPIO_PSR5_PSR53 (0x00000008uL)
+#define GPIO_PSR5_PSR54 (0x00000010uL)
+#define GPIO_PSR5_PSR55 (0x00000020uL)
+#define GPIO_PSR5_PSR56 (0x00000040uL)
+#define GPIO_PSR5_PSR57 (0x00000080uL)
+#define GPIO_PSR5_PSR58 (0x00000100uL)
+#define GPIO_PSR5_PSR59 (0x00000200uL)
+#define GPIO_PSR5_PSR510 (0x00000400uL)
+#define GPIO_PSR5_PSR516 (0x00010000uL)
+#define GPIO_PSR5_PSR517 (0x00020000uL)
+#define GPIO_PSR5_PSR518 (0x00040000uL)
+#define GPIO_PSR5_PSR519 (0x00080000uL)
+#define GPIO_PSR5_PSR520 (0x00100000uL)
+#define GPIO_PSR5_PSR521 (0x00200000uL)
+#define GPIO_PSR5_PSR522 (0x00400000uL)
+#define GPIO_PSR5_PSR523 (0x00800000uL)
+#define GPIO_PSR5_PSR524 (0x01000000uL)
+#define GPIO_PSR5_PSR525 (0x02000000uL)
+#define GPIO_PSR5_PSR526 (0x04000000uL)
+
+#define GPIO_PPR5_PPR50 (0x0001u)
+#define GPIO_PPR5_PPR51 (0x0002u)
+#define GPIO_PPR5_PPR52 (0x0004u)
+#define GPIO_PPR5_PPR53 (0x0008u)
+#define GPIO_PPR5_PPR54 (0x0010u)
+#define GPIO_PPR5_PPR55 (0x0020u)
+#define GPIO_PPR5_PPR56 (0x0040u)
+#define GPIO_PPR5_PPR57 (0x0080u)
+#define GPIO_PPR5_PPR58 (0x0100u)
+#define GPIO_PPR5_PPR59 (0x0200u)
+#define GPIO_PPR5_PPR510 (0x0400u)
+
+#define GPIO_PM5_PM50 (0x0001u)
+#define GPIO_PM5_PM51 (0x0002u)
+#define GPIO_PM5_PM52 (0x0004u)
+#define GPIO_PM5_PM53 (0x0008u)
+#define GPIO_PM5_PM54 (0x0010u)
+#define GPIO_PM5_PM55 (0x0020u)
+#define GPIO_PM5_PM56 (0x0040u)
+#define GPIO_PM5_PM57 (0x0080u)
+#define GPIO_PM5_PM58 (0x0100u)
+#define GPIO_PM5_PM59 (0x0200u)
+#define GPIO_PM5_PM510 (0x0400u)
+
+#define GPIO_PMC5_PMC50 (0x0001u)
+#define GPIO_PMC5_PMC51 (0x0002u)
+#define GPIO_PMC5_PMC52 (0x0004u)
+#define GPIO_PMC5_PMC53 (0x0008u)
+#define GPIO_PMC5_PMC54 (0x0010u)
+#define GPIO_PMC5_PMC55 (0x0020u)
+#define GPIO_PMC5_PMC56 (0x0040u)
+#define GPIO_PMC5_PMC57 (0x0080u)
+#define GPIO_PMC5_PMC58 (0x0100u)
+#define GPIO_PMC5_PMC59 (0x0200u)
+#define GPIO_PMC5_PMC510 (0x0400u)
+
+#define GPIO_PFC5_PFC50 (0x0001u)
+#define GPIO_PFC5_PFC51 (0x0002u)
+#define GPIO_PFC5_PFC52 (0x0004u)
+#define GPIO_PFC5_PFC53 (0x0008u)
+#define GPIO_PFC5_PFC54 (0x0010u)
+#define GPIO_PFC5_PFC55 (0x0020u)
+#define GPIO_PFC5_PFC56 (0x0040u)
+#define GPIO_PFC5_PFC57 (0x0080u)
+#define GPIO_PFC5_PFC58 (0x0100u)
+#define GPIO_PFC5_PFC59 (0x0200u)
+#define GPIO_PFC5_PFC510 (0x0400u)
+
+#define GPIO_PFCE5_PFCE50 (0x0001u)
+#define GPIO_PFCE5_PFCE51 (0x0002u)
+#define GPIO_PFCE5_PFCE52 (0x0004u)
+#define GPIO_PFCE5_PFCE53 (0x0008u)
+#define GPIO_PFCE5_PFCE54 (0x0010u)
+#define GPIO_PFCE5_PFCE55 (0x0020u)
+#define GPIO_PFCE5_PFCE56 (0x0040u)
+#define GPIO_PFCE5_PFCE57 (0x0080u)
+#define GPIO_PFCE5_PFCE58 (0x0100u)
+#define GPIO_PFCE5_PFCE59 (0x0200u)
+#define GPIO_PFCE5_PFCE510 (0x0400u)
+
+#define GPIO_PNOT5_PNOT50 (0x0001u)
+#define GPIO_PNOT5_PNOT51 (0x0002u)
+#define GPIO_PNOT5_PNOT52 (0x0004u)
+#define GPIO_PNOT5_PNOT53 (0x0008u)
+#define GPIO_PNOT5_PNOT54 (0x0010u)
+#define GPIO_PNOT5_PNOT55 (0x0020u)
+#define GPIO_PNOT5_PNOT56 (0x0040u)
+#define GPIO_PNOT5_PNOT57 (0x0080u)
+#define GPIO_PNOT5_PNOT58 (0x0100u)
+#define GPIO_PNOT5_PNOT59 (0x0200u)
+#define GPIO_PNOT5_PNOT510 (0x0400u)
+
+#define GPIO_PMSR5_PMSR50 (0x00000001uL)
+#define GPIO_PMSR5_PMSR51 (0x00000002uL)
+#define GPIO_PMSR5_PMSR52 (0x00000004uL)
+#define GPIO_PMSR5_PMSR53 (0x00000008uL)
+#define GPIO_PMSR5_PMSR54 (0x00000010uL)
+#define GPIO_PMSR5_PMSR55 (0x00000020uL)
+#define GPIO_PMSR5_PMSR56 (0x00000040uL)
+#define GPIO_PMSR5_PMSR57 (0x00000080uL)
+#define GPIO_PMSR5_PMSR58 (0x00000100uL)
+#define GPIO_PMSR5_PMSR59 (0x00000200uL)
+#define GPIO_PMSR5_PMSR510 (0x00000400uL)
+#define GPIO_PMSR5_PMSR516 (0x00010000uL)
+#define GPIO_PMSR5_PMSR517 (0x00020000uL)
+#define GPIO_PMSR5_PMSR518 (0x00040000uL)
+#define GPIO_PMSR5_PMSR519 (0x00080000uL)
+#define GPIO_PMSR5_PMSR520 (0x00100000uL)
+#define GPIO_PMSR5_PMSR521 (0x00200000uL)
+#define GPIO_PMSR5_PMSR522 (0x00400000uL)
+#define GPIO_PMSR5_PMSR523 (0x00800000uL)
+#define GPIO_PMSR5_PMSR524 (0x01000000uL)
+#define GPIO_PMSR5_PMSR525 (0x02000000uL)
+#define GPIO_PMSR5_PMSR526 (0x04000000uL)
+
+#define GPIO_PMCSR5_PMCSR50 (0x00000001uL)
+#define GPIO_PMCSR5_PMCSR51 (0x00000002uL)
+#define GPIO_PMCSR5_PMCSR52 (0x00000004uL)
+#define GPIO_PMCSR5_PMCSR53 (0x00000008uL)
+#define GPIO_PMCSR5_PMCSR54 (0x00000010uL)
+#define GPIO_PMCSR5_PMCSR55 (0x00000020uL)
+#define GPIO_PMCSR5_PMCSR56 (0x00000040uL)
+#define GPIO_PMCSR5_PMCSR57 (0x00000080uL)
+#define GPIO_PMCSR5_PMCSR58 (0x00000100uL)
+#define GPIO_PMCSR5_PMCSR59 (0x00000200uL)
+#define GPIO_PMCSR5_PMCSR510 (0x00000400uL)
+#define GPIO_PMCSR5_PMCSR516 (0x00010000uL)
+#define GPIO_PMCSR5_PMCSR517 (0x00020000uL)
+#define GPIO_PMCSR5_PMCSR518 (0x00040000uL)
+#define GPIO_PMCSR5_PMCSR519 (0x00080000uL)
+#define GPIO_PMCSR5_PMCSR520 (0x00100000uL)
+#define GPIO_PMCSR5_PMCSR521 (0x00200000uL)
+#define GPIO_PMCSR5_PMCSR522 (0x00400000uL)
+#define GPIO_PMCSR5_PMCSR523 (0x00800000uL)
+#define GPIO_PMCSR5_PMCSR524 (0x01000000uL)
+#define GPIO_PMCSR5_PMCSR525 (0x02000000uL)
+#define GPIO_PMCSR5_PMCSR526 (0x04000000uL)
+
+#define GPIO_PFCAE5_PFCAE50 (0x0001u)
+#define GPIO_PFCAE5_PFCAE51 (0x0002u)
+#define GPIO_PFCAE5_PFCAE52 (0x0004u)
+#define GPIO_PFCAE5_PFCAE53 (0x0008u)
+#define GPIO_PFCAE5_PFCAE54 (0x0010u)
+#define GPIO_PFCAE5_PFCAE55 (0x0020u)
+#define GPIO_PFCAE5_PFCAE56 (0x0040u)
+#define GPIO_PFCAE5_PFCAE57 (0x0080u)
+#define GPIO_PFCAE5_PFCAE58 (0x0100u)
+#define GPIO_PFCAE5_PFCAE59 (0x0200u)
+#define GPIO_PFCAE5_PFCAE510 (0x0400u)
+
+#define GPIO_PIBC5_PIBC50 (0x0001u)
+#define GPIO_PIBC5_PIBC51 (0x0002u)
+#define GPIO_PIBC5_PIBC52 (0x0004u)
+#define GPIO_PIBC5_PIBC53 (0x0008u)
+#define GPIO_PIBC5_PIBC54 (0x0010u)
+#define GPIO_PIBC5_PIBC55 (0x0020u)
+#define GPIO_PIBC5_PIBC56 (0x0040u)
+#define GPIO_PIBC5_PIBC57 (0x0080u)
+#define GPIO_PIBC5_PIBC58 (0x0100u)
+#define GPIO_PIBC5_PIBC59 (0x0200u)
+#define GPIO_PIBC5_PIBC510 (0x0400u)
+
+#define GPIO_PBDC5_PBDC50 (0x0001u)
+#define GPIO_PBDC5_PBDC51 (0x0002u)
+#define GPIO_PBDC5_PBDC52 (0x0004u)
+#define GPIO_PBDC5_PBDC53 (0x0008u)
+#define GPIO_PBDC5_PBDC54 (0x0010u)
+#define GPIO_PBDC5_PBDC55 (0x0020u)
+#define GPIO_PBDC5_PBDC56 (0x0040u)
+#define GPIO_PBDC5_PBDC57 (0x0080u)
+#define GPIO_PBDC5_PBDC58 (0x0100u)
+#define GPIO_PBDC5_PBDC59 (0x0200u)
+#define GPIO_PBDC5_PBDC510 (0x0400u)
+
+#define GPIO_PIPC5_PIPC50 (0x0001u)
+#define GPIO_PIPC5_PIPC51 (0x0002u)
+#define GPIO_PIPC5_PIPC52 (0x0004u)
+#define GPIO_PIPC5_PIPC53 (0x0008u)
+#define GPIO_PIPC5_PIPC54 (0x0010u)
+#define GPIO_PIPC5_PIPC55 (0x0020u)
+#define GPIO_PIPC5_PIPC56 (0x0040u)
+#define GPIO_PIPC5_PIPC57 (0x0080u)
+#define GPIO_PIPC5_PIPC58 (0x0100u)
+#define GPIO_PIPC5_PIPC59 (0x0200u)
+#define GPIO_PIPC5_PIPC510 (0x0400u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60 (0x0001u)
+#define GPIO_P6_P61 (0x0002u)
+#define GPIO_P6_P62 (0x0004u)
+#define GPIO_P6_P63 (0x0008u)
+#define GPIO_P6_P64 (0x0010u)
+#define GPIO_P6_P65 (0x0020u)
+#define GPIO_P6_P66 (0x0040u)
+#define GPIO_P6_P67 (0x0080u)
+#define GPIO_P6_P68 (0x0100u)
+#define GPIO_P6_P69 (0x0200u)
+#define GPIO_P6_P610 (0x0400u)
+#define GPIO_P6_P611 (0x0800u)
+#define GPIO_P6_P612 (0x1000u)
+#define GPIO_P6_P613 (0x2000u)
+#define GPIO_P6_P614 (0x4000u)
+#define GPIO_P6_P615 (0x8000u)
+
+#define GPIO_PSR6_PSR60 (0x00000001uL)
+#define GPIO_PSR6_PSR61 (0x00000002uL)
+#define GPIO_PSR6_PSR62 (0x00000004uL)
+#define GPIO_PSR6_PSR63 (0x00000008uL)
+#define GPIO_PSR6_PSR64 (0x00000010uL)
+#define GPIO_PSR6_PSR65 (0x00000020uL)
+#define GPIO_PSR6_PSR66 (0x00000040uL)
+#define GPIO_PSR6_PSR67 (0x00000080uL)
+#define GPIO_PSR6_PSR68 (0x00000100uL)
+#define GPIO_PSR6_PSR69 (0x00000200uL)
+#define GPIO_PSR6_PSR610 (0x00000400uL)
+#define GPIO_PSR6_PSR611 (0x00000800uL)
+#define GPIO_PSR6_PSR612 (0x00001000uL)
+#define GPIO_PSR6_PSR613 (0x00002000uL)
+#define GPIO_PSR6_PSR614 (0x00004000uL)
+#define GPIO_PSR6_PSR615 (0x00008000uL)
+#define GPIO_PSR6_PSR616 (0x00010000uL)
+#define GPIO_PSR6_PSR617 (0x00020000uL)
+#define GPIO_PSR6_PSR618 (0x00040000uL)
+#define GPIO_PSR6_PSR619 (0x00080000uL)
+#define GPIO_PSR6_PSR620 (0x00100000uL)
+#define GPIO_PSR6_PSR621 (0x00200000uL)
+#define GPIO_PSR6_PSR622 (0x00400000uL)
+#define GPIO_PSR6_PSR623 (0x00800000uL)
+#define GPIO_PSR6_PSR624 (0x01000000uL)
+#define GPIO_PSR6_PSR625 (0x02000000uL)
+#define GPIO_PSR6_PSR626 (0x04000000uL)
+#define GPIO_PSR6_PSR627 (0x08000000uL)
+#define GPIO_PSR6_PSR628 (0x10000000uL)
+#define GPIO_PSR6_PSR629 (0x20000000uL)
+#define GPIO_PSR6_PSR630 (0x40000000uL)
+#define GPIO_PSR6_PSR631 (0x80000000uL)
+
+#define GPIO_PPR6_PPR60 (0x0001u)
+#define GPIO_PPR6_PPR61 (0x0002u)
+#define GPIO_PPR6_PPR62 (0x0004u)
+#define GPIO_PPR6_PPR63 (0x0008u)
+#define GPIO_PPR6_PPR64 (0x0010u)
+#define GPIO_PPR6_PPR65 (0x0020u)
+#define GPIO_PPR6_PPR66 (0x0040u)
+#define GPIO_PPR6_PPR67 (0x0080u)
+#define GPIO_PPR6_PPR68 (0x0100u)
+#define GPIO_PPR6_PPR69 (0x0200u)
+#define GPIO_PPR6_PPR610 (0x0400u)
+#define GPIO_PPR6_PPR611 (0x0800u)
+#define GPIO_PPR6_PPR612 (0x1000u)
+#define GPIO_PPR6_PPR613 (0x2000u)
+#define GPIO_PPR6_PPR614 (0x4000u)
+#define GPIO_PPR6_PPR615 (0x8000u)
+
+#define GPIO_PM6_PM60 (0x0001u)
+#define GPIO_PM6_PM61 (0x0002u)
+#define GPIO_PM6_PM62 (0x0004u)
+#define GPIO_PM6_PM63 (0x0008u)
+#define GPIO_PM6_PM64 (0x0010u)
+#define GPIO_PM6_PM65 (0x0020u)
+#define GPIO_PM6_PM66 (0x0040u)
+#define GPIO_PM6_PM67 (0x0080u)
+#define GPIO_PM6_PM68 (0x0100u)
+#define GPIO_PM6_PM69 (0x0200u)
+#define GPIO_PM6_PM610 (0x0400u)
+#define GPIO_PM6_PM611 (0x0800u)
+#define GPIO_PM6_PM612 (0x1000u)
+#define GPIO_PM6_PM613 (0x2000u)
+#define GPIO_PM6_PM614 (0x4000u)
+#define GPIO_PM6_PM615 (0x8000u)
+
+#define GPIO_PMC6_PMC60 (0x0001u)
+#define GPIO_PMC6_PMC61 (0x0002u)
+#define GPIO_PMC6_PMC62 (0x0004u)
+#define GPIO_PMC6_PMC63 (0x0008u)
+#define GPIO_PMC6_PMC64 (0x0010u)
+#define GPIO_PMC6_PMC65 (0x0020u)
+#define GPIO_PMC6_PMC66 (0x0040u)
+#define GPIO_PMC6_PMC67 (0x0080u)
+#define GPIO_PMC6_PMC68 (0x0100u)
+#define GPIO_PMC6_PMC69 (0x0200u)
+#define GPIO_PMC6_PMC610 (0x0400u)
+#define GPIO_PMC6_PMC611 (0x0800u)
+#define GPIO_PMC6_PMC612 (0x1000u)
+#define GPIO_PMC6_PMC613 (0x2000u)
+#define GPIO_PMC6_PMC614 (0x4000u)
+#define GPIO_PMC6_PMC615 (0x8000u)
+
+#define GPIO_PFC6_PFC60 (0x0001u)
+#define GPIO_PFC6_PFC61 (0x0002u)
+#define GPIO_PFC6_PFC62 (0x0004u)
+#define GPIO_PFC6_PFC63 (0x0008u)
+#define GPIO_PFC6_PFC64 (0x0010u)
+#define GPIO_PFC6_PFC65 (0x0020u)
+#define GPIO_PFC6_PFC66 (0x0040u)
+#define GPIO_PFC6_PFC67 (0x0080u)
+#define GPIO_PFC6_PFC68 (0x0100u)
+#define GPIO_PFC6_PFC69 (0x0200u)
+#define GPIO_PFC6_PFC610 (0x0400u)
+#define GPIO_PFC6_PFC611 (0x0800u)
+#define GPIO_PFC6_PFC612 (0x1000u)
+#define GPIO_PFC6_PFC613 (0x2000u)
+#define GPIO_PFC6_PFC614 (0x4000u)
+#define GPIO_PFC6_PFC615 (0x8000u)
+
+#define GPIO_PFCE6_PFCE60 (0x0001u)
+#define GPIO_PFCE6_PFCE61 (0x0002u)
+#define GPIO_PFCE6_PFCE62 (0x0004u)
+#define GPIO_PFCE6_PFCE63 (0x0008u)
+#define GPIO_PFCE6_PFCE64 (0x0010u)
+#define GPIO_PFCE6_PFCE65 (0x0020u)
+#define GPIO_PFCE6_PFCE66 (0x0040u)
+#define GPIO_PFCE6_PFCE67 (0x0080u)
+#define GPIO_PFCE6_PFCE68 (0x0100u)
+#define GPIO_PFCE6_PFCE69 (0x0200u)
+#define GPIO_PFCE6_PFCE610 (0x0400u)
+#define GPIO_PFCE6_PFCE611 (0x0800u)
+#define GPIO_PFCE6_PFCE612 (0x1000u)
+#define GPIO_PFCE6_PFCE613 (0x2000u)
+#define GPIO_PFCE6_PFCE614 (0x4000u)
+#define GPIO_PFCE6_PFCE615 (0x8000u)
+
+#define GPIO_PNOT6_PNOT60 (0x0001u)
+#define GPIO_PNOT6_PNOT61 (0x0002u)
+#define GPIO_PNOT6_PNOT62 (0x0004u)
+#define GPIO_PNOT6_PNOT63 (0x0008u)
+#define GPIO_PNOT6_PNOT64 (0x0010u)
+#define GPIO_PNOT6_PNOT65 (0x0020u)
+#define GPIO_PNOT6_PNOT66 (0x0040u)
+#define GPIO_PNOT6_PNOT67 (0x0080u)
+#define GPIO_PNOT6_PNOT68 (0x0100u)
+#define GPIO_PNOT6_PNOT69 (0x0200u)
+#define GPIO_PNOT6_PNOT610 (0x0400u)
+#define GPIO_PNOT6_PNOT611 (0x0800u)
+#define GPIO_PNOT6_PNOT612 (0x1000u)
+#define GPIO_PNOT6_PNOT613 (0x2000u)
+#define GPIO_PNOT6_PNOT614 (0x4000u)
+#define GPIO_PNOT6_PNOT615 (0x8000u)
+
+#define GPIO_PMSR6_PMSR60 (0x00000001uL)
+#define GPIO_PMSR6_PMSR61 (0x00000002uL)
+#define GPIO_PMSR6_PMSR62 (0x00000004uL)
+#define GPIO_PMSR6_PMSR63 (0x00000008uL)
+#define GPIO_PMSR6_PMSR64 (0x00000010uL)
+#define GPIO_PMSR6_PMSR65 (0x00000020uL)
+#define GPIO_PMSR6_PMSR66 (0x00000040uL)
+#define GPIO_PMSR6_PMSR67 (0x00000080uL)
+#define GPIO_PMSR6_PMSR68 (0x00000100uL)
+#define GPIO_PMSR6_PMSR69 (0x00000200uL)
+#define GPIO_PMSR6_PMSR610 (0x00000400uL)
+#define GPIO_PMSR6_PMSR611 (0x00000800uL)
+#define GPIO_PMSR6_PMSR612 (0x00001000uL)
+#define GPIO_PMSR6_PMSR613 (0x00002000uL)
+#define GPIO_PMSR6_PMSR614 (0x00004000uL)
+#define GPIO_PMSR6_PMSR615 (0x00008000uL)
+#define GPIO_PMSR6_PMSR616 (0x00010000uL)
+#define GPIO_PMSR6_PMSR617 (0x00020000uL)
+#define GPIO_PMSR6_PMSR618 (0x00040000uL)
+#define GPIO_PMSR6_PMSR619 (0x00080000uL)
+#define GPIO_PMSR6_PMSR620 (0x00100000uL)
+#define GPIO_PMSR6_PMSR621 (0x00200000uL)
+#define GPIO_PMSR6_PMSR622 (0x00400000uL)
+#define GPIO_PMSR6_PMSR623 (0x00800000uL)
+#define GPIO_PMSR6_PMSR624 (0x01000000uL)
+#define GPIO_PMSR6_PMSR625 (0x02000000uL)
+#define GPIO_PMSR6_PMSR626 (0x04000000uL)
+#define GPIO_PMSR6_PMSR627 (0x08000000uL)
+#define GPIO_PMSR6_PMSR628 (0x10000000uL)
+#define GPIO_PMSR6_PMSR629 (0x20000000uL)
+#define GPIO_PMSR6_PMSR630 (0x40000000uL)
+#define GPIO_PMSR6_PMSR631 (0x80000000uL)
+
+#define GPIO_PMCSR6_PMCSR60 (0x00000001uL)
+#define GPIO_PMCSR6_PMCSR61 (0x00000002uL)
+#define GPIO_PMCSR6_PMCSR62 (0x00000004uL)
+#define GPIO_PMCSR6_PMCSR63 (0x00000008uL)
+#define GPIO_PMCSR6_PMCSR64 (0x00000010uL)
+#define GPIO_PMCSR6_PMCSR65 (0x00000020uL)
+#define GPIO_PMCSR6_PMCSR66 (0x00000040uL)
+#define GPIO_PMCSR6_PMCSR67 (0x00000080uL)
+#define GPIO_PMCSR6_PMCSR68 (0x00000100uL)
+#define GPIO_PMCSR6_PMCSR69 (0x00000200uL)
+#define GPIO_PMCSR6_PMCSR610 (0x00000400uL)
+#define GPIO_PMCSR6_PMCSR611 (0x00000800uL)
+#define GPIO_PMCSR6_PMCSR612 (0x00001000uL)
+#define GPIO_PMCSR6_PMCSR613 (0x00002000uL)
+#define GPIO_PMCSR6_PMCSR614 (0x00004000uL)
+#define GPIO_PMCSR6_PMCSR615 (0x00008000uL)
+#define GPIO_PMCSR6_PMCSR616 (0x00010000uL)
+#define GPIO_PMCSR6_PMCSR617 (0x00020000uL)
+#define GPIO_PMCSR6_PMCSR618 (0x00040000uL)
+#define GPIO_PMCSR6_PMCSR619 (0x00080000uL)
+#define GPIO_PMCSR6_PMCSR620 (0x00100000uL)
+#define GPIO_PMCSR6_PMCSR621 (0x00200000uL)
+#define GPIO_PMCSR6_PMCSR622 (0x00400000uL)
+#define GPIO_PMCSR6_PMCSR623 (0x00800000uL)
+#define GPIO_PMCSR6_PMCSR624 (0x01000000uL)
+#define GPIO_PMCSR6_PMCSR625 (0x02000000uL)
+#define GPIO_PMCSR6_PMCSR626 (0x04000000uL)
+#define GPIO_PMCSR6_PMCSR627 (0x08000000uL)
+#define GPIO_PMCSR6_PMCSR628 (0x10000000uL)
+#define GPIO_PMCSR6_PMCSR629 (0x20000000uL)
+#define GPIO_PMCSR6_PMCSR630 (0x40000000uL)
+#define GPIO_PMCSR6_PMCSR631 (0x80000000uL)
+
+#define GPIO_PFCAE6_PFCAE60 (0x0001u)
+#define GPIO_PFCAE6_PFCAE61 (0x0002u)
+#define GPIO_PFCAE6_PFCAE62 (0x0004u)
+#define GPIO_PFCAE6_PFCAE63 (0x0008u)
+#define GPIO_PFCAE6_PFCAE64 (0x0010u)
+#define GPIO_PFCAE6_PFCAE65 (0x0020u)
+#define GPIO_PFCAE6_PFCAE66 (0x0040u)
+#define GPIO_PFCAE6_PFCAE67 (0x0080u)
+#define GPIO_PFCAE6_PFCAE68 (0x0100u)
+#define GPIO_PFCAE6_PFCAE69 (0x0200u)
+#define GPIO_PFCAE6_PFCAE610 (0x0400u)
+#define GPIO_PFCAE6_PFCAE611 (0x0800u)
+#define GPIO_PFCAE6_PFCAE612 (0x1000u)
+#define GPIO_PFCAE6_PFCAE613 (0x2000u)
+#define GPIO_PFCAE6_PFCAE614 (0x4000u)
+#define GPIO_PFCAE6_PFCAE615 (0x8000u)
+
+#define GPIO_PIBC6_PIBC60 (0x0001u)
+#define GPIO_PIBC6_PIBC61 (0x0002u)
+#define GPIO_PIBC6_PIBC62 (0x0004u)
+#define GPIO_PIBC6_PIBC63 (0x0008u)
+#define GPIO_PIBC6_PIBC64 (0x0010u)
+#define GPIO_PIBC6_PIBC65 (0x0020u)
+#define GPIO_PIBC6_PIBC66 (0x0040u)
+#define GPIO_PIBC6_PIBC67 (0x0080u)
+#define GPIO_PIBC6_PIBC68 (0x0100u)
+#define GPIO_PIBC6_PIBC69 (0x0200u)
+#define GPIO_PIBC6_PIBC610 (0x0400u)
+#define GPIO_PIBC6_PIBC611 (0x0800u)
+#define GPIO_PIBC6_PIBC612 (0x1000u)
+#define GPIO_PIBC6_PIBC613 (0x2000u)
+#define GPIO_PIBC6_PIBC614 (0x4000u)
+#define GPIO_PIBC6_PIBC615 (0x8000u)
+
+#define GPIO_PBDC6_PBDC60 (0x0001u)
+#define GPIO_PBDC6_PBDC61 (0x0002u)
+#define GPIO_PBDC6_PBDC62 (0x0004u)
+#define GPIO_PBDC6_PBDC63 (0x0008u)
+#define GPIO_PBDC6_PBDC64 (0x0010u)
+#define GPIO_PBDC6_PBDC65 (0x0020u)
+#define GPIO_PBDC6_PBDC66 (0x0040u)
+#define GPIO_PBDC6_PBDC67 (0x0080u)
+#define GPIO_PBDC6_PBDC68 (0x0100u)
+#define GPIO_PBDC6_PBDC69 (0x0200u)
+#define GPIO_PBDC6_PBDC610 (0x0400u)
+#define GPIO_PBDC6_PBDC611 (0x0800u)
+#define GPIO_PBDC6_PBDC612 (0x1000u)
+#define GPIO_PBDC6_PBDC613 (0x2000u)
+#define GPIO_PBDC6_PBDC614 (0x4000u)
+#define GPIO_PBDC6_PBDC615 (0x8000u)
+
+#define GPIO_PIPC6_PIPC60 (0x0001u)
+#define GPIO_PIPC6_PIPC61 (0x0002u)
+#define GPIO_PIPC6_PIPC62 (0x0004u)
+#define GPIO_PIPC6_PIPC63 (0x0008u)
+#define GPIO_PIPC6_PIPC64 (0x0010u)
+#define GPIO_PIPC6_PIPC65 (0x0020u)
+#define GPIO_PIPC6_PIPC66 (0x0040u)
+#define GPIO_PIPC6_PIPC67 (0x0080u)
+#define GPIO_PIPC6_PIPC68 (0x0100u)
+#define GPIO_PIPC6_PIPC69 (0x0200u)
+#define GPIO_PIPC6_PIPC610 (0x0400u)
+#define GPIO_PIPC6_PIPC611 (0x0800u)
+#define GPIO_PIPC6_PIPC612 (0x1000u)
+#define GPIO_PIPC6_PIPC613 (0x2000u)
+#define GPIO_PIPC6_PIPC614 (0x4000u)
+#define GPIO_PIPC6_PIPC615 (0x8000u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70 (0x0001u)
+#define GPIO_P7_P71 (0x0002u)
+#define GPIO_P7_P72 (0x0004u)
+#define GPIO_P7_P73 (0x0008u)
+#define GPIO_P7_P74 (0x0010u)
+#define GPIO_P7_P75 (0x0020u)
+#define GPIO_P7_P76 (0x0040u)
+#define GPIO_P7_P77 (0x0080u)
+#define GPIO_P7_P78 (0x0100u)
+#define GPIO_P7_P79 (0x0200u)
+#define GPIO_P7_P710 (0x0400u)
+#define GPIO_P7_P711 (0x0800u)
+#define GPIO_P7_P712 (0x1000u)
+#define GPIO_P7_P713 (0x2000u)
+#define GPIO_P7_P714 (0x4000u)
+#define GPIO_P7_P715 (0x8000u)
+
+#define GPIO_PSR7_PSR70 (0x00000001uL)
+#define GPIO_PSR7_PSR71 (0x00000002uL)
+#define GPIO_PSR7_PSR72 (0x00000004uL)
+#define GPIO_PSR7_PSR73 (0x00000008uL)
+#define GPIO_PSR7_PSR74 (0x00000010uL)
+#define GPIO_PSR7_PSR75 (0x00000020uL)
+#define GPIO_PSR7_PSR76 (0x00000040uL)
+#define GPIO_PSR7_PSR77 (0x00000080uL)
+#define GPIO_PSR7_PSR78 (0x00000100uL)
+#define GPIO_PSR7_PSR79 (0x00000200uL)
+#define GPIO_PSR7_PSR710 (0x00000400uL)
+#define GPIO_PSR7_PSR711 (0x00000800uL)
+#define GPIO_PSR7_PSR712 (0x00001000uL)
+#define GPIO_PSR7_PSR713 (0x00002000uL)
+#define GPIO_PSR7_PSR714 (0x00004000uL)
+#define GPIO_PSR7_PSR715 (0x00008000uL)
+#define GPIO_PSR7_PSR716 (0x00010000uL)
+#define GPIO_PSR7_PSR717 (0x00020000uL)
+#define GPIO_PSR7_PSR718 (0x00040000uL)
+#define GPIO_PSR7_PSR719 (0x00080000uL)
+#define GPIO_PSR7_PSR720 (0x00100000uL)
+#define GPIO_PSR7_PSR721 (0x00200000uL)
+#define GPIO_PSR7_PSR722 (0x00400000uL)
+#define GPIO_PSR7_PSR723 (0x00800000uL)
+#define GPIO_PSR7_PSR724 (0x01000000uL)
+#define GPIO_PSR7_PSR725 (0x02000000uL)
+#define GPIO_PSR7_PSR726 (0x04000000uL)
+#define GPIO_PSR7_PSR727 (0x08000000uL)
+#define GPIO_PSR7_PSR728 (0x10000000uL)
+#define GPIO_PSR7_PSR729 (0x20000000uL)
+#define GPIO_PSR7_PSR730 (0x40000000uL)
+#define GPIO_PSR7_PSR731 (0x80000000uL)
+
+#define GPIO_PPR7_PPR70 (0x0001u)
+#define GPIO_PPR7_PPR71 (0x0002u)
+#define GPIO_PPR7_PPR72 (0x0004u)
+#define GPIO_PPR7_PPR73 (0x0008u)
+#define GPIO_PPR7_PPR74 (0x0010u)
+#define GPIO_PPR7_PPR75 (0x0020u)
+#define GPIO_PPR7_PPR76 (0x0040u)
+#define GPIO_PPR7_PPR77 (0x0080u)
+#define GPIO_PPR7_PPR78 (0x0100u)
+#define GPIO_PPR7_PPR79 (0x0200u)
+#define GPIO_PPR7_PPR710 (0x0400u)
+#define GPIO_PPR7_PPR711 (0x0800u)
+#define GPIO_PPR7_PPR712 (0x1000u)
+#define GPIO_PPR7_PPR713 (0x2000u)
+#define GPIO_PPR7_PPR714 (0x4000u)
+#define GPIO_PPR7_PPR715 (0x8000u)
+
+#define GPIO_PM7_PM70 (0x0001u)
+#define GPIO_PM7_PM71 (0x0002u)
+#define GPIO_PM7_PM72 (0x0004u)
+#define GPIO_PM7_PM73 (0x0008u)
+#define GPIO_PM7_PM74 (0x0010u)
+#define GPIO_PM7_PM75 (0x0020u)
+#define GPIO_PM7_PM76 (0x0040u)
+#define GPIO_PM7_PM77 (0x0080u)
+#define GPIO_PM7_PM78 (0x0100u)
+#define GPIO_PM7_PM79 (0x0200u)
+#define GPIO_PM7_PM710 (0x0400u)
+#define GPIO_PM7_PM711 (0x0800u)
+#define GPIO_PM7_PM712 (0x1000u)
+#define GPIO_PM7_PM713 (0x2000u)
+#define GPIO_PM7_PM714 (0x4000u)
+#define GPIO_PM7_PM715 (0x8000u)
+
+#define GPIO_PMC7_PMC70 (0x0001u)
+#define GPIO_PMC7_PMC71 (0x0002u)
+#define GPIO_PMC7_PMC72 (0x0004u)
+#define GPIO_PMC7_PMC73 (0x0008u)
+#define GPIO_PMC7_PMC74 (0x0010u)
+#define GPIO_PMC7_PMC75 (0x0020u)
+#define GPIO_PMC7_PMC76 (0x0040u)
+#define GPIO_PMC7_PMC77 (0x0080u)
+#define GPIO_PMC7_PMC78 (0x0100u)
+#define GPIO_PMC7_PMC79 (0x0200u)
+#define GPIO_PMC7_PMC710 (0x0400u)
+#define GPIO_PMC7_PMC711 (0x0800u)
+#define GPIO_PMC7_PMC712 (0x1000u)
+#define GPIO_PMC7_PMC713 (0x2000u)
+#define GPIO_PMC7_PMC714 (0x4000u)
+#define GPIO_PMC7_PMC715 (0x8000u)
+
+#define GPIO_PFC7_PFC70 (0x0001u)
+#define GPIO_PFC7_PFC71 (0x0002u)
+#define GPIO_PFC7_PFC72 (0x0004u)
+#define GPIO_PFC7_PFC73 (0x0008u)
+#define GPIO_PFC7_PFC74 (0x0010u)
+#define GPIO_PFC7_PFC75 (0x0020u)
+#define GPIO_PFC7_PFC76 (0x0040u)
+#define GPIO_PFC7_PFC77 (0x0080u)
+#define GPIO_PFC7_PFC78 (0x0100u)
+#define GPIO_PFC7_PFC79 (0x0200u)
+#define GPIO_PFC7_PFC710 (0x0400u)
+#define GPIO_PFC7_PFC711 (0x0800u)
+#define GPIO_PFC7_PFC712 (0x1000u)
+#define GPIO_PFC7_PFC713 (0x2000u)
+#define GPIO_PFC7_PFC714 (0x4000u)
+#define GPIO_PFC7_PFC715 (0x8000u)
+
+#define GPIO_PFCE7_PFCE70 (0x0001u)
+#define GPIO_PFCE7_PFCE71 (0x0002u)
+#define GPIO_PFCE7_PFCE72 (0x0004u)
+#define GPIO_PFCE7_PFCE73 (0x0008u)
+#define GPIO_PFCE7_PFCE74 (0x0010u)
+#define GPIO_PFCE7_PFCE75 (0x0020u)
+#define GPIO_PFCE7_PFCE76 (0x0040u)
+#define GPIO_PFCE7_PFCE77 (0x0080u)
+#define GPIO_PFCE7_PFCE78 (0x0100u)
+#define GPIO_PFCE7_PFCE79 (0x0200u)
+#define GPIO_PFCE7_PFCE710 (0x0400u)
+#define GPIO_PFCE7_PFCE711 (0x0800u)
+#define GPIO_PFCE7_PFCE712 (0x1000u)
+#define GPIO_PFCE7_PFCE713 (0x2000u)
+#define GPIO_PFCE7_PFCE714 (0x4000u)
+#define GPIO_PFCE7_PFCE715 (0x8000u)
+
+#define GPIO_PNOT7_PNOT70 (0x0001u)
+#define GPIO_PNOT7_PNOT71 (0x0002u)
+#define GPIO_PNOT7_PNOT72 (0x0004u)
+#define GPIO_PNOT7_PNOT73 (0x0008u)
+#define GPIO_PNOT7_PNOT74 (0x0010u)
+#define GPIO_PNOT7_PNOT75 (0x0020u)
+#define GPIO_PNOT7_PNOT76 (0x0040u)
+#define GPIO_PNOT7_PNOT77 (0x0080u)
+#define GPIO_PNOT7_PNOT78 (0x0100u)
+#define GPIO_PNOT7_PNOT79 (0x0200u)
+#define GPIO_PNOT7_PNOT710 (0x0400u)
+#define GPIO_PNOT7_PNOT711 (0x0800u)
+#define GPIO_PNOT7_PNOT712 (0x1000u)
+#define GPIO_PNOT7_PNOT713 (0x2000u)
+#define GPIO_PNOT7_PNOT714 (0x4000u)
+#define GPIO_PNOT7_PNOT715 (0x8000u)
+
+#define GPIO_PMSR7_PMSR70 (0x00000001uL)
+#define GPIO_PMSR7_PMSR71 (0x00000002uL)
+#define GPIO_PMSR7_PMSR72 (0x00000004uL)
+#define GPIO_PMSR7_PMSR73 (0x00000008uL)
+#define GPIO_PMSR7_PMSR74 (0x00000010uL)
+#define GPIO_PMSR7_PMSR75 (0x00000020uL)
+#define GPIO_PMSR7_PMSR76 (0x00000040uL)
+#define GPIO_PMSR7_PMSR77 (0x00000080uL)
+#define GPIO_PMSR7_PMSR78 (0x00000100uL)
+#define GPIO_PMSR7_PMSR79 (0x00000200uL)
+#define GPIO_PMSR7_PMSR710 (0x00000400uL)
+#define GPIO_PMSR7_PMSR711 (0x00000800uL)
+#define GPIO_PMSR7_PMSR712 (0x00001000uL)
+#define GPIO_PMSR7_PMSR713 (0x00002000uL)
+#define GPIO_PMSR7_PMSR714 (0x00004000uL)
+#define GPIO_PMSR7_PMSR715 (0x00008000uL)
+#define GPIO_PMSR7_PMSR716 (0x00010000uL)
+#define GPIO_PMSR7_PMSR717 (0x00020000uL)
+#define GPIO_PMSR7_PMSR718 (0x00040000uL)
+#define GPIO_PMSR7_PMSR719 (0x00080000uL)
+#define GPIO_PMSR7_PMSR720 (0x00100000uL)
+#define GPIO_PMSR7_PMSR721 (0x00200000uL)
+#define GPIO_PMSR7_PMSR722 (0x00400000uL)
+#define GPIO_PMSR7_PMSR723 (0x00800000uL)
+#define GPIO_PMSR7_PMSR724 (0x01000000uL)
+#define GPIO_PMSR7_PMSR725 (0x02000000uL)
+#define GPIO_PMSR7_PMSR726 (0x04000000uL)
+#define GPIO_PMSR7_PMSR727 (0x08000000uL)
+#define GPIO_PMSR7_PMSR728 (0x10000000uL)
+#define GPIO_PMSR7_PMSR729 (0x20000000uL)
+#define GPIO_PMSR7_PMSR730 (0x40000000uL)
+#define GPIO_PMSR7_PMSR731 (0x80000000uL)
+
+#define GPIO_PMCSR7_PMCSR70 (0x00000001uL)
+#define GPIO_PMCSR7_PMCSR71 (0x00000002uL)
+#define GPIO_PMCSR7_PMCSR72 (0x00000004uL)
+#define GPIO_PMCSR7_PMCSR73 (0x00000008uL)
+#define GPIO_PMCSR7_PMCSR74 (0x00000010uL)
+#define GPIO_PMCSR7_PMCSR75 (0x00000020uL)
+#define GPIO_PMCSR7_PMCSR76 (0x00000040uL)
+#define GPIO_PMCSR7_PMCSR77 (0x00000080uL)
+#define GPIO_PMCSR7_PMCSR78 (0x00000100uL)
+#define GPIO_PMCSR7_PMCSR79 (0x00000200uL)
+#define GPIO_PMCSR7_PMCSR710 (0x00000400uL)
+#define GPIO_PMCSR7_PMCSR711 (0x00000800uL)
+#define GPIO_PMCSR7_PMCSR712 (0x00001000uL)
+#define GPIO_PMCSR7_PMCSR713 (0x00002000uL)
+#define GPIO_PMCSR7_PMCSR714 (0x00004000uL)
+#define GPIO_PMCSR7_PMCSR715 (0x00008000uL)
+#define GPIO_PMCSR7_PMCSR716 (0x00010000uL)
+#define GPIO_PMCSR7_PMCSR717 (0x00020000uL)
+#define GPIO_PMCSR7_PMCSR718 (0x00040000uL)
+#define GPIO_PMCSR7_PMCSR719 (0x00080000uL)
+#define GPIO_PMCSR7_PMCSR720 (0x00100000uL)
+#define GPIO_PMCSR7_PMCSR721 (0x00200000uL)
+#define GPIO_PMCSR7_PMCSR722 (0x00400000uL)
+#define GPIO_PMCSR7_PMCSR723 (0x00800000uL)
+#define GPIO_PMCSR7_PMCSR724 (0x01000000uL)
+#define GPIO_PMCSR7_PMCSR725 (0x02000000uL)
+#define GPIO_PMCSR7_PMCSR726 (0x04000000uL)
+#define GPIO_PMCSR7_PMCSR727 (0x08000000uL)
+#define GPIO_PMCSR7_PMCSR728 (0x10000000uL)
+#define GPIO_PMCSR7_PMCSR729 (0x20000000uL)
+#define GPIO_PMCSR7_PMCSR730 (0x40000000uL)
+#define GPIO_PMCSR7_PMCSR731 (0x80000000uL)
+
+#define GPIO_PFCAE7_PFCAE70 (0x0001u)
+#define GPIO_PFCAE7_PFCAE71 (0x0002u)
+#define GPIO_PFCAE7_PFCAE72 (0x0004u)
+#define GPIO_PFCAE7_PFCAE73 (0x0008u)
+#define GPIO_PFCAE7_PFCAE74 (0x0010u)
+#define GPIO_PFCAE7_PFCAE75 (0x0020u)
+#define GPIO_PFCAE7_PFCAE76 (0x0040u)
+#define GPIO_PFCAE7_PFCAE77 (0x0080u)
+#define GPIO_PFCAE7_PFCAE78 (0x0100u)
+#define GPIO_PFCAE7_PFCAE79 (0x0200u)
+#define GPIO_PFCAE7_PFCAE710 (0x0400u)
+#define GPIO_PFCAE7_PFCAE711 (0x0800u)
+#define GPIO_PFCAE7_PFCAE712 (0x1000u)
+#define GPIO_PFCAE7_PFCAE713 (0x2000u)
+#define GPIO_PFCAE7_PFCAE714 (0x4000u)
+#define GPIO_PFCAE7_PFCAE715 (0x8000u)
+
+#define GPIO_PIBC7_PIBC70 (0x0001u)
+#define GPIO_PIBC7_PIBC71 (0x0002u)
+#define GPIO_PIBC7_PIBC72 (0x0004u)
+#define GPIO_PIBC7_PIBC73 (0x0008u)
+#define GPIO_PIBC7_PIBC74 (0x0010u)
+#define GPIO_PIBC7_PIBC75 (0x0020u)
+#define GPIO_PIBC7_PIBC76 (0x0040u)
+#define GPIO_PIBC7_PIBC77 (0x0080u)
+#define GPIO_PIBC7_PIBC78 (0x0100u)
+#define GPIO_PIBC7_PIBC79 (0x0200u)
+#define GPIO_PIBC7_PIBC710 (0x0400u)
+#define GPIO_PIBC7_PIBC711 (0x0800u)
+#define GPIO_PIBC7_PIBC712 (0x1000u)
+#define GPIO_PIBC7_PIBC713 (0x2000u)
+#define GPIO_PIBC7_PIBC714 (0x4000u)
+#define GPIO_PIBC7_PIBC715 (0x8000u)
+
+#define GPIO_PBDC7_PBDC70 (0x0001u)
+#define GPIO_PBDC7_PBDC71 (0x0002u)
+#define GPIO_PBDC7_PBDC72 (0x0004u)
+#define GPIO_PBDC7_PBDC73 (0x0008u)
+#define GPIO_PBDC7_PBDC74 (0x0010u)
+#define GPIO_PBDC7_PBDC75 (0x0020u)
+#define GPIO_PBDC7_PBDC76 (0x0040u)
+#define GPIO_PBDC7_PBDC77 (0x0080u)
+#define GPIO_PBDC7_PBDC78 (0x0100u)
+#define GPIO_PBDC7_PBDC79 (0x0200u)
+#define GPIO_PBDC7_PBDC710 (0x0400u)
+#define GPIO_PBDC7_PBDC711 (0x0800u)
+#define GPIO_PBDC7_PBDC712 (0x1000u)
+#define GPIO_PBDC7_PBDC713 (0x2000u)
+#define GPIO_PBDC7_PBDC714 (0x4000u)
+#define GPIO_PBDC7_PBDC715 (0x8000u)
+
+#define GPIO_PIPC7_PIPC70 (0x0001u)
+#define GPIO_PIPC7_PIPC71 (0x0002u)
+#define GPIO_PIPC7_PIPC72 (0x0004u)
+#define GPIO_PIPC7_PIPC73 (0x0008u)
+#define GPIO_PIPC7_PIPC74 (0x0010u)
+#define GPIO_PIPC7_PIPC75 (0x0020u)
+#define GPIO_PIPC7_PIPC76 (0x0040u)
+#define GPIO_PIPC7_PIPC77 (0x0080u)
+#define GPIO_PIPC7_PIPC78 (0x0100u)
+#define GPIO_PIPC7_PIPC79 (0x0200u)
+#define GPIO_PIPC7_PIPC710 (0x0400u)
+#define GPIO_PIPC7_PIPC711 (0x0800u)
+#define GPIO_PIPC7_PIPC712 (0x1000u)
+#define GPIO_PIPC7_PIPC713 (0x2000u)
+#define GPIO_PIPC7_PIPC714 (0x4000u)
+#define GPIO_PIPC7_PIPC715 (0x8000u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80 (0x0001u)
+#define GPIO_P8_P81 (0x0002u)
+#define GPIO_P8_P82 (0x0004u)
+#define GPIO_P8_P83 (0x0008u)
+#define GPIO_P8_P84 (0x0010u)
+#define GPIO_P8_P85 (0x0020u)
+#define GPIO_P8_P86 (0x0040u)
+#define GPIO_P8_P87 (0x0080u)
+#define GPIO_P8_P88 (0x0100u)
+#define GPIO_P8_P89 (0x0200u)
+#define GPIO_P8_P810 (0x0400u)
+#define GPIO_P8_P811 (0x0800u)
+#define GPIO_P8_P812 (0x1000u)
+#define GPIO_P8_P813 (0x2000u)
+#define GPIO_P8_P814 (0x4000u)
+#define GPIO_P8_P815 (0x8000u)
+
+#define GPIO_PSR8_PSR80 (0x00000001uL)
+#define GPIO_PSR8_PSR81 (0x00000002uL)
+#define GPIO_PSR8_PSR82 (0x00000004uL)
+#define GPIO_PSR8_PSR83 (0x00000008uL)
+#define GPIO_PSR8_PSR84 (0x00000010uL)
+#define GPIO_PSR8_PSR85 (0x00000020uL)
+#define GPIO_PSR8_PSR86 (0x00000040uL)
+#define GPIO_PSR8_PSR87 (0x00000080uL)
+#define GPIO_PSR8_PSR88 (0x00000100uL)
+#define GPIO_PSR8_PSR89 (0x00000200uL)
+#define GPIO_PSR8_PSR810 (0x00000400uL)
+#define GPIO_PSR8_PSR811 (0x00000800uL)
+#define GPIO_PSR8_PSR812 (0x00001000uL)
+#define GPIO_PSR8_PSR813 (0x00002000uL)
+#define GPIO_PSR8_PSR814 (0x00004000uL)
+#define GPIO_PSR8_PSR815 (0x00008000uL)
+#define GPIO_PSR8_PSR816 (0x00010000uL)
+#define GPIO_PSR8_PSR817 (0x00020000uL)
+#define GPIO_PSR8_PSR818 (0x00040000uL)
+#define GPIO_PSR8_PSR819 (0x00080000uL)
+#define GPIO_PSR8_PSR820 (0x00100000uL)
+#define GPIO_PSR8_PSR821 (0x00200000uL)
+#define GPIO_PSR8_PSR822 (0x00400000uL)
+#define GPIO_PSR8_PSR823 (0x00800000uL)
+#define GPIO_PSR8_PSR824 (0x01000000uL)
+#define GPIO_PSR8_PSR825 (0x02000000uL)
+#define GPIO_PSR8_PSR826 (0x04000000uL)
+#define GPIO_PSR8_PSR827 (0x08000000uL)
+#define GPIO_PSR8_PSR828 (0x10000000uL)
+#define GPIO_PSR8_PSR829 (0x20000000uL)
+#define GPIO_PSR8_PSR830 (0x40000000uL)
+#define GPIO_PSR8_PSR831 (0x80000000uL)
+
+#define GPIO_PPR8_PPR80 (0x0001u)
+#define GPIO_PPR8_PPR81 (0x0002u)
+#define GPIO_PPR8_PPR82 (0x0004u)
+#define GPIO_PPR8_PPR83 (0x0008u)
+#define GPIO_PPR8_PPR84 (0x0010u)
+#define GPIO_PPR8_PPR85 (0x0020u)
+#define GPIO_PPR8_PPR86 (0x0040u)
+#define GPIO_PPR8_PPR87 (0x0080u)
+#define GPIO_PPR8_PPR88 (0x0100u)
+#define GPIO_PPR8_PPR89 (0x0200u)
+#define GPIO_PPR8_PPR810 (0x0400u)
+#define GPIO_PPR8_PPR811 (0x0800u)
+#define GPIO_PPR8_PPR812 (0x1000u)
+#define GPIO_PPR8_PPR813 (0x2000u)
+#define GPIO_PPR8_PPR814 (0x4000u)
+#define GPIO_PPR8_PPR815 (0x8000u)
+
+#define GPIO_PM8_PM80 (0x0001u)
+#define GPIO_PM8_PM81 (0x0002u)
+#define GPIO_PM8_PM82 (0x0004u)
+#define GPIO_PM8_PM83 (0x0008u)
+#define GPIO_PM8_PM84 (0x0010u)
+#define GPIO_PM8_PM85 (0x0020u)
+#define GPIO_PM8_PM86 (0x0040u)
+#define GPIO_PM8_PM87 (0x0080u)
+#define GPIO_PM8_PM88 (0x0100u)
+#define GPIO_PM8_PM89 (0x0200u)
+#define GPIO_PM8_PM810 (0x0400u)
+#define GPIO_PM8_PM811 (0x0800u)
+#define GPIO_PM8_PM812 (0x1000u)
+#define GPIO_PM8_PM813 (0x2000u)
+#define GPIO_PM8_PM814 (0x4000u)
+#define GPIO_PM8_PM815 (0x8000u)
+
+#define GPIO_PMC8_PMC80 (0x0001u)
+#define GPIO_PMC8_PMC81 (0x0002u)
+#define GPIO_PMC8_PMC82 (0x0004u)
+#define GPIO_PMC8_PMC83 (0x0008u)
+#define GPIO_PMC8_PMC84 (0x0010u)
+#define GPIO_PMC8_PMC85 (0x0020u)
+#define GPIO_PMC8_PMC86 (0x0040u)
+#define GPIO_PMC8_PMC87 (0x0080u)
+#define GPIO_PMC8_PMC88 (0x0100u)
+#define GPIO_PMC8_PMC89 (0x0200u)
+#define GPIO_PMC8_PMC810 (0x0400u)
+#define GPIO_PMC8_PMC811 (0x0800u)
+#define GPIO_PMC8_PMC812 (0x1000u)
+#define GPIO_PMC8_PMC813 (0x2000u)
+#define GPIO_PMC8_PMC814 (0x4000u)
+#define GPIO_PMC8_PMC815 (0x8000u)
+
+#define GPIO_PFC8_PFC80 (0x0001u)
+#define GPIO_PFC8_PFC81 (0x0002u)
+#define GPIO_PFC8_PFC82 (0x0004u)
+#define GPIO_PFC8_PFC83 (0x0008u)
+#define GPIO_PFC8_PFC84 (0x0010u)
+#define GPIO_PFC8_PFC85 (0x0020u)
+#define GPIO_PFC8_PFC86 (0x0040u)
+#define GPIO_PFC8_PFC87 (0x0080u)
+#define GPIO_PFC8_PFC88 (0x0100u)
+#define GPIO_PFC8_PFC89 (0x0200u)
+#define GPIO_PFC8_PFC810 (0x0400u)
+#define GPIO_PFC8_PFC811 (0x0800u)
+#define GPIO_PFC8_PFC812 (0x1000u)
+#define GPIO_PFC8_PFC813 (0x2000u)
+#define GPIO_PFC8_PFC814 (0x4000u)
+#define GPIO_PFC8_PFC815 (0x8000u)
+
+#define GPIO_PFCE8_PFCE80 (0x0001u)
+#define GPIO_PFCE8_PFCE81 (0x0002u)
+#define GPIO_PFCE8_PFCE82 (0x0004u)
+#define GPIO_PFCE8_PFCE83 (0x0008u)
+#define GPIO_PFCE8_PFCE84 (0x0010u)
+#define GPIO_PFCE8_PFCE85 (0x0020u)
+#define GPIO_PFCE8_PFCE86 (0x0040u)
+#define GPIO_PFCE8_PFCE87 (0x0080u)
+#define GPIO_PFCE8_PFCE88 (0x0100u)
+#define GPIO_PFCE8_PFCE89 (0x0200u)
+#define GPIO_PFCE8_PFCE810 (0x0400u)
+#define GPIO_PFCE8_PFCE811 (0x0800u)
+#define GPIO_PFCE8_PFCE812 (0x1000u)
+#define GPIO_PFCE8_PFCE813 (0x2000u)
+#define GPIO_PFCE8_PFCE814 (0x4000u)
+#define GPIO_PFCE8_PFCE815 (0x8000u)
+
+#define GPIO_PNOT8_PNOT80 (0x0001u)
+#define GPIO_PNOT8_PNOT81 (0x0002u)
+#define GPIO_PNOT8_PNOT82 (0x0004u)
+#define GPIO_PNOT8_PNOT83 (0x0008u)
+#define GPIO_PNOT8_PNOT84 (0x0010u)
+#define GPIO_PNOT8_PNOT85 (0x0020u)
+#define GPIO_PNOT8_PNOT86 (0x0040u)
+#define GPIO_PNOT8_PNOT87 (0x0080u)
+#define GPIO_PNOT8_PNOT88 (0x0100u)
+#define GPIO_PNOT8_PNOT89 (0x0200u)
+#define GPIO_PNOT8_PNOT810 (0x0400u)
+#define GPIO_PNOT8_PNOT811 (0x0800u)
+#define GPIO_PNOT8_PNOT812 (0x1000u)
+#define GPIO_PNOT8_PNOT813 (0x2000u)
+#define GPIO_PNOT8_PNOT814 (0x4000u)
+#define GPIO_PNOT8_PNOT815 (0x8000u)
+
+#define GPIO_PMSR8_PMSR80 (0x00000001uL)
+#define GPIO_PMSR8_PMSR81 (0x00000002uL)
+#define GPIO_PMSR8_PMSR82 (0x00000004uL)
+#define GPIO_PMSR8_PMSR83 (0x00000008uL)
+#define GPIO_PMSR8_PMSR84 (0x00000010uL)
+#define GPIO_PMSR8_PMSR85 (0x00000020uL)
+#define GPIO_PMSR8_PMSR86 (0x00000040uL)
+#define GPIO_PMSR8_PMSR87 (0x00000080uL)
+#define GPIO_PMSR8_PMSR88 (0x00000100uL)
+#define GPIO_PMSR8_PMSR89 (0x00000200uL)
+#define GPIO_PMSR8_PMSR810 (0x00000400uL)
+#define GPIO_PMSR8_PMSR811 (0x00000800uL)
+#define GPIO_PMSR8_PMSR812 (0x00001000uL)
+#define GPIO_PMSR8_PMSR813 (0x00002000uL)
+#define GPIO_PMSR8_PMSR814 (0x00004000uL)
+#define GPIO_PMSR8_PMSR815 (0x00008000uL)
+#define GPIO_PMSR8_PMSR816 (0x00010000uL)
+#define GPIO_PMSR8_PMSR817 (0x00020000uL)
+#define GPIO_PMSR8_PMSR818 (0x00040000uL)
+#define GPIO_PMSR8_PMSR819 (0x00080000uL)
+#define GPIO_PMSR8_PMSR820 (0x00100000uL)
+#define GPIO_PMSR8_PMSR821 (0x00200000uL)
+#define GPIO_PMSR8_PMSR822 (0x00400000uL)
+#define GPIO_PMSR8_PMSR823 (0x00800000uL)
+#define GPIO_PMSR8_PMSR824 (0x01000000uL)
+#define GPIO_PMSR8_PMSR825 (0x02000000uL)
+#define GPIO_PMSR8_PMSR826 (0x04000000uL)
+#define GPIO_PMSR8_PMSR827 (0x08000000uL)
+#define GPIO_PMSR8_PMSR828 (0x10000000uL)
+#define GPIO_PMSR8_PMSR829 (0x20000000uL)
+#define GPIO_PMSR8_PMSR830 (0x40000000uL)
+#define GPIO_PMSR8_PMSR831 (0x80000000uL)
+
+#define GPIO_PMCSR8_PMCSR80 (0x00000001uL)
+#define GPIO_PMCSR8_PMCSR81 (0x00000002uL)
+#define GPIO_PMCSR8_PMCSR82 (0x00000004uL)
+#define GPIO_PMCSR8_PMCSR83 (0x00000008uL)
+#define GPIO_PMCSR8_PMCSR84 (0x00000010uL)
+#define GPIO_PMCSR8_PMCSR85 (0x00000020uL)
+#define GPIO_PMCSR8_PMCSR86 (0x00000040uL)
+#define GPIO_PMCSR8_PMCSR87 (0x00000080uL)
+#define GPIO_PMCSR8_PMCSR88 (0x00000100uL)
+#define GPIO_PMCSR8_PMCSR89 (0x00000200uL)
+#define GPIO_PMCSR8_PMCSR810 (0x00000400uL)
+#define GPIO_PMCSR8_PMCSR811 (0x00000800uL)
+#define GPIO_PMCSR8_PMCSR812 (0x00001000uL)
+#define GPIO_PMCSR8_PMCSR813 (0x00002000uL)
+#define GPIO_PMCSR8_PMCSR814 (0x00004000uL)
+#define GPIO_PMCSR8_PMCSR815 (0x00008000uL)
+#define GPIO_PMCSR8_PMCSR816 (0x00010000uL)
+#define GPIO_PMCSR8_PMCSR817 (0x00020000uL)
+#define GPIO_PMCSR8_PMCSR818 (0x00040000uL)
+#define GPIO_PMCSR8_PMCSR819 (0x00080000uL)
+#define GPIO_PMCSR8_PMCSR820 (0x00100000uL)
+#define GPIO_PMCSR8_PMCSR821 (0x00200000uL)
+#define GPIO_PMCSR8_PMCSR822 (0x00400000uL)
+#define GPIO_PMCSR8_PMCSR823 (0x00800000uL)
+#define GPIO_PMCSR8_PMCSR824 (0x01000000uL)
+#define GPIO_PMCSR8_PMCSR825 (0x02000000uL)
+#define GPIO_PMCSR8_PMCSR826 (0x04000000uL)
+#define GPIO_PMCSR8_PMCSR827 (0x08000000uL)
+#define GPIO_PMCSR8_PMCSR828 (0x10000000uL)
+#define GPIO_PMCSR8_PMCSR829 (0x20000000uL)
+#define GPIO_PMCSR8_PMCSR830 (0x40000000uL)
+#define GPIO_PMCSR8_PMCSR831 (0x80000000uL)
+
+#define GPIO_PFCAE8_PFCAE80 (0x0001u)
+#define GPIO_PFCAE8_PFCAE81 (0x0002u)
+#define GPIO_PFCAE8_PFCAE82 (0x0004u)
+#define GPIO_PFCAE8_PFCAE83 (0x0008u)
+#define GPIO_PFCAE8_PFCAE84 (0x0010u)
+#define GPIO_PFCAE8_PFCAE85 (0x0020u)
+#define GPIO_PFCAE8_PFCAE86 (0x0040u)
+#define GPIO_PFCAE8_PFCAE87 (0x0080u)
+#define GPIO_PFCAE8_PFCAE88 (0x0100u)
+#define GPIO_PFCAE8_PFCAE89 (0x0200u)
+#define GPIO_PFCAE8_PFCAE810 (0x0400u)
+#define GPIO_PFCAE8_PFCAE811 (0x0800u)
+#define GPIO_PFCAE8_PFCAE812 (0x1000u)
+#define GPIO_PFCAE8_PFCAE813 (0x2000u)
+#define GPIO_PFCAE8_PFCAE814 (0x4000u)
+#define GPIO_PFCAE8_PFCAE815 (0x8000u)
+
+#define GPIO_PIBC8_PIBC80 (0x0001u)
+#define GPIO_PIBC8_PIBC81 (0x0002u)
+#define GPIO_PIBC8_PIBC82 (0x0004u)
+#define GPIO_PIBC8_PIBC83 (0x0008u)
+#define GPIO_PIBC8_PIBC84 (0x0010u)
+#define GPIO_PIBC8_PIBC85 (0x0020u)
+#define GPIO_PIBC8_PIBC86 (0x0040u)
+#define GPIO_PIBC8_PIBC87 (0x0080u)
+#define GPIO_PIBC8_PIBC88 (0x0100u)
+#define GPIO_PIBC8_PIBC89 (0x0200u)
+#define GPIO_PIBC8_PIBC810 (0x0400u)
+#define GPIO_PIBC8_PIBC811 (0x0800u)
+#define GPIO_PIBC8_PIBC812 (0x1000u)
+#define GPIO_PIBC8_PIBC813 (0x2000u)
+#define GPIO_PIBC8_PIBC814 (0x4000u)
+#define GPIO_PIBC8_PIBC815 (0x8000u)
+
+#define GPIO_PBDC8_PBDC80 (0x0001u)
+#define GPIO_PBDC8_PBDC81 (0x0002u)
+#define GPIO_PBDC8_PBDC82 (0x0004u)
+#define GPIO_PBDC8_PBDC83 (0x0008u)
+#define GPIO_PBDC8_PBDC84 (0x0010u)
+#define GPIO_PBDC8_PBDC85 (0x0020u)
+#define GPIO_PBDC8_PBDC86 (0x0040u)
+#define GPIO_PBDC8_PBDC87 (0x0080u)
+#define GPIO_PBDC8_PBDC88 (0x0100u)
+#define GPIO_PBDC8_PBDC89 (0x0200u)
+#define GPIO_PBDC8_PBDC810 (0x0400u)
+#define GPIO_PBDC8_PBDC811 (0x0800u)
+#define GPIO_PBDC8_PBDC812 (0x1000u)
+#define GPIO_PBDC8_PBDC813 (0x2000u)
+#define GPIO_PBDC8_PBDC814 (0x4000u)
+#define GPIO_PBDC8_PBDC815 (0x8000u)
+
+#define GPIO_PIPC8_PIPC80 (0x0001u)
+#define GPIO_PIPC8_PIPC81 (0x0002u)
+#define GPIO_PIPC8_PIPC82 (0x0004u)
+#define GPIO_PIPC8_PIPC83 (0x0008u)
+#define GPIO_PIPC8_PIPC84 (0x0010u)
+#define GPIO_PIPC8_PIPC85 (0x0020u)
+#define GPIO_PIPC8_PIPC86 (0x0040u)
+#define GPIO_PIPC8_PIPC87 (0x0080u)
+#define GPIO_PIPC8_PIPC88 (0x0100u)
+#define GPIO_PIPC8_PIPC89 (0x0200u)
+#define GPIO_PIPC8_PIPC810 (0x0400u)
+#define GPIO_PIPC8_PIPC811 (0x0800u)
+#define GPIO_PIPC8_PIPC812 (0x1000u)
+#define GPIO_PIPC8_PIPC813 (0x2000u)
+#define GPIO_PIPC8_PIPC814 (0x4000u)
+#define GPIO_PIPC8_PIPC815 (0x8000u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90 (0x0001u)
+#define GPIO_P9_P91 (0x0002u)
+#define GPIO_P9_P92 (0x0004u)
+#define GPIO_P9_P93 (0x0008u)
+#define GPIO_P9_P94 (0x0010u)
+#define GPIO_P9_P95 (0x0020u)
+#define GPIO_P9_P96 (0x0040u)
+#define GPIO_P9_P97 (0x0080u)
+
+#define GPIO_PSR9_PSR90 (0x00000001uL)
+#define GPIO_PSR9_PSR91 (0x00000002uL)
+#define GPIO_PSR9_PSR92 (0x00000004uL)
+#define GPIO_PSR9_PSR93 (0x00000008uL)
+#define GPIO_PSR9_PSR94 (0x00000010uL)
+#define GPIO_PSR9_PSR95 (0x00000020uL)
+#define GPIO_PSR9_PSR96 (0x00000040uL)
+#define GPIO_PSR9_PSR97 (0x00000080uL)
+#define GPIO_PSR9_PSR916 (0x00010000uL)
+#define GPIO_PSR9_PSR917 (0x00020000uL)
+#define GPIO_PSR9_PSR918 (0x00040000uL)
+#define GPIO_PSR9_PSR919 (0x00080000uL)
+#define GPIO_PSR9_PSR920 (0x00100000uL)
+#define GPIO_PSR9_PSR921 (0x00200000uL)
+#define GPIO_PSR9_PSR922 (0x00400000uL)
+#define GPIO_PSR9_PSR923 (0x00800000uL)
+
+#define GPIO_PPR9_PPR90 (0x0001u)
+#define GPIO_PPR9_PPR91 (0x0002u)
+#define GPIO_PPR9_PPR92 (0x0004u)
+#define GPIO_PPR9_PPR93 (0x0008u)
+#define GPIO_PPR9_PPR94 (0x0010u)
+#define GPIO_PPR9_PPR95 (0x0020u)
+#define GPIO_PPR9_PPR96 (0x0040u)
+#define GPIO_PPR9_PPR97 (0x0080u)
+
+#define GPIO_PM9_PM90 (0x0001u)
+#define GPIO_PM9_PM91 (0x0002u)
+#define GPIO_PM9_PM92 (0x0004u)
+#define GPIO_PM9_PM93 (0x0008u)
+#define GPIO_PM9_PM94 (0x0010u)
+#define GPIO_PM9_PM95 (0x0020u)
+#define GPIO_PM9_PM96 (0x0040u)
+#define GPIO_PM9_PM97 (0x0080u)
+
+#define GPIO_PMC9_PMC90 (0x0001u)
+#define GPIO_PMC9_PMC91 (0x0002u)
+#define GPIO_PMC9_PMC92 (0x0004u)
+#define GPIO_PMC9_PMC93 (0x0008u)
+#define GPIO_PMC9_PMC94 (0x0010u)
+#define GPIO_PMC9_PMC95 (0x0020u)
+#define GPIO_PMC9_PMC96 (0x0040u)
+#define GPIO_PMC9_PMC97 (0x0080u)
+
+#define GPIO_PFC9_PFC90 (0x0001u)
+#define GPIO_PFC9_PFC91 (0x0002u)
+#define GPIO_PFC9_PFC92 (0x0004u)
+#define GPIO_PFC9_PFC93 (0x0008u)
+#define GPIO_PFC9_PFC94 (0x0010u)
+#define GPIO_PFC9_PFC95 (0x0020u)
+#define GPIO_PFC9_PFC96 (0x0040u)
+#define GPIO_PFC9_PFC97 (0x0080u)
+
+#define GPIO_PFCE9_PFCE90 (0x0001u)
+#define GPIO_PFCE9_PFCE91 (0x0002u)
+#define GPIO_PFCE9_PFCE92 (0x0004u)
+#define GPIO_PFCE9_PFCE93 (0x0008u)
+#define GPIO_PFCE9_PFCE94 (0x0010u)
+#define GPIO_PFCE9_PFCE95 (0x0020u)
+#define GPIO_PFCE9_PFCE96 (0x0040u)
+#define GPIO_PFCE9_PFCE97 (0x0080u)
+
+#define GPIO_PNOT9_PNOT90 (0x0001u)
+#define GPIO_PNOT9_PNOT91 (0x0002u)
+#define GPIO_PNOT9_PNOT92 (0x0004u)
+#define GPIO_PNOT9_PNOT93 (0x0008u)
+#define GPIO_PNOT9_PNOT94 (0x0010u)
+#define GPIO_PNOT9_PNOT95 (0x0020u)
+#define GPIO_PNOT9_PNOT96 (0x0040u)
+#define GPIO_PNOT9_PNOT97 (0x0080u)
+
+#define GPIO_PMSR9_PMSR90 (0x00000001uL)
+#define GPIO_PMSR9_PMSR91 (0x00000002uL)
+#define GPIO_PMSR9_PMSR92 (0x00000004uL)
+#define GPIO_PMSR9_PMSR93 (0x00000008uL)
+#define GPIO_PMSR9_PMSR94 (0x00000010uL)
+#define GPIO_PMSR9_PMSR95 (0x00000020uL)
+#define GPIO_PMSR9_PMSR96 (0x00000040uL)
+#define GPIO_PMSR9_PMSR97 (0x00000080uL)
+#define GPIO_PMSR9_PMSR916 (0x00010000uL)
+#define GPIO_PMSR9_PMSR917 (0x00020000uL)
+#define GPIO_PMSR9_PMSR918 (0x00040000uL)
+#define GPIO_PMSR9_PMSR919 (0x00080000uL)
+#define GPIO_PMSR9_PMSR920 (0x00100000uL)
+#define GPIO_PMSR9_PMSR921 (0x00200000uL)
+#define GPIO_PMSR9_PMSR922 (0x00400000uL)
+#define GPIO_PMSR9_PMSR923 (0x00800000uL)
+
+#define GPIO_PMCSR9_PMCSR90 (0x00000001uL)
+#define GPIO_PMCSR9_PMCSR91 (0x00000002uL)
+#define GPIO_PMCSR9_PMCSR92 (0x00000004uL)
+#define GPIO_PMCSR9_PMCSR93 (0x00000008uL)
+#define GPIO_PMCSR9_PMCSR94 (0x00000010uL)
+#define GPIO_PMCSR9_PMCSR95 (0x00000020uL)
+#define GPIO_PMCSR9_PMCSR96 (0x00000040uL)
+#define GPIO_PMCSR9_PMCSR97 (0x00000080uL)
+#define GPIO_PMCSR9_PMCSR916 (0x00010000uL)
+#define GPIO_PMCSR9_PMCSR917 (0x00020000uL)
+#define GPIO_PMCSR9_PMCSR918 (0x00040000uL)
+#define GPIO_PMCSR9_PMCSR919 (0x00080000uL)
+#define GPIO_PMCSR9_PMCSR920 (0x00100000uL)
+#define GPIO_PMCSR9_PMCSR921 (0x00200000uL)
+#define GPIO_PMCSR9_PMCSR922 (0x00400000uL)
+#define GPIO_PMCSR9_PMCSR923 (0x00800000uL)
+
+#define GPIO_PFCAE9_PFCAE90 (0x0001u)
+#define GPIO_PFCAE9_PFCAE91 (0x0002u)
+#define GPIO_PFCAE9_PFCAE92 (0x0004u)
+#define GPIO_PFCAE9_PFCAE93 (0x0008u)
+#define GPIO_PFCAE9_PFCAE94 (0x0010u)
+#define GPIO_PFCAE9_PFCAE95 (0x0020u)
+#define GPIO_PFCAE9_PFCAE96 (0x0040u)
+#define GPIO_PFCAE9_PFCAE97 (0x0080u)
+
+#define GPIO_PIBC9_PIBC90 (0x0001u)
+#define GPIO_PIBC9_PIBC91 (0x0002u)
+#define GPIO_PIBC9_PIBC92 (0x0004u)
+#define GPIO_PIBC9_PIBC93 (0x0008u)
+#define GPIO_PIBC9_PIBC94 (0x0010u)
+#define GPIO_PIBC9_PIBC95 (0x0020u)
+#define GPIO_PIBC9_PIBC96 (0x0040u)
+#define GPIO_PIBC9_PIBC97 (0x0080u)
+
+#define GPIO_PBDC9_PBDC90 (0x0001u)
+#define GPIO_PBDC9_PBDC91 (0x0002u)
+#define GPIO_PBDC9_PBDC92 (0x0004u)
+#define GPIO_PBDC9_PBDC93 (0x0008u)
+#define GPIO_PBDC9_PBDC94 (0x0010u)
+#define GPIO_PBDC9_PBDC95 (0x0020u)
+#define GPIO_PBDC9_PBDC96 (0x0040u)
+#define GPIO_PBDC9_PBDC97 (0x0080u)
+
+#define GPIO_PIPC9_PIPC90 (0x0001u)
+#define GPIO_PIPC9_PIPC91 (0x0002u)
+#define GPIO_PIPC9_PIPC92 (0x0004u)
+#define GPIO_PIPC9_PIPC93 (0x0008u)
+#define GPIO_PIPC9_PIPC94 (0x0010u)
+#define GPIO_PIPC9_PIPC95 (0x0020u)
+#define GPIO_PIPC9_PIPC96 (0x0040u)
+#define GPIO_PIPC9_PIPC97 (0x0080u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100 (0x0001u)
+#define GPIO_P10_P101 (0x0002u)
+#define GPIO_P10_P102 (0x0004u)
+#define GPIO_P10_P103 (0x0008u)
+#define GPIO_P10_P104 (0x0010u)
+#define GPIO_P10_P105 (0x0020u)
+#define GPIO_P10_P106 (0x0040u)
+#define GPIO_P10_P107 (0x0080u)
+#define GPIO_P10_P108 (0x0100u)
+#define GPIO_P10_P109 (0x0200u)
+#define GPIO_P10_P1010 (0x0400u)
+#define GPIO_P10_P1011 (0x0800u)
+#define GPIO_P10_P1012 (0x1000u)
+#define GPIO_P10_P1013 (0x2000u)
+#define GPIO_P10_P1014 (0x4000u)
+#define GPIO_P10_P1015 (0x8000u)
+
+#define GPIO_PSR10_PSR100 (0x00000001uL)
+#define GPIO_PSR10_PSR101 (0x00000002uL)
+#define GPIO_PSR10_PSR102 (0x00000004uL)
+#define GPIO_PSR10_PSR103 (0x00000008uL)
+#define GPIO_PSR10_PSR104 (0x00000010uL)
+#define GPIO_PSR10_PSR105 (0x00000020uL)
+#define GPIO_PSR10_PSR106 (0x00000040uL)
+#define GPIO_PSR10_PSR107 (0x00000080uL)
+#define GPIO_PSR10_PSR108 (0x00000100uL)
+#define GPIO_PSR10_PSR109 (0x00000200uL)
+#define GPIO_PSR10_PSR1010 (0x00000400uL)
+#define GPIO_PSR10_PSR1011 (0x00000800uL)
+#define GPIO_PSR10_PSR1012 (0x00001000uL)
+#define GPIO_PSR10_PSR1013 (0x00002000uL)
+#define GPIO_PSR10_PSR1014 (0x00004000uL)
+#define GPIO_PSR10_PSR1015 (0x00008000uL)
+#define GPIO_PSR10_PSR1016 (0x00010000uL)
+#define GPIO_PSR10_PSR1017 (0x00020000uL)
+#define GPIO_PSR10_PSR1018 (0x00040000uL)
+#define GPIO_PSR10_PSR1019 (0x00080000uL)
+#define GPIO_PSR10_PSR1020 (0x00100000uL)
+#define GPIO_PSR10_PSR1021 (0x00200000uL)
+#define GPIO_PSR10_PSR1022 (0x00400000uL)
+#define GPIO_PSR10_PSR1023 (0x00800000uL)
+#define GPIO_PSR10_PSR1024 (0x01000000uL)
+#define GPIO_PSR10_PSR1025 (0x02000000uL)
+#define GPIO_PSR10_PSR1026 (0x04000000uL)
+#define GPIO_PSR10_PSR1027 (0x08000000uL)
+#define GPIO_PSR10_PSR1028 (0x10000000uL)
+#define GPIO_PSR10_PSR1029 (0x20000000uL)
+#define GPIO_PSR10_PSR1030 (0x40000000uL)
+#define GPIO_PSR10_PSR1031 (0x80000000uL)
+
+#define GPIO_PPR10_PPR100 (0x0001u)
+#define GPIO_PPR10_PPR101 (0x0002u)
+#define GPIO_PPR10_PPR102 (0x0004u)
+#define GPIO_PPR10_PPR103 (0x0008u)
+#define GPIO_PPR10_PPR104 (0x0010u)
+#define GPIO_PPR10_PPR105 (0x0020u)
+#define GPIO_PPR10_PPR106 (0x0040u)
+#define GPIO_PPR10_PPR107 (0x0080u)
+#define GPIO_PPR10_PPR108 (0x0100u)
+#define GPIO_PPR10_PPR109 (0x0200u)
+#define GPIO_PPR10_PPR1010 (0x0400u)
+#define GPIO_PPR10_PPR1011 (0x0800u)
+#define GPIO_PPR10_PPR1012 (0x1000u)
+#define GPIO_PPR10_PPR1013 (0x2000u)
+#define GPIO_PPR10_PPR1014 (0x4000u)
+#define GPIO_PPR10_PPR1015 (0x8000u)
+
+#define GPIO_PM10_PM100 (0x0001u)
+#define GPIO_PM10_PM101 (0x0002u)
+#define GPIO_PM10_PM102 (0x0004u)
+#define GPIO_PM10_PM103 (0x0008u)
+#define GPIO_PM10_PM104 (0x0010u)
+#define GPIO_PM10_PM105 (0x0020u)
+#define GPIO_PM10_PM106 (0x0040u)
+#define GPIO_PM10_PM107 (0x0080u)
+#define GPIO_PM10_PM108 (0x0100u)
+#define GPIO_PM10_PM109 (0x0200u)
+#define GPIO_PM10_PM1010 (0x0400u)
+#define GPIO_PM10_PM1011 (0x0800u)
+#define GPIO_PM10_PM1012 (0x1000u)
+#define GPIO_PM10_PM1013 (0x2000u)
+#define GPIO_PM10_PM1014 (0x4000u)
+#define GPIO_PM10_PM1015 (0x8000u)
+
+#define GPIO_PMC10_PMC100 (0x0001u)
+#define GPIO_PMC10_PMC101 (0x0002u)
+#define GPIO_PMC10_PMC102 (0x0004u)
+#define GPIO_PMC10_PMC103 (0x0008u)
+#define GPIO_PMC10_PMC104 (0x0010u)
+#define GPIO_PMC10_PMC105 (0x0020u)
+#define GPIO_PMC10_PMC106 (0x0040u)
+#define GPIO_PMC10_PMC107 (0x0080u)
+#define GPIO_PMC10_PMC108 (0x0100u)
+#define GPIO_PMC10_PMC109 (0x0200u)
+#define GPIO_PMC10_PMC1010 (0x0400u)
+#define GPIO_PMC10_PMC1011 (0x0800u)
+#define GPIO_PMC10_PMC1012 (0x1000u)
+#define GPIO_PMC10_PMC1013 (0x2000u)
+#define GPIO_PMC10_PMC1014 (0x4000u)
+#define GPIO_PMC10_PMC1015 (0x8000u)
+
+#define GPIO_PFC10_PFC100 (0x0001u)
+#define GPIO_PFC10_PFC101 (0x0002u)
+#define GPIO_PFC10_PFC102 (0x0004u)
+#define GPIO_PFC10_PFC103 (0x0008u)
+#define GPIO_PFC10_PFC104 (0x0010u)
+#define GPIO_PFC10_PFC105 (0x0020u)
+#define GPIO_PFC10_PFC106 (0x0040u)
+#define GPIO_PFC10_PFC107 (0x0080u)
+#define GPIO_PFC10_PFC108 (0x0100u)
+#define GPIO_PFC10_PFC109 (0x0200u)
+#define GPIO_PFC10_PFC1010 (0x0400u)
+#define GPIO_PFC10_PFC1011 (0x0800u)
+#define GPIO_PFC10_PFC1012 (0x1000u)
+#define GPIO_PFC10_PFC1013 (0x2000u)
+#define GPIO_PFC10_PFC1014 (0x4000u)
+#define GPIO_PFC10_PFC1015 (0x8000u)
+
+#define GPIO_PFCE10_PFCE100 (0x0001u)
+#define GPIO_PFCE10_PFCE101 (0x0002u)
+#define GPIO_PFCE10_PFCE102 (0x0004u)
+#define GPIO_PFCE10_PFCE103 (0x0008u)
+#define GPIO_PFCE10_PFCE104 (0x0010u)
+#define GPIO_PFCE10_PFCE105 (0x0020u)
+#define GPIO_PFCE10_PFCE106 (0x0040u)
+#define GPIO_PFCE10_PFCE107 (0x0080u)
+#define GPIO_PFCE10_PFCE108 (0x0100u)
+#define GPIO_PFCE10_PFCE109 (0x0200u)
+#define GPIO_PFCE10_PFCE1010 (0x0400u)
+#define GPIO_PFCE10_PFCE1011 (0x0800u)
+#define GPIO_PFCE10_PFCE1012 (0x1000u)
+#define GPIO_PFCE10_PFCE1013 (0x2000u)
+#define GPIO_PFCE10_PFCE1014 (0x4000u)
+#define GPIO_PFCE10_PFCE1015 (0x8000u)
+
+#define GPIO_PNOT10_PNOT100 (0x0001u)
+#define GPIO_PNOT10_PNOT101 (0x0002u)
+#define GPIO_PNOT10_PNOT102 (0x0004u)
+#define GPIO_PNOT10_PNOT103 (0x0008u)
+#define GPIO_PNOT10_PNOT104 (0x0010u)
+#define GPIO_PNOT10_PNOT105 (0x0020u)
+#define GPIO_PNOT10_PNOT106 (0x0040u)
+#define GPIO_PNOT10_PNOT107 (0x0080u)
+#define GPIO_PNOT10_PNOT108 (0x0100u)
+#define GPIO_PNOT10_PNOT109 (0x0200u)
+#define GPIO_PNOT10_PNOT1010 (0x0400u)
+#define GPIO_PNOT10_PNOT1011 (0x0800u)
+#define GPIO_PNOT10_PNOT1012 (0x1000u)
+#define GPIO_PNOT10_PNOT1013 (0x2000u)
+#define GPIO_PNOT10_PNOT1014 (0x4000u)
+#define GPIO_PNOT10_PNOT1015 (0x8000u)
+
+#define GPIO_PMSR10_PMSR100 (0x00000001uL)
+#define GPIO_PMSR10_PMSR101 (0x00000002uL)
+#define GPIO_PMSR10_PMSR102 (0x00000004uL)
+#define GPIO_PMSR10_PMSR103 (0x00000008uL)
+#define GPIO_PMSR10_PMSR104 (0x00000010uL)
+#define GPIO_PMSR10_PMSR105 (0x00000020uL)
+#define GPIO_PMSR10_PMSR106 (0x00000040uL)
+#define GPIO_PMSR10_PMSR107 (0x00000080uL)
+#define GPIO_PMSR10_PMSR108 (0x00000100uL)
+#define GPIO_PMSR10_PMSR109 (0x00000200uL)
+#define GPIO_PMSR10_PMSR1010 (0x00000400uL)
+#define GPIO_PMSR10_PMSR1011 (0x00000800uL)
+#define GPIO_PMSR10_PMSR1012 (0x00001000uL)
+#define GPIO_PMSR10_PMSR1013 (0x00002000uL)
+#define GPIO_PMSR10_PMSR1014 (0x00004000uL)
+#define GPIO_PMSR10_PMSR1015 (0x00008000uL)
+#define GPIO_PMSR10_PMSR1016 (0x00010000uL)
+#define GPIO_PMSR10_PMSR1017 (0x00020000uL)
+#define GPIO_PMSR10_PMSR1018 (0x00040000uL)
+#define GPIO_PMSR10_PMSR1019 (0x00080000uL)
+#define GPIO_PMSR10_PMSR1020 (0x00100000uL)
+#define GPIO_PMSR10_PMSR1021 (0x00200000uL)
+#define GPIO_PMSR10_PMSR1022 (0x00400000uL)
+#define GPIO_PMSR10_PMSR1023 (0x00800000uL)
+#define GPIO_PMSR10_PMSR1024 (0x01000000uL)
+#define GPIO_PMSR10_PMSR1025 (0x02000000uL)
+#define GPIO_PMSR10_PMSR1026 (0x04000000uL)
+#define GPIO_PMSR10_PMSR1027 (0x08000000uL)
+#define GPIO_PMSR10_PMSR1028 (0x10000000uL)
+#define GPIO_PMSR10_PMSR1029 (0x20000000uL)
+#define GPIO_PMSR10_PMSR1030 (0x40000000uL)
+#define GPIO_PMSR10_PMSR1031 (0x80000000uL)
+
+#define GPIO_PMCSR10_PMCSR100 (0x00000001uL)
+#define GPIO_PMCSR10_PMCSR101 (0x00000002uL)
+#define GPIO_PMCSR10_PMCSR102 (0x00000004uL)
+#define GPIO_PMCSR10_PMCSR103 (0x00000008uL)
+#define GPIO_PMCSR10_PMCSR104 (0x00000010uL)
+#define GPIO_PMCSR10_PMCSR105 (0x00000020uL)
+#define GPIO_PMCSR10_PMCSR106 (0x00000040uL)
+#define GPIO_PMCSR10_PMCSR107 (0x00000080uL)
+#define GPIO_PMCSR10_PMCSR108 (0x00000100uL)
+#define GPIO_PMCSR10_PMCSR109 (0x00000200uL)
+#define GPIO_PMCSR10_PMCSR1010 (0x00000400uL)
+#define GPIO_PMCSR10_PMCSR1011 (0x00000800uL)
+#define GPIO_PMCSR10_PMCSR1012 (0x00001000uL)
+#define GPIO_PMCSR10_PMCSR1013 (0x00002000uL)
+#define GPIO_PMCSR10_PMCSR1014 (0x00004000uL)
+#define GPIO_PMCSR10_PMCSR1015 (0x00008000uL)
+#define GPIO_PMCSR10_PMCSR1016 (0x00010000uL)
+#define GPIO_PMCSR10_PMCSR1017 (0x00020000uL)
+#define GPIO_PMCSR10_PMCSR1018 (0x00040000uL)
+#define GPIO_PMCSR10_PMCSR1019 (0x00080000uL)
+#define GPIO_PMCSR10_PMCSR1020 (0x00100000uL)
+#define GPIO_PMCSR10_PMCSR1021 (0x00200000uL)
+#define GPIO_PMCSR10_PMCSR1022 (0x00400000uL)
+#define GPIO_PMCSR10_PMCSR1023 (0x00800000uL)
+#define GPIO_PMCSR10_PMCSR1024 (0x01000000uL)
+#define GPIO_PMCSR10_PMCSR1025 (0x02000000uL)
+#define GPIO_PMCSR10_PMCSR1026 (0x04000000uL)
+#define GPIO_PMCSR10_PMCSR1027 (0x08000000uL)
+#define GPIO_PMCSR10_PMCSR1028 (0x10000000uL)
+#define GPIO_PMCSR10_PMCSR1029 (0x20000000uL)
+#define GPIO_PMCSR10_PMCSR1030 (0x40000000uL)
+#define GPIO_PMCSR10_PMCSR1031 (0x80000000uL)
+
+#define GPIO_PFCAE10_PFCAE100 (0x0001u)
+#define GPIO_PFCAE10_PFCAE101 (0x0002u)
+#define GPIO_PFCAE10_PFCAE102 (0x0004u)
+#define GPIO_PFCAE10_PFCAE103 (0x0008u)
+#define GPIO_PFCAE10_PFCAE104 (0x0010u)
+#define GPIO_PFCAE10_PFCAE105 (0x0020u)
+#define GPIO_PFCAE10_PFCAE106 (0x0040u)
+#define GPIO_PFCAE10_PFCAE107 (0x0080u)
+#define GPIO_PFCAE10_PFCAE108 (0x0100u)
+#define GPIO_PFCAE10_PFCAE109 (0x0200u)
+#define GPIO_PFCAE10_PFCAE1010 (0x0400u)
+#define GPIO_PFCAE10_PFCAE1011 (0x0800u)
+#define GPIO_PFCAE10_PFCAE1012 (0x1000u)
+#define GPIO_PFCAE10_PFCAE1013 (0x2000u)
+#define GPIO_PFCAE10_PFCAE1014 (0x4000u)
+#define GPIO_PFCAE10_PFCAE1015 (0x8000u)
+
+#define GPIO_PIBC10_PIBC100 (0x0001u)
+#define GPIO_PIBC10_PIBC101 (0x0002u)
+#define GPIO_PIBC10_PIBC102 (0x0004u)
+#define GPIO_PIBC10_PIBC103 (0x0008u)
+#define GPIO_PIBC10_PIBC104 (0x0010u)
+#define GPIO_PIBC10_PIBC105 (0x0020u)
+#define GPIO_PIBC10_PIBC106 (0x0040u)
+#define GPIO_PIBC10_PIBC107 (0x0080u)
+#define GPIO_PIBC10_PIBC108 (0x0100u)
+#define GPIO_PIBC10_PIBC109 (0x0200u)
+#define GPIO_PIBC10_PIBC1010 (0x0400u)
+#define GPIO_PIBC10_PIBC1011 (0x0800u)
+#define GPIO_PIBC10_PIBC1012 (0x1000u)
+#define GPIO_PIBC10_PIBC1013 (0x2000u)
+#define GPIO_PIBC10_PIBC1014 (0x4000u)
+#define GPIO_PIBC10_PIBC1015 (0x8000u)
+
+#define GPIO_PBDC10_PBDC100 (0x0001u)
+#define GPIO_PBDC10_PBDC101 (0x0002u)
+#define GPIO_PBDC10_PBDC102 (0x0004u)
+#define GPIO_PBDC10_PBDC103 (0x0008u)
+#define GPIO_PBDC10_PBDC104 (0x0010u)
+#define GPIO_PBDC10_PBDC105 (0x0020u)
+#define GPIO_PBDC10_PBDC106 (0x0040u)
+#define GPIO_PBDC10_PBDC107 (0x0080u)
+#define GPIO_PBDC10_PBDC108 (0x0100u)
+#define GPIO_PBDC10_PBDC109 (0x0200u)
+#define GPIO_PBDC10_PBDC1010 (0x0400u)
+#define GPIO_PBDC10_PBDC1011 (0x0800u)
+#define GPIO_PBDC10_PBDC1012 (0x1000u)
+#define GPIO_PBDC10_PBDC1013 (0x2000u)
+#define GPIO_PBDC10_PBDC1014 (0x4000u)
+#define GPIO_PBDC10_PBDC1015 (0x8000u)
+
+#define GPIO_PIPC10_PIPC100 (0x0001u)
+#define GPIO_PIPC10_PIPC101 (0x0002u)
+#define GPIO_PIPC10_PIPC102 (0x0004u)
+#define GPIO_PIPC10_PIPC103 (0x0008u)
+#define GPIO_PIPC10_PIPC104 (0x0010u)
+#define GPIO_PIPC10_PIPC105 (0x0020u)
+#define GPIO_PIPC10_PIPC106 (0x0040u)
+#define GPIO_PIPC10_PIPC107 (0x0080u)
+#define GPIO_PIPC10_PIPC108 (0x0100u)
+#define GPIO_PIPC10_PIPC109 (0x0200u)
+#define GPIO_PIPC10_PIPC1010 (0x0400u)
+#define GPIO_PIPC10_PIPC1011 (0x0800u)
+#define GPIO_PIPC10_PIPC1012 (0x1000u)
+#define GPIO_PIPC10_PIPC1013 (0x2000u)
+#define GPIO_PIPC10_PIPC1014 (0x4000u)
+#define GPIO_PIPC10_PIPC1015 (0x8000u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110 (0x0001u)
+#define GPIO_P11_P111 (0x0002u)
+#define GPIO_P11_P112 (0x0004u)
+#define GPIO_P11_P113 (0x0008u)
+#define GPIO_P11_P114 (0x0010u)
+#define GPIO_P11_P115 (0x0020u)
+#define GPIO_P11_P116 (0x0040u)
+#define GPIO_P11_P117 (0x0080u)
+#define GPIO_P11_P118 (0x0100u)
+#define GPIO_P11_P119 (0x0200u)
+#define GPIO_P11_P1110 (0x0400u)
+#define GPIO_P11_P1111 (0x0800u)
+#define GPIO_P11_P1112 (0x1000u)
+#define GPIO_P11_P1113 (0x2000u)
+#define GPIO_P11_P1114 (0x4000u)
+#define GPIO_P11_P1115 (0x8000u)
+
+#define GPIO_PSR11_PSR110 (0x00000001uL)
+#define GPIO_PSR11_PSR111 (0x00000002uL)
+#define GPIO_PSR11_PSR112 (0x00000004uL)
+#define GPIO_PSR11_PSR113 (0x00000008uL)
+#define GPIO_PSR11_PSR114 (0x00000010uL)
+#define GPIO_PSR11_PSR115 (0x00000020uL)
+#define GPIO_PSR11_PSR116 (0x00000040uL)
+#define GPIO_PSR11_PSR117 (0x00000080uL)
+#define GPIO_PSR11_PSR118 (0x00000100uL)
+#define GPIO_PSR11_PSR119 (0x00000200uL)
+#define GPIO_PSR11_PSR1110 (0x00000400uL)
+#define GPIO_PSR11_PSR1111 (0x00000800uL)
+#define GPIO_PSR11_PSR1112 (0x00001000uL)
+#define GPIO_PSR11_PSR1113 (0x00002000uL)
+#define GPIO_PSR11_PSR1114 (0x00004000uL)
+#define GPIO_PSR11_PSR1115 (0x00008000uL)
+#define GPIO_PSR11_PSR1116 (0x00010000uL)
+#define GPIO_PSR11_PSR1117 (0x00020000uL)
+#define GPIO_PSR11_PSR1118 (0x00040000uL)
+#define GPIO_PSR11_PSR1119 (0x00080000uL)
+#define GPIO_PSR11_PSR1120 (0x00100000uL)
+#define GPIO_PSR11_PSR1121 (0x00200000uL)
+#define GPIO_PSR11_PSR1122 (0x00400000uL)
+#define GPIO_PSR11_PSR1123 (0x00800000uL)
+#define GPIO_PSR11_PSR1124 (0x01000000uL)
+#define GPIO_PSR11_PSR1125 (0x02000000uL)
+#define GPIO_PSR11_PSR1126 (0x04000000uL)
+#define GPIO_PSR11_PSR1127 (0x08000000uL)
+#define GPIO_PSR11_PSR1128 (0x10000000uL)
+#define GPIO_PSR11_PSR1129 (0x20000000uL)
+#define GPIO_PSR11_PSR1130 (0x40000000uL)
+#define GPIO_PSR11_PSR1131 (0x80000000uL)
+
+#define GPIO_PPR11_PPR110 (0x0001u)
+#define GPIO_PPR11_PPR111 (0x0002u)
+#define GPIO_PPR11_PPR112 (0x0004u)
+#define GPIO_PPR11_PPR113 (0x0008u)
+#define GPIO_PPR11_PPR114 (0x0010u)
+#define GPIO_PPR11_PPR115 (0x0020u)
+#define GPIO_PPR11_PPR116 (0x0040u)
+#define GPIO_PPR11_PPR117 (0x0080u)
+#define GPIO_PPR11_PPR118 (0x0100u)
+#define GPIO_PPR11_PPR119 (0x0200u)
+#define GPIO_PPR11_PPR1110 (0x0400u)
+#define GPIO_PPR11_PPR1111 (0x0800u)
+#define GPIO_PPR11_PPR1112 (0x1000u)
+#define GPIO_PPR11_PPR1113 (0x2000u)
+#define GPIO_PPR11_PPR1114 (0x4000u)
+#define GPIO_PPR11_PPR1115 (0x8000u)
+
+#define GPIO_PM11_PM110 (0x0001u)
+#define GPIO_PM11_PM111 (0x0002u)
+#define GPIO_PM11_PM112 (0x0004u)
+#define GPIO_PM11_PM113 (0x0008u)
+#define GPIO_PM11_PM114 (0x0010u)
+#define GPIO_PM11_PM115 (0x0020u)
+#define GPIO_PM11_PM116 (0x0040u)
+#define GPIO_PM11_PM117 (0x0080u)
+#define GPIO_PM11_PM118 (0x0100u)
+#define GPIO_PM11_PM119 (0x0200u)
+#define GPIO_PM11_PM1110 (0x0400u)
+#define GPIO_PM11_PM1111 (0x0800u)
+#define GPIO_PM11_PM1112 (0x1000u)
+#define GPIO_PM11_PM1113 (0x2000u)
+#define GPIO_PM11_PM1114 (0x4000u)
+#define GPIO_PM11_PM1115 (0x8000u)
+
+#define GPIO_PMC11_PMC110 (0x0001u)
+#define GPIO_PMC11_PMC111 (0x0002u)
+#define GPIO_PMC11_PMC112 (0x0004u)
+#define GPIO_PMC11_PMC113 (0x0008u)
+#define GPIO_PMC11_PMC114 (0x0010u)
+#define GPIO_PMC11_PMC115 (0x0020u)
+#define GPIO_PMC11_PMC116 (0x0040u)
+#define GPIO_PMC11_PMC117 (0x0080u)
+#define GPIO_PMC11_PMC118 (0x0100u)
+#define GPIO_PMC11_PMC119 (0x0200u)
+#define GPIO_PMC11_PMC1110 (0x0400u)
+#define GPIO_PMC11_PMC1111 (0x0800u)
+#define GPIO_PMC11_PMC1112 (0x1000u)
+#define GPIO_PMC11_PMC1113 (0x2000u)
+#define GPIO_PMC11_PMC1114 (0x4000u)
+#define GPIO_PMC11_PMC1115 (0x8000u)
+
+#define GPIO_PFC11_PFC110 (0x0001u)
+#define GPIO_PFC11_PFC111 (0x0002u)
+#define GPIO_PFC11_PFC112 (0x0004u)
+#define GPIO_PFC11_PFC113 (0x0008u)
+#define GPIO_PFC11_PFC114 (0x0010u)
+#define GPIO_PFC11_PFC115 (0x0020u)
+#define GPIO_PFC11_PFC116 (0x0040u)
+#define GPIO_PFC11_PFC117 (0x0080u)
+#define GPIO_PFC11_PFC118 (0x0100u)
+#define GPIO_PFC11_PFC119 (0x0200u)
+#define GPIO_PFC11_PFC1110 (0x0400u)
+#define GPIO_PFC11_PFC1111 (0x0800u)
+#define GPIO_PFC11_PFC1112 (0x1000u)
+#define GPIO_PFC11_PFC1113 (0x2000u)
+#define GPIO_PFC11_PFC1114 (0x4000u)
+#define GPIO_PFC11_PFC1115 (0x8000u)
+
+#define GPIO_PFCE11_PFCE110 (0x0001u)
+#define GPIO_PFCE11_PFCE111 (0x0002u)
+#define GPIO_PFCE11_PFCE112 (0x0004u)
+#define GPIO_PFCE11_PFCE113 (0x0008u)
+#define GPIO_PFCE11_PFCE114 (0x0010u)
+#define GPIO_PFCE11_PFCE115 (0x0020u)
+#define GPIO_PFCE11_PFCE116 (0x0040u)
+#define GPIO_PFCE11_PFCE117 (0x0080u)
+#define GPIO_PFCE11_PFCE118 (0x0100u)
+#define GPIO_PFCE11_PFCE119 (0x0200u)
+#define GPIO_PFCE11_PFCE1110 (0x0400u)
+#define GPIO_PFCE11_PFCE1111 (0x0800u)
+#define GPIO_PFCE11_PFCE1112 (0x1000u)
+#define GPIO_PFCE11_PFCE1113 (0x2000u)
+#define GPIO_PFCE11_PFCE1114 (0x4000u)
+#define GPIO_PFCE11_PFCE1115 (0x8000u)
+
+#define GPIO_PNOT11_PNOT110 (0x0001u)
+#define GPIO_PNOT11_PNOT111 (0x0002u)
+#define GPIO_PNOT11_PNOT112 (0x0004u)
+#define GPIO_PNOT11_PNOT113 (0x0008u)
+#define GPIO_PNOT11_PNOT114 (0x0010u)
+#define GPIO_PNOT11_PNOT115 (0x0020u)
+#define GPIO_PNOT11_PNOT116 (0x0040u)
+#define GPIO_PNOT11_PNOT117 (0x0080u)
+#define GPIO_PNOT11_PNOT118 (0x0100u)
+#define GPIO_PNOT11_PNOT119 (0x0200u)
+#define GPIO_PNOT11_PNOT1110 (0x0400u)
+#define GPIO_PNOT11_PNOT1111 (0x0800u)
+#define GPIO_PNOT11_PNOT1112 (0x1000u)
+#define GPIO_PNOT11_PNOT1113 (0x2000u)
+#define GPIO_PNOT11_PNOT1114 (0x4000u)
+#define GPIO_PNOT11_PNOT1115 (0x8000u)
+
+#define GPIO_PMSR11_PMSR110 (0x00000001uL)
+#define GPIO_PMSR11_PMSR111 (0x00000002uL)
+#define GPIO_PMSR11_PMSR112 (0x00000004uL)
+#define GPIO_PMSR11_PMSR113 (0x00000008uL)
+#define GPIO_PMSR11_PMSR114 (0x00000010uL)
+#define GPIO_PMSR11_PMSR115 (0x00000020uL)
+#define GPIO_PMSR11_PMSR116 (0x00000040uL)
+#define GPIO_PMSR11_PMSR117 (0x00000080uL)
+#define GPIO_PMSR11_PMSR118 (0x00000100uL)
+#define GPIO_PMSR11_PMSR119 (0x00000200uL)
+#define GPIO_PMSR11_PMSR1110 (0x00000400uL)
+#define GPIO_PMSR11_PMSR1111 (0x00000800uL)
+#define GPIO_PMSR11_PMSR1112 (0x00001000uL)
+#define GPIO_PMSR11_PMSR1113 (0x00002000uL)
+#define GPIO_PMSR11_PMSR1114 (0x00004000uL)
+#define GPIO_PMSR11_PMSR1115 (0x00008000uL)
+#define GPIO_PMSR11_PMSR1116 (0x00010000uL)
+#define GPIO_PMSR11_PMSR1117 (0x00020000uL)
+#define GPIO_PMSR11_PMSR1118 (0x00040000uL)
+#define GPIO_PMSR11_PMSR1119 (0x00080000uL)
+#define GPIO_PMSR11_PMSR1120 (0x00100000uL)
+#define GPIO_PMSR11_PMSR1121 (0x00200000uL)
+#define GPIO_PMSR11_PMSR1122 (0x00400000uL)
+#define GPIO_PMSR11_PMSR1123 (0x00800000uL)
+#define GPIO_PMSR11_PMSR1124 (0x01000000uL)
+#define GPIO_PMSR11_PMSR1125 (0x02000000uL)
+#define GPIO_PMSR11_PMSR1126 (0x04000000uL)
+#define GPIO_PMSR11_PMSR1127 (0x08000000uL)
+#define GPIO_PMSR11_PMSR1128 (0x10000000uL)
+#define GPIO_PMSR11_PMSR1129 (0x20000000uL)
+#define GPIO_PMSR11_PMSR1130 (0x40000000uL)
+#define GPIO_PMSR11_PMSR1131 (0x80000000uL)
+
+#define GPIO_PMCSR11_PMCSR110 (0x00000001uL)
+#define GPIO_PMCSR11_PMCSR111 (0x00000002uL)
+#define GPIO_PMCSR11_PMCSR112 (0x00000004uL)
+#define GPIO_PMCSR11_PMCSR113 (0x00000008uL)
+#define GPIO_PMCSR11_PMCSR114 (0x00000010uL)
+#define GPIO_PMCSR11_PMCSR115 (0x00000020uL)
+#define GPIO_PMCSR11_PMCSR116 (0x00000040uL)
+#define GPIO_PMCSR11_PMCSR117 (0x00000080uL)
+#define GPIO_PMCSR11_PMCSR118 (0x00000100uL)
+#define GPIO_PMCSR11_PMCSR119 (0x00000200uL)
+#define GPIO_PMCSR11_PMCSR1110 (0x00000400uL)
+#define GPIO_PMCSR11_PMCSR1111 (0x00000800uL)
+#define GPIO_PMCSR11_PMCSR1112 (0x00001000uL)
+#define GPIO_PMCSR11_PMCSR1113 (0x00002000uL)
+#define GPIO_PMCSR11_PMCSR1114 (0x00004000uL)
+#define GPIO_PMCSR11_PMCSR1115 (0x00008000uL)
+#define GPIO_PMCSR11_PMCSR1116 (0x00010000uL)
+#define GPIO_PMCSR11_PMCSR1117 (0x00020000uL)
+#define GPIO_PMCSR11_PMCSR1118 (0x00040000uL)
+#define GPIO_PMCSR11_PMCSR1119 (0x00080000uL)
+#define GPIO_PMCSR11_PMCSR1120 (0x00100000uL)
+#define GPIO_PMCSR11_PMCSR1121 (0x00200000uL)
+#define GPIO_PMCSR11_PMCSR1122 (0x00400000uL)
+#define GPIO_PMCSR11_PMCSR1123 (0x00800000uL)
+#define GPIO_PMCSR11_PMCSR1124 (0x01000000uL)
+#define GPIO_PMCSR11_PMCSR1125 (0x02000000uL)
+#define GPIO_PMCSR11_PMCSR1126 (0x04000000uL)
+#define GPIO_PMCSR11_PMCSR1127 (0x08000000uL)
+#define GPIO_PMCSR11_PMCSR1128 (0x10000000uL)
+#define GPIO_PMCSR11_PMCSR1129 (0x20000000uL)
+#define GPIO_PMCSR11_PMCSR1130 (0x40000000uL)
+#define GPIO_PMCSR11_PMCSR1131 (0x80000000uL)
+
+#define GPIO_PFCAE11_PFCAE110 (0x0001u)
+#define GPIO_PFCAE11_PFCAE111 (0x0002u)
+#define GPIO_PFCAE11_PFCAE112 (0x0004u)
+#define GPIO_PFCAE11_PFCAE113 (0x0008u)
+#define GPIO_PFCAE11_PFCAE114 (0x0010u)
+#define GPIO_PFCAE11_PFCAE115 (0x0020u)
+#define GPIO_PFCAE11_PFCAE116 (0x0040u)
+#define GPIO_PFCAE11_PFCAE117 (0x0080u)
+#define GPIO_PFCAE11_PFCAE118 (0x0100u)
+#define GPIO_PFCAE11_PFCAE119 (0x0200u)
+#define GPIO_PFCAE11_PFCAE1110 (0x0400u)
+#define GPIO_PFCAE11_PFCAE1111 (0x0800u)
+#define GPIO_PFCAE11_PFCAE1112 (0x1000u)
+#define GPIO_PFCAE11_PFCAE1113 (0x2000u)
+#define GPIO_PFCAE11_PFCAE1114 (0x4000u)
+#define GPIO_PFCAE11_PFCAE1115 (0x8000u)
+
+#define GPIO_PIBC11_PIBC110 (0x0001u)
+#define GPIO_PIBC11_PIBC111 (0x0002u)
+#define GPIO_PIBC11_PIBC112 (0x0004u)
+#define GPIO_PIBC11_PIBC113 (0x0008u)
+#define GPIO_PIBC11_PIBC114 (0x0010u)
+#define GPIO_PIBC11_PIBC115 (0x0020u)
+#define GPIO_PIBC11_PIBC116 (0x0040u)
+#define GPIO_PIBC11_PIBC117 (0x0080u)
+#define GPIO_PIBC11_PIBC118 (0x0100u)
+#define GPIO_PIBC11_PIBC119 (0x0200u)
+#define GPIO_PIBC11_PIBC1110 (0x0400u)
+#define GPIO_PIBC11_PIBC1111 (0x0800u)
+#define GPIO_PIBC11_PIBC1112 (0x1000u)
+#define GPIO_PIBC11_PIBC1113 (0x2000u)
+#define GPIO_PIBC11_PIBC1114 (0x4000u)
+#define GPIO_PIBC11_PIBC1115 (0x8000u)
+
+#define GPIO_PBDC11_PBDC110 (0x0001u)
+#define GPIO_PBDC11_PBDC111 (0x0002u)
+#define GPIO_PBDC11_PBDC112 (0x0004u)
+#define GPIO_PBDC11_PBDC113 (0x0008u)
+#define GPIO_PBDC11_PBDC114 (0x0010u)
+#define GPIO_PBDC11_PBDC115 (0x0020u)
+#define GPIO_PBDC11_PBDC116 (0x0040u)
+#define GPIO_PBDC11_PBDC117 (0x0080u)
+#define GPIO_PBDC11_PBDC118 (0x0100u)
+#define GPIO_PBDC11_PBDC119 (0x0200u)
+#define GPIO_PBDC11_PBDC1110 (0x0400u)
+#define GPIO_PBDC11_PBDC1111 (0x0800u)
+#define GPIO_PBDC11_PBDC1112 (0x1000u)
+#define GPIO_PBDC11_PBDC1113 (0x2000u)
+#define GPIO_PBDC11_PBDC1114 (0x4000u)
+#define GPIO_PBDC11_PBDC1115 (0x8000u)
+
+#define GPIO_PIPC11_PIPC110 (0x0001u)
+#define GPIO_PIPC11_PIPC111 (0x0002u)
+#define GPIO_PIPC11_PIPC112 (0x0004u)
+#define GPIO_PIPC11_PIPC113 (0x0008u)
+#define GPIO_PIPC11_PIPC114 (0x0010u)
+#define GPIO_PIPC11_PIPC115 (0x0020u)
+#define GPIO_PIPC11_PIPC116 (0x0040u)
+#define GPIO_PIPC11_PIPC117 (0x0080u)
+#define GPIO_PIPC11_PIPC118 (0x0100u)
+#define GPIO_PIPC11_PIPC119 (0x0200u)
+#define GPIO_PIPC11_PIPC1110 (0x0400u)
+#define GPIO_PIPC11_PIPC1111 (0x0800u)
+#define GPIO_PIPC11_PIPC1112 (0x1000u)
+#define GPIO_PIPC11_PIPC1113 (0x2000u)
+#define GPIO_PIPC11_PIPC1114 (0x4000u)
+#define GPIO_PIPC11_PIPC1115 (0x8000u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00_SHIFT (0u)
+#define GPIO_PPR0_PPR01_SHIFT (1u)
+#define GPIO_PPR0_PPR02_SHIFT (2u)
+#define GPIO_PPR0_PPR03_SHIFT (3u)
+#define GPIO_PPR0_PPR04_SHIFT (4u)
+#define GPIO_PPR0_PPR05_SHIFT (5u)
+
+#define GPIO_PMC0_PMC04_SHIFT (4u)
+#define GPIO_PMC0_PMC05_SHIFT (5u)
+
+#define GPIO_PMCSR0_PMCSR04_SHIFT (4u)
+#define GPIO_PMCSR0_PMCSR05_SHIFT (5u)
+
+#define GPIO_PIBC0_PIBC00_SHIFT (0u)
+#define GPIO_PIBC0_PIBC01_SHIFT (1u)
+#define GPIO_PIBC0_PIBC02_SHIFT (2u)
+#define GPIO_PIBC0_PIBC03_SHIFT (3u)
+#define GPIO_PIBC0_PIBC04_SHIFT (4u)
+#define GPIO_PIBC0_PIBC05_SHIFT (5u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10_SHIFT (0u)
+#define GPIO_P1_P11_SHIFT (1u)
+#define GPIO_P1_P12_SHIFT (2u)
+#define GPIO_P1_P13_SHIFT (3u)
+#define GPIO_P1_P14_SHIFT (4u)
+#define GPIO_P1_P15_SHIFT (5u)
+#define GPIO_P1_P16_SHIFT (6u)
+#define GPIO_P1_P17_SHIFT (7u)
+
+#define GPIO_PSR1_PSR10_SHIFT (0u)
+#define GPIO_PSR1_PSR11_SHIFT (1u)
+#define GPIO_PSR1_PSR12_SHIFT (2u)
+#define GPIO_PSR1_PSR13_SHIFT (3u)
+#define GPIO_PSR1_PSR14_SHIFT (4u)
+#define GPIO_PSR1_PSR15_SHIFT (5u)
+#define GPIO_PSR1_PSR16_SHIFT (6u)
+#define GPIO_PSR1_PSR17_SHIFT (7u)
+#define GPIO_PSR1_PSR116_SHIFT (16u)
+#define GPIO_PSR1_PSR117_SHIFT (17u)
+#define GPIO_PSR1_PSR118_SHIFT (18u)
+#define GPIO_PSR1_PSR119_SHIFT (19u)
+#define GPIO_PSR1_PSR120_SHIFT (20u)
+#define GPIO_PSR1_PSR121_SHIFT (21u)
+#define GPIO_PSR1_PSR122_SHIFT (22u)
+#define GPIO_PSR1_PSR123_SHIFT (23u)
+
+#define GPIO_PPR1_PPR10_SHIFT (0u)
+#define GPIO_PPR1_PPR11_SHIFT (1u)
+#define GPIO_PPR1_PPR12_SHIFT (2u)
+#define GPIO_PPR1_PPR13_SHIFT (3u)
+#define GPIO_PPR1_PPR14_SHIFT (4u)
+#define GPIO_PPR1_PPR15_SHIFT (5u)
+#define GPIO_PPR1_PPR16_SHIFT (6u)
+#define GPIO_PPR1_PPR17_SHIFT (7u)
+#define GPIO_PPR1_PPR18_SHIFT (8u)
+#define GPIO_PPR1_PPR19_SHIFT (9u)
+#define GPIO_PPR1_PPR110_SHIFT (10u)
+#define GPIO_PPR1_PPR111_SHIFT (11u)
+#define GPIO_PPR1_PPR112_SHIFT (12u)
+#define GPIO_PPR1_PPR113_SHIFT (13u)
+#define GPIO_PPR1_PPR114_SHIFT (14u)
+#define GPIO_PPR1_PPR115_SHIFT (15u)
+
+#define GPIO_PM1_PM10_SHIFT (0u)
+#define GPIO_PM1_PM11_SHIFT (1u)
+#define GPIO_PM1_PM12_SHIFT (2u)
+#define GPIO_PM1_PM13_SHIFT (3u)
+#define GPIO_PM1_PM14_SHIFT (4u)
+#define GPIO_PM1_PM15_SHIFT (5u)
+#define GPIO_PM1_PM16_SHIFT (6u)
+#define GPIO_PM1_PM17_SHIFT (7u)
+
+#define GPIO_PMC1_PMC10_SHIFT (0u)
+#define GPIO_PMC1_PMC11_SHIFT (1u)
+#define GPIO_PMC1_PMC12_SHIFT (2u)
+#define GPIO_PMC1_PMC13_SHIFT (3u)
+#define GPIO_PMC1_PMC14_SHIFT (4u)
+#define GPIO_PMC1_PMC15_SHIFT (5u)
+#define GPIO_PMC1_PMC16_SHIFT (6u)
+#define GPIO_PMC1_PMC17_SHIFT (7u)
+#define GPIO_PMC1_PMC18_SHIFT (8u)
+#define GPIO_PMC1_PMC19_SHIFT (9u)
+#define GPIO_PMC1_PMC110_SHIFT (10u)
+#define GPIO_PMC1_PMC111_SHIFT (11u)
+#define GPIO_PMC1_PMC112_SHIFT (12u)
+#define GPIO_PMC1_PMC113_SHIFT (13u)
+#define GPIO_PMC1_PMC114_SHIFT (14u)
+#define GPIO_PMC1_PMC115_SHIFT (15u)
+
+#define GPIO_PFC1_PFC10_SHIFT (0u)
+#define GPIO_PFC1_PFC11_SHIFT (1u)
+#define GPIO_PFC1_PFC12_SHIFT (2u)
+#define GPIO_PFC1_PFC13_SHIFT (3u)
+#define GPIO_PFC1_PFC14_SHIFT (4u)
+#define GPIO_PFC1_PFC15_SHIFT (5u)
+#define GPIO_PFC1_PFC16_SHIFT (6u)
+#define GPIO_PFC1_PFC17_SHIFT (7u)
+#define GPIO_PFC1_PFC18_SHIFT (8u)
+#define GPIO_PFC1_PFC19_SHIFT (9u)
+#define GPIO_PFC1_PFC110_SHIFT (10u)
+#define GPIO_PFC1_PFC111_SHIFT (11u)
+#define GPIO_PFC1_PFC112_SHIFT (12u)
+#define GPIO_PFC1_PFC113_SHIFT (13u)
+#define GPIO_PFC1_PFC114_SHIFT (14u)
+#define GPIO_PFC1_PFC115_SHIFT (15u)
+
+#define GPIO_PFCE1_PFCE10_SHIFT (0u)
+#define GPIO_PFCE1_PFCE11_SHIFT (1u)
+#define GPIO_PFCE1_PFCE12_SHIFT (2u)
+#define GPIO_PFCE1_PFCE13_SHIFT (3u)
+#define GPIO_PFCE1_PFCE14_SHIFT (4u)
+#define GPIO_PFCE1_PFCE15_SHIFT (5u)
+#define GPIO_PFCE1_PFCE16_SHIFT (6u)
+#define GPIO_PFCE1_PFCE17_SHIFT (7u)
+#define GPIO_PFCE1_PFCE18_SHIFT (8u)
+#define GPIO_PFCE1_PFCE19_SHIFT (9u)
+#define GPIO_PFCE1_PFCE110_SHIFT (10u)
+#define GPIO_PFCE1_PFCE111_SHIFT (11u)
+#define GPIO_PFCE1_PFCE112_SHIFT (12u)
+#define GPIO_PFCE1_PFCE113_SHIFT (13u)
+#define GPIO_PFCE1_PFCE114_SHIFT (14u)
+#define GPIO_PFCE1_PFCE115_SHIFT (15u)
+
+#define GPIO_PNOT1_PNOT10_SHIFT (0u)
+#define GPIO_PNOT1_PNOT11_SHIFT (1u)
+#define GPIO_PNOT1_PNOT12_SHIFT (2u)
+#define GPIO_PNOT1_PNOT13_SHIFT (3u)
+#define GPIO_PNOT1_PNOT14_SHIFT (4u)
+#define GPIO_PNOT1_PNOT15_SHIFT (5u)
+#define GPIO_PNOT1_PNOT16_SHIFT (6u)
+#define GPIO_PNOT1_PNOT17_SHIFT (7u)
+
+#define GPIO_PMSR1_PMSR10_SHIFT (0u)
+#define GPIO_PMSR1_PMSR11_SHIFT (1u)
+#define GPIO_PMSR1_PMSR12_SHIFT (2u)
+#define GPIO_PMSR1_PMSR13_SHIFT (3u)
+#define GPIO_PMSR1_PMSR14_SHIFT (4u)
+#define GPIO_PMSR1_PMSR15_SHIFT (5u)
+#define GPIO_PMSR1_PMSR16_SHIFT (6u)
+#define GPIO_PMSR1_PMSR17_SHIFT (7u)
+#define GPIO_PMSR1_PMSR116_SHIFT (16u)
+#define GPIO_PMSR1_PMSR117_SHIFT (17u)
+#define GPIO_PMSR1_PMSR118_SHIFT (18u)
+#define GPIO_PMSR1_PMSR119_SHIFT (19u)
+#define GPIO_PMSR1_PMSR120_SHIFT (20u)
+#define GPIO_PMSR1_PMSR121_SHIFT (21u)
+#define GPIO_PMSR1_PMSR122_SHIFT (22u)
+#define GPIO_PMSR1_PMSR123_SHIFT (23u)
+
+#define GPIO_PMCSR1_PMCSR10_SHIFT (0u)
+#define GPIO_PMCSR1_PMCSR11_SHIFT (1u)
+#define GPIO_PMCSR1_PMCSR12_SHIFT (2u)
+#define GPIO_PMCSR1_PMCSR13_SHIFT (3u)
+#define GPIO_PMCSR1_PMCSR14_SHIFT (4u)
+#define GPIO_PMCSR1_PMCSR15_SHIFT (5u)
+#define GPIO_PMCSR1_PMCSR16_SHIFT (6u)
+#define GPIO_PMCSR1_PMCSR17_SHIFT (7u)
+#define GPIO_PMCSR1_PMCSR116_SHIFT (16u)
+#define GPIO_PMCSR1_PMCSR117_SHIFT (17u)
+#define GPIO_PMCSR1_PMCSR118_SHIFT (18u)
+#define GPIO_PMCSR1_PMCSR119_SHIFT (19u)
+#define GPIO_PMCSR1_PMCSR120_SHIFT (20u)
+#define GPIO_PMCSR1_PMCSR121_SHIFT (21u)
+#define GPIO_PMCSR1_PMCSR122_SHIFT (22u)
+#define GPIO_PMCSR1_PMCSR123_SHIFT (23u)
+
+#define GPIO_PFCAE1_PFCAE10_SHIFT (0u)
+#define GPIO_PFCAE1_PFCAE11_SHIFT (1u)
+#define GPIO_PFCAE1_PFCAE12_SHIFT (2u)
+#define GPIO_PFCAE1_PFCAE13_SHIFT (3u)
+#define GPIO_PFCAE1_PFCAE14_SHIFT (4u)
+#define GPIO_PFCAE1_PFCAE15_SHIFT (5u)
+#define GPIO_PFCAE1_PFCAE16_SHIFT (6u)
+#define GPIO_PFCAE1_PFCAE17_SHIFT (7u)
+#define GPIO_PFCAE1_PFCAE18_SHIFT (8u)
+#define GPIO_PFCAE1_PFCAE19_SHIFT (9u)
+#define GPIO_PFCAE1_PFCAE110_SHIFT (10u)
+#define GPIO_PFCAE1_PFCAE111_SHIFT (11u)
+#define GPIO_PFCAE1_PFCAE112_SHIFT (12u)
+#define GPIO_PFCAE1_PFCAE113_SHIFT (13u)
+#define GPIO_PFCAE1_PFCAE114_SHIFT (14u)
+#define GPIO_PFCAE1_PFCAE115_SHIFT (15u)
+
+#define GPIO_PIBC1_PIBC10_SHIFT (0u)
+#define GPIO_PIBC1_PIBC11_SHIFT (1u)
+#define GPIO_PIBC1_PIBC12_SHIFT (2u)
+#define GPIO_PIBC1_PIBC13_SHIFT (3u)
+#define GPIO_PIBC1_PIBC14_SHIFT (4u)
+#define GPIO_PIBC1_PIBC15_SHIFT (5u)
+#define GPIO_PIBC1_PIBC16_SHIFT (6u)
+#define GPIO_PIBC1_PIBC17_SHIFT (7u)
+#define GPIO_PIBC1_PIBC18_SHIFT (8u)
+#define GPIO_PIBC1_PIBC19_SHIFT (9u)
+#define GPIO_PIBC1_PIBC110_SHIFT (10u)
+#define GPIO_PIBC1_PIBC111_SHIFT (11u)
+#define GPIO_PIBC1_PIBC112_SHIFT (12u)
+#define GPIO_PIBC1_PIBC113_SHIFT (13u)
+#define GPIO_PIBC1_PIBC114_SHIFT (14u)
+#define GPIO_PIBC1_PIBC115_SHIFT (15u)
+
+#define GPIO_PBDC1_PBDC10_SHIFT (0u)
+#define GPIO_PBDC1_PBDC11_SHIFT (1u)
+#define GPIO_PBDC1_PBDC12_SHIFT (2u)
+#define GPIO_PBDC1_PBDC13_SHIFT (3u)
+#define GPIO_PBDC1_PBDC14_SHIFT (4u)
+#define GPIO_PBDC1_PBDC15_SHIFT (5u)
+#define GPIO_PBDC1_PBDC16_SHIFT (6u)
+#define GPIO_PBDC1_PBDC17_SHIFT (7u)
+#define GPIO_PBDC1_PBDC18_SHIFT (8u)
+#define GPIO_PBDC1_PBDC19_SHIFT (9u)
+#define GPIO_PBDC1_PBDC110_SHIFT (10u)
+#define GPIO_PBDC1_PBDC111_SHIFT (11u)
+#define GPIO_PBDC1_PBDC112_SHIFT (12u)
+#define GPIO_PBDC1_PBDC113_SHIFT (13u)
+#define GPIO_PBDC1_PBDC114_SHIFT (14u)
+#define GPIO_PBDC1_PBDC115_SHIFT (15u)
+
+#define GPIO_PIPC1_PIPC10_SHIFT (0u)
+#define GPIO_PIPC1_PIPC11_SHIFT (1u)
+#define GPIO_PIPC1_PIPC12_SHIFT (2u)
+#define GPIO_PIPC1_PIPC13_SHIFT (3u)
+#define GPIO_PIPC1_PIPC14_SHIFT (4u)
+#define GPIO_PIPC1_PIPC15_SHIFT (5u)
+#define GPIO_PIPC1_PIPC16_SHIFT (6u)
+#define GPIO_PIPC1_PIPC17_SHIFT (7u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20_SHIFT (0u)
+#define GPIO_P2_P21_SHIFT (1u)
+#define GPIO_P2_P22_SHIFT (2u)
+#define GPIO_P2_P23_SHIFT (3u)
+#define GPIO_P2_P24_SHIFT (4u)
+#define GPIO_P2_P25_SHIFT (5u)
+#define GPIO_P2_P26_SHIFT (6u)
+#define GPIO_P2_P27_SHIFT (7u)
+#define GPIO_P2_P28_SHIFT (8u)
+#define GPIO_P2_P29_SHIFT (9u)
+#define GPIO_P2_P210_SHIFT (10u)
+#define GPIO_P2_P211_SHIFT (11u)
+#define GPIO_P2_P212_SHIFT (12u)
+#define GPIO_P2_P213_SHIFT (13u)
+#define GPIO_P2_P214_SHIFT (14u)
+#define GPIO_P2_P215_SHIFT (15u)
+
+#define GPIO_PSR2_PSR20_SHIFT (0u)
+#define GPIO_PSR2_PSR21_SHIFT (1u)
+#define GPIO_PSR2_PSR22_SHIFT (2u)
+#define GPIO_PSR2_PSR23_SHIFT (3u)
+#define GPIO_PSR2_PSR24_SHIFT (4u)
+#define GPIO_PSR2_PSR25_SHIFT (5u)
+#define GPIO_PSR2_PSR26_SHIFT (6u)
+#define GPIO_PSR2_PSR27_SHIFT (7u)
+#define GPIO_PSR2_PSR28_SHIFT (8u)
+#define GPIO_PSR2_PSR29_SHIFT (9u)
+#define GPIO_PSR2_PSR210_SHIFT (10u)
+#define GPIO_PSR2_PSR211_SHIFT (11u)
+#define GPIO_PSR2_PSR212_SHIFT (12u)
+#define GPIO_PSR2_PSR213_SHIFT (13u)
+#define GPIO_PSR2_PSR214_SHIFT (14u)
+#define GPIO_PSR2_PSR215_SHIFT (15u)
+#define GPIO_PSR2_PSR216_SHIFT (16u)
+#define GPIO_PSR2_PSR217_SHIFT (17u)
+#define GPIO_PSR2_PSR218_SHIFT (18u)
+#define GPIO_PSR2_PSR219_SHIFT (19u)
+#define GPIO_PSR2_PSR220_SHIFT (20u)
+#define GPIO_PSR2_PSR221_SHIFT (21u)
+#define GPIO_PSR2_PSR222_SHIFT (22u)
+#define GPIO_PSR2_PSR223_SHIFT (23u)
+#define GPIO_PSR2_PSR224_SHIFT (24u)
+#define GPIO_PSR2_PSR225_SHIFT (25u)
+#define GPIO_PSR2_PSR226_SHIFT (26u)
+#define GPIO_PSR2_PSR227_SHIFT (27u)
+#define GPIO_PSR2_PSR228_SHIFT (28u)
+#define GPIO_PSR2_PSR229_SHIFT (29u)
+#define GPIO_PSR2_PSR230_SHIFT (30u)
+#define GPIO_PSR2_PSR231_SHIFT (31u)
+
+#define GPIO_PPR2_PPR20_SHIFT (0u)
+#define GPIO_PPR2_PPR21_SHIFT (1u)
+#define GPIO_PPR2_PPR22_SHIFT (2u)
+#define GPIO_PPR2_PPR23_SHIFT (3u)
+#define GPIO_PPR2_PPR24_SHIFT (4u)
+#define GPIO_PPR2_PPR25_SHIFT (5u)
+#define GPIO_PPR2_PPR26_SHIFT (6u)
+#define GPIO_PPR2_PPR27_SHIFT (7u)
+#define GPIO_PPR2_PPR28_SHIFT (8u)
+#define GPIO_PPR2_PPR29_SHIFT (9u)
+#define GPIO_PPR2_PPR210_SHIFT (10u)
+#define GPIO_PPR2_PPR211_SHIFT (11u)
+#define GPIO_PPR2_PPR212_SHIFT (12u)
+#define GPIO_PPR2_PPR213_SHIFT (13u)
+#define GPIO_PPR2_PPR214_SHIFT (14u)
+#define GPIO_PPR2_PPR215_SHIFT (15u)
+
+#define GPIO_PM2_PM20_SHIFT (0u)
+#define GPIO_PM2_PM21_SHIFT (1u)
+#define GPIO_PM2_PM22_SHIFT (2u)
+#define GPIO_PM2_PM23_SHIFT (3u)
+#define GPIO_PM2_PM24_SHIFT (4u)
+#define GPIO_PM2_PM25_SHIFT (5u)
+#define GPIO_PM2_PM26_SHIFT (6u)
+#define GPIO_PM2_PM27_SHIFT (7u)
+#define GPIO_PM2_PM28_SHIFT (8u)
+#define GPIO_PM2_PM29_SHIFT (9u)
+#define GPIO_PM2_PM210_SHIFT (10u)
+#define GPIO_PM2_PM211_SHIFT (11u)
+#define GPIO_PM2_PM212_SHIFT (12u)
+#define GPIO_PM2_PM213_SHIFT (13u)
+#define GPIO_PM2_PM214_SHIFT (14u)
+#define GPIO_PM2_PM215_SHIFT (15u)
+
+#define GPIO_PMC2_PMC20_SHIFT (0u)
+#define GPIO_PMC2_PMC21_SHIFT (1u)
+#define GPIO_PMC2_PMC22_SHIFT (2u)
+#define GPIO_PMC2_PMC23_SHIFT (3u)
+#define GPIO_PMC2_PMC24_SHIFT (4u)
+#define GPIO_PMC2_PMC25_SHIFT (5u)
+#define GPIO_PMC2_PMC26_SHIFT (6u)
+#define GPIO_PMC2_PMC27_SHIFT (7u)
+#define GPIO_PMC2_PMC28_SHIFT (8u)
+#define GPIO_PMC2_PMC29_SHIFT (9u)
+#define GPIO_PMC2_PMC210_SHIFT (10u)
+#define GPIO_PMC2_PMC211_SHIFT (11u)
+#define GPIO_PMC2_PMC212_SHIFT (12u)
+#define GPIO_PMC2_PMC213_SHIFT (13u)
+#define GPIO_PMC2_PMC214_SHIFT (14u)
+#define GPIO_PMC2_PMC215_SHIFT (15u)
+
+#define GPIO_PFC2_PFC20_SHIFT (0u)
+#define GPIO_PFC2_PFC21_SHIFT (1u)
+#define GPIO_PFC2_PFC22_SHIFT (2u)
+#define GPIO_PFC2_PFC23_SHIFT (3u)
+#define GPIO_PFC2_PFC24_SHIFT (4u)
+#define GPIO_PFC2_PFC25_SHIFT (5u)
+#define GPIO_PFC2_PFC26_SHIFT (6u)
+#define GPIO_PFC2_PFC27_SHIFT (7u)
+#define GPIO_PFC2_PFC28_SHIFT (8u)
+#define GPIO_PFC2_PFC29_SHIFT (9u)
+#define GPIO_PFC2_PFC210_SHIFT (10u)
+#define GPIO_PFC2_PFC211_SHIFT (11u)
+#define GPIO_PFC2_PFC212_SHIFT (12u)
+#define GPIO_PFC2_PFC213_SHIFT (13u)
+#define GPIO_PFC2_PFC214_SHIFT (14u)
+#define GPIO_PFC2_PFC215_SHIFT (15u)
+
+#define GPIO_PFCE2_PFCE20_SHIFT (0u)
+#define GPIO_PFCE2_PFCE21_SHIFT (1u)
+#define GPIO_PFCE2_PFCE22_SHIFT (2u)
+#define GPIO_PFCE2_PFCE23_SHIFT (3u)
+#define GPIO_PFCE2_PFCE24_SHIFT (4u)
+#define GPIO_PFCE2_PFCE25_SHIFT (5u)
+#define GPIO_PFCE2_PFCE26_SHIFT (6u)
+#define GPIO_PFCE2_PFCE27_SHIFT (7u)
+#define GPIO_PFCE2_PFCE28_SHIFT (8u)
+#define GPIO_PFCE2_PFCE29_SHIFT (9u)
+#define GPIO_PFCE2_PFCE210_SHIFT (10u)
+#define GPIO_PFCE2_PFCE211_SHIFT (11u)
+#define GPIO_PFCE2_PFCE212_SHIFT (12u)
+#define GPIO_PFCE2_PFCE213_SHIFT (13u)
+#define GPIO_PFCE2_PFCE214_SHIFT (14u)
+#define GPIO_PFCE2_PFCE215_SHIFT (15u)
+
+#define GPIO_PNOT2_PNOT20_SHIFT (0u)
+#define GPIO_PNOT2_PNOT21_SHIFT (1u)
+#define GPIO_PNOT2_PNOT22_SHIFT (2u)
+#define GPIO_PNOT2_PNOT23_SHIFT (3u)
+#define GPIO_PNOT2_PNOT24_SHIFT (4u)
+#define GPIO_PNOT2_PNOT25_SHIFT (5u)
+#define GPIO_PNOT2_PNOT26_SHIFT (6u)
+#define GPIO_PNOT2_PNOT27_SHIFT (7u)
+#define GPIO_PNOT2_PNOT28_SHIFT (8u)
+#define GPIO_PNOT2_PNOT29_SHIFT (9u)
+#define GPIO_PNOT2_PNOT210_SHIFT (10u)
+#define GPIO_PNOT2_PNOT211_SHIFT (11u)
+#define GPIO_PNOT2_PNOT212_SHIFT (12u)
+#define GPIO_PNOT2_PNOT213_SHIFT (13u)
+#define GPIO_PNOT2_PNOT214_SHIFT (14u)
+#define GPIO_PNOT2_PNOT215_SHIFT (15u)
+
+#define GPIO_PMSR2_PMSR20_SHIFT (0u)
+#define GPIO_PMSR2_PMSR21_SHIFT (1u)
+#define GPIO_PMSR2_PMSR22_SHIFT (2u)
+#define GPIO_PMSR2_PMSR23_SHIFT (3u)
+#define GPIO_PMSR2_PMSR24_SHIFT (4u)
+#define GPIO_PMSR2_PMSR25_SHIFT (5u)
+#define GPIO_PMSR2_PMSR26_SHIFT (6u)
+#define GPIO_PMSR2_PMSR27_SHIFT (7u)
+#define GPIO_PMSR2_PMSR28_SHIFT (8u)
+#define GPIO_PMSR2_PMSR29_SHIFT (9u)
+#define GPIO_PMSR2_PMSR210_SHIFT (10u)
+#define GPIO_PMSR2_PMSR211_SHIFT (11u)
+#define GPIO_PMSR2_PMSR212_SHIFT (12u)
+#define GPIO_PMSR2_PMSR213_SHIFT (13u)
+#define GPIO_PMSR2_PMSR214_SHIFT (14u)
+#define GPIO_PMSR2_PMSR215_SHIFT (15u)
+#define GPIO_PMSR2_PMSR216_SHIFT (16u)
+#define GPIO_PMSR2_PMSR217_SHIFT (17u)
+#define GPIO_PMSR2_PMSR218_SHIFT (18u)
+#define GPIO_PMSR2_PMSR219_SHIFT (19u)
+#define GPIO_PMSR2_PMSR220_SHIFT (20u)
+#define GPIO_PMSR2_PMSR221_SHIFT (21u)
+#define GPIO_PMSR2_PMSR222_SHIFT (22u)
+#define GPIO_PMSR2_PMSR223_SHIFT (23u)
+#define GPIO_PMSR2_PMSR224_SHIFT (24u)
+#define GPIO_PMSR2_PMSR225_SHIFT (25u)
+#define GPIO_PMSR2_PMSR226_SHIFT (26u)
+#define GPIO_PMSR2_PMSR227_SHIFT (27u)
+#define GPIO_PMSR2_PMSR228_SHIFT (28u)
+#define GPIO_PMSR2_PMSR229_SHIFT (29u)
+#define GPIO_PMSR2_PMSR230_SHIFT (30u)
+#define GPIO_PMSR2_PMSR231_SHIFT (31u)
+
+#define GPIO_PMCSR2_PMCSR20_SHIFT (0u)
+#define GPIO_PMCSR2_PMCSR21_SHIFT (1u)
+#define GPIO_PMCSR2_PMCSR22_SHIFT (2u)
+#define GPIO_PMCSR2_PMCSR23_SHIFT (3u)
+#define GPIO_PMCSR2_PMCSR24_SHIFT (4u)
+#define GPIO_PMCSR2_PMCSR25_SHIFT (5u)
+#define GPIO_PMCSR2_PMCSR26_SHIFT (6u)
+#define GPIO_PMCSR2_PMCSR27_SHIFT (7u)
+#define GPIO_PMCSR2_PMCSR28_SHIFT (8u)
+#define GPIO_PMCSR2_PMCSR29_SHIFT (9u)
+#define GPIO_PMCSR2_PMCSR210_SHIFT (10u)
+#define GPIO_PMCSR2_PMCSR211_SHIFT (11u)
+#define GPIO_PMCSR2_PMCSR212_SHIFT (12u)
+#define GPIO_PMCSR2_PMCSR213_SHIFT (13u)
+#define GPIO_PMCSR2_PMCSR214_SHIFT (14u)
+#define GPIO_PMCSR2_PMCSR215_SHIFT (15u)
+#define GPIO_PMCSR2_PMCSR216_SHIFT (16u)
+#define GPIO_PMCSR2_PMCSR217_SHIFT (17u)
+#define GPIO_PMCSR2_PMCSR218_SHIFT (18u)
+#define GPIO_PMCSR2_PMCSR219_SHIFT (19u)
+#define GPIO_PMCSR2_PMCSR220_SHIFT (20u)
+#define GPIO_PMCSR2_PMCSR221_SHIFT (21u)
+#define GPIO_PMCSR2_PMCSR222_SHIFT (22u)
+#define GPIO_PMCSR2_PMCSR223_SHIFT (23u)
+#define GPIO_PMCSR2_PMCSR224_SHIFT (24u)
+#define GPIO_PMCSR2_PMCSR225_SHIFT (25u)
+#define GPIO_PMCSR2_PMCSR226_SHIFT (26u)
+#define GPIO_PMCSR2_PMCSR227_SHIFT (27u)
+#define GPIO_PMCSR2_PMCSR228_SHIFT (28u)
+#define GPIO_PMCSR2_PMCSR229_SHIFT (29u)
+#define GPIO_PMCSR2_PMCSR230_SHIFT (30u)
+#define GPIO_PMCSR2_PMCSR231_SHIFT (31u)
+
+#define GPIO_PFCAE2_PFCAE20_SHIFT (0u)
+#define GPIO_PFCAE2_PFCAE21_SHIFT (1u)
+#define GPIO_PFCAE2_PFCAE22_SHIFT (2u)
+#define GPIO_PFCAE2_PFCAE23_SHIFT (3u)
+#define GPIO_PFCAE2_PFCAE24_SHIFT (4u)
+#define GPIO_PFCAE2_PFCAE25_SHIFT (5u)
+#define GPIO_PFCAE2_PFCAE26_SHIFT (6u)
+#define GPIO_PFCAE2_PFCAE27_SHIFT (7u)
+#define GPIO_PFCAE2_PFCAE28_SHIFT (8u)
+#define GPIO_PFCAE2_PFCAE29_SHIFT (9u)
+#define GPIO_PFCAE2_PFCAE210_SHIFT (10u)
+#define GPIO_PFCAE2_PFCAE211_SHIFT (11u)
+#define GPIO_PFCAE2_PFCAE212_SHIFT (12u)
+#define GPIO_PFCAE2_PFCAE213_SHIFT (13u)
+#define GPIO_PFCAE2_PFCAE214_SHIFT (14u)
+#define GPIO_PFCAE2_PFCAE215_SHIFT (15u)
+
+#define GPIO_PIBC2_PIBC20_SHIFT (0u)
+#define GPIO_PIBC2_PIBC21_SHIFT (1u)
+#define GPIO_PIBC2_PIBC22_SHIFT (2u)
+#define GPIO_PIBC2_PIBC23_SHIFT (3u)
+#define GPIO_PIBC2_PIBC24_SHIFT (4u)
+#define GPIO_PIBC2_PIBC25_SHIFT (5u)
+#define GPIO_PIBC2_PIBC26_SHIFT (6u)
+#define GPIO_PIBC2_PIBC27_SHIFT (7u)
+#define GPIO_PIBC2_PIBC28_SHIFT (8u)
+#define GPIO_PIBC2_PIBC29_SHIFT (9u)
+#define GPIO_PIBC2_PIBC210_SHIFT (10u)
+#define GPIO_PIBC2_PIBC211_SHIFT (11u)
+#define GPIO_PIBC2_PIBC212_SHIFT (12u)
+#define GPIO_PIBC2_PIBC213_SHIFT (13u)
+#define GPIO_PIBC2_PIBC214_SHIFT (14u)
+#define GPIO_PIBC2_PIBC215_SHIFT (15u)
+
+#define GPIO_PBDC2_PBDC20_SHIFT (0u)
+#define GPIO_PBDC2_PBDC21_SHIFT (1u)
+#define GPIO_PBDC2_PBDC22_SHIFT (2u)
+#define GPIO_PBDC2_PBDC23_SHIFT (3u)
+#define GPIO_PBDC2_PBDC24_SHIFT (4u)
+#define GPIO_PBDC2_PBDC25_SHIFT (5u)
+#define GPIO_PBDC2_PBDC26_SHIFT (6u)
+#define GPIO_PBDC2_PBDC27_SHIFT (7u)
+#define GPIO_PBDC2_PBDC28_SHIFT (8u)
+#define GPIO_PBDC2_PBDC29_SHIFT (9u)
+#define GPIO_PBDC2_PBDC210_SHIFT (10u)
+#define GPIO_PBDC2_PBDC211_SHIFT (11u)
+#define GPIO_PBDC2_PBDC212_SHIFT (12u)
+#define GPIO_PBDC2_PBDC213_SHIFT (13u)
+#define GPIO_PBDC2_PBDC214_SHIFT (14u)
+#define GPIO_PBDC2_PBDC215_SHIFT (15u)
+
+#define GPIO_PIPC2_PIPC20_SHIFT (0u)
+#define GPIO_PIPC2_PIPC21_SHIFT (1u)
+#define GPIO_PIPC2_PIPC22_SHIFT (2u)
+#define GPIO_PIPC2_PIPC23_SHIFT (3u)
+#define GPIO_PIPC2_PIPC24_SHIFT (4u)
+#define GPIO_PIPC2_PIPC25_SHIFT (5u)
+#define GPIO_PIPC2_PIPC26_SHIFT (6u)
+#define GPIO_PIPC2_PIPC27_SHIFT (7u)
+#define GPIO_PIPC2_PIPC28_SHIFT (8u)
+#define GPIO_PIPC2_PIPC29_SHIFT (9u)
+#define GPIO_PIPC2_PIPC210_SHIFT (10u)
+#define GPIO_PIPC2_PIPC211_SHIFT (11u)
+#define GPIO_PIPC2_PIPC212_SHIFT (12u)
+#define GPIO_PIPC2_PIPC213_SHIFT (13u)
+#define GPIO_PIPC2_PIPC214_SHIFT (14u)
+#define GPIO_PIPC2_PIPC215_SHIFT (15u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30_SHIFT (0u)
+#define GPIO_P3_P31_SHIFT (1u)
+#define GPIO_P3_P32_SHIFT (2u)
+#define GPIO_P3_P33_SHIFT (3u)
+#define GPIO_P3_P34_SHIFT (4u)
+#define GPIO_P3_P35_SHIFT (5u)
+#define GPIO_P3_P36_SHIFT (6u)
+#define GPIO_P3_P37_SHIFT (7u)
+#define GPIO_P3_P38_SHIFT (8u)
+#define GPIO_P3_P39_SHIFT (9u)
+#define GPIO_P3_P310_SHIFT (10u)
+#define GPIO_P3_P311_SHIFT (11u)
+#define GPIO_P3_P312_SHIFT (12u)
+#define GPIO_P3_P313_SHIFT (13u)
+#define GPIO_P3_P314_SHIFT (14u)
+#define GPIO_P3_P315_SHIFT (15u)
+
+#define GPIO_PSR3_PSR30_SHIFT (0u)
+#define GPIO_PSR3_PSR31_SHIFT (1u)
+#define GPIO_PSR3_PSR32_SHIFT (2u)
+#define GPIO_PSR3_PSR33_SHIFT (3u)
+#define GPIO_PSR3_PSR34_SHIFT (4u)
+#define GPIO_PSR3_PSR35_SHIFT (5u)
+#define GPIO_PSR3_PSR36_SHIFT (6u)
+#define GPIO_PSR3_PSR37_SHIFT (7u)
+#define GPIO_PSR3_PSR38_SHIFT (8u)
+#define GPIO_PSR3_PSR39_SHIFT (9u)
+#define GPIO_PSR3_PSR310_SHIFT (10u)
+#define GPIO_PSR3_PSR311_SHIFT (11u)
+#define GPIO_PSR3_PSR312_SHIFT (12u)
+#define GPIO_PSR3_PSR313_SHIFT (13u)
+#define GPIO_PSR3_PSR314_SHIFT (14u)
+#define GPIO_PSR3_PSR315_SHIFT (15u)
+#define GPIO_PSR3_PSR316_SHIFT (16u)
+#define GPIO_PSR3_PSR317_SHIFT (17u)
+#define GPIO_PSR3_PSR318_SHIFT (18u)
+#define GPIO_PSR3_PSR319_SHIFT (19u)
+#define GPIO_PSR3_PSR320_SHIFT (20u)
+#define GPIO_PSR3_PSR321_SHIFT (21u)
+#define GPIO_PSR3_PSR322_SHIFT (22u)
+#define GPIO_PSR3_PSR323_SHIFT (23u)
+#define GPIO_PSR3_PSR324_SHIFT (24u)
+#define GPIO_PSR3_PSR325_SHIFT (25u)
+#define GPIO_PSR3_PSR326_SHIFT (26u)
+#define GPIO_PSR3_PSR327_SHIFT (27u)
+#define GPIO_PSR3_PSR328_SHIFT (28u)
+#define GPIO_PSR3_PSR329_SHIFT (29u)
+#define GPIO_PSR3_PSR330_SHIFT (30u)
+#define GPIO_PSR3_PSR331_SHIFT (31u)
+
+#define GPIO_PPR3_PPR30_SHIFT (0u)
+#define GPIO_PPR3_PPR31_SHIFT (1u)
+#define GPIO_PPR3_PPR32_SHIFT (2u)
+#define GPIO_PPR3_PPR33_SHIFT (3u)
+#define GPIO_PPR3_PPR34_SHIFT (4u)
+#define GPIO_PPR3_PPR35_SHIFT (5u)
+#define GPIO_PPR3_PPR36_SHIFT (6u)
+#define GPIO_PPR3_PPR37_SHIFT (7u)
+#define GPIO_PPR3_PPR38_SHIFT (8u)
+#define GPIO_PPR3_PPR39_SHIFT (9u)
+#define GPIO_PPR3_PPR310_SHIFT (10u)
+#define GPIO_PPR3_PPR311_SHIFT (11u)
+#define GPIO_PPR3_PPR312_SHIFT (12u)
+#define GPIO_PPR3_PPR313_SHIFT (13u)
+#define GPIO_PPR3_PPR314_SHIFT (14u)
+#define GPIO_PPR3_PPR315_SHIFT (15u)
+
+#define GPIO_PM3_PM30_SHIFT (0u)
+#define GPIO_PM3_PM31_SHIFT (1u)
+#define GPIO_PM3_PM32_SHIFT (2u)
+#define GPIO_PM3_PM33_SHIFT (3u)
+#define GPIO_PM3_PM34_SHIFT (4u)
+#define GPIO_PM3_PM35_SHIFT (5u)
+#define GPIO_PM3_PM36_SHIFT (6u)
+#define GPIO_PM3_PM37_SHIFT (7u)
+#define GPIO_PM3_PM38_SHIFT (8u)
+#define GPIO_PM3_PM39_SHIFT (9u)
+#define GPIO_PM3_PM310_SHIFT (10u)
+#define GPIO_PM3_PM311_SHIFT (11u)
+#define GPIO_PM3_PM312_SHIFT (12u)
+#define GPIO_PM3_PM313_SHIFT (13u)
+#define GPIO_PM3_PM314_SHIFT (14u)
+#define GPIO_PM3_PM315_SHIFT (15u)
+
+#define GPIO_PMC3_PMC30_SHIFT (0u)
+#define GPIO_PMC3_PMC31_SHIFT (1u)
+#define GPIO_PMC3_PMC32_SHIFT (2u)
+#define GPIO_PMC3_PMC33_SHIFT (3u)
+#define GPIO_PMC3_PMC34_SHIFT (4u)
+#define GPIO_PMC3_PMC35_SHIFT (5u)
+#define GPIO_PMC3_PMC36_SHIFT (6u)
+#define GPIO_PMC3_PMC37_SHIFT (7u)
+#define GPIO_PMC3_PMC38_SHIFT (8u)
+#define GPIO_PMC3_PMC39_SHIFT (9u)
+#define GPIO_PMC3_PMC310_SHIFT (10u)
+#define GPIO_PMC3_PMC311_SHIFT (11u)
+#define GPIO_PMC3_PMC312_SHIFT (12u)
+#define GPIO_PMC3_PMC313_SHIFT (13u)
+#define GPIO_PMC3_PMC314_SHIFT (14u)
+#define GPIO_PMC3_PMC315_SHIFT (15u)
+
+#define GPIO_PFC3_PFC30_SHIFT (0u)
+#define GPIO_PFC3_PFC31_SHIFT (1u)
+#define GPIO_PFC3_PFC32_SHIFT (2u)
+#define GPIO_PFC3_PFC33_SHIFT (3u)
+#define GPIO_PFC3_PFC34_SHIFT (4u)
+#define GPIO_PFC3_PFC35_SHIFT (5u)
+#define GPIO_PFC3_PFC36_SHIFT (6u)
+#define GPIO_PFC3_PFC37_SHIFT (7u)
+#define GPIO_PFC3_PFC38_SHIFT (8u)
+#define GPIO_PFC3_PFC39_SHIFT (9u)
+#define GPIO_PFC3_PFC310_SHIFT (10u)
+#define GPIO_PFC3_PFC311_SHIFT (11u)
+#define GPIO_PFC3_PFC312_SHIFT (12u)
+#define GPIO_PFC3_PFC313_SHIFT (13u)
+#define GPIO_PFC3_PFC314_SHIFT (14u)
+#define GPIO_PFC3_PFC315_SHIFT (15u)
+
+#define GPIO_PFCE3_PFCE30_SHIFT (0u)
+#define GPIO_PFCE3_PFCE31_SHIFT (1u)
+#define GPIO_PFCE3_PFCE32_SHIFT (2u)
+#define GPIO_PFCE3_PFCE33_SHIFT (3u)
+#define GPIO_PFCE3_PFCE34_SHIFT (4u)
+#define GPIO_PFCE3_PFCE35_SHIFT (5u)
+#define GPIO_PFCE3_PFCE36_SHIFT (6u)
+#define GPIO_PFCE3_PFCE37_SHIFT (7u)
+#define GPIO_PFCE3_PFCE38_SHIFT (8u)
+#define GPIO_PFCE3_PFCE39_SHIFT (9u)
+#define GPIO_PFCE3_PFCE310_SHIFT (10u)
+#define GPIO_PFCE3_PFCE311_SHIFT (11u)
+#define GPIO_PFCE3_PFCE312_SHIFT (12u)
+#define GPIO_PFCE3_PFCE313_SHIFT (13u)
+#define GPIO_PFCE3_PFCE314_SHIFT (14u)
+#define GPIO_PFCE3_PFCE315_SHIFT (15u)
+
+#define GPIO_PNOT3_PNOT30_SHIFT (0u)
+#define GPIO_PNOT3_PNOT31_SHIFT (1u)
+#define GPIO_PNOT3_PNOT32_SHIFT (2u)
+#define GPIO_PNOT3_PNOT33_SHIFT (3u)
+#define GPIO_PNOT3_PNOT34_SHIFT (4u)
+#define GPIO_PNOT3_PNOT35_SHIFT (5u)
+#define GPIO_PNOT3_PNOT36_SHIFT (6u)
+#define GPIO_PNOT3_PNOT37_SHIFT (7u)
+#define GPIO_PNOT3_PNOT38_SHIFT (8u)
+#define GPIO_PNOT3_PNOT39_SHIFT (9u)
+#define GPIO_PNOT3_PNOT310_SHIFT (10u)
+#define GPIO_PNOT3_PNOT311_SHIFT (11u)
+#define GPIO_PNOT3_PNOT312_SHIFT (12u)
+#define GPIO_PNOT3_PNOT313_SHIFT (13u)
+#define GPIO_PNOT3_PNOT314_SHIFT (14u)
+#define GPIO_PNOT3_PNOT315_SHIFT (15u)
+
+#define GPIO_PMSR3_PMSR30_SHIFT (0u)
+#define GPIO_PMSR3_PMSR31_SHIFT (1u)
+#define GPIO_PMSR3_PMSR32_SHIFT (2u)
+#define GPIO_PMSR3_PMSR33_SHIFT (3u)
+#define GPIO_PMSR3_PMSR34_SHIFT (4u)
+#define GPIO_PMSR3_PMSR35_SHIFT (5u)
+#define GPIO_PMSR3_PMSR36_SHIFT (6u)
+#define GPIO_PMSR3_PMSR37_SHIFT (7u)
+#define GPIO_PMSR3_PMSR38_SHIFT (8u)
+#define GPIO_PMSR3_PMSR39_SHIFT (9u)
+#define GPIO_PMSR3_PMSR310_SHIFT (10u)
+#define GPIO_PMSR3_PMSR311_SHIFT (11u)
+#define GPIO_PMSR3_PMSR312_SHIFT (12u)
+#define GPIO_PMSR3_PMSR313_SHIFT (13u)
+#define GPIO_PMSR3_PMSR314_SHIFT (14u)
+#define GPIO_PMSR3_PMSR315_SHIFT (15u)
+#define GPIO_PMSR3_PMSR316_SHIFT (16u)
+#define GPIO_PMSR3_PMSR317_SHIFT (17u)
+#define GPIO_PMSR3_PMSR318_SHIFT (18u)
+#define GPIO_PMSR3_PMSR319_SHIFT (19u)
+#define GPIO_PMSR3_PMSR320_SHIFT (20u)
+#define GPIO_PMSR3_PMSR321_SHIFT (21u)
+#define GPIO_PMSR3_PMSR322_SHIFT (22u)
+#define GPIO_PMSR3_PMSR323_SHIFT (23u)
+#define GPIO_PMSR3_PMSR324_SHIFT (24u)
+#define GPIO_PMSR3_PMSR325_SHIFT (25u)
+#define GPIO_PMSR3_PMSR326_SHIFT (26u)
+#define GPIO_PMSR3_PMSR327_SHIFT (27u)
+#define GPIO_PMSR3_PMSR328_SHIFT (28u)
+#define GPIO_PMSR3_PMSR329_SHIFT (29u)
+#define GPIO_PMSR3_PMSR330_SHIFT (30u)
+#define GPIO_PMSR3_PMSR331_SHIFT (31u)
+
+#define GPIO_PMCSR3_PMCSR30_SHIFT (0u)
+#define GPIO_PMCSR3_PMCSR31_SHIFT (1u)
+#define GPIO_PMCSR3_PMCSR32_SHIFT (2u)
+#define GPIO_PMCSR3_PMCSR33_SHIFT (3u)
+#define GPIO_PMCSR3_PMCSR34_SHIFT (4u)
+#define GPIO_PMCSR3_PMCSR35_SHIFT (5u)
+#define GPIO_PMCSR3_PMCSR36_SHIFT (6u)
+#define GPIO_PMCSR3_PMCSR37_SHIFT (7u)
+#define GPIO_PMCSR3_PMCSR38_SHIFT (8u)
+#define GPIO_PMCSR3_PMCSR39_SHIFT (9u)
+#define GPIO_PMCSR3_PMCSR310_SHIFT (10u)
+#define GPIO_PMCSR3_PMCSR311_SHIFT (11u)
+#define GPIO_PMCSR3_PMCSR312_SHIFT (12u)
+#define GPIO_PMCSR3_PMCSR313_SHIFT (13u)
+#define GPIO_PMCSR3_PMCSR314_SHIFT (14u)
+#define GPIO_PMCSR3_PMCSR315_SHIFT (15u)
+#define GPIO_PMCSR3_PMCSR316_SHIFT (16u)
+#define GPIO_PMCSR3_PMCSR317_SHIFT (17u)
+#define GPIO_PMCSR3_PMCSR318_SHIFT (18u)
+#define GPIO_PMCSR3_PMCSR319_SHIFT (19u)
+#define GPIO_PMCSR3_PMCSR320_SHIFT (20u)
+#define GPIO_PMCSR3_PMCSR321_SHIFT (21u)
+#define GPIO_PMCSR3_PMCSR322_SHIFT (22u)
+#define GPIO_PMCSR3_PMCSR323_SHIFT (23u)
+#define GPIO_PMCSR3_PMCSR324_SHIFT (24u)
+#define GPIO_PMCSR3_PMCSR325_SHIFT (25u)
+#define GPIO_PMCSR3_PMCSR326_SHIFT (26u)
+#define GPIO_PMCSR3_PMCSR327_SHIFT (27u)
+#define GPIO_PMCSR3_PMCSR328_SHIFT (28u)
+#define GPIO_PMCSR3_PMCSR329_SHIFT (29u)
+#define GPIO_PMCSR3_PMCSR330_SHIFT (30u)
+#define GPIO_PMCSR3_PMCSR331_SHIFT (31u)
+
+#define GPIO_PFCAE3_PFCAE30_SHIFT (0u)
+#define GPIO_PFCAE3_PFCAE31_SHIFT (1u)
+#define GPIO_PFCAE3_PFCAE32_SHIFT (2u)
+#define GPIO_PFCAE3_PFCAE33_SHIFT (3u)
+#define GPIO_PFCAE3_PFCAE34_SHIFT (4u)
+#define GPIO_PFCAE3_PFCAE35_SHIFT (5u)
+#define GPIO_PFCAE3_PFCAE36_SHIFT (6u)
+#define GPIO_PFCAE3_PFCAE37_SHIFT (7u)
+#define GPIO_PFCAE3_PFCAE38_SHIFT (8u)
+#define GPIO_PFCAE3_PFCAE39_SHIFT (9u)
+#define GPIO_PFCAE3_PFCAE310_SHIFT (10u)
+#define GPIO_PFCAE3_PFCAE311_SHIFT (11u)
+#define GPIO_PFCAE3_PFCAE312_SHIFT (12u)
+#define GPIO_PFCAE3_PFCAE313_SHIFT (13u)
+#define GPIO_PFCAE3_PFCAE314_SHIFT (14u)
+#define GPIO_PFCAE3_PFCAE315_SHIFT (15u)
+
+#define GPIO_PIBC3_PIBC30_SHIFT (0u)
+#define GPIO_PIBC3_PIBC31_SHIFT (1u)
+#define GPIO_PIBC3_PIBC32_SHIFT (2u)
+#define GPIO_PIBC3_PIBC33_SHIFT (3u)
+#define GPIO_PIBC3_PIBC34_SHIFT (4u)
+#define GPIO_PIBC3_PIBC35_SHIFT (5u)
+#define GPIO_PIBC3_PIBC36_SHIFT (6u)
+#define GPIO_PIBC3_PIBC37_SHIFT (7u)
+#define GPIO_PIBC3_PIBC38_SHIFT (8u)
+#define GPIO_PIBC3_PIBC39_SHIFT (9u)
+#define GPIO_PIBC3_PIBC310_SHIFT (10u)
+#define GPIO_PIBC3_PIBC311_SHIFT (11u)
+#define GPIO_PIBC3_PIBC312_SHIFT (12u)
+#define GPIO_PIBC3_PIBC313_SHIFT (13u)
+#define GPIO_PIBC3_PIBC314_SHIFT (14u)
+#define GPIO_PIBC3_PIBC315_SHIFT (15u)
+
+#define GPIO_PBDC3_PBDC30_SHIFT (0u)
+#define GPIO_PBDC3_PBDC31_SHIFT (1u)
+#define GPIO_PBDC3_PBDC32_SHIFT (2u)
+#define GPIO_PBDC3_PBDC33_SHIFT (3u)
+#define GPIO_PBDC3_PBDC34_SHIFT (4u)
+#define GPIO_PBDC3_PBDC35_SHIFT (5u)
+#define GPIO_PBDC3_PBDC36_SHIFT (6u)
+#define GPIO_PBDC3_PBDC37_SHIFT (7u)
+#define GPIO_PBDC3_PBDC38_SHIFT (8u)
+#define GPIO_PBDC3_PBDC39_SHIFT (9u)
+#define GPIO_PBDC3_PBDC310_SHIFT (10u)
+#define GPIO_PBDC3_PBDC311_SHIFT (11u)
+#define GPIO_PBDC3_PBDC312_SHIFT (12u)
+#define GPIO_PBDC3_PBDC313_SHIFT (13u)
+#define GPIO_PBDC3_PBDC314_SHIFT (14u)
+#define GPIO_PBDC3_PBDC315_SHIFT (15u)
+
+#define GPIO_PIPC3_PIPC30_SHIFT (0u)
+#define GPIO_PIPC3_PIPC31_SHIFT (1u)
+#define GPIO_PIPC3_PIPC32_SHIFT (2u)
+#define GPIO_PIPC3_PIPC33_SHIFT (3u)
+#define GPIO_PIPC3_PIPC34_SHIFT (4u)
+#define GPIO_PIPC3_PIPC35_SHIFT (5u)
+#define GPIO_PIPC3_PIPC36_SHIFT (6u)
+#define GPIO_PIPC3_PIPC37_SHIFT (7u)
+#define GPIO_PIPC3_PIPC38_SHIFT (8u)
+#define GPIO_PIPC3_PIPC39_SHIFT (9u)
+#define GPIO_PIPC3_PIPC310_SHIFT (10u)
+#define GPIO_PIPC3_PIPC311_SHIFT (11u)
+#define GPIO_PIPC3_PIPC312_SHIFT (12u)
+#define GPIO_PIPC3_PIPC313_SHIFT (13u)
+#define GPIO_PIPC3_PIPC314_SHIFT (14u)
+#define GPIO_PIPC3_PIPC315_SHIFT (15u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40_SHIFT (0u)
+#define GPIO_P4_P41_SHIFT (1u)
+#define GPIO_P4_P42_SHIFT (2u)
+#define GPIO_P4_P43_SHIFT (3u)
+#define GPIO_P4_P44_SHIFT (4u)
+#define GPIO_P4_P45_SHIFT (5u)
+#define GPIO_P4_P46_SHIFT (6u)
+#define GPIO_P4_P47_SHIFT (7u)
+#define GPIO_P4_P48_SHIFT (8u)
+#define GPIO_P4_P49_SHIFT (9u)
+#define GPIO_P4_P410_SHIFT (10u)
+#define GPIO_P4_P411_SHIFT (11u)
+#define GPIO_P4_P412_SHIFT (12u)
+#define GPIO_P4_P413_SHIFT (13u)
+#define GPIO_P4_P414_SHIFT (14u)
+#define GPIO_P4_P415_SHIFT (15u)
+
+#define GPIO_PSR4_PSR40_SHIFT (0u)
+#define GPIO_PSR4_PSR41_SHIFT (1u)
+#define GPIO_PSR4_PSR42_SHIFT (2u)
+#define GPIO_PSR4_PSR43_SHIFT (3u)
+#define GPIO_PSR4_PSR44_SHIFT (4u)
+#define GPIO_PSR4_PSR45_SHIFT (5u)
+#define GPIO_PSR4_PSR46_SHIFT (6u)
+#define GPIO_PSR4_PSR47_SHIFT (7u)
+#define GPIO_PSR4_PSR48_SHIFT (8u)
+#define GPIO_PSR4_PSR49_SHIFT (9u)
+#define GPIO_PSR4_PSR410_SHIFT (10u)
+#define GPIO_PSR4_PSR411_SHIFT (11u)
+#define GPIO_PSR4_PSR412_SHIFT (12u)
+#define GPIO_PSR4_PSR413_SHIFT (13u)
+#define GPIO_PSR4_PSR414_SHIFT (14u)
+#define GPIO_PSR4_PSR415_SHIFT (15u)
+#define GPIO_PSR4_PSR416_SHIFT (16u)
+#define GPIO_PSR4_PSR417_SHIFT (17u)
+#define GPIO_PSR4_PSR418_SHIFT (18u)
+#define GPIO_PSR4_PSR419_SHIFT (19u)
+#define GPIO_PSR4_PSR420_SHIFT (20u)
+#define GPIO_PSR4_PSR421_SHIFT (21u)
+#define GPIO_PSR4_PSR422_SHIFT (22u)
+#define GPIO_PSR4_PSR423_SHIFT (23u)
+#define GPIO_PSR4_PSR424_SHIFT (24u)
+#define GPIO_PSR4_PSR425_SHIFT (25u)
+#define GPIO_PSR4_PSR426_SHIFT (26u)
+#define GPIO_PSR4_PSR427_SHIFT (27u)
+#define GPIO_PSR4_PSR428_SHIFT (28u)
+#define GPIO_PSR4_PSR429_SHIFT (29u)
+#define GPIO_PSR4_PSR430_SHIFT (30u)
+#define GPIO_PSR4_PSR431_SHIFT (31u)
+
+#define GPIO_PPR4_PPR40_SHIFT (0u)
+#define GPIO_PPR4_PPR41_SHIFT (1u)
+#define GPIO_PPR4_PPR42_SHIFT (2u)
+#define GPIO_PPR4_PPR43_SHIFT (3u)
+#define GPIO_PPR4_PPR44_SHIFT (4u)
+#define GPIO_PPR4_PPR45_SHIFT (5u)
+#define GPIO_PPR4_PPR46_SHIFT (6u)
+#define GPIO_PPR4_PPR47_SHIFT (7u)
+#define GPIO_PPR4_PPR48_SHIFT (8u)
+#define GPIO_PPR4_PPR49_SHIFT (9u)
+#define GPIO_PPR4_PPR410_SHIFT (10u)
+#define GPIO_PPR4_PPR411_SHIFT (11u)
+#define GPIO_PPR4_PPR412_SHIFT (12u)
+#define GPIO_PPR4_PPR413_SHIFT (13u)
+#define GPIO_PPR4_PPR414_SHIFT (14u)
+#define GPIO_PPR4_PPR415_SHIFT (15u)
+
+#define GPIO_PM4_PM40_SHIFT (0u)
+#define GPIO_PM4_PM41_SHIFT (1u)
+#define GPIO_PM4_PM42_SHIFT (2u)
+#define GPIO_PM4_PM43_SHIFT (3u)
+#define GPIO_PM4_PM44_SHIFT (4u)
+#define GPIO_PM4_PM45_SHIFT (5u)
+#define GPIO_PM4_PM46_SHIFT (6u)
+#define GPIO_PM4_PM47_SHIFT (7u)
+#define GPIO_PM4_PM48_SHIFT (8u)
+#define GPIO_PM4_PM49_SHIFT (9u)
+#define GPIO_PM4_PM410_SHIFT (10u)
+#define GPIO_PM4_PM411_SHIFT (11u)
+#define GPIO_PM4_PM412_SHIFT (12u)
+#define GPIO_PM4_PM413_SHIFT (13u)
+#define GPIO_PM4_PM414_SHIFT (14u)
+#define GPIO_PM4_PM415_SHIFT (15u)
+
+#define GPIO_PMC4_PMC40_SHIFT (0u)
+#define GPIO_PMC4_PMC41_SHIFT (1u)
+#define GPIO_PMC4_PMC42_SHIFT (2u)
+#define GPIO_PMC4_PMC43_SHIFT (3u)
+#define GPIO_PMC4_PMC44_SHIFT (4u)
+#define GPIO_PMC4_PMC45_SHIFT (5u)
+#define GPIO_PMC4_PMC46_SHIFT (6u)
+#define GPIO_PMC4_PMC47_SHIFT (7u)
+#define GPIO_PMC4_PMC48_SHIFT (8u)
+#define GPIO_PMC4_PMC49_SHIFT (9u)
+#define GPIO_PMC4_PMC410_SHIFT (10u)
+#define GPIO_PMC4_PMC411_SHIFT (11u)
+#define GPIO_PMC4_PMC412_SHIFT (12u)
+#define GPIO_PMC4_PMC413_SHIFT (13u)
+#define GPIO_PMC4_PMC414_SHIFT (14u)
+#define GPIO_PMC4_PMC415_SHIFT (15u)
+
+#define GPIO_PFC4_PFC40_SHIFT (0u)
+#define GPIO_PFC4_PFC41_SHIFT (1u)
+#define GPIO_PFC4_PFC42_SHIFT (2u)
+#define GPIO_PFC4_PFC43_SHIFT (3u)
+#define GPIO_PFC4_PFC44_SHIFT (4u)
+#define GPIO_PFC4_PFC45_SHIFT (5u)
+#define GPIO_PFC4_PFC46_SHIFT (6u)
+#define GPIO_PFC4_PFC47_SHIFT (7u)
+#define GPIO_PFC4_PFC48_SHIFT (8u)
+#define GPIO_PFC4_PFC49_SHIFT (9u)
+#define GPIO_PFC4_PFC410_SHIFT (10u)
+#define GPIO_PFC4_PFC411_SHIFT (11u)
+#define GPIO_PFC4_PFC412_SHIFT (12u)
+#define GPIO_PFC4_PFC413_SHIFT (13u)
+#define GPIO_PFC4_PFC414_SHIFT (14u)
+#define GPIO_PFC4_PFC415_SHIFT (15u)
+
+#define GPIO_PFCE4_PFCE40_SHIFT (0u)
+#define GPIO_PFCE4_PFCE41_SHIFT (1u)
+#define GPIO_PFCE4_PFCE42_SHIFT (2u)
+#define GPIO_PFCE4_PFCE43_SHIFT (3u)
+#define GPIO_PFCE4_PFCE44_SHIFT (4u)
+#define GPIO_PFCE4_PFCE45_SHIFT (5u)
+#define GPIO_PFCE4_PFCE46_SHIFT (6u)
+#define GPIO_PFCE4_PFCE47_SHIFT (7u)
+#define GPIO_PFCE4_PFCE48_SHIFT (8u)
+#define GPIO_PFCE4_PFCE49_SHIFT (9u)
+#define GPIO_PFCE4_PFCE410_SHIFT (10u)
+#define GPIO_PFCE4_PFCE411_SHIFT (11u)
+#define GPIO_PFCE4_PFCE412_SHIFT (12u)
+#define GPIO_PFCE4_PFCE413_SHIFT (13u)
+#define GPIO_PFCE4_PFCE414_SHIFT (14u)
+#define GPIO_PFCE4_PFCE415_SHIFT (15u)
+
+#define GPIO_PNOT4_PNOT40_SHIFT (0u)
+#define GPIO_PNOT4_PNOT41_SHIFT (1u)
+#define GPIO_PNOT4_PNOT42_SHIFT (2u)
+#define GPIO_PNOT4_PNOT43_SHIFT (3u)
+#define GPIO_PNOT4_PNOT44_SHIFT (4u)
+#define GPIO_PNOT4_PNOT45_SHIFT (5u)
+#define GPIO_PNOT4_PNOT46_SHIFT (6u)
+#define GPIO_PNOT4_PNOT47_SHIFT (7u)
+#define GPIO_PNOT4_PNOT48_SHIFT (8u)
+#define GPIO_PNOT4_PNOT49_SHIFT (9u)
+#define GPIO_PNOT4_PNOT410_SHIFT (10u)
+#define GPIO_PNOT4_PNOT411_SHIFT (11u)
+#define GPIO_PNOT4_PNOT412_SHIFT (12u)
+#define GPIO_PNOT4_PNOT413_SHIFT (13u)
+#define GPIO_PNOT4_PNOT414_SHIFT (14u)
+#define GPIO_PNOT4_PNOT415_SHIFT (15u)
+
+#define GPIO_PMSR4_PMSR40_SHIFT (0u)
+#define GPIO_PMSR4_PMSR41_SHIFT (1u)
+#define GPIO_PMSR4_PMSR42_SHIFT (2u)
+#define GPIO_PMSR4_PMSR43_SHIFT (3u)
+#define GPIO_PMSR4_PMSR44_SHIFT (4u)
+#define GPIO_PMSR4_PMSR45_SHIFT (5u)
+#define GPIO_PMSR4_PMSR46_SHIFT (6u)
+#define GPIO_PMSR4_PMSR47_SHIFT (7u)
+#define GPIO_PMSR4_PMSR48_SHIFT (8u)
+#define GPIO_PMSR4_PMSR49_SHIFT (9u)
+#define GPIO_PMSR4_PMSR410_SHIFT (10u)
+#define GPIO_PMSR4_PMSR411_SHIFT (11u)
+#define GPIO_PMSR4_PMSR412_SHIFT (12u)
+#define GPIO_PMSR4_PMSR413_SHIFT (13u)
+#define GPIO_PMSR4_PMSR414_SHIFT (14u)
+#define GPIO_PMSR4_PMSR415_SHIFT (15u)
+#define GPIO_PMSR4_PMSR416_SHIFT (16u)
+#define GPIO_PMSR4_PMSR417_SHIFT (17u)
+#define GPIO_PMSR4_PMSR418_SHIFT (18u)
+#define GPIO_PMSR4_PMSR419_SHIFT (19u)
+#define GPIO_PMSR4_PMSR420_SHIFT (20u)
+#define GPIO_PMSR4_PMSR421_SHIFT (21u)
+#define GPIO_PMSR4_PMSR422_SHIFT (22u)
+#define GPIO_PMSR4_PMSR423_SHIFT (23u)
+#define GPIO_PMSR4_PMSR424_SHIFT (24u)
+#define GPIO_PMSR4_PMSR425_SHIFT (25u)
+#define GPIO_PMSR4_PMSR426_SHIFT (26u)
+#define GPIO_PMSR4_PMSR427_SHIFT (27u)
+#define GPIO_PMSR4_PMSR428_SHIFT (28u)
+#define GPIO_PMSR4_PMSR429_SHIFT (29u)
+#define GPIO_PMSR4_PMSR430_SHIFT (30u)
+#define GPIO_PMSR4_PMSR431_SHIFT (31u)
+
+#define GPIO_PMCSR4_PMCSR40_SHIFT (0u)
+#define GPIO_PMCSR4_PMCSR41_SHIFT (1u)
+#define GPIO_PMCSR4_PMCSR42_SHIFT (2u)
+#define GPIO_PMCSR4_PMCSR43_SHIFT (3u)
+#define GPIO_PMCSR4_PMCSR44_SHIFT (4u)
+#define GPIO_PMCSR4_PMCSR45_SHIFT (5u)
+#define GPIO_PMCSR4_PMCSR46_SHIFT (6u)
+#define GPIO_PMCSR4_PMCSR47_SHIFT (7u)
+#define GPIO_PMCSR4_PMCSR48_SHIFT (8u)
+#define GPIO_PMCSR4_PMCSR49_SHIFT (9u)
+#define GPIO_PMCSR4_PMCSR410_SHIFT (10u)
+#define GPIO_PMCSR4_PMCSR411_SHIFT (11u)
+#define GPIO_PMCSR4_PMCSR412_SHIFT (12u)
+#define GPIO_PMCSR4_PMCSR413_SHIFT (13u)
+#define GPIO_PMCSR4_PMCSR414_SHIFT (14u)
+#define GPIO_PMCSR4_PMCSR415_SHIFT (15u)
+#define GPIO_PMCSR4_PMCSR416_SHIFT (16u)
+#define GPIO_PMCSR4_PMCSR417_SHIFT (17u)
+#define GPIO_PMCSR4_PMCSR418_SHIFT (18u)
+#define GPIO_PMCSR4_PMCSR419_SHIFT (19u)
+#define GPIO_PMCSR4_PMCSR420_SHIFT (20u)
+#define GPIO_PMCSR4_PMCSR421_SHIFT (21u)
+#define GPIO_PMCSR4_PMCSR422_SHIFT (22u)
+#define GPIO_PMCSR4_PMCSR423_SHIFT (23u)
+#define GPIO_PMCSR4_PMCSR424_SHIFT (24u)
+#define GPIO_PMCSR4_PMCSR425_SHIFT (25u)
+#define GPIO_PMCSR4_PMCSR426_SHIFT (26u)
+#define GPIO_PMCSR4_PMCSR427_SHIFT (27u)
+#define GPIO_PMCSR4_PMCSR428_SHIFT (28u)
+#define GPIO_PMCSR4_PMCSR429_SHIFT (29u)
+#define GPIO_PMCSR4_PMCSR430_SHIFT (30u)
+#define GPIO_PMCSR4_PMCSR431_SHIFT (31u)
+
+#define GPIO_PFCAE4_PFCAE40_SHIFT (0u)
+#define GPIO_PFCAE4_PFCAE41_SHIFT (1u)
+#define GPIO_PFCAE4_PFCAE42_SHIFT (2u)
+#define GPIO_PFCAE4_PFCAE43_SHIFT (3u)
+#define GPIO_PFCAE4_PFCAE44_SHIFT (4u)
+#define GPIO_PFCAE4_PFCAE45_SHIFT (5u)
+#define GPIO_PFCAE4_PFCAE46_SHIFT (6u)
+#define GPIO_PFCAE4_PFCAE47_SHIFT (7u)
+#define GPIO_PFCAE4_PFCAE48_SHIFT (8u)
+#define GPIO_PFCAE4_PFCAE49_SHIFT (9u)
+#define GPIO_PFCAE4_PFCAE410_SHIFT (10u)
+#define GPIO_PFCAE4_PFCAE411_SHIFT (11u)
+#define GPIO_PFCAE4_PFCAE412_SHIFT (12u)
+#define GPIO_PFCAE4_PFCAE413_SHIFT (13u)
+#define GPIO_PFCAE4_PFCAE414_SHIFT (14u)
+#define GPIO_PFCAE4_PFCAE415_SHIFT (15u)
+
+#define GPIO_PIBC4_PIBC40_SHIFT (0u)
+#define GPIO_PIBC4_PIBC41_SHIFT (1u)
+#define GPIO_PIBC4_PIBC42_SHIFT (2u)
+#define GPIO_PIBC4_PIBC43_SHIFT (3u)
+#define GPIO_PIBC4_PIBC44_SHIFT (4u)
+#define GPIO_PIBC4_PIBC45_SHIFT (5u)
+#define GPIO_PIBC4_PIBC46_SHIFT (6u)
+#define GPIO_PIBC4_PIBC47_SHIFT (7u)
+#define GPIO_PIBC4_PIBC48_SHIFT (8u)
+#define GPIO_PIBC4_PIBC49_SHIFT (9u)
+#define GPIO_PIBC4_PIBC410_SHIFT (10u)
+#define GPIO_PIBC4_PIBC411_SHIFT (11u)
+#define GPIO_PIBC4_PIBC412_SHIFT (12u)
+#define GPIO_PIBC4_PIBC413_SHIFT (13u)
+#define GPIO_PIBC4_PIBC414_SHIFT (14u)
+#define GPIO_PIBC4_PIBC415_SHIFT (15u)
+
+#define GPIO_PBDC4_PBDC40_SHIFT (0u)
+#define GPIO_PBDC4_PBDC41_SHIFT (1u)
+#define GPIO_PBDC4_PBDC42_SHIFT (2u)
+#define GPIO_PBDC4_PBDC43_SHIFT (3u)
+#define GPIO_PBDC4_PBDC44_SHIFT (4u)
+#define GPIO_PBDC4_PBDC45_SHIFT (5u)
+#define GPIO_PBDC4_PBDC46_SHIFT (6u)
+#define GPIO_PBDC4_PBDC47_SHIFT (7u)
+#define GPIO_PBDC4_PBDC48_SHIFT (8u)
+#define GPIO_PBDC4_PBDC49_SHIFT (9u)
+#define GPIO_PBDC4_PBDC410_SHIFT (10u)
+#define GPIO_PBDC4_PBDC411_SHIFT (11u)
+#define GPIO_PBDC4_PBDC412_SHIFT (12u)
+#define GPIO_PBDC4_PBDC413_SHIFT (13u)
+#define GPIO_PBDC4_PBDC414_SHIFT (14u)
+#define GPIO_PBDC4_PBDC415_SHIFT (15u)
+
+#define GPIO_PIPC4_PIPC40_SHIFT (0u)
+#define GPIO_PIPC4_PIPC41_SHIFT (1u)
+#define GPIO_PIPC4_PIPC42_SHIFT (2u)
+#define GPIO_PIPC4_PIPC43_SHIFT (3u)
+#define GPIO_PIPC4_PIPC44_SHIFT (4u)
+#define GPIO_PIPC4_PIPC45_SHIFT (5u)
+#define GPIO_PIPC4_PIPC46_SHIFT (6u)
+#define GPIO_PIPC4_PIPC47_SHIFT (7u)
+#define GPIO_PIPC4_PIPC48_SHIFT (8u)
+#define GPIO_PIPC4_PIPC49_SHIFT (9u)
+#define GPIO_PIPC4_PIPC410_SHIFT (10u)
+#define GPIO_PIPC4_PIPC411_SHIFT (11u)
+#define GPIO_PIPC4_PIPC412_SHIFT (12u)
+#define GPIO_PIPC4_PIPC413_SHIFT (13u)
+#define GPIO_PIPC4_PIPC414_SHIFT (14u)
+#define GPIO_PIPC4_PIPC415_SHIFT (15u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50_SHIFT (0u)
+#define GPIO_P5_P51_SHIFT (1u)
+#define GPIO_P5_P52_SHIFT (2u)
+#define GPIO_P5_P53_SHIFT (3u)
+#define GPIO_P5_P54_SHIFT (4u)
+#define GPIO_P5_P55_SHIFT (5u)
+#define GPIO_P5_P56_SHIFT (6u)
+#define GPIO_P5_P57_SHIFT (7u)
+#define GPIO_P5_P58_SHIFT (8u)
+#define GPIO_P5_P59_SHIFT (9u)
+#define GPIO_P5_P510_SHIFT (10u)
+
+#define GPIO_PSR5_PSR50_SHIFT (0u)
+#define GPIO_PSR5_PSR51_SHIFT (1u)
+#define GPIO_PSR5_PSR52_SHIFT (2u)
+#define GPIO_PSR5_PSR53_SHIFT (3u)
+#define GPIO_PSR5_PSR54_SHIFT (4u)
+#define GPIO_PSR5_PSR55_SHIFT (5u)
+#define GPIO_PSR5_PSR56_SHIFT (6u)
+#define GPIO_PSR5_PSR57_SHIFT (7u)
+#define GPIO_PSR5_PSR58_SHIFT (8u)
+#define GPIO_PSR5_PSR59_SHIFT (9u)
+#define GPIO_PSR5_PSR510_SHIFT (10u)
+#define GPIO_PSR5_PSR516_SHIFT (16u)
+#define GPIO_PSR5_PSR517_SHIFT (17u)
+#define GPIO_PSR5_PSR518_SHIFT (18u)
+#define GPIO_PSR5_PSR519_SHIFT (19u)
+#define GPIO_PSR5_PSR520_SHIFT (20u)
+#define GPIO_PSR5_PSR521_SHIFT (21u)
+#define GPIO_PSR5_PSR522_SHIFT (22u)
+#define GPIO_PSR5_PSR523_SHIFT (23u)
+#define GPIO_PSR5_PSR524_SHIFT (24u)
+#define GPIO_PSR5_PSR525_SHIFT (25u)
+#define GPIO_PSR5_PSR526_SHIFT (26u)
+
+#define GPIO_PPR5_PPR50_SHIFT (0u)
+#define GPIO_PPR5_PPR51_SHIFT (1u)
+#define GPIO_PPR5_PPR52_SHIFT (2u)
+#define GPIO_PPR5_PPR53_SHIFT (3u)
+#define GPIO_PPR5_PPR54_SHIFT (4u)
+#define GPIO_PPR5_PPR55_SHIFT (5u)
+#define GPIO_PPR5_PPR56_SHIFT (6u)
+#define GPIO_PPR5_PPR57_SHIFT (7u)
+#define GPIO_PPR5_PPR58_SHIFT (8u)
+#define GPIO_PPR5_PPR59_SHIFT (9u)
+#define GPIO_PPR5_PPR510_SHIFT (10u)
+
+#define GPIO_PM5_PM50_SHIFT (0u)
+#define GPIO_PM5_PM51_SHIFT (1u)
+#define GPIO_PM5_PM52_SHIFT (2u)
+#define GPIO_PM5_PM53_SHIFT (3u)
+#define GPIO_PM5_PM54_SHIFT (4u)
+#define GPIO_PM5_PM55_SHIFT (5u)
+#define GPIO_PM5_PM56_SHIFT (6u)
+#define GPIO_PM5_PM57_SHIFT (7u)
+#define GPIO_PM5_PM58_SHIFT (8u)
+#define GPIO_PM5_PM59_SHIFT (9u)
+#define GPIO_PM5_PM510_SHIFT (10u)
+
+#define GPIO_PMC5_PMC50_SHIFT (0u)
+#define GPIO_PMC5_PMC51_SHIFT (1u)
+#define GPIO_PMC5_PMC52_SHIFT (2u)
+#define GPIO_PMC5_PMC53_SHIFT (3u)
+#define GPIO_PMC5_PMC54_SHIFT (4u)
+#define GPIO_PMC5_PMC55_SHIFT (5u)
+#define GPIO_PMC5_PMC56_SHIFT (6u)
+#define GPIO_PMC5_PMC57_SHIFT (7u)
+#define GPIO_PMC5_PMC58_SHIFT (8u)
+#define GPIO_PMC5_PMC59_SHIFT (9u)
+#define GPIO_PMC5_PMC510_SHIFT (10u)
+
+#define GPIO_PFC5_PFC50_SHIFT (0u)
+#define GPIO_PFC5_PFC51_SHIFT (1u)
+#define GPIO_PFC5_PFC52_SHIFT (2u)
+#define GPIO_PFC5_PFC53_SHIFT (3u)
+#define GPIO_PFC5_PFC54_SHIFT (4u)
+#define GPIO_PFC5_PFC55_SHIFT (5u)
+#define GPIO_PFC5_PFC56_SHIFT (6u)
+#define GPIO_PFC5_PFC57_SHIFT (7u)
+#define GPIO_PFC5_PFC58_SHIFT (8u)
+#define GPIO_PFC5_PFC59_SHIFT (9u)
+#define GPIO_PFC5_PFC510_SHIFT (10u)
+
+#define GPIO_PFCE5_PFCE50_SHIFT (0u)
+#define GPIO_PFCE5_PFCE51_SHIFT (1u)
+#define GPIO_PFCE5_PFCE52_SHIFT (2u)
+#define GPIO_PFCE5_PFCE53_SHIFT (3u)
+#define GPIO_PFCE5_PFCE54_SHIFT (4u)
+#define GPIO_PFCE5_PFCE55_SHIFT (5u)
+#define GPIO_PFCE5_PFCE56_SHIFT (6u)
+#define GPIO_PFCE5_PFCE57_SHIFT (7u)
+#define GPIO_PFCE5_PFCE58_SHIFT (8u)
+#define GPIO_PFCE5_PFCE59_SHIFT (9u)
+#define GPIO_PFCE5_PFCE510_SHIFT (10u)
+
+#define GPIO_PNOT5_PNOT50_SHIFT (0u)
+#define GPIO_PNOT5_PNOT51_SHIFT (1u)
+#define GPIO_PNOT5_PNOT52_SHIFT (2u)
+#define GPIO_PNOT5_PNOT53_SHIFT (3u)
+#define GPIO_PNOT5_PNOT54_SHIFT (4u)
+#define GPIO_PNOT5_PNOT55_SHIFT (5u)
+#define GPIO_PNOT5_PNOT56_SHIFT (6u)
+#define GPIO_PNOT5_PNOT57_SHIFT (7u)
+#define GPIO_PNOT5_PNOT58_SHIFT (8u)
+#define GPIO_PNOT5_PNOT59_SHIFT (9u)
+#define GPIO_PNOT5_PNOT510_SHIFT (10u)
+
+#define GPIO_PMSR5_PMSR50_SHIFT (0u)
+#define GPIO_PMSR5_PMSR51_SHIFT (1u)
+#define GPIO_PMSR5_PMSR52_SHIFT (2u)
+#define GPIO_PMSR5_PMSR53_SHIFT (3u)
+#define GPIO_PMSR5_PMSR54_SHIFT (4u)
+#define GPIO_PMSR5_PMSR55_SHIFT (5u)
+#define GPIO_PMSR5_PMSR56_SHIFT (6u)
+#define GPIO_PMSR5_PMSR57_SHIFT (7u)
+#define GPIO_PMSR5_PMSR58_SHIFT (8u)
+#define GPIO_PMSR5_PMSR59_SHIFT (9u)
+#define GPIO_PMSR5_PMSR510_SHIFT (10u)
+#define GPIO_PMSR5_PMSR516_SHIFT (16u)
+#define GPIO_PMSR5_PMSR517_SHIFT (17u)
+#define GPIO_PMSR5_PMSR518_SHIFT (18u)
+#define GPIO_PMSR5_PMSR519_SHIFT (19u)
+#define GPIO_PMSR5_PMSR520_SHIFT (20u)
+#define GPIO_PMSR5_PMSR521_SHIFT (21u)
+#define GPIO_PMSR5_PMSR522_SHIFT (22u)
+#define GPIO_PMSR5_PMSR523_SHIFT (23u)
+#define GPIO_PMSR5_PMSR524_SHIFT (24u)
+#define GPIO_PMSR5_PMSR525_SHIFT (25u)
+#define GPIO_PMSR5_PMSR526_SHIFT (26u)
+
+#define GPIO_PMCSR5_PMCSR50_SHIFT (0u)
+#define GPIO_PMCSR5_PMCSR51_SHIFT (1u)
+#define GPIO_PMCSR5_PMCSR52_SHIFT (2u)
+#define GPIO_PMCSR5_PMCSR53_SHIFT (3u)
+#define GPIO_PMCSR5_PMCSR54_SHIFT (4u)
+#define GPIO_PMCSR5_PMCSR55_SHIFT (5u)
+#define GPIO_PMCSR5_PMCSR56_SHIFT (6u)
+#define GPIO_PMCSR5_PMCSR57_SHIFT (7u)
+#define GPIO_PMCSR5_PMCSR58_SHIFT (8u)
+#define GPIO_PMCSR5_PMCSR59_SHIFT (9u)
+#define GPIO_PMCSR5_PMCSR510_SHIFT (10u)
+#define GPIO_PMCSR5_PMCSR516_SHIFT (16u)
+#define GPIO_PMCSR5_PMCSR517_SHIFT (17u)
+#define GPIO_PMCSR5_PMCSR518_SHIFT (18u)
+#define GPIO_PMCSR5_PMCSR519_SHIFT (19u)
+#define GPIO_PMCSR5_PMCSR520_SHIFT (20u)
+#define GPIO_PMCSR5_PMCSR521_SHIFT (21u)
+#define GPIO_PMCSR5_PMCSR522_SHIFT (22u)
+#define GPIO_PMCSR5_PMCSR523_SHIFT (23u)
+#define GPIO_PMCSR5_PMCSR524_SHIFT (24u)
+#define GPIO_PMCSR5_PMCSR525_SHIFT (25u)
+#define GPIO_PMCSR5_PMCSR526_SHIFT (26u)
+
+#define GPIO_PFCAE5_PFCAE50_SHIFT (0u)
+#define GPIO_PFCAE5_PFCAE51_SHIFT (1u)
+#define GPIO_PFCAE5_PFCAE52_SHIFT (2u)
+#define GPIO_PFCAE5_PFCAE53_SHIFT (3u)
+#define GPIO_PFCAE5_PFCAE54_SHIFT (4u)
+#define GPIO_PFCAE5_PFCAE55_SHIFT (5u)
+#define GPIO_PFCAE5_PFCAE56_SHIFT (6u)
+#define GPIO_PFCAE5_PFCAE57_SHIFT (7u)
+#define GPIO_PFCAE5_PFCAE58_SHIFT (8u)
+#define GPIO_PFCAE5_PFCAE59_SHIFT (9u)
+#define GPIO_PFCAE5_PFCAE510_SHIFT (10u)
+
+#define GPIO_PIBC5_PIBC50_SHIFT (0u)
+#define GPIO_PIBC5_PIBC51_SHIFT (1u)
+#define GPIO_PIBC5_PIBC52_SHIFT (2u)
+#define GPIO_PIBC5_PIBC53_SHIFT (3u)
+#define GPIO_PIBC5_PIBC54_SHIFT (4u)
+#define GPIO_PIBC5_PIBC55_SHIFT (5u)
+#define GPIO_PIBC5_PIBC56_SHIFT (6u)
+#define GPIO_PIBC5_PIBC57_SHIFT (7u)
+#define GPIO_PIBC5_PIBC58_SHIFT (8u)
+#define GPIO_PIBC5_PIBC59_SHIFT (9u)
+#define GPIO_PIBC5_PIBC510_SHIFT (10u)
+
+#define GPIO_PBDC5_PBDC50_SHIFT (0u)
+#define GPIO_PBDC5_PBDC51_SHIFT (1u)
+#define GPIO_PBDC5_PBDC52_SHIFT (2u)
+#define GPIO_PBDC5_PBDC53_SHIFT (3u)
+#define GPIO_PBDC5_PBDC54_SHIFT (4u)
+#define GPIO_PBDC5_PBDC55_SHIFT (5u)
+#define GPIO_PBDC5_PBDC56_SHIFT (6u)
+#define GPIO_PBDC5_PBDC57_SHIFT (7u)
+#define GPIO_PBDC5_PBDC58_SHIFT (8u)
+#define GPIO_PBDC5_PBDC59_SHIFT (9u)
+#define GPIO_PBDC5_PBDC510_SHIFT (10u)
+
+#define GPIO_PIPC5_PIPC50_SHIFT (0u)
+#define GPIO_PIPC5_PIPC51_SHIFT (1u)
+#define GPIO_PIPC5_PIPC52_SHIFT (2u)
+#define GPIO_PIPC5_PIPC53_SHIFT (3u)
+#define GPIO_PIPC5_PIPC54_SHIFT (4u)
+#define GPIO_PIPC5_PIPC55_SHIFT (5u)
+#define GPIO_PIPC5_PIPC56_SHIFT (6u)
+#define GPIO_PIPC5_PIPC57_SHIFT (7u)
+#define GPIO_PIPC5_PIPC58_SHIFT (8u)
+#define GPIO_PIPC5_PIPC59_SHIFT (9u)
+#define GPIO_PIPC5_PIPC510_SHIFT (10u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60_SHIFT (0u)
+#define GPIO_P6_P61_SHIFT (1u)
+#define GPIO_P6_P62_SHIFT (2u)
+#define GPIO_P6_P63_SHIFT (3u)
+#define GPIO_P6_P64_SHIFT (4u)
+#define GPIO_P6_P65_SHIFT (5u)
+#define GPIO_P6_P66_SHIFT (6u)
+#define GPIO_P6_P67_SHIFT (7u)
+#define GPIO_P6_P68_SHIFT (8u)
+#define GPIO_P6_P69_SHIFT (9u)
+#define GPIO_P6_P610_SHIFT (10u)
+#define GPIO_P6_P611_SHIFT (11u)
+#define GPIO_P6_P612_SHIFT (12u)
+#define GPIO_P6_P613_SHIFT (13u)
+#define GPIO_P6_P614_SHIFT (14u)
+#define GPIO_P6_P615_SHIFT (15u)
+
+#define GPIO_PSR6_PSR60_SHIFT (0u)
+#define GPIO_PSR6_PSR61_SHIFT (1u)
+#define GPIO_PSR6_PSR62_SHIFT (2u)
+#define GPIO_PSR6_PSR63_SHIFT (3u)
+#define GPIO_PSR6_PSR64_SHIFT (4u)
+#define GPIO_PSR6_PSR65_SHIFT (5u)
+#define GPIO_PSR6_PSR66_SHIFT (6u)
+#define GPIO_PSR6_PSR67_SHIFT (7u)
+#define GPIO_PSR6_PSR68_SHIFT (8u)
+#define GPIO_PSR6_PSR69_SHIFT (9u)
+#define GPIO_PSR6_PSR610_SHIFT (10u)
+#define GPIO_PSR6_PSR611_SHIFT (11u)
+#define GPIO_PSR6_PSR612_SHIFT (12u)
+#define GPIO_PSR6_PSR613_SHIFT (13u)
+#define GPIO_PSR6_PSR614_SHIFT (14u)
+#define GPIO_PSR6_PSR615_SHIFT (15u)
+#define GPIO_PSR6_PSR616_SHIFT (16u)
+#define GPIO_PSR6_PSR617_SHIFT (17u)
+#define GPIO_PSR6_PSR618_SHIFT (18u)
+#define GPIO_PSR6_PSR619_SHIFT (19u)
+#define GPIO_PSR6_PSR620_SHIFT (20u)
+#define GPIO_PSR6_PSR621_SHIFT (21u)
+#define GPIO_PSR6_PSR622_SHIFT (22u)
+#define GPIO_PSR6_PSR623_SHIFT (23u)
+#define GPIO_PSR6_PSR624_SHIFT (24u)
+#define GPIO_PSR6_PSR625_SHIFT (25u)
+#define GPIO_PSR6_PSR626_SHIFT (26u)
+#define GPIO_PSR6_PSR627_SHIFT (27u)
+#define GPIO_PSR6_PSR628_SHIFT (28u)
+#define GPIO_PSR6_PSR629_SHIFT (29u)
+#define GPIO_PSR6_PSR630_SHIFT (30u)
+#define GPIO_PSR6_PSR631_SHIFT (31u)
+
+#define GPIO_PPR6_PPR60_SHIFT (0u)
+#define GPIO_PPR6_PPR61_SHIFT (1u)
+#define GPIO_PPR6_PPR62_SHIFT (2u)
+#define GPIO_PPR6_PPR63_SHIFT (3u)
+#define GPIO_PPR6_PPR64_SHIFT (4u)
+#define GPIO_PPR6_PPR65_SHIFT (5u)
+#define GPIO_PPR6_PPR66_SHIFT (6u)
+#define GPIO_PPR6_PPR67_SHIFT (7u)
+#define GPIO_PPR6_PPR68_SHIFT (8u)
+#define GPIO_PPR6_PPR69_SHIFT (9u)
+#define GPIO_PPR6_PPR610_SHIFT (10u)
+#define GPIO_PPR6_PPR611_SHIFT (11u)
+#define GPIO_PPR6_PPR612_SHIFT (12u)
+#define GPIO_PPR6_PPR613_SHIFT (13u)
+#define GPIO_PPR6_PPR614_SHIFT (14u)
+#define GPIO_PPR6_PPR615_SHIFT (15u)
+
+#define GPIO_PM6_PM60_SHIFT (0u)
+#define GPIO_PM6_PM61_SHIFT (1u)
+#define GPIO_PM6_PM62_SHIFT (2u)
+#define GPIO_PM6_PM63_SHIFT (3u)
+#define GPIO_PM6_PM64_SHIFT (4u)
+#define GPIO_PM6_PM65_SHIFT (5u)
+#define GPIO_PM6_PM66_SHIFT (6u)
+#define GPIO_PM6_PM67_SHIFT (7u)
+#define GPIO_PM6_PM68_SHIFT (8u)
+#define GPIO_PM6_PM69_SHIFT (9u)
+#define GPIO_PM6_PM610_SHIFT (10u)
+#define GPIO_PM6_PM611_SHIFT (11u)
+#define GPIO_PM6_PM612_SHIFT (12u)
+#define GPIO_PM6_PM613_SHIFT (13u)
+#define GPIO_PM6_PM614_SHIFT (14u)
+#define GPIO_PM6_PM615_SHIFT (15u)
+
+#define GPIO_PMC6_PMC60_SHIFT (0u)
+#define GPIO_PMC6_PMC61_SHIFT (1u)
+#define GPIO_PMC6_PMC62_SHIFT (2u)
+#define GPIO_PMC6_PMC63_SHIFT (3u)
+#define GPIO_PMC6_PMC64_SHIFT (4u)
+#define GPIO_PMC6_PMC65_SHIFT (5u)
+#define GPIO_PMC6_PMC66_SHIFT (6u)
+#define GPIO_PMC6_PMC67_SHIFT (7u)
+#define GPIO_PMC6_PMC68_SHIFT (8u)
+#define GPIO_PMC6_PMC69_SHIFT (9u)
+#define GPIO_PMC6_PMC610_SHIFT (10u)
+#define GPIO_PMC6_PMC611_SHIFT (11u)
+#define GPIO_PMC6_PMC612_SHIFT (12u)
+#define GPIO_PMC6_PMC613_SHIFT (13u)
+#define GPIO_PMC6_PMC614_SHIFT (14u)
+#define GPIO_PMC6_PMC615_SHIFT (15u)
+
+#define GPIO_PFC6_PFC60_SHIFT (0u)
+#define GPIO_PFC6_PFC61_SHIFT (1u)
+#define GPIO_PFC6_PFC62_SHIFT (2u)
+#define GPIO_PFC6_PFC63_SHIFT (3u)
+#define GPIO_PFC6_PFC64_SHIFT (4u)
+#define GPIO_PFC6_PFC65_SHIFT (5u)
+#define GPIO_PFC6_PFC66_SHIFT (6u)
+#define GPIO_PFC6_PFC67_SHIFT (7u)
+#define GPIO_PFC6_PFC68_SHIFT (8u)
+#define GPIO_PFC6_PFC69_SHIFT (9u)
+#define GPIO_PFC6_PFC610_SHIFT (10u)
+#define GPIO_PFC6_PFC611_SHIFT (11u)
+#define GPIO_PFC6_PFC612_SHIFT (12u)
+#define GPIO_PFC6_PFC613_SHIFT (13u)
+#define GPIO_PFC6_PFC614_SHIFT (14u)
+#define GPIO_PFC6_PFC615_SHIFT (15u)
+
+#define GPIO_PFCE6_PFCE60_SHIFT (0u)
+#define GPIO_PFCE6_PFCE61_SHIFT (1u)
+#define GPIO_PFCE6_PFCE62_SHIFT (2u)
+#define GPIO_PFCE6_PFCE63_SHIFT (3u)
+#define GPIO_PFCE6_PFCE64_SHIFT (4u)
+#define GPIO_PFCE6_PFCE65_SHIFT (5u)
+#define GPIO_PFCE6_PFCE66_SHIFT (6u)
+#define GPIO_PFCE6_PFCE67_SHIFT (7u)
+#define GPIO_PFCE6_PFCE68_SHIFT (8u)
+#define GPIO_PFCE6_PFCE69_SHIFT (9u)
+#define GPIO_PFCE6_PFCE610_SHIFT (10u)
+#define GPIO_PFCE6_PFCE611_SHIFT (11u)
+#define GPIO_PFCE6_PFCE612_SHIFT (12u)
+#define GPIO_PFCE6_PFCE613_SHIFT (13u)
+#define GPIO_PFCE6_PFCE614_SHIFT (14u)
+#define GPIO_PFCE6_PFCE615_SHIFT (15u)
+
+#define GPIO_PNOT6_PNOT60_SHIFT (0u)
+#define GPIO_PNOT6_PNOT61_SHIFT (1u)
+#define GPIO_PNOT6_PNOT62_SHIFT (2u)
+#define GPIO_PNOT6_PNOT63_SHIFT (3u)
+#define GPIO_PNOT6_PNOT64_SHIFT (4u)
+#define GPIO_PNOT6_PNOT65_SHIFT (5u)
+#define GPIO_PNOT6_PNOT66_SHIFT (6u)
+#define GPIO_PNOT6_PNOT67_SHIFT (7u)
+#define GPIO_PNOT6_PNOT68_SHIFT (8u)
+#define GPIO_PNOT6_PNOT69_SHIFT (9u)
+#define GPIO_PNOT6_PNOT610_SHIFT (10u)
+#define GPIO_PNOT6_PNOT611_SHIFT (11u)
+#define GPIO_PNOT6_PNOT612_SHIFT (12u)
+#define GPIO_PNOT6_PNOT613_SHIFT (13u)
+#define GPIO_PNOT6_PNOT614_SHIFT (14u)
+#define GPIO_PNOT6_PNOT615_SHIFT (15u)
+
+#define GPIO_PMSR6_PMSR60_SHIFT (0u)
+#define GPIO_PMSR6_PMSR61_SHIFT (1u)
+#define GPIO_PMSR6_PMSR62_SHIFT (2u)
+#define GPIO_PMSR6_PMSR63_SHIFT (3u)
+#define GPIO_PMSR6_PMSR64_SHIFT (4u)
+#define GPIO_PMSR6_PMSR65_SHIFT (5u)
+#define GPIO_PMSR6_PMSR66_SHIFT (6u)
+#define GPIO_PMSR6_PMSR67_SHIFT (7u)
+#define GPIO_PMSR6_PMSR68_SHIFT (8u)
+#define GPIO_PMSR6_PMSR69_SHIFT (9u)
+#define GPIO_PMSR6_PMSR610_SHIFT (10u)
+#define GPIO_PMSR6_PMSR611_SHIFT (11u)
+#define GPIO_PMSR6_PMSR612_SHIFT (12u)
+#define GPIO_PMSR6_PMSR613_SHIFT (13u)
+#define GPIO_PMSR6_PMSR614_SHIFT (14u)
+#define GPIO_PMSR6_PMSR615_SHIFT (15u)
+#define GPIO_PMSR6_PMSR616_SHIFT (16u)
+#define GPIO_PMSR6_PMSR617_SHIFT (17u)
+#define GPIO_PMSR6_PMSR618_SHIFT (18u)
+#define GPIO_PMSR6_PMSR619_SHIFT (19u)
+#define GPIO_PMSR6_PMSR620_SHIFT (20u)
+#define GPIO_PMSR6_PMSR621_SHIFT (21u)
+#define GPIO_PMSR6_PMSR622_SHIFT (22u)
+#define GPIO_PMSR6_PMSR623_SHIFT (23u)
+#define GPIO_PMSR6_PMSR624_SHIFT (24u)
+#define GPIO_PMSR6_PMSR625_SHIFT (25u)
+#define GPIO_PMSR6_PMSR626_SHIFT (26u)
+#define GPIO_PMSR6_PMSR627_SHIFT (27u)
+#define GPIO_PMSR6_PMSR628_SHIFT (28u)
+#define GPIO_PMSR6_PMSR629_SHIFT (29u)
+#define GPIO_PMSR6_PMSR630_SHIFT (30u)
+#define GPIO_PMSR6_PMSR631_SHIFT (31u)
+
+#define GPIO_PMCSR6_PMCSR60_SHIFT (0u)
+#define GPIO_PMCSR6_PMCSR61_SHIFT (1u)
+#define GPIO_PMCSR6_PMCSR62_SHIFT (2u)
+#define GPIO_PMCSR6_PMCSR63_SHIFT (3u)
+#define GPIO_PMCSR6_PMCSR64_SHIFT (4u)
+#define GPIO_PMCSR6_PMCSR65_SHIFT (5u)
+#define GPIO_PMCSR6_PMCSR66_SHIFT (6u)
+#define GPIO_PMCSR6_PMCSR67_SHIFT (7u)
+#define GPIO_PMCSR6_PMCSR68_SHIFT (8u)
+#define GPIO_PMCSR6_PMCSR69_SHIFT (9u)
+#define GPIO_PMCSR6_PMCSR610_SHIFT (10u)
+#define GPIO_PMCSR6_PMCSR611_SHIFT (11u)
+#define GPIO_PMCSR6_PMCSR612_SHIFT (12u)
+#define GPIO_PMCSR6_PMCSR613_SHIFT (13u)
+#define GPIO_PMCSR6_PMCSR614_SHIFT (14u)
+#define GPIO_PMCSR6_PMCSR615_SHIFT (15u)
+#define GPIO_PMCSR6_PMCSR616_SHIFT (16u)
+#define GPIO_PMCSR6_PMCSR617_SHIFT (17u)
+#define GPIO_PMCSR6_PMCSR618_SHIFT (18u)
+#define GPIO_PMCSR6_PMCSR619_SHIFT (19u)
+#define GPIO_PMCSR6_PMCSR620_SHIFT (20u)
+#define GPIO_PMCSR6_PMCSR621_SHIFT (21u)
+#define GPIO_PMCSR6_PMCSR622_SHIFT (22u)
+#define GPIO_PMCSR6_PMCSR623_SHIFT (23u)
+#define GPIO_PMCSR6_PMCSR624_SHIFT (24u)
+#define GPIO_PMCSR6_PMCSR625_SHIFT (25u)
+#define GPIO_PMCSR6_PMCSR626_SHIFT (26u)
+#define GPIO_PMCSR6_PMCSR627_SHIFT (27u)
+#define GPIO_PMCSR6_PMCSR628_SHIFT (28u)
+#define GPIO_PMCSR6_PMCSR629_SHIFT (29u)
+#define GPIO_PMCSR6_PMCSR630_SHIFT (30u)
+#define GPIO_PMCSR6_PMCSR631_SHIFT (31u)
+
+#define GPIO_PFCAE6_PFCAE60_SHIFT (0u)
+#define GPIO_PFCAE6_PFCAE61_SHIFT (1u)
+#define GPIO_PFCAE6_PFCAE62_SHIFT (2u)
+#define GPIO_PFCAE6_PFCAE63_SHIFT (3u)
+#define GPIO_PFCAE6_PFCAE64_SHIFT (4u)
+#define GPIO_PFCAE6_PFCAE65_SHIFT (5u)
+#define GPIO_PFCAE6_PFCAE66_SHIFT (6u)
+#define GPIO_PFCAE6_PFCAE67_SHIFT (7u)
+#define GPIO_PFCAE6_PFCAE68_SHIFT (8u)
+#define GPIO_PFCAE6_PFCAE69_SHIFT (9u)
+#define GPIO_PFCAE6_PFCAE610_SHIFT (10u)
+#define GPIO_PFCAE6_PFCAE611_SHIFT (11u)
+#define GPIO_PFCAE6_PFCAE612_SHIFT (12u)
+#define GPIO_PFCAE6_PFCAE613_SHIFT (13u)
+#define GPIO_PFCAE6_PFCAE614_SHIFT (14u)
+#define GPIO_PFCAE6_PFCAE615_SHIFT (15u)
+
+#define GPIO_PIBC6_PIBC60_SHIFT (0u)
+#define GPIO_PIBC6_PIBC61_SHIFT (1u)
+#define GPIO_PIBC6_PIBC62_SHIFT (2u)
+#define GPIO_PIBC6_PIBC63_SHIFT (3u)
+#define GPIO_PIBC6_PIBC64_SHIFT (4u)
+#define GPIO_PIBC6_PIBC65_SHIFT (5u)
+#define GPIO_PIBC6_PIBC66_SHIFT (6u)
+#define GPIO_PIBC6_PIBC67_SHIFT (7u)
+#define GPIO_PIBC6_PIBC68_SHIFT (8u)
+#define GPIO_PIBC6_PIBC69_SHIFT (9u)
+#define GPIO_PIBC6_PIBC610_SHIFT (10u)
+#define GPIO_PIBC6_PIBC611_SHIFT (11u)
+#define GPIO_PIBC6_PIBC612_SHIFT (12u)
+#define GPIO_PIBC6_PIBC613_SHIFT (13u)
+#define GPIO_PIBC6_PIBC614_SHIFT (14u)
+#define GPIO_PIBC6_PIBC615_SHIFT (15u)
+
+#define GPIO_PBDC6_PBDC60_SHIFT (0u)
+#define GPIO_PBDC6_PBDC61_SHIFT (1u)
+#define GPIO_PBDC6_PBDC62_SHIFT (2u)
+#define GPIO_PBDC6_PBDC63_SHIFT (3u)
+#define GPIO_PBDC6_PBDC64_SHIFT (4u)
+#define GPIO_PBDC6_PBDC65_SHIFT (5u)
+#define GPIO_PBDC6_PBDC66_SHIFT (6u)
+#define GPIO_PBDC6_PBDC67_SHIFT (7u)
+#define GPIO_PBDC6_PBDC68_SHIFT (8u)
+#define GPIO_PBDC6_PBDC69_SHIFT (9u)
+#define GPIO_PBDC6_PBDC610_SHIFT (10u)
+#define GPIO_PBDC6_PBDC611_SHIFT (11u)
+#define GPIO_PBDC6_PBDC612_SHIFT (12u)
+#define GPIO_PBDC6_PBDC613_SHIFT (13u)
+#define GPIO_PBDC6_PBDC614_SHIFT (14u)
+#define GPIO_PBDC6_PBDC615_SHIFT (15u)
+
+#define GPIO_PIPC6_PIPC60_SHIFT (0u)
+#define GPIO_PIPC6_PIPC61_SHIFT (1u)
+#define GPIO_PIPC6_PIPC62_SHIFT (2u)
+#define GPIO_PIPC6_PIPC63_SHIFT (3u)
+#define GPIO_PIPC6_PIPC64_SHIFT (4u)
+#define GPIO_PIPC6_PIPC65_SHIFT (5u)
+#define GPIO_PIPC6_PIPC66_SHIFT (6u)
+#define GPIO_PIPC6_PIPC67_SHIFT (7u)
+#define GPIO_PIPC6_PIPC68_SHIFT (8u)
+#define GPIO_PIPC6_PIPC69_SHIFT (9u)
+#define GPIO_PIPC6_PIPC610_SHIFT (10u)
+#define GPIO_PIPC6_PIPC611_SHIFT (11u)
+#define GPIO_PIPC6_PIPC612_SHIFT (12u)
+#define GPIO_PIPC6_PIPC613_SHIFT (13u)
+#define GPIO_PIPC6_PIPC614_SHIFT (14u)
+#define GPIO_PIPC6_PIPC615_SHIFT (15u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70_SHIFT (0u)
+#define GPIO_P7_P71_SHIFT (1u)
+#define GPIO_P7_P72_SHIFT (2u)
+#define GPIO_P7_P73_SHIFT (3u)
+#define GPIO_P7_P74_SHIFT (4u)
+#define GPIO_P7_P75_SHIFT (5u)
+#define GPIO_P7_P76_SHIFT (6u)
+#define GPIO_P7_P77_SHIFT (7u)
+#define GPIO_P7_P78_SHIFT (8u)
+#define GPIO_P7_P79_SHIFT (9u)
+#define GPIO_P7_P710_SHIFT (10u)
+#define GPIO_P7_P711_SHIFT (11u)
+#define GPIO_P7_P712_SHIFT (12u)
+#define GPIO_P7_P713_SHIFT (13u)
+#define GPIO_P7_P714_SHIFT (14u)
+#define GPIO_P7_P715_SHIFT (15u)
+
+#define GPIO_PSR7_PSR70_SHIFT (0u)
+#define GPIO_PSR7_PSR71_SHIFT (1u)
+#define GPIO_PSR7_PSR72_SHIFT (2u)
+#define GPIO_PSR7_PSR73_SHIFT (3u)
+#define GPIO_PSR7_PSR74_SHIFT (4u)
+#define GPIO_PSR7_PSR75_SHIFT (5u)
+#define GPIO_PSR7_PSR76_SHIFT (6u)
+#define GPIO_PSR7_PSR77_SHIFT (7u)
+#define GPIO_PSR7_PSR78_SHIFT (8u)
+#define GPIO_PSR7_PSR79_SHIFT (9u)
+#define GPIO_PSR7_PSR710_SHIFT (10u)
+#define GPIO_PSR7_PSR711_SHIFT (11u)
+#define GPIO_PSR7_PSR712_SHIFT (12u)
+#define GPIO_PSR7_PSR713_SHIFT (13u)
+#define GPIO_PSR7_PSR714_SHIFT (14u)
+#define GPIO_PSR7_PSR715_SHIFT (15u)
+#define GPIO_PSR7_PSR716_SHIFT (16u)
+#define GPIO_PSR7_PSR717_SHIFT (17u)
+#define GPIO_PSR7_PSR718_SHIFT (18u)
+#define GPIO_PSR7_PSR719_SHIFT (19u)
+#define GPIO_PSR7_PSR720_SHIFT (20u)
+#define GPIO_PSR7_PSR721_SHIFT (21u)
+#define GPIO_PSR7_PSR722_SHIFT (22u)
+#define GPIO_PSR7_PSR723_SHIFT (23u)
+#define GPIO_PSR7_PSR724_SHIFT (24u)
+#define GPIO_PSR7_PSR725_SHIFT (25u)
+#define GPIO_PSR7_PSR726_SHIFT (26u)
+#define GPIO_PSR7_PSR727_SHIFT (27u)
+#define GPIO_PSR7_PSR728_SHIFT (28u)
+#define GPIO_PSR7_PSR729_SHIFT (29u)
+#define GPIO_PSR7_PSR730_SHIFT (30u)
+#define GPIO_PSR7_PSR731_SHIFT (31u)
+
+#define GPIO_PPR7_PPR70_SHIFT (0u)
+#define GPIO_PPR7_PPR71_SHIFT (1u)
+#define GPIO_PPR7_PPR72_SHIFT (2u)
+#define GPIO_PPR7_PPR73_SHIFT (3u)
+#define GPIO_PPR7_PPR74_SHIFT (4u)
+#define GPIO_PPR7_PPR75_SHIFT (5u)
+#define GPIO_PPR7_PPR76_SHIFT (6u)
+#define GPIO_PPR7_PPR77_SHIFT (7u)
+#define GPIO_PPR7_PPR78_SHIFT (8u)
+#define GPIO_PPR7_PPR79_SHIFT (9u)
+#define GPIO_PPR7_PPR710_SHIFT (10u)
+#define GPIO_PPR7_PPR711_SHIFT (11u)
+#define GPIO_PPR7_PPR712_SHIFT (12u)
+#define GPIO_PPR7_PPR713_SHIFT (13u)
+#define GPIO_PPR7_PPR714_SHIFT (14u)
+#define GPIO_PPR7_PPR715_SHIFT (15u)
+
+#define GPIO_PM7_PM70_SHIFT (0u)
+#define GPIO_PM7_PM71_SHIFT (1u)
+#define GPIO_PM7_PM72_SHIFT (2u)
+#define GPIO_PM7_PM73_SHIFT (3u)
+#define GPIO_PM7_PM74_SHIFT (4u)
+#define GPIO_PM7_PM75_SHIFT (5u)
+#define GPIO_PM7_PM76_SHIFT (6u)
+#define GPIO_PM7_PM77_SHIFT (7u)
+#define GPIO_PM7_PM78_SHIFT (8u)
+#define GPIO_PM7_PM79_SHIFT (9u)
+#define GPIO_PM7_PM710_SHIFT (10u)
+#define GPIO_PM7_PM711_SHIFT (11u)
+#define GPIO_PM7_PM712_SHIFT (12u)
+#define GPIO_PM7_PM713_SHIFT (13u)
+#define GPIO_PM7_PM714_SHIFT (14u)
+#define GPIO_PM7_PM715_SHIFT (15u)
+
+#define GPIO_PMC7_PMC70_SHIFT (0u)
+#define GPIO_PMC7_PMC71_SHIFT (1u)
+#define GPIO_PMC7_PMC72_SHIFT (2u)
+#define GPIO_PMC7_PMC73_SHIFT (3u)
+#define GPIO_PMC7_PMC74_SHIFT (4u)
+#define GPIO_PMC7_PMC75_SHIFT (5u)
+#define GPIO_PMC7_PMC76_SHIFT (6u)
+#define GPIO_PMC7_PMC77_SHIFT (7u)
+#define GPIO_PMC7_PMC78_SHIFT (8u)
+#define GPIO_PMC7_PMC79_SHIFT (9u)
+#define GPIO_PMC7_PMC710_SHIFT (10u)
+#define GPIO_PMC7_PMC711_SHIFT (11u)
+#define GPIO_PMC7_PMC712_SHIFT (12u)
+#define GPIO_PMC7_PMC713_SHIFT (13u)
+#define GPIO_PMC7_PMC714_SHIFT (14u)
+#define GPIO_PMC7_PMC715_SHIFT (15u)
+
+#define GPIO_PFC7_PFC70_SHIFT (0u)
+#define GPIO_PFC7_PFC71_SHIFT (1u)
+#define GPIO_PFC7_PFC72_SHIFT (2u)
+#define GPIO_PFC7_PFC73_SHIFT (3u)
+#define GPIO_PFC7_PFC74_SHIFT (4u)
+#define GPIO_PFC7_PFC75_SHIFT (5u)
+#define GPIO_PFC7_PFC76_SHIFT (6u)
+#define GPIO_PFC7_PFC77_SHIFT (7u)
+#define GPIO_PFC7_PFC78_SHIFT (8u)
+#define GPIO_PFC7_PFC79_SHIFT (9u)
+#define GPIO_PFC7_PFC710_SHIFT (10u)
+#define GPIO_PFC7_PFC711_SHIFT (11u)
+#define GPIO_PFC7_PFC712_SHIFT (12u)
+#define GPIO_PFC7_PFC713_SHIFT (13u)
+#define GPIO_PFC7_PFC714_SHIFT (14u)
+#define GPIO_PFC7_PFC715_SHIFT (15u)
+
+#define GPIO_PFCE7_PFCE70_SHIFT (0u)
+#define GPIO_PFCE7_PFCE71_SHIFT (1u)
+#define GPIO_PFCE7_PFCE72_SHIFT (2u)
+#define GPIO_PFCE7_PFCE73_SHIFT (3u)
+#define GPIO_PFCE7_PFCE74_SHIFT (4u)
+#define GPIO_PFCE7_PFCE75_SHIFT (5u)
+#define GPIO_PFCE7_PFCE76_SHIFT (6u)
+#define GPIO_PFCE7_PFCE77_SHIFT (7u)
+#define GPIO_PFCE7_PFCE78_SHIFT (8u)
+#define GPIO_PFCE7_PFCE79_SHIFT (9u)
+#define GPIO_PFCE7_PFCE710_SHIFT (10u)
+#define GPIO_PFCE7_PFCE711_SHIFT (11u)
+#define GPIO_PFCE7_PFCE712_SHIFT (12u)
+#define GPIO_PFCE7_PFCE713_SHIFT (13u)
+#define GPIO_PFCE7_PFCE714_SHIFT (14u)
+#define GPIO_PFCE7_PFCE715_SHIFT (15u)
+
+#define GPIO_PNOT7_PNOT70_SHIFT (0u)
+#define GPIO_PNOT7_PNOT71_SHIFT (1u)
+#define GPIO_PNOT7_PNOT72_SHIFT (2u)
+#define GPIO_PNOT7_PNOT73_SHIFT (3u)
+#define GPIO_PNOT7_PNOT74_SHIFT (4u)
+#define GPIO_PNOT7_PNOT75_SHIFT (5u)
+#define GPIO_PNOT7_PNOT76_SHIFT (6u)
+#define GPIO_PNOT7_PNOT77_SHIFT (7u)
+#define GPIO_PNOT7_PNOT78_SHIFT (8u)
+#define GPIO_PNOT7_PNOT79_SHIFT (9u)
+#define GPIO_PNOT7_PNOT710_SHIFT (10u)
+#define GPIO_PNOT7_PNOT711_SHIFT (11u)
+#define GPIO_PNOT7_PNOT712_SHIFT (12u)
+#define GPIO_PNOT7_PNOT713_SHIFT (13u)
+#define GPIO_PNOT7_PNOT714_SHIFT (14u)
+#define GPIO_PNOT7_PNOT715_SHIFT (15u)
+
+#define GPIO_PMSR7_PMSR70_SHIFT (0u)
+#define GPIO_PMSR7_PMSR71_SHIFT (1u)
+#define GPIO_PMSR7_PMSR72_SHIFT (2u)
+#define GPIO_PMSR7_PMSR73_SHIFT (3u)
+#define GPIO_PMSR7_PMSR74_SHIFT (4u)
+#define GPIO_PMSR7_PMSR75_SHIFT (5u)
+#define GPIO_PMSR7_PMSR76_SHIFT (6u)
+#define GPIO_PMSR7_PMSR77_SHIFT (7u)
+#define GPIO_PMSR7_PMSR78_SHIFT (8u)
+#define GPIO_PMSR7_PMSR79_SHIFT (9u)
+#define GPIO_PMSR7_PMSR710_SHIFT (10u)
+#define GPIO_PMSR7_PMSR711_SHIFT (11u)
+#define GPIO_PMSR7_PMSR712_SHIFT (12u)
+#define GPIO_PMSR7_PMSR713_SHIFT (13u)
+#define GPIO_PMSR7_PMSR714_SHIFT (14u)
+#define GPIO_PMSR7_PMSR715_SHIFT (15u)
+#define GPIO_PMSR7_PMSR716_SHIFT (16u)
+#define GPIO_PMSR7_PMSR717_SHIFT (17u)
+#define GPIO_PMSR7_PMSR718_SHIFT (18u)
+#define GPIO_PMSR7_PMSR719_SHIFT (19u)
+#define GPIO_PMSR7_PMSR720_SHIFT (20u)
+#define GPIO_PMSR7_PMSR721_SHIFT (21u)
+#define GPIO_PMSR7_PMSR722_SHIFT (22u)
+#define GPIO_PMSR7_PMSR723_SHIFT (23u)
+#define GPIO_PMSR7_PMSR724_SHIFT (24u)
+#define GPIO_PMSR7_PMSR725_SHIFT (25u)
+#define GPIO_PMSR7_PMSR726_SHIFT (26u)
+#define GPIO_PMSR7_PMSR727_SHIFT (27u)
+#define GPIO_PMSR7_PMSR728_SHIFT (28u)
+#define GPIO_PMSR7_PMSR729_SHIFT (29u)
+#define GPIO_PMSR7_PMSR730_SHIFT (30u)
+#define GPIO_PMSR7_PMSR731_SHIFT (31u)
+
+#define GPIO_PMCSR7_PMCSR70_SHIFT (0u)
+#define GPIO_PMCSR7_PMCSR71_SHIFT (1u)
+#define GPIO_PMCSR7_PMCSR72_SHIFT (2u)
+#define GPIO_PMCSR7_PMCSR73_SHIFT (3u)
+#define GPIO_PMCSR7_PMCSR74_SHIFT (4u)
+#define GPIO_PMCSR7_PMCSR75_SHIFT (5u)
+#define GPIO_PMCSR7_PMCSR76_SHIFT (6u)
+#define GPIO_PMCSR7_PMCSR77_SHIFT (7u)
+#define GPIO_PMCSR7_PMCSR78_SHIFT (8u)
+#define GPIO_PMCSR7_PMCSR79_SHIFT (9u)
+#define GPIO_PMCSR7_PMCSR710_SHIFT (10u)
+#define GPIO_PMCSR7_PMCSR711_SHIFT (11u)
+#define GPIO_PMCSR7_PMCSR712_SHIFT (12u)
+#define GPIO_PMCSR7_PMCSR713_SHIFT (13u)
+#define GPIO_PMCSR7_PMCSR714_SHIFT (14u)
+#define GPIO_PMCSR7_PMCSR715_SHIFT (15u)
+#define GPIO_PMCSR7_PMCSR716_SHIFT (16u)
+#define GPIO_PMCSR7_PMCSR717_SHIFT (17u)
+#define GPIO_PMCSR7_PMCSR718_SHIFT (18u)
+#define GPIO_PMCSR7_PMCSR719_SHIFT (19u)
+#define GPIO_PMCSR7_PMCSR720_SHIFT (20u)
+#define GPIO_PMCSR7_PMCSR721_SHIFT (21u)
+#define GPIO_PMCSR7_PMCSR722_SHIFT (22u)
+#define GPIO_PMCSR7_PMCSR723_SHIFT (23u)
+#define GPIO_PMCSR7_PMCSR724_SHIFT (24u)
+#define GPIO_PMCSR7_PMCSR725_SHIFT (25u)
+#define GPIO_PMCSR7_PMCSR726_SHIFT (26u)
+#define GPIO_PMCSR7_PMCSR727_SHIFT (27u)
+#define GPIO_PMCSR7_PMCSR728_SHIFT (28u)
+#define GPIO_PMCSR7_PMCSR729_SHIFT (29u)
+#define GPIO_PMCSR7_PMCSR730_SHIFT (30u)
+#define GPIO_PMCSR7_PMCSR731_SHIFT (31u)
+
+#define GPIO_PFCAE7_PFCAE70_SHIFT (0u)
+#define GPIO_PFCAE7_PFCAE71_SHIFT (1u)
+#define GPIO_PFCAE7_PFCAE72_SHIFT (2u)
+#define GPIO_PFCAE7_PFCAE73_SHIFT (3u)
+#define GPIO_PFCAE7_PFCAE74_SHIFT (4u)
+#define GPIO_PFCAE7_PFCAE75_SHIFT (5u)
+#define GPIO_PFCAE7_PFCAE76_SHIFT (6u)
+#define GPIO_PFCAE7_PFCAE77_SHIFT (7u)
+#define GPIO_PFCAE7_PFCAE78_SHIFT (8u)
+#define GPIO_PFCAE7_PFCAE79_SHIFT (9u)
+#define GPIO_PFCAE7_PFCAE710_SHIFT (10u)
+#define GPIO_PFCAE7_PFCAE711_SHIFT (11u)
+#define GPIO_PFCAE7_PFCAE712_SHIFT (12u)
+#define GPIO_PFCAE7_PFCAE713_SHIFT (13u)
+#define GPIO_PFCAE7_PFCAE714_SHIFT (14u)
+#define GPIO_PFCAE7_PFCAE715_SHIFT (15u)
+
+#define GPIO_PIBC7_PIBC70_SHIFT (0u)
+#define GPIO_PIBC7_PIBC71_SHIFT (1u)
+#define GPIO_PIBC7_PIBC72_SHIFT (2u)
+#define GPIO_PIBC7_PIBC73_SHIFT (3u)
+#define GPIO_PIBC7_PIBC74_SHIFT (4u)
+#define GPIO_PIBC7_PIBC75_SHIFT (5u)
+#define GPIO_PIBC7_PIBC76_SHIFT (6u)
+#define GPIO_PIBC7_PIBC77_SHIFT (7u)
+#define GPIO_PIBC7_PIBC78_SHIFT (8u)
+#define GPIO_PIBC7_PIBC79_SHIFT (9u)
+#define GPIO_PIBC7_PIBC710_SHIFT (10u)
+#define GPIO_PIBC7_PIBC711_SHIFT (11u)
+#define GPIO_PIBC7_PIBC712_SHIFT (12u)
+#define GPIO_PIBC7_PIBC713_SHIFT (13u)
+#define GPIO_PIBC7_PIBC714_SHIFT (14u)
+#define GPIO_PIBC7_PIBC715_SHIFT (15u)
+
+#define GPIO_PBDC7_PBDC70_SHIFT (0u)
+#define GPIO_PBDC7_PBDC71_SHIFT (1u)
+#define GPIO_PBDC7_PBDC72_SHIFT (2u)
+#define GPIO_PBDC7_PBDC73_SHIFT (3u)
+#define GPIO_PBDC7_PBDC74_SHIFT (4u)
+#define GPIO_PBDC7_PBDC75_SHIFT (5u)
+#define GPIO_PBDC7_PBDC76_SHIFT (6u)
+#define GPIO_PBDC7_PBDC77_SHIFT (7u)
+#define GPIO_PBDC7_PBDC78_SHIFT (8u)
+#define GPIO_PBDC7_PBDC79_SHIFT (9u)
+#define GPIO_PBDC7_PBDC710_SHIFT (10u)
+#define GPIO_PBDC7_PBDC711_SHIFT (11u)
+#define GPIO_PBDC7_PBDC712_SHIFT (12u)
+#define GPIO_PBDC7_PBDC713_SHIFT (13u)
+#define GPIO_PBDC7_PBDC714_SHIFT (14u)
+#define GPIO_PBDC7_PBDC715_SHIFT (15u)
+
+#define GPIO_PIPC7_PIPC70_SHIFT (0u)
+#define GPIO_PIPC7_PIPC71_SHIFT (1u)
+#define GPIO_PIPC7_PIPC72_SHIFT (2u)
+#define GPIO_PIPC7_PIPC73_SHIFT (3u)
+#define GPIO_PIPC7_PIPC74_SHIFT (4u)
+#define GPIO_PIPC7_PIPC75_SHIFT (5u)
+#define GPIO_PIPC7_PIPC76_SHIFT (6u)
+#define GPIO_PIPC7_PIPC77_SHIFT (7u)
+#define GPIO_PIPC7_PIPC78_SHIFT (8u)
+#define GPIO_PIPC7_PIPC79_SHIFT (9u)
+#define GPIO_PIPC7_PIPC710_SHIFT (10u)
+#define GPIO_PIPC7_PIPC711_SHIFT (11u)
+#define GPIO_PIPC7_PIPC712_SHIFT (12u)
+#define GPIO_PIPC7_PIPC713_SHIFT (13u)
+#define GPIO_PIPC7_PIPC714_SHIFT (14u)
+#define GPIO_PIPC7_PIPC715_SHIFT (15u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80_SHIFT (0u)
+#define GPIO_P8_P81_SHIFT (1u)
+#define GPIO_P8_P82_SHIFT (2u)
+#define GPIO_P8_P83_SHIFT (3u)
+#define GPIO_P8_P84_SHIFT (4u)
+#define GPIO_P8_P85_SHIFT (5u)
+#define GPIO_P8_P86_SHIFT (6u)
+#define GPIO_P8_P87_SHIFT (7u)
+#define GPIO_P8_P88_SHIFT (8u)
+#define GPIO_P8_P89_SHIFT (9u)
+#define GPIO_P8_P810_SHIFT (10u)
+#define GPIO_P8_P811_SHIFT (11u)
+#define GPIO_P8_P812_SHIFT (12u)
+#define GPIO_P8_P813_SHIFT (13u)
+#define GPIO_P8_P814_SHIFT (14u)
+#define GPIO_P8_P815_SHIFT (15u)
+
+#define GPIO_PSR8_PSR80_SHIFT (0u)
+#define GPIO_PSR8_PSR81_SHIFT (1u)
+#define GPIO_PSR8_PSR82_SHIFT (2u)
+#define GPIO_PSR8_PSR83_SHIFT (3u)
+#define GPIO_PSR8_PSR84_SHIFT (4u)
+#define GPIO_PSR8_PSR85_SHIFT (5u)
+#define GPIO_PSR8_PSR86_SHIFT (6u)
+#define GPIO_PSR8_PSR87_SHIFT (7u)
+#define GPIO_PSR8_PSR88_SHIFT (8u)
+#define GPIO_PSR8_PSR89_SHIFT (9u)
+#define GPIO_PSR8_PSR810_SHIFT (10u)
+#define GPIO_PSR8_PSR811_SHIFT (11u)
+#define GPIO_PSR8_PSR812_SHIFT (12u)
+#define GPIO_PSR8_PSR813_SHIFT (13u)
+#define GPIO_PSR8_PSR814_SHIFT (14u)
+#define GPIO_PSR8_PSR815_SHIFT (15u)
+#define GPIO_PSR8_PSR816_SHIFT (16u)
+#define GPIO_PSR8_PSR817_SHIFT (17u)
+#define GPIO_PSR8_PSR818_SHIFT (18u)
+#define GPIO_PSR8_PSR819_SHIFT (19u)
+#define GPIO_PSR8_PSR820_SHIFT (20u)
+#define GPIO_PSR8_PSR821_SHIFT (21u)
+#define GPIO_PSR8_PSR822_SHIFT (22u)
+#define GPIO_PSR8_PSR823_SHIFT (23u)
+#define GPIO_PSR8_PSR824_SHIFT (24u)
+#define GPIO_PSR8_PSR825_SHIFT (25u)
+#define GPIO_PSR8_PSR826_SHIFT (26u)
+#define GPIO_PSR8_PSR827_SHIFT (27u)
+#define GPIO_PSR8_PSR828_SHIFT (28u)
+#define GPIO_PSR8_PSR829_SHIFT (29u)
+#define GPIO_PSR8_PSR830_SHIFT (30u)
+#define GPIO_PSR8_PSR831_SHIFT (31u)
+
+#define GPIO_PPR8_PPR80_SHIFT (0u)
+#define GPIO_PPR8_PPR81_SHIFT (1u)
+#define GPIO_PPR8_PPR82_SHIFT (2u)
+#define GPIO_PPR8_PPR83_SHIFT (3u)
+#define GPIO_PPR8_PPR84_SHIFT (4u)
+#define GPIO_PPR8_PPR85_SHIFT (5u)
+#define GPIO_PPR8_PPR86_SHIFT (6u)
+#define GPIO_PPR8_PPR87_SHIFT (7u)
+#define GPIO_PPR8_PPR88_SHIFT (8u)
+#define GPIO_PPR8_PPR89_SHIFT (9u)
+#define GPIO_PPR8_PPR810_SHIFT (10u)
+#define GPIO_PPR8_PPR811_SHIFT (11u)
+#define GPIO_PPR8_PPR812_SHIFT (12u)
+#define GPIO_PPR8_PPR813_SHIFT (13u)
+#define GPIO_PPR8_PPR814_SHIFT (14u)
+#define GPIO_PPR8_PPR815_SHIFT (15u)
+
+#define GPIO_PM8_PM80_SHIFT (0u)
+#define GPIO_PM8_PM81_SHIFT (1u)
+#define GPIO_PM8_PM82_SHIFT (2u)
+#define GPIO_PM8_PM83_SHIFT (3u)
+#define GPIO_PM8_PM84_SHIFT (4u)
+#define GPIO_PM8_PM85_SHIFT (5u)
+#define GPIO_PM8_PM86_SHIFT (6u)
+#define GPIO_PM8_PM87_SHIFT (7u)
+#define GPIO_PM8_PM88_SHIFT (8u)
+#define GPIO_PM8_PM89_SHIFT (9u)
+#define GPIO_PM8_PM810_SHIFT (10u)
+#define GPIO_PM8_PM811_SHIFT (11u)
+#define GPIO_PM8_PM812_SHIFT (12u)
+#define GPIO_PM8_PM813_SHIFT (13u)
+#define GPIO_PM8_PM814_SHIFT (14u)
+#define GPIO_PM8_PM815_SHIFT (15u)
+
+#define GPIO_PMC8_PMC80_SHIFT (0u)
+#define GPIO_PMC8_PMC81_SHIFT (1u)
+#define GPIO_PMC8_PMC82_SHIFT (2u)
+#define GPIO_PMC8_PMC83_SHIFT (3u)
+#define GPIO_PMC8_PMC84_SHIFT (4u)
+#define GPIO_PMC8_PMC85_SHIFT (5u)
+#define GPIO_PMC8_PMC86_SHIFT (6u)
+#define GPIO_PMC8_PMC87_SHIFT (7u)
+#define GPIO_PMC8_PMC88_SHIFT (8u)
+#define GPIO_PMC8_PMC89_SHIFT (9u)
+#define GPIO_PMC8_PMC810_SHIFT (10u)
+#define GPIO_PMC8_PMC811_SHIFT (11u)
+#define GPIO_PMC8_PMC812_SHIFT (12u)
+#define GPIO_PMC8_PMC813_SHIFT (13u)
+#define GPIO_PMC8_PMC814_SHIFT (14u)
+#define GPIO_PMC8_PMC815_SHIFT (15u)
+
+#define GPIO_PFC8_PFC80_SHIFT (0u)
+#define GPIO_PFC8_PFC81_SHIFT (1u)
+#define GPIO_PFC8_PFC82_SHIFT (2u)
+#define GPIO_PFC8_PFC83_SHIFT (3u)
+#define GPIO_PFC8_PFC84_SHIFT (4u)
+#define GPIO_PFC8_PFC85_SHIFT (5u)
+#define GPIO_PFC8_PFC86_SHIFT (6u)
+#define GPIO_PFC8_PFC87_SHIFT (7u)
+#define GPIO_PFC8_PFC88_SHIFT (8u)
+#define GPIO_PFC8_PFC89_SHIFT (9u)
+#define GPIO_PFC8_PFC810_SHIFT (10u)
+#define GPIO_PFC8_PFC811_SHIFT (11u)
+#define GPIO_PFC8_PFC812_SHIFT (12u)
+#define GPIO_PFC8_PFC813_SHIFT (13u)
+#define GPIO_PFC8_PFC814_SHIFT (14u)
+#define GPIO_PFC8_PFC815_SHIFT (15u)
+
+#define GPIO_PFCE8_PFCE80_SHIFT (0u)
+#define GPIO_PFCE8_PFCE81_SHIFT (1u)
+#define GPIO_PFCE8_PFCE82_SHIFT (2u)
+#define GPIO_PFCE8_PFCE83_SHIFT (3u)
+#define GPIO_PFCE8_PFCE84_SHIFT (4u)
+#define GPIO_PFCE8_PFCE85_SHIFT (5u)
+#define GPIO_PFCE8_PFCE86_SHIFT (6u)
+#define GPIO_PFCE8_PFCE87_SHIFT (7u)
+#define GPIO_PFCE8_PFCE88_SHIFT (8u)
+#define GPIO_PFCE8_PFCE89_SHIFT (9u)
+#define GPIO_PFCE8_PFCE810_SHIFT (10u)
+#define GPIO_PFCE8_PFCE811_SHIFT (11u)
+#define GPIO_PFCE8_PFCE812_SHIFT (12u)
+#define GPIO_PFCE8_PFCE813_SHIFT (13u)
+#define GPIO_PFCE8_PFCE814_SHIFT (14u)
+#define GPIO_PFCE8_PFCE815_SHIFT (15u)
+
+#define GPIO_PNOT8_PNOT80_SHIFT (0u)
+#define GPIO_PNOT8_PNOT81_SHIFT (1u)
+#define GPIO_PNOT8_PNOT82_SHIFT (2u)
+#define GPIO_PNOT8_PNOT83_SHIFT (3u)
+#define GPIO_PNOT8_PNOT84_SHIFT (4u)
+#define GPIO_PNOT8_PNOT85_SHIFT (5u)
+#define GPIO_PNOT8_PNOT86_SHIFT (6u)
+#define GPIO_PNOT8_PNOT87_SHIFT (7u)
+#define GPIO_PNOT8_PNOT88_SHIFT (8u)
+#define GPIO_PNOT8_PNOT89_SHIFT (9u)
+#define GPIO_PNOT8_PNOT810_SHIFT (10u)
+#define GPIO_PNOT8_PNOT811_SHIFT (11u)
+#define GPIO_PNOT8_PNOT812_SHIFT (12u)
+#define GPIO_PNOT8_PNOT813_SHIFT (13u)
+#define GPIO_PNOT8_PNOT814_SHIFT (14u)
+#define GPIO_PNOT8_PNOT815_SHIFT (15u)
+
+#define GPIO_PMSR8_PMSR80_SHIFT (0u)
+#define GPIO_PMSR8_PMSR81_SHIFT (1u)
+#define GPIO_PMSR8_PMSR82_SHIFT (2u)
+#define GPIO_PMSR8_PMSR83_SHIFT (3u)
+#define GPIO_PMSR8_PMSR84_SHIFT (4u)
+#define GPIO_PMSR8_PMSR85_SHIFT (5u)
+#define GPIO_PMSR8_PMSR86_SHIFT (6u)
+#define GPIO_PMSR8_PMSR87_SHIFT (7u)
+#define GPIO_PMSR8_PMSR88_SHIFT (8u)
+#define GPIO_PMSR8_PMSR89_SHIFT (9u)
+#define GPIO_PMSR8_PMSR810_SHIFT (10u)
+#define GPIO_PMSR8_PMSR811_SHIFT (11u)
+#define GPIO_PMSR8_PMSR812_SHIFT (12u)
+#define GPIO_PMSR8_PMSR813_SHIFT (13u)
+#define GPIO_PMSR8_PMSR814_SHIFT (14u)
+#define GPIO_PMSR8_PMSR815_SHIFT (15u)
+#define GPIO_PMSR8_PMSR816_SHIFT (16u)
+#define GPIO_PMSR8_PMSR817_SHIFT (17u)
+#define GPIO_PMSR8_PMSR818_SHIFT (18u)
+#define GPIO_PMSR8_PMSR819_SHIFT (19u)
+#define GPIO_PMSR8_PMSR820_SHIFT (20u)
+#define GPIO_PMSR8_PMSR821_SHIFT (21u)
+#define GPIO_PMSR8_PMSR822_SHIFT (22u)
+#define GPIO_PMSR8_PMSR823_SHIFT (23u)
+#define GPIO_PMSR8_PMSR824_SHIFT (24u)
+#define GPIO_PMSR8_PMSR825_SHIFT (25u)
+#define GPIO_PMSR8_PMSR826_SHIFT (26u)
+#define GPIO_PMSR8_PMSR827_SHIFT (27u)
+#define GPIO_PMSR8_PMSR828_SHIFT (28u)
+#define GPIO_PMSR8_PMSR829_SHIFT (29u)
+#define GPIO_PMSR8_PMSR830_SHIFT (30u)
+#define GPIO_PMSR8_PMSR831_SHIFT (31u)
+
+#define GPIO_PMCSR8_PMCSR80_SHIFT (0u)
+#define GPIO_PMCSR8_PMCSR81_SHIFT (1u)
+#define GPIO_PMCSR8_PMCSR82_SHIFT (2u)
+#define GPIO_PMCSR8_PMCSR83_SHIFT (3u)
+#define GPIO_PMCSR8_PMCSR84_SHIFT (4u)
+#define GPIO_PMCSR8_PMCSR85_SHIFT (5u)
+#define GPIO_PMCSR8_PMCSR86_SHIFT (6u)
+#define GPIO_PMCSR8_PMCSR87_SHIFT (7u)
+#define GPIO_PMCSR8_PMCSR88_SHIFT (8u)
+#define GPIO_PMCSR8_PMCSR89_SHIFT (9u)
+#define GPIO_PMCSR8_PMCSR810_SHIFT (10u)
+#define GPIO_PMCSR8_PMCSR811_SHIFT (11u)
+#define GPIO_PMCSR8_PMCSR812_SHIFT (12u)
+#define GPIO_PMCSR8_PMCSR813_SHIFT (13u)
+#define GPIO_PMCSR8_PMCSR814_SHIFT (14u)
+#define GPIO_PMCSR8_PMCSR815_SHIFT (15u)
+#define GPIO_PMCSR8_PMCSR816_SHIFT (16u)
+#define GPIO_PMCSR8_PMCSR817_SHIFT (17u)
+#define GPIO_PMCSR8_PMCSR818_SHIFT (18u)
+#define GPIO_PMCSR8_PMCSR819_SHIFT (19u)
+#define GPIO_PMCSR8_PMCSR820_SHIFT (20u)
+#define GPIO_PMCSR8_PMCSR821_SHIFT (21u)
+#define GPIO_PMCSR8_PMCSR822_SHIFT (22u)
+#define GPIO_PMCSR8_PMCSR823_SHIFT (23u)
+#define GPIO_PMCSR8_PMCSR824_SHIFT (24u)
+#define GPIO_PMCSR8_PMCSR825_SHIFT (25u)
+#define GPIO_PMCSR8_PMCSR826_SHIFT (26u)
+#define GPIO_PMCSR8_PMCSR827_SHIFT (27u)
+#define GPIO_PMCSR8_PMCSR828_SHIFT (28u)
+#define GPIO_PMCSR8_PMCSR829_SHIFT (29u)
+#define GPIO_PMCSR8_PMCSR830_SHIFT (30u)
+#define GPIO_PMCSR8_PMCSR831_SHIFT (31u)
+
+#define GPIO_PFCAE8_PFCAE80_SHIFT (0u)
+#define GPIO_PFCAE8_PFCAE81_SHIFT (1u)
+#define GPIO_PFCAE8_PFCAE82_SHIFT (2u)
+#define GPIO_PFCAE8_PFCAE83_SHIFT (3u)
+#define GPIO_PFCAE8_PFCAE84_SHIFT (4u)
+#define GPIO_PFCAE8_PFCAE85_SHIFT (5u)
+#define GPIO_PFCAE8_PFCAE86_SHIFT (6u)
+#define GPIO_PFCAE8_PFCAE87_SHIFT (7u)
+#define GPIO_PFCAE8_PFCAE88_SHIFT (8u)
+#define GPIO_PFCAE8_PFCAE89_SHIFT (9u)
+#define GPIO_PFCAE8_PFCAE810_SHIFT (10u)
+#define GPIO_PFCAE8_PFCAE811_SHIFT (11u)
+#define GPIO_PFCAE8_PFCAE812_SHIFT (12u)
+#define GPIO_PFCAE8_PFCAE813_SHIFT (13u)
+#define GPIO_PFCAE8_PFCAE814_SHIFT (14u)
+#define GPIO_PFCAE8_PFCAE815_SHIFT (15u)
+
+#define GPIO_PIBC8_PIBC80_SHIFT (0u)
+#define GPIO_PIBC8_PIBC81_SHIFT (1u)
+#define GPIO_PIBC8_PIBC82_SHIFT (2u)
+#define GPIO_PIBC8_PIBC83_SHIFT (3u)
+#define GPIO_PIBC8_PIBC84_SHIFT (4u)
+#define GPIO_PIBC8_PIBC85_SHIFT (5u)
+#define GPIO_PIBC8_PIBC86_SHIFT (6u)
+#define GPIO_PIBC8_PIBC87_SHIFT (7u)
+#define GPIO_PIBC8_PIBC88_SHIFT (8u)
+#define GPIO_PIBC8_PIBC89_SHIFT (9u)
+#define GPIO_PIBC8_PIBC810_SHIFT (10u)
+#define GPIO_PIBC8_PIBC811_SHIFT (11u)
+#define GPIO_PIBC8_PIBC812_SHIFT (12u)
+#define GPIO_PIBC8_PIBC813_SHIFT (13u)
+#define GPIO_PIBC8_PIBC814_SHIFT (14u)
+#define GPIO_PIBC8_PIBC815_SHIFT (15u)
+
+#define GPIO_PBDC8_PBDC80_SHIFT (0u)
+#define GPIO_PBDC8_PBDC81_SHIFT (1u)
+#define GPIO_PBDC8_PBDC82_SHIFT (2u)
+#define GPIO_PBDC8_PBDC83_SHIFT (3u)
+#define GPIO_PBDC8_PBDC84_SHIFT (4u)
+#define GPIO_PBDC8_PBDC85_SHIFT (5u)
+#define GPIO_PBDC8_PBDC86_SHIFT (6u)
+#define GPIO_PBDC8_PBDC87_SHIFT (7u)
+#define GPIO_PBDC8_PBDC88_SHIFT (8u)
+#define GPIO_PBDC8_PBDC89_SHIFT (9u)
+#define GPIO_PBDC8_PBDC810_SHIFT (10u)
+#define GPIO_PBDC8_PBDC811_SHIFT (11u)
+#define GPIO_PBDC8_PBDC812_SHIFT (12u)
+#define GPIO_PBDC8_PBDC813_SHIFT (13u)
+#define GPIO_PBDC8_PBDC814_SHIFT (14u)
+#define GPIO_PBDC8_PBDC815_SHIFT (15u)
+
+#define GPIO_PIPC8_PIPC80_SHIFT (0u)
+#define GPIO_PIPC8_PIPC81_SHIFT (1u)
+#define GPIO_PIPC8_PIPC82_SHIFT (2u)
+#define GPIO_PIPC8_PIPC83_SHIFT (3u)
+#define GPIO_PIPC8_PIPC84_SHIFT (4u)
+#define GPIO_PIPC8_PIPC85_SHIFT (5u)
+#define GPIO_PIPC8_PIPC86_SHIFT (6u)
+#define GPIO_PIPC8_PIPC87_SHIFT (7u)
+#define GPIO_PIPC8_PIPC88_SHIFT (8u)
+#define GPIO_PIPC8_PIPC89_SHIFT (9u)
+#define GPIO_PIPC8_PIPC810_SHIFT (10u)
+#define GPIO_PIPC8_PIPC811_SHIFT (11u)
+#define GPIO_PIPC8_PIPC812_SHIFT (12u)
+#define GPIO_PIPC8_PIPC813_SHIFT (13u)
+#define GPIO_PIPC8_PIPC814_SHIFT (14u)
+#define GPIO_PIPC8_PIPC815_SHIFT (15u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90_SHIFT (0u)
+#define GPIO_P9_P91_SHIFT (1u)
+#define GPIO_P9_P92_SHIFT (2u)
+#define GPIO_P9_P93_SHIFT (3u)
+#define GPIO_P9_P94_SHIFT (4u)
+#define GPIO_P9_P95_SHIFT (5u)
+#define GPIO_P9_P96_SHIFT (6u)
+#define GPIO_P9_P97_SHIFT (7u)
+
+#define GPIO_PSR9_PSR90_SHIFT (0u)
+#define GPIO_PSR9_PSR91_SHIFT (1u)
+#define GPIO_PSR9_PSR92_SHIFT (2u)
+#define GPIO_PSR9_PSR93_SHIFT (3u)
+#define GPIO_PSR9_PSR94_SHIFT (4u)
+#define GPIO_PSR9_PSR95_SHIFT (5u)
+#define GPIO_PSR9_PSR96_SHIFT (6u)
+#define GPIO_PSR9_PSR97_SHIFT (7u)
+#define GPIO_PSR9_PSR916_SHIFT (16u)
+#define GPIO_PSR9_PSR917_SHIFT (17u)
+#define GPIO_PSR9_PSR918_SHIFT (18u)
+#define GPIO_PSR9_PSR919_SHIFT (19u)
+#define GPIO_PSR9_PSR920_SHIFT (20u)
+#define GPIO_PSR9_PSR921_SHIFT (21u)
+#define GPIO_PSR9_PSR922_SHIFT (22u)
+#define GPIO_PSR9_PSR923_SHIFT (23u)
+
+#define GPIO_PPR9_PPR90_SHIFT (0u)
+#define GPIO_PPR9_PPR91_SHIFT (1u)
+#define GPIO_PPR9_PPR92_SHIFT (2u)
+#define GPIO_PPR9_PPR93_SHIFT (3u)
+#define GPIO_PPR9_PPR94_SHIFT (4u)
+#define GPIO_PPR9_PPR95_SHIFT (5u)
+#define GPIO_PPR9_PPR96_SHIFT (6u)
+#define GPIO_PPR9_PPR97_SHIFT (7u)
+
+#define GPIO_PM9_PM90_SHIFT (0u)
+#define GPIO_PM9_PM91_SHIFT (1u)
+#define GPIO_PM9_PM92_SHIFT (2u)
+#define GPIO_PM9_PM93_SHIFT (3u)
+#define GPIO_PM9_PM94_SHIFT (4u)
+#define GPIO_PM9_PM95_SHIFT (5u)
+#define GPIO_PM9_PM96_SHIFT (6u)
+#define GPIO_PM9_PM97_SHIFT (7u)
+
+#define GPIO_PMC9_PMC90_SHIFT (0u)
+#define GPIO_PMC9_PMC91_SHIFT (1u)
+#define GPIO_PMC9_PMC92_SHIFT (2u)
+#define GPIO_PMC9_PMC93_SHIFT (3u)
+#define GPIO_PMC9_PMC94_SHIFT (4u)
+#define GPIO_PMC9_PMC95_SHIFT (5u)
+#define GPIO_PMC9_PMC96_SHIFT (6u)
+#define GPIO_PMC9_PMC97_SHIFT (7u)
+
+#define GPIO_PFC9_PFC90_SHIFT (0u)
+#define GPIO_PFC9_PFC91_SHIFT (1u)
+#define GPIO_PFC9_PFC92_SHIFT (2u)
+#define GPIO_PFC9_PFC93_SHIFT (3u)
+#define GPIO_PFC9_PFC94_SHIFT (4u)
+#define GPIO_PFC9_PFC95_SHIFT (5u)
+#define GPIO_PFC9_PFC96_SHIFT (6u)
+#define GPIO_PFC9_PFC97_SHIFT (7u)
+
+#define GPIO_PFCE9_PFCE90_SHIFT (0u)
+#define GPIO_PFCE9_PFCE91_SHIFT (1u)
+#define GPIO_PFCE9_PFCE92_SHIFT (2u)
+#define GPIO_PFCE9_PFCE93_SHIFT (3u)
+#define GPIO_PFCE9_PFCE94_SHIFT (4u)
+#define GPIO_PFCE9_PFCE95_SHIFT (5u)
+#define GPIO_PFCE9_PFCE96_SHIFT (6u)
+#define GPIO_PFCE9_PFCE97_SHIFT (7u)
+
+#define GPIO_PNOT9_PNOT90_SHIFT (0u)
+#define GPIO_PNOT9_PNOT91_SHIFT (1u)
+#define GPIO_PNOT9_PNOT92_SHIFT (2u)
+#define GPIO_PNOT9_PNOT93_SHIFT (3u)
+#define GPIO_PNOT9_PNOT94_SHIFT (4u)
+#define GPIO_PNOT9_PNOT95_SHIFT (5u)
+#define GPIO_PNOT9_PNOT96_SHIFT (6u)
+#define GPIO_PNOT9_PNOT97_SHIFT (7u)
+
+#define GPIO_PMSR9_PMSR90_SHIFT (0u)
+#define GPIO_PMSR9_PMSR91_SHIFT (1u)
+#define GPIO_PMSR9_PMSR92_SHIFT (2u)
+#define GPIO_PMSR9_PMSR93_SHIFT (3u)
+#define GPIO_PMSR9_PMSR94_SHIFT (4u)
+#define GPIO_PMSR9_PMSR95_SHIFT (5u)
+#define GPIO_PMSR9_PMSR96_SHIFT (6u)
+#define GPIO_PMSR9_PMSR97_SHIFT (7u)
+#define GPIO_PMSR9_PMSR916_SHIFT (16u)
+#define GPIO_PMSR9_PMSR917_SHIFT (17u)
+#define GPIO_PMSR9_PMSR918_SHIFT (18u)
+#define GPIO_PMSR9_PMSR919_SHIFT (19u)
+#define GPIO_PMSR9_PMSR920_SHIFT (20u)
+#define GPIO_PMSR9_PMSR921_SHIFT (21u)
+#define GPIO_PMSR9_PMSR922_SHIFT (22u)
+#define GPIO_PMSR9_PMSR923_SHIFT (23u)
+
+#define GPIO_PMCSR9_PMCSR90_SHIFT (0u)
+#define GPIO_PMCSR9_PMCSR91_SHIFT (1u)
+#define GPIO_PMCSR9_PMCSR92_SHIFT (2u)
+#define GPIO_PMCSR9_PMCSR93_SHIFT (3u)
+#define GPIO_PMCSR9_PMCSR94_SHIFT (4u)
+#define GPIO_PMCSR9_PMCSR95_SHIFT (5u)
+#define GPIO_PMCSR9_PMCSR96_SHIFT (6u)
+#define GPIO_PMCSR9_PMCSR97_SHIFT (7u)
+#define GPIO_PMCSR9_PMCSR916_SHIFT (16u)
+#define GPIO_PMCSR9_PMCSR917_SHIFT (17u)
+#define GPIO_PMCSR9_PMCSR918_SHIFT (18u)
+#define GPIO_PMCSR9_PMCSR919_SHIFT (19u)
+#define GPIO_PMCSR9_PMCSR920_SHIFT (20u)
+#define GPIO_PMCSR9_PMCSR921_SHIFT (21u)
+#define GPIO_PMCSR9_PMCSR922_SHIFT (22u)
+#define GPIO_PMCSR9_PMCSR923_SHIFT (23u)
+
+#define GPIO_PFCAE9_PFCAE90_SHIFT (0u)
+#define GPIO_PFCAE9_PFCAE91_SHIFT (1u)
+#define GPIO_PFCAE9_PFCAE92_SHIFT (2u)
+#define GPIO_PFCAE9_PFCAE93_SHIFT (3u)
+#define GPIO_PFCAE9_PFCAE94_SHIFT (4u)
+#define GPIO_PFCAE9_PFCAE95_SHIFT (5u)
+#define GPIO_PFCAE9_PFCAE96_SHIFT (6u)
+#define GPIO_PFCAE9_PFCAE97_SHIFT (7u)
+
+#define GPIO_PIBC9_PIBC90_SHIFT (0u)
+#define GPIO_PIBC9_PIBC91_SHIFT (1u)
+#define GPIO_PIBC9_PIBC92_SHIFT (2u)
+#define GPIO_PIBC9_PIBC93_SHIFT (3u)
+#define GPIO_PIBC9_PIBC94_SHIFT (4u)
+#define GPIO_PIBC9_PIBC95_SHIFT (5u)
+#define GPIO_PIBC9_PIBC96_SHIFT (6u)
+#define GPIO_PIBC9_PIBC97_SHIFT (7u)
+
+#define GPIO_PBDC9_PBDC90_SHIFT (0u)
+#define GPIO_PBDC9_PBDC91_SHIFT (1u)
+#define GPIO_PBDC9_PBDC92_SHIFT (2u)
+#define GPIO_PBDC9_PBDC93_SHIFT (3u)
+#define GPIO_PBDC9_PBDC94_SHIFT (4u)
+#define GPIO_PBDC9_PBDC95_SHIFT (5u)
+#define GPIO_PBDC9_PBDC96_SHIFT (6u)
+#define GPIO_PBDC9_PBDC97_SHIFT (7u)
+
+#define GPIO_PIPC9_PIPC90_SHIFT (0u)
+#define GPIO_PIPC9_PIPC91_SHIFT (1u)
+#define GPIO_PIPC9_PIPC92_SHIFT (2u)
+#define GPIO_PIPC9_PIPC93_SHIFT (3u)
+#define GPIO_PIPC9_PIPC94_SHIFT (4u)
+#define GPIO_PIPC9_PIPC95_SHIFT (5u)
+#define GPIO_PIPC9_PIPC96_SHIFT (6u)
+#define GPIO_PIPC9_PIPC97_SHIFT (7u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100_SHIFT (0u)
+#define GPIO_P10_P101_SHIFT (1u)
+#define GPIO_P10_P102_SHIFT (2u)
+#define GPIO_P10_P103_SHIFT (3u)
+#define GPIO_P10_P104_SHIFT (4u)
+#define GPIO_P10_P105_SHIFT (5u)
+#define GPIO_P10_P106_SHIFT (6u)
+#define GPIO_P10_P107_SHIFT (7u)
+#define GPIO_P10_P108_SHIFT (8u)
+#define GPIO_P10_P109_SHIFT (9u)
+#define GPIO_P10_P1010_SHIFT (10u)
+#define GPIO_P10_P1011_SHIFT (11u)
+#define GPIO_P10_P1012_SHIFT (12u)
+#define GPIO_P10_P1013_SHIFT (13u)
+#define GPIO_P10_P1014_SHIFT (14u)
+#define GPIO_P10_P1015_SHIFT (15u)
+
+#define GPIO_PSR10_PSR100_SHIFT (0u)
+#define GPIO_PSR10_PSR101_SHIFT (1u)
+#define GPIO_PSR10_PSR102_SHIFT (2u)
+#define GPIO_PSR10_PSR103_SHIFT (3u)
+#define GPIO_PSR10_PSR104_SHIFT (4u)
+#define GPIO_PSR10_PSR105_SHIFT (5u)
+#define GPIO_PSR10_PSR106_SHIFT (6u)
+#define GPIO_PSR10_PSR107_SHIFT (7u)
+#define GPIO_PSR10_PSR108_SHIFT (8u)
+#define GPIO_PSR10_PSR109_SHIFT (9u)
+#define GPIO_PSR10_PSR1010_SHIFT (10u)
+#define GPIO_PSR10_PSR1011_SHIFT (11u)
+#define GPIO_PSR10_PSR1012_SHIFT (12u)
+#define GPIO_PSR10_PSR1013_SHIFT (13u)
+#define GPIO_PSR10_PSR1014_SHIFT (14u)
+#define GPIO_PSR10_PSR1015_SHIFT (15u)
+#define GPIO_PSR10_PSR1016_SHIFT (16u)
+#define GPIO_PSR10_PSR1017_SHIFT (17u)
+#define GPIO_PSR10_PSR1018_SHIFT (18u)
+#define GPIO_PSR10_PSR1019_SHIFT (19u)
+#define GPIO_PSR10_PSR1020_SHIFT (20u)
+#define GPIO_PSR10_PSR1021_SHIFT (21u)
+#define GPIO_PSR10_PSR1022_SHIFT (22u)
+#define GPIO_PSR10_PSR1023_SHIFT (23u)
+#define GPIO_PSR10_PSR1024_SHIFT (24u)
+#define GPIO_PSR10_PSR1025_SHIFT (25u)
+#define GPIO_PSR10_PSR1026_SHIFT (26u)
+#define GPIO_PSR10_PSR1027_SHIFT (27u)
+#define GPIO_PSR10_PSR1028_SHIFT (28u)
+#define GPIO_PSR10_PSR1029_SHIFT (29u)
+#define GPIO_PSR10_PSR1030_SHIFT (30u)
+#define GPIO_PSR10_PSR1031_SHIFT (31u)
+
+#define GPIO_PPR10_PPR100_SHIFT (0u)
+#define GPIO_PPR10_PPR101_SHIFT (1u)
+#define GPIO_PPR10_PPR102_SHIFT (2u)
+#define GPIO_PPR10_PPR103_SHIFT (3u)
+#define GPIO_PPR10_PPR104_SHIFT (4u)
+#define GPIO_PPR10_PPR105_SHIFT (5u)
+#define GPIO_PPR10_PPR106_SHIFT (6u)
+#define GPIO_PPR10_PPR107_SHIFT (7u)
+#define GPIO_PPR10_PPR108_SHIFT (8u)
+#define GPIO_PPR10_PPR109_SHIFT (9u)
+#define GPIO_PPR10_PPR1010_SHIFT (10u)
+#define GPIO_PPR10_PPR1011_SHIFT (11u)
+#define GPIO_PPR10_PPR1012_SHIFT (12u)
+#define GPIO_PPR10_PPR1013_SHIFT (13u)
+#define GPIO_PPR10_PPR1014_SHIFT (14u)
+#define GPIO_PPR10_PPR1015_SHIFT (15u)
+
+#define GPIO_PM10_PM100_SHIFT (0u)
+#define GPIO_PM10_PM101_SHIFT (1u)
+#define GPIO_PM10_PM102_SHIFT (2u)
+#define GPIO_PM10_PM103_SHIFT (3u)
+#define GPIO_PM10_PM104_SHIFT (4u)
+#define GPIO_PM10_PM105_SHIFT (5u)
+#define GPIO_PM10_PM106_SHIFT (6u)
+#define GPIO_PM10_PM107_SHIFT (7u)
+#define GPIO_PM10_PM108_SHIFT (8u)
+#define GPIO_PM10_PM109_SHIFT (9u)
+#define GPIO_PM10_PM1010_SHIFT (10u)
+#define GPIO_PM10_PM1011_SHIFT (11u)
+#define GPIO_PM10_PM1012_SHIFT (12u)
+#define GPIO_PM10_PM1013_SHIFT (13u)
+#define GPIO_PM10_PM1014_SHIFT (14u)
+#define GPIO_PM10_PM1015_SHIFT (15u)
+
+#define GPIO_PMC10_PMC100_SHIFT (0u)
+#define GPIO_PMC10_PMC101_SHIFT (1u)
+#define GPIO_PMC10_PMC102_SHIFT (2u)
+#define GPIO_PMC10_PMC103_SHIFT (3u)
+#define GPIO_PMC10_PMC104_SHIFT (4u)
+#define GPIO_PMC10_PMC105_SHIFT (5u)
+#define GPIO_PMC10_PMC106_SHIFT (6u)
+#define GPIO_PMC10_PMC107_SHIFT (7u)
+#define GPIO_PMC10_PMC108_SHIFT (8u)
+#define GPIO_PMC10_PMC109_SHIFT (9u)
+#define GPIO_PMC10_PMC1010_SHIFT (10u)
+#define GPIO_PMC10_PMC1011_SHIFT (11u)
+#define GPIO_PMC10_PMC1012_SHIFT (12u)
+#define GPIO_PMC10_PMC1013_SHIFT (13u)
+#define GPIO_PMC10_PMC1014_SHIFT (14u)
+#define GPIO_PMC10_PMC1015_SHIFT (15u)
+
+#define GPIO_PFC10_PFC100_SHIFT (0u)
+#define GPIO_PFC10_PFC101_SHIFT (1u)
+#define GPIO_PFC10_PFC102_SHIFT (2u)
+#define GPIO_PFC10_PFC103_SHIFT (3u)
+#define GPIO_PFC10_PFC104_SHIFT (4u)
+#define GPIO_PFC10_PFC105_SHIFT (5u)
+#define GPIO_PFC10_PFC106_SHIFT (6u)
+#define GPIO_PFC10_PFC107_SHIFT (7u)
+#define GPIO_PFC10_PFC108_SHIFT (8u)
+#define GPIO_PFC10_PFC109_SHIFT (9u)
+#define GPIO_PFC10_PFC1010_SHIFT (10u)
+#define GPIO_PFC10_PFC1011_SHIFT (11u)
+#define GPIO_PFC10_PFC1012_SHIFT (12u)
+#define GPIO_PFC10_PFC1013_SHIFT (13u)
+#define GPIO_PFC10_PFC1014_SHIFT (14u)
+#define GPIO_PFC10_PFC1015_SHIFT (15u)
+
+#define GPIO_PFCE10_PFCE100_SHIFT (0u)
+#define GPIO_PFCE10_PFCE101_SHIFT (1u)
+#define GPIO_PFCE10_PFCE102_SHIFT (2u)
+#define GPIO_PFCE10_PFCE103_SHIFT (3u)
+#define GPIO_PFCE10_PFCE104_SHIFT (4u)
+#define GPIO_PFCE10_PFCE105_SHIFT (5u)
+#define GPIO_PFCE10_PFCE106_SHIFT (6u)
+#define GPIO_PFCE10_PFCE107_SHIFT (7u)
+#define GPIO_PFCE10_PFCE108_SHIFT (8u)
+#define GPIO_PFCE10_PFCE109_SHIFT (9u)
+#define GPIO_PFCE10_PFCE1010_SHIFT (10u)
+#define GPIO_PFCE10_PFCE1011_SHIFT (11u)
+#define GPIO_PFCE10_PFCE1012_SHIFT (12u)
+#define GPIO_PFCE10_PFCE1013_SHIFT (13u)
+#define GPIO_PFCE10_PFCE1014_SHIFT (14u)
+#define GPIO_PFCE10_PFCE1015_SHIFT (15u)
+
+#define GPIO_PNOT10_PNOT100_SHIFT (0u)
+#define GPIO_PNOT10_PNOT101_SHIFT (1u)
+#define GPIO_PNOT10_PNOT102_SHIFT (2u)
+#define GPIO_PNOT10_PNOT103_SHIFT (3u)
+#define GPIO_PNOT10_PNOT104_SHIFT (4u)
+#define GPIO_PNOT10_PNOT105_SHIFT (5u)
+#define GPIO_PNOT10_PNOT106_SHIFT (6u)
+#define GPIO_PNOT10_PNOT107_SHIFT (7u)
+#define GPIO_PNOT10_PNOT108_SHIFT (8u)
+#define GPIO_PNOT10_PNOT109_SHIFT (9u)
+#define GPIO_PNOT10_PNOT1010_SHIFT (10u)
+#define GPIO_PNOT10_PNOT1011_SHIFT (11u)
+#define GPIO_PNOT10_PNOT1012_SHIFT (12u)
+#define GPIO_PNOT10_PNOT1013_SHIFT (13u)
+#define GPIO_PNOT10_PNOT1014_SHIFT (14u)
+#define GPIO_PNOT10_PNOT1015_SHIFT (15u)
+
+#define GPIO_PMSR10_PMSR100_SHIFT (0u)
+#define GPIO_PMSR10_PMSR101_SHIFT (1u)
+#define GPIO_PMSR10_PMSR102_SHIFT (2u)
+#define GPIO_PMSR10_PMSR103_SHIFT (3u)
+#define GPIO_PMSR10_PMSR104_SHIFT (4u)
+#define GPIO_PMSR10_PMSR105_SHIFT (5u)
+#define GPIO_PMSR10_PMSR106_SHIFT (6u)
+#define GPIO_PMSR10_PMSR107_SHIFT (7u)
+#define GPIO_PMSR10_PMSR108_SHIFT (8u)
+#define GPIO_PMSR10_PMSR109_SHIFT (9u)
+#define GPIO_PMSR10_PMSR1010_SHIFT (10u)
+#define GPIO_PMSR10_PMSR1011_SHIFT (11u)
+#define GPIO_PMSR10_PMSR1012_SHIFT (12u)
+#define GPIO_PMSR10_PMSR1013_SHIFT (13u)
+#define GPIO_PMSR10_PMSR1014_SHIFT (14u)
+#define GPIO_PMSR10_PMSR1015_SHIFT (15u)
+#define GPIO_PMSR10_PMSR1016_SHIFT (16u)
+#define GPIO_PMSR10_PMSR1017_SHIFT (17u)
+#define GPIO_PMSR10_PMSR1018_SHIFT (18u)
+#define GPIO_PMSR10_PMSR1019_SHIFT (19u)
+#define GPIO_PMSR10_PMSR1020_SHIFT (20u)
+#define GPIO_PMSR10_PMSR1021_SHIFT (21u)
+#define GPIO_PMSR10_PMSR1022_SHIFT (22u)
+#define GPIO_PMSR10_PMSR1023_SHIFT (23u)
+#define GPIO_PMSR10_PMSR1024_SHIFT (24u)
+#define GPIO_PMSR10_PMSR1025_SHIFT (25u)
+#define GPIO_PMSR10_PMSR1026_SHIFT (26u)
+#define GPIO_PMSR10_PMSR1027_SHIFT (27u)
+#define GPIO_PMSR10_PMSR1028_SHIFT (28u)
+#define GPIO_PMSR10_PMSR1029_SHIFT (29u)
+#define GPIO_PMSR10_PMSR1030_SHIFT (30u)
+#define GPIO_PMSR10_PMSR1031_SHIFT (31u)
+
+#define GPIO_PMCSR10_PMCSR100_SHIFT (0u)
+#define GPIO_PMCSR10_PMCSR101_SHIFT (1u)
+#define GPIO_PMCSR10_PMCSR102_SHIFT (2u)
+#define GPIO_PMCSR10_PMCSR103_SHIFT (3u)
+#define GPIO_PMCSR10_PMCSR104_SHIFT (4u)
+#define GPIO_PMCSR10_PMCSR105_SHIFT (5u)
+#define GPIO_PMCSR10_PMCSR106_SHIFT (6u)
+#define GPIO_PMCSR10_PMCSR107_SHIFT (7u)
+#define GPIO_PMCSR10_PMCSR108_SHIFT (8u)
+#define GPIO_PMCSR10_PMCSR109_SHIFT (9u)
+#define GPIO_PMCSR10_PMCSR1010_SHIFT (10u)
+#define GPIO_PMCSR10_PMCSR1011_SHIFT (11u)
+#define GPIO_PMCSR10_PMCSR1012_SHIFT (12u)
+#define GPIO_PMCSR10_PMCSR1013_SHIFT (13u)
+#define GPIO_PMCSR10_PMCSR1014_SHIFT (14u)
+#define GPIO_PMCSR10_PMCSR1015_SHIFT (15u)
+#define GPIO_PMCSR10_PMCSR1016_SHIFT (16u)
+#define GPIO_PMCSR10_PMCSR1017_SHIFT (17u)
+#define GPIO_PMCSR10_PMCSR1018_SHIFT (18u)
+#define GPIO_PMCSR10_PMCSR1019_SHIFT (19u)
+#define GPIO_PMCSR10_PMCSR1020_SHIFT (20u)
+#define GPIO_PMCSR10_PMCSR1021_SHIFT (21u)
+#define GPIO_PMCSR10_PMCSR1022_SHIFT (22u)
+#define GPIO_PMCSR10_PMCSR1023_SHIFT (23u)
+#define GPIO_PMCSR10_PMCSR1024_SHIFT (24u)
+#define GPIO_PMCSR10_PMCSR1025_SHIFT (25u)
+#define GPIO_PMCSR10_PMCSR1026_SHIFT (26u)
+#define GPIO_PMCSR10_PMCSR1027_SHIFT (27u)
+#define GPIO_PMCSR10_PMCSR1028_SHIFT (28u)
+#define GPIO_PMCSR10_PMCSR1029_SHIFT (29u)
+#define GPIO_PMCSR10_PMCSR1030_SHIFT (30u)
+#define GPIO_PMCSR10_PMCSR1031_SHIFT (31u)
+
+#define GPIO_PFCAE10_PFCAE100_SHIFT (0u)
+#define GPIO_PFCAE10_PFCAE101_SHIFT (1u)
+#define GPIO_PFCAE10_PFCAE102_SHIFT (2u)
+#define GPIO_PFCAE10_PFCAE103_SHIFT (3u)
+#define GPIO_PFCAE10_PFCAE104_SHIFT (4u)
+#define GPIO_PFCAE10_PFCAE105_SHIFT (5u)
+#define GPIO_PFCAE10_PFCAE106_SHIFT (6u)
+#define GPIO_PFCAE10_PFCAE107_SHIFT (7u)
+#define GPIO_PFCAE10_PFCAE108_SHIFT (8u)
+#define GPIO_PFCAE10_PFCAE109_SHIFT (9u)
+#define GPIO_PFCAE10_PFCAE1010_SHIFT (10u)
+#define GPIO_PFCAE10_PFCAE1011_SHIFT (11u)
+#define GPIO_PFCAE10_PFCAE1012_SHIFT (12u)
+#define GPIO_PFCAE10_PFCAE1013_SHIFT (13u)
+#define GPIO_PFCAE10_PFCAE1014_SHIFT (14u)
+#define GPIO_PFCAE10_PFCAE1015_SHIFT (15u)
+
+#define GPIO_PIBC10_PIBC100_SHIFT (0u)
+#define GPIO_PIBC10_PIBC101_SHIFT (1u)
+#define GPIO_PIBC10_PIBC102_SHIFT (2u)
+#define GPIO_PIBC10_PIBC103_SHIFT (3u)
+#define GPIO_PIBC10_PIBC104_SHIFT (4u)
+#define GPIO_PIBC10_PIBC105_SHIFT (5u)
+#define GPIO_PIBC10_PIBC106_SHIFT (6u)
+#define GPIO_PIBC10_PIBC107_SHIFT (7u)
+#define GPIO_PIBC10_PIBC108_SHIFT (8u)
+#define GPIO_PIBC10_PIBC109_SHIFT (9u)
+#define GPIO_PIBC10_PIBC1010_SHIFT (10u)
+#define GPIO_PIBC10_PIBC1011_SHIFT (11u)
+#define GPIO_PIBC10_PIBC1012_SHIFT (12u)
+#define GPIO_PIBC10_PIBC1013_SHIFT (13u)
+#define GPIO_PIBC10_PIBC1014_SHIFT (14u)
+#define GPIO_PIBC10_PIBC1015_SHIFT (15u)
+
+#define GPIO_PBDC10_PBDC100_SHIFT (0u)
+#define GPIO_PBDC10_PBDC101_SHIFT (1u)
+#define GPIO_PBDC10_PBDC102_SHIFT (2u)
+#define GPIO_PBDC10_PBDC103_SHIFT (3u)
+#define GPIO_PBDC10_PBDC104_SHIFT (4u)
+#define GPIO_PBDC10_PBDC105_SHIFT (5u)
+#define GPIO_PBDC10_PBDC106_SHIFT (6u)
+#define GPIO_PBDC10_PBDC107_SHIFT (7u)
+#define GPIO_PBDC10_PBDC108_SHIFT (8u)
+#define GPIO_PBDC10_PBDC109_SHIFT (9u)
+#define GPIO_PBDC10_PBDC1010_SHIFT (10u)
+#define GPIO_PBDC10_PBDC1011_SHIFT (11u)
+#define GPIO_PBDC10_PBDC1012_SHIFT (12u)
+#define GPIO_PBDC10_PBDC1013_SHIFT (13u)
+#define GPIO_PBDC10_PBDC1014_SHIFT (14u)
+#define GPIO_PBDC10_PBDC1015_SHIFT (15u)
+
+#define GPIO_PIPC10_PIPC100_SHIFT (0u)
+#define GPIO_PIPC10_PIPC101_SHIFT (1u)
+#define GPIO_PIPC10_PIPC102_SHIFT (2u)
+#define GPIO_PIPC10_PIPC103_SHIFT (3u)
+#define GPIO_PIPC10_PIPC104_SHIFT (4u)
+#define GPIO_PIPC10_PIPC105_SHIFT (5u)
+#define GPIO_PIPC10_PIPC106_SHIFT (6u)
+#define GPIO_PIPC10_PIPC107_SHIFT (7u)
+#define GPIO_PIPC10_PIPC108_SHIFT (8u)
+#define GPIO_PIPC10_PIPC109_SHIFT (9u)
+#define GPIO_PIPC10_PIPC1010_SHIFT (10u)
+#define GPIO_PIPC10_PIPC1011_SHIFT (11u)
+#define GPIO_PIPC10_PIPC1012_SHIFT (12u)
+#define GPIO_PIPC10_PIPC1013_SHIFT (13u)
+#define GPIO_PIPC10_PIPC1014_SHIFT (14u)
+#define GPIO_PIPC10_PIPC1015_SHIFT (15u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110_SHIFT (0u)
+#define GPIO_P11_P111_SHIFT (1u)
+#define GPIO_P11_P112_SHIFT (2u)
+#define GPIO_P11_P113_SHIFT (3u)
+#define GPIO_P11_P114_SHIFT (4u)
+#define GPIO_P11_P115_SHIFT (5u)
+#define GPIO_P11_P116_SHIFT (6u)
+#define GPIO_P11_P117_SHIFT (7u)
+#define GPIO_P11_P118_SHIFT (8u)
+#define GPIO_P11_P119_SHIFT (9u)
+#define GPIO_P11_P1110_SHIFT (10u)
+#define GPIO_P11_P1111_SHIFT (11u)
+#define GPIO_P11_P1112_SHIFT (12u)
+#define GPIO_P11_P1113_SHIFT (13u)
+#define GPIO_P11_P1114_SHIFT (14u)
+#define GPIO_P11_P1115_SHIFT (15u)
+
+#define GPIO_PSR11_PSR110_SHIFT (0u)
+#define GPIO_PSR11_PSR111_SHIFT (1u)
+#define GPIO_PSR11_PSR112_SHIFT (2u)
+#define GPIO_PSR11_PSR113_SHIFT (3u)
+#define GPIO_PSR11_PSR114_SHIFT (4u)
+#define GPIO_PSR11_PSR115_SHIFT (5u)
+#define GPIO_PSR11_PSR116_SHIFT (6u)
+#define GPIO_PSR11_PSR117_SHIFT (7u)
+#define GPIO_PSR11_PSR118_SHIFT (8u)
+#define GPIO_PSR11_PSR119_SHIFT (9u)
+#define GPIO_PSR11_PSR1110_SHIFT (10u)
+#define GPIO_PSR11_PSR1111_SHIFT (11u)
+#define GPIO_PSR11_PSR1112_SHIFT (12u)
+#define GPIO_PSR11_PSR1113_SHIFT (13u)
+#define GPIO_PSR11_PSR1114_SHIFT (14u)
+#define GPIO_PSR11_PSR1115_SHIFT (15u)
+#define GPIO_PSR11_PSR1116_SHIFT (16u)
+#define GPIO_PSR11_PSR1117_SHIFT (17u)
+#define GPIO_PSR11_PSR1118_SHIFT (18u)
+#define GPIO_PSR11_PSR1119_SHIFT (19u)
+#define GPIO_PSR11_PSR1120_SHIFT (20u)
+#define GPIO_PSR11_PSR1121_SHIFT (21u)
+#define GPIO_PSR11_PSR1122_SHIFT (22u)
+#define GPIO_PSR11_PSR1123_SHIFT (23u)
+#define GPIO_PSR11_PSR1124_SHIFT (24u)
+#define GPIO_PSR11_PSR1125_SHIFT (25u)
+#define GPIO_PSR11_PSR1126_SHIFT (26u)
+#define GPIO_PSR11_PSR1127_SHIFT (27u)
+#define GPIO_PSR11_PSR1128_SHIFT (28u)
+#define GPIO_PSR11_PSR1129_SHIFT (29u)
+#define GPIO_PSR11_PSR1130_SHIFT (30u)
+#define GPIO_PSR11_PSR1131_SHIFT (31u)
+
+#define GPIO_PPR11_PPR110_SHIFT (0u)
+#define GPIO_PPR11_PPR111_SHIFT (1u)
+#define GPIO_PPR11_PPR112_SHIFT (2u)
+#define GPIO_PPR11_PPR113_SHIFT (3u)
+#define GPIO_PPR11_PPR114_SHIFT (4u)
+#define GPIO_PPR11_PPR115_SHIFT (5u)
+#define GPIO_PPR11_PPR116_SHIFT (6u)
+#define GPIO_PPR11_PPR117_SHIFT (7u)
+#define GPIO_PPR11_PPR118_SHIFT (8u)
+#define GPIO_PPR11_PPR119_SHIFT (9u)
+#define GPIO_PPR11_PPR1110_SHIFT (10u)
+#define GPIO_PPR11_PPR1111_SHIFT (11u)
+#define GPIO_PPR11_PPR1112_SHIFT (12u)
+#define GPIO_PPR11_PPR1113_SHIFT (13u)
+#define GPIO_PPR11_PPR1114_SHIFT (14u)
+#define GPIO_PPR11_PPR1115_SHIFT (15u)
+
+#define GPIO_PM11_PM110_SHIFT (0u)
+#define GPIO_PM11_PM111_SHIFT (1u)
+#define GPIO_PM11_PM112_SHIFT (2u)
+#define GPIO_PM11_PM113_SHIFT (3u)
+#define GPIO_PM11_PM114_SHIFT (4u)
+#define GPIO_PM11_PM115_SHIFT (5u)
+#define GPIO_PM11_PM116_SHIFT (6u)
+#define GPIO_PM11_PM117_SHIFT (7u)
+#define GPIO_PM11_PM118_SHIFT (8u)
+#define GPIO_PM11_PM119_SHIFT (9u)
+#define GPIO_PM11_PM1110_SHIFT (10u)
+#define GPIO_PM11_PM1111_SHIFT (11u)
+#define GPIO_PM11_PM1112_SHIFT (12u)
+#define GPIO_PM11_PM1113_SHIFT (13u)
+#define GPIO_PM11_PM1114_SHIFT (14u)
+#define GPIO_PM11_PM1115_SHIFT (15u)
+
+#define GPIO_PMC11_PMC110_SHIFT (0u)
+#define GPIO_PMC11_PMC111_SHIFT (1u)
+#define GPIO_PMC11_PMC112_SHIFT (2u)
+#define GPIO_PMC11_PMC113_SHIFT (3u)
+#define GPIO_PMC11_PMC114_SHIFT (4u)
+#define GPIO_PMC11_PMC115_SHIFT (5u)
+#define GPIO_PMC11_PMC116_SHIFT (6u)
+#define GPIO_PMC11_PMC117_SHIFT (7u)
+#define GPIO_PMC11_PMC118_SHIFT (8u)
+#define GPIO_PMC11_PMC119_SHIFT (9u)
+#define GPIO_PMC11_PMC1110_SHIFT (10u)
+#define GPIO_PMC11_PMC1111_SHIFT (11u)
+#define GPIO_PMC11_PMC1112_SHIFT (12u)
+#define GPIO_PMC11_PMC1113_SHIFT (13u)
+#define GPIO_PMC11_PMC1114_SHIFT (14u)
+#define GPIO_PMC11_PMC1115_SHIFT (15u)
+
+#define GPIO_PFC11_PFC110_SHIFT (0u)
+#define GPIO_PFC11_PFC111_SHIFT (1u)
+#define GPIO_PFC11_PFC112_SHIFT (2u)
+#define GPIO_PFC11_PFC113_SHIFT (3u)
+#define GPIO_PFC11_PFC114_SHIFT (4u)
+#define GPIO_PFC11_PFC115_SHIFT (5u)
+#define GPIO_PFC11_PFC116_SHIFT (6u)
+#define GPIO_PFC11_PFC117_SHIFT (7u)
+#define GPIO_PFC11_PFC118_SHIFT (8u)
+#define GPIO_PFC11_PFC119_SHIFT (9u)
+#define GPIO_PFC11_PFC1110_SHIFT (10u)
+#define GPIO_PFC11_PFC1111_SHIFT (11u)
+#define GPIO_PFC11_PFC1112_SHIFT (12u)
+#define GPIO_PFC11_PFC1113_SHIFT (13u)
+#define GPIO_PFC11_PFC1114_SHIFT (14u)
+#define GPIO_PFC11_PFC1115_SHIFT (15u)
+
+#define GPIO_PFCE11_PFCE110_SHIFT (0u)
+#define GPIO_PFCE11_PFCE111_SHIFT (1u)
+#define GPIO_PFCE11_PFCE112_SHIFT (2u)
+#define GPIO_PFCE11_PFCE113_SHIFT (3u)
+#define GPIO_PFCE11_PFCE114_SHIFT (4u)
+#define GPIO_PFCE11_PFCE115_SHIFT (5u)
+#define GPIO_PFCE11_PFCE116_SHIFT (6u)
+#define GPIO_PFCE11_PFCE117_SHIFT (7u)
+#define GPIO_PFCE11_PFCE118_SHIFT (8u)
+#define GPIO_PFCE11_PFCE119_SHIFT (9u)
+#define GPIO_PFCE11_PFCE1110_SHIFT (10u)
+#define GPIO_PFCE11_PFCE1111_SHIFT (11u)
+#define GPIO_PFCE11_PFCE1112_SHIFT (12u)
+#define GPIO_PFCE11_PFCE1113_SHIFT (13u)
+#define GPIO_PFCE11_PFCE1114_SHIFT (14u)
+#define GPIO_PFCE11_PFCE1115_SHIFT (15u)
+
+#define GPIO_PNOT11_PNOT110_SHIFT (0u)
+#define GPIO_PNOT11_PNOT111_SHIFT (1u)
+#define GPIO_PNOT11_PNOT112_SHIFT (2u)
+#define GPIO_PNOT11_PNOT113_SHIFT (3u)
+#define GPIO_PNOT11_PNOT114_SHIFT (4u)
+#define GPIO_PNOT11_PNOT115_SHIFT (5u)
+#define GPIO_PNOT11_PNOT116_SHIFT (6u)
+#define GPIO_PNOT11_PNOT117_SHIFT (7u)
+#define GPIO_PNOT11_PNOT118_SHIFT (8u)
+#define GPIO_PNOT11_PNOT119_SHIFT (9u)
+#define GPIO_PNOT11_PNOT1110_SHIFT (10u)
+#define GPIO_PNOT11_PNOT1111_SHIFT (11u)
+#define GPIO_PNOT11_PNOT1112_SHIFT (12u)
+#define GPIO_PNOT11_PNOT1113_SHIFT (13u)
+#define GPIO_PNOT11_PNOT1114_SHIFT (14u)
+#define GPIO_PNOT11_PNOT1115_SHIFT (15u)
+
+#define GPIO_PMSR11_PMSR110_SHIFT (0u)
+#define GPIO_PMSR11_PMSR111_SHIFT (1u)
+#define GPIO_PMSR11_PMSR112_SHIFT (2u)
+#define GPIO_PMSR11_PMSR113_SHIFT (3u)
+#define GPIO_PMSR11_PMSR114_SHIFT (4u)
+#define GPIO_PMSR11_PMSR115_SHIFT (5u)
+#define GPIO_PMSR11_PMSR116_SHIFT (6u)
+#define GPIO_PMSR11_PMSR117_SHIFT (7u)
+#define GPIO_PMSR11_PMSR118_SHIFT (8u)
+#define GPIO_PMSR11_PMSR119_SHIFT (9u)
+#define GPIO_PMSR11_PMSR1110_SHIFT (10u)
+#define GPIO_PMSR11_PMSR1111_SHIFT (11u)
+#define GPIO_PMSR11_PMSR1112_SHIFT (12u)
+#define GPIO_PMSR11_PMSR1113_SHIFT (13u)
+#define GPIO_PMSR11_PMSR1114_SHIFT (14u)
+#define GPIO_PMSR11_PMSR1115_SHIFT (15u)
+#define GPIO_PMSR11_PMSR1116_SHIFT (16u)
+#define GPIO_PMSR11_PMSR1117_SHIFT (17u)
+#define GPIO_PMSR11_PMSR1118_SHIFT (18u)
+#define GPIO_PMSR11_PMSR1119_SHIFT (19u)
+#define GPIO_PMSR11_PMSR1120_SHIFT (20u)
+#define GPIO_PMSR11_PMSR1121_SHIFT (21u)
+#define GPIO_PMSR11_PMSR1122_SHIFT (22u)
+#define GPIO_PMSR11_PMSR1123_SHIFT (23u)
+#define GPIO_PMSR11_PMSR1124_SHIFT (24u)
+#define GPIO_PMSR11_PMSR1125_SHIFT (25u)
+#define GPIO_PMSR11_PMSR1126_SHIFT (26u)
+#define GPIO_PMSR11_PMSR1127_SHIFT (27u)
+#define GPIO_PMSR11_PMSR1128_SHIFT (28u)
+#define GPIO_PMSR11_PMSR1129_SHIFT (29u)
+#define GPIO_PMSR11_PMSR1130_SHIFT (30u)
+#define GPIO_PMSR11_PMSR1131_SHIFT (31u)
+
+#define GPIO_PMCSR11_PMCSR110_SHIFT (0u)
+#define GPIO_PMCSR11_PMCSR111_SHIFT (1u)
+#define GPIO_PMCSR11_PMCSR112_SHIFT (2u)
+#define GPIO_PMCSR11_PMCSR113_SHIFT (3u)
+#define GPIO_PMCSR11_PMCSR114_SHIFT (4u)
+#define GPIO_PMCSR11_PMCSR115_SHIFT (5u)
+#define GPIO_PMCSR11_PMCSR116_SHIFT (6u)
+#define GPIO_PMCSR11_PMCSR117_SHIFT (7u)
+#define GPIO_PMCSR11_PMCSR118_SHIFT (8u)
+#define GPIO_PMCSR11_PMCSR119_SHIFT (9u)
+#define GPIO_PMCSR11_PMCSR1110_SHIFT (10u)
+#define GPIO_PMCSR11_PMCSR1111_SHIFT (11u)
+#define GPIO_PMCSR11_PMCSR1112_SHIFT (12u)
+#define GPIO_PMCSR11_PMCSR1113_SHIFT (13u)
+#define GPIO_PMCSR11_PMCSR1114_SHIFT (14u)
+#define GPIO_PMCSR11_PMCSR1115_SHIFT (15u)
+#define GPIO_PMCSR11_PMCSR1116_SHIFT (16u)
+#define GPIO_PMCSR11_PMCSR1117_SHIFT (17u)
+#define GPIO_PMCSR11_PMCSR1118_SHIFT (18u)
+#define GPIO_PMCSR11_PMCSR1119_SHIFT (19u)
+#define GPIO_PMCSR11_PMCSR1120_SHIFT (20u)
+#define GPIO_PMCSR11_PMCSR1121_SHIFT (21u)
+#define GPIO_PMCSR11_PMCSR1122_SHIFT (22u)
+#define GPIO_PMCSR11_PMCSR1123_SHIFT (23u)
+#define GPIO_PMCSR11_PMCSR1124_SHIFT (24u)
+#define GPIO_PMCSR11_PMCSR1125_SHIFT (25u)
+#define GPIO_PMCSR11_PMCSR1126_SHIFT (26u)
+#define GPIO_PMCSR11_PMCSR1127_SHIFT (27u)
+#define GPIO_PMCSR11_PMCSR1128_SHIFT (28u)
+#define GPIO_PMCSR11_PMCSR1129_SHIFT (29u)
+#define GPIO_PMCSR11_PMCSR1130_SHIFT (30u)
+#define GPIO_PMCSR11_PMCSR1131_SHIFT (31u)
+
+#define GPIO_PFCAE11_PFCAE110_SHIFT (0u)
+#define GPIO_PFCAE11_PFCAE111_SHIFT (1u)
+#define GPIO_PFCAE11_PFCAE112_SHIFT (2u)
+#define GPIO_PFCAE11_PFCAE113_SHIFT (3u)
+#define GPIO_PFCAE11_PFCAE114_SHIFT (4u)
+#define GPIO_PFCAE11_PFCAE115_SHIFT (5u)
+#define GPIO_PFCAE11_PFCAE116_SHIFT (6u)
+#define GPIO_PFCAE11_PFCAE117_SHIFT (7u)
+#define GPIO_PFCAE11_PFCAE118_SHIFT (8u)
+#define GPIO_PFCAE11_PFCAE119_SHIFT (9u)
+#define GPIO_PFCAE11_PFCAE1110_SHIFT (10u)
+#define GPIO_PFCAE11_PFCAE1111_SHIFT (11u)
+#define GPIO_PFCAE11_PFCAE1112_SHIFT (12u)
+#define GPIO_PFCAE11_PFCAE1113_SHIFT (13u)
+#define GPIO_PFCAE11_PFCAE1114_SHIFT (14u)
+#define GPIO_PFCAE11_PFCAE1115_SHIFT (15u)
+
+#define GPIO_PIBC11_PIBC110_SHIFT (0u)
+#define GPIO_PIBC11_PIBC111_SHIFT (1u)
+#define GPIO_PIBC11_PIBC112_SHIFT (2u)
+#define GPIO_PIBC11_PIBC113_SHIFT (3u)
+#define GPIO_PIBC11_PIBC114_SHIFT (4u)
+#define GPIO_PIBC11_PIBC115_SHIFT (5u)
+#define GPIO_PIBC11_PIBC116_SHIFT (6u)
+#define GPIO_PIBC11_PIBC117_SHIFT (7u)
+#define GPIO_PIBC11_PIBC118_SHIFT (8u)
+#define GPIO_PIBC11_PIBC119_SHIFT (9u)
+#define GPIO_PIBC11_PIBC1110_SHIFT (10u)
+#define GPIO_PIBC11_PIBC1111_SHIFT (11u)
+#define GPIO_PIBC11_PIBC1112_SHIFT (12u)
+#define GPIO_PIBC11_PIBC1113_SHIFT (13u)
+#define GPIO_PIBC11_PIBC1114_SHIFT (14u)
+#define GPIO_PIBC11_PIBC1115_SHIFT (15u)
+
+#define GPIO_PBDC11_PBDC110_SHIFT (0u)
+#define GPIO_PBDC11_PBDC111_SHIFT (1u)
+#define GPIO_PBDC11_PBDC112_SHIFT (2u)
+#define GPIO_PBDC11_PBDC113_SHIFT (3u)
+#define GPIO_PBDC11_PBDC114_SHIFT (4u)
+#define GPIO_PBDC11_PBDC115_SHIFT (5u)
+#define GPIO_PBDC11_PBDC116_SHIFT (6u)
+#define GPIO_PBDC11_PBDC117_SHIFT (7u)
+#define GPIO_PBDC11_PBDC118_SHIFT (8u)
+#define GPIO_PBDC11_PBDC119_SHIFT (9u)
+#define GPIO_PBDC11_PBDC1110_SHIFT (10u)
+#define GPIO_PBDC11_PBDC1111_SHIFT (11u)
+#define GPIO_PBDC11_PBDC1112_SHIFT (12u)
+#define GPIO_PBDC11_PBDC1113_SHIFT (13u)
+#define GPIO_PBDC11_PBDC1114_SHIFT (14u)
+#define GPIO_PBDC11_PBDC1115_SHIFT (15u)
+
+#define GPIO_PIPC11_PIPC110_SHIFT (0u)
+#define GPIO_PIPC11_PIPC111_SHIFT (1u)
+#define GPIO_PIPC11_PIPC112_SHIFT (2u)
+#define GPIO_PIPC11_PIPC113_SHIFT (3u)
+#define GPIO_PIPC11_PIPC114_SHIFT (4u)
+#define GPIO_PIPC11_PIPC115_SHIFT (5u)
+#define GPIO_PIPC11_PIPC116_SHIFT (6u)
+#define GPIO_PIPC11_PIPC117_SHIFT (7u)
+#define GPIO_PIPC11_PIPC118_SHIFT (8u)
+#define GPIO_PIPC11_PIPC119_SHIFT (9u)
+#define GPIO_PIPC11_PIPC1110_SHIFT (10u)
+#define GPIO_PIPC11_PIPC1111_SHIFT (11u)
+#define GPIO_PIPC11_PIPC1112_SHIFT (12u)
+#define GPIO_PIPC11_PIPC1113_SHIFT (13u)
+#define GPIO_PIPC11_PIPC1114_SHIFT (14u)
+#define GPIO_PIPC11_PIPC1115_SHIFT (15u)
+
+
+#endif /* GPIO_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/intc_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/intc_iobitmask.h
new file mode 100644
index 000000000..e1b95cb26
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/intc_iobitmask.h
@@ -0,0 +1,11236 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : INTC register define header
+*******************************************************************************/
+#ifndef INTC_IOBITMASK_H
+#define INTC_IOBITMASK_H
+
+/* ==== Mask values for IO registers ==== */
+#define INTC_ICDDCR_Enable (0x00000001uL)
+
+#define INTC_ICDICTR_ITLinesNumber (0x0000001FuL)
+#define INTC_ICDICTR_CPUNumber (0x000000E0uL)
+#define INTC_ICDICTR_SecurityExtn (0x00000400uL)
+#define INTC_ICDICTR_LSPI (0x0000F800uL)
+
+#define INTC_ICDIIDR_Implementer (0x00000FFFuL)
+#define INTC_ICDIIDR_Revision (0x0000F000uL)
+#define INTC_ICDIIDR_Variant (0x000F0000uL)
+#define INTC_ICDIIDR_ProductID (0xFF000000uL)
+
+#define INTC_ICDISR0_SW0 (0x00000001uL)
+#define INTC_ICDISR0_SW1 (0x00000002uL)
+#define INTC_ICDISR0_SW2 (0x00000004uL)
+#define INTC_ICDISR0_SW3 (0x00000008uL)
+#define INTC_ICDISR0_SW4 (0x00000010uL)
+#define INTC_ICDISR0_SW5 (0x00000020uL)
+#define INTC_ICDISR0_SW6 (0x00000040uL)
+#define INTC_ICDISR0_SW7 (0x00000080uL)
+#define INTC_ICDISR0_SW8 (0x00000100uL)
+#define INTC_ICDISR0_SW9 (0x00000200uL)
+#define INTC_ICDISR0_SW10 (0x00000400uL)
+#define INTC_ICDISR0_SW11 (0x00000800uL)
+#define INTC_ICDISR0_SW12 (0x00001000uL)
+#define INTC_ICDISR0_SW13 (0x00002000uL)
+#define INTC_ICDISR0_SW14 (0x00004000uL)
+#define INTC_ICDISR0_SW15 (0x00008000uL)
+#define INTC_ICDISR0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDISR0_COMMRX0 (0x00020000uL)
+#define INTC_ICDISR0_COMMTX0 (0x00040000uL)
+#define INTC_ICDISR0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDISR1_IRQ0 (0x00000001uL)
+#define INTC_ICDISR1_IRQ1 (0x00000002uL)
+#define INTC_ICDISR1_IRQ2 (0x00000004uL)
+#define INTC_ICDISR1_IRQ3 (0x00000008uL)
+#define INTC_ICDISR1_IRQ4 (0x00000010uL)
+#define INTC_ICDISR1_IRQ5 (0x00000020uL)
+#define INTC_ICDISR1_IRQ6 (0x00000040uL)
+#define INTC_ICDISR1_IRQ7 (0x00000080uL)
+#define INTC_ICDISR1_PL310ERR (0x00000100uL)
+#define INTC_ICDISR1_DMAINT0 (0x00000200uL)
+#define INTC_ICDISR1_DMAINT1 (0x00000400uL)
+#define INTC_ICDISR1_DMAINT2 (0x00000800uL)
+#define INTC_ICDISR1_DMAINT3 (0x00001000uL)
+#define INTC_ICDISR1_DMAINT4 (0x00002000uL)
+#define INTC_ICDISR1_DMAINT5 (0x00004000uL)
+#define INTC_ICDISR1_DMAINT6 (0x00008000uL)
+#define INTC_ICDISR1_DMAINT7 (0x00010000uL)
+#define INTC_ICDISR1_DMAINT8 (0x00020000uL)
+#define INTC_ICDISR1_DMAINT9 (0x00040000uL)
+#define INTC_ICDISR1_DMAINT10 (0x00080000uL)
+#define INTC_ICDISR1_DMAINT11 (0x00100000uL)
+#define INTC_ICDISR1_DMAINT12 (0x00200000uL)
+#define INTC_ICDISR1_DMAINT13 (0x00400000uL)
+#define INTC_ICDISR1_DMAINT14 (0x00800000uL)
+#define INTC_ICDISR1_DMAINT15 (0x01000000uL)
+#define INTC_ICDISR1_DMAERR (0x02000000uL)
+
+#define INTC_ICDISR2_USBI0 (0x00000200uL)
+#define INTC_ICDISR2_USBI1 (0x00000400uL)
+#define INTC_ICDISR2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDISR2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDISR2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDISR2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDISR2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDISR2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDISR2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDISR2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDISR2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDISR2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDISR2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDISR2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDISR2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDISR2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDISR2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDISR2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDISR2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDISR2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDISR2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDISR2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDISR2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDISR3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDISR3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDISR3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDISR3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDISR3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDISR3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDISR3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDISR3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDISR3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDISR3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDISR3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDISR3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDISR3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDISR3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDISR3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDISR3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDISR3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDISR3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDISR3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDISR3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDISR3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDISR3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDISR3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDISR3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDISR3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDISR3_IMRDI (0x08000000uL)
+#define INTC_ICDISR3_IMR2I0 (0x10000000uL)
+#define INTC_ICDISR3_IMR2I1 (0x20000000uL)
+#define INTC_ICDISR3_JEDI (0x40000000uL)
+#define INTC_ICDISR3_JDTI (0x80000000uL)
+
+#define INTC_ICDISR4_CMP0 (0x00000001uL)
+#define INTC_ICDISR4_CMP1 (0x00000002uL)
+#define INTC_ICDISR4_INT0 (0x00000004uL)
+#define INTC_ICDISR4_INT1 (0x00000008uL)
+#define INTC_ICDISR4_INT2 (0x00000010uL)
+#define INTC_ICDISR4_INT3 (0x00000020uL)
+#define INTC_ICDISR4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDISR4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDISR4_CMI (0x00000100uL)
+#define INTC_ICDISR4_WTOUT (0x00000200uL)
+#define INTC_ICDISR4_ITI (0x00000400uL)
+#define INTC_ICDISR4_TGI0A (0x00000800uL)
+#define INTC_ICDISR4_TGI0B (0x00001000uL)
+#define INTC_ICDISR4_TGI0C (0x00002000uL)
+#define INTC_ICDISR4_TGI0D (0x00004000uL)
+#define INTC_ICDISR4_TGI0V (0x00008000uL)
+#define INTC_ICDISR4_TGI0E (0x00010000uL)
+#define INTC_ICDISR4_TGI0F (0x00020000uL)
+#define INTC_ICDISR4_TGI1A (0x00040000uL)
+#define INTC_ICDISR4_TGI1B (0x00080000uL)
+#define INTC_ICDISR4_TGI1V (0x00100000uL)
+#define INTC_ICDISR4_TGI1U (0x00200000uL)
+#define INTC_ICDISR4_TGI2A (0x00400000uL)
+#define INTC_ICDISR4_TGI2B (0x00800000uL)
+#define INTC_ICDISR4_TGI2V (0x01000000uL)
+#define INTC_ICDISR4_TGI2U (0x02000000uL)
+#define INTC_ICDISR4_TGI3A (0x04000000uL)
+#define INTC_ICDISR4_TGI3B (0x08000000uL)
+#define INTC_ICDISR4_TGI3C (0x10000000uL)
+#define INTC_ICDISR4_TGI3D (0x20000000uL)
+#define INTC_ICDISR4_TGI3V (0x40000000uL)
+#define INTC_ICDISR4_TGI4A (0x80000000uL)
+
+#define INTC_ICDISR5_TGI4B (0x00000001uL)
+#define INTC_ICDISR5_TGI4C (0x00000002uL)
+#define INTC_ICDISR5_TGI4D (0x00000004uL)
+#define INTC_ICDISR5_TGI4V (0x00000008uL)
+#define INTC_ICDISR5_CMI1 (0x00000010uL)
+#define INTC_ICDISR5_CMI2 (0x00000020uL)
+#define INTC_ICDISR5_SGDEI0 (0x00000040uL)
+#define INTC_ICDISR5_SGDEI1 (0x00000080uL)
+#define INTC_ICDISR5_SGDEI2 (0x00000100uL)
+#define INTC_ICDISR5_SGDEI3 (0x00000200uL)
+#define INTC_ICDISR5_ADI (0x00000400uL)
+#define INTC_ICDISR5_LMTI (0x00000800uL)
+#define INTC_ICDISR5_SSII0 (0x00001000uL)
+#define INTC_ICDISR5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDISR5_SSITXI0 (0x00004000uL)
+#define INTC_ICDISR5_SSII1 (0x00008000uL)
+#define INTC_ICDISR5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDISR5_SSITXI1 (0x00020000uL)
+#define INTC_ICDISR5_SSII2 (0x00040000uL)
+#define INTC_ICDISR5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDISR5_SSII3 (0x00100000uL)
+#define INTC_ICDISR5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDISR5_SSITXI3 (0x00400000uL)
+#define INTC_ICDISR5_SSII4 (0x00800000uL)
+#define INTC_ICDISR5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDISR5_SSII5 (0x02000000uL)
+#define INTC_ICDISR5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDISR5_SSITXI5 (0x08000000uL)
+#define INTC_ICDISR5_SPDIFI (0x10000000uL)
+#define INTC_ICDISR5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDISR5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDISR5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDISR6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDISR6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDISR6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDISR6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDISR6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDISR6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDISR6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDISR6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDISR6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDISR6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDISR6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDISR6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDISR6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDISR6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDISR6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDISR6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDISR6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDISR6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDISR6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDISR6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDISR6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDISR6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDISR6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDISR6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDISR6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDISR6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDISR6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDISR6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDISR6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDISR6_BRI0 (0x20000000uL)
+#define INTC_ICDISR6_ERI0 (0x40000000uL)
+#define INTC_ICDISR6_RXI0 (0x80000000uL)
+
+#define INTC_ICDISR7_TXI0 (0x00000001uL)
+#define INTC_ICDISR7_BRI1 (0x00000002uL)
+#define INTC_ICDISR7_ERI1 (0x00000004uL)
+#define INTC_ICDISR7_RXI1 (0x00000008uL)
+#define INTC_ICDISR7_TXI1 (0x00000010uL)
+#define INTC_ICDISR7_BRI2 (0x00000020uL)
+#define INTC_ICDISR7_ERI2 (0x00000040uL)
+#define INTC_ICDISR7_RXI2 (0x00000080uL)
+#define INTC_ICDISR7_TXI2 (0x00000100uL)
+#define INTC_ICDISR7_BRI3 (0x00000200uL)
+#define INTC_ICDISR7_ERI3 (0x00000400uL)
+#define INTC_ICDISR7_RXI3 (0x00000800uL)
+#define INTC_ICDISR7_TXI3 (0x00001000uL)
+#define INTC_ICDISR7_BRI4 (0x00002000uL)
+#define INTC_ICDISR7_ERI4 (0x00004000uL)
+#define INTC_ICDISR7_RXI4 (0x00008000uL)
+#define INTC_ICDISR7_TXI4 (0x00010000uL)
+#define INTC_ICDISR7_BRI5 (0x00020000uL)
+#define INTC_ICDISR7_ERI5 (0x00040000uL)
+#define INTC_ICDISR7_RXI5 (0x00080000uL)
+#define INTC_ICDISR7_TXI5 (0x00100000uL)
+#define INTC_ICDISR7_BRI6 (0x00200000uL)
+#define INTC_ICDISR7_ERI6 (0x00400000uL)
+#define INTC_ICDISR7_RXI6 (0x00800000uL)
+#define INTC_ICDISR7_TXI6 (0x01000000uL)
+#define INTC_ICDISR7_BRI7 (0x02000000uL)
+#define INTC_ICDISR7_ERI7 (0x04000000uL)
+#define INTC_ICDISR7_RXI7 (0x08000000uL)
+#define INTC_ICDISR7_TXI7 (0x10000000uL)
+#define INTC_ICDISR7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDISR7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDISR7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDISR8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDISR8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDISR8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDISR8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDISR8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDISR8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDISR8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDISR8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDISR8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDISR8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDISR8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDISR8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDISR8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDISR8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDISR8_SPEI0 (0x00004000uL)
+#define INTC_ICDISR8_SPRI0 (0x00008000uL)
+#define INTC_ICDISR8_SPTI0 (0x00010000uL)
+#define INTC_ICDISR8_SPEI1 (0x00020000uL)
+#define INTC_ICDISR8_SPRI1 (0x00040000uL)
+#define INTC_ICDISR8_SPTI1 (0x00080000uL)
+#define INTC_ICDISR8_SPEI2 (0x00100000uL)
+#define INTC_ICDISR8_SPRI2 (0x00200000uL)
+#define INTC_ICDISR8_SPTI2 (0x00400000uL)
+#define INTC_ICDISR8_SPEI3 (0x00800000uL)
+#define INTC_ICDISR8_SPRI3 (0x01000000uL)
+#define INTC_ICDISR8_SPTI3 (0x02000000uL)
+#define INTC_ICDISR8_SPEI4 (0x04000000uL)
+#define INTC_ICDISR8_SPRI4 (0x08000000uL)
+#define INTC_ICDISR8_SPTI4 (0x10000000uL)
+#define INTC_ICDISR8_IEBBTD (0x20000000uL)
+#define INTC_ICDISR8_IEBBTERR (0x40000000uL)
+#define INTC_ICDISR8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDISR9_IEBBTV (0x00000001uL)
+#define INTC_ICDISR9_ISY (0x00000002uL)
+#define INTC_ICDISR9_IERR (0x00000004uL)
+#define INTC_ICDISR9_ITARG (0x00000008uL)
+#define INTC_ICDISR9_ISEC (0x00000010uL)
+#define INTC_ICDISR9_IBUF (0x00000020uL)
+#define INTC_ICDISR9_IREADY (0x00000040uL)
+#define INTC_ICDISR9_FLSTE (0x00000080uL)
+#define INTC_ICDISR9_FLTENDI (0x00000100uL)
+#define INTC_ICDISR9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDISR9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDISR9_MMC0 (0x00000800uL)
+#define INTC_ICDISR9_MMC1 (0x00001000uL)
+#define INTC_ICDISR9_MMC2 (0x00002000uL)
+#define INTC_ICDISR9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDISR9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDISR9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDISR9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDISR9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDISR9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDISR9_ARM (0x00100000uL)
+#define INTC_ICDISR9_PRD (0x00200000uL)
+#define INTC_ICDISR9_CUP (0x00400000uL)
+#define INTC_ICDISR9_SCUAI0 (0x00800000uL)
+#define INTC_ICDISR9_SCUAI1 (0x01000000uL)
+#define INTC_ICDISR9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDISR9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDISR9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDISR9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDISR9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDISR9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDISR9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDISR10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDISR10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDISR10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDISR10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDISR10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDISR10_MLB_CINT (0x00000020uL)
+#define INTC_ICDISR10_MLB_SINT (0x00000040uL)
+#define INTC_ICDISR10_DRC0 (0x00000080uL)
+#define INTC_ICDISR10_DRC1 (0x00000100uL)
+#define INTC_ICDISR10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDISR10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDISR10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDISR10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDISR10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDISR10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDISR10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDISR10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDISR10_ERI0 (0x08000000uL)
+#define INTC_ICDISR10_RXI0 (0x10000000uL)
+#define INTC_ICDISR10_TXI0 (0x20000000uL)
+#define INTC_ICDISR10_TEI0 (0x40000000uL)
+#define INTC_ICDISR10_ERI1 (0x80000000uL)
+
+#define INTC_ICDISR11_RXI1 (0x00000001uL)
+#define INTC_ICDISR11_TXI1 (0x00000002uL)
+#define INTC_ICDISR11_TEI1 (0x00000004uL)
+#define INTC_ICDISR11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDISR11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDISR11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDISR11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDISR11_ETHERI (0x00000080uL)
+#define INTC_ICDISR11_CEUI (0x00001000uL)
+#define INTC_ICDISR11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDISR11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDISR11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDISR12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDISR12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDISR12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDISR12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDISR12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDISR12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDISR12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDISR12_PRRI (0x00000100uL)
+#define INTC_ICDISR12_IFEI0 (0x00000200uL)
+#define INTC_ICDISR12_OFFI0 (0x00000400uL)
+#define INTC_ICDISR12_PFVEI0 (0x00000800uL)
+#define INTC_ICDISR12_IFEI1 (0x00001000uL)
+#define INTC_ICDISR12_OFFI1 (0x00002000uL)
+#define INTC_ICDISR12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDISR13_TINT0 (0x00000001uL)
+#define INTC_ICDISR13_TINT1 (0x00000002uL)
+#define INTC_ICDISR13_TINT2 (0x00000004uL)
+#define INTC_ICDISR13_TINT3 (0x00000008uL)
+#define INTC_ICDISR13_TINT4 (0x00000010uL)
+#define INTC_ICDISR13_TINT5 (0x00000020uL)
+#define INTC_ICDISR13_TINT6 (0x00000040uL)
+#define INTC_ICDISR13_TINT7 (0x00000080uL)
+#define INTC_ICDISR13_TINT8 (0x00000100uL)
+#define INTC_ICDISR13_TINT9 (0x00000200uL)
+#define INTC_ICDISR13_TINT10 (0x00000400uL)
+#define INTC_ICDISR13_TINT11 (0x00000800uL)
+#define INTC_ICDISR13_TINT12 (0x00001000uL)
+#define INTC_ICDISR13_TINT13 (0x00002000uL)
+#define INTC_ICDISR13_TINT14 (0x00004000uL)
+#define INTC_ICDISR13_TINT15 (0x00008000uL)
+#define INTC_ICDISR13_TINT16 (0x00010000uL)
+#define INTC_ICDISR13_TINT17 (0x00020000uL)
+#define INTC_ICDISR13_TINT18 (0x00040000uL)
+#define INTC_ICDISR13_TINT19 (0x00080000uL)
+#define INTC_ICDISR13_TINT20 (0x00100000uL)
+#define INTC_ICDISR13_TINT21 (0x00200000uL)
+#define INTC_ICDISR13_TINT22 (0x00400000uL)
+#define INTC_ICDISR13_TINT23 (0x00800000uL)
+#define INTC_ICDISR13_TINT24 (0x01000000uL)
+#define INTC_ICDISR13_TINT25 (0x02000000uL)
+#define INTC_ICDISR13_TINT26 (0x04000000uL)
+#define INTC_ICDISR13_TINT27 (0x08000000uL)
+#define INTC_ICDISR13_TINT28 (0x10000000uL)
+#define INTC_ICDISR13_TINT29 (0x20000000uL)
+#define INTC_ICDISR13_TINT30 (0x40000000uL)
+#define INTC_ICDISR13_TINT31 (0x80000000uL)
+
+#define INTC_ICDISR14_TINT32 (0x00000001uL)
+#define INTC_ICDISR14_TINT33 (0x00000002uL)
+#define INTC_ICDISR14_TINT34 (0x00000004uL)
+#define INTC_ICDISR14_TINT35 (0x00000008uL)
+#define INTC_ICDISR14_TINT36 (0x00000010uL)
+#define INTC_ICDISR14_TINT37 (0x00000020uL)
+#define INTC_ICDISR14_TINT38 (0x00000040uL)
+#define INTC_ICDISR14_TINT39 (0x00000080uL)
+#define INTC_ICDISR14_TINT40 (0x00000100uL)
+#define INTC_ICDISR14_TINT41 (0x00000200uL)
+#define INTC_ICDISR14_TINT42 (0x00000400uL)
+#define INTC_ICDISR14_TINT43 (0x00000800uL)
+#define INTC_ICDISR14_TINT44 (0x00001000uL)
+#define INTC_ICDISR14_TINT45 (0x00002000uL)
+#define INTC_ICDISR14_TINT46 (0x00004000uL)
+#define INTC_ICDISR14_TINT47 (0x00008000uL)
+#define INTC_ICDISR14_TINT48 (0x00010000uL)
+#define INTC_ICDISR14_TINT49 (0x00020000uL)
+#define INTC_ICDISR14_TINT50 (0x00040000uL)
+#define INTC_ICDISR14_TINT51 (0x00080000uL)
+#define INTC_ICDISR14_TINT52 (0x00100000uL)
+#define INTC_ICDISR14_TINT53 (0x00200000uL)
+#define INTC_ICDISR14_TINT54 (0x00400000uL)
+#define INTC_ICDISR14_TINT55 (0x00800000uL)
+#define INTC_ICDISR14_TINT56 (0x01000000uL)
+#define INTC_ICDISR14_TINT57 (0x02000000uL)
+#define INTC_ICDISR14_TINT58 (0x04000000uL)
+#define INTC_ICDISR14_TINT59 (0x08000000uL)
+#define INTC_ICDISR14_TINT60 (0x10000000uL)
+#define INTC_ICDISR14_TINT61 (0x20000000uL)
+#define INTC_ICDISR14_TINT62 (0x40000000uL)
+#define INTC_ICDISR14_TINT63 (0x80000000uL)
+
+#define INTC_ICDISR15_TINT64 (0x00000001uL)
+#define INTC_ICDISR15_TINT65 (0x00000002uL)
+#define INTC_ICDISR15_TINT66 (0x00000004uL)
+#define INTC_ICDISR15_TINT67 (0x00000008uL)
+#define INTC_ICDISR15_TINT68 (0x00000010uL)
+#define INTC_ICDISR15_TINT69 (0x00000020uL)
+#define INTC_ICDISR15_TINT70 (0x00000040uL)
+#define INTC_ICDISR15_TINT71 (0x00000080uL)
+#define INTC_ICDISR15_TINT72 (0x00000100uL)
+#define INTC_ICDISR15_TINT73 (0x00000200uL)
+#define INTC_ICDISR15_TINT74 (0x00000400uL)
+#define INTC_ICDISR15_TINT75 (0x00000800uL)
+#define INTC_ICDISR15_TINT76 (0x00001000uL)
+#define INTC_ICDISR15_TINT77 (0x00002000uL)
+#define INTC_ICDISR15_TINT78 (0x00004000uL)
+#define INTC_ICDISR15_TINT79 (0x00008000uL)
+#define INTC_ICDISR15_TINT80 (0x00010000uL)
+#define INTC_ICDISR15_TINT81 (0x00020000uL)
+#define INTC_ICDISR15_TINT82 (0x00040000uL)
+#define INTC_ICDISR15_TINT83 (0x00080000uL)
+#define INTC_ICDISR15_TINT84 (0x00100000uL)
+#define INTC_ICDISR15_TINT85 (0x00200000uL)
+#define INTC_ICDISR15_TINT86 (0x00400000uL)
+#define INTC_ICDISR15_TINT87 (0x00800000uL)
+#define INTC_ICDISR15_TINT88 (0x01000000uL)
+#define INTC_ICDISR15_TINT89 (0x02000000uL)
+#define INTC_ICDISR15_TINT90 (0x04000000uL)
+#define INTC_ICDISR15_TINT91 (0x08000000uL)
+#define INTC_ICDISR15_TINT92 (0x10000000uL)
+#define INTC_ICDISR15_TINT93 (0x20000000uL)
+#define INTC_ICDISR15_TINT94 (0x40000000uL)
+#define INTC_ICDISR15_TINT95 (0x80000000uL)
+
+#define INTC_ICDISR16_TINT96 (0x00000001uL)
+#define INTC_ICDISR16_TINT97 (0x00000002uL)
+#define INTC_ICDISR16_TINT98 (0x00000004uL)
+#define INTC_ICDISR16_TINT99 (0x00000008uL)
+#define INTC_ICDISR16_TINT100 (0x00000010uL)
+#define INTC_ICDISR16_TINT101 (0x00000020uL)
+#define INTC_ICDISR16_TINT102 (0x00000040uL)
+#define INTC_ICDISR16_TINT103 (0x00000080uL)
+#define INTC_ICDISR16_TINT104 (0x00000100uL)
+#define INTC_ICDISR16_TINT105 (0x00000200uL)
+#define INTC_ICDISR16_TINT106 (0x00000400uL)
+#define INTC_ICDISR16_TINT107 (0x00000800uL)
+#define INTC_ICDISR16_TINT108 (0x00001000uL)
+#define INTC_ICDISR16_TINT109 (0x00002000uL)
+#define INTC_ICDISR16_TINT110 (0x00004000uL)
+#define INTC_ICDISR16_TINT111 (0x00008000uL)
+#define INTC_ICDISR16_TINT112 (0x00010000uL)
+#define INTC_ICDISR16_TINT113 (0x00020000uL)
+#define INTC_ICDISR16_TINT114 (0x00040000uL)
+#define INTC_ICDISR16_TINT115 (0x00080000uL)
+#define INTC_ICDISR16_TINT116 (0x00100000uL)
+#define INTC_ICDISR16_TINT117 (0x00200000uL)
+#define INTC_ICDISR16_TINT118 (0x00400000uL)
+#define INTC_ICDISR16_TINT119 (0x00800000uL)
+#define INTC_ICDISR16_TINT120 (0x01000000uL)
+#define INTC_ICDISR16_TINT121 (0x02000000uL)
+#define INTC_ICDISR16_TINT122 (0x04000000uL)
+#define INTC_ICDISR16_TINT123 (0x08000000uL)
+#define INTC_ICDISR16_TINT124 (0x10000000uL)
+#define INTC_ICDISR16_TINT125 (0x20000000uL)
+#define INTC_ICDISR16_TINT126 (0x40000000uL)
+#define INTC_ICDISR16_TINT127 (0x80000000uL)
+
+#define INTC_ICDISR17_TINT128 (0x00000001uL)
+#define INTC_ICDISR17_TINT129 (0x00000002uL)
+#define INTC_ICDISR17_TINT130 (0x00000004uL)
+#define INTC_ICDISR17_TINT131 (0x00000008uL)
+#define INTC_ICDISR17_TINT132 (0x00000010uL)
+#define INTC_ICDISR17_TINT133 (0x00000020uL)
+#define INTC_ICDISR17_TINT134 (0x00000040uL)
+#define INTC_ICDISR17_TINT135 (0x00000080uL)
+#define INTC_ICDISR17_TINT136 (0x00000100uL)
+#define INTC_ICDISR17_TINT137 (0x00000200uL)
+#define INTC_ICDISR17_TINT138 (0x00000400uL)
+#define INTC_ICDISR17_TINT139 (0x00000800uL)
+#define INTC_ICDISR17_TINT140 (0x00001000uL)
+#define INTC_ICDISR17_TINT141 (0x00002000uL)
+#define INTC_ICDISR17_TINT142 (0x00004000uL)
+#define INTC_ICDISR17_TINT143 (0x00008000uL)
+#define INTC_ICDISR17_TINT144 (0x00010000uL)
+#define INTC_ICDISR17_TINT145 (0x00020000uL)
+#define INTC_ICDISR17_TINT146 (0x00040000uL)
+#define INTC_ICDISR17_TINT147 (0x00080000uL)
+#define INTC_ICDISR17_TINT148 (0x00100000uL)
+#define INTC_ICDISR17_TINT149 (0x00200000uL)
+#define INTC_ICDISR17_TINT150 (0x00400000uL)
+#define INTC_ICDISR17_TINT151 (0x00800000uL)
+#define INTC_ICDISR17_TINT152 (0x01000000uL)
+#define INTC_ICDISR17_TINT153 (0x02000000uL)
+#define INTC_ICDISR17_TINT154 (0x04000000uL)
+#define INTC_ICDISR17_TINT155 (0x08000000uL)
+#define INTC_ICDISR17_TINT156 (0x10000000uL)
+#define INTC_ICDISR17_TINT157 (0x20000000uL)
+#define INTC_ICDISR17_TINT158 (0x40000000uL)
+#define INTC_ICDISR17_TINT159 (0x80000000uL)
+
+#define INTC_ICDISR18_TINT160 (0x00000001uL)
+#define INTC_ICDISR18_TINT161 (0x00000002uL)
+#define INTC_ICDISR18_TINT162 (0x00000004uL)
+#define INTC_ICDISR18_TINT163 (0x00000008uL)
+#define INTC_ICDISR18_TINT164 (0x00000010uL)
+#define INTC_ICDISR18_TINT165 (0x00000020uL)
+#define INTC_ICDISR18_TINT166 (0x00000040uL)
+#define INTC_ICDISR18_TINT167 (0x00000080uL)
+#define INTC_ICDISR18_TINT168 (0x00000100uL)
+#define INTC_ICDISR18_TINT169 (0x00000200uL)
+#define INTC_ICDISR18_TINT170 (0x00000400uL)
+
+#define INTC_ICDISER0_SW0 (0x00000001uL)
+#define INTC_ICDISER0_SW1 (0x00000002uL)
+#define INTC_ICDISER0_SW2 (0x00000004uL)
+#define INTC_ICDISER0_SW3 (0x00000008uL)
+#define INTC_ICDISER0_SW4 (0x00000010uL)
+#define INTC_ICDISER0_SW5 (0x00000020uL)
+#define INTC_ICDISER0_SW6 (0x00000040uL)
+#define INTC_ICDISER0_SW7 (0x00000080uL)
+#define INTC_ICDISER0_SW8 (0x00000100uL)
+#define INTC_ICDISER0_SW9 (0x00000200uL)
+#define INTC_ICDISER0_SW10 (0x00000400uL)
+#define INTC_ICDISER0_SW11 (0x00000800uL)
+#define INTC_ICDISER0_SW12 (0x00001000uL)
+#define INTC_ICDISER0_SW13 (0x00002000uL)
+#define INTC_ICDISER0_SW14 (0x00004000uL)
+#define INTC_ICDISER0_SW15 (0x00008000uL)
+#define INTC_ICDISER0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDISER0_COMMRX0 (0x00020000uL)
+#define INTC_ICDISER0_COMMTX0 (0x00040000uL)
+#define INTC_ICDISER0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDISER1_IRQ0 (0x00000001uL)
+#define INTC_ICDISER1_IRQ1 (0x00000002uL)
+#define INTC_ICDISER1_IRQ2 (0x00000004uL)
+#define INTC_ICDISER1_IRQ3 (0x00000008uL)
+#define INTC_ICDISER1_IRQ4 (0x00000010uL)
+#define INTC_ICDISER1_IRQ5 (0x00000020uL)
+#define INTC_ICDISER1_IRQ6 (0x00000040uL)
+#define INTC_ICDISER1_IRQ7 (0x00000080uL)
+#define INTC_ICDISER1_PL310ERR (0x00000100uL)
+#define INTC_ICDISER1_DMAINT0 (0x00000200uL)
+#define INTC_ICDISER1_DMAINT1 (0x00000400uL)
+#define INTC_ICDISER1_DMAINT2 (0x00000800uL)
+#define INTC_ICDISER1_DMAINT3 (0x00001000uL)
+#define INTC_ICDISER1_DMAINT4 (0x00002000uL)
+#define INTC_ICDISER1_DMAINT5 (0x00004000uL)
+#define INTC_ICDISER1_DMAINT6 (0x00008000uL)
+#define INTC_ICDISER1_DMAINT7 (0x00010000uL)
+#define INTC_ICDISER1_DMAINT8 (0x00020000uL)
+#define INTC_ICDISER1_DMAINT9 (0x00040000uL)
+#define INTC_ICDISER1_DMAINT10 (0x00080000uL)
+#define INTC_ICDISER1_DMAINT11 (0x00100000uL)
+#define INTC_ICDISER1_DMAINT12 (0x00200000uL)
+#define INTC_ICDISER1_DMAINT13 (0x00400000uL)
+#define INTC_ICDISER1_DMAINT14 (0x00800000uL)
+#define INTC_ICDISER1_DMAINT15 (0x01000000uL)
+#define INTC_ICDISER1_DMAERR (0x02000000uL)
+
+#define INTC_ICDISER2_USBI0 (0x00000200uL)
+#define INTC_ICDISER2_USBI1 (0x00000400uL)
+#define INTC_ICDISER2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDISER2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDISER2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDISER2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDISER2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDISER2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDISER2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDISER2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDISER2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDISER2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDISER2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDISER2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDISER2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDISER2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDISER2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDISER2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDISER2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDISER2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDISER2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDISER2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDISER2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDISER3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDISER3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDISER3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDISER3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDISER3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDISER3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDISER3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDISER3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDISER3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDISER3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDISER3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDISER3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDISER3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDISER3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDISER3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDISER3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDISER3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDISER3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDISER3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDISER3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDISER3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDISER3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDISER3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDISER3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDISER3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDISER3_IMRDI (0x08000000uL)
+#define INTC_ICDISER3_IMR2I0 (0x10000000uL)
+#define INTC_ICDISER3_IMR2I1 (0x20000000uL)
+#define INTC_ICDISER3_JEDI (0x40000000uL)
+#define INTC_ICDISER3_JDTI (0x80000000uL)
+
+#define INTC_ICDISER4_CMP0 (0x00000001uL)
+#define INTC_ICDISER4_CMP1 (0x00000002uL)
+#define INTC_ICDISER4_INT0 (0x00000004uL)
+#define INTC_ICDISER4_INT1 (0x00000008uL)
+#define INTC_ICDISER4_INT2 (0x00000010uL)
+#define INTC_ICDISER4_INT3 (0x00000020uL)
+#define INTC_ICDISER4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDISER4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDISER4_CMI (0x00000100uL)
+#define INTC_ICDISER4_WTOUT (0x00000200uL)
+#define INTC_ICDISER4_ITI (0x00000400uL)
+#define INTC_ICDISER4_TGI0A (0x00000800uL)
+#define INTC_ICDISER4_TGI0B (0x00001000uL)
+#define INTC_ICDISER4_TGI0C (0x00002000uL)
+#define INTC_ICDISER4_TGI0D (0x00004000uL)
+#define INTC_ICDISER4_TGI0V (0x00008000uL)
+#define INTC_ICDISER4_TGI0E (0x00010000uL)
+#define INTC_ICDISER4_TGI0F (0x00020000uL)
+#define INTC_ICDISER4_TGI1A (0x00040000uL)
+#define INTC_ICDISER4_TGI1B (0x00080000uL)
+#define INTC_ICDISER4_TGI1V (0x00100000uL)
+#define INTC_ICDISER4_TGI1U (0x00200000uL)
+#define INTC_ICDISER4_TGI2A (0x00400000uL)
+#define INTC_ICDISER4_TGI2B (0x00800000uL)
+#define INTC_ICDISER4_TGI2V (0x01000000uL)
+#define INTC_ICDISER4_TGI2U (0x02000000uL)
+#define INTC_ICDISER4_TGI3A (0x04000000uL)
+#define INTC_ICDISER4_TGI3B (0x08000000uL)
+#define INTC_ICDISER4_TGI3C (0x10000000uL)
+#define INTC_ICDISER4_TGI3D (0x20000000uL)
+#define INTC_ICDISER4_TGI3V (0x40000000uL)
+#define INTC_ICDISER4_TGI4A (0x80000000uL)
+
+#define INTC_ICDISER5_TGI4B (0x00000001uL)
+#define INTC_ICDISER5_TGI4C (0x00000002uL)
+#define INTC_ICDISER5_TGI4D (0x00000004uL)
+#define INTC_ICDISER5_TGI4V (0x00000008uL)
+#define INTC_ICDISER5_CMI1 (0x00000010uL)
+#define INTC_ICDISER5_CMI2 (0x00000020uL)
+#define INTC_ICDISER5_SGDEI0 (0x00000040uL)
+#define INTC_ICDISER5_SGDEI1 (0x00000080uL)
+#define INTC_ICDISER5_SGDEI2 (0x00000100uL)
+#define INTC_ICDISER5_SGDEI3 (0x00000200uL)
+#define INTC_ICDISER5_ADI (0x00000400uL)
+#define INTC_ICDISER5_LMTI (0x00000800uL)
+#define INTC_ICDISER5_SSII0 (0x00001000uL)
+#define INTC_ICDISER5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDISER5_SSITXI0 (0x00004000uL)
+#define INTC_ICDISER5_SSII1 (0x00008000uL)
+#define INTC_ICDISER5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDISER5_SSITXI1 (0x00020000uL)
+#define INTC_ICDISER5_SSII2 (0x00040000uL)
+#define INTC_ICDISER5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDISER5_SSII3 (0x00100000uL)
+#define INTC_ICDISER5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDISER5_SSITXI3 (0x00400000uL)
+#define INTC_ICDISER5_SSII4 (0x00800000uL)
+#define INTC_ICDISER5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDISER5_SSII5 (0x02000000uL)
+#define INTC_ICDISER5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDISER5_SSITXI5 (0x08000000uL)
+#define INTC_ICDISER5_SPDIFI (0x10000000uL)
+#define INTC_ICDISER5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDISER5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDISER5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDISER6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDISER6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDISER6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDISER6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDISER6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDISER6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDISER6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDISER6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDISER6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDISER6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDISER6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDISER6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDISER6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDISER6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDISER6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDISER6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDISER6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDISER6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDISER6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDISER6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDISER6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDISER6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDISER6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDISER6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDISER6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDISER6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDISER6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDISER6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDISER6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDISER6_BRI0 (0x20000000uL)
+#define INTC_ICDISER6_ERI0 (0x40000000uL)
+#define INTC_ICDISER6_RXI0 (0x80000000uL)
+
+#define INTC_ICDISER7_TXI0 (0x00000001uL)
+#define INTC_ICDISER7_BRI1 (0x00000002uL)
+#define INTC_ICDISER7_ERI1 (0x00000004uL)
+#define INTC_ICDISER7_RXI1 (0x00000008uL)
+#define INTC_ICDISER7_TXI1 (0x00000010uL)
+#define INTC_ICDISER7_BRI2 (0x00000020uL)
+#define INTC_ICDISER7_ERI2 (0x00000040uL)
+#define INTC_ICDISER7_RXI2 (0x00000080uL)
+#define INTC_ICDISER7_TXI2 (0x00000100uL)
+#define INTC_ICDISER7_BRI3 (0x00000200uL)
+#define INTC_ICDISER7_ERI3 (0x00000400uL)
+#define INTC_ICDISER7_RXI3 (0x00000800uL)
+#define INTC_ICDISER7_TXI3 (0x00001000uL)
+#define INTC_ICDISER7_BRI4 (0x00002000uL)
+#define INTC_ICDISER7_ERI4 (0x00004000uL)
+#define INTC_ICDISER7_RXI4 (0x00008000uL)
+#define INTC_ICDISER7_TXI4 (0x00010000uL)
+#define INTC_ICDISER7_BRI5 (0x00020000uL)
+#define INTC_ICDISER7_ERI5 (0x00040000uL)
+#define INTC_ICDISER7_RXI5 (0x00080000uL)
+#define INTC_ICDISER7_TXI5 (0x00100000uL)
+#define INTC_ICDISER7_BRI6 (0x00200000uL)
+#define INTC_ICDISER7_ERI6 (0x00400000uL)
+#define INTC_ICDISER7_RXI6 (0x00800000uL)
+#define INTC_ICDISER7_TXI6 (0x01000000uL)
+#define INTC_ICDISER7_BRI7 (0x02000000uL)
+#define INTC_ICDISER7_ERI7 (0x04000000uL)
+#define INTC_ICDISER7_RXI7 (0x08000000uL)
+#define INTC_ICDISER7_TXI7 (0x10000000uL)
+#define INTC_ICDISER7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDISER7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDISER7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDISER8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDISER8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDISER8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDISER8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDISER8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDISER8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDISER8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDISER8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDISER8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDISER8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDISER8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDISER8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDISER8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDISER8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDISER8_SPEI0 (0x00004000uL)
+#define INTC_ICDISER8_SPRI0 (0x00008000uL)
+#define INTC_ICDISER8_SPTI0 (0x00010000uL)
+#define INTC_ICDISER8_SPEI1 (0x00020000uL)
+#define INTC_ICDISER8_SPRI1 (0x00040000uL)
+#define INTC_ICDISER8_SPTI1 (0x00080000uL)
+#define INTC_ICDISER8_SPEI2 (0x00100000uL)
+#define INTC_ICDISER8_SPRI2 (0x00200000uL)
+#define INTC_ICDISER8_SPTI2 (0x00400000uL)
+#define INTC_ICDISER8_SPEI3 (0x00800000uL)
+#define INTC_ICDISER8_SPRI3 (0x01000000uL)
+#define INTC_ICDISER8_SPTI3 (0x02000000uL)
+#define INTC_ICDISER8_SPEI4 (0x04000000uL)
+#define INTC_ICDISER8_SPRI4 (0x08000000uL)
+#define INTC_ICDISER8_SPTI4 (0x10000000uL)
+#define INTC_ICDISER8_IEBBTD (0x20000000uL)
+#define INTC_ICDISER8_IEBBTERR (0x40000000uL)
+#define INTC_ICDISER8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDISER9_IEBBTV (0x00000001uL)
+#define INTC_ICDISER9_ISY (0x00000002uL)
+#define INTC_ICDISER9_IERR (0x00000004uL)
+#define INTC_ICDISER9_ITARG (0x00000008uL)
+#define INTC_ICDISER9_ISEC (0x00000010uL)
+#define INTC_ICDISER9_IBUF (0x00000020uL)
+#define INTC_ICDISER9_IREADY (0x00000040uL)
+#define INTC_ICDISER9_FLSTE (0x00000080uL)
+#define INTC_ICDISER9_FLTENDI (0x00000100uL)
+#define INTC_ICDISER9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDISER9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDISER9_MMC0 (0x00000800uL)
+#define INTC_ICDISER9_MMC1 (0x00001000uL)
+#define INTC_ICDISER9_MMC2 (0x00002000uL)
+#define INTC_ICDISER9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDISER9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDISER9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDISER9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDISER9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDISER9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDISER9_ARM (0x00100000uL)
+#define INTC_ICDISER9_PRD (0x00200000uL)
+#define INTC_ICDISER9_CUP (0x00400000uL)
+#define INTC_ICDISER9_SCUAI0 (0x00800000uL)
+#define INTC_ICDISER9_SCUAI1 (0x01000000uL)
+#define INTC_ICDISER9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDISER9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDISER9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDISER9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDISER9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDISER9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDISER9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDISER10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDISER10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDISER10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDISER10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDISER10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDISER10_MLB_CINT (0x00000020uL)
+#define INTC_ICDISER10_MLB_SINT (0x00000040uL)
+#define INTC_ICDISER10_DRC0 (0x00000080uL)
+#define INTC_ICDISER10_DRC1 (0x00000100uL)
+#define INTC_ICDISER10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDISER10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDISER10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDISER10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDISER10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDISER10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDISER10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDISER10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDISER10_ERI0 (0x08000000uL)
+#define INTC_ICDISER10_RXI0 (0x10000000uL)
+#define INTC_ICDISER10_TXI0 (0x20000000uL)
+#define INTC_ICDISER10_TEI0 (0x40000000uL)
+#define INTC_ICDISER10_ERI1 (0x80000000uL)
+
+#define INTC_ICDISER11_RXI1 (0x00000001uL)
+#define INTC_ICDISER11_TXI1 (0x00000002uL)
+#define INTC_ICDISER11_TEI1 (0x00000004uL)
+#define INTC_ICDISER11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDISER11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDISER11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDISER11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDISER11_ETHERI (0x00000080uL)
+#define INTC_ICDISER11_CEUI (0x00001000uL)
+#define INTC_ICDISER11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDISER11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDISER11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDISER12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDISER12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDISER12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDISER12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDISER12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDISER12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDISER12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDISER12_PRRI (0x00000100uL)
+#define INTC_ICDISER12_IFEI0 (0x00000200uL)
+#define INTC_ICDISER12_OFFI0 (0x00000400uL)
+#define INTC_ICDISER12_PFVEI0 (0x00000800uL)
+#define INTC_ICDISER12_IFEI1 (0x00001000uL)
+#define INTC_ICDISER12_OFFI1 (0x00002000uL)
+#define INTC_ICDISER12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDISER13_TINT0 (0x00000001uL)
+#define INTC_ICDISER13_TINT1 (0x00000002uL)
+#define INTC_ICDISER13_TINT2 (0x00000004uL)
+#define INTC_ICDISER13_TINT3 (0x00000008uL)
+#define INTC_ICDISER13_TINT4 (0x00000010uL)
+#define INTC_ICDISER13_TINT5 (0x00000020uL)
+#define INTC_ICDISER13_TINT6 (0x00000040uL)
+#define INTC_ICDISER13_TINT7 (0x00000080uL)
+#define INTC_ICDISER13_TINT8 (0x00000100uL)
+#define INTC_ICDISER13_TINT9 (0x00000200uL)
+#define INTC_ICDISER13_TINT10 (0x00000400uL)
+#define INTC_ICDISER13_TINT11 (0x00000800uL)
+#define INTC_ICDISER13_TINT12 (0x00001000uL)
+#define INTC_ICDISER13_TINT13 (0x00002000uL)
+#define INTC_ICDISER13_TINT14 (0x00004000uL)
+#define INTC_ICDISER13_TINT15 (0x00008000uL)
+#define INTC_ICDISER13_TINT16 (0x00010000uL)
+#define INTC_ICDISER13_TINT17 (0x00020000uL)
+#define INTC_ICDISER13_TINT18 (0x00040000uL)
+#define INTC_ICDISER13_TINT19 (0x00080000uL)
+#define INTC_ICDISER13_TINT20 (0x00100000uL)
+#define INTC_ICDISER13_TINT21 (0x00200000uL)
+#define INTC_ICDISER13_TINT22 (0x00400000uL)
+#define INTC_ICDISER13_TINT23 (0x00800000uL)
+#define INTC_ICDISER13_TINT24 (0x01000000uL)
+#define INTC_ICDISER13_TINT25 (0x02000000uL)
+#define INTC_ICDISER13_TINT26 (0x04000000uL)
+#define INTC_ICDISER13_TINT27 (0x08000000uL)
+#define INTC_ICDISER13_TINT28 (0x10000000uL)
+#define INTC_ICDISER13_TINT29 (0x20000000uL)
+#define INTC_ICDISER13_TINT30 (0x40000000uL)
+#define INTC_ICDISER13_TINT31 (0x80000000uL)
+
+#define INTC_ICDISER14_TINT32 (0x00000001uL)
+#define INTC_ICDISER14_TINT33 (0x00000002uL)
+#define INTC_ICDISER14_TINT34 (0x00000004uL)
+#define INTC_ICDISER14_TINT35 (0x00000008uL)
+#define INTC_ICDISER14_TINT36 (0x00000010uL)
+#define INTC_ICDISER14_TINT37 (0x00000020uL)
+#define INTC_ICDISER14_TINT38 (0x00000040uL)
+#define INTC_ICDISER14_TINT39 (0x00000080uL)
+#define INTC_ICDISER14_TINT40 (0x00000100uL)
+#define INTC_ICDISER14_TINT41 (0x00000200uL)
+#define INTC_ICDISER14_TINT42 (0x00000400uL)
+#define INTC_ICDISER14_TINT43 (0x00000800uL)
+#define INTC_ICDISER14_TINT44 (0x00001000uL)
+#define INTC_ICDISER14_TINT45 (0x00002000uL)
+#define INTC_ICDISER14_TINT46 (0x00004000uL)
+#define INTC_ICDISER14_TINT47 (0x00008000uL)
+#define INTC_ICDISER14_TINT48 (0x00010000uL)
+#define INTC_ICDISER14_TINT49 (0x00020000uL)
+#define INTC_ICDISER14_TINT50 (0x00040000uL)
+#define INTC_ICDISER14_TINT51 (0x00080000uL)
+#define INTC_ICDISER14_TINT52 (0x00100000uL)
+#define INTC_ICDISER14_TINT53 (0x00200000uL)
+#define INTC_ICDISER14_TINT54 (0x00400000uL)
+#define INTC_ICDISER14_TINT55 (0x00800000uL)
+#define INTC_ICDISER14_TINT56 (0x01000000uL)
+#define INTC_ICDISER14_TINT57 (0x02000000uL)
+#define INTC_ICDISER14_TINT58 (0x04000000uL)
+#define INTC_ICDISER14_TINT59 (0x08000000uL)
+#define INTC_ICDISER14_TINT60 (0x10000000uL)
+#define INTC_ICDISER14_TINT61 (0x20000000uL)
+#define INTC_ICDISER14_TINT62 (0x40000000uL)
+#define INTC_ICDISER14_TINT63 (0x80000000uL)
+
+#define INTC_ICDISER15_TINT64 (0x00000001uL)
+#define INTC_ICDISER15_TINT65 (0x00000002uL)
+#define INTC_ICDISER15_TINT66 (0x00000004uL)
+#define INTC_ICDISER15_TINT67 (0x00000008uL)
+#define INTC_ICDISER15_TINT68 (0x00000010uL)
+#define INTC_ICDISER15_TINT69 (0x00000020uL)
+#define INTC_ICDISER15_TINT70 (0x00000040uL)
+#define INTC_ICDISER15_TINT71 (0x00000080uL)
+#define INTC_ICDISER15_TINT72 (0x00000100uL)
+#define INTC_ICDISER15_TINT73 (0x00000200uL)
+#define INTC_ICDISER15_TINT74 (0x00000400uL)
+#define INTC_ICDISER15_TINT75 (0x00000800uL)
+#define INTC_ICDISER15_TINT76 (0x00001000uL)
+#define INTC_ICDISER15_TINT77 (0x00002000uL)
+#define INTC_ICDISER15_TINT78 (0x00004000uL)
+#define INTC_ICDISER15_TINT79 (0x00008000uL)
+#define INTC_ICDISER15_TINT80 (0x00010000uL)
+#define INTC_ICDISER15_TINT81 (0x00020000uL)
+#define INTC_ICDISER15_TINT82 (0x00040000uL)
+#define INTC_ICDISER15_TINT83 (0x00080000uL)
+#define INTC_ICDISER15_TINT84 (0x00100000uL)
+#define INTC_ICDISER15_TINT85 (0x00200000uL)
+#define INTC_ICDISER15_TINT86 (0x00400000uL)
+#define INTC_ICDISER15_TINT87 (0x00800000uL)
+#define INTC_ICDISER15_TINT88 (0x01000000uL)
+#define INTC_ICDISER15_TINT89 (0x02000000uL)
+#define INTC_ICDISER15_TINT90 (0x04000000uL)
+#define INTC_ICDISER15_TINT91 (0x08000000uL)
+#define INTC_ICDISER15_TINT92 (0x10000000uL)
+#define INTC_ICDISER15_TINT93 (0x20000000uL)
+#define INTC_ICDISER15_TINT94 (0x40000000uL)
+#define INTC_ICDISER15_TINT95 (0x80000000uL)
+
+#define INTC_ICDISER16_TINT96 (0x00000001uL)
+#define INTC_ICDISER16_TINT97 (0x00000002uL)
+#define INTC_ICDISER16_TINT98 (0x00000004uL)
+#define INTC_ICDISER16_TINT99 (0x00000008uL)
+#define INTC_ICDISER16_TINT100 (0x00000010uL)
+#define INTC_ICDISER16_TINT101 (0x00000020uL)
+#define INTC_ICDISER16_TINT102 (0x00000040uL)
+#define INTC_ICDISER16_TINT103 (0x00000080uL)
+#define INTC_ICDISER16_TINT104 (0x00000100uL)
+#define INTC_ICDISER16_TINT105 (0x00000200uL)
+#define INTC_ICDISER16_TINT106 (0x00000400uL)
+#define INTC_ICDISER16_TINT107 (0x00000800uL)
+#define INTC_ICDISER16_TINT108 (0x00001000uL)
+#define INTC_ICDISER16_TINT109 (0x00002000uL)
+#define INTC_ICDISER16_TINT110 (0x00004000uL)
+#define INTC_ICDISER16_TINT111 (0x00008000uL)
+#define INTC_ICDISER16_TINT112 (0x00010000uL)
+#define INTC_ICDISER16_TINT113 (0x00020000uL)
+#define INTC_ICDISER16_TINT114 (0x00040000uL)
+#define INTC_ICDISER16_TINT115 (0x00080000uL)
+#define INTC_ICDISER16_TINT116 (0x00100000uL)
+#define INTC_ICDISER16_TINT117 (0x00200000uL)
+#define INTC_ICDISER16_TINT118 (0x00400000uL)
+#define INTC_ICDISER16_TINT119 (0x00800000uL)
+#define INTC_ICDISER16_TINT120 (0x01000000uL)
+#define INTC_ICDISER16_TINT121 (0x02000000uL)
+#define INTC_ICDISER16_TINT122 (0x04000000uL)
+#define INTC_ICDISER16_TINT123 (0x08000000uL)
+#define INTC_ICDISER16_TINT124 (0x10000000uL)
+#define INTC_ICDISER16_TINT125 (0x20000000uL)
+#define INTC_ICDISER16_TINT126 (0x40000000uL)
+#define INTC_ICDISER16_TINT127 (0x80000000uL)
+
+#define INTC_ICDISER17_TINT128 (0x00000001uL)
+#define INTC_ICDISER17_TINT129 (0x00000002uL)
+#define INTC_ICDISER17_TINT130 (0x00000004uL)
+#define INTC_ICDISER17_TINT131 (0x00000008uL)
+#define INTC_ICDISER17_TINT132 (0x00000010uL)
+#define INTC_ICDISER17_TINT133 (0x00000020uL)
+#define INTC_ICDISER17_TINT134 (0x00000040uL)
+#define INTC_ICDISER17_TINT135 (0x00000080uL)
+#define INTC_ICDISER17_TINT136 (0x00000100uL)
+#define INTC_ICDISER17_TINT137 (0x00000200uL)
+#define INTC_ICDISER17_TINT138 (0x00000400uL)
+#define INTC_ICDISER17_TINT139 (0x00000800uL)
+#define INTC_ICDISER17_TINT140 (0x00001000uL)
+#define INTC_ICDISER17_TINT141 (0x00002000uL)
+#define INTC_ICDISER17_TINT142 (0x00004000uL)
+#define INTC_ICDISER17_TINT143 (0x00008000uL)
+#define INTC_ICDISER17_TINT144 (0x00010000uL)
+#define INTC_ICDISER17_TINT145 (0x00020000uL)
+#define INTC_ICDISER17_TINT146 (0x00040000uL)
+#define INTC_ICDISER17_TINT147 (0x00080000uL)
+#define INTC_ICDISER17_TINT148 (0x00100000uL)
+#define INTC_ICDISER17_TINT149 (0x00200000uL)
+#define INTC_ICDISER17_TINT150 (0x00400000uL)
+#define INTC_ICDISER17_TINT151 (0x00800000uL)
+#define INTC_ICDISER17_TINT152 (0x01000000uL)
+#define INTC_ICDISER17_TINT153 (0x02000000uL)
+#define INTC_ICDISER17_TINT154 (0x04000000uL)
+#define INTC_ICDISER17_TINT155 (0x08000000uL)
+#define INTC_ICDISER17_TINT156 (0x10000000uL)
+#define INTC_ICDISER17_TINT157 (0x20000000uL)
+#define INTC_ICDISER17_TINT158 (0x40000000uL)
+#define INTC_ICDISER17_TINT159 (0x80000000uL)
+
+#define INTC_ICDISER18_TINT160 (0x00000001uL)
+#define INTC_ICDISER18_TINT161 (0x00000002uL)
+#define INTC_ICDISER18_TINT162 (0x00000004uL)
+#define INTC_ICDISER18_TINT163 (0x00000008uL)
+#define INTC_ICDISER18_TINT164 (0x00000010uL)
+#define INTC_ICDISER18_TINT165 (0x00000020uL)
+#define INTC_ICDISER18_TINT166 (0x00000040uL)
+#define INTC_ICDISER18_TINT167 (0x00000080uL)
+#define INTC_ICDISER18_TINT168 (0x00000100uL)
+#define INTC_ICDISER18_TINT169 (0x00000200uL)
+#define INTC_ICDISER18_TINT170 (0x00000400uL)
+
+#define INTC_ICDICER0_SW0 (0x00000001uL)
+#define INTC_ICDICER0_SW1 (0x00000002uL)
+#define INTC_ICDICER0_SW2 (0x00000004uL)
+#define INTC_ICDICER0_SW3 (0x00000008uL)
+#define INTC_ICDICER0_SW4 (0x00000010uL)
+#define INTC_ICDICER0_SW5 (0x00000020uL)
+#define INTC_ICDICER0_SW6 (0x00000040uL)
+#define INTC_ICDICER0_SW7 (0x00000080uL)
+#define INTC_ICDICER0_SW8 (0x00000100uL)
+#define INTC_ICDICER0_SW9 (0x00000200uL)
+#define INTC_ICDICER0_SW10 (0x00000400uL)
+#define INTC_ICDICER0_SW11 (0x00000800uL)
+#define INTC_ICDICER0_SW12 (0x00001000uL)
+#define INTC_ICDICER0_SW13 (0x00002000uL)
+#define INTC_ICDICER0_SW14 (0x00004000uL)
+#define INTC_ICDICER0_SW15 (0x00008000uL)
+#define INTC_ICDICER0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDICER0_COMMRX0 (0x00020000uL)
+#define INTC_ICDICER0_COMMTX0 (0x00040000uL)
+#define INTC_ICDICER0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDICER1_IRQ0 (0x00000001uL)
+#define INTC_ICDICER1_IRQ1 (0x00000002uL)
+#define INTC_ICDICER1_IRQ2 (0x00000004uL)
+#define INTC_ICDICER1_IRQ3 (0x00000008uL)
+#define INTC_ICDICER1_IRQ4 (0x00000010uL)
+#define INTC_ICDICER1_IRQ5 (0x00000020uL)
+#define INTC_ICDICER1_IRQ6 (0x00000040uL)
+#define INTC_ICDICER1_IRQ7 (0x00000080uL)
+#define INTC_ICDICER1_PL310ERR (0x00000100uL)
+#define INTC_ICDICER1_DMAINT0 (0x00000200uL)
+#define INTC_ICDICER1_DMAINT1 (0x00000400uL)
+#define INTC_ICDICER1_DMAINT2 (0x00000800uL)
+#define INTC_ICDICER1_DMAINT3 (0x00001000uL)
+#define INTC_ICDICER1_DMAINT4 (0x00002000uL)
+#define INTC_ICDICER1_DMAINT5 (0x00004000uL)
+#define INTC_ICDICER1_DMAINT6 (0x00008000uL)
+#define INTC_ICDICER1_DMAINT7 (0x00010000uL)
+#define INTC_ICDICER1_DMAINT8 (0x00020000uL)
+#define INTC_ICDICER1_DMAINT9 (0x00040000uL)
+#define INTC_ICDICER1_DMAINT10 (0x00080000uL)
+#define INTC_ICDICER1_DMAINT11 (0x00100000uL)
+#define INTC_ICDICER1_DMAINT12 (0x00200000uL)
+#define INTC_ICDICER1_DMAINT13 (0x00400000uL)
+#define INTC_ICDICER1_DMAINT14 (0x00800000uL)
+#define INTC_ICDICER1_DMAINT15 (0x01000000uL)
+#define INTC_ICDICER1_DMAERR (0x02000000uL)
+
+#define INTC_ICDICER2_USBI0 (0x00000200uL)
+#define INTC_ICDICER2_USBI1 (0x00000400uL)
+#define INTC_ICDICER2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDICER2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDICER2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDICER2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDICER2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDICER2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDICER2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDICER2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDICER2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDICER2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDICER2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDICER2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDICER2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDICER2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDICER2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDICER2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDICER2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDICER2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDICER2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDICER2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDICER2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDICER3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDICER3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDICER3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDICER3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDICER3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDICER3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDICER3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDICER3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDICER3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDICER3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDICER3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDICER3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDICER3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDICER3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDICER3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDICER3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDICER3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDICER3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDICER3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDICER3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDICER3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDICER3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDICER3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDICER3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDICER3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDICER3_IMRDI (0x08000000uL)
+#define INTC_ICDICER3_IMR2I0 (0x10000000uL)
+#define INTC_ICDICER3_IMR2I1 (0x20000000uL)
+#define INTC_ICDICER3_JEDI (0x40000000uL)
+#define INTC_ICDICER3_JDTI (0x80000000uL)
+
+#define INTC_ICDICER4_CMP0 (0x00000001uL)
+#define INTC_ICDICER4_CMP1 (0x00000002uL)
+#define INTC_ICDICER4_INT0 (0x00000004uL)
+#define INTC_ICDICER4_INT1 (0x00000008uL)
+#define INTC_ICDICER4_INT2 (0x00000010uL)
+#define INTC_ICDICER4_INT3 (0x00000020uL)
+#define INTC_ICDICER4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDICER4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDICER4_CMI (0x00000100uL)
+#define INTC_ICDICER4_WTOUT (0x00000200uL)
+#define INTC_ICDICER4_ITI (0x00000400uL)
+#define INTC_ICDICER4_TGI0A (0x00000800uL)
+#define INTC_ICDICER4_TGI0B (0x00001000uL)
+#define INTC_ICDICER4_TGI0C (0x00002000uL)
+#define INTC_ICDICER4_TGI0D (0x00004000uL)
+#define INTC_ICDICER4_TGI0V (0x00008000uL)
+#define INTC_ICDICER4_TGI0E (0x00010000uL)
+#define INTC_ICDICER4_TGI0F (0x00020000uL)
+#define INTC_ICDICER4_TGI1A (0x00040000uL)
+#define INTC_ICDICER4_TGI1B (0x00080000uL)
+#define INTC_ICDICER4_TGI1V (0x00100000uL)
+#define INTC_ICDICER4_TGI1U (0x00200000uL)
+#define INTC_ICDICER4_TGI2A (0x00400000uL)
+#define INTC_ICDICER4_TGI2B (0x00800000uL)
+#define INTC_ICDICER4_TGI2V (0x01000000uL)
+#define INTC_ICDICER4_TGI2U (0x02000000uL)
+#define INTC_ICDICER4_TGI3A (0x04000000uL)
+#define INTC_ICDICER4_TGI3B (0x08000000uL)
+#define INTC_ICDICER4_TGI3C (0x10000000uL)
+#define INTC_ICDICER4_TGI3D (0x20000000uL)
+#define INTC_ICDICER4_TGI3V (0x40000000uL)
+#define INTC_ICDICER4_TGI4A (0x80000000uL)
+
+#define INTC_ICDICER5_TGI4B (0x00000001uL)
+#define INTC_ICDICER5_TGI4C (0x00000002uL)
+#define INTC_ICDICER5_TGI4D (0x00000004uL)
+#define INTC_ICDICER5_TGI4V (0x00000008uL)
+#define INTC_ICDICER5_CMI1 (0x00000010uL)
+#define INTC_ICDICER5_CMI2 (0x00000020uL)
+#define INTC_ICDICER5_SGDEI0 (0x00000040uL)
+#define INTC_ICDICER5_SGDEI1 (0x00000080uL)
+#define INTC_ICDICER5_SGDEI2 (0x00000100uL)
+#define INTC_ICDICER5_SGDEI3 (0x00000200uL)
+#define INTC_ICDICER5_ADI (0x00000400uL)
+#define INTC_ICDICER5_LMTI (0x00000800uL)
+#define INTC_ICDICER5_SSII0 (0x00001000uL)
+#define INTC_ICDICER5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDICER5_SSITXI0 (0x00004000uL)
+#define INTC_ICDICER5_SSII1 (0x00008000uL)
+#define INTC_ICDICER5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDICER5_SSITXI1 (0x00020000uL)
+#define INTC_ICDICER5_SSII2 (0x00040000uL)
+#define INTC_ICDICER5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDICER5_SSII3 (0x00100000uL)
+#define INTC_ICDICER5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDICER5_SSITXI3 (0x00400000uL)
+#define INTC_ICDICER5_SSII4 (0x00800000uL)
+#define INTC_ICDICER5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDICER5_SSII5 (0x02000000uL)
+#define INTC_ICDICER5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDICER5_SSITXI5 (0x08000000uL)
+#define INTC_ICDICER5_SPDIFI (0x10000000uL)
+#define INTC_ICDICER5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDICER5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDICER5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDICER6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDICER6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDICER6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDICER6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDICER6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDICER6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDICER6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDICER6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDICER6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDICER6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDICER6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDICER6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDICER6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDICER6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDICER6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDICER6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDICER6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDICER6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDICER6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDICER6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDICER6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDICER6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDICER6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDICER6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDICER6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDICER6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDICER6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDICER6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDICER6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDICER6_BRI0 (0x20000000uL)
+#define INTC_ICDICER6_ERI0 (0x40000000uL)
+#define INTC_ICDICER6_RXI0 (0x80000000uL)
+
+#define INTC_ICDICER7_TXI0 (0x00000001uL)
+#define INTC_ICDICER7_BRI1 (0x00000002uL)
+#define INTC_ICDICER7_ERI1 (0x00000004uL)
+#define INTC_ICDICER7_RXI1 (0x00000008uL)
+#define INTC_ICDICER7_TXI1 (0x00000010uL)
+#define INTC_ICDICER7_BRI2 (0x00000020uL)
+#define INTC_ICDICER7_ERI2 (0x00000040uL)
+#define INTC_ICDICER7_RXI2 (0x00000080uL)
+#define INTC_ICDICER7_TXI2 (0x00000100uL)
+#define INTC_ICDICER7_BRI3 (0x00000200uL)
+#define INTC_ICDICER7_ERI3 (0x00000400uL)
+#define INTC_ICDICER7_RXI3 (0x00000800uL)
+#define INTC_ICDICER7_TXI3 (0x00001000uL)
+#define INTC_ICDICER7_BRI4 (0x00002000uL)
+#define INTC_ICDICER7_ERI4 (0x00004000uL)
+#define INTC_ICDICER7_RXI4 (0x00008000uL)
+#define INTC_ICDICER7_TXI4 (0x00010000uL)
+#define INTC_ICDICER7_BRI5 (0x00020000uL)
+#define INTC_ICDICER7_ERI5 (0x00040000uL)
+#define INTC_ICDICER7_RXI5 (0x00080000uL)
+#define INTC_ICDICER7_TXI5 (0x00100000uL)
+#define INTC_ICDICER7_BRI6 (0x00200000uL)
+#define INTC_ICDICER7_ERI6 (0x00400000uL)
+#define INTC_ICDICER7_RXI6 (0x00800000uL)
+#define INTC_ICDICER7_TXI6 (0x01000000uL)
+#define INTC_ICDICER7_BRI7 (0x02000000uL)
+#define INTC_ICDICER7_ERI7 (0x04000000uL)
+#define INTC_ICDICER7_RXI7 (0x08000000uL)
+#define INTC_ICDICER7_TXI7 (0x10000000uL)
+#define INTC_ICDICER7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDICER7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDICER7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDICER8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDICER8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDICER8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDICER8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDICER8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDICER8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDICER8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDICER8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDICER8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDICER8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDICER8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDICER8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDICER8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDICER8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDICER8_SPEI0 (0x00004000uL)
+#define INTC_ICDICER8_SPRI0 (0x00008000uL)
+#define INTC_ICDICER8_SPTI0 (0x00010000uL)
+#define INTC_ICDICER8_SPEI1 (0x00020000uL)
+#define INTC_ICDICER8_SPRI1 (0x00040000uL)
+#define INTC_ICDICER8_SPTI1 (0x00080000uL)
+#define INTC_ICDICER8_SPEI2 (0x00100000uL)
+#define INTC_ICDICER8_SPRI2 (0x00200000uL)
+#define INTC_ICDICER8_SPTI2 (0x00400000uL)
+#define INTC_ICDICER8_SPEI3 (0x00800000uL)
+#define INTC_ICDICER8_SPRI3 (0x01000000uL)
+#define INTC_ICDICER8_SPTI3 (0x02000000uL)
+#define INTC_ICDICER8_SPEI4 (0x04000000uL)
+#define INTC_ICDICER8_SPRI4 (0x08000000uL)
+#define INTC_ICDICER8_SPTI4 (0x10000000uL)
+#define INTC_ICDICER8_IEBBTD (0x20000000uL)
+#define INTC_ICDICER8_IEBBTERR (0x40000000uL)
+#define INTC_ICDICER8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDICER9_IEBBTV (0x00000001uL)
+#define INTC_ICDICER9_ISY (0x00000002uL)
+#define INTC_ICDICER9_IERR (0x00000004uL)
+#define INTC_ICDICER9_ITARG (0x00000008uL)
+#define INTC_ICDICER9_ISEC (0x00000010uL)
+#define INTC_ICDICER9_IBUF (0x00000020uL)
+#define INTC_ICDICER9_IREADY (0x00000040uL)
+#define INTC_ICDICER9_FLSTE (0x00000080uL)
+#define INTC_ICDICER9_FLTENDI (0x00000100uL)
+#define INTC_ICDICER9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDICER9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDICER9_MMC0 (0x00000800uL)
+#define INTC_ICDICER9_MMC1 (0x00001000uL)
+#define INTC_ICDICER9_MMC2 (0x00002000uL)
+#define INTC_ICDICER9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDICER9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDICER9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDICER9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDICER9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDICER9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDICER9_ARM (0x00100000uL)
+#define INTC_ICDICER9_PRD (0x00200000uL)
+#define INTC_ICDICER9_CUP (0x00400000uL)
+#define INTC_ICDICER9_SCUAI0 (0x00800000uL)
+#define INTC_ICDICER9_SCUAI1 (0x01000000uL)
+#define INTC_ICDICER9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDICER9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDICER9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDICER9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDICER9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDICER9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDICER9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDICER10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDICER10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDICER10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDICER10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDICER10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDICER10_MLB_CINT (0x00000020uL)
+#define INTC_ICDICER10_MLB_SINT (0x00000040uL)
+#define INTC_ICDICER10_DRC0 (0x00000080uL)
+#define INTC_ICDICER10_DRC1 (0x00000100uL)
+#define INTC_ICDICER10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDICER10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDICER10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDICER10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDICER10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDICER10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDICER10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDICER10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDICER10_ERI0 (0x08000000uL)
+#define INTC_ICDICER10_RXI0 (0x10000000uL)
+#define INTC_ICDICER10_TXI0 (0x20000000uL)
+#define INTC_ICDICER10_TEI0 (0x40000000uL)
+#define INTC_ICDICER10_ERI1 (0x80000000uL)
+
+#define INTC_ICDICER11_RXI1 (0x00000001uL)
+#define INTC_ICDICER11_TXI1 (0x00000002uL)
+#define INTC_ICDICER11_TEI1 (0x00000004uL)
+#define INTC_ICDICER11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDICER11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDICER11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDICER11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDICER11_ETHERI (0x00000080uL)
+#define INTC_ICDICER11_CEUI (0x00001000uL)
+#define INTC_ICDICER11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDICER11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDICER11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDICER12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDICER12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDICER12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDICER12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDICER12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDICER12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDICER12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDICER12_PRRI (0x00000100uL)
+#define INTC_ICDICER12_IFEI0 (0x00000200uL)
+#define INTC_ICDICER12_OFFI0 (0x00000400uL)
+#define INTC_ICDICER12_PFVEI0 (0x00000800uL)
+#define INTC_ICDICER12_IFEI1 (0x00001000uL)
+#define INTC_ICDICER12_OFFI1 (0x00002000uL)
+#define INTC_ICDICER12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDICER13_TINT0 (0x00000001uL)
+#define INTC_ICDICER13_TINT1 (0x00000002uL)
+#define INTC_ICDICER13_TINT2 (0x00000004uL)
+#define INTC_ICDICER13_TINT3 (0x00000008uL)
+#define INTC_ICDICER13_TINT4 (0x00000010uL)
+#define INTC_ICDICER13_TINT5 (0x00000020uL)
+#define INTC_ICDICER13_TINT6 (0x00000040uL)
+#define INTC_ICDICER13_TINT7 (0x00000080uL)
+#define INTC_ICDICER13_TINT8 (0x00000100uL)
+#define INTC_ICDICER13_TINT9 (0x00000200uL)
+#define INTC_ICDICER13_TINT10 (0x00000400uL)
+#define INTC_ICDICER13_TINT11 (0x00000800uL)
+#define INTC_ICDICER13_TINT12 (0x00001000uL)
+#define INTC_ICDICER13_TINT13 (0x00002000uL)
+#define INTC_ICDICER13_TINT14 (0x00004000uL)
+#define INTC_ICDICER13_TINT15 (0x00008000uL)
+#define INTC_ICDICER13_TINT16 (0x00010000uL)
+#define INTC_ICDICER13_TINT17 (0x00020000uL)
+#define INTC_ICDICER13_TINT18 (0x00040000uL)
+#define INTC_ICDICER13_TINT19 (0x00080000uL)
+#define INTC_ICDICER13_TINT20 (0x00100000uL)
+#define INTC_ICDICER13_TINT21 (0x00200000uL)
+#define INTC_ICDICER13_TINT22 (0x00400000uL)
+#define INTC_ICDICER13_TINT23 (0x00800000uL)
+#define INTC_ICDICER13_TINT24 (0x01000000uL)
+#define INTC_ICDICER13_TINT25 (0x02000000uL)
+#define INTC_ICDICER13_TINT26 (0x04000000uL)
+#define INTC_ICDICER13_TINT27 (0x08000000uL)
+#define INTC_ICDICER13_TINT28 (0x10000000uL)
+#define INTC_ICDICER13_TINT29 (0x20000000uL)
+#define INTC_ICDICER13_TINT30 (0x40000000uL)
+#define INTC_ICDICER13_TINT31 (0x80000000uL)
+
+#define INTC_ICDICER14_TINT32 (0x00000001uL)
+#define INTC_ICDICER14_TINT33 (0x00000002uL)
+#define INTC_ICDICER14_TINT34 (0x00000004uL)
+#define INTC_ICDICER14_TINT35 (0x00000008uL)
+#define INTC_ICDICER14_TINT36 (0x00000010uL)
+#define INTC_ICDICER14_TINT37 (0x00000020uL)
+#define INTC_ICDICER14_TINT38 (0x00000040uL)
+#define INTC_ICDICER14_TINT39 (0x00000080uL)
+#define INTC_ICDICER14_TINT40 (0x00000100uL)
+#define INTC_ICDICER14_TINT41 (0x00000200uL)
+#define INTC_ICDICER14_TINT42 (0x00000400uL)
+#define INTC_ICDICER14_TINT43 (0x00000800uL)
+#define INTC_ICDICER14_TINT44 (0x00001000uL)
+#define INTC_ICDICER14_TINT45 (0x00002000uL)
+#define INTC_ICDICER14_TINT46 (0x00004000uL)
+#define INTC_ICDICER14_TINT47 (0x00008000uL)
+#define INTC_ICDICER14_TINT48 (0x00010000uL)
+#define INTC_ICDICER14_TINT49 (0x00020000uL)
+#define INTC_ICDICER14_TINT50 (0x00040000uL)
+#define INTC_ICDICER14_TINT51 (0x00080000uL)
+#define INTC_ICDICER14_TINT52 (0x00100000uL)
+#define INTC_ICDICER14_TINT53 (0x00200000uL)
+#define INTC_ICDICER14_TINT54 (0x00400000uL)
+#define INTC_ICDICER14_TINT55 (0x00800000uL)
+#define INTC_ICDICER14_TINT56 (0x01000000uL)
+#define INTC_ICDICER14_TINT57 (0x02000000uL)
+#define INTC_ICDICER14_TINT58 (0x04000000uL)
+#define INTC_ICDICER14_TINT59 (0x08000000uL)
+#define INTC_ICDICER14_TINT60 (0x10000000uL)
+#define INTC_ICDICER14_TINT61 (0x20000000uL)
+#define INTC_ICDICER14_TINT62 (0x40000000uL)
+#define INTC_ICDICER14_TINT63 (0x80000000uL)
+
+#define INTC_ICDICER15_TINT64 (0x00000001uL)
+#define INTC_ICDICER15_TINT65 (0x00000002uL)
+#define INTC_ICDICER15_TINT66 (0x00000004uL)
+#define INTC_ICDICER15_TINT67 (0x00000008uL)
+#define INTC_ICDICER15_TINT68 (0x00000010uL)
+#define INTC_ICDICER15_TINT69 (0x00000020uL)
+#define INTC_ICDICER15_TINT70 (0x00000040uL)
+#define INTC_ICDICER15_TINT71 (0x00000080uL)
+#define INTC_ICDICER15_TINT72 (0x00000100uL)
+#define INTC_ICDICER15_TINT73 (0x00000200uL)
+#define INTC_ICDICER15_TINT74 (0x00000400uL)
+#define INTC_ICDICER15_TINT75 (0x00000800uL)
+#define INTC_ICDICER15_TINT76 (0x00001000uL)
+#define INTC_ICDICER15_TINT77 (0x00002000uL)
+#define INTC_ICDICER15_TINT78 (0x00004000uL)
+#define INTC_ICDICER15_TINT79 (0x00008000uL)
+#define INTC_ICDICER15_TINT80 (0x00010000uL)
+#define INTC_ICDICER15_TINT81 (0x00020000uL)
+#define INTC_ICDICER15_TINT82 (0x00040000uL)
+#define INTC_ICDICER15_TINT83 (0x00080000uL)
+#define INTC_ICDICER15_TINT84 (0x00100000uL)
+#define INTC_ICDICER15_TINT85 (0x00200000uL)
+#define INTC_ICDICER15_TINT86 (0x00400000uL)
+#define INTC_ICDICER15_TINT87 (0x00800000uL)
+#define INTC_ICDICER15_TINT88 (0x01000000uL)
+#define INTC_ICDICER15_TINT89 (0x02000000uL)
+#define INTC_ICDICER15_TINT90 (0x04000000uL)
+#define INTC_ICDICER15_TINT91 (0x08000000uL)
+#define INTC_ICDICER15_TINT92 (0x10000000uL)
+#define INTC_ICDICER15_TINT93 (0x20000000uL)
+#define INTC_ICDICER15_TINT94 (0x40000000uL)
+#define INTC_ICDICER15_TINT95 (0x80000000uL)
+
+#define INTC_ICDICER16_TINT96 (0x00000001uL)
+#define INTC_ICDICER16_TINT97 (0x00000002uL)
+#define INTC_ICDICER16_TINT98 (0x00000004uL)
+#define INTC_ICDICER16_TINT99 (0x00000008uL)
+#define INTC_ICDICER16_TINT100 (0x00000010uL)
+#define INTC_ICDICER16_TINT101 (0x00000020uL)
+#define INTC_ICDICER16_TINT102 (0x00000040uL)
+#define INTC_ICDICER16_TINT103 (0x00000080uL)
+#define INTC_ICDICER16_TINT104 (0x00000100uL)
+#define INTC_ICDICER16_TINT105 (0x00000200uL)
+#define INTC_ICDICER16_TINT106 (0x00000400uL)
+#define INTC_ICDICER16_TINT107 (0x00000800uL)
+#define INTC_ICDICER16_TINT108 (0x00001000uL)
+#define INTC_ICDICER16_TINT109 (0x00002000uL)
+#define INTC_ICDICER16_TINT110 (0x00004000uL)
+#define INTC_ICDICER16_TINT111 (0x00008000uL)
+#define INTC_ICDICER16_TINT112 (0x00010000uL)
+#define INTC_ICDICER16_TINT113 (0x00020000uL)
+#define INTC_ICDICER16_TINT114 (0x00040000uL)
+#define INTC_ICDICER16_TINT115 (0x00080000uL)
+#define INTC_ICDICER16_TINT116 (0x00100000uL)
+#define INTC_ICDICER16_TINT117 (0x00200000uL)
+#define INTC_ICDICER16_TINT118 (0x00400000uL)
+#define INTC_ICDICER16_TINT119 (0x00800000uL)
+#define INTC_ICDICER16_TINT120 (0x01000000uL)
+#define INTC_ICDICER16_TINT121 (0x02000000uL)
+#define INTC_ICDICER16_TINT122 (0x04000000uL)
+#define INTC_ICDICER16_TINT123 (0x08000000uL)
+#define INTC_ICDICER16_TINT124 (0x10000000uL)
+#define INTC_ICDICER16_TINT125 (0x20000000uL)
+#define INTC_ICDICER16_TINT126 (0x40000000uL)
+#define INTC_ICDICER16_TINT127 (0x80000000uL)
+
+#define INTC_ICDICER17_TINT128 (0x00000001uL)
+#define INTC_ICDICER17_TINT129 (0x00000002uL)
+#define INTC_ICDICER17_TINT130 (0x00000004uL)
+#define INTC_ICDICER17_TINT131 (0x00000008uL)
+#define INTC_ICDICER17_TINT132 (0x00000010uL)
+#define INTC_ICDICER17_TINT133 (0x00000020uL)
+#define INTC_ICDICER17_TINT134 (0x00000040uL)
+#define INTC_ICDICER17_TINT135 (0x00000080uL)
+#define INTC_ICDICER17_TINT136 (0x00000100uL)
+#define INTC_ICDICER17_TINT137 (0x00000200uL)
+#define INTC_ICDICER17_TINT138 (0x00000400uL)
+#define INTC_ICDICER17_TINT139 (0x00000800uL)
+#define INTC_ICDICER17_TINT140 (0x00001000uL)
+#define INTC_ICDICER17_TINT141 (0x00002000uL)
+#define INTC_ICDICER17_TINT142 (0x00004000uL)
+#define INTC_ICDICER17_TINT143 (0x00008000uL)
+#define INTC_ICDICER17_TINT144 (0x00010000uL)
+#define INTC_ICDICER17_TINT145 (0x00020000uL)
+#define INTC_ICDICER17_TINT146 (0x00040000uL)
+#define INTC_ICDICER17_TINT147 (0x00080000uL)
+#define INTC_ICDICER17_TINT148 (0x00100000uL)
+#define INTC_ICDICER17_TINT149 (0x00200000uL)
+#define INTC_ICDICER17_TINT150 (0x00400000uL)
+#define INTC_ICDICER17_TINT151 (0x00800000uL)
+#define INTC_ICDICER17_TINT152 (0x01000000uL)
+#define INTC_ICDICER17_TINT153 (0x02000000uL)
+#define INTC_ICDICER17_TINT154 (0x04000000uL)
+#define INTC_ICDICER17_TINT155 (0x08000000uL)
+#define INTC_ICDICER17_TINT156 (0x10000000uL)
+#define INTC_ICDICER17_TINT157 (0x20000000uL)
+#define INTC_ICDICER17_TINT158 (0x40000000uL)
+#define INTC_ICDICER17_TINT159 (0x80000000uL)
+
+#define INTC_ICDICER18_TINT160 (0x00000001uL)
+#define INTC_ICDICER18_TINT161 (0x00000002uL)
+#define INTC_ICDICER18_TINT162 (0x00000004uL)
+#define INTC_ICDICER18_TINT163 (0x00000008uL)
+#define INTC_ICDICER18_TINT164 (0x00000010uL)
+#define INTC_ICDICER18_TINT165 (0x00000020uL)
+#define INTC_ICDICER18_TINT166 (0x00000040uL)
+#define INTC_ICDICER18_TINT167 (0x00000080uL)
+#define INTC_ICDICER18_TINT168 (0x00000100uL)
+#define INTC_ICDICER18_TINT169 (0x00000200uL)
+#define INTC_ICDICER18_TINT170 (0x00000400uL)
+
+#define INTC_ICDISPR0_SW0 (0x00000001uL)
+#define INTC_ICDISPR0_SW1 (0x00000002uL)
+#define INTC_ICDISPR0_SW2 (0x00000004uL)
+#define INTC_ICDISPR0_SW3 (0x00000008uL)
+#define INTC_ICDISPR0_SW4 (0x00000010uL)
+#define INTC_ICDISPR0_SW5 (0x00000020uL)
+#define INTC_ICDISPR0_SW6 (0x00000040uL)
+#define INTC_ICDISPR0_SW7 (0x00000080uL)
+#define INTC_ICDISPR0_SW8 (0x00000100uL)
+#define INTC_ICDISPR0_SW9 (0x00000200uL)
+#define INTC_ICDISPR0_SW10 (0x00000400uL)
+#define INTC_ICDISPR0_SW11 (0x00000800uL)
+#define INTC_ICDISPR0_SW12 (0x00001000uL)
+#define INTC_ICDISPR0_SW13 (0x00002000uL)
+#define INTC_ICDISPR0_SW14 (0x00004000uL)
+#define INTC_ICDISPR0_SW15 (0x00008000uL)
+#define INTC_ICDISPR0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDISPR0_COMMRX0 (0x00020000uL)
+#define INTC_ICDISPR0_COMMTX0 (0x00040000uL)
+#define INTC_ICDISPR0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDISPR1_IRQ0 (0x00000001uL)
+#define INTC_ICDISPR1_IRQ1 (0x00000002uL)
+#define INTC_ICDISPR1_IRQ2 (0x00000004uL)
+#define INTC_ICDISPR1_IRQ3 (0x00000008uL)
+#define INTC_ICDISPR1_IRQ4 (0x00000010uL)
+#define INTC_ICDISPR1_IRQ5 (0x00000020uL)
+#define INTC_ICDISPR1_IRQ6 (0x00000040uL)
+#define INTC_ICDISPR1_IRQ7 (0x00000080uL)
+#define INTC_ICDISPR1_PL310ERR (0x00000100uL)
+#define INTC_ICDISPR1_DMAINT0 (0x00000200uL)
+#define INTC_ICDISPR1_DMAINT1 (0x00000400uL)
+#define INTC_ICDISPR1_DMAINT2 (0x00000800uL)
+#define INTC_ICDISPR1_DMAINT3 (0x00001000uL)
+#define INTC_ICDISPR1_DMAINT4 (0x00002000uL)
+#define INTC_ICDISPR1_DMAINT5 (0x00004000uL)
+#define INTC_ICDISPR1_DMAINT6 (0x00008000uL)
+#define INTC_ICDISPR1_DMAINT7 (0x00010000uL)
+#define INTC_ICDISPR1_DMAINT8 (0x00020000uL)
+#define INTC_ICDISPR1_DMAINT9 (0x00040000uL)
+#define INTC_ICDISPR1_DMAINT10 (0x00080000uL)
+#define INTC_ICDISPR1_DMAINT11 (0x00100000uL)
+#define INTC_ICDISPR1_DMAINT12 (0x00200000uL)
+#define INTC_ICDISPR1_DMAINT13 (0x00400000uL)
+#define INTC_ICDISPR1_DMAINT14 (0x00800000uL)
+#define INTC_ICDISPR1_DMAINT15 (0x01000000uL)
+#define INTC_ICDISPR1_DMAERR (0x02000000uL)
+
+#define INTC_ICDISPR2_USBI0 (0x00000200uL)
+#define INTC_ICDISPR2_USBI1 (0x00000400uL)
+#define INTC_ICDISPR2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDISPR2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDISPR2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDISPR2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDISPR2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDISPR2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDISPR2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDISPR2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDISPR2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDISPR2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDISPR2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDISPR2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDISPR2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDISPR2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDISPR2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDISPR2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDISPR2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDISPR2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDISPR2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDISPR3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDISPR3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDISPR3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDISPR3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDISPR3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDISPR3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDISPR3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDISPR3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDISPR3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDISPR3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDISPR3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDISPR3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDISPR3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDISPR3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDISPR3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDISPR3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDISPR3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDISPR3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDISPR3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDISPR3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDISPR3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDISPR3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDISPR3_IMRDI (0x08000000uL)
+#define INTC_ICDISPR3_IMR2I0 (0x10000000uL)
+#define INTC_ICDISPR3_IMR2I1 (0x20000000uL)
+#define INTC_ICDISPR3_JEDI (0x40000000uL)
+#define INTC_ICDISPR3_JDTI (0x80000000uL)
+
+#define INTC_ICDISPR4_CMP0 (0x00000001uL)
+#define INTC_ICDISPR4_CMP1 (0x00000002uL)
+#define INTC_ICDISPR4_INT0 (0x00000004uL)
+#define INTC_ICDISPR4_INT1 (0x00000008uL)
+#define INTC_ICDISPR4_INT2 (0x00000010uL)
+#define INTC_ICDISPR4_INT3 (0x00000020uL)
+#define INTC_ICDISPR4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDISPR4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDISPR4_CMI (0x00000100uL)
+#define INTC_ICDISPR4_WTOUT (0x00000200uL)
+#define INTC_ICDISPR4_ITI (0x00000400uL)
+#define INTC_ICDISPR4_TGI0A (0x00000800uL)
+#define INTC_ICDISPR4_TGI0B (0x00001000uL)
+#define INTC_ICDISPR4_TGI0C (0x00002000uL)
+#define INTC_ICDISPR4_TGI0D (0x00004000uL)
+#define INTC_ICDISPR4_TGI0V (0x00008000uL)
+#define INTC_ICDISPR4_TGI0E (0x00010000uL)
+#define INTC_ICDISPR4_TGI0F (0x00020000uL)
+#define INTC_ICDISPR4_TGI1A (0x00040000uL)
+#define INTC_ICDISPR4_TGI1B (0x00080000uL)
+#define INTC_ICDISPR4_TGI1V (0x00100000uL)
+#define INTC_ICDISPR4_TGI1U (0x00200000uL)
+#define INTC_ICDISPR4_TGI2A (0x00400000uL)
+#define INTC_ICDISPR4_TGI2B (0x00800000uL)
+#define INTC_ICDISPR4_TGI2V (0x01000000uL)
+#define INTC_ICDISPR4_TGI2U (0x02000000uL)
+#define INTC_ICDISPR4_TGI3A (0x04000000uL)
+#define INTC_ICDISPR4_TGI3B (0x08000000uL)
+#define INTC_ICDISPR4_TGI3C (0x10000000uL)
+#define INTC_ICDISPR4_TGI3D (0x20000000uL)
+#define INTC_ICDISPR4_TGI3V (0x40000000uL)
+#define INTC_ICDISPR4_TGI4A (0x80000000uL)
+
+#define INTC_ICDISPR5_TGI4B (0x00000001uL)
+#define INTC_ICDISPR5_TGI4C (0x00000002uL)
+#define INTC_ICDISPR5_TGI4D (0x00000004uL)
+#define INTC_ICDISPR5_TGI4V (0x00000008uL)
+#define INTC_ICDISPR5_CMI1 (0x00000010uL)
+#define INTC_ICDISPR5_CMI2 (0x00000020uL)
+#define INTC_ICDISPR5_SGDEI0 (0x00000040uL)
+#define INTC_ICDISPR5_SGDEI1 (0x00000080uL)
+#define INTC_ICDISPR5_SGDEI2 (0x00000100uL)
+#define INTC_ICDISPR5_SGDEI3 (0x00000200uL)
+#define INTC_ICDISPR5_ADI (0x00000400uL)
+#define INTC_ICDISPR5_LMTI (0x00000800uL)
+#define INTC_ICDISPR5_SSII0 (0x00001000uL)
+#define INTC_ICDISPR5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDISPR5_SSITXI0 (0x00004000uL)
+#define INTC_ICDISPR5_SSII1 (0x00008000uL)
+#define INTC_ICDISPR5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDISPR5_SSITXI1 (0x00020000uL)
+#define INTC_ICDISPR5_SSII2 (0x00040000uL)
+#define INTC_ICDISPR5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDISPR5_SSII3 (0x00100000uL)
+#define INTC_ICDISPR5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDISPR5_SSITXI3 (0x00400000uL)
+#define INTC_ICDISPR5_SSII4 (0x00800000uL)
+#define INTC_ICDISPR5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDISPR5_SSII5 (0x02000000uL)
+#define INTC_ICDISPR5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDISPR5_SSITXI5 (0x08000000uL)
+#define INTC_ICDISPR5_SPDIFI (0x10000000uL)
+#define INTC_ICDISPR5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDISPR5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDISPR5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDISPR6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDISPR6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDISPR6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDISPR6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDISPR6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDISPR6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDISPR6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDISPR6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDISPR6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDISPR6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDISPR6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDISPR6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDISPR6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDISPR6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDISPR6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDISPR6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDISPR6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDISPR6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDISPR6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDISPR6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDISPR6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDISPR6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDISPR6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDISPR6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDISPR6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDISPR6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDISPR6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDISPR6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDISPR6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDISPR6_BRI0 (0x20000000uL)
+#define INTC_ICDISPR6_ERI0 (0x40000000uL)
+#define INTC_ICDISPR6_RXI0 (0x80000000uL)
+
+#define INTC_ICDISPR7_TXI0 (0x00000001uL)
+#define INTC_ICDISPR7_BRI1 (0x00000002uL)
+#define INTC_ICDISPR7_ERI1 (0x00000004uL)
+#define INTC_ICDISPR7_RXI1 (0x00000008uL)
+#define INTC_ICDISPR7_TXI1 (0x00000010uL)
+#define INTC_ICDISPR7_BRI2 (0x00000020uL)
+#define INTC_ICDISPR7_ERI2 (0x00000040uL)
+#define INTC_ICDISPR7_RXI2 (0x00000080uL)
+#define INTC_ICDISPR7_TXI2 (0x00000100uL)
+#define INTC_ICDISPR7_BRI3 (0x00000200uL)
+#define INTC_ICDISPR7_ERI3 (0x00000400uL)
+#define INTC_ICDISPR7_RXI3 (0x00000800uL)
+#define INTC_ICDISPR7_TXI3 (0x00001000uL)
+#define INTC_ICDISPR7_BRI4 (0x00002000uL)
+#define INTC_ICDISPR7_ERI4 (0x00004000uL)
+#define INTC_ICDISPR7_RXI4 (0x00008000uL)
+#define INTC_ICDISPR7_TXI4 (0x00010000uL)
+#define INTC_ICDISPR7_BRI5 (0x00020000uL)
+#define INTC_ICDISPR7_ERI5 (0x00040000uL)
+#define INTC_ICDISPR7_RXI5 (0x00080000uL)
+#define INTC_ICDISPR7_TXI5 (0x00100000uL)
+#define INTC_ICDISPR7_BRI6 (0x00200000uL)
+#define INTC_ICDISPR7_ERI6 (0x00400000uL)
+#define INTC_ICDISPR7_RXI6 (0x00800000uL)
+#define INTC_ICDISPR7_TXI6 (0x01000000uL)
+#define INTC_ICDISPR7_BRI7 (0x02000000uL)
+#define INTC_ICDISPR7_ERI7 (0x04000000uL)
+#define INTC_ICDISPR7_RXI7 (0x08000000uL)
+#define INTC_ICDISPR7_TXI7 (0x10000000uL)
+#define INTC_ICDISPR7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDISPR7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDISPR7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDISPR8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDISPR8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDISPR8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDISPR8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDISPR8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDISPR8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDISPR8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDISPR8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDISPR8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDISPR8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDISPR8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDISPR8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDISPR8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDISPR8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDISPR8_SPEI0 (0x00004000uL)
+#define INTC_ICDISPR8_SPRI0 (0x00008000uL)
+#define INTC_ICDISPR8_SPTI0 (0x00010000uL)
+#define INTC_ICDISPR8_SPEI1 (0x00020000uL)
+#define INTC_ICDISPR8_SPRI1 (0x00040000uL)
+#define INTC_ICDISPR8_SPTI1 (0x00080000uL)
+#define INTC_ICDISPR8_SPEI2 (0x00100000uL)
+#define INTC_ICDISPR8_SPRI2 (0x00200000uL)
+#define INTC_ICDISPR8_SPTI2 (0x00400000uL)
+#define INTC_ICDISPR8_SPEI3 (0x00800000uL)
+#define INTC_ICDISPR8_SPRI3 (0x01000000uL)
+#define INTC_ICDISPR8_SPTI3 (0x02000000uL)
+#define INTC_ICDISPR8_SPEI4 (0x04000000uL)
+#define INTC_ICDISPR8_SPRI4 (0x08000000uL)
+#define INTC_ICDISPR8_SPTI4 (0x10000000uL)
+#define INTC_ICDISPR8_IEBBTD (0x20000000uL)
+#define INTC_ICDISPR8_IEBBTERR (0x40000000uL)
+#define INTC_ICDISPR8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDISPR9_IEBBTV (0x00000001uL)
+#define INTC_ICDISPR9_ISY (0x00000002uL)
+#define INTC_ICDISPR9_IERR (0x00000004uL)
+#define INTC_ICDISPR9_ITARG (0x00000008uL)
+#define INTC_ICDISPR9_ISEC (0x00000010uL)
+#define INTC_ICDISPR9_IBUF (0x00000020uL)
+#define INTC_ICDISPR9_IREADY (0x00000040uL)
+#define INTC_ICDISPR9_FLSTE (0x00000080uL)
+#define INTC_ICDISPR9_FLTENDI (0x00000100uL)
+#define INTC_ICDISPR9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDISPR9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDISPR9_MMC0 (0x00000800uL)
+#define INTC_ICDISPR9_MMC1 (0x00001000uL)
+#define INTC_ICDISPR9_MMC2 (0x00002000uL)
+#define INTC_ICDISPR9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDISPR9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDISPR9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDISPR9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDISPR9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDISPR9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDISPR9_ARM (0x00100000uL)
+#define INTC_ICDISPR9_PRD (0x00200000uL)
+#define INTC_ICDISPR9_CUP (0x00400000uL)
+#define INTC_ICDISPR9_SCUAI0 (0x00800000uL)
+#define INTC_ICDISPR9_SCUAI1 (0x01000000uL)
+#define INTC_ICDISPR9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDISPR9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDISPR9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDISPR9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDISPR9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDISPR9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDISPR9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDISPR10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDISPR10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDISPR10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDISPR10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDISPR10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDISPR10_MLB_CINT (0x00000020uL)
+#define INTC_ICDISPR10_MLB_SINT (0x00000040uL)
+#define INTC_ICDISPR10_DRC0 (0x00000080uL)
+#define INTC_ICDISPR10_DRC1 (0x00000100uL)
+#define INTC_ICDISPR10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDISPR10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDISPR10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDISPR10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDISPR10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDISPR10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDISPR10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDISPR10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDISPR10_ERI0 (0x08000000uL)
+#define INTC_ICDISPR10_RXI0 (0x10000000uL)
+#define INTC_ICDISPR10_TXI0 (0x20000000uL)
+#define INTC_ICDISPR10_TEI0 (0x40000000uL)
+#define INTC_ICDISPR10_ERI1 (0x80000000uL)
+
+#define INTC_ICDISPR11_RXI1 (0x00000001uL)
+#define INTC_ICDISPR11_TXI1 (0x00000002uL)
+#define INTC_ICDISPR11_TEI1 (0x00000004uL)
+#define INTC_ICDISPR11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDISPR11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDISPR11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDISPR11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDISPR11_ETHERI (0x00000080uL)
+#define INTC_ICDISPR11_CEUI (0x00001000uL)
+#define INTC_ICDISPR11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDISPR11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDISPR12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDISPR12_PRRI (0x00000100uL)
+#define INTC_ICDISPR12_IFEI0 (0x00000200uL)
+#define INTC_ICDISPR12_OFFI0 (0x00000400uL)
+#define INTC_ICDISPR12_PFVEI0 (0x00000800uL)
+#define INTC_ICDISPR12_IFEI1 (0x00001000uL)
+#define INTC_ICDISPR12_OFFI1 (0x00002000uL)
+#define INTC_ICDISPR12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDISPR13_TINT0 (0x00000001uL)
+#define INTC_ICDISPR13_TINT1 (0x00000002uL)
+#define INTC_ICDISPR13_TINT2 (0x00000004uL)
+#define INTC_ICDISPR13_TINT3 (0x00000008uL)
+#define INTC_ICDISPR13_TINT4 (0x00000010uL)
+#define INTC_ICDISPR13_TINT5 (0x00000020uL)
+#define INTC_ICDISPR13_TINT6 (0x00000040uL)
+#define INTC_ICDISPR13_TINT7 (0x00000080uL)
+#define INTC_ICDISPR13_TINT8 (0x00000100uL)
+#define INTC_ICDISPR13_TINT9 (0x00000200uL)
+#define INTC_ICDISPR13_TINT10 (0x00000400uL)
+#define INTC_ICDISPR13_TINT11 (0x00000800uL)
+#define INTC_ICDISPR13_TINT12 (0x00001000uL)
+#define INTC_ICDISPR13_TINT13 (0x00002000uL)
+#define INTC_ICDISPR13_TINT14 (0x00004000uL)
+#define INTC_ICDISPR13_TINT15 (0x00008000uL)
+#define INTC_ICDISPR13_TINT16 (0x00010000uL)
+#define INTC_ICDISPR13_TINT17 (0x00020000uL)
+#define INTC_ICDISPR13_TINT18 (0x00040000uL)
+#define INTC_ICDISPR13_TINT19 (0x00080000uL)
+#define INTC_ICDISPR13_TINT20 (0x00100000uL)
+#define INTC_ICDISPR13_TINT21 (0x00200000uL)
+#define INTC_ICDISPR13_TINT22 (0x00400000uL)
+#define INTC_ICDISPR13_TINT23 (0x00800000uL)
+#define INTC_ICDISPR13_TINT24 (0x01000000uL)
+#define INTC_ICDISPR13_TINT25 (0x02000000uL)
+#define INTC_ICDISPR13_TINT26 (0x04000000uL)
+#define INTC_ICDISPR13_TINT27 (0x08000000uL)
+#define INTC_ICDISPR13_TINT28 (0x10000000uL)
+#define INTC_ICDISPR13_TINT29 (0x20000000uL)
+#define INTC_ICDISPR13_TINT30 (0x40000000uL)
+#define INTC_ICDISPR13_TINT31 (0x80000000uL)
+
+#define INTC_ICDISPR14_TINT32 (0x00000001uL)
+#define INTC_ICDISPR14_TINT33 (0x00000002uL)
+#define INTC_ICDISPR14_TINT34 (0x00000004uL)
+#define INTC_ICDISPR14_TINT35 (0x00000008uL)
+#define INTC_ICDISPR14_TINT36 (0x00000010uL)
+#define INTC_ICDISPR14_TINT37 (0x00000020uL)
+#define INTC_ICDISPR14_TINT38 (0x00000040uL)
+#define INTC_ICDISPR14_TINT39 (0x00000080uL)
+#define INTC_ICDISPR14_TINT40 (0x00000100uL)
+#define INTC_ICDISPR14_TINT41 (0x00000200uL)
+#define INTC_ICDISPR14_TINT42 (0x00000400uL)
+#define INTC_ICDISPR14_TINT43 (0x00000800uL)
+#define INTC_ICDISPR14_TINT44 (0x00001000uL)
+#define INTC_ICDISPR14_TINT45 (0x00002000uL)
+#define INTC_ICDISPR14_TINT46 (0x00004000uL)
+#define INTC_ICDISPR14_TINT47 (0x00008000uL)
+#define INTC_ICDISPR14_TINT48 (0x00010000uL)
+#define INTC_ICDISPR14_TINT49 (0x00020000uL)
+#define INTC_ICDISPR14_TINT50 (0x00040000uL)
+#define INTC_ICDISPR14_TINT51 (0x00080000uL)
+#define INTC_ICDISPR14_TINT52 (0x00100000uL)
+#define INTC_ICDISPR14_TINT53 (0x00200000uL)
+#define INTC_ICDISPR14_TINT54 (0x00400000uL)
+#define INTC_ICDISPR14_TINT55 (0x00800000uL)
+#define INTC_ICDISPR14_TINT56 (0x01000000uL)
+#define INTC_ICDISPR14_TINT57 (0x02000000uL)
+#define INTC_ICDISPR14_TINT58 (0x04000000uL)
+#define INTC_ICDISPR14_TINT59 (0x08000000uL)
+#define INTC_ICDISPR14_TINT60 (0x10000000uL)
+#define INTC_ICDISPR14_TINT61 (0x20000000uL)
+#define INTC_ICDISPR14_TINT62 (0x40000000uL)
+#define INTC_ICDISPR14_TINT63 (0x80000000uL)
+
+#define INTC_ICDISPR15_TINT64 (0x00000001uL)
+#define INTC_ICDISPR15_TINT65 (0x00000002uL)
+#define INTC_ICDISPR15_TINT66 (0x00000004uL)
+#define INTC_ICDISPR15_TINT67 (0x00000008uL)
+#define INTC_ICDISPR15_TINT68 (0x00000010uL)
+#define INTC_ICDISPR15_TINT69 (0x00000020uL)
+#define INTC_ICDISPR15_TINT70 (0x00000040uL)
+#define INTC_ICDISPR15_TINT71 (0x00000080uL)
+#define INTC_ICDISPR15_TINT72 (0x00000100uL)
+#define INTC_ICDISPR15_TINT73 (0x00000200uL)
+#define INTC_ICDISPR15_TINT74 (0x00000400uL)
+#define INTC_ICDISPR15_TINT75 (0x00000800uL)
+#define INTC_ICDISPR15_TINT76 (0x00001000uL)
+#define INTC_ICDISPR15_TINT77 (0x00002000uL)
+#define INTC_ICDISPR15_TINT78 (0x00004000uL)
+#define INTC_ICDISPR15_TINT79 (0x00008000uL)
+#define INTC_ICDISPR15_TINT80 (0x00010000uL)
+#define INTC_ICDISPR15_TINT81 (0x00020000uL)
+#define INTC_ICDISPR15_TINT82 (0x00040000uL)
+#define INTC_ICDISPR15_TINT83 (0x00080000uL)
+#define INTC_ICDISPR15_TINT84 (0x00100000uL)
+#define INTC_ICDISPR15_TINT85 (0x00200000uL)
+#define INTC_ICDISPR15_TINT86 (0x00400000uL)
+#define INTC_ICDISPR15_TINT87 (0x00800000uL)
+#define INTC_ICDISPR15_TINT88 (0x01000000uL)
+#define INTC_ICDISPR15_TINT89 (0x02000000uL)
+#define INTC_ICDISPR15_TINT90 (0x04000000uL)
+#define INTC_ICDISPR15_TINT91 (0x08000000uL)
+#define INTC_ICDISPR15_TINT92 (0x10000000uL)
+#define INTC_ICDISPR15_TINT93 (0x20000000uL)
+#define INTC_ICDISPR15_TINT94 (0x40000000uL)
+#define INTC_ICDISPR15_TINT95 (0x80000000uL)
+
+#define INTC_ICDISPR16_TINT96 (0x00000001uL)
+#define INTC_ICDISPR16_TINT97 (0x00000002uL)
+#define INTC_ICDISPR16_TINT98 (0x00000004uL)
+#define INTC_ICDISPR16_TINT99 (0x00000008uL)
+#define INTC_ICDISPR16_TINT100 (0x00000010uL)
+#define INTC_ICDISPR16_TINT101 (0x00000020uL)
+#define INTC_ICDISPR16_TINT102 (0x00000040uL)
+#define INTC_ICDISPR16_TINT103 (0x00000080uL)
+#define INTC_ICDISPR16_TINT104 (0x00000100uL)
+#define INTC_ICDISPR16_TINT105 (0x00000200uL)
+#define INTC_ICDISPR16_TINT106 (0x00000400uL)
+#define INTC_ICDISPR16_TINT107 (0x00000800uL)
+#define INTC_ICDISPR16_TINT108 (0x00001000uL)
+#define INTC_ICDISPR16_TINT109 (0x00002000uL)
+#define INTC_ICDISPR16_TINT110 (0x00004000uL)
+#define INTC_ICDISPR16_TINT111 (0x00008000uL)
+#define INTC_ICDISPR16_TINT112 (0x00010000uL)
+#define INTC_ICDISPR16_TINT113 (0x00020000uL)
+#define INTC_ICDISPR16_TINT114 (0x00040000uL)
+#define INTC_ICDISPR16_TINT115 (0x00080000uL)
+#define INTC_ICDISPR16_TINT116 (0x00100000uL)
+#define INTC_ICDISPR16_TINT117 (0x00200000uL)
+#define INTC_ICDISPR16_TINT118 (0x00400000uL)
+#define INTC_ICDISPR16_TINT119 (0x00800000uL)
+#define INTC_ICDISPR16_TINT120 (0x01000000uL)
+#define INTC_ICDISPR16_TINT121 (0x02000000uL)
+#define INTC_ICDISPR16_TINT122 (0x04000000uL)
+#define INTC_ICDISPR16_TINT123 (0x08000000uL)
+#define INTC_ICDISPR16_TINT124 (0x10000000uL)
+#define INTC_ICDISPR16_TINT125 (0x20000000uL)
+#define INTC_ICDISPR16_TINT126 (0x40000000uL)
+#define INTC_ICDISPR16_TINT127 (0x80000000uL)
+
+#define INTC_ICDISPR17_TINT128 (0x00000001uL)
+#define INTC_ICDISPR17_TINT129 (0x00000002uL)
+#define INTC_ICDISPR17_TINT130 (0x00000004uL)
+#define INTC_ICDISPR17_TINT131 (0x00000008uL)
+#define INTC_ICDISPR17_TINT132 (0x00000010uL)
+#define INTC_ICDISPR17_TINT133 (0x00000020uL)
+#define INTC_ICDISPR17_TINT134 (0x00000040uL)
+#define INTC_ICDISPR17_TINT135 (0x00000080uL)
+#define INTC_ICDISPR17_TINT136 (0x00000100uL)
+#define INTC_ICDISPR17_TINT137 (0x00000200uL)
+#define INTC_ICDISPR17_TINT138 (0x00000400uL)
+#define INTC_ICDISPR17_TINT139 (0x00000800uL)
+#define INTC_ICDISPR17_TINT140 (0x00001000uL)
+#define INTC_ICDISPR17_TINT141 (0x00002000uL)
+#define INTC_ICDISPR17_TINT142 (0x00004000uL)
+#define INTC_ICDISPR17_TINT143 (0x00008000uL)
+#define INTC_ICDISPR17_TINT144 (0x00010000uL)
+#define INTC_ICDISPR17_TINT145 (0x00020000uL)
+#define INTC_ICDISPR17_TINT146 (0x00040000uL)
+#define INTC_ICDISPR17_TINT147 (0x00080000uL)
+#define INTC_ICDISPR17_TINT148 (0x00100000uL)
+#define INTC_ICDISPR17_TINT149 (0x00200000uL)
+#define INTC_ICDISPR17_TINT150 (0x00400000uL)
+#define INTC_ICDISPR17_TINT151 (0x00800000uL)
+#define INTC_ICDISPR17_TINT152 (0x01000000uL)
+#define INTC_ICDISPR17_TINT153 (0x02000000uL)
+#define INTC_ICDISPR17_TINT154 (0x04000000uL)
+#define INTC_ICDISPR17_TINT155 (0x08000000uL)
+#define INTC_ICDISPR17_TINT156 (0x10000000uL)
+#define INTC_ICDISPR17_TINT157 (0x20000000uL)
+#define INTC_ICDISPR17_TINT158 (0x40000000uL)
+#define INTC_ICDISPR17_TINT159 (0x80000000uL)
+
+#define INTC_ICDISPR18_TINT160 (0x00000001uL)
+#define INTC_ICDISPR18_TINT161 (0x00000002uL)
+#define INTC_ICDISPR18_TINT162 (0x00000004uL)
+#define INTC_ICDISPR18_TINT163 (0x00000008uL)
+#define INTC_ICDISPR18_TINT164 (0x00000010uL)
+#define INTC_ICDISPR18_TINT165 (0x00000020uL)
+#define INTC_ICDISPR18_TINT166 (0x00000040uL)
+#define INTC_ICDISPR18_TINT167 (0x00000080uL)
+#define INTC_ICDISPR18_TINT168 (0x00000100uL)
+#define INTC_ICDISPR18_TINT169 (0x00000200uL)
+#define INTC_ICDISPR18_TINT170 (0x00000400uL)
+
+#define INTC_ICDICPR0_SW0 (0x00000001uL)
+#define INTC_ICDICPR0_SW1 (0x00000002uL)
+#define INTC_ICDICPR0_SW2 (0x00000004uL)
+#define INTC_ICDICPR0_SW3 (0x00000008uL)
+#define INTC_ICDICPR0_SW4 (0x00000010uL)
+#define INTC_ICDICPR0_SW5 (0x00000020uL)
+#define INTC_ICDICPR0_SW6 (0x00000040uL)
+#define INTC_ICDICPR0_SW7 (0x00000080uL)
+#define INTC_ICDICPR0_SW8 (0x00000100uL)
+#define INTC_ICDICPR0_SW9 (0x00000200uL)
+#define INTC_ICDICPR0_SW10 (0x00000400uL)
+#define INTC_ICDICPR0_SW11 (0x00000800uL)
+#define INTC_ICDICPR0_SW12 (0x00001000uL)
+#define INTC_ICDICPR0_SW13 (0x00002000uL)
+#define INTC_ICDICPR0_SW14 (0x00004000uL)
+#define INTC_ICDICPR0_SW15 (0x00008000uL)
+#define INTC_ICDICPR0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDICPR0_COMMRX0 (0x00020000uL)
+#define INTC_ICDICPR0_COMMTX0 (0x00040000uL)
+#define INTC_ICDICPR0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDICPR1_IRQ0 (0x00000001uL)
+#define INTC_ICDICPR1_IRQ1 (0x00000002uL)
+#define INTC_ICDICPR1_IRQ2 (0x00000004uL)
+#define INTC_ICDICPR1_IRQ3 (0x00000008uL)
+#define INTC_ICDICPR1_IRQ4 (0x00000010uL)
+#define INTC_ICDICPR1_IRQ5 (0x00000020uL)
+#define INTC_ICDICPR1_IRQ6 (0x00000040uL)
+#define INTC_ICDICPR1_IRQ7 (0x00000080uL)
+#define INTC_ICDICPR1_PL310ERR (0x00000100uL)
+#define INTC_ICDICPR1_DMAINT0 (0x00000200uL)
+#define INTC_ICDICPR1_DMAINT1 (0x00000400uL)
+#define INTC_ICDICPR1_DMAINT2 (0x00000800uL)
+#define INTC_ICDICPR1_DMAINT3 (0x00001000uL)
+#define INTC_ICDICPR1_DMAINT4 (0x00002000uL)
+#define INTC_ICDICPR1_DMAINT5 (0x00004000uL)
+#define INTC_ICDICPR1_DMAINT6 (0x00008000uL)
+#define INTC_ICDICPR1_DMAINT7 (0x00010000uL)
+#define INTC_ICDICPR1_DMAINT8 (0x00020000uL)
+#define INTC_ICDICPR1_DMAINT9 (0x00040000uL)
+#define INTC_ICDICPR1_DMAINT10 (0x00080000uL)
+#define INTC_ICDICPR1_DMAINT11 (0x00100000uL)
+#define INTC_ICDICPR1_DMAINT12 (0x00200000uL)
+#define INTC_ICDICPR1_DMAINT13 (0x00400000uL)
+#define INTC_ICDICPR1_DMAINT14 (0x00800000uL)
+#define INTC_ICDICPR1_DMAINT15 (0x01000000uL)
+#define INTC_ICDICPR1_DMAERR (0x02000000uL)
+
+#define INTC_ICDICPR2_USBI0 (0x00000200uL)
+#define INTC_ICDICPR2_USBI1 (0x00000400uL)
+#define INTC_ICDICPR2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDICPR2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDICPR2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDICPR2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDICPR2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDICPR2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDICPR2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDICPR2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDICPR2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDICPR2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDICPR2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDICPR2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDICPR2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDICPR2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDICPR2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDICPR2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDICPR2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDICPR2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDICPR2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDICPR3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDICPR3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDICPR3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDICPR3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDICPR3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDICPR3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDICPR3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDICPR3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDICPR3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDICPR3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDICPR3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDICPR3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDICPR3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDICPR3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDICPR3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDICPR3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDICPR3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDICPR3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDICPR3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDICPR3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDICPR3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDICPR3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDICPR3_IMRDI (0x08000000uL)
+#define INTC_ICDICPR3_IMR2I0 (0x10000000uL)
+#define INTC_ICDICPR3_IMR2I1 (0x20000000uL)
+#define INTC_ICDICPR3_JEDI (0x40000000uL)
+#define INTC_ICDICPR3_JDTI (0x80000000uL)
+
+#define INTC_ICDICPR4_CMP0 (0x00000001uL)
+#define INTC_ICDICPR4_CMP1 (0x00000002uL)
+#define INTC_ICDICPR4_INT0 (0x00000004uL)
+#define INTC_ICDICPR4_INT1 (0x00000008uL)
+#define INTC_ICDICPR4_INT2 (0x00000010uL)
+#define INTC_ICDICPR4_INT3 (0x00000020uL)
+#define INTC_ICDICPR4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDICPR4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDICPR4_CMI (0x00000100uL)
+#define INTC_ICDICPR4_WTOUT (0x00000200uL)
+#define INTC_ICDICPR4_ITI (0x00000400uL)
+#define INTC_ICDICPR4_TGI0A (0x00000800uL)
+#define INTC_ICDICPR4_TGI0B (0x00001000uL)
+#define INTC_ICDICPR4_TGI0C (0x00002000uL)
+#define INTC_ICDICPR4_TGI0D (0x00004000uL)
+#define INTC_ICDICPR4_TGI0V (0x00008000uL)
+#define INTC_ICDICPR4_TGI0E (0x00010000uL)
+#define INTC_ICDICPR4_TGI0F (0x00020000uL)
+#define INTC_ICDICPR4_TGI1A (0x00040000uL)
+#define INTC_ICDICPR4_TGI1B (0x00080000uL)
+#define INTC_ICDICPR4_TGI1V (0x00100000uL)
+#define INTC_ICDICPR4_TGI1U (0x00200000uL)
+#define INTC_ICDICPR4_TGI2A (0x00400000uL)
+#define INTC_ICDICPR4_TGI2B (0x00800000uL)
+#define INTC_ICDICPR4_TGI2V (0x01000000uL)
+#define INTC_ICDICPR4_TGI2U (0x02000000uL)
+#define INTC_ICDICPR4_TGI3A (0x04000000uL)
+#define INTC_ICDICPR4_TGI3B (0x08000000uL)
+#define INTC_ICDICPR4_TGI3C (0x10000000uL)
+#define INTC_ICDICPR4_TGI3D (0x20000000uL)
+#define INTC_ICDICPR4_TGI3V (0x40000000uL)
+#define INTC_ICDICPR4_TGI4A (0x80000000uL)
+
+#define INTC_ICDICPR5_TGI4B (0x00000001uL)
+#define INTC_ICDICPR5_TGI4C (0x00000002uL)
+#define INTC_ICDICPR5_TGI4D (0x00000004uL)
+#define INTC_ICDICPR5_TGI4V (0x00000008uL)
+#define INTC_ICDICPR5_CMI1 (0x00000010uL)
+#define INTC_ICDICPR5_CMI2 (0x00000020uL)
+#define INTC_ICDICPR5_SGDEI0 (0x00000040uL)
+#define INTC_ICDICPR5_SGDEI1 (0x00000080uL)
+#define INTC_ICDICPR5_SGDEI2 (0x00000100uL)
+#define INTC_ICDICPR5_SGDEI3 (0x00000200uL)
+#define INTC_ICDICPR5_ADI (0x00000400uL)
+#define INTC_ICDICPR5_LMTI (0x00000800uL)
+#define INTC_ICDICPR5_SSII0 (0x00001000uL)
+#define INTC_ICDICPR5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDICPR5_SSITXI0 (0x00004000uL)
+#define INTC_ICDICPR5_SSII1 (0x00008000uL)
+#define INTC_ICDICPR5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDICPR5_SSITXI1 (0x00020000uL)
+#define INTC_ICDICPR5_SSII2 (0x00040000uL)
+#define INTC_ICDICPR5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDICPR5_SSII3 (0x00100000uL)
+#define INTC_ICDICPR5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDICPR5_SSITXI3 (0x00400000uL)
+#define INTC_ICDICPR5_SSII4 (0x00800000uL)
+#define INTC_ICDICPR5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDICPR5_SSII5 (0x02000000uL)
+#define INTC_ICDICPR5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDICPR5_SSITXI5 (0x08000000uL)
+#define INTC_ICDICPR5_SPDIFI (0x10000000uL)
+#define INTC_ICDICPR5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDICPR5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDICPR5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDICPR6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDICPR6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDICPR6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDICPR6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDICPR6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDICPR6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDICPR6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDICPR6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDICPR6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDICPR6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDICPR6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDICPR6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDICPR6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDICPR6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDICPR6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDICPR6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDICPR6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDICPR6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDICPR6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDICPR6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDICPR6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDICPR6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDICPR6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDICPR6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDICPR6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDICPR6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDICPR6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDICPR6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDICPR6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDICPR6_BRI0 (0x20000000uL)
+#define INTC_ICDICPR6_ERI0 (0x40000000uL)
+#define INTC_ICDICPR6_RXI0 (0x80000000uL)
+
+#define INTC_ICDICPR7_TXI0 (0x00000001uL)
+#define INTC_ICDICPR7_BRI1 (0x00000002uL)
+#define INTC_ICDICPR7_ERI1 (0x00000004uL)
+#define INTC_ICDICPR7_RXI1 (0x00000008uL)
+#define INTC_ICDICPR7_TXI1 (0x00000010uL)
+#define INTC_ICDICPR7_BRI2 (0x00000020uL)
+#define INTC_ICDICPR7_ERI2 (0x00000040uL)
+#define INTC_ICDICPR7_RXI2 (0x00000080uL)
+#define INTC_ICDICPR7_TXI2 (0x00000100uL)
+#define INTC_ICDICPR7_BRI3 (0x00000200uL)
+#define INTC_ICDICPR7_ERI3 (0x00000400uL)
+#define INTC_ICDICPR7_RXI3 (0x00000800uL)
+#define INTC_ICDICPR7_TXI3 (0x00001000uL)
+#define INTC_ICDICPR7_BRI4 (0x00002000uL)
+#define INTC_ICDICPR7_ERI4 (0x00004000uL)
+#define INTC_ICDICPR7_RXI4 (0x00008000uL)
+#define INTC_ICDICPR7_TXI4 (0x00010000uL)
+#define INTC_ICDICPR7_BRI5 (0x00020000uL)
+#define INTC_ICDICPR7_ERI5 (0x00040000uL)
+#define INTC_ICDICPR7_RXI5 (0x00080000uL)
+#define INTC_ICDICPR7_TXI5 (0x00100000uL)
+#define INTC_ICDICPR7_BRI6 (0x00200000uL)
+#define INTC_ICDICPR7_ERI6 (0x00400000uL)
+#define INTC_ICDICPR7_RXI6 (0x00800000uL)
+#define INTC_ICDICPR7_TXI6 (0x01000000uL)
+#define INTC_ICDICPR7_BRI7 (0x02000000uL)
+#define INTC_ICDICPR7_ERI7 (0x04000000uL)
+#define INTC_ICDICPR7_RXI7 (0x08000000uL)
+#define INTC_ICDICPR7_TXI7 (0x10000000uL)
+#define INTC_ICDICPR7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDICPR7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDICPR7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDICPR8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDICPR8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDICPR8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDICPR8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDICPR8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDICPR8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDICPR8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDICPR8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDICPR8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDICPR8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDICPR8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDICPR8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDICPR8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDICPR8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDICPR8_SPEI0 (0x00004000uL)
+#define INTC_ICDICPR8_SPRI0 (0x00008000uL)
+#define INTC_ICDICPR8_SPTI0 (0x00010000uL)
+#define INTC_ICDICPR8_SPEI1 (0x00020000uL)
+#define INTC_ICDICPR8_SPRI1 (0x00040000uL)
+#define INTC_ICDICPR8_SPTI1 (0x00080000uL)
+#define INTC_ICDICPR8_SPEI2 (0x00100000uL)
+#define INTC_ICDICPR8_SPRI2 (0x00200000uL)
+#define INTC_ICDICPR8_SPTI2 (0x00400000uL)
+#define INTC_ICDICPR8_SPEI3 (0x00800000uL)
+#define INTC_ICDICPR8_SPRI3 (0x01000000uL)
+#define INTC_ICDICPR8_SPTI3 (0x02000000uL)
+#define INTC_ICDICPR8_SPEI4 (0x04000000uL)
+#define INTC_ICDICPR8_SPRI4 (0x08000000uL)
+#define INTC_ICDICPR8_SPTI4 (0x10000000uL)
+#define INTC_ICDICPR8_IEBBTD (0x20000000uL)
+#define INTC_ICDICPR8_IEBBTERR (0x40000000uL)
+#define INTC_ICDICPR8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDICPR9_IEBBTV (0x00000001uL)
+#define INTC_ICDICPR9_ISY (0x00000002uL)
+#define INTC_ICDICPR9_IERR (0x00000004uL)
+#define INTC_ICDICPR9_ITARG (0x00000008uL)
+#define INTC_ICDICPR9_ISEC (0x00000010uL)
+#define INTC_ICDICPR9_IBUF (0x00000020uL)
+#define INTC_ICDICPR9_IREADY (0x00000040uL)
+#define INTC_ICDICPR9_FLSTE (0x00000080uL)
+#define INTC_ICDICPR9_FLTENDI (0x00000100uL)
+#define INTC_ICDICPR9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDICPR9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDICPR9_MMC0 (0x00000800uL)
+#define INTC_ICDICPR9_MMC1 (0x00001000uL)
+#define INTC_ICDICPR9_MMC2 (0x00002000uL)
+#define INTC_ICDICPR9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDICPR9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDICPR9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDICPR9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDICPR9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDICPR9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDICPR9_ARM (0x00100000uL)
+#define INTC_ICDICPR9_PRD (0x00200000uL)
+#define INTC_ICDICPR9_CUP (0x00400000uL)
+#define INTC_ICDICPR9_SCUAI0 (0x00800000uL)
+#define INTC_ICDICPR9_SCUAI1 (0x01000000uL)
+#define INTC_ICDICPR9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDICPR9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDICPR9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDICPR9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDICPR9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDICPR9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDICPR9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDICPR10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDICPR10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDICPR10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDICPR10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDICPR10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDICPR10_MLB_CINT (0x00000020uL)
+#define INTC_ICDICPR10_MLB_SINT (0x00000040uL)
+#define INTC_ICDICPR10_DRC0 (0x00000080uL)
+#define INTC_ICDICPR10_DRC1 (0x00000100uL)
+#define INTC_ICDICPR10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDICPR10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDICPR10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDICPR10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDICPR10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDICPR10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDICPR10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDICPR10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDICPR10_ERI0 (0x08000000uL)
+#define INTC_ICDICPR10_RXI0 (0x10000000uL)
+#define INTC_ICDICPR10_TXI0 (0x20000000uL)
+#define INTC_ICDICPR10_TEI0 (0x40000000uL)
+#define INTC_ICDICPR10_ERI1 (0x80000000uL)
+
+#define INTC_ICDICPR11_RXI1 (0x00000001uL)
+#define INTC_ICDICPR11_TXI1 (0x00000002uL)
+#define INTC_ICDICPR11_TEI1 (0x00000004uL)
+#define INTC_ICDICPR11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDICPR11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDICPR11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDICPR11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDICPR11_ETHERI (0x00000080uL)
+#define INTC_ICDICPR11_CEUI (0x00001000uL)
+#define INTC_ICDICPR11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDICPR11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDICPR12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDICPR12_PRRI (0x00000100uL)
+#define INTC_ICDICPR12_IFEI0 (0x00000200uL)
+#define INTC_ICDICPR12_OFFI0 (0x00000400uL)
+#define INTC_ICDICPR12_PFVEI0 (0x00000800uL)
+#define INTC_ICDICPR12_IFEI1 (0x00001000uL)
+#define INTC_ICDICPR12_OFFI1 (0x00002000uL)
+#define INTC_ICDICPR12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDICPR13_TINT0 (0x00000001uL)
+#define INTC_ICDICPR13_TINT1 (0x00000002uL)
+#define INTC_ICDICPR13_TINT2 (0x00000004uL)
+#define INTC_ICDICPR13_TINT3 (0x00000008uL)
+#define INTC_ICDICPR13_TINT4 (0x00000010uL)
+#define INTC_ICDICPR13_TINT5 (0x00000020uL)
+#define INTC_ICDICPR13_TINT6 (0x00000040uL)
+#define INTC_ICDICPR13_TINT7 (0x00000080uL)
+#define INTC_ICDICPR13_TINT8 (0x00000100uL)
+#define INTC_ICDICPR13_TINT9 (0x00000200uL)
+#define INTC_ICDICPR13_TINT10 (0x00000400uL)
+#define INTC_ICDICPR13_TINT11 (0x00000800uL)
+#define INTC_ICDICPR13_TINT12 (0x00001000uL)
+#define INTC_ICDICPR13_TINT13 (0x00002000uL)
+#define INTC_ICDICPR13_TINT14 (0x00004000uL)
+#define INTC_ICDICPR13_TINT15 (0x00008000uL)
+#define INTC_ICDICPR13_TINT16 (0x00010000uL)
+#define INTC_ICDICPR13_TINT17 (0x00020000uL)
+#define INTC_ICDICPR13_TINT18 (0x00040000uL)
+#define INTC_ICDICPR13_TINT19 (0x00080000uL)
+#define INTC_ICDICPR13_TINT20 (0x00100000uL)
+#define INTC_ICDICPR13_TINT21 (0x00200000uL)
+#define INTC_ICDICPR13_TINT22 (0x00400000uL)
+#define INTC_ICDICPR13_TINT23 (0x00800000uL)
+#define INTC_ICDICPR13_TINT24 (0x01000000uL)
+#define INTC_ICDICPR13_TINT25 (0x02000000uL)
+#define INTC_ICDICPR13_TINT26 (0x04000000uL)
+#define INTC_ICDICPR13_TINT27 (0x08000000uL)
+#define INTC_ICDICPR13_TINT28 (0x10000000uL)
+#define INTC_ICDICPR13_TINT29 (0x20000000uL)
+#define INTC_ICDICPR13_TINT30 (0x40000000uL)
+#define INTC_ICDICPR13_TINT31 (0x80000000uL)
+
+#define INTC_ICDICPR14_TINT32 (0x00000001uL)
+#define INTC_ICDICPR14_TINT33 (0x00000002uL)
+#define INTC_ICDICPR14_TINT34 (0x00000004uL)
+#define INTC_ICDICPR14_TINT35 (0x00000008uL)
+#define INTC_ICDICPR14_TINT36 (0x00000010uL)
+#define INTC_ICDICPR14_TINT37 (0x00000020uL)
+#define INTC_ICDICPR14_TINT38 (0x00000040uL)
+#define INTC_ICDICPR14_TINT39 (0x00000080uL)
+#define INTC_ICDICPR14_TINT40 (0x00000100uL)
+#define INTC_ICDICPR14_TINT41 (0x00000200uL)
+#define INTC_ICDICPR14_TINT42 (0x00000400uL)
+#define INTC_ICDICPR14_TINT43 (0x00000800uL)
+#define INTC_ICDICPR14_TINT44 (0x00001000uL)
+#define INTC_ICDICPR14_TINT45 (0x00002000uL)
+#define INTC_ICDICPR14_TINT46 (0x00004000uL)
+#define INTC_ICDICPR14_TINT47 (0x00008000uL)
+#define INTC_ICDICPR14_TINT48 (0x00010000uL)
+#define INTC_ICDICPR14_TINT49 (0x00020000uL)
+#define INTC_ICDICPR14_TINT50 (0x00040000uL)
+#define INTC_ICDICPR14_TINT51 (0x00080000uL)
+#define INTC_ICDICPR14_TINT52 (0x00100000uL)
+#define INTC_ICDICPR14_TINT53 (0x00200000uL)
+#define INTC_ICDICPR14_TINT54 (0x00400000uL)
+#define INTC_ICDICPR14_TINT55 (0x00800000uL)
+#define INTC_ICDICPR14_TINT56 (0x01000000uL)
+#define INTC_ICDICPR14_TINT57 (0x02000000uL)
+#define INTC_ICDICPR14_TINT58 (0x04000000uL)
+#define INTC_ICDICPR14_TINT59 (0x08000000uL)
+#define INTC_ICDICPR14_TINT60 (0x10000000uL)
+#define INTC_ICDICPR14_TINT61 (0x20000000uL)
+#define INTC_ICDICPR14_TINT62 (0x40000000uL)
+#define INTC_ICDICPR14_TINT63 (0x80000000uL)
+
+#define INTC_ICDICPR15_TINT64 (0x00000001uL)
+#define INTC_ICDICPR15_TINT65 (0x00000002uL)
+#define INTC_ICDICPR15_TINT66 (0x00000004uL)
+#define INTC_ICDICPR15_TINT67 (0x00000008uL)
+#define INTC_ICDICPR15_TINT68 (0x00000010uL)
+#define INTC_ICDICPR15_TINT69 (0x00000020uL)
+#define INTC_ICDICPR15_TINT70 (0x00000040uL)
+#define INTC_ICDICPR15_TINT71 (0x00000080uL)
+#define INTC_ICDICPR15_TINT72 (0x00000100uL)
+#define INTC_ICDICPR15_TINT73 (0x00000200uL)
+#define INTC_ICDICPR15_TINT74 (0x00000400uL)
+#define INTC_ICDICPR15_TINT75 (0x00000800uL)
+#define INTC_ICDICPR15_TINT76 (0x00001000uL)
+#define INTC_ICDICPR15_TINT77 (0x00002000uL)
+#define INTC_ICDICPR15_TINT78 (0x00004000uL)
+#define INTC_ICDICPR15_TINT79 (0x00008000uL)
+#define INTC_ICDICPR15_TINT80 (0x00010000uL)
+#define INTC_ICDICPR15_TINT81 (0x00020000uL)
+#define INTC_ICDICPR15_TINT82 (0x00040000uL)
+#define INTC_ICDICPR15_TINT83 (0x00080000uL)
+#define INTC_ICDICPR15_TINT84 (0x00100000uL)
+#define INTC_ICDICPR15_TINT85 (0x00200000uL)
+#define INTC_ICDICPR15_TINT86 (0x00400000uL)
+#define INTC_ICDICPR15_TINT87 (0x00800000uL)
+#define INTC_ICDICPR15_TINT88 (0x01000000uL)
+#define INTC_ICDICPR15_TINT89 (0x02000000uL)
+#define INTC_ICDICPR15_TINT90 (0x04000000uL)
+#define INTC_ICDICPR15_TINT91 (0x08000000uL)
+#define INTC_ICDICPR15_TINT92 (0x10000000uL)
+#define INTC_ICDICPR15_TINT93 (0x20000000uL)
+#define INTC_ICDICPR15_TINT94 (0x40000000uL)
+#define INTC_ICDICPR15_TINT95 (0x80000000uL)
+
+#define INTC_ICDICPR16_TINT96 (0x00000001uL)
+#define INTC_ICDICPR16_TINT97 (0x00000002uL)
+#define INTC_ICDICPR16_TINT98 (0x00000004uL)
+#define INTC_ICDICPR16_TINT99 (0x00000008uL)
+#define INTC_ICDICPR16_TINT100 (0x00000010uL)
+#define INTC_ICDICPR16_TINT101 (0x00000020uL)
+#define INTC_ICDICPR16_TINT102 (0x00000040uL)
+#define INTC_ICDICPR16_TINT103 (0x00000080uL)
+#define INTC_ICDICPR16_TINT104 (0x00000100uL)
+#define INTC_ICDICPR16_TINT105 (0x00000200uL)
+#define INTC_ICDICPR16_TINT106 (0x00000400uL)
+#define INTC_ICDICPR16_TINT107 (0x00000800uL)
+#define INTC_ICDICPR16_TINT108 (0x00001000uL)
+#define INTC_ICDICPR16_TINT109 (0x00002000uL)
+#define INTC_ICDICPR16_TINT110 (0x00004000uL)
+#define INTC_ICDICPR16_TINT111 (0x00008000uL)
+#define INTC_ICDICPR16_TINT112 (0x00010000uL)
+#define INTC_ICDICPR16_TINT113 (0x00020000uL)
+#define INTC_ICDICPR16_TINT114 (0x00040000uL)
+#define INTC_ICDICPR16_TINT115 (0x00080000uL)
+#define INTC_ICDICPR16_TINT116 (0x00100000uL)
+#define INTC_ICDICPR16_TINT117 (0x00200000uL)
+#define INTC_ICDICPR16_TINT118 (0x00400000uL)
+#define INTC_ICDICPR16_TINT119 (0x00800000uL)
+#define INTC_ICDICPR16_TINT120 (0x01000000uL)
+#define INTC_ICDICPR16_TINT121 (0x02000000uL)
+#define INTC_ICDICPR16_TINT122 (0x04000000uL)
+#define INTC_ICDICPR16_TINT123 (0x08000000uL)
+#define INTC_ICDICPR16_TINT124 (0x10000000uL)
+#define INTC_ICDICPR16_TINT125 (0x20000000uL)
+#define INTC_ICDICPR16_TINT126 (0x40000000uL)
+#define INTC_ICDICPR16_TINT127 (0x80000000uL)
+
+#define INTC_ICDICPR17_TINT128 (0x00000001uL)
+#define INTC_ICDICPR17_TINT129 (0x00000002uL)
+#define INTC_ICDICPR17_TINT130 (0x00000004uL)
+#define INTC_ICDICPR17_TINT131 (0x00000008uL)
+#define INTC_ICDICPR17_TINT132 (0x00000010uL)
+#define INTC_ICDICPR17_TINT133 (0x00000020uL)
+#define INTC_ICDICPR17_TINT134 (0x00000040uL)
+#define INTC_ICDICPR17_TINT135 (0x00000080uL)
+#define INTC_ICDICPR17_TINT136 (0x00000100uL)
+#define INTC_ICDICPR17_TINT137 (0x00000200uL)
+#define INTC_ICDICPR17_TINT138 (0x00000400uL)
+#define INTC_ICDICPR17_TINT139 (0x00000800uL)
+#define INTC_ICDICPR17_TINT140 (0x00001000uL)
+#define INTC_ICDICPR17_TINT141 (0x00002000uL)
+#define INTC_ICDICPR17_TINT142 (0x00004000uL)
+#define INTC_ICDICPR17_TINT143 (0x00008000uL)
+#define INTC_ICDICPR17_TINT144 (0x00010000uL)
+#define INTC_ICDICPR17_TINT145 (0x00020000uL)
+#define INTC_ICDICPR17_TINT146 (0x00040000uL)
+#define INTC_ICDICPR17_TINT147 (0x00080000uL)
+#define INTC_ICDICPR17_TINT148 (0x00100000uL)
+#define INTC_ICDICPR17_TINT149 (0x00200000uL)
+#define INTC_ICDICPR17_TINT150 (0x00400000uL)
+#define INTC_ICDICPR17_TINT151 (0x00800000uL)
+#define INTC_ICDICPR17_TINT152 (0x01000000uL)
+#define INTC_ICDICPR17_TINT153 (0x02000000uL)
+#define INTC_ICDICPR17_TINT154 (0x04000000uL)
+#define INTC_ICDICPR17_TINT155 (0x08000000uL)
+#define INTC_ICDICPR17_TINT156 (0x10000000uL)
+#define INTC_ICDICPR17_TINT157 (0x20000000uL)
+#define INTC_ICDICPR17_TINT158 (0x40000000uL)
+#define INTC_ICDICPR17_TINT159 (0x80000000uL)
+
+#define INTC_ICDICPR18_TINT160 (0x00000001uL)
+#define INTC_ICDICPR18_TINT161 (0x00000002uL)
+#define INTC_ICDICPR18_TINT162 (0x00000004uL)
+#define INTC_ICDICPR18_TINT163 (0x00000008uL)
+#define INTC_ICDICPR18_TINT164 (0x00000010uL)
+#define INTC_ICDICPR18_TINT165 (0x00000020uL)
+#define INTC_ICDICPR18_TINT166 (0x00000040uL)
+#define INTC_ICDICPR18_TINT167 (0x00000080uL)
+#define INTC_ICDICPR18_TINT168 (0x00000100uL)
+#define INTC_ICDICPR18_TINT169 (0x00000200uL)
+#define INTC_ICDICPR18_TINT170 (0x00000400uL)
+
+#define INTC_ICDABR0_SW0 (0x00000001uL)
+#define INTC_ICDABR0_SW1 (0x00000002uL)
+#define INTC_ICDABR0_SW2 (0x00000004uL)
+#define INTC_ICDABR0_SW3 (0x00000008uL)
+#define INTC_ICDABR0_SW4 (0x00000010uL)
+#define INTC_ICDABR0_SW5 (0x00000020uL)
+#define INTC_ICDABR0_SW6 (0x00000040uL)
+#define INTC_ICDABR0_SW7 (0x00000080uL)
+#define INTC_ICDABR0_SW8 (0x00000100uL)
+#define INTC_ICDABR0_SW9 (0x00000200uL)
+#define INTC_ICDABR0_SW10 (0x00000400uL)
+#define INTC_ICDABR0_SW11 (0x00000800uL)
+#define INTC_ICDABR0_SW12 (0x00001000uL)
+#define INTC_ICDABR0_SW13 (0x00002000uL)
+#define INTC_ICDABR0_SW14 (0x00004000uL)
+#define INTC_ICDABR0_SW15 (0x00008000uL)
+#define INTC_ICDABR0_PMUIRQ0 (0x00010000uL)
+#define INTC_ICDABR0_COMMRX0 (0x00020000uL)
+#define INTC_ICDABR0_COMMTX0 (0x00040000uL)
+#define INTC_ICDABR0_CTIIRQ0 (0x00080000uL)
+
+#define INTC_ICDABR1_IRQ0 (0x00000001uL)
+#define INTC_ICDABR1_IRQ1 (0x00000002uL)
+#define INTC_ICDABR1_IRQ2 (0x00000004uL)
+#define INTC_ICDABR1_IRQ3 (0x00000008uL)
+#define INTC_ICDABR1_IRQ4 (0x00000010uL)
+#define INTC_ICDABR1_IRQ5 (0x00000020uL)
+#define INTC_ICDABR1_IRQ6 (0x00000040uL)
+#define INTC_ICDABR1_IRQ7 (0x00000080uL)
+#define INTC_ICDABR1_PL310ERR (0x00000100uL)
+#define INTC_ICDABR1_DMAINT0 (0x00000200uL)
+#define INTC_ICDABR1_DMAINT1 (0x00000400uL)
+#define INTC_ICDABR1_DMAINT2 (0x00000800uL)
+#define INTC_ICDABR1_DMAINT3 (0x00001000uL)
+#define INTC_ICDABR1_DMAINT4 (0x00002000uL)
+#define INTC_ICDABR1_DMAINT5 (0x00004000uL)
+#define INTC_ICDABR1_DMAINT6 (0x00008000uL)
+#define INTC_ICDABR1_DMAINT7 (0x00010000uL)
+#define INTC_ICDABR1_DMAINT8 (0x00020000uL)
+#define INTC_ICDABR1_DMAINT9 (0x00040000uL)
+#define INTC_ICDABR1_DMAINT10 (0x00080000uL)
+#define INTC_ICDABR1_DMAINT11 (0x00100000uL)
+#define INTC_ICDABR1_DMAINT12 (0x00200000uL)
+#define INTC_ICDABR1_DMAINT13 (0x00400000uL)
+#define INTC_ICDABR1_DMAINT14 (0x00800000uL)
+#define INTC_ICDABR1_DMAINT15 (0x01000000uL)
+#define INTC_ICDABR1_DMAERR (0x02000000uL)
+
+#define INTC_ICDABR2_USBI0 (0x00000200uL)
+#define INTC_ICDABR2_USBI1 (0x00000400uL)
+#define INTC_ICDABR2_S0_VI_VSYNC0 (0x00000800uL)
+#define INTC_ICDABR2_S0_LO_VSYNC0 (0x00001000uL)
+#define INTC_ICDABR2_S0_VSYNCERR0 (0x00002000uL)
+#define INTC_ICDABR2_GR3_VLINE0 (0x00004000uL)
+#define INTC_ICDABR2_S0_VFIELD0 (0x00008000uL)
+#define INTC_ICDABR2_IV1_VBUFERR0 (0x00010000uL)
+#define INTC_ICDABR2_IV3_VBUFERR0 (0x00020000uL)
+#define INTC_ICDABR2_IV5_VBUFERR0 (0x00040000uL)
+#define INTC_ICDABR2_IV6_VBUFERR0 (0x00080000uL)
+#define INTC_ICDABR2_S0_WLINE0 (0x00100000uL)
+#define INTC_ICDABR2_S1_VI_VSYNC0 (0x00200000uL)
+#define INTC_ICDABR2_S1_LO_VSYNC0 (0x00400000uL)
+#define INTC_ICDABR2_S1_VSYNCERR0 (0x00800000uL)
+#define INTC_ICDABR2_S1_VFIELD0 (0x01000000uL)
+#define INTC_ICDABR2_IV2_VBUFERR0 (0x02000000uL)
+#define INTC_ICDABR2_IV4_VBUFERR0 (0x04000000uL)
+#define INTC_ICDABR2_S1_WLINE0 (0x08000000uL)
+#define INTC_ICDABR2_OIR_VI_VSYNC0 (0x10000000uL)
+#define INTC_ICDABR2_OIR_LO_VSYNC0 (0x20000000uL)
+#define INTC_ICDABR2_OIR_VSYNCERR0 (0x40000000uL)
+#define INTC_ICDABR2_OIR_VFIELD0 (0x80000000uL)
+
+#define INTC_ICDABR3_IV7_VBUFERR0 (0x00000001uL)
+#define INTC_ICDABR3_IV8_VBUFERR0 (0x00000002uL)
+#define INTC_ICDABR3_S0_VI_VSYNC1 (0x00000008uL)
+#define INTC_ICDABR3_S0_LO_VSYNC1 (0x00000010uL)
+#define INTC_ICDABR3_S0_VSYNCERR1 (0x00000020uL)
+#define INTC_ICDABR3_GR3_VLINE1 (0x00000040uL)
+#define INTC_ICDABR3_S0_VFIELD1 (0x00000080uL)
+#define INTC_ICDABR3_IV1_VBUFERR1 (0x00000100uL)
+#define INTC_ICDABR3_IV3_VBUFERR1 (0x00000200uL)
+#define INTC_ICDABR3_IV5_VBUFERR1 (0x00000400uL)
+#define INTC_ICDABR3_IV6_VBUFERR1 (0x00000800uL)
+#define INTC_ICDABR3_S0_WLINE1 (0x00001000uL)
+#define INTC_ICDABR3_S1_VI_VSYNC1 (0x00002000uL)
+#define INTC_ICDABR3_S1_LO_VSYNC1 (0x00004000uL)
+#define INTC_ICDABR3_S1_VSYNCERR1 (0x00008000uL)
+#define INTC_ICDABR3_S1_VFIELD1 (0x00010000uL)
+#define INTC_ICDABR3_IV2_VBUFERR1 (0x00020000uL)
+#define INTC_ICDABR3_IV4_VBUFERR1 (0x00040000uL)
+#define INTC_ICDABR3_S1_WLINE1 (0x00080000uL)
+#define INTC_ICDABR3_OIR_VI_VSYNC1 (0x00100000uL)
+#define INTC_ICDABR3_OIR_LO_VSYNC1 (0x00200000uL)
+#define INTC_ICDABR3_OIR_VLINE1 (0x00400000uL)
+#define INTC_ICDABR3_OIR_VFIELD1 (0x00800000uL)
+#define INTC_ICDABR3_IV7_VBUFERR1 (0x01000000uL)
+#define INTC_ICDABR3_IV8_VBUFERR1 (0x02000000uL)
+#define INTC_ICDABR3_IMRDI (0x08000000uL)
+#define INTC_ICDABR3_IMR2I0 (0x10000000uL)
+#define INTC_ICDABR3_IMR2I1 (0x20000000uL)
+#define INTC_ICDABR3_JEDI (0x40000000uL)
+#define INTC_ICDABR3_JDTI (0x80000000uL)
+
+#define INTC_ICDABR4_CMP0 (0x00000001uL)
+#define INTC_ICDABR4_CMP1 (0x00000002uL)
+#define INTC_ICDABR4_INT0 (0x00000004uL)
+#define INTC_ICDABR4_INT1 (0x00000008uL)
+#define INTC_ICDABR4_INT2 (0x00000010uL)
+#define INTC_ICDABR4_INT3 (0x00000020uL)
+#define INTC_ICDABR4_OSTM0TINT (0x00000040uL)
+#define INTC_ICDABR4_OSTM1TINT (0x00000080uL)
+#define INTC_ICDABR4_CMI (0x00000100uL)
+#define INTC_ICDABR4_WTOUT (0x00000200uL)
+#define INTC_ICDABR4_ITI (0x00000400uL)
+#define INTC_ICDABR4_TGI0A (0x00000800uL)
+#define INTC_ICDABR4_TGI0B (0x00001000uL)
+#define INTC_ICDABR4_TGI0C (0x00002000uL)
+#define INTC_ICDABR4_TGI0D (0x00004000uL)
+#define INTC_ICDABR4_TGI0V (0x00008000uL)
+#define INTC_ICDABR4_TGI0E (0x00010000uL)
+#define INTC_ICDABR4_TGI0F (0x00020000uL)
+#define INTC_ICDABR4_TGI1A (0x00040000uL)
+#define INTC_ICDABR4_TGI1B (0x00080000uL)
+#define INTC_ICDABR4_TGI1V (0x00100000uL)
+#define INTC_ICDABR4_TGI1U (0x00200000uL)
+#define INTC_ICDABR4_TGI2A (0x00400000uL)
+#define INTC_ICDABR4_TGI2B (0x00800000uL)
+#define INTC_ICDABR4_TGI2V (0x01000000uL)
+#define INTC_ICDABR4_TGI2U (0x02000000uL)
+#define INTC_ICDABR4_TGI3A (0x04000000uL)
+#define INTC_ICDABR4_TGI3B (0x08000000uL)
+#define INTC_ICDABR4_TGI3C (0x10000000uL)
+#define INTC_ICDABR4_TGI3D (0x20000000uL)
+#define INTC_ICDABR4_TGI3V (0x40000000uL)
+#define INTC_ICDABR4_TGI4A (0x80000000uL)
+
+#define INTC_ICDABR5_TGI4B (0x00000001uL)
+#define INTC_ICDABR5_TGI4C (0x00000002uL)
+#define INTC_ICDABR5_TGI4D (0x00000004uL)
+#define INTC_ICDABR5_TGI4V (0x00000008uL)
+#define INTC_ICDABR5_CMI1 (0x00000010uL)
+#define INTC_ICDABR5_CMI2 (0x00000020uL)
+#define INTC_ICDABR5_SGDEI0 (0x00000040uL)
+#define INTC_ICDABR5_SGDEI1 (0x00000080uL)
+#define INTC_ICDABR5_SGDEI2 (0x00000100uL)
+#define INTC_ICDABR5_SGDEI3 (0x00000200uL)
+#define INTC_ICDABR5_ADI (0x00000400uL)
+#define INTC_ICDABR5_LMTI (0x00000800uL)
+#define INTC_ICDABR5_SSII0 (0x00001000uL)
+#define INTC_ICDABR5_SSIRXI0 (0x00002000uL)
+#define INTC_ICDABR5_SSITXI0 (0x00004000uL)
+#define INTC_ICDABR5_SSII1 (0x00008000uL)
+#define INTC_ICDABR5_SSIRXI1 (0x00010000uL)
+#define INTC_ICDABR5_SSITXI1 (0x00020000uL)
+#define INTC_ICDABR5_SSII2 (0x00040000uL)
+#define INTC_ICDABR5_SSIRTI2 (0x00080000uL)
+#define INTC_ICDABR5_SSII3 (0x00100000uL)
+#define INTC_ICDABR5_SSIRXI3 (0x00200000uL)
+#define INTC_ICDABR5_SSITXI3 (0x00400000uL)
+#define INTC_ICDABR5_SSII4 (0x00800000uL)
+#define INTC_ICDABR5_SSIRTI4 (0x01000000uL)
+#define INTC_ICDABR5_SSII5 (0x02000000uL)
+#define INTC_ICDABR5_SSIRXI5 (0x04000000uL)
+#define INTC_ICDABR5_SSITXI5 (0x08000000uL)
+#define INTC_ICDABR5_SPDIFI (0x10000000uL)
+#define INTC_ICDABR5_INTIICTEI0 (0x20000000uL)
+#define INTC_ICDABR5_INTIICRI0 (0x40000000uL)
+#define INTC_ICDABR5_INTIICTI0 (0x80000000uL)
+
+#define INTC_ICDABR6_INTIICSPI0 (0x00000001uL)
+#define INTC_ICDABR6_INTIICSTI0 (0x00000002uL)
+#define INTC_ICDABR6_INTIICNAKI0 (0x00000004uL)
+#define INTC_ICDABR6_INTIICALI0 (0x00000008uL)
+#define INTC_ICDABR6_INTIICTMOI0 (0x00000010uL)
+#define INTC_ICDABR6_INTIICTEI1 (0x00000020uL)
+#define INTC_ICDABR6_INTIICRI1 (0x00000040uL)
+#define INTC_ICDABR6_INTIICTI1 (0x00000080uL)
+#define INTC_ICDABR6_INTIICSPI1 (0x00000100uL)
+#define INTC_ICDABR6_INTIICSTI1 (0x00000200uL)
+#define INTC_ICDABR6_INTIICNAKI1 (0x00000400uL)
+#define INTC_ICDABR6_INTIICALI1 (0x00000800uL)
+#define INTC_ICDABR6_INTIICTMOI1 (0x00001000uL)
+#define INTC_ICDABR6_INTIICTEI2 (0x00002000uL)
+#define INTC_ICDABR6_INTIICRI2 (0x00004000uL)
+#define INTC_ICDABR6_INTIICTI2 (0x00008000uL)
+#define INTC_ICDABR6_INTIICSPI2 (0x00010000uL)
+#define INTC_ICDABR6_INTIICSTI2 (0x00020000uL)
+#define INTC_ICDABR6_INTIICNAKI2 (0x00040000uL)
+#define INTC_ICDABR6_INTIICALI2 (0x00080000uL)
+#define INTC_ICDABR6_INTIICTMOI2 (0x00100000uL)
+#define INTC_ICDABR6_INTIICTEI3 (0x00200000uL)
+#define INTC_ICDABR6_INTIICRI3 (0x00400000uL)
+#define INTC_ICDABR6_INTIICTI3 (0x00800000uL)
+#define INTC_ICDABR6_INTIICSPI3 (0x01000000uL)
+#define INTC_ICDABR6_INTIICSTI3 (0x02000000uL)
+#define INTC_ICDABR6_INTIICNAKI3 (0x04000000uL)
+#define INTC_ICDABR6_INTIICALI3 (0x08000000uL)
+#define INTC_ICDABR6_INTIICTMOI3 (0x10000000uL)
+#define INTC_ICDABR6_BRI0 (0x20000000uL)
+#define INTC_ICDABR6_ERI0 (0x40000000uL)
+#define INTC_ICDABR6_RXI0 (0x80000000uL)
+
+#define INTC_ICDABR7_TXI0 (0x00000001uL)
+#define INTC_ICDABR7_BRI1 (0x00000002uL)
+#define INTC_ICDABR7_ERI1 (0x00000004uL)
+#define INTC_ICDABR7_RXI1 (0x00000008uL)
+#define INTC_ICDABR7_TXI1 (0x00000010uL)
+#define INTC_ICDABR7_BRI2 (0x00000020uL)
+#define INTC_ICDABR7_ERI2 (0x00000040uL)
+#define INTC_ICDABR7_RXI2 (0x00000080uL)
+#define INTC_ICDABR7_TXI2 (0x00000100uL)
+#define INTC_ICDABR7_BRI3 (0x00000200uL)
+#define INTC_ICDABR7_ERI3 (0x00000400uL)
+#define INTC_ICDABR7_RXI3 (0x00000800uL)
+#define INTC_ICDABR7_TXI3 (0x00001000uL)
+#define INTC_ICDABR7_BRI4 (0x00002000uL)
+#define INTC_ICDABR7_ERI4 (0x00004000uL)
+#define INTC_ICDABR7_RXI4 (0x00008000uL)
+#define INTC_ICDABR7_TXI4 (0x00010000uL)
+#define INTC_ICDABR7_BRI5 (0x00020000uL)
+#define INTC_ICDABR7_ERI5 (0x00040000uL)
+#define INTC_ICDABR7_RXI5 (0x00080000uL)
+#define INTC_ICDABR7_TXI5 (0x00100000uL)
+#define INTC_ICDABR7_BRI6 (0x00200000uL)
+#define INTC_ICDABR7_ERI6 (0x00400000uL)
+#define INTC_ICDABR7_RXI6 (0x00800000uL)
+#define INTC_ICDABR7_TXI6 (0x01000000uL)
+#define INTC_ICDABR7_BRI7 (0x02000000uL)
+#define INTC_ICDABR7_ERI7 (0x04000000uL)
+#define INTC_ICDABR7_RXI7 (0x08000000uL)
+#define INTC_ICDABR7_TXI7 (0x10000000uL)
+#define INTC_ICDABR7_INTRCANGERR (0x20000000uL)
+#define INTC_ICDABR7_INTRCANGRECC (0x40000000uL)
+#define INTC_ICDABR7_INTRCAN0REC (0x80000000uL)
+
+#define INTC_ICDABR8_INTRCAN0ERR (0x00000001uL)
+#define INTC_ICDABR8_INTRCAN0TRX (0x00000002uL)
+#define INTC_ICDABR8_INTRCAN1REC (0x00000004uL)
+#define INTC_ICDABR8_INTRCAN1ERR (0x00000008uL)
+#define INTC_ICDABR8_INTRCAN1TRX (0x00000010uL)
+#define INTC_ICDABR8_INTRCAN2REC (0x00000020uL)
+#define INTC_ICDABR8_INTRCAN2ERR (0x00000040uL)
+#define INTC_ICDABR8_INTRCAN2TRX (0x00000080uL)
+#define INTC_ICDABR8_INTRCAN3REC (0x00000100uL)
+#define INTC_ICDABR8_INTRCAN3ERR (0x00000200uL)
+#define INTC_ICDABR8_INTRCAN3TRX (0x00000400uL)
+#define INTC_ICDABR8_INTRCAN4REC (0x00000800uL)
+#define INTC_ICDABR8_INTRCAN4ERR (0x00001000uL)
+#define INTC_ICDABR8_INTRCAN4TRX (0x00002000uL)
+#define INTC_ICDABR8_SPEI0 (0x00004000uL)
+#define INTC_ICDABR8_SPRI0 (0x00008000uL)
+#define INTC_ICDABR8_SPTI0 (0x00010000uL)
+#define INTC_ICDABR8_SPEI1 (0x00020000uL)
+#define INTC_ICDABR8_SPRI1 (0x00040000uL)
+#define INTC_ICDABR8_SPTI1 (0x00080000uL)
+#define INTC_ICDABR8_SPEI2 (0x00100000uL)
+#define INTC_ICDABR8_SPRI2 (0x00200000uL)
+#define INTC_ICDABR8_SPTI2 (0x00400000uL)
+#define INTC_ICDABR8_SPEI3 (0x00800000uL)
+#define INTC_ICDABR8_SPRI3 (0x01000000uL)
+#define INTC_ICDABR8_SPTI3 (0x02000000uL)
+#define INTC_ICDABR8_SPEI4 (0x04000000uL)
+#define INTC_ICDABR8_SPRI4 (0x08000000uL)
+#define INTC_ICDABR8_SPTI4 (0x10000000uL)
+#define INTC_ICDABR8_IEBBTD (0x20000000uL)
+#define INTC_ICDABR8_IEBBTERR (0x40000000uL)
+#define INTC_ICDABR8_IEBBTSTA (0x80000000uL)
+
+#define INTC_ICDABR9_IEBBTV (0x00000001uL)
+#define INTC_ICDABR9_ISY (0x00000002uL)
+#define INTC_ICDABR9_IERR (0x00000004uL)
+#define INTC_ICDABR9_ITARG (0x00000008uL)
+#define INTC_ICDABR9_ISEC (0x00000010uL)
+#define INTC_ICDABR9_IBUF (0x00000020uL)
+#define INTC_ICDABR9_IREADY (0x00000040uL)
+#define INTC_ICDABR9_FLSTE (0x00000080uL)
+#define INTC_ICDABR9_FLTENDI (0x00000100uL)
+#define INTC_ICDABR9_FLTREQ0I (0x00000200uL)
+#define INTC_ICDABR9_FLTREQ1I (0x00000400uL)
+#define INTC_ICDABR9_MMC0 (0x00000800uL)
+#define INTC_ICDABR9_MMC1 (0x00001000uL)
+#define INTC_ICDABR9_MMC2 (0x00002000uL)
+#define INTC_ICDABR9_SDHI0_3 (0x00004000uL)
+#define INTC_ICDABR9_SDHI0_0 (0x00008000uL)
+#define INTC_ICDABR9_SDHI0_1 (0x00010000uL)
+#define INTC_ICDABR9_SDHI1_3 (0x00020000uL)
+#define INTC_ICDABR9_SDHI1_0 (0x00040000uL)
+#define INTC_ICDABR9_SDHI1_1 (0x00080000uL)
+#define INTC_ICDABR9_ARM (0x00100000uL)
+#define INTC_ICDABR9_PRD (0x00200000uL)
+#define INTC_ICDABR9_CUP (0x00400000uL)
+#define INTC_ICDABR9_SCUAI0 (0x00800000uL)
+#define INTC_ICDABR9_SCUAI1 (0x01000000uL)
+#define INTC_ICDABR9_SCUFDI0 (0x02000000uL)
+#define INTC_ICDABR9_SCUFDI1 (0x04000000uL)
+#define INTC_ICDABR9_SCUFDI2 (0x08000000uL)
+#define INTC_ICDABR9_SCUFDI3 (0x10000000uL)
+#define INTC_ICDABR9_SCUFUI0 (0x20000000uL)
+#define INTC_ICDABR9_SCUFUI1 (0x40000000uL)
+#define INTC_ICDABR9_SCUFUI2 (0x80000000uL)
+
+#define INTC_ICDABR10_SCUFUI3 (0x00000001uL)
+#define INTC_ICDABR10_SCUDVI0 (0x00000002uL)
+#define INTC_ICDABR10_SCUDVI1 (0x00000004uL)
+#define INTC_ICDABR10_SCUDVI2 (0x00000008uL)
+#define INTC_ICDABR10_SCUDVI3 (0x00000010uL)
+#define INTC_ICDABR10_MLB_CINT (0x00000020uL)
+#define INTC_ICDABR10_MLB_SINT (0x00000040uL)
+#define INTC_ICDABR10_DRC0 (0x00000080uL)
+#define INTC_ICDABR10_DRC1 (0x00000100uL)
+#define INTC_ICDABR10_LINI0_INT_T (0x00000800uL)
+#define INTC_ICDABR10_LINI0_INT_R (0x00001000uL)
+#define INTC_ICDABR10_LINI0_INT_S (0x00002000uL)
+#define INTC_ICDABR10_LINI0_INT_M (0x00004000uL)
+#define INTC_ICDABR10_LINI1_INT_T (0x00008000uL)
+#define INTC_ICDABR10_LINI1_INT_R (0x00010000uL)
+#define INTC_ICDABR10_LINI1_INT_S (0x00020000uL)
+#define INTC_ICDABR10_LINI1_INT_M (0x00040000uL)
+#define INTC_ICDABR10_ERI0 (0x08000000uL)
+#define INTC_ICDABR10_RXI0 (0x10000000uL)
+#define INTC_ICDABR10_TXI0 (0x20000000uL)
+#define INTC_ICDABR10_TEI0 (0x40000000uL)
+#define INTC_ICDABR10_ERI1 (0x80000000uL)
+
+#define INTC_ICDABR11_RXI1 (0x00000001uL)
+#define INTC_ICDABR11_TXI1 (0x00000002uL)
+#define INTC_ICDABR11_TEI1 (0x00000004uL)
+#define INTC_ICDABR11_AVBI_DATA (0x00000008uL)
+#define INTC_ICDABR11_AVBI_ERROR (0x00000010uL)
+#define INTC_ICDABR11_AVBI_MANAGE (0x00000020uL)
+#define INTC_ICDABR11_AVBI_MAC (0x00000040uL)
+#define INTC_ICDABR11_ETHERI (0x00000080uL)
+#define INTC_ICDABR11_CEUI (0x00001000uL)
+#define INTC_ICDABR11_H2XMLB_ERRINT (0x20000000uL)
+#define INTC_ICDABR11_H2XIC1_ERRINT (0x40000000uL)
+#define INTC_ICDABR11_X2HPERI1_ERRINT (0x80000000uL)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT (0x00000001uL)
+#define INTC_ICDABR12_X2HPERI34_ERRINT (0x00000002uL)
+#define INTC_ICDABR12_X2HPERI5_ERRINT (0x00000004uL)
+#define INTC_ICDABR12_X2HPERI67_ERRINT (0x00000008uL)
+#define INTC_ICDABR12_X2HDBGR_ERRINT (0x00000010uL)
+#define INTC_ICDABR12_X2HBSC_ERRINT (0x00000020uL)
+#define INTC_ICDABR12_X2HSPI1_ERRINT (0x00000040uL)
+#define INTC_ICDABR12_X2HSPI2_ERRINT (0x00000080uL)
+#define INTC_ICDABR12_PRRI (0x00000100uL)
+#define INTC_ICDABR12_IFEI0 (0x00000200uL)
+#define INTC_ICDABR12_OFFI0 (0x00000400uL)
+#define INTC_ICDABR12_PFVEI0 (0x00000800uL)
+#define INTC_ICDABR12_IFEI1 (0x00001000uL)
+#define INTC_ICDABR12_OFFI1 (0x00002000uL)
+#define INTC_ICDABR12_PFVEI1 (0x00004000uL)
+
+#define INTC_ICDABR13_TINT0 (0x00000001uL)
+#define INTC_ICDABR13_TINT1 (0x00000002uL)
+#define INTC_ICDABR13_TINT2 (0x00000004uL)
+#define INTC_ICDABR13_TINT3 (0x00000008uL)
+#define INTC_ICDABR13_TINT4 (0x00000010uL)
+#define INTC_ICDABR13_TINT5 (0x00000020uL)
+#define INTC_ICDABR13_TINT6 (0x00000040uL)
+#define INTC_ICDABR13_TINT7 (0x00000080uL)
+#define INTC_ICDABR13_TINT8 (0x00000100uL)
+#define INTC_ICDABR13_TINT9 (0x00000200uL)
+#define INTC_ICDABR13_TINT10 (0x00000400uL)
+#define INTC_ICDABR13_TINT11 (0x00000800uL)
+#define INTC_ICDABR13_TINT12 (0x00001000uL)
+#define INTC_ICDABR13_TINT13 (0x00002000uL)
+#define INTC_ICDABR13_TINT14 (0x00004000uL)
+#define INTC_ICDABR13_TINT15 (0x00008000uL)
+#define INTC_ICDABR13_TINT16 (0x00010000uL)
+#define INTC_ICDABR13_TINT17 (0x00020000uL)
+#define INTC_ICDABR13_TINT18 (0x00040000uL)
+#define INTC_ICDABR13_TINT19 (0x00080000uL)
+#define INTC_ICDABR13_TINT20 (0x00100000uL)
+#define INTC_ICDABR13_TINT21 (0x00200000uL)
+#define INTC_ICDABR13_TINT22 (0x00400000uL)
+#define INTC_ICDABR13_TINT23 (0x00800000uL)
+#define INTC_ICDABR13_TINT24 (0x01000000uL)
+#define INTC_ICDABR13_TINT25 (0x02000000uL)
+#define INTC_ICDABR13_TINT26 (0x04000000uL)
+#define INTC_ICDABR13_TINT27 (0x08000000uL)
+#define INTC_ICDABR13_TINT28 (0x10000000uL)
+#define INTC_ICDABR13_TINT29 (0x20000000uL)
+#define INTC_ICDABR13_TINT30 (0x40000000uL)
+#define INTC_ICDABR13_TINT31 (0x80000000uL)
+
+#define INTC_ICDABR14_TINT32 (0x00000001uL)
+#define INTC_ICDABR14_TINT33 (0x00000002uL)
+#define INTC_ICDABR14_TINT34 (0x00000004uL)
+#define INTC_ICDABR14_TINT35 (0x00000008uL)
+#define INTC_ICDABR14_TINT36 (0x00000010uL)
+#define INTC_ICDABR14_TINT37 (0x00000020uL)
+#define INTC_ICDABR14_TINT38 (0x00000040uL)
+#define INTC_ICDABR14_TINT39 (0x00000080uL)
+#define INTC_ICDABR14_TINT40 (0x00000100uL)
+#define INTC_ICDABR14_TINT41 (0x00000200uL)
+#define INTC_ICDABR14_TINT42 (0x00000400uL)
+#define INTC_ICDABR14_TINT43 (0x00000800uL)
+#define INTC_ICDABR14_TINT44 (0x00001000uL)
+#define INTC_ICDABR14_TINT45 (0x00002000uL)
+#define INTC_ICDABR14_TINT46 (0x00004000uL)
+#define INTC_ICDABR14_TINT47 (0x00008000uL)
+#define INTC_ICDABR14_TINT48 (0x00010000uL)
+#define INTC_ICDABR14_TINT49 (0x00020000uL)
+#define INTC_ICDABR14_TINT50 (0x00040000uL)
+#define INTC_ICDABR14_TINT51 (0x00080000uL)
+#define INTC_ICDABR14_TINT52 (0x00100000uL)
+#define INTC_ICDABR14_TINT53 (0x00200000uL)
+#define INTC_ICDABR14_TINT54 (0x00400000uL)
+#define INTC_ICDABR14_TINT55 (0x00800000uL)
+#define INTC_ICDABR14_TINT56 (0x01000000uL)
+#define INTC_ICDABR14_TINT57 (0x02000000uL)
+#define INTC_ICDABR14_TINT58 (0x04000000uL)
+#define INTC_ICDABR14_TINT59 (0x08000000uL)
+#define INTC_ICDABR14_TINT60 (0x10000000uL)
+#define INTC_ICDABR14_TINT61 (0x20000000uL)
+#define INTC_ICDABR14_TINT62 (0x40000000uL)
+#define INTC_ICDABR14_TINT63 (0x80000000uL)
+
+#define INTC_ICDABR15_TINT64 (0x00000001uL)
+#define INTC_ICDABR15_TINT65 (0x00000002uL)
+#define INTC_ICDABR15_TINT66 (0x00000004uL)
+#define INTC_ICDABR15_TINT67 (0x00000008uL)
+#define INTC_ICDABR15_TINT68 (0x00000010uL)
+#define INTC_ICDABR15_TINT69 (0x00000020uL)
+#define INTC_ICDABR15_TINT70 (0x00000040uL)
+#define INTC_ICDABR15_TINT71 (0x00000080uL)
+#define INTC_ICDABR15_TINT72 (0x00000100uL)
+#define INTC_ICDABR15_TINT73 (0x00000200uL)
+#define INTC_ICDABR15_TINT74 (0x00000400uL)
+#define INTC_ICDABR15_TINT75 (0x00000800uL)
+#define INTC_ICDABR15_TINT76 (0x00001000uL)
+#define INTC_ICDABR15_TINT77 (0x00002000uL)
+#define INTC_ICDABR15_TINT78 (0x00004000uL)
+#define INTC_ICDABR15_TINT79 (0x00008000uL)
+#define INTC_ICDABR15_TINT80 (0x00010000uL)
+#define INTC_ICDABR15_TINT81 (0x00020000uL)
+#define INTC_ICDABR15_TINT82 (0x00040000uL)
+#define INTC_ICDABR15_TINT83 (0x00080000uL)
+#define INTC_ICDABR15_TINT84 (0x00100000uL)
+#define INTC_ICDABR15_TINT85 (0x00200000uL)
+#define INTC_ICDABR15_TINT86 (0x00400000uL)
+#define INTC_ICDABR15_TINT87 (0x00800000uL)
+#define INTC_ICDABR15_TINT88 (0x01000000uL)
+#define INTC_ICDABR15_TINT89 (0x02000000uL)
+#define INTC_ICDABR15_TINT90 (0x04000000uL)
+#define INTC_ICDABR15_TINT91 (0x08000000uL)
+#define INTC_ICDABR15_TINT92 (0x10000000uL)
+#define INTC_ICDABR15_TINT93 (0x20000000uL)
+#define INTC_ICDABR15_TINT94 (0x40000000uL)
+#define INTC_ICDABR15_TINT95 (0x80000000uL)
+
+#define INTC_ICDABR16_TINT96 (0x00000001uL)
+#define INTC_ICDABR16_TINT97 (0x00000002uL)
+#define INTC_ICDABR16_TINT98 (0x00000004uL)
+#define INTC_ICDABR16_TINT99 (0x00000008uL)
+#define INTC_ICDABR16_TINT100 (0x00000010uL)
+#define INTC_ICDABR16_TINT101 (0x00000020uL)
+#define INTC_ICDABR16_TINT102 (0x00000040uL)
+#define INTC_ICDABR16_TINT103 (0x00000080uL)
+#define INTC_ICDABR16_TINT104 (0x00000100uL)
+#define INTC_ICDABR16_TINT105 (0x00000200uL)
+#define INTC_ICDABR16_TINT106 (0x00000400uL)
+#define INTC_ICDABR16_TINT107 (0x00000800uL)
+#define INTC_ICDABR16_TINT108 (0x00001000uL)
+#define INTC_ICDABR16_TINT109 (0x00002000uL)
+#define INTC_ICDABR16_TINT110 (0x00004000uL)
+#define INTC_ICDABR16_TINT111 (0x00008000uL)
+#define INTC_ICDABR16_TINT112 (0x00010000uL)
+#define INTC_ICDABR16_TINT113 (0x00020000uL)
+#define INTC_ICDABR16_TINT114 (0x00040000uL)
+#define INTC_ICDABR16_TINT115 (0x00080000uL)
+#define INTC_ICDABR16_TINT116 (0x00100000uL)
+#define INTC_ICDABR16_TINT117 (0x00200000uL)
+#define INTC_ICDABR16_TINT118 (0x00400000uL)
+#define INTC_ICDABR16_TINT119 (0x00800000uL)
+#define INTC_ICDABR16_TINT120 (0x01000000uL)
+#define INTC_ICDABR16_TINT121 (0x02000000uL)
+#define INTC_ICDABR16_TINT122 (0x04000000uL)
+#define INTC_ICDABR16_TINT123 (0x08000000uL)
+#define INTC_ICDABR16_TINT124 (0x10000000uL)
+#define INTC_ICDABR16_TINT125 (0x20000000uL)
+#define INTC_ICDABR16_TINT126 (0x40000000uL)
+#define INTC_ICDABR16_TINT127 (0x80000000uL)
+
+#define INTC_ICDABR17_TINT128 (0x00000001uL)
+#define INTC_ICDABR17_TINT129 (0x00000002uL)
+#define INTC_ICDABR17_TINT130 (0x00000004uL)
+#define INTC_ICDABR17_TINT131 (0x00000008uL)
+#define INTC_ICDABR17_TINT132 (0x00000010uL)
+#define INTC_ICDABR17_TINT133 (0x00000020uL)
+#define INTC_ICDABR17_TINT134 (0x00000040uL)
+#define INTC_ICDABR17_TINT135 (0x00000080uL)
+#define INTC_ICDABR17_TINT136 (0x00000100uL)
+#define INTC_ICDABR17_TINT137 (0x00000200uL)
+#define INTC_ICDABR17_TINT138 (0x00000400uL)
+#define INTC_ICDABR17_TINT139 (0x00000800uL)
+#define INTC_ICDABR17_TINT140 (0x00001000uL)
+#define INTC_ICDABR17_TINT141 (0x00002000uL)
+#define INTC_ICDABR17_TINT142 (0x00004000uL)
+#define INTC_ICDABR17_TINT143 (0x00008000uL)
+#define INTC_ICDABR17_TINT144 (0x00010000uL)
+#define INTC_ICDABR17_TINT145 (0x00020000uL)
+#define INTC_ICDABR17_TINT146 (0x00040000uL)
+#define INTC_ICDABR17_TINT147 (0x00080000uL)
+#define INTC_ICDABR17_TINT148 (0x00100000uL)
+#define INTC_ICDABR17_TINT149 (0x00200000uL)
+#define INTC_ICDABR17_TINT150 (0x00400000uL)
+#define INTC_ICDABR17_TINT151 (0x00800000uL)
+#define INTC_ICDABR17_TINT152 (0x01000000uL)
+#define INTC_ICDABR17_TINT153 (0x02000000uL)
+#define INTC_ICDABR17_TINT154 (0x04000000uL)
+#define INTC_ICDABR17_TINT155 (0x08000000uL)
+#define INTC_ICDABR17_TINT156 (0x10000000uL)
+#define INTC_ICDABR17_TINT157 (0x20000000uL)
+#define INTC_ICDABR17_TINT158 (0x40000000uL)
+#define INTC_ICDABR17_TINT159 (0x80000000uL)
+
+#define INTC_ICDABR18_TINT160 (0x00000001uL)
+#define INTC_ICDABR18_TINT161 (0x00000002uL)
+#define INTC_ICDABR18_TINT162 (0x00000004uL)
+#define INTC_ICDABR18_TINT163 (0x00000008uL)
+#define INTC_ICDABR18_TINT164 (0x00000010uL)
+#define INTC_ICDABR18_TINT165 (0x00000020uL)
+#define INTC_ICDABR18_TINT166 (0x00000040uL)
+#define INTC_ICDABR18_TINT167 (0x00000080uL)
+#define INTC_ICDABR18_TINT168 (0x00000100uL)
+#define INTC_ICDABR18_TINT169 (0x00000200uL)
+#define INTC_ICDABR18_TINT170 (0x00000400uL)
+
+#define INTC_ICDIPR0_SW0 (0x000000FFuL)
+#define INTC_ICDIPR0_SW1 (0x0000FF00uL)
+#define INTC_ICDIPR0_SW2 (0x00FF0000uL)
+#define INTC_ICDIPR0_SW3 (0xFF000000uL)
+
+#define INTC_ICDIPR1_SW4 (0x000000FFuL)
+#define INTC_ICDIPR1_SW5 (0x0000FF00uL)
+#define INTC_ICDIPR1_SW6 (0x00FF0000uL)
+#define INTC_ICDIPR1_SW7 (0xFF000000uL)
+
+#define INTC_ICDIPR2_SW8 (0x000000FFuL)
+#define INTC_ICDIPR2_SW9 (0x0000FF00uL)
+#define INTC_ICDIPR2_SW10 (0x00FF0000uL)
+#define INTC_ICDIPR2_SW11 (0xFF000000uL)
+
+#define INTC_ICDIPR3_SW12 (0x000000FFuL)
+#define INTC_ICDIPR3_SW13 (0x0000FF00uL)
+#define INTC_ICDIPR3_SW14 (0x00FF0000uL)
+#define INTC_ICDIPR3_SW15 (0xFF000000uL)
+
+#define INTC_ICDIPR4_PMUIRQ0 (0x000000FFuL)
+#define INTC_ICDIPR4_COMMRX0 (0x0000FF00uL)
+#define INTC_ICDIPR4_COMMTX0 (0x00FF0000uL)
+#define INTC_ICDIPR4_CTIIRQ0 (0xFF000000uL)
+
+#define INTC_ICDIPR8_IRQ0 (0x000000FFuL)
+#define INTC_ICDIPR8_IRQ1 (0x0000FF00uL)
+#define INTC_ICDIPR8_IRQ2 (0x00FF0000uL)
+#define INTC_ICDIPR8_IRQ3 (0xFF000000uL)
+
+#define INTC_ICDIPR9_IRQ4 (0x000000FFuL)
+#define INTC_ICDIPR9_IRQ5 (0x0000FF00uL)
+#define INTC_ICDIPR9_IRQ6 (0x00FF0000uL)
+#define INTC_ICDIPR9_IRQ7 (0xFF000000uL)
+
+#define INTC_ICDIPR10_PL310ERR (0x000000FFuL)
+#define INTC_ICDIPR10_DMAINT0 (0x0000FF00uL)
+#define INTC_ICDIPR10_DMAINT1 (0x00FF0000uL)
+#define INTC_ICDIPR10_DMAINT2 (0xFF000000uL)
+
+#define INTC_ICDIPR11_DMAINT3 (0x000000FFuL)
+#define INTC_ICDIPR11_DMAINT4 (0x0000FF00uL)
+#define INTC_ICDIPR11_DMAINT5 (0x00FF0000uL)
+#define INTC_ICDIPR11_DMAINT6 (0xFF000000uL)
+
+#define INTC_ICDIPR12_DMAINT7 (0x000000FFuL)
+#define INTC_ICDIPR12_DMAINT8 (0x0000FF00uL)
+#define INTC_ICDIPR12_DMAINT9 (0x00FF0000uL)
+#define INTC_ICDIPR12_DMAINT10 (0xFF000000uL)
+
+#define INTC_ICDIPR13_DMAINT11 (0x000000FFuL)
+#define INTC_ICDIPR13_DMAINT12 (0x0000FF00uL)
+#define INTC_ICDIPR13_DMAINT13 (0x00FF0000uL)
+#define INTC_ICDIPR13_DMAINT14 (0xFF000000uL)
+
+#define INTC_ICDIPR14_DMAINT15 (0x000000FFuL)
+#define INTC_ICDIPR14_DMAERR (0x0000FF00uL)
+
+#define INTC_ICDIPR18_USBI0 (0x0000FF00uL)
+#define INTC_ICDIPR18_USBI1 (0x00FF0000uL)
+#define INTC_ICDIPR18_S0_VI_VSYNC0 (0xFF000000uL)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0 (0x000000FFuL)
+#define INTC_ICDIPR19_S0_VSYNCERR0 (0x0000FF00uL)
+#define INTC_ICDIPR19_GR3_VLINE0 (0x00FF0000uL)
+#define INTC_ICDIPR19_S0_VFIELD0 (0xFF000000uL)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0 (0x000000FFuL)
+#define INTC_ICDIPR20_IV3_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPR20_IV5_VBUFERR0 (0x00FF0000uL)
+#define INTC_ICDIPR20_IV6_VBUFERR0 (0xFF000000uL)
+
+#define INTC_ICDIPR21_S0_WLINE0 (0x000000FFuL)
+#define INTC_ICDIPR21_S1_VI_VSYNC0 (0x0000FF00uL)
+#define INTC_ICDIPR21_S1_LO_VSYNC0 (0x00FF0000uL)
+#define INTC_ICDIPR21_S1_VSYNCERR0 (0xFF000000uL)
+
+#define INTC_ICDIPR22_S1_VFIELD0 (0x000000FFuL)
+#define INTC_ICDIPR22_IV2_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPR22_IV4_VBUFERR0 (0x00FF0000uL)
+#define INTC_ICDIPR22_S1_WLINE0 (0xFF000000uL)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0 (0x000000FFuL)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0 (0x0000FF00uL)
+#define INTC_ICDIPR23_OIR_VSYNCERR0 (0x00FF0000uL)
+#define INTC_ICDIPR23_OIR_VFIELD0 (0xFF000000uL)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0 (0x000000FFuL)
+#define INTC_ICDIPR24_IV8_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPR24_S0_VI_VSYNC1 (0xFF000000uL)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1 (0x000000FFuL)
+#define INTC_ICDIPR25_S0_VSYNCERR1 (0x0000FF00uL)
+#define INTC_ICDIPR25_GR3_VLINE1 (0x00FF0000uL)
+#define INTC_ICDIPR25_S0_VFIELD1 (0xFF000000uL)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1 (0x000000FFuL)
+#define INTC_ICDIPR26_IV3_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPR26_IV5_VBUFERR1 (0x00FF0000uL)
+#define INTC_ICDIPR26_IV6_VBUFERR1 (0xFF000000uL)
+
+#define INTC_ICDIPR27_S0_WLINE1 (0x000000FFuL)
+#define INTC_ICDIPR27_S1_VI_VSYNC1 (0x0000FF00uL)
+#define INTC_ICDIPR27_S1_LO_VSYNC1 (0x00FF0000uL)
+#define INTC_ICDIPR27_S1_VSYNCERR1 (0xFF000000uL)
+
+#define INTC_ICDIPR28_S1_VFIELD1 (0x000000FFuL)
+#define INTC_ICDIPR28_IV2_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPR28_IV4_VBUFERR1 (0x00FF0000uL)
+#define INTC_ICDIPR28_S1_WLINE1 (0xFF000000uL)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1 (0x000000FFuL)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1 (0x0000FF00uL)
+#define INTC_ICDIPR29_OIR_VLINE1 (0x00FF0000uL)
+#define INTC_ICDIPR29_OIR_VFIELD1 (0xFF000000uL)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1 (0x000000FFuL)
+#define INTC_ICDIPR30_IV8_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPR30_IMRDI (0xFF000000uL)
+
+#define INTC_ICDIPR31_IMR2I0 (0x000000FFuL)
+#define INTC_ICDIPR31_IMR2I1 (0x0000FF00uL)
+#define INTC_ICDIPR31_JEDI (0x00FF0000uL)
+#define INTC_ICDIPR31_JDTI (0xFF000000uL)
+
+#define INTC_ICDIPR32_CMP0 (0x000000FFuL)
+#define INTC_ICDIPR32_CMP1 (0x0000FF00uL)
+#define INTC_ICDIPR32_INT0 (0x00FF0000uL)
+#define INTC_ICDIPR32_INT1 (0xFF000000uL)
+
+#define INTC_ICDIPR33_INT2 (0x000000FFuL)
+#define INTC_ICDIPR33_INT3 (0x0000FF00uL)
+#define INTC_ICDIPR33_OSTM0TINT (0x00FF0000uL)
+#define INTC_ICDIPR33_OSTM1TINT (0xFF000000uL)
+
+#define INTC_ICDIPR34_CMI (0x000000FFuL)
+#define INTC_ICDIPR34_WTOUT (0x0000FF00uL)
+#define INTC_ICDIPR34_ITI (0x00FF0000uL)
+#define INTC_ICDIPR34_TGI0A (0xFF000000uL)
+
+#define INTC_ICDIPR35_TGI0B (0x000000FFuL)
+#define INTC_ICDIPR35_TGI0C (0x0000FF00uL)
+#define INTC_ICDIPR35_TGI0D (0x00FF0000uL)
+#define INTC_ICDIPR35_TGI0V (0xFF000000uL)
+
+#define INTC_ICDIPR36_TGI0E (0x000000FFuL)
+#define INTC_ICDIPR36_TGI0F (0x0000FF00uL)
+#define INTC_ICDIPR36_TGI1A (0x00FF0000uL)
+#define INTC_ICDIPR36_TGI1B (0xFF000000uL)
+
+#define INTC_ICDIPR37_TGI1V (0x000000FFuL)
+#define INTC_ICDIPR37_TGI1U (0x0000FF00uL)
+#define INTC_ICDIPR37_TGI2A (0x00FF0000uL)
+#define INTC_ICDIPR37_TGI2B (0xFF000000uL)
+
+#define INTC_ICDIPR38_TGI2V (0x000000FFuL)
+#define INTC_ICDIPR38_TGI2U (0x0000FF00uL)
+#define INTC_ICDIPR38_TGI3A (0x00FF0000uL)
+#define INTC_ICDIPR38_TGI3B (0xFF000000uL)
+
+#define INTC_ICDIPR39_TGI3C (0x000000FFuL)
+#define INTC_ICDIPR39_TGI3D (0x0000FF00uL)
+#define INTC_ICDIPR39_TGI3V (0x00FF0000uL)
+#define INTC_ICDIPR39_TGI4A (0xFF000000uL)
+
+#define INTC_ICDIPR40_TGI4B (0x000000FFuL)
+#define INTC_ICDIPR40_TGI4C (0x0000FF00uL)
+#define INTC_ICDIPR40_TGI4D (0x00FF0000uL)
+#define INTC_ICDIPR40_TGI4V (0xFF000000uL)
+
+#define INTC_ICDIPR41_CMI1 (0x000000FFuL)
+#define INTC_ICDIPR41_CMI2 (0x0000FF00uL)
+#define INTC_ICDIPR41_SGDEI0 (0x00FF0000uL)
+#define INTC_ICDIPR41_SGDEI1 (0xFF000000uL)
+
+#define INTC_ICDIPR42_SGDEI2 (0x000000FFuL)
+#define INTC_ICDIPR42_SGDEI3 (0x0000FF00uL)
+#define INTC_ICDIPR42_ADI (0x00FF0000uL)
+#define INTC_ICDIPR42_LMTI (0xFF000000uL)
+
+#define INTC_ICDIPR43_SSII0 (0x000000FFuL)
+#define INTC_ICDIPR43_SSIRXI0 (0x0000FF00uL)
+#define INTC_ICDIPR43_SSITXI0 (0x00FF0000uL)
+#define INTC_ICDIPR43_SSII1 (0xFF000000uL)
+
+#define INTC_ICDIPR44_SSIRXI1 (0x000000FFuL)
+#define INTC_ICDIPR44_SSITXI1 (0x0000FF00uL)
+#define INTC_ICDIPR44_SSII2 (0x00FF0000uL)
+#define INTC_ICDIPR44_SSIRTI2 (0xFF000000uL)
+
+#define INTC_ICDIPR45_SSII3 (0x000000FFuL)
+#define INTC_ICDIPR45_SSIRXI3 (0x0000FF00uL)
+#define INTC_ICDIPR45_SSITXI3 (0x00FF0000uL)
+#define INTC_ICDIPR45_SSII4 (0xFF000000uL)
+
+#define INTC_ICDIPR46_SSIRTI4 (0x000000FFuL)
+#define INTC_ICDIPR46_SSII5 (0x0000FF00uL)
+#define INTC_ICDIPR46_SSIRXI5 (0x00FF0000uL)
+#define INTC_ICDIPR46_SSITXI5 (0xFF000000uL)
+
+#define INTC_ICDIPR47_SPDIFI (0x000000FFuL)
+#define INTC_ICDIPR47_INTIICTEI0 (0x0000FF00uL)
+#define INTC_ICDIPR47_INTIICRI0 (0x00FF0000uL)
+#define INTC_ICDIPR47_INTIICTI0 (0xFF000000uL)
+
+#define INTC_ICDIPR48_INTIICSPI0 (0x000000FFuL)
+#define INTC_ICDIPR48_INTIICSTI0 (0x0000FF00uL)
+#define INTC_ICDIPR48_INTIICNAKI0 (0x00FF0000uL)
+#define INTC_ICDIPR48_INTIICALI0 (0xFF000000uL)
+
+#define INTC_ICDIPR49_INTIICTMOI0 (0x000000FFuL)
+#define INTC_ICDIPR49_INTIICTEI1 (0x0000FF00uL)
+#define INTC_ICDIPR49_INTIICRI1 (0x00FF0000uL)
+#define INTC_ICDIPR49_INTIICTI1 (0xFF000000uL)
+
+#define INTC_ICDIPR50_INTIICSPI1 (0x000000FFuL)
+#define INTC_ICDIPR50_INTIICSTI1 (0x0000FF00uL)
+#define INTC_ICDIPR50_INTIICNAKI1 (0x00FF0000uL)
+#define INTC_ICDIPR50_INTIICALI1 (0xFF000000uL)
+
+#define INTC_ICDIPR51_INTIICTMOI1 (0x000000FFuL)
+#define INTC_ICDIPR51_INTIICTEI2 (0x0000FF00uL)
+#define INTC_ICDIPR51_INTIICRI2 (0x00FF0000uL)
+#define INTC_ICDIPR51_INTIICTI2 (0xFF000000uL)
+
+#define INTC_ICDIPR52_INTIICSPI2 (0x000000FFuL)
+#define INTC_ICDIPR52_INTIICSTI2 (0x0000FF00uL)
+#define INTC_ICDIPR52_INTIICNAKI2 (0x00FF0000uL)
+#define INTC_ICDIPR52_INTIICALI2 (0xFF000000uL)
+
+#define INTC_ICDIPR53_INTIICTMOI2 (0x000000FFuL)
+#define INTC_ICDIPR53_INTIICTEI3 (0x0000FF00uL)
+#define INTC_ICDIPR53_INTIICRI3 (0x00FF0000uL)
+#define INTC_ICDIPR53_INTIICTI3 (0xFF000000uL)
+
+#define INTC_ICDIPR54_INTIICSPI3 (0x000000FFuL)
+#define INTC_ICDIPR54_INTIICSTI3 (0x0000FF00uL)
+#define INTC_ICDIPR54_INTIICNAKI3 (0x00FF0000uL)
+#define INTC_ICDIPR54_INTIICALI3 (0xFF000000uL)
+
+#define INTC_ICDIPR55_INTIICTMOI3 (0x000000FFuL)
+#define INTC_ICDIPR55_BRI0 (0x0000FF00uL)
+#define INTC_ICDIPR55_ERI0 (0x00FF0000uL)
+#define INTC_ICDIPR55_RXI0 (0xFF000000uL)
+
+#define INTC_ICDIPR56_TXI0 (0x000000FFuL)
+#define INTC_ICDIPR56_BRI1 (0x0000FF00uL)
+#define INTC_ICDIPR56_ERI1 (0x00FF0000uL)
+#define INTC_ICDIPR56_RXI1 (0xFF000000uL)
+
+#define INTC_ICDIPR57_TXI1 (0x000000FFuL)
+#define INTC_ICDIPR57_BRI2 (0x0000FF00uL)
+#define INTC_ICDIPR57_ERI2 (0x00FF0000uL)
+#define INTC_ICDIPR57_RXI2 (0xFF000000uL)
+
+#define INTC_ICDIPR58_TXI2 (0x000000FFuL)
+#define INTC_ICDIPR58_BRI3 (0x0000FF00uL)
+#define INTC_ICDIPR58_ERI3 (0x00FF0000uL)
+#define INTC_ICDIPR58_RXI3 (0xFF000000uL)
+
+#define INTC_ICDIPR59_TXI3 (0x000000FFuL)
+#define INTC_ICDIPR59_BRI4 (0x0000FF00uL)
+#define INTC_ICDIPR59_ERI4 (0x00FF0000uL)
+#define INTC_ICDIPR59_RXI4 (0xFF000000uL)
+
+#define INTC_ICDIPR60_TXI4 (0x000000FFuL)
+#define INTC_ICDIPR60_BRI5 (0x0000FF00uL)
+#define INTC_ICDIPR60_ERI5 (0x00FF0000uL)
+#define INTC_ICDIPR60_RXI5 (0xFF000000uL)
+
+#define INTC_ICDIPR61_TXI5 (0x000000FFuL)
+#define INTC_ICDIPR61_BRI6 (0x0000FF00uL)
+#define INTC_ICDIPR61_ERI6 (0x00FF0000uL)
+#define INTC_ICDIPR61_RXI6 (0xFF000000uL)
+
+#define INTC_ICDIPR62_TXI6 (0x000000FFuL)
+#define INTC_ICDIPR62_BRI7 (0x0000FF00uL)
+#define INTC_ICDIPR62_ERI7 (0x00FF0000uL)
+#define INTC_ICDIPR62_RXI7 (0xFF000000uL)
+
+#define INTC_ICDIPR63_TXI7 (0x000000FFuL)
+#define INTC_ICDIPR63_INTRCANGERR (0x0000FF00uL)
+#define INTC_ICDIPR63_INTRCANGRECC (0x00FF0000uL)
+#define INTC_ICDIPR63_INTRCAN0REC (0xFF000000uL)
+
+#define INTC_ICDIPR64_INTRCAN0ERR (0x000000FFuL)
+#define INTC_ICDIPR64_INTRCAN0TRX (0x0000FF00uL)
+#define INTC_ICDIPR64_INTRCAN1REC (0x00FF0000uL)
+#define INTC_ICDIPR64_INTRCAN1ERR (0xFF000000uL)
+
+#define INTC_ICDIPR65_INTRCAN1TRX (0x000000FFuL)
+#define INTC_ICDIPR65_INTRCAN2REC (0x0000FF00uL)
+#define INTC_ICDIPR65_INTRCAN2ERR (0x00FF0000uL)
+#define INTC_ICDIPR65_INTRCAN2TRX (0xFF000000uL)
+
+#define INTC_ICDIPR66_INTRCAN3REC (0x000000FFuL)
+#define INTC_ICDIPR66_INTRCAN3ERR (0x0000FF00uL)
+#define INTC_ICDIPR66_INTRCAN3TRX (0x00FF0000uL)
+#define INTC_ICDIPR66_INTRCAN4REC (0xFF000000uL)
+
+#define INTC_ICDIPR67_INTRCAN4ERR (0x000000FFuL)
+#define INTC_ICDIPR67_INTRCAN4TRX (0x0000FF00uL)
+#define INTC_ICDIPR67_SPEI0 (0x00FF0000uL)
+#define INTC_ICDIPR67_SPRI0 (0xFF000000uL)
+
+#define INTC_ICDIPR68_SPTI0 (0x000000FFuL)
+#define INTC_ICDIPR68_SPEI1 (0x0000FF00uL)
+#define INTC_ICDIPR68_SPRI1 (0x00FF0000uL)
+#define INTC_ICDIPR68_SPTI1 (0xFF000000uL)
+
+#define INTC_ICDIPR69_SPEI2 (0x000000FFuL)
+#define INTC_ICDIPR69_SPRI2 (0x0000FF00uL)
+#define INTC_ICDIPR69_SPTI2 (0x00FF0000uL)
+#define INTC_ICDIPR69_SPEI3 (0xFF000000uL)
+
+#define INTC_ICDIPR70_SPRI3 (0x000000FFuL)
+#define INTC_ICDIPR70_SPTI3 (0x0000FF00uL)
+#define INTC_ICDIPR70_SPEI4 (0x00FF0000uL)
+#define INTC_ICDIPR70_SPRI4 (0xFF000000uL)
+
+#define INTC_ICDIPR71_SPTI4 (0x000000FFuL)
+#define INTC_ICDIPR71_IEBBTD (0x0000FF00uL)
+#define INTC_ICDIPR71_IEBBTERR (0x00FF0000uL)
+#define INTC_ICDIPR71_IEBBTSTA (0xFF000000uL)
+
+#define INTC_ICDIPR72_IEBBTV (0x000000FFuL)
+#define INTC_ICDIPR72_ISY (0x0000FF00uL)
+#define INTC_ICDIPR72_IERR (0x00FF0000uL)
+#define INTC_ICDIPR72_ITARG (0xFF000000uL)
+
+#define INTC_ICDIPR73_ISEC (0x000000FFuL)
+#define INTC_ICDIPR73_IBUF (0x0000FF00uL)
+#define INTC_ICDIPR73_IREADY (0x00FF0000uL)
+#define INTC_ICDIPR73_FLSTE (0xFF000000uL)
+
+#define INTC_ICDIPR74_FLTENDI (0x000000FFuL)
+#define INTC_ICDIPR74_FLTREQ0I (0x0000FF00uL)
+#define INTC_ICDIPR74_FLTREQ1I (0x00FF0000uL)
+#define INTC_ICDIPR74_MMC0 (0xFF000000uL)
+
+#define INTC_ICDIPR75_MMC1 (0x000000FFuL)
+#define INTC_ICDIPR75_MMC2 (0x0000FF00uL)
+#define INTC_ICDIPR75_SDHI0_3 (0x00FF0000uL)
+#define INTC_ICDIPR75_SDHI0_0 (0xFF000000uL)
+
+#define INTC_ICDIPR76_SDHI0_1 (0x000000FFuL)
+#define INTC_ICDIPR76_SDHI1_3 (0x0000FF00uL)
+#define INTC_ICDIPR76_SDHI1_0 (0x00FF0000uL)
+#define INTC_ICDIPR76_SDHI1_1 (0xFF000000uL)
+
+#define INTC_ICDIPR77_ARM (0x000000FFuL)
+#define INTC_ICDIPR77_PRD (0x0000FF00uL)
+#define INTC_ICDIPR77_CUP (0x00FF0000uL)
+#define INTC_ICDIPR77_SCUAI0 (0xFF000000uL)
+
+#define INTC_ICDIPR78_SCUAI1 (0x000000FFuL)
+#define INTC_ICDIPR78_SCUFDI0 (0x0000FF00uL)
+#define INTC_ICDIPR78_SCUFDI1 (0x00FF0000uL)
+#define INTC_ICDIPR78_SCUFDI2 (0xFF000000uL)
+
+#define INTC_ICDIPR79_SCUFDI3 (0x000000FFuL)
+#define INTC_ICDIPR79_SCUFUI0 (0x0000FF00uL)
+#define INTC_ICDIPR79_SCUFUI1 (0x00FF0000uL)
+#define INTC_ICDIPR79_SCUFUI2 (0xFF000000uL)
+
+#define INTC_ICDIPR80_SCUFUI3 (0x000000FFuL)
+#define INTC_ICDIPR80_SCUDVI0 (0x0000FF00uL)
+#define INTC_ICDIPR80_SCUDVI1 (0x00FF0000uL)
+#define INTC_ICDIPR80_SCUDVI2 (0xFF000000uL)
+
+#define INTC_ICDIPR81_SCUDVI3 (0x000000FFuL)
+#define INTC_ICDIPR81_MLB_CINT (0x0000FF00uL)
+#define INTC_ICDIPR81_MLB_SINT (0x00FF0000uL)
+#define INTC_ICDIPR81_DRC0 (0xFF000000uL)
+
+#define INTC_ICDIPR82_DRC1 (0x000000FFuL)
+#define INTC_ICDIPR82_LINI0_INT_T (0xFF000000uL)
+
+#define INTC_ICDIPR83_LINI0_INT_R (0x000000FFuL)
+#define INTC_ICDIPR83_LINI0_INT_S (0x0000FF00uL)
+#define INTC_ICDIPR83_LINI0_INT_M (0x00FF0000uL)
+#define INTC_ICDIPR83_LINI1_INT_T (0xFF000000uL)
+
+#define INTC_ICDIPR84_LINI1_INT_R (0x000000FFuL)
+#define INTC_ICDIPR84_LINI1_INT_S (0x0000FF00uL)
+#define INTC_ICDIPR84_LINI1_INT_M (0x00FF0000uL)
+
+#define INTC_ICDIPR86_ERI0 (0xFF000000uL)
+
+#define INTC_ICDIPR87_RXI0 (0x000000FFuL)
+#define INTC_ICDIPR87_TXI0 (0x0000FF00uL)
+#define INTC_ICDIPR87_TEI0 (0x00FF0000uL)
+#define INTC_ICDIPR87_ERI1 (0xFF000000uL)
+
+#define INTC_ICDIPR88_RXI1 (0x000000FFuL)
+#define INTC_ICDIPR88_TXI1 (0x0000FF00uL)
+#define INTC_ICDIPR88_TEI1 (0x00FF0000uL)
+#define INTC_ICDIPR88_AVBI_DATA (0xFF000000uL)
+
+#define INTC_ICDIPR89_AVBI_ERROR (0x000000FFuL)
+#define INTC_ICDIPR89_AVBI_MANAGE (0x0000FF00uL)
+#define INTC_ICDIPR89_AVBI_MAC (0x00FF0000uL)
+#define INTC_ICDIPR89_ETHERI (0xFF000000uL)
+
+#define INTC_ICDIPR91_CEUI (0x000000FFuL)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPR95_H2XIC1_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT (0x000000FFuL)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT (0x000000FFuL)
+#define INTC_ICDIPR97_X2HBSC_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPR98_PRRI (0x000000FFuL)
+#define INTC_ICDIPR98_IFEI0 (0x0000FF00uL)
+#define INTC_ICDIPR98_OFFI0 (0x00FF0000uL)
+#define INTC_ICDIPR98_PFVEI0 (0xFF000000uL)
+
+#define INTC_ICDIPR99_IFEI1 (0x000000FFuL)
+#define INTC_ICDIPR99_OFFI1 (0x0000FF00uL)
+#define INTC_ICDIPR99_PFVEI1 (0x00FF0000uL)
+
+#define INTC_ICDIPR104_TINT0 (0x000000FFuL)
+#define INTC_ICDIPR104_TINT1 (0x0000FF00uL)
+#define INTC_ICDIPR104_TINT2 (0x00FF0000uL)
+#define INTC_ICDIPR104_TINT3 (0xFF000000uL)
+
+#define INTC_ICDIPR105_TINT4 (0x000000FFuL)
+#define INTC_ICDIPR105_TINT5 (0x0000FF00uL)
+#define INTC_ICDIPR105_TINT6 (0x00FF0000uL)
+#define INTC_ICDIPR105_TINT7 (0xFF000000uL)
+
+#define INTC_ICDIPR106_TINT8 (0x000000FFuL)
+#define INTC_ICDIPR106_TINT9 (0x0000FF00uL)
+#define INTC_ICDIPR106_TINT10 (0x00FF0000uL)
+#define INTC_ICDIPR106_TINT11 (0xFF000000uL)
+
+#define INTC_ICDIPR107_TINT12 (0x000000FFuL)
+#define INTC_ICDIPR107_TINT13 (0x0000FF00uL)
+#define INTC_ICDIPR107_TINT14 (0x00FF0000uL)
+#define INTC_ICDIPR107_TINT15 (0xFF000000uL)
+
+#define INTC_ICDIPR108_TINT16 (0x000000FFuL)
+#define INTC_ICDIPR108_TINT17 (0x0000FF00uL)
+#define INTC_ICDIPR108_TINT18 (0x00FF0000uL)
+#define INTC_ICDIPR108_TINT19 (0xFF000000uL)
+
+#define INTC_ICDIPR109_TINT20 (0x000000FFuL)
+#define INTC_ICDIPR109_TINT21 (0x0000FF00uL)
+#define INTC_ICDIPR109_TINT22 (0x00FF0000uL)
+#define INTC_ICDIPR109_TINT23 (0xFF000000uL)
+
+#define INTC_ICDIPR110_TINT24 (0x000000FFuL)
+#define INTC_ICDIPR110_TINT25 (0x0000FF00uL)
+#define INTC_ICDIPR110_TINT26 (0x00FF0000uL)
+#define INTC_ICDIPR110_TINT27 (0xFF000000uL)
+
+#define INTC_ICDIPR111_TINT28 (0x000000FFuL)
+#define INTC_ICDIPR111_TINT29 (0x0000FF00uL)
+#define INTC_ICDIPR111_TINT30 (0x00FF0000uL)
+#define INTC_ICDIPR111_TINT31 (0xFF000000uL)
+
+#define INTC_ICDIPR112_TINT32 (0x000000FFuL)
+#define INTC_ICDIPR112_TINT33 (0x0000FF00uL)
+#define INTC_ICDIPR112_TINT34 (0x00FF0000uL)
+#define INTC_ICDIPR112_TINT35 (0xFF000000uL)
+
+#define INTC_ICDIPR113_TINT36 (0x000000FFuL)
+#define INTC_ICDIPR113_TINT37 (0x0000FF00uL)
+#define INTC_ICDIPR113_TINT38 (0x00FF0000uL)
+#define INTC_ICDIPR113_TINT39 (0xFF000000uL)
+
+#define INTC_ICDIPR114_TINT40 (0x000000FFuL)
+#define INTC_ICDIPR114_TINT41 (0x0000FF00uL)
+#define INTC_ICDIPR114_TINT42 (0x00FF0000uL)
+#define INTC_ICDIPR114_TINT43 (0xFF000000uL)
+
+#define INTC_ICDIPR115_TINT44 (0x000000FFuL)
+#define INTC_ICDIPR115_TINT45 (0x0000FF00uL)
+#define INTC_ICDIPR115_TINT46 (0x00FF0000uL)
+#define INTC_ICDIPR115_TINT47 (0xFF000000uL)
+
+#define INTC_ICDIPR116_TINT48 (0x000000FFuL)
+#define INTC_ICDIPR116_TINT49 (0x0000FF00uL)
+#define INTC_ICDIPR116_TINT50 (0x00FF0000uL)
+#define INTC_ICDIPR116_TINT51 (0xFF000000uL)
+
+#define INTC_ICDIPR117_TINT52 (0x000000FFuL)
+#define INTC_ICDIPR117_TINT53 (0x0000FF00uL)
+#define INTC_ICDIPR117_TINT54 (0x00FF0000uL)
+#define INTC_ICDIPR117_TINT55 (0xFF000000uL)
+
+#define INTC_ICDIPR118_TINT56 (0x000000FFuL)
+#define INTC_ICDIPR118_TINT57 (0x0000FF00uL)
+#define INTC_ICDIPR118_TINT58 (0x00FF0000uL)
+#define INTC_ICDIPR118_TINT59 (0xFF000000uL)
+
+#define INTC_ICDIPR119_TINT60 (0x000000FFuL)
+#define INTC_ICDIPR119_TINT61 (0x0000FF00uL)
+#define INTC_ICDIPR119_TINT62 (0x00FF0000uL)
+#define INTC_ICDIPR119_TINT63 (0xFF000000uL)
+
+#define INTC_ICDIPR120_TINT64 (0x000000FFuL)
+#define INTC_ICDIPR120_TINT65 (0x0000FF00uL)
+#define INTC_ICDIPR120_TINT66 (0x00FF0000uL)
+#define INTC_ICDIPR120_TINT67 (0xFF000000uL)
+
+#define INTC_ICDIPR121_TINT68 (0x000000FFuL)
+#define INTC_ICDIPR121_TINT69 (0x0000FF00uL)
+#define INTC_ICDIPR121_TINT70 (0x00FF0000uL)
+#define INTC_ICDIPR121_TINT71 (0xFF000000uL)
+
+#define INTC_ICDIPR122_TINT72 (0x000000FFuL)
+#define INTC_ICDIPR122_TINT73 (0x0000FF00uL)
+#define INTC_ICDIPR122_TINT74 (0x00FF0000uL)
+#define INTC_ICDIPR122_TINT75 (0xFF000000uL)
+
+#define INTC_ICDIPR123_TINT76 (0x000000FFuL)
+#define INTC_ICDIPR123_TINT77 (0x0000FF00uL)
+#define INTC_ICDIPR123_TINT78 (0x00FF0000uL)
+#define INTC_ICDIPR123_TINT79 (0xFF000000uL)
+
+#define INTC_ICDIPR124_TINT80 (0x000000FFuL)
+#define INTC_ICDIPR124_TINT81 (0x0000FF00uL)
+#define INTC_ICDIPR124_TINT82 (0x00FF0000uL)
+#define INTC_ICDIPR124_TINT83 (0xFF000000uL)
+
+#define INTC_ICDIPR125_TINT84 (0x000000FFuL)
+#define INTC_ICDIPR125_TINT85 (0x0000FF00uL)
+#define INTC_ICDIPR125_TINT86 (0x00FF0000uL)
+#define INTC_ICDIPR125_TINT87 (0xFF000000uL)
+
+#define INTC_ICDIPR126_TINT88 (0x000000FFuL)
+#define INTC_ICDIPR126_TINT89 (0x0000FF00uL)
+#define INTC_ICDIPR126_TINT90 (0x00FF0000uL)
+#define INTC_ICDIPR126_TINT91 (0xFF000000uL)
+
+#define INTC_ICDIPR127_TINT92 (0x000000FFuL)
+#define INTC_ICDIPR127_TINT93 (0x0000FF00uL)
+#define INTC_ICDIPR127_TINT94 (0x00FF0000uL)
+#define INTC_ICDIPR127_TINT95 (0xFF000000uL)
+
+#define INTC_ICDIPR128_TINT96 (0x000000FFuL)
+#define INTC_ICDIPR128_TINT97 (0x0000FF00uL)
+#define INTC_ICDIPR128_TINT98 (0x00FF0000uL)
+#define INTC_ICDIPR128_TINT99 (0xFF000000uL)
+
+#define INTC_ICDIPR129_TINT100 (0x000000FFuL)
+#define INTC_ICDIPR129_TINT101 (0x0000FF00uL)
+#define INTC_ICDIPR129_TINT102 (0x00FF0000uL)
+#define INTC_ICDIPR129_TINT103 (0xFF000000uL)
+
+#define INTC_ICDIPR130_TINT104 (0x000000FFuL)
+#define INTC_ICDIPR130_TINT105 (0x0000FF00uL)
+#define INTC_ICDIPR130_TINT106 (0x00FF0000uL)
+#define INTC_ICDIPR130_TINT107 (0xFF000000uL)
+
+#define INTC_ICDIPR131_TINT108 (0x000000FFuL)
+#define INTC_ICDIPR131_TINT109 (0x0000FF00uL)
+#define INTC_ICDIPR131_TINT110 (0x00FF0000uL)
+#define INTC_ICDIPR131_TINT111 (0xFF000000uL)
+
+#define INTC_ICDIPR132_TINT112 (0x000000FFuL)
+#define INTC_ICDIPR132_TINT113 (0x0000FF00uL)
+#define INTC_ICDIPR132_TINT114 (0x00FF0000uL)
+#define INTC_ICDIPR132_TINT115 (0xFF000000uL)
+
+#define INTC_ICDIPR133_TINT116 (0x000000FFuL)
+#define INTC_ICDIPR133_TINT117 (0x0000FF00uL)
+#define INTC_ICDIPR133_TINT118 (0x00FF0000uL)
+#define INTC_ICDIPR133_TINT119 (0xFF000000uL)
+
+#define INTC_ICDIPR134_TINT120 (0x000000FFuL)
+#define INTC_ICDIPR134_TINT121 (0x0000FF00uL)
+#define INTC_ICDIPR134_TINT122 (0x00FF0000uL)
+#define INTC_ICDIPR134_TINT123 (0xFF000000uL)
+
+#define INTC_ICDIPR135_TINT124 (0x000000FFuL)
+#define INTC_ICDIPR135_TINT125 (0x0000FF00uL)
+#define INTC_ICDIPR135_TINT126 (0x00FF0000uL)
+#define INTC_ICDIPR135_TINT127 (0xFF000000uL)
+
+#define INTC_ICDIPR136_TINT128 (0x000000FFuL)
+#define INTC_ICDIPR136_TINT129 (0x0000FF00uL)
+#define INTC_ICDIPR136_TINT130 (0x00FF0000uL)
+#define INTC_ICDIPR136_TINT131 (0xFF000000uL)
+
+#define INTC_ICDIPR137_TINT132 (0x000000FFuL)
+#define INTC_ICDIPR137_TINT133 (0x0000FF00uL)
+#define INTC_ICDIPR137_TINT134 (0x00FF0000uL)
+#define INTC_ICDIPR137_TINT135 (0xFF000000uL)
+
+#define INTC_ICDIPR138_TINT136 (0x000000FFuL)
+#define INTC_ICDIPR138_TINT137 (0x0000FF00uL)
+#define INTC_ICDIPR138_TINT138 (0x00FF0000uL)
+#define INTC_ICDIPR138_TINT139 (0xFF000000uL)
+
+#define INTC_ICDIPR139_TINT140 (0x000000FFuL)
+#define INTC_ICDIPR139_TINT141 (0x0000FF00uL)
+#define INTC_ICDIPR139_TINT142 (0x00FF0000uL)
+#define INTC_ICDIPR139_TINT143 (0xFF000000uL)
+
+#define INTC_ICDIPR140_TINT144 (0x000000FFuL)
+#define INTC_ICDIPR140_TINT145 (0x0000FF00uL)
+#define INTC_ICDIPR140_TINT146 (0x00FF0000uL)
+#define INTC_ICDIPR140_TINT147 (0xFF000000uL)
+
+#define INTC_ICDIPR141_TINT148 (0x000000FFuL)
+#define INTC_ICDIPR141_TINT149 (0x0000FF00uL)
+#define INTC_ICDIPR141_TINT150 (0x00FF0000uL)
+#define INTC_ICDIPR141_TINT151 (0xFF000000uL)
+
+#define INTC_ICDIPR142_TINT152 (0x000000FFuL)
+#define INTC_ICDIPR142_TINT153 (0x0000FF00uL)
+#define INTC_ICDIPR142_TINT154 (0x00FF0000uL)
+#define INTC_ICDIPR142_TINT155 (0xFF000000uL)
+
+#define INTC_ICDIPR143_TINT156 (0x000000FFuL)
+#define INTC_ICDIPR143_TINT157 (0x0000FF00uL)
+#define INTC_ICDIPR143_TINT158 (0x00FF0000uL)
+#define INTC_ICDIPR143_TINT159 (0xFF000000uL)
+
+#define INTC_ICDIPR144_TINT160 (0x000000FFuL)
+#define INTC_ICDIPR144_TINT161 (0x0000FF00uL)
+#define INTC_ICDIPR144_TINT162 (0x00FF0000uL)
+#define INTC_ICDIPR144_TINT163 (0xFF000000uL)
+
+#define INTC_ICDIPR145_TINT164 (0x000000FFuL)
+#define INTC_ICDIPR145_TINT165 (0x0000FF00uL)
+#define INTC_ICDIPR145_TINT166 (0x00FF0000uL)
+#define INTC_ICDIPR145_TINT167 (0xFF000000uL)
+
+#define INTC_ICDIPR146_TINT168 (0x000000FFuL)
+#define INTC_ICDIPR146_TINT169 (0x0000FF00uL)
+#define INTC_ICDIPR146_TINT170 (0x00FF0000uL)
+
+#define INTC_ICDIPTR0_SW0 (0x000000FFuL)
+#define INTC_ICDIPTR0_SW1 (0x0000FF00uL)
+#define INTC_ICDIPTR0_SW2 (0x00FF0000uL)
+#define INTC_ICDIPTR0_SW3 (0xFF000000uL)
+
+#define INTC_ICDIPTR1_SW4 (0x000000FFuL)
+#define INTC_ICDIPTR1_SW5 (0x0000FF00uL)
+#define INTC_ICDIPTR1_SW6 (0x00FF0000uL)
+#define INTC_ICDIPTR1_SW7 (0xFF000000uL)
+
+#define INTC_ICDIPTR2_SW8 (0x000000FFuL)
+#define INTC_ICDIPTR2_SW9 (0x0000FF00uL)
+#define INTC_ICDIPTR2_SW10 (0x00FF0000uL)
+#define INTC_ICDIPTR2_SW11 (0xFF000000uL)
+
+#define INTC_ICDIPTR3_SW12 (0x000000FFuL)
+#define INTC_ICDIPTR3_SW13 (0x0000FF00uL)
+#define INTC_ICDIPTR3_SW14 (0x00FF0000uL)
+#define INTC_ICDIPTR3_SW15 (0xFF000000uL)
+
+#define INTC_ICDIPTR4_PMUIRQ0 (0x000000FFuL)
+#define INTC_ICDIPTR4_COMMRX0 (0x0000FF00uL)
+#define INTC_ICDIPTR4_COMMTX0 (0x00FF0000uL)
+#define INTC_ICDIPTR4_CTIIRQ0 (0xFF000000uL)
+
+#define INTC_ICDIPTR8_IRQ0 (0x000000FFuL)
+#define INTC_ICDIPTR8_IRQ1 (0x0000FF00uL)
+#define INTC_ICDIPTR8_IRQ2 (0x00FF0000uL)
+#define INTC_ICDIPTR8_IRQ3 (0xFF000000uL)
+
+#define INTC_ICDIPTR9_IRQ4 (0x000000FFuL)
+#define INTC_ICDIPTR9_IRQ5 (0x0000FF00uL)
+#define INTC_ICDIPTR9_IRQ6 (0x00FF0000uL)
+#define INTC_ICDIPTR9_IRQ7 (0xFF000000uL)
+
+#define INTC_ICDIPTR10_PL310ERR (0x000000FFuL)
+#define INTC_ICDIPTR10_DMAINT0 (0x0000FF00uL)
+#define INTC_ICDIPTR10_DMAINT1 (0x00FF0000uL)
+#define INTC_ICDIPTR10_DMAINT2 (0xFF000000uL)
+
+#define INTC_ICDIPTR11_DMAINT3 (0x000000FFuL)
+#define INTC_ICDIPTR11_DMAINT4 (0x0000FF00uL)
+#define INTC_ICDIPTR11_DMAINT5 (0x00FF0000uL)
+#define INTC_ICDIPTR11_DMAINT6 (0xFF000000uL)
+
+#define INTC_ICDIPTR12_DMAINT7 (0x000000FFuL)
+#define INTC_ICDIPTR12_DMAINT8 (0x0000FF00uL)
+#define INTC_ICDIPTR12_DMAINT9 (0x00FF0000uL)
+#define INTC_ICDIPTR12_DMAINT10 (0xFF000000uL)
+
+#define INTC_ICDIPTR13_DMAINT11 (0x000000FFuL)
+#define INTC_ICDIPTR13_DMAINT12 (0x0000FF00uL)
+#define INTC_ICDIPTR13_DMAINT13 (0x00FF0000uL)
+#define INTC_ICDIPTR13_DMAINT14 (0xFF000000uL)
+
+#define INTC_ICDIPTR14_DMAINT15 (0x000000FFuL)
+#define INTC_ICDIPTR14_DMAERR (0x0000FF00uL)
+
+#define INTC_ICDIPTR18_USBI0 (0x0000FF00uL)
+#define INTC_ICDIPTR18_USBI1 (0x00FF0000uL)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0 (0xFF000000uL)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0 (0x000000FFuL)
+#define INTC_ICDIPTR19_S0_VSYNCERR0 (0x0000FF00uL)
+#define INTC_ICDIPTR19_GR3_VLINE0 (0x00FF0000uL)
+#define INTC_ICDIPTR19_S0_VFIELD0 (0xFF000000uL)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0 (0x000000FFuL)
+#define INTC_ICDIPTR20_IV3_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPTR20_IV5_VBUFERR0 (0x00FF0000uL)
+#define INTC_ICDIPTR20_IV6_VBUFERR0 (0xFF000000uL)
+
+#define INTC_ICDIPTR21_S0_WLINE0 (0x000000FFuL)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0 (0x0000FF00uL)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0 (0x00FF0000uL)
+#define INTC_ICDIPTR21_S1_VSYNCERR0 (0xFF000000uL)
+
+#define INTC_ICDIPTR22_S1_VFIELD0 (0x000000FFuL)
+#define INTC_ICDIPTR22_IV2_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPTR22_IV4_VBUFERR0 (0x00FF0000uL)
+#define INTC_ICDIPTR22_S1_WLINE0 (0xFF000000uL)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0 (0x000000FFuL)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0 (0x0000FF00uL)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0 (0x00FF0000uL)
+#define INTC_ICDIPTR23_OIR_VFIELD0 (0xFF000000uL)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0 (0x000000FFuL)
+#define INTC_ICDIPTR24_IV8_VBUFERR0 (0x0000FF00uL)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1 (0xFF000000uL)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1 (0x000000FFuL)
+#define INTC_ICDIPTR25_S0_VSYNCERR1 (0x0000FF00uL)
+#define INTC_ICDIPTR25_GR3_VLINE1 (0x00FF0000uL)
+#define INTC_ICDIPTR25_S0_VFIELD1 (0xFF000000uL)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1 (0x000000FFuL)
+#define INTC_ICDIPTR26_IV3_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPTR26_IV5_VBUFERR1 (0x00FF0000uL)
+#define INTC_ICDIPTR26_IV6_VBUFERR1 (0xFF000000uL)
+
+#define INTC_ICDIPTR27_S0_WLINE1 (0x000000FFuL)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1 (0x0000FF00uL)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1 (0x00FF0000uL)
+#define INTC_ICDIPTR27_S1_VSYNCERR1 (0xFF000000uL)
+
+#define INTC_ICDIPTR28_S1_VFIELD1 (0x000000FFuL)
+#define INTC_ICDIPTR28_IV2_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPTR28_IV4_VBUFERR1 (0x00FF0000uL)
+#define INTC_ICDIPTR28_S1_WLINE1 (0xFF000000uL)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1 (0x000000FFuL)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1 (0x0000FF00uL)
+#define INTC_ICDIPTR29_OIR_VLINE1 (0x00FF0000uL)
+#define INTC_ICDIPTR29_OIR_VFIELD1 (0xFF000000uL)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1 (0x000000FFuL)
+#define INTC_ICDIPTR30_IV8_VBUFERR1 (0x0000FF00uL)
+#define INTC_ICDIPTR30_IMRDI (0xFF000000uL)
+
+#define INTC_ICDIPTR31_IMR2I0 (0x000000FFuL)
+#define INTC_ICDIPTR31_IMR2I1 (0x0000FF00uL)
+#define INTC_ICDIPTR31_JEDI (0x00FF0000uL)
+#define INTC_ICDIPTR31_JDTI (0xFF000000uL)
+
+#define INTC_ICDIPTR32_CMP0 (0x000000FFuL)
+#define INTC_ICDIPTR32_CMP1 (0x0000FF00uL)
+#define INTC_ICDIPTR32_INT0 (0x00FF0000uL)
+#define INTC_ICDIPTR32_INT1 (0xFF000000uL)
+
+#define INTC_ICDIPTR33_INT2 (0x000000FFuL)
+#define INTC_ICDIPTR33_INT3 (0x0000FF00uL)
+#define INTC_ICDIPTR33_OSTM0TINT (0x00FF0000uL)
+#define INTC_ICDIPTR33_OSTM1TINT (0xFF000000uL)
+
+#define INTC_ICDIPTR34_CMI (0x000000FFuL)
+#define INTC_ICDIPTR34_WTOUT (0x0000FF00uL)
+#define INTC_ICDIPTR34_ITI (0x00FF0000uL)
+#define INTC_ICDIPTR34_TGI0A (0xFF000000uL)
+
+#define INTC_ICDIPTR35_TGI0B (0x000000FFuL)
+#define INTC_ICDIPTR35_TGI0C (0x0000FF00uL)
+#define INTC_ICDIPTR35_TGI0D (0x00FF0000uL)
+#define INTC_ICDIPTR35_TGI0V (0xFF000000uL)
+
+#define INTC_ICDIPTR36_TGI0E (0x000000FFuL)
+#define INTC_ICDIPTR36_TGI0F (0x0000FF00uL)
+#define INTC_ICDIPTR36_TGI1A (0x00FF0000uL)
+#define INTC_ICDIPTR36_TGI1B (0xFF000000uL)
+
+#define INTC_ICDIPTR37_TGI1V (0x000000FFuL)
+#define INTC_ICDIPTR37_TGI1U (0x0000FF00uL)
+#define INTC_ICDIPTR37_TGI2A (0x00FF0000uL)
+#define INTC_ICDIPTR37_TGI2B (0xFF000000uL)
+
+#define INTC_ICDIPTR38_TGI2V (0x000000FFuL)
+#define INTC_ICDIPTR38_TGI2U (0x0000FF00uL)
+#define INTC_ICDIPTR38_TGI3A (0x00FF0000uL)
+#define INTC_ICDIPTR38_TGI3B (0xFF000000uL)
+
+#define INTC_ICDIPTR39_TGI3C (0x000000FFuL)
+#define INTC_ICDIPTR39_TGI3D (0x0000FF00uL)
+#define INTC_ICDIPTR39_TGI3V (0x00FF0000uL)
+#define INTC_ICDIPTR39_TGI4A (0xFF000000uL)
+
+#define INTC_ICDIPTR40_TGI4B (0x000000FFuL)
+#define INTC_ICDIPTR40_TGI4C (0x0000FF00uL)
+#define INTC_ICDIPTR40_TGI4D (0x00FF0000uL)
+#define INTC_ICDIPTR40_TGI4V (0xFF000000uL)
+
+#define INTC_ICDIPTR41_CMI1 (0x000000FFuL)
+#define INTC_ICDIPTR41_CMI2 (0x0000FF00uL)
+#define INTC_ICDIPTR41_SGDEI0 (0x00FF0000uL)
+#define INTC_ICDIPTR41_SGDEI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR42_SGDEI2 (0x000000FFuL)
+#define INTC_ICDIPTR42_SGDEI3 (0x0000FF00uL)
+#define INTC_ICDIPTR42_ADI (0x00FF0000uL)
+#define INTC_ICDIPTR42_LMTI (0xFF000000uL)
+
+#define INTC_ICDIPTR43_SSII0 (0x000000FFuL)
+#define INTC_ICDIPTR43_SSIRXI0 (0x0000FF00uL)
+#define INTC_ICDIPTR43_SSITXI0 (0x00FF0000uL)
+#define INTC_ICDIPTR43_SSII1 (0xFF000000uL)
+
+#define INTC_ICDIPTR44_SSIRXI1 (0x000000FFuL)
+#define INTC_ICDIPTR44_SSITXI1 (0x0000FF00uL)
+#define INTC_ICDIPTR44_SSII2 (0x00FF0000uL)
+#define INTC_ICDIPTR44_SSIRTI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR45_SSII3 (0x000000FFuL)
+#define INTC_ICDIPTR45_SSIRXI3 (0x0000FF00uL)
+#define INTC_ICDIPTR45_SSITXI3 (0x00FF0000uL)
+#define INTC_ICDIPTR45_SSII4 (0xFF000000uL)
+
+#define INTC_ICDIPTR46_SSIRTI4 (0x000000FFuL)
+#define INTC_ICDIPTR46_SSII5 (0x0000FF00uL)
+#define INTC_ICDIPTR46_SSIRXI5 (0x00FF0000uL)
+#define INTC_ICDIPTR46_SSITXI5 (0xFF000000uL)
+
+#define INTC_ICDIPTR47_SPDIFI (0x000000FFuL)
+#define INTC_ICDIPTR47_INTIICTEI0 (0x0000FF00uL)
+#define INTC_ICDIPTR47_INTIICRI0 (0x00FF0000uL)
+#define INTC_ICDIPTR47_INTIICTI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR48_INTIICSPI0 (0x000000FFuL)
+#define INTC_ICDIPTR48_INTIICSTI0 (0x0000FF00uL)
+#define INTC_ICDIPTR48_INTIICNAKI0 (0x00FF0000uL)
+#define INTC_ICDIPTR48_INTIICALI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR49_INTIICTMOI0 (0x000000FFuL)
+#define INTC_ICDIPTR49_INTIICTEI1 (0x0000FF00uL)
+#define INTC_ICDIPTR49_INTIICRI1 (0x00FF0000uL)
+#define INTC_ICDIPTR49_INTIICTI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR50_INTIICSPI1 (0x000000FFuL)
+#define INTC_ICDIPTR50_INTIICSTI1 (0x0000FF00uL)
+#define INTC_ICDIPTR50_INTIICNAKI1 (0x00FF0000uL)
+#define INTC_ICDIPTR50_INTIICALI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR51_INTIICTMOI1 (0x000000FFuL)
+#define INTC_ICDIPTR51_INTIICTEI2 (0x0000FF00uL)
+#define INTC_ICDIPTR51_INTIICRI2 (0x00FF0000uL)
+#define INTC_ICDIPTR51_INTIICTI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR52_INTIICSPI2 (0x000000FFuL)
+#define INTC_ICDIPTR52_INTIICSTI2 (0x0000FF00uL)
+#define INTC_ICDIPTR52_INTIICNAKI2 (0x00FF0000uL)
+#define INTC_ICDIPTR52_INTIICALI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR53_INTIICTMOI2 (0x000000FFuL)
+#define INTC_ICDIPTR53_INTIICTEI3 (0x0000FF00uL)
+#define INTC_ICDIPTR53_INTIICRI3 (0x00FF0000uL)
+#define INTC_ICDIPTR53_INTIICTI3 (0xFF000000uL)
+
+#define INTC_ICDIPTR54_INTIICSPI3 (0x000000FFuL)
+#define INTC_ICDIPTR54_INTIICSTI3 (0x0000FF00uL)
+#define INTC_ICDIPTR54_INTIICNAKI3 (0x00FF0000uL)
+#define INTC_ICDIPTR54_INTIICALI3 (0xFF000000uL)
+
+#define INTC_ICDIPTR55_INTIICTMOI3 (0x000000FFuL)
+#define INTC_ICDIPTR55_BRI0 (0x0000FF00uL)
+#define INTC_ICDIPTR55_ERI0 (0x00FF0000uL)
+#define INTC_ICDIPTR55_RXI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR56_TXI0 (0x000000FFuL)
+#define INTC_ICDIPTR56_BRI1 (0x0000FF00uL)
+#define INTC_ICDIPTR56_ERI1 (0x00FF0000uL)
+#define INTC_ICDIPTR56_RXI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR57_TXI1 (0x000000FFuL)
+#define INTC_ICDIPTR57_BRI2 (0x0000FF00uL)
+#define INTC_ICDIPTR57_ERI2 (0x00FF0000uL)
+#define INTC_ICDIPTR57_RXI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR58_TXI2 (0x000000FFuL)
+#define INTC_ICDIPTR58_BRI3 (0x0000FF00uL)
+#define INTC_ICDIPTR58_ERI3 (0x00FF0000uL)
+#define INTC_ICDIPTR58_RXI3 (0xFF000000uL)
+
+#define INTC_ICDIPTR59_TXI3 (0x000000FFuL)
+#define INTC_ICDIPTR59_BRI4 (0x0000FF00uL)
+#define INTC_ICDIPTR59_ERI4 (0x00FF0000uL)
+#define INTC_ICDIPTR59_RXI4 (0xFF000000uL)
+
+#define INTC_ICDIPTR60_TXI4 (0x000000FFuL)
+#define INTC_ICDIPTR60_BRI5 (0x0000FF00uL)
+#define INTC_ICDIPTR60_ERI5 (0x00FF0000uL)
+#define INTC_ICDIPTR60_RXI5 (0xFF000000uL)
+
+#define INTC_ICDIPTR61_TXI5 (0x000000FFuL)
+#define INTC_ICDIPTR61_BRI6 (0x0000FF00uL)
+#define INTC_ICDIPTR61_ERI6 (0x00FF0000uL)
+#define INTC_ICDIPTR61_RXI6 (0xFF000000uL)
+
+#define INTC_ICDIPTR62_TXI6 (0x000000FFuL)
+#define INTC_ICDIPTR62_BRI7 (0x0000FF00uL)
+#define INTC_ICDIPTR62_ERI7 (0x00FF0000uL)
+#define INTC_ICDIPTR62_RXI7 (0xFF000000uL)
+
+#define INTC_ICDIPTR63_TXI7 (0x000000FFuL)
+#define INTC_ICDIPTR63_INTRCANGERR (0x0000FF00uL)
+#define INTC_ICDIPTR63_INTRCANGRECC (0x00FF0000uL)
+#define INTC_ICDIPTR63_INTRCAN0REC (0xFF000000uL)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR (0x000000FFuL)
+#define INTC_ICDIPTR64_INTRCAN0TRX (0x0000FF00uL)
+#define INTC_ICDIPTR64_INTRCAN1REC (0x00FF0000uL)
+#define INTC_ICDIPTR64_INTRCAN1ERR (0xFF000000uL)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX (0x000000FFuL)
+#define INTC_ICDIPTR65_INTRCAN2REC (0x0000FF00uL)
+#define INTC_ICDIPTR65_INTRCAN2ERR (0x00FF0000uL)
+#define INTC_ICDIPTR65_INTRCAN2TRX (0xFF000000uL)
+
+#define INTC_ICDIPTR66_INTRCAN3REC (0x000000FFuL)
+#define INTC_ICDIPTR66_INTRCAN3ERR (0x0000FF00uL)
+#define INTC_ICDIPTR66_INTRCAN3TRX (0x00FF0000uL)
+#define INTC_ICDIPTR66_INTRCAN4REC (0xFF000000uL)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR (0x000000FFuL)
+#define INTC_ICDIPTR67_INTRCAN4TRX (0x0000FF00uL)
+#define INTC_ICDIPTR67_SPEI0 (0x00FF0000uL)
+#define INTC_ICDIPTR67_SPRI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR68_SPTI0 (0x000000FFuL)
+#define INTC_ICDIPTR68_SPEI1 (0x0000FF00uL)
+#define INTC_ICDIPTR68_SPRI1 (0x00FF0000uL)
+#define INTC_ICDIPTR68_SPTI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR69_SPEI2 (0x000000FFuL)
+#define INTC_ICDIPTR69_SPRI2 (0x0000FF00uL)
+#define INTC_ICDIPTR69_SPTI2 (0x00FF0000uL)
+#define INTC_ICDIPTR69_SPEI3 (0xFF000000uL)
+
+#define INTC_ICDIPTR70_SPRI3 (0x000000FFuL)
+#define INTC_ICDIPTR70_SPTI3 (0x0000FF00uL)
+#define INTC_ICDIPTR70_SPEI4 (0x00FF0000uL)
+#define INTC_ICDIPTR70_SPRI4 (0xFF000000uL)
+
+#define INTC_ICDIPTR71_SPTI4 (0x000000FFuL)
+#define INTC_ICDIPTR71_IEBBTD (0x0000FF00uL)
+#define INTC_ICDIPTR71_IEBBTERR (0x00FF0000uL)
+#define INTC_ICDIPTR71_IEBBTSTA (0xFF000000uL)
+
+#define INTC_ICDIPTR72_IEBBTV (0x000000FFuL)
+#define INTC_ICDIPTR72_ISY (0x0000FF00uL)
+#define INTC_ICDIPTR72_IERR (0x00FF0000uL)
+#define INTC_ICDIPTR72_ITARG (0xFF000000uL)
+
+#define INTC_ICDIPTR73_ISEC (0x000000FFuL)
+#define INTC_ICDIPTR73_IBUF (0x0000FF00uL)
+#define INTC_ICDIPTR73_IREADY (0x00FF0000uL)
+#define INTC_ICDIPTR73_FLSTE (0xFF000000uL)
+
+#define INTC_ICDIPTR74_FLTENDI (0x000000FFuL)
+#define INTC_ICDIPTR74_FLTREQ0I (0x0000FF00uL)
+#define INTC_ICDIPTR74_FLTREQ1I (0x00FF0000uL)
+#define INTC_ICDIPTR74_MMC0 (0xFF000000uL)
+
+#define INTC_ICDIPTR75_MMC1 (0x000000FFuL)
+#define INTC_ICDIPTR75_MMC2 (0x0000FF00uL)
+#define INTC_ICDIPTR75_SDHI0_3 (0x00FF0000uL)
+#define INTC_ICDIPTR75_SDHI0_0 (0xFF000000uL)
+
+#define INTC_ICDIPTR76_SDHI0_1 (0x000000FFuL)
+#define INTC_ICDIPTR76_SDHI1_3 (0x0000FF00uL)
+#define INTC_ICDIPTR76_SDHI1_0 (0x00FF0000uL)
+#define INTC_ICDIPTR76_SDHI1_1 (0xFF000000uL)
+
+#define INTC_ICDIPTR77_ARM (0x000000FFuL)
+#define INTC_ICDIPTR77_PRD (0x0000FF00uL)
+#define INTC_ICDIPTR77_CUP (0x00FF0000uL)
+#define INTC_ICDIPTR77_SCUAI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR78_SCUAI1 (0x000000FFuL)
+#define INTC_ICDIPTR78_SCUFDI0 (0x0000FF00uL)
+#define INTC_ICDIPTR78_SCUFDI1 (0x00FF0000uL)
+#define INTC_ICDIPTR78_SCUFDI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR79_SCUFDI3 (0x000000FFuL)
+#define INTC_ICDIPTR79_SCUFUI0 (0x0000FF00uL)
+#define INTC_ICDIPTR79_SCUFUI1 (0x00FF0000uL)
+#define INTC_ICDIPTR79_SCUFUI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR80_SCUFUI3 (0x000000FFuL)
+#define INTC_ICDIPTR80_SCUDVI0 (0x0000FF00uL)
+#define INTC_ICDIPTR80_SCUDVI1 (0x00FF0000uL)
+#define INTC_ICDIPTR80_SCUDVI2 (0xFF000000uL)
+
+#define INTC_ICDIPTR81_SCUDVI3 (0x000000FFuL)
+#define INTC_ICDIPTR81_MLB_CINT (0x0000FF00uL)
+#define INTC_ICDIPTR81_MLB_SINT (0x00FF0000uL)
+#define INTC_ICDIPTR81_DRC0 (0xFF000000uL)
+
+#define INTC_ICDIPTR82_DRC1 (0x000000FFuL)
+#define INTC_ICDIPTR82_LINI0_INT_T (0xFF000000uL)
+
+#define INTC_ICDIPTR83_LINI0_INT_R (0x000000FFuL)
+#define INTC_ICDIPTR83_LINI0_INT_S (0x0000FF00uL)
+#define INTC_ICDIPTR83_LINI0_INT_M (0x00FF0000uL)
+#define INTC_ICDIPTR83_LINI1_INT_T (0xFF000000uL)
+
+#define INTC_ICDIPTR84_LINI1_INT_R (0x000000FFuL)
+#define INTC_ICDIPTR84_LINI1_INT_S (0x0000FF00uL)
+#define INTC_ICDIPTR84_LINI1_INT_M (0x00FF0000uL)
+
+#define INTC_ICDIPTR86_ERI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR87_RXI0 (0x000000FFuL)
+#define INTC_ICDIPTR87_TXI0 (0x0000FF00uL)
+#define INTC_ICDIPTR87_TEI0 (0x00FF0000uL)
+#define INTC_ICDIPTR87_ERI1 (0xFF000000uL)
+
+#define INTC_ICDIPTR88_RXI1 (0x000000FFuL)
+#define INTC_ICDIPTR88_TXI1 (0x0000FF00uL)
+#define INTC_ICDIPTR88_TEI1 (0x00FF0000uL)
+#define INTC_ICDIPTR88_AVBI_DATA (0xFF000000uL)
+
+#define INTC_ICDIPTR89_AVBI_ERROR (0x000000FFuL)
+#define INTC_ICDIPTR89_AVBI_MANAGE (0x0000FF00uL)
+#define INTC_ICDIPTR89_AVBI_MAC (0x00FF0000uL)
+#define INTC_ICDIPTR89_ETHERI (0xFF000000uL)
+
+#define INTC_ICDIPTR91_CEUI (0x000000FFuL)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT (0x000000FFuL)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT (0x000000FFuL)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT (0x0000FF00uL)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT (0x00FF0000uL)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT (0xFF000000uL)
+
+#define INTC_ICDIPTR98_PRRI (0x000000FFuL)
+#define INTC_ICDIPTR98_IFEI0 (0x0000FF00uL)
+#define INTC_ICDIPTR98_OFFI0 (0x00FF0000uL)
+#define INTC_ICDIPTR98_PFVEI0 (0xFF000000uL)
+
+#define INTC_ICDIPTR99_IFEI1 (0x000000FFuL)
+#define INTC_ICDIPTR99_OFFI1 (0x0000FF00uL)
+#define INTC_ICDIPTR99_PFVEI1 (0x00FF0000uL)
+
+#define INTC_ICDIPTR104_TINT0 (0x000000FFuL)
+#define INTC_ICDIPTR104_TINT1 (0x0000FF00uL)
+#define INTC_ICDIPTR104_TINT2 (0x00FF0000uL)
+#define INTC_ICDIPTR104_TINT3 (0xFF000000uL)
+
+#define INTC_ICDIPTR105_TINT4 (0x000000FFuL)
+#define INTC_ICDIPTR105_TINT5 (0x0000FF00uL)
+#define INTC_ICDIPTR105_TINT6 (0x00FF0000uL)
+#define INTC_ICDIPTR105_TINT7 (0xFF000000uL)
+
+#define INTC_ICDIPTR106_TINT8 (0x000000FFuL)
+#define INTC_ICDIPTR106_TINT9 (0x0000FF00uL)
+#define INTC_ICDIPTR106_TINT10 (0x00FF0000uL)
+#define INTC_ICDIPTR106_TINT11 (0xFF000000uL)
+
+#define INTC_ICDIPTR107_TINT12 (0x000000FFuL)
+#define INTC_ICDIPTR107_TINT13 (0x0000FF00uL)
+#define INTC_ICDIPTR107_TINT14 (0x00FF0000uL)
+#define INTC_ICDIPTR107_TINT15 (0xFF000000uL)
+
+#define INTC_ICDIPTR108_TINT16 (0x000000FFuL)
+#define INTC_ICDIPTR108_TINT17 (0x0000FF00uL)
+#define INTC_ICDIPTR108_TINT18 (0x00FF0000uL)
+#define INTC_ICDIPTR108_TINT19 (0xFF000000uL)
+
+#define INTC_ICDIPTR109_TINT20 (0x000000FFuL)
+#define INTC_ICDIPTR109_TINT21 (0x0000FF00uL)
+#define INTC_ICDIPTR109_TINT22 (0x00FF0000uL)
+#define INTC_ICDIPTR109_TINT23 (0xFF000000uL)
+
+#define INTC_ICDIPTR110_TINT24 (0x000000FFuL)
+#define INTC_ICDIPTR110_TINT25 (0x0000FF00uL)
+#define INTC_ICDIPTR110_TINT26 (0x00FF0000uL)
+#define INTC_ICDIPTR110_TINT27 (0xFF000000uL)
+
+#define INTC_ICDIPTR111_TINT28 (0x000000FFuL)
+#define INTC_ICDIPTR111_TINT29 (0x0000FF00uL)
+#define INTC_ICDIPTR111_TINT30 (0x00FF0000uL)
+#define INTC_ICDIPTR111_TINT31 (0xFF000000uL)
+
+#define INTC_ICDIPTR112_TINT32 (0x000000FFuL)
+#define INTC_ICDIPTR112_TINT33 (0x0000FF00uL)
+#define INTC_ICDIPTR112_TINT34 (0x00FF0000uL)
+#define INTC_ICDIPTR112_TINT35 (0xFF000000uL)
+
+#define INTC_ICDIPTR113_TINT36 (0x000000FFuL)
+#define INTC_ICDIPTR113_TINT37 (0x0000FF00uL)
+#define INTC_ICDIPTR113_TINT38 (0x00FF0000uL)
+#define INTC_ICDIPTR113_TINT39 (0xFF000000uL)
+
+#define INTC_ICDIPTR114_TINT40 (0x000000FFuL)
+#define INTC_ICDIPTR114_TINT41 (0x0000FF00uL)
+#define INTC_ICDIPTR114_TINT42 (0x00FF0000uL)
+#define INTC_ICDIPTR114_TINT43 (0xFF000000uL)
+
+#define INTC_ICDIPTR115_TINT44 (0x000000FFuL)
+#define INTC_ICDIPTR115_TINT45 (0x0000FF00uL)
+#define INTC_ICDIPTR115_TINT46 (0x00FF0000uL)
+#define INTC_ICDIPTR115_TINT47 (0xFF000000uL)
+
+#define INTC_ICDIPTR116_TINT48 (0x000000FFuL)
+#define INTC_ICDIPTR116_TINT49 (0x0000FF00uL)
+#define INTC_ICDIPTR116_TINT50 (0x00FF0000uL)
+#define INTC_ICDIPTR116_TINT51 (0xFF000000uL)
+
+#define INTC_ICDIPTR117_TINT52 (0x000000FFuL)
+#define INTC_ICDIPTR117_TINT53 (0x0000FF00uL)
+#define INTC_ICDIPTR117_TINT54 (0x00FF0000uL)
+#define INTC_ICDIPTR117_TINT55 (0xFF000000uL)
+
+#define INTC_ICDIPTR118_TINT56 (0x000000FFuL)
+#define INTC_ICDIPTR118_TINT57 (0x0000FF00uL)
+#define INTC_ICDIPTR118_TINT58 (0x00FF0000uL)
+#define INTC_ICDIPTR118_TINT59 (0xFF000000uL)
+
+#define INTC_ICDIPTR119_TINT60 (0x000000FFuL)
+#define INTC_ICDIPTR119_TINT61 (0x0000FF00uL)
+#define INTC_ICDIPTR119_TINT62 (0x00FF0000uL)
+#define INTC_ICDIPTR119_TINT63 (0xFF000000uL)
+
+#define INTC_ICDIPTR120_TINT64 (0x000000FFuL)
+#define INTC_ICDIPTR120_TINT65 (0x0000FF00uL)
+#define INTC_ICDIPTR120_TINT66 (0x00FF0000uL)
+#define INTC_ICDIPTR120_TINT67 (0xFF000000uL)
+
+#define INTC_ICDIPTR121_TINT68 (0x000000FFuL)
+#define INTC_ICDIPTR121_TINT69 (0x0000FF00uL)
+#define INTC_ICDIPTR121_TINT70 (0x00FF0000uL)
+#define INTC_ICDIPTR121_TINT71 (0xFF000000uL)
+
+#define INTC_ICDIPTR122_TINT72 (0x000000FFuL)
+#define INTC_ICDIPTR122_TINT73 (0x0000FF00uL)
+#define INTC_ICDIPTR122_TINT74 (0x00FF0000uL)
+#define INTC_ICDIPTR122_TINT75 (0xFF000000uL)
+
+#define INTC_ICDIPTR123_TINT76 (0x000000FFuL)
+#define INTC_ICDIPTR123_TINT77 (0x0000FF00uL)
+#define INTC_ICDIPTR123_TINT78 (0x00FF0000uL)
+#define INTC_ICDIPTR123_TINT79 (0xFF000000uL)
+
+#define INTC_ICDIPTR124_TINT80 (0x000000FFuL)
+#define INTC_ICDIPTR124_TINT81 (0x0000FF00uL)
+#define INTC_ICDIPTR124_TINT82 (0x00FF0000uL)
+#define INTC_ICDIPTR124_TINT83 (0xFF000000uL)
+
+#define INTC_ICDIPTR125_TINT84 (0x000000FFuL)
+#define INTC_ICDIPTR125_TINT85 (0x0000FF00uL)
+#define INTC_ICDIPTR125_TINT86 (0x00FF0000uL)
+#define INTC_ICDIPTR125_TINT87 (0xFF000000uL)
+
+#define INTC_ICDIPTR126_TINT88 (0x000000FFuL)
+#define INTC_ICDIPTR126_TINT89 (0x0000FF00uL)
+#define INTC_ICDIPTR126_TINT90 (0x00FF0000uL)
+#define INTC_ICDIPTR126_TINT91 (0xFF000000uL)
+
+#define INTC_ICDIPTR127_TINT92 (0x000000FFuL)
+#define INTC_ICDIPTR127_TINT93 (0x0000FF00uL)
+#define INTC_ICDIPTR127_TINT94 (0x00FF0000uL)
+#define INTC_ICDIPTR127_TINT95 (0xFF000000uL)
+
+#define INTC_ICDIPTR128_TINT96 (0x000000FFuL)
+#define INTC_ICDIPTR128_TINT97 (0x0000FF00uL)
+#define INTC_ICDIPTR128_TINT98 (0x00FF0000uL)
+#define INTC_ICDIPTR128_TINT99 (0xFF000000uL)
+
+#define INTC_ICDIPTR129_TINT100 (0x000000FFuL)
+#define INTC_ICDIPTR129_TINT101 (0x0000FF00uL)
+#define INTC_ICDIPTR129_TINT102 (0x00FF0000uL)
+#define INTC_ICDIPTR129_TINT103 (0xFF000000uL)
+
+#define INTC_ICDIPTR130_TINT104 (0x000000FFuL)
+#define INTC_ICDIPTR130_TINT105 (0x0000FF00uL)
+#define INTC_ICDIPTR130_TINT106 (0x00FF0000uL)
+#define INTC_ICDIPTR130_TINT107 (0xFF000000uL)
+
+#define INTC_ICDIPTR131_TINT108 (0x000000FFuL)
+#define INTC_ICDIPTR131_TINT109 (0x0000FF00uL)
+#define INTC_ICDIPTR131_TINT110 (0x00FF0000uL)
+#define INTC_ICDIPTR131_TINT111 (0xFF000000uL)
+
+#define INTC_ICDIPTR132_TINT112 (0x000000FFuL)
+#define INTC_ICDIPTR132_TINT113 (0x0000FF00uL)
+#define INTC_ICDIPTR132_TINT114 (0x00FF0000uL)
+#define INTC_ICDIPTR132_TINT115 (0xFF000000uL)
+
+#define INTC_ICDIPTR133_TINT116 (0x000000FFuL)
+#define INTC_ICDIPTR133_TINT117 (0x0000FF00uL)
+#define INTC_ICDIPTR133_TINT118 (0x00FF0000uL)
+#define INTC_ICDIPTR133_TINT119 (0xFF000000uL)
+
+#define INTC_ICDIPTR134_TINT120 (0x000000FFuL)
+#define INTC_ICDIPTR134_TINT121 (0x0000FF00uL)
+#define INTC_ICDIPTR134_TINT122 (0x00FF0000uL)
+#define INTC_ICDIPTR134_TINT123 (0xFF000000uL)
+
+#define INTC_ICDIPTR135_TINT124 (0x000000FFuL)
+#define INTC_ICDIPTR135_TINT125 (0x0000FF00uL)
+#define INTC_ICDIPTR135_TINT126 (0x00FF0000uL)
+#define INTC_ICDIPTR135_TINT127 (0xFF000000uL)
+
+#define INTC_ICDIPTR136_TINT128 (0x000000FFuL)
+#define INTC_ICDIPTR136_TINT129 (0x0000FF00uL)
+#define INTC_ICDIPTR136_TINT130 (0x00FF0000uL)
+#define INTC_ICDIPTR136_TINT131 (0xFF000000uL)
+
+#define INTC_ICDIPTR137_TINT132 (0x000000FFuL)
+#define INTC_ICDIPTR137_TINT133 (0x0000FF00uL)
+#define INTC_ICDIPTR137_TINT134 (0x00FF0000uL)
+#define INTC_ICDIPTR137_TINT135 (0xFF000000uL)
+
+#define INTC_ICDIPTR138_TINT136 (0x000000FFuL)
+#define INTC_ICDIPTR138_TINT137 (0x0000FF00uL)
+#define INTC_ICDIPTR138_TINT138 (0x00FF0000uL)
+#define INTC_ICDIPTR138_TINT139 (0xFF000000uL)
+
+#define INTC_ICDIPTR139_TINT140 (0x000000FFuL)
+#define INTC_ICDIPTR139_TINT141 (0x0000FF00uL)
+#define INTC_ICDIPTR139_TINT142 (0x00FF0000uL)
+#define INTC_ICDIPTR139_TINT143 (0xFF000000uL)
+
+#define INTC_ICDIPTR140_TINT144 (0x000000FFuL)
+#define INTC_ICDIPTR140_TINT145 (0x0000FF00uL)
+#define INTC_ICDIPTR140_TINT146 (0x00FF0000uL)
+#define INTC_ICDIPTR140_TINT147 (0xFF000000uL)
+
+#define INTC_ICDIPTR141_TINT148 (0x000000FFuL)
+#define INTC_ICDIPTR141_TINT149 (0x0000FF00uL)
+#define INTC_ICDIPTR141_TINT150 (0x00FF0000uL)
+#define INTC_ICDIPTR141_TINT151 (0xFF000000uL)
+
+#define INTC_ICDIPTR142_TINT152 (0x000000FFuL)
+#define INTC_ICDIPTR142_TINT153 (0x0000FF00uL)
+#define INTC_ICDIPTR142_TINT154 (0x00FF0000uL)
+#define INTC_ICDIPTR142_TINT155 (0xFF000000uL)
+
+#define INTC_ICDIPTR143_TINT156 (0x000000FFuL)
+#define INTC_ICDIPTR143_TINT157 (0x0000FF00uL)
+#define INTC_ICDIPTR143_TINT158 (0x00FF0000uL)
+#define INTC_ICDIPTR143_TINT159 (0xFF000000uL)
+
+#define INTC_ICDIPTR144_TINT160 (0x000000FFuL)
+#define INTC_ICDIPTR144_TINT161 (0x0000FF00uL)
+#define INTC_ICDIPTR144_TINT162 (0x00FF0000uL)
+#define INTC_ICDIPTR144_TINT163 (0xFF000000uL)
+
+#define INTC_ICDIPTR145_TINT164 (0x000000FFuL)
+#define INTC_ICDIPTR145_TINT165 (0x0000FF00uL)
+#define INTC_ICDIPTR145_TINT166 (0x00FF0000uL)
+#define INTC_ICDIPTR145_TINT167 (0xFF000000uL)
+
+#define INTC_ICDIPTR146_TINT168 (0x000000FFuL)
+#define INTC_ICDIPTR146_TINT169 (0x0000FF00uL)
+#define INTC_ICDIPTR146_TINT170 (0x00FF0000uL)
+
+#define INTC_ICDICFR0_SW0_0 (0x00000001uL)
+#define INTC_ICDICFR0_SW0_1 (0x00000002uL)
+#define INTC_ICDICFR0_SW1_0 (0x00000004uL)
+#define INTC_ICDICFR0_SW1_1 (0x00000008uL)
+#define INTC_ICDICFR0_SW2_0 (0x00000010uL)
+#define INTC_ICDICFR0_SW2_1 (0x00000020uL)
+#define INTC_ICDICFR0_SW3_0 (0x00000040uL)
+#define INTC_ICDICFR0_SW3_1 (0x00000080uL)
+#define INTC_ICDICFR0_SW4_0 (0x00000100uL)
+#define INTC_ICDICFR0_SW4_1 (0x00000200uL)
+#define INTC_ICDICFR0_SW5_0 (0x00000400uL)
+#define INTC_ICDICFR0_SW5_1 (0x00000800uL)
+#define INTC_ICDICFR0_SW6_0 (0x00001000uL)
+#define INTC_ICDICFR0_SW6_1 (0x00002000uL)
+#define INTC_ICDICFR0_SW7_0 (0x00004000uL)
+#define INTC_ICDICFR0_SW7_1 (0x00008000uL)
+#define INTC_ICDICFR0_SW8_0 (0x00010000uL)
+#define INTC_ICDICFR0_SW8_1 (0x00020000uL)
+#define INTC_ICDICFR0_SW9_0 (0x00040000uL)
+#define INTC_ICDICFR0_SW9_1 (0x00080000uL)
+#define INTC_ICDICFR0_SW10_0 (0x00100000uL)
+#define INTC_ICDICFR0_SW10_1 (0x00200000uL)
+#define INTC_ICDICFR0_SW11_0 (0x00400000uL)
+#define INTC_ICDICFR0_SW11_1 (0x00800000uL)
+#define INTC_ICDICFR0_SW12_0 (0x01000000uL)
+#define INTC_ICDICFR0_SW12_1 (0x02000000uL)
+#define INTC_ICDICFR0_SW13_0 (0x04000000uL)
+#define INTC_ICDICFR0_SW13_1 (0x08000000uL)
+#define INTC_ICDICFR0_SW14_0 (0x10000000uL)
+#define INTC_ICDICFR0_SW14_1 (0x20000000uL)
+#define INTC_ICDICFR0_SW15_0 (0x40000000uL)
+#define INTC_ICDICFR0_SW15_1 (0x80000000uL)
+
+#define INTC_ICDICFR1_PMUIRQ0_0 (0x00000001uL)
+#define INTC_ICDICFR1_PMUIRQ0_1 (0x00000002uL)
+#define INTC_ICDICFR1_COMMRX0_0 (0x00000004uL)
+#define INTC_ICDICFR1_COMMRX0_1 (0x00000008uL)
+#define INTC_ICDICFR1_COMMTX0_0 (0x00000010uL)
+#define INTC_ICDICFR1_COMMTX0_1 (0x00000020uL)
+#define INTC_ICDICFR1_CTIIRQ0_0 (0x00000040uL)
+#define INTC_ICDICFR1_CTIIRQ0_1 (0x00000080uL)
+
+#define INTC_ICDICFR2_IRQ0_0 (0x00000001uL)
+#define INTC_ICDICFR2_IRQ0_1 (0x00000002uL)
+#define INTC_ICDICFR2_IRQ1_0 (0x00000004uL)
+#define INTC_ICDICFR2_IRQ1_1 (0x00000008uL)
+#define INTC_ICDICFR2_IRQ2_0 (0x00000010uL)
+#define INTC_ICDICFR2_IRQ2_1 (0x00000020uL)
+#define INTC_ICDICFR2_IRQ3_0 (0x00000040uL)
+#define INTC_ICDICFR2_IRQ3_1 (0x00000080uL)
+#define INTC_ICDICFR2_IRQ4_0 (0x00000100uL)
+#define INTC_ICDICFR2_IRQ4_1 (0x00000200uL)
+#define INTC_ICDICFR2_IRQ5_0 (0x00000400uL)
+#define INTC_ICDICFR2_IRQ5_1 (0x00000800uL)
+#define INTC_ICDICFR2_IRQ6_0 (0x00001000uL)
+#define INTC_ICDICFR2_IRQ6_1 (0x00002000uL)
+#define INTC_ICDICFR2_IRQ7_0 (0x00004000uL)
+#define INTC_ICDICFR2_IRQ7_1 (0x00008000uL)
+#define INTC_ICDICFR2_PL310ERR_0 (0x00010000uL)
+#define INTC_ICDICFR2_PL310ERR_1 (0x00020000uL)
+#define INTC_ICDICFR2_DMAINT0_0 (0x00040000uL)
+#define INTC_ICDICFR2_DMAINT0_1 (0x00080000uL)
+#define INTC_ICDICFR2_DMAINT1_0 (0x00100000uL)
+#define INTC_ICDICFR2_DMAINT1_1 (0x00200000uL)
+#define INTC_ICDICFR2_DMAINT2_0 (0x00400000uL)
+#define INTC_ICDICFR2_DMAINT2_1 (0x00800000uL)
+#define INTC_ICDICFR2_DMAINT3_0 (0x01000000uL)
+#define INTC_ICDICFR2_DMAINT3_1 (0x02000000uL)
+#define INTC_ICDICFR2_DMAINT4_0 (0x04000000uL)
+#define INTC_ICDICFR2_DMAINT4_1 (0x08000000uL)
+#define INTC_ICDICFR2_DMAINT5_0 (0x10000000uL)
+#define INTC_ICDICFR2_DMAINT5_1 (0x20000000uL)
+#define INTC_ICDICFR2_DMAINT6_0 (0x40000000uL)
+#define INTC_ICDICFR2_DMAINT6_1 (0x80000000uL)
+
+#define INTC_ICDICFR3_DMAINT7_0 (0x00000001uL)
+#define INTC_ICDICFR3_DMAINT7_1 (0x00000002uL)
+#define INTC_ICDICFR3_DMAINT8_0 (0x00000004uL)
+#define INTC_ICDICFR3_DMAINT8_1 (0x00000008uL)
+#define INTC_ICDICFR3_DMAINT9_0 (0x00000010uL)
+#define INTC_ICDICFR3_DMAINT9_1 (0x00000020uL)
+#define INTC_ICDICFR3_DMAINT10_0 (0x00000040uL)
+#define INTC_ICDICFR3_DMAINT10_1 (0x00000080uL)
+#define INTC_ICDICFR3_DMAINT11_0 (0x00000100uL)
+#define INTC_ICDICFR3_DMAINT11_1 (0x00000200uL)
+#define INTC_ICDICFR3_DMAINT12_0 (0x00000400uL)
+#define INTC_ICDICFR3_DMAINT12_1 (0x00000800uL)
+#define INTC_ICDICFR3_DMAINT13_0 (0x00001000uL)
+#define INTC_ICDICFR3_DMAINT13_1 (0x00002000uL)
+#define INTC_ICDICFR3_DMAINT14_0 (0x00004000uL)
+#define INTC_ICDICFR3_DMAINT14_1 (0x00008000uL)
+#define INTC_ICDICFR3_DMAINT15_0 (0x00010000uL)
+#define INTC_ICDICFR3_DMAINT15_1 (0x00020000uL)
+#define INTC_ICDICFR3_DMAERR_0 (0x00040000uL)
+#define INTC_ICDICFR3_DMAERR_1 (0x00080000uL)
+
+#define INTC_ICDICFR4_USBI0_0 (0x00040000uL)
+#define INTC_ICDICFR4_USBI0_1 (0x00080000uL)
+#define INTC_ICDICFR4_USBI1_0 (0x00100000uL)
+#define INTC_ICDICFR4_USBI1_1 (0x00200000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0 (0x00400000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1 (0x00800000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0 (0x01000000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1 (0x02000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0 (0x04000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1 (0x08000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_0 (0x10000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_1 (0x20000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_0 (0x40000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_1 (0x80000000uL)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0 (0x00000001uL)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1 (0x00000002uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0 (0x00000004uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1 (0x00000008uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0 (0x00000010uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1 (0x00000020uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0 (0x00000040uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1 (0x00000080uL)
+#define INTC_ICDICFR5_S0_WLINE0_0 (0x00000100uL)
+#define INTC_ICDICFR5_S0_WLINE0_1 (0x00000200uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0 (0x00000400uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1 (0x00000800uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0 (0x00001000uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1 (0x00002000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0 (0x00004000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1 (0x00008000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_0 (0x00010000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_1 (0x00020000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0 (0x00040000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1 (0x00080000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0 (0x00100000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1 (0x00200000uL)
+#define INTC_ICDICFR5_S1_WLINE0_0 (0x00400000uL)
+#define INTC_ICDICFR5_S1_WLINE0_1 (0x00800000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0 (0x01000000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1 (0x02000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0 (0x04000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1 (0x08000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0 (0x10000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1 (0x20000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_0 (0x40000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_1 (0x80000000uL)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0 (0x00000001uL)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1 (0x00000002uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0 (0x00000004uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1 (0x00000008uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0 (0x00000040uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1 (0x00000080uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0 (0x00000100uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1 (0x00000200uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0 (0x00000400uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1 (0x00000800uL)
+#define INTC_ICDICFR6_GR3_VLINE1_0 (0x00001000uL)
+#define INTC_ICDICFR6_GR3_VLINE1_1 (0x00002000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_0 (0x00004000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_1 (0x00008000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0 (0x00010000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1 (0x00020000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0 (0x00040000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1 (0x00080000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0 (0x00100000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1 (0x00200000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0 (0x00400000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1 (0x00800000uL)
+#define INTC_ICDICFR6_S0_WLINE1_0 (0x01000000uL)
+#define INTC_ICDICFR6_S0_WLINE1_1 (0x02000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0 (0x04000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1 (0x08000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0 (0x10000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1 (0x20000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0 (0x40000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1 (0x80000000uL)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0 (0x00000001uL)
+#define INTC_ICDICFR7_S1_VFIELD1_1 (0x00000002uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0 (0x00000004uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1 (0x00000008uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0 (0x00000010uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1 (0x00000020uL)
+#define INTC_ICDICFR7_S1_WLINE1_0 (0x00000040uL)
+#define INTC_ICDICFR7_S1_WLINE1_1 (0x00000080uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0 (0x00000100uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1 (0x00000200uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0 (0x00000400uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1 (0x00000800uL)
+#define INTC_ICDICFR7_OIR_VLINE1_0 (0x00001000uL)
+#define INTC_ICDICFR7_OIR_VLINE1_1 (0x00002000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_0 (0x00004000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_1 (0x00008000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0 (0x00010000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1 (0x00020000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0 (0x00040000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1 (0x00080000uL)
+#define INTC_ICDICFR7_IMRDI_0 (0x00400000uL)
+#define INTC_ICDICFR7_IMRDI_1 (0x00800000uL)
+#define INTC_ICDICFR7_IMR2I0_0 (0x01000000uL)
+#define INTC_ICDICFR7_IMR2I0_1 (0x02000000uL)
+#define INTC_ICDICFR7_IMR2I1_0 (0x04000000uL)
+#define INTC_ICDICFR7_IMR2I1_1 (0x08000000uL)
+#define INTC_ICDICFR7_JEDI_0 (0x10000000uL)
+#define INTC_ICDICFR7_JEDI_1 (0x20000000uL)
+#define INTC_ICDICFR7_JDTI_0 (0x40000000uL)
+#define INTC_ICDICFR7_JDTI_1 (0x80000000uL)
+
+#define INTC_ICDICFR8_CMP0_0 (0x00000001uL)
+#define INTC_ICDICFR8_CMP0_1 (0x00000002uL)
+#define INTC_ICDICFR8_CMP1_0 (0x00000004uL)
+#define INTC_ICDICFR8_CMP1_1 (0x00000008uL)
+#define INTC_ICDICFR8_INT0_0 (0x00000010uL)
+#define INTC_ICDICFR8_INT0_1 (0x00000020uL)
+#define INTC_ICDICFR8_INT1_0 (0x00000040uL)
+#define INTC_ICDICFR8_INT1_1 (0x00000080uL)
+#define INTC_ICDICFR8_INT2_0 (0x00000100uL)
+#define INTC_ICDICFR8_INT2_1 (0x00000200uL)
+#define INTC_ICDICFR8_INT3_0 (0x00000400uL)
+#define INTC_ICDICFR8_INT3_1 (0x00000800uL)
+#define INTC_ICDICFR8_OSTM0TINT_0 (0x00001000uL)
+#define INTC_ICDICFR8_OSTM0TINT_1 (0x00002000uL)
+#define INTC_ICDICFR8_OSTM1TINT_0 (0x00004000uL)
+#define INTC_ICDICFR8_OSTM1TINT_1 (0x00008000uL)
+#define INTC_ICDICFR8_CMI_0 (0x00010000uL)
+#define INTC_ICDICFR8_CMI_1 (0x00020000uL)
+#define INTC_ICDICFR8_WTOUT_0 (0x00040000uL)
+#define INTC_ICDICFR8_WTOUT_1 (0x00080000uL)
+#define INTC_ICDICFR8_ITI_0 (0x00100000uL)
+#define INTC_ICDICFR8_ITI_1 (0x00200000uL)
+#define INTC_ICDICFR8_TGI0A_0 (0x00400000uL)
+#define INTC_ICDICFR8_TGI0A_1 (0x00800000uL)
+#define INTC_ICDICFR8_TGI0B_0 (0x01000000uL)
+#define INTC_ICDICFR8_TGI0B_1 (0x02000000uL)
+#define INTC_ICDICFR8_TGI0C_0 (0x04000000uL)
+#define INTC_ICDICFR8_TGI0C_1 (0x08000000uL)
+#define INTC_ICDICFR8_TGI0D_0 (0x10000000uL)
+#define INTC_ICDICFR8_TGI0D_1 (0x20000000uL)
+#define INTC_ICDICFR8_TGI0V_0 (0x40000000uL)
+#define INTC_ICDICFR8_TGI0V_1 (0x80000000uL)
+
+#define INTC_ICDICFR9_TGI0E_0 (0x00000001uL)
+#define INTC_ICDICFR9_TGI0E_1 (0x00000002uL)
+#define INTC_ICDICFR9_TGI0F_0 (0x00000004uL)
+#define INTC_ICDICFR9_TGI0F_1 (0x00000008uL)
+#define INTC_ICDICFR9_TGI1A_0 (0x00000010uL)
+#define INTC_ICDICFR9_TGI1A_1 (0x00000020uL)
+#define INTC_ICDICFR9_TGI1B_0 (0x00000040uL)
+#define INTC_ICDICFR9_TGI1B_1 (0x00000080uL)
+#define INTC_ICDICFR9_TGI1V_0 (0x00000100uL)
+#define INTC_ICDICFR9_TGI1V_1 (0x00000200uL)
+#define INTC_ICDICFR9_TGI1U_0 (0x00000400uL)
+#define INTC_ICDICFR9_TGI1U_1 (0x00000800uL)
+#define INTC_ICDICFR9_TGI2A_0 (0x00001000uL)
+#define INTC_ICDICFR9_TGI2A_1 (0x00002000uL)
+#define INTC_ICDICFR9_TGI2B_0 (0x00004000uL)
+#define INTC_ICDICFR9_TGI2B_1 (0x00008000uL)
+#define INTC_ICDICFR9_TGI2V_0 (0x00010000uL)
+#define INTC_ICDICFR9_TGI2V_1 (0x00020000uL)
+#define INTC_ICDICFR9_TGI2U_0 (0x00040000uL)
+#define INTC_ICDICFR9_TGI2U_1 (0x00080000uL)
+#define INTC_ICDICFR9_TGI3A_0 (0x00100000uL)
+#define INTC_ICDICFR9_TGI3A_1 (0x00200000uL)
+#define INTC_ICDICFR9_TGI3B_0 (0x00400000uL)
+#define INTC_ICDICFR9_TGI3B_1 (0x00800000uL)
+#define INTC_ICDICFR9_TGI3C_0 (0x01000000uL)
+#define INTC_ICDICFR9_TGI3C_1 (0x02000000uL)
+#define INTC_ICDICFR9_TGI3D_0 (0x04000000uL)
+#define INTC_ICDICFR9_TGI3D_1 (0x08000000uL)
+#define INTC_ICDICFR9_TGI3V_0 (0x10000000uL)
+#define INTC_ICDICFR9_TGI3V_1 (0x20000000uL)
+#define INTC_ICDICFR9_TGI4A_0 (0x40000000uL)
+#define INTC_ICDICFR9_TGI4A_1 (0x80000000uL)
+
+#define INTC_ICDICFR10_TGI4B_0 (0x00000001uL)
+#define INTC_ICDICFR10_TGI4B_1 (0x00000002uL)
+#define INTC_ICDICFR10_TGI4C_0 (0x00000004uL)
+#define INTC_ICDICFR10_TGI4C_1 (0x00000008uL)
+#define INTC_ICDICFR10_TGI4D_0 (0x00000010uL)
+#define INTC_ICDICFR10_TGI4D_1 (0x00000020uL)
+#define INTC_ICDICFR10_TGI4V_0 (0x00000040uL)
+#define INTC_ICDICFR10_TGI4V_1 (0x00000080uL)
+#define INTC_ICDICFR10_CMI1_0 (0x00000100uL)
+#define INTC_ICDICFR10_CMI1_1 (0x00000200uL)
+#define INTC_ICDICFR10_CMI2_0 (0x00000400uL)
+#define INTC_ICDICFR10_CMI2_1 (0x00000800uL)
+#define INTC_ICDICFR10_SGDEI0_0 (0x00001000uL)
+#define INTC_ICDICFR10_SGDEI0_1 (0x00002000uL)
+#define INTC_ICDICFR10_SGDEI1_0 (0x00004000uL)
+#define INTC_ICDICFR10_SGDEI1_1 (0x00008000uL)
+#define INTC_ICDICFR10_SGDEI2_0 (0x00010000uL)
+#define INTC_ICDICFR10_SGDEI2_1 (0x00020000uL)
+#define INTC_ICDICFR10_SGDEI3_0 (0x00040000uL)
+#define INTC_ICDICFR10_SGDEI3_1 (0x00080000uL)
+#define INTC_ICDICFR10_ADI_0 (0x00100000uL)
+#define INTC_ICDICFR10_ADI_1 (0x00200000uL)
+#define INTC_ICDICFR10_LMTI_0 (0x00400000uL)
+#define INTC_ICDICFR10_LMTI_1 (0x00800000uL)
+#define INTC_ICDICFR10_SSII0_0 (0x01000000uL)
+#define INTC_ICDICFR10_SSII0_1 (0x02000000uL)
+#define INTC_ICDICFR10_SSIRXI0_0 (0x04000000uL)
+#define INTC_ICDICFR10_SSIRXI0_1 (0x08000000uL)
+#define INTC_ICDICFR10_SSITXI0_0 (0x10000000uL)
+#define INTC_ICDICFR10_SSITXI0_1 (0x20000000uL)
+#define INTC_ICDICFR10_SSII1_0 (0x40000000uL)
+#define INTC_ICDICFR10_SSII1_1 (0x80000000uL)
+
+#define INTC_ICDICFR11_SSIRXI1_0 (0x00000001uL)
+#define INTC_ICDICFR11_SSIRXI1_1 (0x00000002uL)
+#define INTC_ICDICFR11_SSITXI1_0 (0x00000004uL)
+#define INTC_ICDICFR11_SSITXI1_1 (0x00000008uL)
+#define INTC_ICDICFR11_SSII2_0 (0x00000010uL)
+#define INTC_ICDICFR11_SSII2_1 (0x00000020uL)
+#define INTC_ICDICFR11_SSIRTI2_0 (0x00000040uL)
+#define INTC_ICDICFR11_SSIRTI2_1 (0x00000080uL)
+#define INTC_ICDICFR11_SSII3_0 (0x00000100uL)
+#define INTC_ICDICFR11_SSII3_1 (0x00000200uL)
+#define INTC_ICDICFR11_SSIRXI3_0 (0x00000400uL)
+#define INTC_ICDICFR11_SSIRXI3_1 (0x00000800uL)
+#define INTC_ICDICFR11_SSITXI3_0 (0x00001000uL)
+#define INTC_ICDICFR11_SSITXI3_1 (0x00002000uL)
+#define INTC_ICDICFR11_SSII4_0 (0x00004000uL)
+#define INTC_ICDICFR11_SSII4_1 (0x00008000uL)
+#define INTC_ICDICFR11_SSIRTI4_0 (0x00010000uL)
+#define INTC_ICDICFR11_SSIRTI4_1 (0x00020000uL)
+#define INTC_ICDICFR11_SSII5_0 (0x00040000uL)
+#define INTC_ICDICFR11_SSII5_1 (0x00080000uL)
+#define INTC_ICDICFR11_SSIRXI5_0 (0x00100000uL)
+#define INTC_ICDICFR11_SSIRXI5_1 (0x00200000uL)
+#define INTC_ICDICFR11_SSITXI5_0 (0x00400000uL)
+#define INTC_ICDICFR11_SSITXI5_1 (0x00800000uL)
+#define INTC_ICDICFR11_SPDIFI_0 (0x01000000uL)
+#define INTC_ICDICFR11_SPDIFI_1 (0x02000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_0 (0x04000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_1 (0x08000000uL)
+#define INTC_ICDICFR11_INTIICRI0_0 (0x10000000uL)
+#define INTC_ICDICFR11_INTIICRI0_1 (0x20000000uL)
+#define INTC_ICDICFR11_INTIICTI0_0 (0x40000000uL)
+#define INTC_ICDICFR11_INTIICTI0_1 (0x80000000uL)
+
+#define INTC_ICDICFR12_INTIICSPI0_0 (0x00000001uL)
+#define INTC_ICDICFR12_INTIICSPI0_1 (0x00000002uL)
+#define INTC_ICDICFR12_INTIICSTI0_0 (0x00000004uL)
+#define INTC_ICDICFR12_INTIICSTI0_1 (0x00000008uL)
+#define INTC_ICDICFR12_INTIICNAKI0_0 (0x00000010uL)
+#define INTC_ICDICFR12_INTIICNAKI0_1 (0x00000020uL)
+#define INTC_ICDICFR12_INTIICALI0_0 (0x00000040uL)
+#define INTC_ICDICFR12_INTIICALI0_1 (0x00000080uL)
+#define INTC_ICDICFR12_INTIICTMOI0_0 (0x00000100uL)
+#define INTC_ICDICFR12_INTIICTMOI0_1 (0x00000200uL)
+#define INTC_ICDICFR12_INTIICTEI1_0 (0x00000400uL)
+#define INTC_ICDICFR12_INTIICTEI1_1 (0x00000800uL)
+#define INTC_ICDICFR12_INTIICRI1_0 (0x00001000uL)
+#define INTC_ICDICFR12_INTIICRI1_1 (0x00002000uL)
+#define INTC_ICDICFR12_INTIICTI1_0 (0x00004000uL)
+#define INTC_ICDICFR12_INTIICTI1_1 (0x00008000uL)
+#define INTC_ICDICFR12_INTIICSPI1_0 (0x00010000uL)
+#define INTC_ICDICFR12_INTIICSPI1_1 (0x00020000uL)
+#define INTC_ICDICFR12_INTIICSTI1_0 (0x00040000uL)
+#define INTC_ICDICFR12_INTIICSTI1_1 (0x00080000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_0 (0x00100000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_1 (0x00200000uL)
+#define INTC_ICDICFR12_INTIICALI1_0 (0x00400000uL)
+#define INTC_ICDICFR12_INTIICALI1_1 (0x00800000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_0 (0x01000000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_1 (0x02000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_0 (0x04000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_1 (0x08000000uL)
+#define INTC_ICDICFR12_INTIICRI2_0 (0x10000000uL)
+#define INTC_ICDICFR12_INTIICRI2_1 (0x20000000uL)
+#define INTC_ICDICFR12_INTIICTI2_0 (0x40000000uL)
+#define INTC_ICDICFR12_INTIICTI2_1 (0x80000000uL)
+
+#define INTC_ICDICFR13_INTIICSPI2_0 (0x00000001uL)
+#define INTC_ICDICFR13_INTIICSPI2_1 (0x00000002uL)
+#define INTC_ICDICFR13_INTIICSTI2_0 (0x00000004uL)
+#define INTC_ICDICFR13_INTIICSTI2_1 (0x00000008uL)
+#define INTC_ICDICFR13_INTIICNAKI2_0 (0x00000010uL)
+#define INTC_ICDICFR13_INTIICNAKI2_1 (0x00000020uL)
+#define INTC_ICDICFR13_INTIICALI2_0 (0x00000040uL)
+#define INTC_ICDICFR13_INTIICALI2_1 (0x00000080uL)
+#define INTC_ICDICFR13_INTIICTMOI2_0 (0x00000100uL)
+#define INTC_ICDICFR13_INTIICTMOI2_1 (0x00000200uL)
+#define INTC_ICDICFR13_INTIICTEI3_0 (0x00000400uL)
+#define INTC_ICDICFR13_INTIICTEI3_1 (0x00000800uL)
+#define INTC_ICDICFR13_INTIICRI3_0 (0x00001000uL)
+#define INTC_ICDICFR13_INTIICRI3_1 (0x00002000uL)
+#define INTC_ICDICFR13_INTIICTI3_0 (0x00004000uL)
+#define INTC_ICDICFR13_INTIICTI3_1 (0x00008000uL)
+#define INTC_ICDICFR13_INTIICSPI3_0 (0x00010000uL)
+#define INTC_ICDICFR13_INTIICSPI3_1 (0x00020000uL)
+#define INTC_ICDICFR13_INTIICSTI3_0 (0x00040000uL)
+#define INTC_ICDICFR13_INTIICSTI3_1 (0x00080000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_0 (0x00100000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_1 (0x00200000uL)
+#define INTC_ICDICFR13_INTIICALI3_0 (0x00400000uL)
+#define INTC_ICDICFR13_INTIICALI3_1 (0x00800000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_0 (0x01000000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_1 (0x02000000uL)
+#define INTC_ICDICFR13_BRI0_0 (0x04000000uL)
+#define INTC_ICDICFR13_BRI0_1 (0x08000000uL)
+#define INTC_ICDICFR13_ERI0_0 (0x10000000uL)
+#define INTC_ICDICFR13_ERI0_1 (0x20000000uL)
+#define INTC_ICDICFR13_RXI0_0 (0x40000000uL)
+#define INTC_ICDICFR13_RXI0_1 (0x80000000uL)
+
+#define INTC_ICDICFR14_TXI0_0 (0x00000001uL)
+#define INTC_ICDICFR14_TXI0_1 (0x00000002uL)
+#define INTC_ICDICFR14_BRI1_0 (0x00000004uL)
+#define INTC_ICDICFR14_BRI1_1 (0x00000008uL)
+#define INTC_ICDICFR14_ERI1_0 (0x00000010uL)
+#define INTC_ICDICFR14_ERI1_1 (0x00000020uL)
+#define INTC_ICDICFR14_RXI1_0 (0x00000040uL)
+#define INTC_ICDICFR14_RXI1_1 (0x00000080uL)
+#define INTC_ICDICFR14_TXI1_0 (0x00000100uL)
+#define INTC_ICDICFR14_TXI1_1 (0x00000200uL)
+#define INTC_ICDICFR14_BRI2_0 (0x00000400uL)
+#define INTC_ICDICFR14_BRI2_1 (0x00000800uL)
+#define INTC_ICDICFR14_ERI2_0 (0x00001000uL)
+#define INTC_ICDICFR14_ERI2_1 (0x00002000uL)
+#define INTC_ICDICFR14_RXI2_0 (0x00004000uL)
+#define INTC_ICDICFR14_RXI2_1 (0x00008000uL)
+#define INTC_ICDICFR14_TXI2_0 (0x00010000uL)
+#define INTC_ICDICFR14_TXI2_1 (0x00020000uL)
+#define INTC_ICDICFR14_BRI3_0 (0x00040000uL)
+#define INTC_ICDICFR14_BRI3_1 (0x00080000uL)
+#define INTC_ICDICFR14_ERI3_0 (0x00100000uL)
+#define INTC_ICDICFR14_ERI3_1 (0x00200000uL)
+#define INTC_ICDICFR14_RXI3_0 (0x00400000uL)
+#define INTC_ICDICFR14_RXI3_1 (0x00800000uL)
+#define INTC_ICDICFR14_TXI3_0 (0x01000000uL)
+#define INTC_ICDICFR14_TXI3_1 (0x02000000uL)
+#define INTC_ICDICFR14_BRI4_0 (0x04000000uL)
+#define INTC_ICDICFR14_BRI4_1 (0x08000000uL)
+#define INTC_ICDICFR14_ERI4_0 (0x10000000uL)
+#define INTC_ICDICFR14_ERI4_1 (0x20000000uL)
+#define INTC_ICDICFR14_RXI4_0 (0x40000000uL)
+#define INTC_ICDICFR14_RXI4_1 (0x80000000uL)
+
+#define INTC_ICDICFR15_TXI4_0 (0x00000001uL)
+#define INTC_ICDICFR15_TXI4_1 (0x00000002uL)
+#define INTC_ICDICFR15_BRI5_0 (0x00000004uL)
+#define INTC_ICDICFR15_BRI5_1 (0x00000008uL)
+#define INTC_ICDICFR15_ERI5_0 (0x00000010uL)
+#define INTC_ICDICFR15_ERI5_1 (0x00000020uL)
+#define INTC_ICDICFR15_RXI5_0 (0x00000040uL)
+#define INTC_ICDICFR15_RXI5_1 (0x00000080uL)
+#define INTC_ICDICFR15_TXI5_0 (0x00000100uL)
+#define INTC_ICDICFR15_TXI5_1 (0x00000200uL)
+#define INTC_ICDICFR15_BRI6_0 (0x00000400uL)
+#define INTC_ICDICFR15_BRI6_1 (0x00000800uL)
+#define INTC_ICDICFR15_ERI6_0 (0x00001000uL)
+#define INTC_ICDICFR15_ERI6_1 (0x00002000uL)
+#define INTC_ICDICFR15_RXI6_0 (0x00004000uL)
+#define INTC_ICDICFR15_RXI6_1 (0x00008000uL)
+#define INTC_ICDICFR15_TXI6_0 (0x00010000uL)
+#define INTC_ICDICFR15_TXI6_1 (0x00020000uL)
+#define INTC_ICDICFR15_BRI7_0 (0x00040000uL)
+#define INTC_ICDICFR15_BRI7_1 (0x00080000uL)
+#define INTC_ICDICFR15_ERI7_0 (0x00100000uL)
+#define INTC_ICDICFR15_ERI7_1 (0x00200000uL)
+#define INTC_ICDICFR15_RXI7_0 (0x00400000uL)
+#define INTC_ICDICFR15_RXI7_1 (0x00800000uL)
+#define INTC_ICDICFR15_TXI7_0 (0x01000000uL)
+#define INTC_ICDICFR15_TXI7_1 (0x02000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_0 (0x04000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_1 (0x08000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_0 (0x10000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_1 (0x20000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_0 (0x40000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_1 (0x80000000uL)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0 (0x00000001uL)
+#define INTC_ICDICFR16_INTRCAN0ERR_1 (0x00000002uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_0 (0x00000004uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_1 (0x00000008uL)
+#define INTC_ICDICFR16_INTRCAN1REC_0 (0x00000010uL)
+#define INTC_ICDICFR16_INTRCAN1REC_1 (0x00000020uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_0 (0x00000040uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_1 (0x00000080uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_0 (0x00000100uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_1 (0x00000200uL)
+#define INTC_ICDICFR16_INTRCAN2REC_0 (0x00000400uL)
+#define INTC_ICDICFR16_INTRCAN2REC_1 (0x00000800uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_0 (0x00001000uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_1 (0x00002000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_0 (0x00004000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_1 (0x00008000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_0 (0x00010000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_1 (0x00020000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_0 (0x00040000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_1 (0x00080000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_0 (0x00100000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_1 (0x00200000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_0 (0x00400000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_1 (0x00800000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_0 (0x01000000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_1 (0x02000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_0 (0x04000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_1 (0x08000000uL)
+#define INTC_ICDICFR16_SPEI0_0 (0x10000000uL)
+#define INTC_ICDICFR16_SPEI0_1 (0x20000000uL)
+#define INTC_ICDICFR16_SPRI0_0 (0x40000000uL)
+#define INTC_ICDICFR16_SPRI0_1 (0x80000000uL)
+
+#define INTC_ICDICFR17_SPTI0_0 (0x00000001uL)
+#define INTC_ICDICFR17_SPTI0_1 (0x00000002uL)
+#define INTC_ICDICFR17_SPEI1_0 (0x00000004uL)
+#define INTC_ICDICFR17_SPEI1_1 (0x00000008uL)
+#define INTC_ICDICFR17_SPRI1_0 (0x00000010uL)
+#define INTC_ICDICFR17_SPRI1_1 (0x00000020uL)
+#define INTC_ICDICFR17_SPTI1_0 (0x00000040uL)
+#define INTC_ICDICFR17_SPTI1_1 (0x00000080uL)
+#define INTC_ICDICFR17_SPEI2_0 (0x00000100uL)
+#define INTC_ICDICFR17_SPEI2_1 (0x00000200uL)
+#define INTC_ICDICFR17_SPRI2_0 (0x00000400uL)
+#define INTC_ICDICFR17_SPRI2_1 (0x00000800uL)
+#define INTC_ICDICFR17_SPTI2_0 (0x00001000uL)
+#define INTC_ICDICFR17_SPTI2_1 (0x00002000uL)
+#define INTC_ICDICFR17_SPEI3_0 (0x00004000uL)
+#define INTC_ICDICFR17_SPEI3_1 (0x00008000uL)
+#define INTC_ICDICFR17_SPRI3_0 (0x00010000uL)
+#define INTC_ICDICFR17_SPRI3_1 (0x00020000uL)
+#define INTC_ICDICFR17_SPTI3_0 (0x00040000uL)
+#define INTC_ICDICFR17_SPTI3_1 (0x00080000uL)
+#define INTC_ICDICFR17_SPEI4_0 (0x00100000uL)
+#define INTC_ICDICFR17_SPEI4_1 (0x00200000uL)
+#define INTC_ICDICFR17_SPRI4_0 (0x00400000uL)
+#define INTC_ICDICFR17_SPRI4_1 (0x00800000uL)
+#define INTC_ICDICFR17_SPTI4_0 (0x01000000uL)
+#define INTC_ICDICFR17_SPTI4_1 (0x02000000uL)
+#define INTC_ICDICFR17_IEBBTD_0 (0x04000000uL)
+#define INTC_ICDICFR17_IEBBTD_1 (0x08000000uL)
+#define INTC_ICDICFR17_IEBBTERR_0 (0x10000000uL)
+#define INTC_ICDICFR17_IEBBTERR_1 (0x20000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_0 (0x40000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_1 (0x80000000uL)
+
+#define INTC_ICDICFR18_IEBBTV_0 (0x00000001uL)
+#define INTC_ICDICFR18_IEBBTV_1 (0x00000002uL)
+#define INTC_ICDICFR18_ISY_0 (0x00000004uL)
+#define INTC_ICDICFR18_ISY_1 (0x00000008uL)
+#define INTC_ICDICFR18_IERR_0 (0x00000010uL)
+#define INTC_ICDICFR18_IERR_1 (0x00000020uL)
+#define INTC_ICDICFR18_ITARG_0 (0x00000040uL)
+#define INTC_ICDICFR18_ITARG_1 (0x00000080uL)
+#define INTC_ICDICFR18_ISEC_0 (0x00000100uL)
+#define INTC_ICDICFR18_ISEC_1 (0x00000200uL)
+#define INTC_ICDICFR18_IBUF_0 (0x00000400uL)
+#define INTC_ICDICFR18_IBUF_1 (0x00000800uL)
+#define INTC_ICDICFR18_IREADY_0 (0x00001000uL)
+#define INTC_ICDICFR18_IREADY_1 (0x00002000uL)
+#define INTC_ICDICFR18_FLSTE_0 (0x00004000uL)
+#define INTC_ICDICFR18_FLSTE_1 (0x00008000uL)
+#define INTC_ICDICFR18_FLTENDI_0 (0x00010000uL)
+#define INTC_ICDICFR18_FLTENDI_1 (0x00020000uL)
+#define INTC_ICDICFR18_FLTREQ0I_0 (0x00040000uL)
+#define INTC_ICDICFR18_FLTREQ0I_1 (0x00080000uL)
+#define INTC_ICDICFR18_FLTREQ1I_0 (0x00100000uL)
+#define INTC_ICDICFR18_FLTREQ1I_1 (0x00200000uL)
+#define INTC_ICDICFR18_MMC0_0 (0x00400000uL)
+#define INTC_ICDICFR18_MMC0_1 (0x00800000uL)
+#define INTC_ICDICFR18_MMC1_0 (0x01000000uL)
+#define INTC_ICDICFR18_MMC1_1 (0x02000000uL)
+#define INTC_ICDICFR18_MMC2_0 (0x04000000uL)
+#define INTC_ICDICFR18_MMC2_1 (0x08000000uL)
+#define INTC_ICDICFR18_SDHI0_3_0 (0x10000000uL)
+#define INTC_ICDICFR18_SDHI0_3_1 (0x20000000uL)
+#define INTC_ICDICFR18_SDHI0_0_0 (0x40000000uL)
+#define INTC_ICDICFR18_SDHI0_0_1 (0x80000000uL)
+
+#define INTC_ICDICFR19_SDHI0_1_0 (0x00000001uL)
+#define INTC_ICDICFR19_SDHI0_1_1 (0x00000002uL)
+#define INTC_ICDICFR19_SDHI1_3_0 (0x00000004uL)
+#define INTC_ICDICFR19_SDHI1_3_1 (0x00000008uL)
+#define INTC_ICDICFR19_SDHI1_0_0 (0x00000010uL)
+#define INTC_ICDICFR19_SDHI1_0_1 (0x00000020uL)
+#define INTC_ICDICFR19_SDHI1_1_0 (0x00000040uL)
+#define INTC_ICDICFR19_SDHI1_1_1 (0x00000080uL)
+#define INTC_ICDICFR19_ARM_0 (0x00000100uL)
+#define INTC_ICDICFR19_ARM_1 (0x00000200uL)
+#define INTC_ICDICFR19_PRD_0 (0x00000400uL)
+#define INTC_ICDICFR19_PRD_1 (0x00000800uL)
+#define INTC_ICDICFR19_CUP_0 (0x00001000uL)
+#define INTC_ICDICFR19_CUP_1 (0x00002000uL)
+#define INTC_ICDICFR19_SCUAI0_0 (0x00004000uL)
+#define INTC_ICDICFR19_SCUAI0_1 (0x00008000uL)
+#define INTC_ICDICFR19_SCUAI1_0 (0x00010000uL)
+#define INTC_ICDICFR19_SCUAI1_1 (0x00020000uL)
+#define INTC_ICDICFR19_SCUFDI0_0 (0x00040000uL)
+#define INTC_ICDICFR19_SCUFDI0_1 (0x00080000uL)
+#define INTC_ICDICFR19_SCUFDI1_0 (0x00100000uL)
+#define INTC_ICDICFR19_SCUFDI1_1 (0x00200000uL)
+#define INTC_ICDICFR19_SCUFDI2_0 (0x00400000uL)
+#define INTC_ICDICFR19_SCUFDI2_1 (0x00800000uL)
+#define INTC_ICDICFR19_SCUFDI3_0 (0x01000000uL)
+#define INTC_ICDICFR19_SCUFDI3_1 (0x02000000uL)
+#define INTC_ICDICFR19_SCUFUI0_0 (0x04000000uL)
+#define INTC_ICDICFR19_SCUFUI0_1 (0x08000000uL)
+#define INTC_ICDICFR19_SCUFUI1_0 (0x10000000uL)
+#define INTC_ICDICFR19_SCUFUI1_1 (0x20000000uL)
+#define INTC_ICDICFR19_SCUFUI2_0 (0x40000000uL)
+#define INTC_ICDICFR19_SCUFUI2_1 (0x80000000uL)
+
+#define INTC_ICDICFR20_SCUFUI3_0 (0x00000001uL)
+#define INTC_ICDICFR20_SCUFUI3_1 (0x00000002uL)
+#define INTC_ICDICFR20_SCUDVI0_0 (0x00000004uL)
+#define INTC_ICDICFR20_SCUDVI0_1 (0x00000008uL)
+#define INTC_ICDICFR20_SCUDVI1_0 (0x00000010uL)
+#define INTC_ICDICFR20_SCUDVI1_1 (0x00000020uL)
+#define INTC_ICDICFR20_SCUDVI2_0 (0x00000040uL)
+#define INTC_ICDICFR20_SCUDVI2_1 (0x00000080uL)
+#define INTC_ICDICFR20_SCUDVI3_0 (0x00000100uL)
+#define INTC_ICDICFR20_SCUDVI3_1 (0x00000200uL)
+#define INTC_ICDICFR20_MLB_CINT_0 (0x00000400uL)
+#define INTC_ICDICFR20_MLB_CINT_1 (0x00000800uL)
+#define INTC_ICDICFR20_MLB_SINT_0 (0x00001000uL)
+#define INTC_ICDICFR20_MLB_SINT_1 (0x00002000uL)
+#define INTC_ICDICFR20_DRC0_0 (0x00004000uL)
+#define INTC_ICDICFR20_DRC0_1 (0x00008000uL)
+#define INTC_ICDICFR20_DRC1_0 (0x00010000uL)
+#define INTC_ICDICFR20_DRC1_1 (0x00020000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_0 (0x00400000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_1 (0x00800000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_0 (0x01000000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_1 (0x02000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_0 (0x04000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_1 (0x08000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_0 (0x10000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_1 (0x20000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_0 (0x40000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_1 (0x80000000uL)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0 (0x00000001uL)
+#define INTC_ICDICFR21_LINI1_INT_R_1 (0x00000002uL)
+#define INTC_ICDICFR21_LINI1_INT_S_0 (0x00000004uL)
+#define INTC_ICDICFR21_LINI1_INT_S_1 (0x00000008uL)
+#define INTC_ICDICFR21_LINI1_INT_M_0 (0x00000010uL)
+#define INTC_ICDICFR21_LINI1_INT_M_1 (0x00000020uL)
+#define INTC_ICDICFR21_ERI0_0 (0x00400000uL)
+#define INTC_ICDICFR21_ERI0_1 (0x00800000uL)
+#define INTC_ICDICFR21_RXI0_0 (0x01000000uL)
+#define INTC_ICDICFR21_RXI0_1 (0x02000000uL)
+#define INTC_ICDICFR21_TXI0_0 (0x04000000uL)
+#define INTC_ICDICFR21_TXI0_1 (0x08000000uL)
+#define INTC_ICDICFR21_TEI0_0 (0x10000000uL)
+#define INTC_ICDICFR21_TEI0_1 (0x20000000uL)
+#define INTC_ICDICFR21_ERI1_0 (0x40000000uL)
+#define INTC_ICDICFR21_ERI1_1 (0x80000000uL)
+
+#define INTC_ICDICFR22_RXI1_0 (0x00000001uL)
+#define INTC_ICDICFR22_RXI1_1 (0x00000002uL)
+#define INTC_ICDICFR22_TXI1_0 (0x00000004uL)
+#define INTC_ICDICFR22_TXI1_1 (0x00000008uL)
+#define INTC_ICDICFR22_TEI1_0 (0x00000010uL)
+#define INTC_ICDICFR22_TEI1_1 (0x00000020uL)
+#define INTC_ICDICFR22_AVBI_DATA_0 (0x00000040uL)
+#define INTC_ICDICFR22_AVBI_DATA_1 (0x00000080uL)
+#define INTC_ICDICFR22_AVBI_ERROR_0 (0x00000100uL)
+#define INTC_ICDICFR22_AVBI_ERROR_1 (0x00000200uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_0 (0x00000400uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_1 (0x00000800uL)
+#define INTC_ICDICFR22_AVBI_MAC_0 (0x00001000uL)
+#define INTC_ICDICFR22_AVBI_MAC_1 (0x00002000uL)
+#define INTC_ICDICFR22_ETHERI_0 (0x00004000uL)
+#define INTC_ICDICFR22_ETHERI_1 (0x00008000uL)
+#define INTC_ICDICFR22_CEUI_0 (0x01000000uL)
+#define INTC_ICDICFR22_CEUI_1 (0x02000000uL)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0 (0x04000000uL)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1 (0x08000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0 (0x10000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1 (0x20000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0 (0x40000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1 (0x80000000uL)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0 (0x00000001uL)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1 (0x00000002uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0 (0x00000004uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1 (0x00000008uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0 (0x00000010uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1 (0x00000020uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0 (0x00000040uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1 (0x00000080uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0 (0x00000100uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1 (0x00000200uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0 (0x00000400uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1 (0x00000800uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0 (0x00001000uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1 (0x00002000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0 (0x00004000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1 (0x00008000uL)
+#define INTC_ICDICFR24_PRRI_0 (0x00010000uL)
+#define INTC_ICDICFR24_PRRI_1 (0x00020000uL)
+#define INTC_ICDICFR24_IFEI0_0 (0x00040000uL)
+#define INTC_ICDICFR24_IFEI0_1 (0x00080000uL)
+#define INTC_ICDICFR24_OFFI0_0 (0x00100000uL)
+#define INTC_ICDICFR24_OFFI0_1 (0x00200000uL)
+#define INTC_ICDICFR24_PFVEI0_0 (0x00400000uL)
+#define INTC_ICDICFR24_PFVEI0_1 (0x00800000uL)
+#define INTC_ICDICFR24_IFEI1_0 (0x01000000uL)
+#define INTC_ICDICFR24_IFEI1_1 (0x02000000uL)
+#define INTC_ICDICFR24_OFFI1_0 (0x04000000uL)
+#define INTC_ICDICFR24_OFFI1_1 (0x08000000uL)
+#define INTC_ICDICFR24_PFVEI1_0 (0x10000000uL)
+#define INTC_ICDICFR24_PFVEI1_1 (0x20000000uL)
+
+#define INTC_ICDICFR26_TINT0_0 (0x00000001uL)
+#define INTC_ICDICFR26_TINT0_1 (0x00000002uL)
+#define INTC_ICDICFR26_TINT1_0 (0x00000004uL)
+#define INTC_ICDICFR26_TINT1_1 (0x00000008uL)
+#define INTC_ICDICFR26_TINT2_0 (0x00000010uL)
+#define INTC_ICDICFR26_TINT2_1 (0x00000020uL)
+#define INTC_ICDICFR26_TINT3_0 (0x00000040uL)
+#define INTC_ICDICFR26_TINT3_1 (0x00000080uL)
+#define INTC_ICDICFR26_TINT4_0 (0x00000100uL)
+#define INTC_ICDICFR26_TINT4_1 (0x00000200uL)
+#define INTC_ICDICFR26_TINT5_0 (0x00000400uL)
+#define INTC_ICDICFR26_TINT5_1 (0x00000800uL)
+#define INTC_ICDICFR26_TINT6_0 (0x00001000uL)
+#define INTC_ICDICFR26_TINT6_1 (0x00002000uL)
+#define INTC_ICDICFR26_TINT7_0 (0x00004000uL)
+#define INTC_ICDICFR26_TINT7_1 (0x00008000uL)
+#define INTC_ICDICFR26_TINT8_0 (0x00010000uL)
+#define INTC_ICDICFR26_TINT8_1 (0x00020000uL)
+#define INTC_ICDICFR26_TINT9_0 (0x00040000uL)
+#define INTC_ICDICFR26_TINT9_1 (0x00080000uL)
+#define INTC_ICDICFR26_TINT10_0 (0x00100000uL)
+#define INTC_ICDICFR26_TINT10_1 (0x00200000uL)
+#define INTC_ICDICFR26_TINT11_0 (0x00400000uL)
+#define INTC_ICDICFR26_TINT11_1 (0x00800000uL)
+#define INTC_ICDICFR26_TINT12_0 (0x01000000uL)
+#define INTC_ICDICFR26_TINT12_1 (0x02000000uL)
+#define INTC_ICDICFR26_TINT13_0 (0x04000000uL)
+#define INTC_ICDICFR26_TINT13_1 (0x08000000uL)
+#define INTC_ICDICFR26_TINT14_0 (0x10000000uL)
+#define INTC_ICDICFR26_TINT14_1 (0x20000000uL)
+#define INTC_ICDICFR26_TINT15_0 (0x40000000uL)
+#define INTC_ICDICFR26_TINT15_1 (0x80000000uL)
+
+#define INTC_ICDICFR27_TINT16_0 (0x00000001uL)
+#define INTC_ICDICFR27_TINT16_1 (0x00000002uL)
+#define INTC_ICDICFR27_TINT17_0 (0x00000004uL)
+#define INTC_ICDICFR27_TINT17_1 (0x00000008uL)
+#define INTC_ICDICFR27_TINT18_0 (0x00000010uL)
+#define INTC_ICDICFR27_TINT18_1 (0x00000020uL)
+#define INTC_ICDICFR27_TINT19_0 (0x00000040uL)
+#define INTC_ICDICFR27_TINT19_1 (0x00000080uL)
+#define INTC_ICDICFR27_TINT20_0 (0x00000100uL)
+#define INTC_ICDICFR27_TINT20_1 (0x00000200uL)
+#define INTC_ICDICFR27_TINT21_0 (0x00000400uL)
+#define INTC_ICDICFR27_TINT21_1 (0x00000800uL)
+#define INTC_ICDICFR27_TINT22_0 (0x00001000uL)
+#define INTC_ICDICFR27_TINT22_1 (0x00002000uL)
+#define INTC_ICDICFR27_TINT23_0 (0x00004000uL)
+#define INTC_ICDICFR27_TINT23_1 (0x00008000uL)
+#define INTC_ICDICFR27_TINT24_0 (0x00010000uL)
+#define INTC_ICDICFR27_TINT24_1 (0x00020000uL)
+#define INTC_ICDICFR27_TINT25_0 (0x00040000uL)
+#define INTC_ICDICFR27_TINT25_1 (0x00080000uL)
+#define INTC_ICDICFR27_TINT26_0 (0x00100000uL)
+#define INTC_ICDICFR27_TINT26_1 (0x00200000uL)
+#define INTC_ICDICFR27_TINT27_0 (0x00400000uL)
+#define INTC_ICDICFR27_TINT27_1 (0x00800000uL)
+#define INTC_ICDICFR27_TINT28_0 (0x01000000uL)
+#define INTC_ICDICFR27_TINT28_1 (0x02000000uL)
+#define INTC_ICDICFR27_TINT29_0 (0x04000000uL)
+#define INTC_ICDICFR27_TINT29_1 (0x08000000uL)
+#define INTC_ICDICFR27_TINT30_0 (0x10000000uL)
+#define INTC_ICDICFR27_TINT30_1 (0x20000000uL)
+#define INTC_ICDICFR27_TINT31_0 (0x40000000uL)
+#define INTC_ICDICFR27_TINT31_1 (0x80000000uL)
+
+#define INTC_ICDICFR28_TINT32_0 (0x00000001uL)
+#define INTC_ICDICFR28_TINT32_1 (0x00000002uL)
+#define INTC_ICDICFR28_TINT33_0 (0x00000004uL)
+#define INTC_ICDICFR28_TINT33_1 (0x00000008uL)
+#define INTC_ICDICFR28_TINT34_0 (0x00000010uL)
+#define INTC_ICDICFR28_TINT34_1 (0x00000020uL)
+#define INTC_ICDICFR28_TINT35_0 (0x00000040uL)
+#define INTC_ICDICFR28_TINT35_1 (0x00000080uL)
+#define INTC_ICDICFR28_TINT36_0 (0x00000100uL)
+#define INTC_ICDICFR28_TINT36_1 (0x00000200uL)
+#define INTC_ICDICFR28_TINT37_0 (0x00000400uL)
+#define INTC_ICDICFR28_TINT37_1 (0x00000800uL)
+#define INTC_ICDICFR28_TINT38_0 (0x00001000uL)
+#define INTC_ICDICFR28_TINT38_1 (0x00002000uL)
+#define INTC_ICDICFR28_TINT39_0 (0x00004000uL)
+#define INTC_ICDICFR28_TINT39_1 (0x00008000uL)
+#define INTC_ICDICFR28_TINT40_0 (0x00010000uL)
+#define INTC_ICDICFR28_TINT40_1 (0x00020000uL)
+#define INTC_ICDICFR28_TINT41_0 (0x00040000uL)
+#define INTC_ICDICFR28_TINT41_1 (0x00080000uL)
+#define INTC_ICDICFR28_TINT42_0 (0x00100000uL)
+#define INTC_ICDICFR28_TINT42_1 (0x00200000uL)
+#define INTC_ICDICFR28_TINT43_0 (0x00400000uL)
+#define INTC_ICDICFR28_TINT43_1 (0x00800000uL)
+#define INTC_ICDICFR28_TINT44_0 (0x01000000uL)
+#define INTC_ICDICFR28_TINT44_1 (0x02000000uL)
+#define INTC_ICDICFR28_TINT45_0 (0x04000000uL)
+#define INTC_ICDICFR28_TINT45_1 (0x08000000uL)
+#define INTC_ICDICFR28_TINT46_0 (0x10000000uL)
+#define INTC_ICDICFR28_TINT46_1 (0x20000000uL)
+#define INTC_ICDICFR28_TINT47_0 (0x40000000uL)
+#define INTC_ICDICFR28_TINT47_1 (0x80000000uL)
+
+#define INTC_ICDICFR29_TINT48_0 (0x00000001uL)
+#define INTC_ICDICFR29_TINT48_1 (0x00000002uL)
+#define INTC_ICDICFR29_TINT49_0 (0x00000004uL)
+#define INTC_ICDICFR29_TINT49_1 (0x00000008uL)
+#define INTC_ICDICFR29_TINT50_0 (0x00000010uL)
+#define INTC_ICDICFR29_TINT50_1 (0x00000020uL)
+#define INTC_ICDICFR29_TINT51_0 (0x00000040uL)
+#define INTC_ICDICFR29_TINT51_1 (0x00000080uL)
+#define INTC_ICDICFR29_TINT52_0 (0x00000100uL)
+#define INTC_ICDICFR29_TINT52_1 (0x00000200uL)
+#define INTC_ICDICFR29_TINT53_0 (0x00000400uL)
+#define INTC_ICDICFR29_TINT53_1 (0x00000800uL)
+#define INTC_ICDICFR29_TINT54_0 (0x00001000uL)
+#define INTC_ICDICFR29_TINT54_1 (0x00002000uL)
+#define INTC_ICDICFR29_TINT55_0 (0x00004000uL)
+#define INTC_ICDICFR29_TINT55_1 (0x00008000uL)
+#define INTC_ICDICFR29_TINT56_0 (0x00010000uL)
+#define INTC_ICDICFR29_TINT56_1 (0x00020000uL)
+#define INTC_ICDICFR29_TINT57_0 (0x00040000uL)
+#define INTC_ICDICFR29_TINT57_1 (0x00080000uL)
+#define INTC_ICDICFR29_TINT58_0 (0x00100000uL)
+#define INTC_ICDICFR29_TINT58_1 (0x00200000uL)
+#define INTC_ICDICFR29_TINT59_0 (0x00400000uL)
+#define INTC_ICDICFR29_TINT59_1 (0x00800000uL)
+#define INTC_ICDICFR29_TINT60_0 (0x01000000uL)
+#define INTC_ICDICFR29_TINT60_1 (0x02000000uL)
+#define INTC_ICDICFR29_TINT61_0 (0x04000000uL)
+#define INTC_ICDICFR29_TINT61_1 (0x08000000uL)
+#define INTC_ICDICFR29_TINT62_0 (0x10000000uL)
+#define INTC_ICDICFR29_TINT62_1 (0x20000000uL)
+#define INTC_ICDICFR29_TINT63_0 (0x40000000uL)
+#define INTC_ICDICFR29_TINT63_1 (0x80000000uL)
+
+#define INTC_ICDICFR30_TINT64_0 (0x00000001uL)
+#define INTC_ICDICFR30_TINT64_1 (0x00000002uL)
+#define INTC_ICDICFR30_TINT65_0 (0x00000004uL)
+#define INTC_ICDICFR30_TINT65_1 (0x00000008uL)
+#define INTC_ICDICFR30_TINT66_0 (0x00000010uL)
+#define INTC_ICDICFR30_TINT66_1 (0x00000020uL)
+#define INTC_ICDICFR30_TINT67_0 (0x00000040uL)
+#define INTC_ICDICFR30_TINT67_1 (0x00000080uL)
+#define INTC_ICDICFR30_TINT68_0 (0x00000100uL)
+#define INTC_ICDICFR30_TINT68_1 (0x00000200uL)
+#define INTC_ICDICFR30_TINT69_0 (0x00000400uL)
+#define INTC_ICDICFR30_TINT69_1 (0x00000800uL)
+#define INTC_ICDICFR30_TINT70_0 (0x00001000uL)
+#define INTC_ICDICFR30_TINT70_1 (0x00002000uL)
+#define INTC_ICDICFR30_TINT71_0 (0x00004000uL)
+#define INTC_ICDICFR30_TINT71_1 (0x00008000uL)
+#define INTC_ICDICFR30_TINT72_0 (0x00010000uL)
+#define INTC_ICDICFR30_TINT72_1 (0x00020000uL)
+#define INTC_ICDICFR30_TINT73_0 (0x00040000uL)
+#define INTC_ICDICFR30_TINT73_1 (0x00080000uL)
+#define INTC_ICDICFR30_TINT74_0 (0x00100000uL)
+#define INTC_ICDICFR30_TINT74_1 (0x00200000uL)
+#define INTC_ICDICFR30_TINT75_0 (0x00400000uL)
+#define INTC_ICDICFR30_TINT75_1 (0x00800000uL)
+#define INTC_ICDICFR30_TINT76_0 (0x01000000uL)
+#define INTC_ICDICFR30_TINT76_1 (0x02000000uL)
+#define INTC_ICDICFR30_TINT77_0 (0x04000000uL)
+#define INTC_ICDICFR30_TINT77_1 (0x08000000uL)
+#define INTC_ICDICFR30_TINT78_0 (0x10000000uL)
+#define INTC_ICDICFR30_TINT78_1 (0x20000000uL)
+#define INTC_ICDICFR30_TINT79_0 (0x40000000uL)
+#define INTC_ICDICFR30_TINT79_1 (0x80000000uL)
+
+#define INTC_ICDICFR31_TINT80_0 (0x00000001uL)
+#define INTC_ICDICFR31_TINT80_1 (0x00000002uL)
+#define INTC_ICDICFR31_TINT81_0 (0x00000004uL)
+#define INTC_ICDICFR31_TINT81_1 (0x00000008uL)
+#define INTC_ICDICFR31_TINT82_0 (0x00000010uL)
+#define INTC_ICDICFR31_TINT82_1 (0x00000020uL)
+#define INTC_ICDICFR31_TINT83_0 (0x00000040uL)
+#define INTC_ICDICFR31_TINT83_1 (0x00000080uL)
+#define INTC_ICDICFR31_TINT84_0 (0x00000100uL)
+#define INTC_ICDICFR31_TINT84_1 (0x00000200uL)
+#define INTC_ICDICFR31_TINT85_0 (0x00000400uL)
+#define INTC_ICDICFR31_TINT85_1 (0x00000800uL)
+#define INTC_ICDICFR31_TINT86_0 (0x00001000uL)
+#define INTC_ICDICFR31_TINT86_1 (0x00002000uL)
+#define INTC_ICDICFR31_TINT87_0 (0x00004000uL)
+#define INTC_ICDICFR31_TINT87_1 (0x00008000uL)
+#define INTC_ICDICFR31_TINT88_0 (0x00010000uL)
+#define INTC_ICDICFR31_TINT88_1 (0x00020000uL)
+#define INTC_ICDICFR31_TINT89_0 (0x00040000uL)
+#define INTC_ICDICFR31_TINT89_1 (0x00080000uL)
+#define INTC_ICDICFR31_TINT90_0 (0x00100000uL)
+#define INTC_ICDICFR31_TINT90_1 (0x00200000uL)
+#define INTC_ICDICFR31_TINT91_0 (0x00400000uL)
+#define INTC_ICDICFR31_TINT91_1 (0x00800000uL)
+#define INTC_ICDICFR31_TINT92_0 (0x01000000uL)
+#define INTC_ICDICFR31_TINT92_1 (0x02000000uL)
+#define INTC_ICDICFR31_TINT93_0 (0x04000000uL)
+#define INTC_ICDICFR31_TINT93_1 (0x08000000uL)
+#define INTC_ICDICFR31_TINT94_0 (0x10000000uL)
+#define INTC_ICDICFR31_TINT94_1 (0x20000000uL)
+#define INTC_ICDICFR31_TINT95_0 (0x40000000uL)
+#define INTC_ICDICFR31_TINT95_1 (0x80000000uL)
+
+#define INTC_ICDICFR32_TINT96_0 (0x00000001uL)
+#define INTC_ICDICFR32_TINT96_1 (0x00000002uL)
+#define INTC_ICDICFR32_TINT97_0 (0x00000004uL)
+#define INTC_ICDICFR32_TINT97_1 (0x00000008uL)
+#define INTC_ICDICFR32_TINT98_0 (0x00000010uL)
+#define INTC_ICDICFR32_TINT98_1 (0x00000020uL)
+#define INTC_ICDICFR32_TINT99_0 (0x00000040uL)
+#define INTC_ICDICFR32_TINT99_1 (0x00000080uL)
+#define INTC_ICDICFR32_TINT100_0 (0x00000100uL)
+#define INTC_ICDICFR32_TINT100_1 (0x00000200uL)
+#define INTC_ICDICFR32_TINT101_0 (0x00000400uL)
+#define INTC_ICDICFR32_TINT101_1 (0x00000800uL)
+#define INTC_ICDICFR32_TINT102_0 (0x00001000uL)
+#define INTC_ICDICFR32_TINT102_1 (0x00002000uL)
+#define INTC_ICDICFR32_TINT103_0 (0x00004000uL)
+#define INTC_ICDICFR32_TINT103_1 (0x00008000uL)
+#define INTC_ICDICFR32_TINT104_0 (0x00010000uL)
+#define INTC_ICDICFR32_TINT104_1 (0x00020000uL)
+#define INTC_ICDICFR32_TINT105_0 (0x00040000uL)
+#define INTC_ICDICFR32_TINT105_1 (0x00080000uL)
+#define INTC_ICDICFR32_TINT106_0 (0x00100000uL)
+#define INTC_ICDICFR32_TINT106_1 (0x00200000uL)
+#define INTC_ICDICFR32_TINT107_0 (0x00400000uL)
+#define INTC_ICDICFR32_TINT107_1 (0x00800000uL)
+#define INTC_ICDICFR32_TINT108_0 (0x01000000uL)
+#define INTC_ICDICFR32_TINT108_1 (0x02000000uL)
+#define INTC_ICDICFR32_TINT109_0 (0x04000000uL)
+#define INTC_ICDICFR32_TINT109_1 (0x08000000uL)
+#define INTC_ICDICFR32_TINT110_0 (0x10000000uL)
+#define INTC_ICDICFR32_TINT110_1 (0x20000000uL)
+#define INTC_ICDICFR32_TINT111_0 (0x40000000uL)
+#define INTC_ICDICFR32_TINT111_1 (0x80000000uL)
+
+#define INTC_ICDICFR33_TINT112_0 (0x00000001uL)
+#define INTC_ICDICFR33_TINT112_1 (0x00000002uL)
+#define INTC_ICDICFR33_TINT113_0 (0x00000004uL)
+#define INTC_ICDICFR33_TINT113_1 (0x00000008uL)
+#define INTC_ICDICFR33_TINT114_0 (0x00000010uL)
+#define INTC_ICDICFR33_TINT114_1 (0x00000020uL)
+#define INTC_ICDICFR33_TINT115_0 (0x00000040uL)
+#define INTC_ICDICFR33_TINT115_1 (0x00000080uL)
+#define INTC_ICDICFR33_TINT116_0 (0x00000100uL)
+#define INTC_ICDICFR33_TINT116_1 (0x00000200uL)
+#define INTC_ICDICFR33_TINT117_0 (0x00000400uL)
+#define INTC_ICDICFR33_TINT117_1 (0x00000800uL)
+#define INTC_ICDICFR33_TINT118_0 (0x00001000uL)
+#define INTC_ICDICFR33_TINT118_1 (0x00002000uL)
+#define INTC_ICDICFR33_TINT119_0 (0x00004000uL)
+#define INTC_ICDICFR33_TINT119_1 (0x00008000uL)
+#define INTC_ICDICFR33_TINT120_0 (0x00010000uL)
+#define INTC_ICDICFR33_TINT120_1 (0x00020000uL)
+#define INTC_ICDICFR33_TINT121_0 (0x00040000uL)
+#define INTC_ICDICFR33_TINT121_1 (0x00080000uL)
+#define INTC_ICDICFR33_TINT122_0 (0x00100000uL)
+#define INTC_ICDICFR33_TINT122_1 (0x00200000uL)
+#define INTC_ICDICFR33_TINT123_0 (0x00400000uL)
+#define INTC_ICDICFR33_TINT123_1 (0x00800000uL)
+#define INTC_ICDICFR33_TINT124_0 (0x01000000uL)
+#define INTC_ICDICFR33_TINT124_1 (0x02000000uL)
+#define INTC_ICDICFR33_TINT125_0 (0x04000000uL)
+#define INTC_ICDICFR33_TINT125_1 (0x08000000uL)
+#define INTC_ICDICFR33_TINT126_0 (0x10000000uL)
+#define INTC_ICDICFR33_TINT126_1 (0x20000000uL)
+#define INTC_ICDICFR33_TINT127_0 (0x40000000uL)
+#define INTC_ICDICFR33_TINT127_1 (0x80000000uL)
+
+#define INTC_ICDICFR34_TINT128_0 (0x00000001uL)
+#define INTC_ICDICFR34_TINT128_1 (0x00000002uL)
+#define INTC_ICDICFR34_TINT129_0 (0x00000004uL)
+#define INTC_ICDICFR34_TINT129_1 (0x00000008uL)
+#define INTC_ICDICFR34_TINT130_0 (0x00000010uL)
+#define INTC_ICDICFR34_TINT130_1 (0x00000020uL)
+#define INTC_ICDICFR34_TINT131_0 (0x00000040uL)
+#define INTC_ICDICFR34_TINT131_1 (0x00000080uL)
+#define INTC_ICDICFR34_TINT132_0 (0x00000100uL)
+#define INTC_ICDICFR34_TINT132_1 (0x00000200uL)
+#define INTC_ICDICFR34_TINT133_0 (0x00000400uL)
+#define INTC_ICDICFR34_TINT133_1 (0x00000800uL)
+#define INTC_ICDICFR34_TINT134_0 (0x00001000uL)
+#define INTC_ICDICFR34_TINT134_1 (0x00002000uL)
+#define INTC_ICDICFR34_TINT135_0 (0x00004000uL)
+#define INTC_ICDICFR34_TINT135_1 (0x00008000uL)
+#define INTC_ICDICFR34_TINT136_0 (0x00010000uL)
+#define INTC_ICDICFR34_TINT136_1 (0x00020000uL)
+#define INTC_ICDICFR34_TINT137_0 (0x00040000uL)
+#define INTC_ICDICFR34_TINT137_1 (0x00080000uL)
+#define INTC_ICDICFR34_TINT138_0 (0x00100000uL)
+#define INTC_ICDICFR34_TINT138_1 (0x00200000uL)
+#define INTC_ICDICFR34_TINT139_0 (0x00400000uL)
+#define INTC_ICDICFR34_TINT139_1 (0x00800000uL)
+#define INTC_ICDICFR34_TINT140_0 (0x01000000uL)
+#define INTC_ICDICFR34_TINT140_1 (0x02000000uL)
+#define INTC_ICDICFR34_TINT141_0 (0x04000000uL)
+#define INTC_ICDICFR34_TINT141_1 (0x08000000uL)
+#define INTC_ICDICFR34_TINT142_0 (0x10000000uL)
+#define INTC_ICDICFR34_TINT142_1 (0x20000000uL)
+#define INTC_ICDICFR34_TINT143_0 (0x40000000uL)
+#define INTC_ICDICFR34_TINT143_1 (0x80000000uL)
+
+#define INTC_ICDICFR35_TINT144_0 (0x00000001uL)
+#define INTC_ICDICFR35_TINT144_1 (0x00000002uL)
+#define INTC_ICDICFR35_TINT145_0 (0x00000004uL)
+#define INTC_ICDICFR35_TINT145_1 (0x00000008uL)
+#define INTC_ICDICFR35_TINT146_0 (0x00000010uL)
+#define INTC_ICDICFR35_TINT146_1 (0x00000020uL)
+#define INTC_ICDICFR35_TINT147_0 (0x00000040uL)
+#define INTC_ICDICFR35_TINT147_1 (0x00000080uL)
+#define INTC_ICDICFR35_TINT148_0 (0x00000100uL)
+#define INTC_ICDICFR35_TINT148_1 (0x00000200uL)
+#define INTC_ICDICFR35_TINT149_0 (0x00000400uL)
+#define INTC_ICDICFR35_TINT149_1 (0x00000800uL)
+#define INTC_ICDICFR35_TINT150_0 (0x00001000uL)
+#define INTC_ICDICFR35_TINT150_1 (0x00002000uL)
+#define INTC_ICDICFR35_TINT151_0 (0x00004000uL)
+#define INTC_ICDICFR35_TINT151_1 (0x00008000uL)
+#define INTC_ICDICFR35_TINT152_0 (0x00010000uL)
+#define INTC_ICDICFR35_TINT152_1 (0x00020000uL)
+#define INTC_ICDICFR35_TINT153_0 (0x00040000uL)
+#define INTC_ICDICFR35_TINT153_1 (0x00080000uL)
+#define INTC_ICDICFR35_TINT154_0 (0x00100000uL)
+#define INTC_ICDICFR35_TINT154_1 (0x00200000uL)
+#define INTC_ICDICFR35_TINT155_0 (0x00400000uL)
+#define INTC_ICDICFR35_TINT155_1 (0x00800000uL)
+#define INTC_ICDICFR35_TINT156_0 (0x01000000uL)
+#define INTC_ICDICFR35_TINT156_1 (0x02000000uL)
+#define INTC_ICDICFR35_TINT157_0 (0x04000000uL)
+#define INTC_ICDICFR35_TINT157_1 (0x08000000uL)
+#define INTC_ICDICFR35_TINT158_0 (0x10000000uL)
+#define INTC_ICDICFR35_TINT158_1 (0x20000000uL)
+#define INTC_ICDICFR35_TINT159_0 (0x40000000uL)
+#define INTC_ICDICFR35_TINT159_1 (0x80000000uL)
+
+#define INTC_ICDICFR36_TINT160_0 (0x00000001uL)
+#define INTC_ICDICFR36_TINT160_1 (0x00000002uL)
+#define INTC_ICDICFR36_TINT161_0 (0x00000004uL)
+#define INTC_ICDICFR36_TINT161_1 (0x00000008uL)
+#define INTC_ICDICFR36_TINT162_0 (0x00000010uL)
+#define INTC_ICDICFR36_TINT162_1 (0x00000020uL)
+#define INTC_ICDICFR36_TINT163_0 (0x00000040uL)
+#define INTC_ICDICFR36_TINT163_1 (0x00000080uL)
+#define INTC_ICDICFR36_TINT164_0 (0x00000100uL)
+#define INTC_ICDICFR36_TINT164_1 (0x00000200uL)
+#define INTC_ICDICFR36_TINT165_0 (0x00000400uL)
+#define INTC_ICDICFR36_TINT165_1 (0x00000800uL)
+#define INTC_ICDICFR36_TINT166_0 (0x00001000uL)
+#define INTC_ICDICFR36_TINT166_1 (0x00002000uL)
+#define INTC_ICDICFR36_TINT167_0 (0x00004000uL)
+#define INTC_ICDICFR36_TINT167_1 (0x00008000uL)
+#define INTC_ICDICFR36_TINT168_0 (0x00010000uL)
+#define INTC_ICDICFR36_TINT168_1 (0x00020000uL)
+#define INTC_ICDICFR36_TINT169_0 (0x00040000uL)
+#define INTC_ICDICFR36_TINT169_1 (0x00080000uL)
+#define INTC_ICDICFR36_TINT170_0 (0x00100000uL)
+#define INTC_ICDICFR36_TINT170_1 (0x00200000uL)
+
+#define INTC_ICDSGIR_SGIINTID (0x0000000FuL)
+#define INTC_ICDSGIR_SATT (0x00008000uL)
+#define INTC_ICDSGIR_CPUTargetList (0x00FF0000uL)
+#define INTC_ICDSGIR_TargetListFilter (0x03000000uL)
+
+#define INTC_ICCICR_EnableS (0x00000001uL)
+#define INTC_ICCICR_EnableNS (0x00000002uL)
+#define INTC_ICCICR_AckCtl (0x00000004uL)
+#define INTC_ICCICR_FIQEn (0x00000008uL)
+#define INTC_ICCICR_SBPR (0x00000010uL)
+
+#define INTC_ICCPMR_Priority (0x000000FFuL)
+
+#define INTC_ICCBPR_Binarypoint (0x00000007uL)
+
+#define INTC_ICCIAR_ACKINTID (0x000003FFuL)
+#define INTC_ICCIAR_CPUID (0x00001C00uL)
+
+#define INTC_ICCEOIR_EOIINTID (0x000003FFuL)
+#define INTC_ICCEOIR_CPUID (0x00001C00uL)
+
+#define INTC_ICCRPR_Priority (0x000000FFuL)
+
+#define INTC_ICCHPIR_PENDINTID (0x000003FFuL)
+#define INTC_ICCHPIR_CPUID (0x00001C00uL)
+
+#define INTC_ICCABPR_Binarypoint (0x00000007uL)
+
+#define INTC_ICCIIDR_Implementer (0x00000FFFuL)
+#define INTC_ICCIIDR_Revision (0x0000F000uL)
+#define INTC_ICCIIDR_Architecture_version (0x000F0000uL)
+#define INTC_ICCIIDR_ProductID (0xFFF00000uL)
+
+#define INTC_ICR0_NMIF (0x0002u)
+#define INTC_ICR0_NMIE (0x0100u)
+#define INTC_ICR0_NMIL (0x8000u)
+
+#define INTC_ICR1_IRQ00S (0x0001u)
+#define INTC_ICR1_IRQ01S (0x0002u)
+#define INTC_ICR1_IRQ10S (0x0004u)
+#define INTC_ICR1_IRQ11S (0x0008u)
+#define INTC_ICR1_IRQ20S (0x0010u)
+#define INTC_ICR1_IRQ21S (0x0020u)
+#define INTC_ICR1_IRQ30S (0x0040u)
+#define INTC_ICR1_IRQ31S (0x0080u)
+#define INTC_ICR1_IRQ40S (0x0100u)
+#define INTC_ICR1_IRQ41S (0x0200u)
+#define INTC_ICR1_IRQ50S (0x0400u)
+#define INTC_ICR1_IRQ51S (0x0800u)
+#define INTC_ICR1_IRQ60S (0x1000u)
+#define INTC_ICR1_IRQ61S (0x2000u)
+#define INTC_ICR1_IRQ70S (0x4000u)
+#define INTC_ICR1_IRQ71S (0x8000u)
+
+#define INTC_IRQRR_IRQ0F (0x0001u)
+#define INTC_IRQRR_IRQ1F (0x0002u)
+#define INTC_IRQRR_IRQ2F (0x0004u)
+#define INTC_IRQRR_IRQ3F (0x0008u)
+#define INTC_IRQRR_IRQ4F (0x0010u)
+#define INTC_IRQRR_IRQ5F (0x0020u)
+#define INTC_IRQRR_IRQ6F (0x0040u)
+#define INTC_IRQRR_IRQ7F (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define INTC_ICDDCR_Enable_SHIFT (0u)
+
+#define INTC_ICDICTR_ITLinesNumber_SHIFT (0u)
+#define INTC_ICDICTR_CPUNumber_SHIFT (5u)
+#define INTC_ICDICTR_SecurityExtn_SHIFT (10u)
+#define INTC_ICDICTR_LSPI_SHIFT (11u)
+
+#define INTC_ICDIIDR_Implementer_SHIFT (0u)
+#define INTC_ICDIIDR_Revision_SHIFT (12u)
+#define INTC_ICDIIDR_Variant_SHIFT (16u)
+#define INTC_ICDIIDR_ProductID_SHIFT (24u)
+
+#define INTC_ICDISR0_SW0_SHIFT (0u)
+#define INTC_ICDISR0_SW1_SHIFT (1u)
+#define INTC_ICDISR0_SW2_SHIFT (2u)
+#define INTC_ICDISR0_SW3_SHIFT (3u)
+#define INTC_ICDISR0_SW4_SHIFT (4u)
+#define INTC_ICDISR0_SW5_SHIFT (5u)
+#define INTC_ICDISR0_SW6_SHIFT (6u)
+#define INTC_ICDISR0_SW7_SHIFT (7u)
+#define INTC_ICDISR0_SW8_SHIFT (8u)
+#define INTC_ICDISR0_SW9_SHIFT (9u)
+#define INTC_ICDISR0_SW10_SHIFT (10u)
+#define INTC_ICDISR0_SW11_SHIFT (11u)
+#define INTC_ICDISR0_SW12_SHIFT (12u)
+#define INTC_ICDISR0_SW13_SHIFT (13u)
+#define INTC_ICDISR0_SW14_SHIFT (14u)
+#define INTC_ICDISR0_SW15_SHIFT (15u)
+#define INTC_ICDISR0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDISR0_COMMRX0_SHIFT (17u)
+#define INTC_ICDISR0_COMMTX0_SHIFT (18u)
+#define INTC_ICDISR0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDISR1_IRQ0_SHIFT (0u)
+#define INTC_ICDISR1_IRQ1_SHIFT (1u)
+#define INTC_ICDISR1_IRQ2_SHIFT (2u)
+#define INTC_ICDISR1_IRQ3_SHIFT (3u)
+#define INTC_ICDISR1_IRQ4_SHIFT (4u)
+#define INTC_ICDISR1_IRQ5_SHIFT (5u)
+#define INTC_ICDISR1_IRQ6_SHIFT (6u)
+#define INTC_ICDISR1_IRQ7_SHIFT (7u)
+#define INTC_ICDISR1_PL310ERR_SHIFT (8u)
+#define INTC_ICDISR1_DMAINT0_SHIFT (9u)
+#define INTC_ICDISR1_DMAINT1_SHIFT (10u)
+#define INTC_ICDISR1_DMAINT2_SHIFT (11u)
+#define INTC_ICDISR1_DMAINT3_SHIFT (12u)
+#define INTC_ICDISR1_DMAINT4_SHIFT (13u)
+#define INTC_ICDISR1_DMAINT5_SHIFT (14u)
+#define INTC_ICDISR1_DMAINT6_SHIFT (15u)
+#define INTC_ICDISR1_DMAINT7_SHIFT (16u)
+#define INTC_ICDISR1_DMAINT8_SHIFT (17u)
+#define INTC_ICDISR1_DMAINT9_SHIFT (18u)
+#define INTC_ICDISR1_DMAINT10_SHIFT (19u)
+#define INTC_ICDISR1_DMAINT11_SHIFT (20u)
+#define INTC_ICDISR1_DMAINT12_SHIFT (21u)
+#define INTC_ICDISR1_DMAINT13_SHIFT (22u)
+#define INTC_ICDISR1_DMAINT14_SHIFT (23u)
+#define INTC_ICDISR1_DMAINT15_SHIFT (24u)
+#define INTC_ICDISR1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDISR2_USBI0_SHIFT (9u)
+#define INTC_ICDISR2_USBI1_SHIFT (10u)
+#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDISR2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDISR2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDISR2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDISR2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDISR2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDISR2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDISR3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDISR3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDISR3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDISR3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDISR3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDISR3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDISR3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDISR3_IMRDI_SHIFT (27u)
+#define INTC_ICDISR3_IMR2I0_SHIFT (28u)
+#define INTC_ICDISR3_IMR2I1_SHIFT (29u)
+#define INTC_ICDISR3_JEDI_SHIFT (30u)
+#define INTC_ICDISR3_JDTI_SHIFT (31u)
+
+#define INTC_ICDISR4_CMP0_SHIFT (0u)
+#define INTC_ICDISR4_CMP1_SHIFT (1u)
+#define INTC_ICDISR4_INT0_SHIFT (2u)
+#define INTC_ICDISR4_INT1_SHIFT (3u)
+#define INTC_ICDISR4_INT2_SHIFT (4u)
+#define INTC_ICDISR4_INT3_SHIFT (5u)
+#define INTC_ICDISR4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDISR4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDISR4_CMI_SHIFT (8u)
+#define INTC_ICDISR4_WTOUT_SHIFT (9u)
+#define INTC_ICDISR4_ITI_SHIFT (10u)
+#define INTC_ICDISR4_TGI0A_SHIFT (11u)
+#define INTC_ICDISR4_TGI0B_SHIFT (12u)
+#define INTC_ICDISR4_TGI0C_SHIFT (13u)
+#define INTC_ICDISR4_TGI0D_SHIFT (14u)
+#define INTC_ICDISR4_TGI0V_SHIFT (15u)
+#define INTC_ICDISR4_TGI0E_SHIFT (16u)
+#define INTC_ICDISR4_TGI0F_SHIFT (17u)
+#define INTC_ICDISR4_TGI1A_SHIFT (18u)
+#define INTC_ICDISR4_TGI1B_SHIFT (19u)
+#define INTC_ICDISR4_TGI1V_SHIFT (20u)
+#define INTC_ICDISR4_TGI1U_SHIFT (21u)
+#define INTC_ICDISR4_TGI2A_SHIFT (22u)
+#define INTC_ICDISR4_TGI2B_SHIFT (23u)
+#define INTC_ICDISR4_TGI2V_SHIFT (24u)
+#define INTC_ICDISR4_TGI2U_SHIFT (25u)
+#define INTC_ICDISR4_TGI3A_SHIFT (26u)
+#define INTC_ICDISR4_TGI3B_SHIFT (27u)
+#define INTC_ICDISR4_TGI3C_SHIFT (28u)
+#define INTC_ICDISR4_TGI3D_SHIFT (29u)
+#define INTC_ICDISR4_TGI3V_SHIFT (30u)
+#define INTC_ICDISR4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDISR5_TGI4B_SHIFT (0u)
+#define INTC_ICDISR5_TGI4C_SHIFT (1u)
+#define INTC_ICDISR5_TGI4D_SHIFT (2u)
+#define INTC_ICDISR5_TGI4V_SHIFT (3u)
+#define INTC_ICDISR5_CMI1_SHIFT (4u)
+#define INTC_ICDISR5_CMI2_SHIFT (5u)
+#define INTC_ICDISR5_SGDEI0_SHIFT (6u)
+#define INTC_ICDISR5_SGDEI1_SHIFT (7u)
+#define INTC_ICDISR5_SGDEI2_SHIFT (8u)
+#define INTC_ICDISR5_SGDEI3_SHIFT (9u)
+#define INTC_ICDISR5_ADI_SHIFT (10u)
+#define INTC_ICDISR5_LMTI_SHIFT (11u)
+#define INTC_ICDISR5_SSII0_SHIFT (12u)
+#define INTC_ICDISR5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDISR5_SSITXI0_SHIFT (14u)
+#define INTC_ICDISR5_SSII1_SHIFT (15u)
+#define INTC_ICDISR5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDISR5_SSITXI1_SHIFT (17u)
+#define INTC_ICDISR5_SSII2_SHIFT (18u)
+#define INTC_ICDISR5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDISR5_SSII3_SHIFT (20u)
+#define INTC_ICDISR5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDISR5_SSITXI3_SHIFT (22u)
+#define INTC_ICDISR5_SSII4_SHIFT (23u)
+#define INTC_ICDISR5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDISR5_SSII5_SHIFT (25u)
+#define INTC_ICDISR5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDISR5_SSITXI5_SHIFT (27u)
+#define INTC_ICDISR5_SPDIFI_SHIFT (28u)
+#define INTC_ICDISR5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDISR5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDISR5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDISR6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDISR6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDISR6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDISR6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDISR6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDISR6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDISR6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDISR6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDISR6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDISR6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDISR6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDISR6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDISR6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDISR6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDISR6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDISR6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDISR6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDISR6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDISR6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDISR6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDISR6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDISR6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDISR6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDISR6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDISR6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDISR6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDISR6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDISR6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDISR6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDISR6_BRI0_SHIFT (29u)
+#define INTC_ICDISR6_ERI0_SHIFT (30u)
+#define INTC_ICDISR6_RXI0_SHIFT (31u)
+
+#define INTC_ICDISR7_TXI0_SHIFT (0u)
+#define INTC_ICDISR7_BRI1_SHIFT (1u)
+#define INTC_ICDISR7_ERI1_SHIFT (2u)
+#define INTC_ICDISR7_RXI1_SHIFT (3u)
+#define INTC_ICDISR7_TXI1_SHIFT (4u)
+#define INTC_ICDISR7_BRI2_SHIFT (5u)
+#define INTC_ICDISR7_ERI2_SHIFT (6u)
+#define INTC_ICDISR7_RXI2_SHIFT (7u)
+#define INTC_ICDISR7_TXI2_SHIFT (8u)
+#define INTC_ICDISR7_BRI3_SHIFT (9u)
+#define INTC_ICDISR7_ERI3_SHIFT (10u)
+#define INTC_ICDISR7_RXI3_SHIFT (11u)
+#define INTC_ICDISR7_TXI3_SHIFT (12u)
+#define INTC_ICDISR7_BRI4_SHIFT (13u)
+#define INTC_ICDISR7_ERI4_SHIFT (14u)
+#define INTC_ICDISR7_RXI4_SHIFT (15u)
+#define INTC_ICDISR7_TXI4_SHIFT (16u)
+#define INTC_ICDISR7_BRI5_SHIFT (17u)
+#define INTC_ICDISR7_ERI5_SHIFT (18u)
+#define INTC_ICDISR7_RXI5_SHIFT (19u)
+#define INTC_ICDISR7_TXI5_SHIFT (20u)
+#define INTC_ICDISR7_BRI6_SHIFT (21u)
+#define INTC_ICDISR7_ERI6_SHIFT (22u)
+#define INTC_ICDISR7_RXI6_SHIFT (23u)
+#define INTC_ICDISR7_TXI6_SHIFT (24u)
+#define INTC_ICDISR7_BRI7_SHIFT (25u)
+#define INTC_ICDISR7_ERI7_SHIFT (26u)
+#define INTC_ICDISR7_RXI7_SHIFT (27u)
+#define INTC_ICDISR7_TXI7_SHIFT (28u)
+#define INTC_ICDISR7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDISR7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDISR7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDISR8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDISR8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDISR8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDISR8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDISR8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDISR8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDISR8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDISR8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDISR8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDISR8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDISR8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDISR8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDISR8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDISR8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDISR8_SPEI0_SHIFT (14u)
+#define INTC_ICDISR8_SPRI0_SHIFT (15u)
+#define INTC_ICDISR8_SPTI0_SHIFT (16u)
+#define INTC_ICDISR8_SPEI1_SHIFT (17u)
+#define INTC_ICDISR8_SPRI1_SHIFT (18u)
+#define INTC_ICDISR8_SPTI1_SHIFT (19u)
+#define INTC_ICDISR8_SPEI2_SHIFT (20u)
+#define INTC_ICDISR8_SPRI2_SHIFT (21u)
+#define INTC_ICDISR8_SPTI2_SHIFT (22u)
+#define INTC_ICDISR8_SPEI3_SHIFT (23u)
+#define INTC_ICDISR8_SPRI3_SHIFT (24u)
+#define INTC_ICDISR8_SPTI3_SHIFT (25u)
+#define INTC_ICDISR8_SPEI4_SHIFT (26u)
+#define INTC_ICDISR8_SPRI4_SHIFT (27u)
+#define INTC_ICDISR8_SPTI4_SHIFT (28u)
+#define INTC_ICDISR8_IEBBTD_SHIFT (29u)
+#define INTC_ICDISR8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDISR8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDISR9_IEBBTV_SHIFT (0u)
+#define INTC_ICDISR9_ISY_SHIFT (1u)
+#define INTC_ICDISR9_IERR_SHIFT (2u)
+#define INTC_ICDISR9_ITARG_SHIFT (3u)
+#define INTC_ICDISR9_ISEC_SHIFT (4u)
+#define INTC_ICDISR9_IBUF_SHIFT (5u)
+#define INTC_ICDISR9_IREADY_SHIFT (6u)
+#define INTC_ICDISR9_FLSTE_SHIFT (7u)
+#define INTC_ICDISR9_FLTENDI_SHIFT (8u)
+#define INTC_ICDISR9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDISR9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDISR9_MMC0_SHIFT (11u)
+#define INTC_ICDISR9_MMC1_SHIFT (12u)
+#define INTC_ICDISR9_MMC2_SHIFT (13u)
+#define INTC_ICDISR9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDISR9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDISR9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDISR9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDISR9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDISR9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDISR9_ARM_SHIFT (20u)
+#define INTC_ICDISR9_PRD_SHIFT (21u)
+#define INTC_ICDISR9_CUP_SHIFT (22u)
+#define INTC_ICDISR9_SCUAI0_SHIFT (23u)
+#define INTC_ICDISR9_SCUAI1_SHIFT (24u)
+#define INTC_ICDISR9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDISR9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDISR9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDISR9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDISR9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDISR9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDISR9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDISR10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDISR10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDISR10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDISR10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDISR10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDISR10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDISR10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDISR10_DRC0_SHIFT (7u)
+#define INTC_ICDISR10_DRC1_SHIFT (8u)
+#define INTC_ICDISR10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDISR10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDISR10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDISR10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDISR10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDISR10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDISR10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDISR10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDISR10_ERI0_SHIFT (27u)
+#define INTC_ICDISR10_RXI0_SHIFT (28u)
+#define INTC_ICDISR10_TXI0_SHIFT (29u)
+#define INTC_ICDISR10_TEI0_SHIFT (30u)
+#define INTC_ICDISR10_ERI1_SHIFT (31u)
+
+#define INTC_ICDISR11_RXI1_SHIFT (0u)
+#define INTC_ICDISR11_TXI1_SHIFT (1u)
+#define INTC_ICDISR11_TEI1_SHIFT (2u)
+#define INTC_ICDISR11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDISR11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDISR11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDISR11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDISR11_ETHERI_SHIFT (7u)
+#define INTC_ICDISR11_CEUI_SHIFT (12u)
+#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDISR12_PRRI_SHIFT (8u)
+#define INTC_ICDISR12_IFEI0_SHIFT (9u)
+#define INTC_ICDISR12_OFFI0_SHIFT (10u)
+#define INTC_ICDISR12_PFVEI0_SHIFT (11u)
+#define INTC_ICDISR12_IFEI1_SHIFT (12u)
+#define INTC_ICDISR12_OFFI1_SHIFT (13u)
+#define INTC_ICDISR12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDISR13_TINT0_SHIFT (0u)
+#define INTC_ICDISR13_TINT1_SHIFT (1u)
+#define INTC_ICDISR13_TINT2_SHIFT (2u)
+#define INTC_ICDISR13_TINT3_SHIFT (3u)
+#define INTC_ICDISR13_TINT4_SHIFT (4u)
+#define INTC_ICDISR13_TINT5_SHIFT (5u)
+#define INTC_ICDISR13_TINT6_SHIFT (6u)
+#define INTC_ICDISR13_TINT7_SHIFT (7u)
+#define INTC_ICDISR13_TINT8_SHIFT (8u)
+#define INTC_ICDISR13_TINT9_SHIFT (9u)
+#define INTC_ICDISR13_TINT10_SHIFT (10u)
+#define INTC_ICDISR13_TINT11_SHIFT (11u)
+#define INTC_ICDISR13_TINT12_SHIFT (12u)
+#define INTC_ICDISR13_TINT13_SHIFT (13u)
+#define INTC_ICDISR13_TINT14_SHIFT (14u)
+#define INTC_ICDISR13_TINT15_SHIFT (15u)
+#define INTC_ICDISR13_TINT16_SHIFT (16u)
+#define INTC_ICDISR13_TINT17_SHIFT (17u)
+#define INTC_ICDISR13_TINT18_SHIFT (18u)
+#define INTC_ICDISR13_TINT19_SHIFT (19u)
+#define INTC_ICDISR13_TINT20_SHIFT (20u)
+#define INTC_ICDISR13_TINT21_SHIFT (21u)
+#define INTC_ICDISR13_TINT22_SHIFT (22u)
+#define INTC_ICDISR13_TINT23_SHIFT (23u)
+#define INTC_ICDISR13_TINT24_SHIFT (24u)
+#define INTC_ICDISR13_TINT25_SHIFT (25u)
+#define INTC_ICDISR13_TINT26_SHIFT (26u)
+#define INTC_ICDISR13_TINT27_SHIFT (27u)
+#define INTC_ICDISR13_TINT28_SHIFT (28u)
+#define INTC_ICDISR13_TINT29_SHIFT (29u)
+#define INTC_ICDISR13_TINT30_SHIFT (30u)
+#define INTC_ICDISR13_TINT31_SHIFT (31u)
+
+#define INTC_ICDISR14_TINT32_SHIFT (0u)
+#define INTC_ICDISR14_TINT33_SHIFT (1u)
+#define INTC_ICDISR14_TINT34_SHIFT (2u)
+#define INTC_ICDISR14_TINT35_SHIFT (3u)
+#define INTC_ICDISR14_TINT36_SHIFT (4u)
+#define INTC_ICDISR14_TINT37_SHIFT (5u)
+#define INTC_ICDISR14_TINT38_SHIFT (6u)
+#define INTC_ICDISR14_TINT39_SHIFT (7u)
+#define INTC_ICDISR14_TINT40_SHIFT (8u)
+#define INTC_ICDISR14_TINT41_SHIFT (9u)
+#define INTC_ICDISR14_TINT42_SHIFT (10u)
+#define INTC_ICDISR14_TINT43_SHIFT (11u)
+#define INTC_ICDISR14_TINT44_SHIFT (12u)
+#define INTC_ICDISR14_TINT45_SHIFT (13u)
+#define INTC_ICDISR14_TINT46_SHIFT (14u)
+#define INTC_ICDISR14_TINT47_SHIFT (15u)
+#define INTC_ICDISR14_TINT48_SHIFT (16u)
+#define INTC_ICDISR14_TINT49_SHIFT (17u)
+#define INTC_ICDISR14_TINT50_SHIFT (18u)
+#define INTC_ICDISR14_TINT51_SHIFT (19u)
+#define INTC_ICDISR14_TINT52_SHIFT (20u)
+#define INTC_ICDISR14_TINT53_SHIFT (21u)
+#define INTC_ICDISR14_TINT54_SHIFT (22u)
+#define INTC_ICDISR14_TINT55_SHIFT (23u)
+#define INTC_ICDISR14_TINT56_SHIFT (24u)
+#define INTC_ICDISR14_TINT57_SHIFT (25u)
+#define INTC_ICDISR14_TINT58_SHIFT (26u)
+#define INTC_ICDISR14_TINT59_SHIFT (27u)
+#define INTC_ICDISR14_TINT60_SHIFT (28u)
+#define INTC_ICDISR14_TINT61_SHIFT (29u)
+#define INTC_ICDISR14_TINT62_SHIFT (30u)
+#define INTC_ICDISR14_TINT63_SHIFT (31u)
+
+#define INTC_ICDISR15_TINT64_SHIFT (0u)
+#define INTC_ICDISR15_TINT65_SHIFT (1u)
+#define INTC_ICDISR15_TINT66_SHIFT (2u)
+#define INTC_ICDISR15_TINT67_SHIFT (3u)
+#define INTC_ICDISR15_TINT68_SHIFT (4u)
+#define INTC_ICDISR15_TINT69_SHIFT (5u)
+#define INTC_ICDISR15_TINT70_SHIFT (6u)
+#define INTC_ICDISR15_TINT71_SHIFT (7u)
+#define INTC_ICDISR15_TINT72_SHIFT (8u)
+#define INTC_ICDISR15_TINT73_SHIFT (9u)
+#define INTC_ICDISR15_TINT74_SHIFT (10u)
+#define INTC_ICDISR15_TINT75_SHIFT (11u)
+#define INTC_ICDISR15_TINT76_SHIFT (12u)
+#define INTC_ICDISR15_TINT77_SHIFT (13u)
+#define INTC_ICDISR15_TINT78_SHIFT (14u)
+#define INTC_ICDISR15_TINT79_SHIFT (15u)
+#define INTC_ICDISR15_TINT80_SHIFT (16u)
+#define INTC_ICDISR15_TINT81_SHIFT (17u)
+#define INTC_ICDISR15_TINT82_SHIFT (18u)
+#define INTC_ICDISR15_TINT83_SHIFT (19u)
+#define INTC_ICDISR15_TINT84_SHIFT (20u)
+#define INTC_ICDISR15_TINT85_SHIFT (21u)
+#define INTC_ICDISR15_TINT86_SHIFT (22u)
+#define INTC_ICDISR15_TINT87_SHIFT (23u)
+#define INTC_ICDISR15_TINT88_SHIFT (24u)
+#define INTC_ICDISR15_TINT89_SHIFT (25u)
+#define INTC_ICDISR15_TINT90_SHIFT (26u)
+#define INTC_ICDISR15_TINT91_SHIFT (27u)
+#define INTC_ICDISR15_TINT92_SHIFT (28u)
+#define INTC_ICDISR15_TINT93_SHIFT (29u)
+#define INTC_ICDISR15_TINT94_SHIFT (30u)
+#define INTC_ICDISR15_TINT95_SHIFT (31u)
+
+#define INTC_ICDISR16_TINT96_SHIFT (0u)
+#define INTC_ICDISR16_TINT97_SHIFT (1u)
+#define INTC_ICDISR16_TINT98_SHIFT (2u)
+#define INTC_ICDISR16_TINT99_SHIFT (3u)
+#define INTC_ICDISR16_TINT100_SHIFT (4u)
+#define INTC_ICDISR16_TINT101_SHIFT (5u)
+#define INTC_ICDISR16_TINT102_SHIFT (6u)
+#define INTC_ICDISR16_TINT103_SHIFT (7u)
+#define INTC_ICDISR16_TINT104_SHIFT (8u)
+#define INTC_ICDISR16_TINT105_SHIFT (9u)
+#define INTC_ICDISR16_TINT106_SHIFT (10u)
+#define INTC_ICDISR16_TINT107_SHIFT (11u)
+#define INTC_ICDISR16_TINT108_SHIFT (12u)
+#define INTC_ICDISR16_TINT109_SHIFT (13u)
+#define INTC_ICDISR16_TINT110_SHIFT (14u)
+#define INTC_ICDISR16_TINT111_SHIFT (15u)
+#define INTC_ICDISR16_TINT112_SHIFT (16u)
+#define INTC_ICDISR16_TINT113_SHIFT (17u)
+#define INTC_ICDISR16_TINT114_SHIFT (18u)
+#define INTC_ICDISR16_TINT115_SHIFT (19u)
+#define INTC_ICDISR16_TINT116_SHIFT (20u)
+#define INTC_ICDISR16_TINT117_SHIFT (21u)
+#define INTC_ICDISR16_TINT118_SHIFT (22u)
+#define INTC_ICDISR16_TINT119_SHIFT (23u)
+#define INTC_ICDISR16_TINT120_SHIFT (24u)
+#define INTC_ICDISR16_TINT121_SHIFT (25u)
+#define INTC_ICDISR16_TINT122_SHIFT (26u)
+#define INTC_ICDISR16_TINT123_SHIFT (27u)
+#define INTC_ICDISR16_TINT124_SHIFT (28u)
+#define INTC_ICDISR16_TINT125_SHIFT (29u)
+#define INTC_ICDISR16_TINT126_SHIFT (30u)
+#define INTC_ICDISR16_TINT127_SHIFT (31u)
+
+#define INTC_ICDISR17_TINT128_SHIFT (0u)
+#define INTC_ICDISR17_TINT129_SHIFT (1u)
+#define INTC_ICDISR17_TINT130_SHIFT (2u)
+#define INTC_ICDISR17_TINT131_SHIFT (3u)
+#define INTC_ICDISR17_TINT132_SHIFT (4u)
+#define INTC_ICDISR17_TINT133_SHIFT (5u)
+#define INTC_ICDISR17_TINT134_SHIFT (6u)
+#define INTC_ICDISR17_TINT135_SHIFT (7u)
+#define INTC_ICDISR17_TINT136_SHIFT (8u)
+#define INTC_ICDISR17_TINT137_SHIFT (9u)
+#define INTC_ICDISR17_TINT138_SHIFT (10u)
+#define INTC_ICDISR17_TINT139_SHIFT (11u)
+#define INTC_ICDISR17_TINT140_SHIFT (12u)
+#define INTC_ICDISR17_TINT141_SHIFT (13u)
+#define INTC_ICDISR17_TINT142_SHIFT (14u)
+#define INTC_ICDISR17_TINT143_SHIFT (15u)
+#define INTC_ICDISR17_TINT144_SHIFT (16u)
+#define INTC_ICDISR17_TINT145_SHIFT (17u)
+#define INTC_ICDISR17_TINT146_SHIFT (18u)
+#define INTC_ICDISR17_TINT147_SHIFT (19u)
+#define INTC_ICDISR17_TINT148_SHIFT (20u)
+#define INTC_ICDISR17_TINT149_SHIFT (21u)
+#define INTC_ICDISR17_TINT150_SHIFT (22u)
+#define INTC_ICDISR17_TINT151_SHIFT (23u)
+#define INTC_ICDISR17_TINT152_SHIFT (24u)
+#define INTC_ICDISR17_TINT153_SHIFT (25u)
+#define INTC_ICDISR17_TINT154_SHIFT (26u)
+#define INTC_ICDISR17_TINT155_SHIFT (27u)
+#define INTC_ICDISR17_TINT156_SHIFT (28u)
+#define INTC_ICDISR17_TINT157_SHIFT (29u)
+#define INTC_ICDISR17_TINT158_SHIFT (30u)
+#define INTC_ICDISR17_TINT159_SHIFT (31u)
+
+#define INTC_ICDISR18_TINT160_SHIFT (0u)
+#define INTC_ICDISR18_TINT161_SHIFT (1u)
+#define INTC_ICDISR18_TINT162_SHIFT (2u)
+#define INTC_ICDISR18_TINT163_SHIFT (3u)
+#define INTC_ICDISR18_TINT164_SHIFT (4u)
+#define INTC_ICDISR18_TINT165_SHIFT (5u)
+#define INTC_ICDISR18_TINT166_SHIFT (6u)
+#define INTC_ICDISR18_TINT167_SHIFT (7u)
+#define INTC_ICDISR18_TINT168_SHIFT (8u)
+#define INTC_ICDISR18_TINT169_SHIFT (9u)
+#define INTC_ICDISR18_TINT170_SHIFT (10u)
+
+#define INTC_ICDISER0_SW0_SHIFT (0u)
+#define INTC_ICDISER0_SW1_SHIFT (1u)
+#define INTC_ICDISER0_SW2_SHIFT (2u)
+#define INTC_ICDISER0_SW3_SHIFT (3u)
+#define INTC_ICDISER0_SW4_SHIFT (4u)
+#define INTC_ICDISER0_SW5_SHIFT (5u)
+#define INTC_ICDISER0_SW6_SHIFT (6u)
+#define INTC_ICDISER0_SW7_SHIFT (7u)
+#define INTC_ICDISER0_SW8_SHIFT (8u)
+#define INTC_ICDISER0_SW9_SHIFT (9u)
+#define INTC_ICDISER0_SW10_SHIFT (10u)
+#define INTC_ICDISER0_SW11_SHIFT (11u)
+#define INTC_ICDISER0_SW12_SHIFT (12u)
+#define INTC_ICDISER0_SW13_SHIFT (13u)
+#define INTC_ICDISER0_SW14_SHIFT (14u)
+#define INTC_ICDISER0_SW15_SHIFT (15u)
+#define INTC_ICDISER0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDISER0_COMMRX0_SHIFT (17u)
+#define INTC_ICDISER0_COMMTX0_SHIFT (18u)
+#define INTC_ICDISER0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDISER1_IRQ0_SHIFT (0u)
+#define INTC_ICDISER1_IRQ1_SHIFT (1u)
+#define INTC_ICDISER1_IRQ2_SHIFT (2u)
+#define INTC_ICDISER1_IRQ3_SHIFT (3u)
+#define INTC_ICDISER1_IRQ4_SHIFT (4u)
+#define INTC_ICDISER1_IRQ5_SHIFT (5u)
+#define INTC_ICDISER1_IRQ6_SHIFT (6u)
+#define INTC_ICDISER1_IRQ7_SHIFT (7u)
+#define INTC_ICDISER1_PL310ERR_SHIFT (8u)
+#define INTC_ICDISER1_DMAINT0_SHIFT (9u)
+#define INTC_ICDISER1_DMAINT1_SHIFT (10u)
+#define INTC_ICDISER1_DMAINT2_SHIFT (11u)
+#define INTC_ICDISER1_DMAINT3_SHIFT (12u)
+#define INTC_ICDISER1_DMAINT4_SHIFT (13u)
+#define INTC_ICDISER1_DMAINT5_SHIFT (14u)
+#define INTC_ICDISER1_DMAINT6_SHIFT (15u)
+#define INTC_ICDISER1_DMAINT7_SHIFT (16u)
+#define INTC_ICDISER1_DMAINT8_SHIFT (17u)
+#define INTC_ICDISER1_DMAINT9_SHIFT (18u)
+#define INTC_ICDISER1_DMAINT10_SHIFT (19u)
+#define INTC_ICDISER1_DMAINT11_SHIFT (20u)
+#define INTC_ICDISER1_DMAINT12_SHIFT (21u)
+#define INTC_ICDISER1_DMAINT13_SHIFT (22u)
+#define INTC_ICDISER1_DMAINT14_SHIFT (23u)
+#define INTC_ICDISER1_DMAINT15_SHIFT (24u)
+#define INTC_ICDISER1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDISER2_USBI0_SHIFT (9u)
+#define INTC_ICDISER2_USBI1_SHIFT (10u)
+#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDISER2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDISER2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDISER2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDISER2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDISER2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDISER2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDISER3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDISER3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDISER3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDISER3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDISER3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDISER3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDISER3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDISER3_IMRDI_SHIFT (27u)
+#define INTC_ICDISER3_IMR2I0_SHIFT (28u)
+#define INTC_ICDISER3_IMR2I1_SHIFT (29u)
+#define INTC_ICDISER3_JEDI_SHIFT (30u)
+#define INTC_ICDISER3_JDTI_SHIFT (31u)
+
+#define INTC_ICDISER4_CMP0_SHIFT (0u)
+#define INTC_ICDISER4_CMP1_SHIFT (1u)
+#define INTC_ICDISER4_INT0_SHIFT (2u)
+#define INTC_ICDISER4_INT1_SHIFT (3u)
+#define INTC_ICDISER4_INT2_SHIFT (4u)
+#define INTC_ICDISER4_INT3_SHIFT (5u)
+#define INTC_ICDISER4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDISER4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDISER4_CMI_SHIFT (8u)
+#define INTC_ICDISER4_WTOUT_SHIFT (9u)
+#define INTC_ICDISER4_ITI_SHIFT (10u)
+#define INTC_ICDISER4_TGI0A_SHIFT (11u)
+#define INTC_ICDISER4_TGI0B_SHIFT (12u)
+#define INTC_ICDISER4_TGI0C_SHIFT (13u)
+#define INTC_ICDISER4_TGI0D_SHIFT (14u)
+#define INTC_ICDISER4_TGI0V_SHIFT (15u)
+#define INTC_ICDISER4_TGI0E_SHIFT (16u)
+#define INTC_ICDISER4_TGI0F_SHIFT (17u)
+#define INTC_ICDISER4_TGI1A_SHIFT (18u)
+#define INTC_ICDISER4_TGI1B_SHIFT (19u)
+#define INTC_ICDISER4_TGI1V_SHIFT (20u)
+#define INTC_ICDISER4_TGI1U_SHIFT (21u)
+#define INTC_ICDISER4_TGI2A_SHIFT (22u)
+#define INTC_ICDISER4_TGI2B_SHIFT (23u)
+#define INTC_ICDISER4_TGI2V_SHIFT (24u)
+#define INTC_ICDISER4_TGI2U_SHIFT (25u)
+#define INTC_ICDISER4_TGI3A_SHIFT (26u)
+#define INTC_ICDISER4_TGI3B_SHIFT (27u)
+#define INTC_ICDISER4_TGI3C_SHIFT (28u)
+#define INTC_ICDISER4_TGI3D_SHIFT (29u)
+#define INTC_ICDISER4_TGI3V_SHIFT (30u)
+#define INTC_ICDISER4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDISER5_TGI4B_SHIFT (0u)
+#define INTC_ICDISER5_TGI4C_SHIFT (1u)
+#define INTC_ICDISER5_TGI4D_SHIFT (2u)
+#define INTC_ICDISER5_TGI4V_SHIFT (3u)
+#define INTC_ICDISER5_CMI1_SHIFT (4u)
+#define INTC_ICDISER5_CMI2_SHIFT (5u)
+#define INTC_ICDISER5_SGDEI0_SHIFT (6u)
+#define INTC_ICDISER5_SGDEI1_SHIFT (7u)
+#define INTC_ICDISER5_SGDEI2_SHIFT (8u)
+#define INTC_ICDISER5_SGDEI3_SHIFT (9u)
+#define INTC_ICDISER5_ADI_SHIFT (10u)
+#define INTC_ICDISER5_LMTI_SHIFT (11u)
+#define INTC_ICDISER5_SSII0_SHIFT (12u)
+#define INTC_ICDISER5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDISER5_SSITXI0_SHIFT (14u)
+#define INTC_ICDISER5_SSII1_SHIFT (15u)
+#define INTC_ICDISER5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDISER5_SSITXI1_SHIFT (17u)
+#define INTC_ICDISER5_SSII2_SHIFT (18u)
+#define INTC_ICDISER5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDISER5_SSII3_SHIFT (20u)
+#define INTC_ICDISER5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDISER5_SSITXI3_SHIFT (22u)
+#define INTC_ICDISER5_SSII4_SHIFT (23u)
+#define INTC_ICDISER5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDISER5_SSII5_SHIFT (25u)
+#define INTC_ICDISER5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDISER5_SSITXI5_SHIFT (27u)
+#define INTC_ICDISER5_SPDIFI_SHIFT (28u)
+#define INTC_ICDISER5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDISER5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDISER5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDISER6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDISER6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDISER6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDISER6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDISER6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDISER6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDISER6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDISER6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDISER6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDISER6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDISER6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDISER6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDISER6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDISER6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDISER6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDISER6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDISER6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDISER6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDISER6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDISER6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDISER6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDISER6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDISER6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDISER6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDISER6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDISER6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDISER6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDISER6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDISER6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDISER6_BRI0_SHIFT (29u)
+#define INTC_ICDISER6_ERI0_SHIFT (30u)
+#define INTC_ICDISER6_RXI0_SHIFT (31u)
+
+#define INTC_ICDISER7_TXI0_SHIFT (0u)
+#define INTC_ICDISER7_BRI1_SHIFT (1u)
+#define INTC_ICDISER7_ERI1_SHIFT (2u)
+#define INTC_ICDISER7_RXI1_SHIFT (3u)
+#define INTC_ICDISER7_TXI1_SHIFT (4u)
+#define INTC_ICDISER7_BRI2_SHIFT (5u)
+#define INTC_ICDISER7_ERI2_SHIFT (6u)
+#define INTC_ICDISER7_RXI2_SHIFT (7u)
+#define INTC_ICDISER7_TXI2_SHIFT (8u)
+#define INTC_ICDISER7_BRI3_SHIFT (9u)
+#define INTC_ICDISER7_ERI3_SHIFT (10u)
+#define INTC_ICDISER7_RXI3_SHIFT (11u)
+#define INTC_ICDISER7_TXI3_SHIFT (12u)
+#define INTC_ICDISER7_BRI4_SHIFT (13u)
+#define INTC_ICDISER7_ERI4_SHIFT (14u)
+#define INTC_ICDISER7_RXI4_SHIFT (15u)
+#define INTC_ICDISER7_TXI4_SHIFT (16u)
+#define INTC_ICDISER7_BRI5_SHIFT (17u)
+#define INTC_ICDISER7_ERI5_SHIFT (18u)
+#define INTC_ICDISER7_RXI5_SHIFT (19u)
+#define INTC_ICDISER7_TXI5_SHIFT (20u)
+#define INTC_ICDISER7_BRI6_SHIFT (21u)
+#define INTC_ICDISER7_ERI6_SHIFT (22u)
+#define INTC_ICDISER7_RXI6_SHIFT (23u)
+#define INTC_ICDISER7_TXI6_SHIFT (24u)
+#define INTC_ICDISER7_BRI7_SHIFT (25u)
+#define INTC_ICDISER7_ERI7_SHIFT (26u)
+#define INTC_ICDISER7_RXI7_SHIFT (27u)
+#define INTC_ICDISER7_TXI7_SHIFT (28u)
+#define INTC_ICDISER7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDISER7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDISER7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDISER8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDISER8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDISER8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDISER8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDISER8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDISER8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDISER8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDISER8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDISER8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDISER8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDISER8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDISER8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDISER8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDISER8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDISER8_SPEI0_SHIFT (14u)
+#define INTC_ICDISER8_SPRI0_SHIFT (15u)
+#define INTC_ICDISER8_SPTI0_SHIFT (16u)
+#define INTC_ICDISER8_SPEI1_SHIFT (17u)
+#define INTC_ICDISER8_SPRI1_SHIFT (18u)
+#define INTC_ICDISER8_SPTI1_SHIFT (19u)
+#define INTC_ICDISER8_SPEI2_SHIFT (20u)
+#define INTC_ICDISER8_SPRI2_SHIFT (21u)
+#define INTC_ICDISER8_SPTI2_SHIFT (22u)
+#define INTC_ICDISER8_SPEI3_SHIFT (23u)
+#define INTC_ICDISER8_SPRI3_SHIFT (24u)
+#define INTC_ICDISER8_SPTI3_SHIFT (25u)
+#define INTC_ICDISER8_SPEI4_SHIFT (26u)
+#define INTC_ICDISER8_SPRI4_SHIFT (27u)
+#define INTC_ICDISER8_SPTI4_SHIFT (28u)
+#define INTC_ICDISER8_IEBBTD_SHIFT (29u)
+#define INTC_ICDISER8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDISER8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDISER9_IEBBTV_SHIFT (0u)
+#define INTC_ICDISER9_ISY_SHIFT (1u)
+#define INTC_ICDISER9_IERR_SHIFT (2u)
+#define INTC_ICDISER9_ITARG_SHIFT (3u)
+#define INTC_ICDISER9_ISEC_SHIFT (4u)
+#define INTC_ICDISER9_IBUF_SHIFT (5u)
+#define INTC_ICDISER9_IREADY_SHIFT (6u)
+#define INTC_ICDISER9_FLSTE_SHIFT (7u)
+#define INTC_ICDISER9_FLTENDI_SHIFT (8u)
+#define INTC_ICDISER9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDISER9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDISER9_MMC0_SHIFT (11u)
+#define INTC_ICDISER9_MMC1_SHIFT (12u)
+#define INTC_ICDISER9_MMC2_SHIFT (13u)
+#define INTC_ICDISER9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDISER9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDISER9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDISER9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDISER9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDISER9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDISER9_ARM_SHIFT (20u)
+#define INTC_ICDISER9_PRD_SHIFT (21u)
+#define INTC_ICDISER9_CUP_SHIFT (22u)
+#define INTC_ICDISER9_SCUAI0_SHIFT (23u)
+#define INTC_ICDISER9_SCUAI1_SHIFT (24u)
+#define INTC_ICDISER9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDISER9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDISER9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDISER9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDISER9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDISER9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDISER9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDISER10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDISER10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDISER10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDISER10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDISER10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDISER10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDISER10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDISER10_DRC0_SHIFT (7u)
+#define INTC_ICDISER10_DRC1_SHIFT (8u)
+#define INTC_ICDISER10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDISER10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDISER10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDISER10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDISER10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDISER10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDISER10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDISER10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDISER10_ERI0_SHIFT (27u)
+#define INTC_ICDISER10_RXI0_SHIFT (28u)
+#define INTC_ICDISER10_TXI0_SHIFT (29u)
+#define INTC_ICDISER10_TEI0_SHIFT (30u)
+#define INTC_ICDISER10_ERI1_SHIFT (31u)
+
+#define INTC_ICDISER11_RXI1_SHIFT (0u)
+#define INTC_ICDISER11_TXI1_SHIFT (1u)
+#define INTC_ICDISER11_TEI1_SHIFT (2u)
+#define INTC_ICDISER11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDISER11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDISER11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDISER11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDISER11_ETHERI_SHIFT (7u)
+#define INTC_ICDISER11_CEUI_SHIFT (12u)
+#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDISER12_PRRI_SHIFT (8u)
+#define INTC_ICDISER12_IFEI0_SHIFT (9u)
+#define INTC_ICDISER12_OFFI0_SHIFT (10u)
+#define INTC_ICDISER12_PFVEI0_SHIFT (11u)
+#define INTC_ICDISER12_IFEI1_SHIFT (12u)
+#define INTC_ICDISER12_OFFI1_SHIFT (13u)
+#define INTC_ICDISER12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDISER13_TINT0_SHIFT (0u)
+#define INTC_ICDISER13_TINT1_SHIFT (1u)
+#define INTC_ICDISER13_TINT2_SHIFT (2u)
+#define INTC_ICDISER13_TINT3_SHIFT (3u)
+#define INTC_ICDISER13_TINT4_SHIFT (4u)
+#define INTC_ICDISER13_TINT5_SHIFT (5u)
+#define INTC_ICDISER13_TINT6_SHIFT (6u)
+#define INTC_ICDISER13_TINT7_SHIFT (7u)
+#define INTC_ICDISER13_TINT8_SHIFT (8u)
+#define INTC_ICDISER13_TINT9_SHIFT (9u)
+#define INTC_ICDISER13_TINT10_SHIFT (10u)
+#define INTC_ICDISER13_TINT11_SHIFT (11u)
+#define INTC_ICDISER13_TINT12_SHIFT (12u)
+#define INTC_ICDISER13_TINT13_SHIFT (13u)
+#define INTC_ICDISER13_TINT14_SHIFT (14u)
+#define INTC_ICDISER13_TINT15_SHIFT (15u)
+#define INTC_ICDISER13_TINT16_SHIFT (16u)
+#define INTC_ICDISER13_TINT17_SHIFT (17u)
+#define INTC_ICDISER13_TINT18_SHIFT (18u)
+#define INTC_ICDISER13_TINT19_SHIFT (19u)
+#define INTC_ICDISER13_TINT20_SHIFT (20u)
+#define INTC_ICDISER13_TINT21_SHIFT (21u)
+#define INTC_ICDISER13_TINT22_SHIFT (22u)
+#define INTC_ICDISER13_TINT23_SHIFT (23u)
+#define INTC_ICDISER13_TINT24_SHIFT (24u)
+#define INTC_ICDISER13_TINT25_SHIFT (25u)
+#define INTC_ICDISER13_TINT26_SHIFT (26u)
+#define INTC_ICDISER13_TINT27_SHIFT (27u)
+#define INTC_ICDISER13_TINT28_SHIFT (28u)
+#define INTC_ICDISER13_TINT29_SHIFT (29u)
+#define INTC_ICDISER13_TINT30_SHIFT (30u)
+#define INTC_ICDISER13_TINT31_SHIFT (31u)
+
+#define INTC_ICDISER14_TINT32_SHIFT (0u)
+#define INTC_ICDISER14_TINT33_SHIFT (1u)
+#define INTC_ICDISER14_TINT34_SHIFT (2u)
+#define INTC_ICDISER14_TINT35_SHIFT (3u)
+#define INTC_ICDISER14_TINT36_SHIFT (4u)
+#define INTC_ICDISER14_TINT37_SHIFT (5u)
+#define INTC_ICDISER14_TINT38_SHIFT (6u)
+#define INTC_ICDISER14_TINT39_SHIFT (7u)
+#define INTC_ICDISER14_TINT40_SHIFT (8u)
+#define INTC_ICDISER14_TINT41_SHIFT (9u)
+#define INTC_ICDISER14_TINT42_SHIFT (10u)
+#define INTC_ICDISER14_TINT43_SHIFT (11u)
+#define INTC_ICDISER14_TINT44_SHIFT (12u)
+#define INTC_ICDISER14_TINT45_SHIFT (13u)
+#define INTC_ICDISER14_TINT46_SHIFT (14u)
+#define INTC_ICDISER14_TINT47_SHIFT (15u)
+#define INTC_ICDISER14_TINT48_SHIFT (16u)
+#define INTC_ICDISER14_TINT49_SHIFT (17u)
+#define INTC_ICDISER14_TINT50_SHIFT (18u)
+#define INTC_ICDISER14_TINT51_SHIFT (19u)
+#define INTC_ICDISER14_TINT52_SHIFT (20u)
+#define INTC_ICDISER14_TINT53_SHIFT (21u)
+#define INTC_ICDISER14_TINT54_SHIFT (22u)
+#define INTC_ICDISER14_TINT55_SHIFT (23u)
+#define INTC_ICDISER14_TINT56_SHIFT (24u)
+#define INTC_ICDISER14_TINT57_SHIFT (25u)
+#define INTC_ICDISER14_TINT58_SHIFT (26u)
+#define INTC_ICDISER14_TINT59_SHIFT (27u)
+#define INTC_ICDISER14_TINT60_SHIFT (28u)
+#define INTC_ICDISER14_TINT61_SHIFT (29u)
+#define INTC_ICDISER14_TINT62_SHIFT (30u)
+#define INTC_ICDISER14_TINT63_SHIFT (31u)
+
+#define INTC_ICDISER15_TINT64_SHIFT (0u)
+#define INTC_ICDISER15_TINT65_SHIFT (1u)
+#define INTC_ICDISER15_TINT66_SHIFT (2u)
+#define INTC_ICDISER15_TINT67_SHIFT (3u)
+#define INTC_ICDISER15_TINT68_SHIFT (4u)
+#define INTC_ICDISER15_TINT69_SHIFT (5u)
+#define INTC_ICDISER15_TINT70_SHIFT (6u)
+#define INTC_ICDISER15_TINT71_SHIFT (7u)
+#define INTC_ICDISER15_TINT72_SHIFT (8u)
+#define INTC_ICDISER15_TINT73_SHIFT (9u)
+#define INTC_ICDISER15_TINT74_SHIFT (10u)
+#define INTC_ICDISER15_TINT75_SHIFT (11u)
+#define INTC_ICDISER15_TINT76_SHIFT (12u)
+#define INTC_ICDISER15_TINT77_SHIFT (13u)
+#define INTC_ICDISER15_TINT78_SHIFT (14u)
+#define INTC_ICDISER15_TINT79_SHIFT (15u)
+#define INTC_ICDISER15_TINT80_SHIFT (16u)
+#define INTC_ICDISER15_TINT81_SHIFT (17u)
+#define INTC_ICDISER15_TINT82_SHIFT (18u)
+#define INTC_ICDISER15_TINT83_SHIFT (19u)
+#define INTC_ICDISER15_TINT84_SHIFT (20u)
+#define INTC_ICDISER15_TINT85_SHIFT (21u)
+#define INTC_ICDISER15_TINT86_SHIFT (22u)
+#define INTC_ICDISER15_TINT87_SHIFT (23u)
+#define INTC_ICDISER15_TINT88_SHIFT (24u)
+#define INTC_ICDISER15_TINT89_SHIFT (25u)
+#define INTC_ICDISER15_TINT90_SHIFT (26u)
+#define INTC_ICDISER15_TINT91_SHIFT (27u)
+#define INTC_ICDISER15_TINT92_SHIFT (28u)
+#define INTC_ICDISER15_TINT93_SHIFT (29u)
+#define INTC_ICDISER15_TINT94_SHIFT (30u)
+#define INTC_ICDISER15_TINT95_SHIFT (31u)
+
+#define INTC_ICDISER16_TINT96_SHIFT (0u)
+#define INTC_ICDISER16_TINT97_SHIFT (1u)
+#define INTC_ICDISER16_TINT98_SHIFT (2u)
+#define INTC_ICDISER16_TINT99_SHIFT (3u)
+#define INTC_ICDISER16_TINT100_SHIFT (4u)
+#define INTC_ICDISER16_TINT101_SHIFT (5u)
+#define INTC_ICDISER16_TINT102_SHIFT (6u)
+#define INTC_ICDISER16_TINT103_SHIFT (7u)
+#define INTC_ICDISER16_TINT104_SHIFT (8u)
+#define INTC_ICDISER16_TINT105_SHIFT (9u)
+#define INTC_ICDISER16_TINT106_SHIFT (10u)
+#define INTC_ICDISER16_TINT107_SHIFT (11u)
+#define INTC_ICDISER16_TINT108_SHIFT (12u)
+#define INTC_ICDISER16_TINT109_SHIFT (13u)
+#define INTC_ICDISER16_TINT110_SHIFT (14u)
+#define INTC_ICDISER16_TINT111_SHIFT (15u)
+#define INTC_ICDISER16_TINT112_SHIFT (16u)
+#define INTC_ICDISER16_TINT113_SHIFT (17u)
+#define INTC_ICDISER16_TINT114_SHIFT (18u)
+#define INTC_ICDISER16_TINT115_SHIFT (19u)
+#define INTC_ICDISER16_TINT116_SHIFT (20u)
+#define INTC_ICDISER16_TINT117_SHIFT (21u)
+#define INTC_ICDISER16_TINT118_SHIFT (22u)
+#define INTC_ICDISER16_TINT119_SHIFT (23u)
+#define INTC_ICDISER16_TINT120_SHIFT (24u)
+#define INTC_ICDISER16_TINT121_SHIFT (25u)
+#define INTC_ICDISER16_TINT122_SHIFT (26u)
+#define INTC_ICDISER16_TINT123_SHIFT (27u)
+#define INTC_ICDISER16_TINT124_SHIFT (28u)
+#define INTC_ICDISER16_TINT125_SHIFT (29u)
+#define INTC_ICDISER16_TINT126_SHIFT (30u)
+#define INTC_ICDISER16_TINT127_SHIFT (31u)
+
+#define INTC_ICDISER17_TINT128_SHIFT (0u)
+#define INTC_ICDISER17_TINT129_SHIFT (1u)
+#define INTC_ICDISER17_TINT130_SHIFT (2u)
+#define INTC_ICDISER17_TINT131_SHIFT (3u)
+#define INTC_ICDISER17_TINT132_SHIFT (4u)
+#define INTC_ICDISER17_TINT133_SHIFT (5u)
+#define INTC_ICDISER17_TINT134_SHIFT (6u)
+#define INTC_ICDISER17_TINT135_SHIFT (7u)
+#define INTC_ICDISER17_TINT136_SHIFT (8u)
+#define INTC_ICDISER17_TINT137_SHIFT (9u)
+#define INTC_ICDISER17_TINT138_SHIFT (10u)
+#define INTC_ICDISER17_TINT139_SHIFT (11u)
+#define INTC_ICDISER17_TINT140_SHIFT (12u)
+#define INTC_ICDISER17_TINT141_SHIFT (13u)
+#define INTC_ICDISER17_TINT142_SHIFT (14u)
+#define INTC_ICDISER17_TINT143_SHIFT (15u)
+#define INTC_ICDISER17_TINT144_SHIFT (16u)
+#define INTC_ICDISER17_TINT145_SHIFT (17u)
+#define INTC_ICDISER17_TINT146_SHIFT (18u)
+#define INTC_ICDISER17_TINT147_SHIFT (19u)
+#define INTC_ICDISER17_TINT148_SHIFT (20u)
+#define INTC_ICDISER17_TINT149_SHIFT (21u)
+#define INTC_ICDISER17_TINT150_SHIFT (22u)
+#define INTC_ICDISER17_TINT151_SHIFT (23u)
+#define INTC_ICDISER17_TINT152_SHIFT (24u)
+#define INTC_ICDISER17_TINT153_SHIFT (25u)
+#define INTC_ICDISER17_TINT154_SHIFT (26u)
+#define INTC_ICDISER17_TINT155_SHIFT (27u)
+#define INTC_ICDISER17_TINT156_SHIFT (28u)
+#define INTC_ICDISER17_TINT157_SHIFT (29u)
+#define INTC_ICDISER17_TINT158_SHIFT (30u)
+#define INTC_ICDISER17_TINT159_SHIFT (31u)
+
+#define INTC_ICDISER18_TINT160_SHIFT (0u)
+#define INTC_ICDISER18_TINT161_SHIFT (1u)
+#define INTC_ICDISER18_TINT162_SHIFT (2u)
+#define INTC_ICDISER18_TINT163_SHIFT (3u)
+#define INTC_ICDISER18_TINT164_SHIFT (4u)
+#define INTC_ICDISER18_TINT165_SHIFT (5u)
+#define INTC_ICDISER18_TINT166_SHIFT (6u)
+#define INTC_ICDISER18_TINT167_SHIFT (7u)
+#define INTC_ICDISER18_TINT168_SHIFT (8u)
+#define INTC_ICDISER18_TINT169_SHIFT (9u)
+#define INTC_ICDISER18_TINT170_SHIFT (10u)
+
+#define INTC_ICDICER0_SW0_SHIFT (0u)
+#define INTC_ICDICER0_SW1_SHIFT (1u)
+#define INTC_ICDICER0_SW2_SHIFT (2u)
+#define INTC_ICDICER0_SW3_SHIFT (3u)
+#define INTC_ICDICER0_SW4_SHIFT (4u)
+#define INTC_ICDICER0_SW5_SHIFT (5u)
+#define INTC_ICDICER0_SW6_SHIFT (6u)
+#define INTC_ICDICER0_SW7_SHIFT (7u)
+#define INTC_ICDICER0_SW8_SHIFT (8u)
+#define INTC_ICDICER0_SW9_SHIFT (9u)
+#define INTC_ICDICER0_SW10_SHIFT (10u)
+#define INTC_ICDICER0_SW11_SHIFT (11u)
+#define INTC_ICDICER0_SW12_SHIFT (12u)
+#define INTC_ICDICER0_SW13_SHIFT (13u)
+#define INTC_ICDICER0_SW14_SHIFT (14u)
+#define INTC_ICDICER0_SW15_SHIFT (15u)
+#define INTC_ICDICER0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDICER0_COMMRX0_SHIFT (17u)
+#define INTC_ICDICER0_COMMTX0_SHIFT (18u)
+#define INTC_ICDICER0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDICER1_IRQ0_SHIFT (0u)
+#define INTC_ICDICER1_IRQ1_SHIFT (1u)
+#define INTC_ICDICER1_IRQ2_SHIFT (2u)
+#define INTC_ICDICER1_IRQ3_SHIFT (3u)
+#define INTC_ICDICER1_IRQ4_SHIFT (4u)
+#define INTC_ICDICER1_IRQ5_SHIFT (5u)
+#define INTC_ICDICER1_IRQ6_SHIFT (6u)
+#define INTC_ICDICER1_IRQ7_SHIFT (7u)
+#define INTC_ICDICER1_PL310ERR_SHIFT (8u)
+#define INTC_ICDICER1_DMAINT0_SHIFT (9u)
+#define INTC_ICDICER1_DMAINT1_SHIFT (10u)
+#define INTC_ICDICER1_DMAINT2_SHIFT (11u)
+#define INTC_ICDICER1_DMAINT3_SHIFT (12u)
+#define INTC_ICDICER1_DMAINT4_SHIFT (13u)
+#define INTC_ICDICER1_DMAINT5_SHIFT (14u)
+#define INTC_ICDICER1_DMAINT6_SHIFT (15u)
+#define INTC_ICDICER1_DMAINT7_SHIFT (16u)
+#define INTC_ICDICER1_DMAINT8_SHIFT (17u)
+#define INTC_ICDICER1_DMAINT9_SHIFT (18u)
+#define INTC_ICDICER1_DMAINT10_SHIFT (19u)
+#define INTC_ICDICER1_DMAINT11_SHIFT (20u)
+#define INTC_ICDICER1_DMAINT12_SHIFT (21u)
+#define INTC_ICDICER1_DMAINT13_SHIFT (22u)
+#define INTC_ICDICER1_DMAINT14_SHIFT (23u)
+#define INTC_ICDICER1_DMAINT15_SHIFT (24u)
+#define INTC_ICDICER1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDICER2_USBI0_SHIFT (9u)
+#define INTC_ICDICER2_USBI1_SHIFT (10u)
+#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDICER2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDICER2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDICER2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDICER2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDICER2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDICER2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDICER3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDICER3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDICER3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDICER3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDICER3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDICER3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDICER3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDICER3_IMRDI_SHIFT (27u)
+#define INTC_ICDICER3_IMR2I0_SHIFT (28u)
+#define INTC_ICDICER3_IMR2I1_SHIFT (29u)
+#define INTC_ICDICER3_JEDI_SHIFT (30u)
+#define INTC_ICDICER3_JDTI_SHIFT (31u)
+
+#define INTC_ICDICER4_CMP0_SHIFT (0u)
+#define INTC_ICDICER4_CMP1_SHIFT (1u)
+#define INTC_ICDICER4_INT0_SHIFT (2u)
+#define INTC_ICDICER4_INT1_SHIFT (3u)
+#define INTC_ICDICER4_INT2_SHIFT (4u)
+#define INTC_ICDICER4_INT3_SHIFT (5u)
+#define INTC_ICDICER4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDICER4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDICER4_CMI_SHIFT (8u)
+#define INTC_ICDICER4_WTOUT_SHIFT (9u)
+#define INTC_ICDICER4_ITI_SHIFT (10u)
+#define INTC_ICDICER4_TGI0A_SHIFT (11u)
+#define INTC_ICDICER4_TGI0B_SHIFT (12u)
+#define INTC_ICDICER4_TGI0C_SHIFT (13u)
+#define INTC_ICDICER4_TGI0D_SHIFT (14u)
+#define INTC_ICDICER4_TGI0V_SHIFT (15u)
+#define INTC_ICDICER4_TGI0E_SHIFT (16u)
+#define INTC_ICDICER4_TGI0F_SHIFT (17u)
+#define INTC_ICDICER4_TGI1A_SHIFT (18u)
+#define INTC_ICDICER4_TGI1B_SHIFT (19u)
+#define INTC_ICDICER4_TGI1V_SHIFT (20u)
+#define INTC_ICDICER4_TGI1U_SHIFT (21u)
+#define INTC_ICDICER4_TGI2A_SHIFT (22u)
+#define INTC_ICDICER4_TGI2B_SHIFT (23u)
+#define INTC_ICDICER4_TGI2V_SHIFT (24u)
+#define INTC_ICDICER4_TGI2U_SHIFT (25u)
+#define INTC_ICDICER4_TGI3A_SHIFT (26u)
+#define INTC_ICDICER4_TGI3B_SHIFT (27u)
+#define INTC_ICDICER4_TGI3C_SHIFT (28u)
+#define INTC_ICDICER4_TGI3D_SHIFT (29u)
+#define INTC_ICDICER4_TGI3V_SHIFT (30u)
+#define INTC_ICDICER4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDICER5_TGI4B_SHIFT (0u)
+#define INTC_ICDICER5_TGI4C_SHIFT (1u)
+#define INTC_ICDICER5_TGI4D_SHIFT (2u)
+#define INTC_ICDICER5_TGI4V_SHIFT (3u)
+#define INTC_ICDICER5_CMI1_SHIFT (4u)
+#define INTC_ICDICER5_CMI2_SHIFT (5u)
+#define INTC_ICDICER5_SGDEI0_SHIFT (6u)
+#define INTC_ICDICER5_SGDEI1_SHIFT (7u)
+#define INTC_ICDICER5_SGDEI2_SHIFT (8u)
+#define INTC_ICDICER5_SGDEI3_SHIFT (9u)
+#define INTC_ICDICER5_ADI_SHIFT (10u)
+#define INTC_ICDICER5_LMTI_SHIFT (11u)
+#define INTC_ICDICER5_SSII0_SHIFT (12u)
+#define INTC_ICDICER5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDICER5_SSITXI0_SHIFT (14u)
+#define INTC_ICDICER5_SSII1_SHIFT (15u)
+#define INTC_ICDICER5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDICER5_SSITXI1_SHIFT (17u)
+#define INTC_ICDICER5_SSII2_SHIFT (18u)
+#define INTC_ICDICER5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDICER5_SSII3_SHIFT (20u)
+#define INTC_ICDICER5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDICER5_SSITXI3_SHIFT (22u)
+#define INTC_ICDICER5_SSII4_SHIFT (23u)
+#define INTC_ICDICER5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDICER5_SSII5_SHIFT (25u)
+#define INTC_ICDICER5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDICER5_SSITXI5_SHIFT (27u)
+#define INTC_ICDICER5_SPDIFI_SHIFT (28u)
+#define INTC_ICDICER5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDICER5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDICER5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDICER6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDICER6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDICER6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDICER6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDICER6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDICER6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDICER6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDICER6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDICER6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDICER6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDICER6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDICER6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDICER6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDICER6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDICER6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDICER6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDICER6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDICER6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDICER6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDICER6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDICER6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDICER6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDICER6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDICER6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDICER6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDICER6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDICER6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDICER6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDICER6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDICER6_BRI0_SHIFT (29u)
+#define INTC_ICDICER6_ERI0_SHIFT (30u)
+#define INTC_ICDICER6_RXI0_SHIFT (31u)
+
+#define INTC_ICDICER7_TXI0_SHIFT (0u)
+#define INTC_ICDICER7_BRI1_SHIFT (1u)
+#define INTC_ICDICER7_ERI1_SHIFT (2u)
+#define INTC_ICDICER7_RXI1_SHIFT (3u)
+#define INTC_ICDICER7_TXI1_SHIFT (4u)
+#define INTC_ICDICER7_BRI2_SHIFT (5u)
+#define INTC_ICDICER7_ERI2_SHIFT (6u)
+#define INTC_ICDICER7_RXI2_SHIFT (7u)
+#define INTC_ICDICER7_TXI2_SHIFT (8u)
+#define INTC_ICDICER7_BRI3_SHIFT (9u)
+#define INTC_ICDICER7_ERI3_SHIFT (10u)
+#define INTC_ICDICER7_RXI3_SHIFT (11u)
+#define INTC_ICDICER7_TXI3_SHIFT (12u)
+#define INTC_ICDICER7_BRI4_SHIFT (13u)
+#define INTC_ICDICER7_ERI4_SHIFT (14u)
+#define INTC_ICDICER7_RXI4_SHIFT (15u)
+#define INTC_ICDICER7_TXI4_SHIFT (16u)
+#define INTC_ICDICER7_BRI5_SHIFT (17u)
+#define INTC_ICDICER7_ERI5_SHIFT (18u)
+#define INTC_ICDICER7_RXI5_SHIFT (19u)
+#define INTC_ICDICER7_TXI5_SHIFT (20u)
+#define INTC_ICDICER7_BRI6_SHIFT (21u)
+#define INTC_ICDICER7_ERI6_SHIFT (22u)
+#define INTC_ICDICER7_RXI6_SHIFT (23u)
+#define INTC_ICDICER7_TXI6_SHIFT (24u)
+#define INTC_ICDICER7_BRI7_SHIFT (25u)
+#define INTC_ICDICER7_ERI7_SHIFT (26u)
+#define INTC_ICDICER7_RXI7_SHIFT (27u)
+#define INTC_ICDICER7_TXI7_SHIFT (28u)
+#define INTC_ICDICER7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDICER7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDICER7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDICER8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDICER8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDICER8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDICER8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDICER8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDICER8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDICER8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDICER8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDICER8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDICER8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDICER8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDICER8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDICER8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDICER8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDICER8_SPEI0_SHIFT (14u)
+#define INTC_ICDICER8_SPRI0_SHIFT (15u)
+#define INTC_ICDICER8_SPTI0_SHIFT (16u)
+#define INTC_ICDICER8_SPEI1_SHIFT (17u)
+#define INTC_ICDICER8_SPRI1_SHIFT (18u)
+#define INTC_ICDICER8_SPTI1_SHIFT (19u)
+#define INTC_ICDICER8_SPEI2_SHIFT (20u)
+#define INTC_ICDICER8_SPRI2_SHIFT (21u)
+#define INTC_ICDICER8_SPTI2_SHIFT (22u)
+#define INTC_ICDICER8_SPEI3_SHIFT (23u)
+#define INTC_ICDICER8_SPRI3_SHIFT (24u)
+#define INTC_ICDICER8_SPTI3_SHIFT (25u)
+#define INTC_ICDICER8_SPEI4_SHIFT (26u)
+#define INTC_ICDICER8_SPRI4_SHIFT (27u)
+#define INTC_ICDICER8_SPTI4_SHIFT (28u)
+#define INTC_ICDICER8_IEBBTD_SHIFT (29u)
+#define INTC_ICDICER8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDICER8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDICER9_IEBBTV_SHIFT (0u)
+#define INTC_ICDICER9_ISY_SHIFT (1u)
+#define INTC_ICDICER9_IERR_SHIFT (2u)
+#define INTC_ICDICER9_ITARG_SHIFT (3u)
+#define INTC_ICDICER9_ISEC_SHIFT (4u)
+#define INTC_ICDICER9_IBUF_SHIFT (5u)
+#define INTC_ICDICER9_IREADY_SHIFT (6u)
+#define INTC_ICDICER9_FLSTE_SHIFT (7u)
+#define INTC_ICDICER9_FLTENDI_SHIFT (8u)
+#define INTC_ICDICER9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDICER9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDICER9_MMC0_SHIFT (11u)
+#define INTC_ICDICER9_MMC1_SHIFT (12u)
+#define INTC_ICDICER9_MMC2_SHIFT (13u)
+#define INTC_ICDICER9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDICER9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDICER9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDICER9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDICER9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDICER9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDICER9_ARM_SHIFT (20u)
+#define INTC_ICDICER9_PRD_SHIFT (21u)
+#define INTC_ICDICER9_CUP_SHIFT (22u)
+#define INTC_ICDICER9_SCUAI0_SHIFT (23u)
+#define INTC_ICDICER9_SCUAI1_SHIFT (24u)
+#define INTC_ICDICER9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDICER9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDICER9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDICER9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDICER9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDICER9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDICER9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDICER10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDICER10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDICER10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDICER10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDICER10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDICER10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDICER10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDICER10_DRC0_SHIFT (7u)
+#define INTC_ICDICER10_DRC1_SHIFT (8u)
+#define INTC_ICDICER10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDICER10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDICER10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDICER10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDICER10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDICER10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDICER10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDICER10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDICER10_ERI0_SHIFT (27u)
+#define INTC_ICDICER10_RXI0_SHIFT (28u)
+#define INTC_ICDICER10_TXI0_SHIFT (29u)
+#define INTC_ICDICER10_TEI0_SHIFT (30u)
+#define INTC_ICDICER10_ERI1_SHIFT (31u)
+
+#define INTC_ICDICER11_RXI1_SHIFT (0u)
+#define INTC_ICDICER11_TXI1_SHIFT (1u)
+#define INTC_ICDICER11_TEI1_SHIFT (2u)
+#define INTC_ICDICER11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDICER11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDICER11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDICER11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDICER11_ETHERI_SHIFT (7u)
+#define INTC_ICDICER11_CEUI_SHIFT (12u)
+#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDICER12_PRRI_SHIFT (8u)
+#define INTC_ICDICER12_IFEI0_SHIFT (9u)
+#define INTC_ICDICER12_OFFI0_SHIFT (10u)
+#define INTC_ICDICER12_PFVEI0_SHIFT (11u)
+#define INTC_ICDICER12_IFEI1_SHIFT (12u)
+#define INTC_ICDICER12_OFFI1_SHIFT (13u)
+#define INTC_ICDICER12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDICER13_TINT0_SHIFT (0u)
+#define INTC_ICDICER13_TINT1_SHIFT (1u)
+#define INTC_ICDICER13_TINT2_SHIFT (2u)
+#define INTC_ICDICER13_TINT3_SHIFT (3u)
+#define INTC_ICDICER13_TINT4_SHIFT (4u)
+#define INTC_ICDICER13_TINT5_SHIFT (5u)
+#define INTC_ICDICER13_TINT6_SHIFT (6u)
+#define INTC_ICDICER13_TINT7_SHIFT (7u)
+#define INTC_ICDICER13_TINT8_SHIFT (8u)
+#define INTC_ICDICER13_TINT9_SHIFT (9u)
+#define INTC_ICDICER13_TINT10_SHIFT (10u)
+#define INTC_ICDICER13_TINT11_SHIFT (11u)
+#define INTC_ICDICER13_TINT12_SHIFT (12u)
+#define INTC_ICDICER13_TINT13_SHIFT (13u)
+#define INTC_ICDICER13_TINT14_SHIFT (14u)
+#define INTC_ICDICER13_TINT15_SHIFT (15u)
+#define INTC_ICDICER13_TINT16_SHIFT (16u)
+#define INTC_ICDICER13_TINT17_SHIFT (17u)
+#define INTC_ICDICER13_TINT18_SHIFT (18u)
+#define INTC_ICDICER13_TINT19_SHIFT (19u)
+#define INTC_ICDICER13_TINT20_SHIFT (20u)
+#define INTC_ICDICER13_TINT21_SHIFT (21u)
+#define INTC_ICDICER13_TINT22_SHIFT (22u)
+#define INTC_ICDICER13_TINT23_SHIFT (23u)
+#define INTC_ICDICER13_TINT24_SHIFT (24u)
+#define INTC_ICDICER13_TINT25_SHIFT (25u)
+#define INTC_ICDICER13_TINT26_SHIFT (26u)
+#define INTC_ICDICER13_TINT27_SHIFT (27u)
+#define INTC_ICDICER13_TINT28_SHIFT (28u)
+#define INTC_ICDICER13_TINT29_SHIFT (29u)
+#define INTC_ICDICER13_TINT30_SHIFT (30u)
+#define INTC_ICDICER13_TINT31_SHIFT (31u)
+
+#define INTC_ICDICER14_TINT32_SHIFT (0u)
+#define INTC_ICDICER14_TINT33_SHIFT (1u)
+#define INTC_ICDICER14_TINT34_SHIFT (2u)
+#define INTC_ICDICER14_TINT35_SHIFT (3u)
+#define INTC_ICDICER14_TINT36_SHIFT (4u)
+#define INTC_ICDICER14_TINT37_SHIFT (5u)
+#define INTC_ICDICER14_TINT38_SHIFT (6u)
+#define INTC_ICDICER14_TINT39_SHIFT (7u)
+#define INTC_ICDICER14_TINT40_SHIFT (8u)
+#define INTC_ICDICER14_TINT41_SHIFT (9u)
+#define INTC_ICDICER14_TINT42_SHIFT (10u)
+#define INTC_ICDICER14_TINT43_SHIFT (11u)
+#define INTC_ICDICER14_TINT44_SHIFT (12u)
+#define INTC_ICDICER14_TINT45_SHIFT (13u)
+#define INTC_ICDICER14_TINT46_SHIFT (14u)
+#define INTC_ICDICER14_TINT47_SHIFT (15u)
+#define INTC_ICDICER14_TINT48_SHIFT (16u)
+#define INTC_ICDICER14_TINT49_SHIFT (17u)
+#define INTC_ICDICER14_TINT50_SHIFT (18u)
+#define INTC_ICDICER14_TINT51_SHIFT (19u)
+#define INTC_ICDICER14_TINT52_SHIFT (20u)
+#define INTC_ICDICER14_TINT53_SHIFT (21u)
+#define INTC_ICDICER14_TINT54_SHIFT (22u)
+#define INTC_ICDICER14_TINT55_SHIFT (23u)
+#define INTC_ICDICER14_TINT56_SHIFT (24u)
+#define INTC_ICDICER14_TINT57_SHIFT (25u)
+#define INTC_ICDICER14_TINT58_SHIFT (26u)
+#define INTC_ICDICER14_TINT59_SHIFT (27u)
+#define INTC_ICDICER14_TINT60_SHIFT (28u)
+#define INTC_ICDICER14_TINT61_SHIFT (29u)
+#define INTC_ICDICER14_TINT62_SHIFT (30u)
+#define INTC_ICDICER14_TINT63_SHIFT (31u)
+
+#define INTC_ICDICER15_TINT64_SHIFT (0u)
+#define INTC_ICDICER15_TINT65_SHIFT (1u)
+#define INTC_ICDICER15_TINT66_SHIFT (2u)
+#define INTC_ICDICER15_TINT67_SHIFT (3u)
+#define INTC_ICDICER15_TINT68_SHIFT (4u)
+#define INTC_ICDICER15_TINT69_SHIFT (5u)
+#define INTC_ICDICER15_TINT70_SHIFT (6u)
+#define INTC_ICDICER15_TINT71_SHIFT (7u)
+#define INTC_ICDICER15_TINT72_SHIFT (8u)
+#define INTC_ICDICER15_TINT73_SHIFT (9u)
+#define INTC_ICDICER15_TINT74_SHIFT (10u)
+#define INTC_ICDICER15_TINT75_SHIFT (11u)
+#define INTC_ICDICER15_TINT76_SHIFT (12u)
+#define INTC_ICDICER15_TINT77_SHIFT (13u)
+#define INTC_ICDICER15_TINT78_SHIFT (14u)
+#define INTC_ICDICER15_TINT79_SHIFT (15u)
+#define INTC_ICDICER15_TINT80_SHIFT (16u)
+#define INTC_ICDICER15_TINT81_SHIFT (17u)
+#define INTC_ICDICER15_TINT82_SHIFT (18u)
+#define INTC_ICDICER15_TINT83_SHIFT (19u)
+#define INTC_ICDICER15_TINT84_SHIFT (20u)
+#define INTC_ICDICER15_TINT85_SHIFT (21u)
+#define INTC_ICDICER15_TINT86_SHIFT (22u)
+#define INTC_ICDICER15_TINT87_SHIFT (23u)
+#define INTC_ICDICER15_TINT88_SHIFT (24u)
+#define INTC_ICDICER15_TINT89_SHIFT (25u)
+#define INTC_ICDICER15_TINT90_SHIFT (26u)
+#define INTC_ICDICER15_TINT91_SHIFT (27u)
+#define INTC_ICDICER15_TINT92_SHIFT (28u)
+#define INTC_ICDICER15_TINT93_SHIFT (29u)
+#define INTC_ICDICER15_TINT94_SHIFT (30u)
+#define INTC_ICDICER15_TINT95_SHIFT (31u)
+
+#define INTC_ICDICER16_TINT96_SHIFT (0u)
+#define INTC_ICDICER16_TINT97_SHIFT (1u)
+#define INTC_ICDICER16_TINT98_SHIFT (2u)
+#define INTC_ICDICER16_TINT99_SHIFT (3u)
+#define INTC_ICDICER16_TINT100_SHIFT (4u)
+#define INTC_ICDICER16_TINT101_SHIFT (5u)
+#define INTC_ICDICER16_TINT102_SHIFT (6u)
+#define INTC_ICDICER16_TINT103_SHIFT (7u)
+#define INTC_ICDICER16_TINT104_SHIFT (8u)
+#define INTC_ICDICER16_TINT105_SHIFT (9u)
+#define INTC_ICDICER16_TINT106_SHIFT (10u)
+#define INTC_ICDICER16_TINT107_SHIFT (11u)
+#define INTC_ICDICER16_TINT108_SHIFT (12u)
+#define INTC_ICDICER16_TINT109_SHIFT (13u)
+#define INTC_ICDICER16_TINT110_SHIFT (14u)
+#define INTC_ICDICER16_TINT111_SHIFT (15u)
+#define INTC_ICDICER16_TINT112_SHIFT (16u)
+#define INTC_ICDICER16_TINT113_SHIFT (17u)
+#define INTC_ICDICER16_TINT114_SHIFT (18u)
+#define INTC_ICDICER16_TINT115_SHIFT (19u)
+#define INTC_ICDICER16_TINT116_SHIFT (20u)
+#define INTC_ICDICER16_TINT117_SHIFT (21u)
+#define INTC_ICDICER16_TINT118_SHIFT (22u)
+#define INTC_ICDICER16_TINT119_SHIFT (23u)
+#define INTC_ICDICER16_TINT120_SHIFT (24u)
+#define INTC_ICDICER16_TINT121_SHIFT (25u)
+#define INTC_ICDICER16_TINT122_SHIFT (26u)
+#define INTC_ICDICER16_TINT123_SHIFT (27u)
+#define INTC_ICDICER16_TINT124_SHIFT (28u)
+#define INTC_ICDICER16_TINT125_SHIFT (29u)
+#define INTC_ICDICER16_TINT126_SHIFT (30u)
+#define INTC_ICDICER16_TINT127_SHIFT (31u)
+
+#define INTC_ICDICER17_TINT128_SHIFT (0u)
+#define INTC_ICDICER17_TINT129_SHIFT (1u)
+#define INTC_ICDICER17_TINT130_SHIFT (2u)
+#define INTC_ICDICER17_TINT131_SHIFT (3u)
+#define INTC_ICDICER17_TINT132_SHIFT (4u)
+#define INTC_ICDICER17_TINT133_SHIFT (5u)
+#define INTC_ICDICER17_TINT134_SHIFT (6u)
+#define INTC_ICDICER17_TINT135_SHIFT (7u)
+#define INTC_ICDICER17_TINT136_SHIFT (8u)
+#define INTC_ICDICER17_TINT137_SHIFT (9u)
+#define INTC_ICDICER17_TINT138_SHIFT (10u)
+#define INTC_ICDICER17_TINT139_SHIFT (11u)
+#define INTC_ICDICER17_TINT140_SHIFT (12u)
+#define INTC_ICDICER17_TINT141_SHIFT (13u)
+#define INTC_ICDICER17_TINT142_SHIFT (14u)
+#define INTC_ICDICER17_TINT143_SHIFT (15u)
+#define INTC_ICDICER17_TINT144_SHIFT (16u)
+#define INTC_ICDICER17_TINT145_SHIFT (17u)
+#define INTC_ICDICER17_TINT146_SHIFT (18u)
+#define INTC_ICDICER17_TINT147_SHIFT (19u)
+#define INTC_ICDICER17_TINT148_SHIFT (20u)
+#define INTC_ICDICER17_TINT149_SHIFT (21u)
+#define INTC_ICDICER17_TINT150_SHIFT (22u)
+#define INTC_ICDICER17_TINT151_SHIFT (23u)
+#define INTC_ICDICER17_TINT152_SHIFT (24u)
+#define INTC_ICDICER17_TINT153_SHIFT (25u)
+#define INTC_ICDICER17_TINT154_SHIFT (26u)
+#define INTC_ICDICER17_TINT155_SHIFT (27u)
+#define INTC_ICDICER17_TINT156_SHIFT (28u)
+#define INTC_ICDICER17_TINT157_SHIFT (29u)
+#define INTC_ICDICER17_TINT158_SHIFT (30u)
+#define INTC_ICDICER17_TINT159_SHIFT (31u)
+
+#define INTC_ICDICER18_TINT160_SHIFT (0u)
+#define INTC_ICDICER18_TINT161_SHIFT (1u)
+#define INTC_ICDICER18_TINT162_SHIFT (2u)
+#define INTC_ICDICER18_TINT163_SHIFT (3u)
+#define INTC_ICDICER18_TINT164_SHIFT (4u)
+#define INTC_ICDICER18_TINT165_SHIFT (5u)
+#define INTC_ICDICER18_TINT166_SHIFT (6u)
+#define INTC_ICDICER18_TINT167_SHIFT (7u)
+#define INTC_ICDICER18_TINT168_SHIFT (8u)
+#define INTC_ICDICER18_TINT169_SHIFT (9u)
+#define INTC_ICDICER18_TINT170_SHIFT (10u)
+
+#define INTC_ICDISPR0_SW0_SHIFT (0u)
+#define INTC_ICDISPR0_SW1_SHIFT (1u)
+#define INTC_ICDISPR0_SW2_SHIFT (2u)
+#define INTC_ICDISPR0_SW3_SHIFT (3u)
+#define INTC_ICDISPR0_SW4_SHIFT (4u)
+#define INTC_ICDISPR0_SW5_SHIFT (5u)
+#define INTC_ICDISPR0_SW6_SHIFT (6u)
+#define INTC_ICDISPR0_SW7_SHIFT (7u)
+#define INTC_ICDISPR0_SW8_SHIFT (8u)
+#define INTC_ICDISPR0_SW9_SHIFT (9u)
+#define INTC_ICDISPR0_SW10_SHIFT (10u)
+#define INTC_ICDISPR0_SW11_SHIFT (11u)
+#define INTC_ICDISPR0_SW12_SHIFT (12u)
+#define INTC_ICDISPR0_SW13_SHIFT (13u)
+#define INTC_ICDISPR0_SW14_SHIFT (14u)
+#define INTC_ICDISPR0_SW15_SHIFT (15u)
+#define INTC_ICDISPR0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDISPR0_COMMRX0_SHIFT (17u)
+#define INTC_ICDISPR0_COMMTX0_SHIFT (18u)
+#define INTC_ICDISPR0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDISPR1_IRQ0_SHIFT (0u)
+#define INTC_ICDISPR1_IRQ1_SHIFT (1u)
+#define INTC_ICDISPR1_IRQ2_SHIFT (2u)
+#define INTC_ICDISPR1_IRQ3_SHIFT (3u)
+#define INTC_ICDISPR1_IRQ4_SHIFT (4u)
+#define INTC_ICDISPR1_IRQ5_SHIFT (5u)
+#define INTC_ICDISPR1_IRQ6_SHIFT (6u)
+#define INTC_ICDISPR1_IRQ7_SHIFT (7u)
+#define INTC_ICDISPR1_PL310ERR_SHIFT (8u)
+#define INTC_ICDISPR1_DMAINT0_SHIFT (9u)
+#define INTC_ICDISPR1_DMAINT1_SHIFT (10u)
+#define INTC_ICDISPR1_DMAINT2_SHIFT (11u)
+#define INTC_ICDISPR1_DMAINT3_SHIFT (12u)
+#define INTC_ICDISPR1_DMAINT4_SHIFT (13u)
+#define INTC_ICDISPR1_DMAINT5_SHIFT (14u)
+#define INTC_ICDISPR1_DMAINT6_SHIFT (15u)
+#define INTC_ICDISPR1_DMAINT7_SHIFT (16u)
+#define INTC_ICDISPR1_DMAINT8_SHIFT (17u)
+#define INTC_ICDISPR1_DMAINT9_SHIFT (18u)
+#define INTC_ICDISPR1_DMAINT10_SHIFT (19u)
+#define INTC_ICDISPR1_DMAINT11_SHIFT (20u)
+#define INTC_ICDISPR1_DMAINT12_SHIFT (21u)
+#define INTC_ICDISPR1_DMAINT13_SHIFT (22u)
+#define INTC_ICDISPR1_DMAINT14_SHIFT (23u)
+#define INTC_ICDISPR1_DMAINT15_SHIFT (24u)
+#define INTC_ICDISPR1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDISPR2_USBI0_SHIFT (9u)
+#define INTC_ICDISPR2_USBI1_SHIFT (10u)
+#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDISPR2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDISPR2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDISPR2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDISPR2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDISPR2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDISPR3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDISPR3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDISPR3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDISPR3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDISPR3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDISPR3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDISPR3_IMRDI_SHIFT (27u)
+#define INTC_ICDISPR3_IMR2I0_SHIFT (28u)
+#define INTC_ICDISPR3_IMR2I1_SHIFT (29u)
+#define INTC_ICDISPR3_JEDI_SHIFT (30u)
+#define INTC_ICDISPR3_JDTI_SHIFT (31u)
+
+#define INTC_ICDISPR4_CMP0_SHIFT (0u)
+#define INTC_ICDISPR4_CMP1_SHIFT (1u)
+#define INTC_ICDISPR4_INT0_SHIFT (2u)
+#define INTC_ICDISPR4_INT1_SHIFT (3u)
+#define INTC_ICDISPR4_INT2_SHIFT (4u)
+#define INTC_ICDISPR4_INT3_SHIFT (5u)
+#define INTC_ICDISPR4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDISPR4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDISPR4_CMI_SHIFT (8u)
+#define INTC_ICDISPR4_WTOUT_SHIFT (9u)
+#define INTC_ICDISPR4_ITI_SHIFT (10u)
+#define INTC_ICDISPR4_TGI0A_SHIFT (11u)
+#define INTC_ICDISPR4_TGI0B_SHIFT (12u)
+#define INTC_ICDISPR4_TGI0C_SHIFT (13u)
+#define INTC_ICDISPR4_TGI0D_SHIFT (14u)
+#define INTC_ICDISPR4_TGI0V_SHIFT (15u)
+#define INTC_ICDISPR4_TGI0E_SHIFT (16u)
+#define INTC_ICDISPR4_TGI0F_SHIFT (17u)
+#define INTC_ICDISPR4_TGI1A_SHIFT (18u)
+#define INTC_ICDISPR4_TGI1B_SHIFT (19u)
+#define INTC_ICDISPR4_TGI1V_SHIFT (20u)
+#define INTC_ICDISPR4_TGI1U_SHIFT (21u)
+#define INTC_ICDISPR4_TGI2A_SHIFT (22u)
+#define INTC_ICDISPR4_TGI2B_SHIFT (23u)
+#define INTC_ICDISPR4_TGI2V_SHIFT (24u)
+#define INTC_ICDISPR4_TGI2U_SHIFT (25u)
+#define INTC_ICDISPR4_TGI3A_SHIFT (26u)
+#define INTC_ICDISPR4_TGI3B_SHIFT (27u)
+#define INTC_ICDISPR4_TGI3C_SHIFT (28u)
+#define INTC_ICDISPR4_TGI3D_SHIFT (29u)
+#define INTC_ICDISPR4_TGI3V_SHIFT (30u)
+#define INTC_ICDISPR4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDISPR5_TGI4B_SHIFT (0u)
+#define INTC_ICDISPR5_TGI4C_SHIFT (1u)
+#define INTC_ICDISPR5_TGI4D_SHIFT (2u)
+#define INTC_ICDISPR5_TGI4V_SHIFT (3u)
+#define INTC_ICDISPR5_CMI1_SHIFT (4u)
+#define INTC_ICDISPR5_CMI2_SHIFT (5u)
+#define INTC_ICDISPR5_SGDEI0_SHIFT (6u)
+#define INTC_ICDISPR5_SGDEI1_SHIFT (7u)
+#define INTC_ICDISPR5_SGDEI2_SHIFT (8u)
+#define INTC_ICDISPR5_SGDEI3_SHIFT (9u)
+#define INTC_ICDISPR5_ADI_SHIFT (10u)
+#define INTC_ICDISPR5_LMTI_SHIFT (11u)
+#define INTC_ICDISPR5_SSII0_SHIFT (12u)
+#define INTC_ICDISPR5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDISPR5_SSITXI0_SHIFT (14u)
+#define INTC_ICDISPR5_SSII1_SHIFT (15u)
+#define INTC_ICDISPR5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDISPR5_SSITXI1_SHIFT (17u)
+#define INTC_ICDISPR5_SSII2_SHIFT (18u)
+#define INTC_ICDISPR5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDISPR5_SSII3_SHIFT (20u)
+#define INTC_ICDISPR5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDISPR5_SSITXI3_SHIFT (22u)
+#define INTC_ICDISPR5_SSII4_SHIFT (23u)
+#define INTC_ICDISPR5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDISPR5_SSII5_SHIFT (25u)
+#define INTC_ICDISPR5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDISPR5_SSITXI5_SHIFT (27u)
+#define INTC_ICDISPR5_SPDIFI_SHIFT (28u)
+#define INTC_ICDISPR5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDISPR5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDISPR5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDISPR6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDISPR6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDISPR6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDISPR6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDISPR6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDISPR6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDISPR6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDISPR6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDISPR6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDISPR6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDISPR6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDISPR6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDISPR6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDISPR6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDISPR6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDISPR6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDISPR6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDISPR6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDISPR6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDISPR6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDISPR6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDISPR6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDISPR6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDISPR6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDISPR6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDISPR6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDISPR6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDISPR6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDISPR6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDISPR6_BRI0_SHIFT (29u)
+#define INTC_ICDISPR6_ERI0_SHIFT (30u)
+#define INTC_ICDISPR6_RXI0_SHIFT (31u)
+
+#define INTC_ICDISPR7_TXI0_SHIFT (0u)
+#define INTC_ICDISPR7_BRI1_SHIFT (1u)
+#define INTC_ICDISPR7_ERI1_SHIFT (2u)
+#define INTC_ICDISPR7_RXI1_SHIFT (3u)
+#define INTC_ICDISPR7_TXI1_SHIFT (4u)
+#define INTC_ICDISPR7_BRI2_SHIFT (5u)
+#define INTC_ICDISPR7_ERI2_SHIFT (6u)
+#define INTC_ICDISPR7_RXI2_SHIFT (7u)
+#define INTC_ICDISPR7_TXI2_SHIFT (8u)
+#define INTC_ICDISPR7_BRI3_SHIFT (9u)
+#define INTC_ICDISPR7_ERI3_SHIFT (10u)
+#define INTC_ICDISPR7_RXI3_SHIFT (11u)
+#define INTC_ICDISPR7_TXI3_SHIFT (12u)
+#define INTC_ICDISPR7_BRI4_SHIFT (13u)
+#define INTC_ICDISPR7_ERI4_SHIFT (14u)
+#define INTC_ICDISPR7_RXI4_SHIFT (15u)
+#define INTC_ICDISPR7_TXI4_SHIFT (16u)
+#define INTC_ICDISPR7_BRI5_SHIFT (17u)
+#define INTC_ICDISPR7_ERI5_SHIFT (18u)
+#define INTC_ICDISPR7_RXI5_SHIFT (19u)
+#define INTC_ICDISPR7_TXI5_SHIFT (20u)
+#define INTC_ICDISPR7_BRI6_SHIFT (21u)
+#define INTC_ICDISPR7_ERI6_SHIFT (22u)
+#define INTC_ICDISPR7_RXI6_SHIFT (23u)
+#define INTC_ICDISPR7_TXI6_SHIFT (24u)
+#define INTC_ICDISPR7_BRI7_SHIFT (25u)
+#define INTC_ICDISPR7_ERI7_SHIFT (26u)
+#define INTC_ICDISPR7_RXI7_SHIFT (27u)
+#define INTC_ICDISPR7_TXI7_SHIFT (28u)
+#define INTC_ICDISPR7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDISPR7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDISPR7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDISPR8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDISPR8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDISPR8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDISPR8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDISPR8_SPEI0_SHIFT (14u)
+#define INTC_ICDISPR8_SPRI0_SHIFT (15u)
+#define INTC_ICDISPR8_SPTI0_SHIFT (16u)
+#define INTC_ICDISPR8_SPEI1_SHIFT (17u)
+#define INTC_ICDISPR8_SPRI1_SHIFT (18u)
+#define INTC_ICDISPR8_SPTI1_SHIFT (19u)
+#define INTC_ICDISPR8_SPEI2_SHIFT (20u)
+#define INTC_ICDISPR8_SPRI2_SHIFT (21u)
+#define INTC_ICDISPR8_SPTI2_SHIFT (22u)
+#define INTC_ICDISPR8_SPEI3_SHIFT (23u)
+#define INTC_ICDISPR8_SPRI3_SHIFT (24u)
+#define INTC_ICDISPR8_SPTI3_SHIFT (25u)
+#define INTC_ICDISPR8_SPEI4_SHIFT (26u)
+#define INTC_ICDISPR8_SPRI4_SHIFT (27u)
+#define INTC_ICDISPR8_SPTI4_SHIFT (28u)
+#define INTC_ICDISPR8_IEBBTD_SHIFT (29u)
+#define INTC_ICDISPR8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDISPR8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDISPR9_IEBBTV_SHIFT (0u)
+#define INTC_ICDISPR9_ISY_SHIFT (1u)
+#define INTC_ICDISPR9_IERR_SHIFT (2u)
+#define INTC_ICDISPR9_ITARG_SHIFT (3u)
+#define INTC_ICDISPR9_ISEC_SHIFT (4u)
+#define INTC_ICDISPR9_IBUF_SHIFT (5u)
+#define INTC_ICDISPR9_IREADY_SHIFT (6u)
+#define INTC_ICDISPR9_FLSTE_SHIFT (7u)
+#define INTC_ICDISPR9_FLTENDI_SHIFT (8u)
+#define INTC_ICDISPR9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDISPR9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDISPR9_MMC0_SHIFT (11u)
+#define INTC_ICDISPR9_MMC1_SHIFT (12u)
+#define INTC_ICDISPR9_MMC2_SHIFT (13u)
+#define INTC_ICDISPR9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDISPR9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDISPR9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDISPR9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDISPR9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDISPR9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDISPR9_ARM_SHIFT (20u)
+#define INTC_ICDISPR9_PRD_SHIFT (21u)
+#define INTC_ICDISPR9_CUP_SHIFT (22u)
+#define INTC_ICDISPR9_SCUAI0_SHIFT (23u)
+#define INTC_ICDISPR9_SCUAI1_SHIFT (24u)
+#define INTC_ICDISPR9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDISPR9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDISPR9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDISPR9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDISPR9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDISPR9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDISPR9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDISPR10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDISPR10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDISPR10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDISPR10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDISPR10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDISPR10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDISPR10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDISPR10_DRC0_SHIFT (7u)
+#define INTC_ICDISPR10_DRC1_SHIFT (8u)
+#define INTC_ICDISPR10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDISPR10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDISPR10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDISPR10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDISPR10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDISPR10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDISPR10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDISPR10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDISPR10_ERI0_SHIFT (27u)
+#define INTC_ICDISPR10_RXI0_SHIFT (28u)
+#define INTC_ICDISPR10_TXI0_SHIFT (29u)
+#define INTC_ICDISPR10_TEI0_SHIFT (30u)
+#define INTC_ICDISPR10_ERI1_SHIFT (31u)
+
+#define INTC_ICDISPR11_RXI1_SHIFT (0u)
+#define INTC_ICDISPR11_TXI1_SHIFT (1u)
+#define INTC_ICDISPR11_TEI1_SHIFT (2u)
+#define INTC_ICDISPR11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDISPR11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDISPR11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDISPR11_ETHERI_SHIFT (7u)
+#define INTC_ICDISPR11_CEUI_SHIFT (12u)
+#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDISPR12_PRRI_SHIFT (8u)
+#define INTC_ICDISPR12_IFEI0_SHIFT (9u)
+#define INTC_ICDISPR12_OFFI0_SHIFT (10u)
+#define INTC_ICDISPR12_PFVEI0_SHIFT (11u)
+#define INTC_ICDISPR12_IFEI1_SHIFT (12u)
+#define INTC_ICDISPR12_OFFI1_SHIFT (13u)
+#define INTC_ICDISPR12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDISPR13_TINT0_SHIFT (0u)
+#define INTC_ICDISPR13_TINT1_SHIFT (1u)
+#define INTC_ICDISPR13_TINT2_SHIFT (2u)
+#define INTC_ICDISPR13_TINT3_SHIFT (3u)
+#define INTC_ICDISPR13_TINT4_SHIFT (4u)
+#define INTC_ICDISPR13_TINT5_SHIFT (5u)
+#define INTC_ICDISPR13_TINT6_SHIFT (6u)
+#define INTC_ICDISPR13_TINT7_SHIFT (7u)
+#define INTC_ICDISPR13_TINT8_SHIFT (8u)
+#define INTC_ICDISPR13_TINT9_SHIFT (9u)
+#define INTC_ICDISPR13_TINT10_SHIFT (10u)
+#define INTC_ICDISPR13_TINT11_SHIFT (11u)
+#define INTC_ICDISPR13_TINT12_SHIFT (12u)
+#define INTC_ICDISPR13_TINT13_SHIFT (13u)
+#define INTC_ICDISPR13_TINT14_SHIFT (14u)
+#define INTC_ICDISPR13_TINT15_SHIFT (15u)
+#define INTC_ICDISPR13_TINT16_SHIFT (16u)
+#define INTC_ICDISPR13_TINT17_SHIFT (17u)
+#define INTC_ICDISPR13_TINT18_SHIFT (18u)
+#define INTC_ICDISPR13_TINT19_SHIFT (19u)
+#define INTC_ICDISPR13_TINT20_SHIFT (20u)
+#define INTC_ICDISPR13_TINT21_SHIFT (21u)
+#define INTC_ICDISPR13_TINT22_SHIFT (22u)
+#define INTC_ICDISPR13_TINT23_SHIFT (23u)
+#define INTC_ICDISPR13_TINT24_SHIFT (24u)
+#define INTC_ICDISPR13_TINT25_SHIFT (25u)
+#define INTC_ICDISPR13_TINT26_SHIFT (26u)
+#define INTC_ICDISPR13_TINT27_SHIFT (27u)
+#define INTC_ICDISPR13_TINT28_SHIFT (28u)
+#define INTC_ICDISPR13_TINT29_SHIFT (29u)
+#define INTC_ICDISPR13_TINT30_SHIFT (30u)
+#define INTC_ICDISPR13_TINT31_SHIFT (31u)
+
+#define INTC_ICDISPR14_TINT32_SHIFT (0u)
+#define INTC_ICDISPR14_TINT33_SHIFT (1u)
+#define INTC_ICDISPR14_TINT34_SHIFT (2u)
+#define INTC_ICDISPR14_TINT35_SHIFT (3u)
+#define INTC_ICDISPR14_TINT36_SHIFT (4u)
+#define INTC_ICDISPR14_TINT37_SHIFT (5u)
+#define INTC_ICDISPR14_TINT38_SHIFT (6u)
+#define INTC_ICDISPR14_TINT39_SHIFT (7u)
+#define INTC_ICDISPR14_TINT40_SHIFT (8u)
+#define INTC_ICDISPR14_TINT41_SHIFT (9u)
+#define INTC_ICDISPR14_TINT42_SHIFT (10u)
+#define INTC_ICDISPR14_TINT43_SHIFT (11u)
+#define INTC_ICDISPR14_TINT44_SHIFT (12u)
+#define INTC_ICDISPR14_TINT45_SHIFT (13u)
+#define INTC_ICDISPR14_TINT46_SHIFT (14u)
+#define INTC_ICDISPR14_TINT47_SHIFT (15u)
+#define INTC_ICDISPR14_TINT48_SHIFT (16u)
+#define INTC_ICDISPR14_TINT49_SHIFT (17u)
+#define INTC_ICDISPR14_TINT50_SHIFT (18u)
+#define INTC_ICDISPR14_TINT51_SHIFT (19u)
+#define INTC_ICDISPR14_TINT52_SHIFT (20u)
+#define INTC_ICDISPR14_TINT53_SHIFT (21u)
+#define INTC_ICDISPR14_TINT54_SHIFT (22u)
+#define INTC_ICDISPR14_TINT55_SHIFT (23u)
+#define INTC_ICDISPR14_TINT56_SHIFT (24u)
+#define INTC_ICDISPR14_TINT57_SHIFT (25u)
+#define INTC_ICDISPR14_TINT58_SHIFT (26u)
+#define INTC_ICDISPR14_TINT59_SHIFT (27u)
+#define INTC_ICDISPR14_TINT60_SHIFT (28u)
+#define INTC_ICDISPR14_TINT61_SHIFT (29u)
+#define INTC_ICDISPR14_TINT62_SHIFT (30u)
+#define INTC_ICDISPR14_TINT63_SHIFT (31u)
+
+#define INTC_ICDISPR15_TINT64_SHIFT (0u)
+#define INTC_ICDISPR15_TINT65_SHIFT (1u)
+#define INTC_ICDISPR15_TINT66_SHIFT (2u)
+#define INTC_ICDISPR15_TINT67_SHIFT (3u)
+#define INTC_ICDISPR15_TINT68_SHIFT (4u)
+#define INTC_ICDISPR15_TINT69_SHIFT (5u)
+#define INTC_ICDISPR15_TINT70_SHIFT (6u)
+#define INTC_ICDISPR15_TINT71_SHIFT (7u)
+#define INTC_ICDISPR15_TINT72_SHIFT (8u)
+#define INTC_ICDISPR15_TINT73_SHIFT (9u)
+#define INTC_ICDISPR15_TINT74_SHIFT (10u)
+#define INTC_ICDISPR15_TINT75_SHIFT (11u)
+#define INTC_ICDISPR15_TINT76_SHIFT (12u)
+#define INTC_ICDISPR15_TINT77_SHIFT (13u)
+#define INTC_ICDISPR15_TINT78_SHIFT (14u)
+#define INTC_ICDISPR15_TINT79_SHIFT (15u)
+#define INTC_ICDISPR15_TINT80_SHIFT (16u)
+#define INTC_ICDISPR15_TINT81_SHIFT (17u)
+#define INTC_ICDISPR15_TINT82_SHIFT (18u)
+#define INTC_ICDISPR15_TINT83_SHIFT (19u)
+#define INTC_ICDISPR15_TINT84_SHIFT (20u)
+#define INTC_ICDISPR15_TINT85_SHIFT (21u)
+#define INTC_ICDISPR15_TINT86_SHIFT (22u)
+#define INTC_ICDISPR15_TINT87_SHIFT (23u)
+#define INTC_ICDISPR15_TINT88_SHIFT (24u)
+#define INTC_ICDISPR15_TINT89_SHIFT (25u)
+#define INTC_ICDISPR15_TINT90_SHIFT (26u)
+#define INTC_ICDISPR15_TINT91_SHIFT (27u)
+#define INTC_ICDISPR15_TINT92_SHIFT (28u)
+#define INTC_ICDISPR15_TINT93_SHIFT (29u)
+#define INTC_ICDISPR15_TINT94_SHIFT (30u)
+#define INTC_ICDISPR15_TINT95_SHIFT (31u)
+
+#define INTC_ICDISPR16_TINT96_SHIFT (0u)
+#define INTC_ICDISPR16_TINT97_SHIFT (1u)
+#define INTC_ICDISPR16_TINT98_SHIFT (2u)
+#define INTC_ICDISPR16_TINT99_SHIFT (3u)
+#define INTC_ICDISPR16_TINT100_SHIFT (4u)
+#define INTC_ICDISPR16_TINT101_SHIFT (5u)
+#define INTC_ICDISPR16_TINT102_SHIFT (6u)
+#define INTC_ICDISPR16_TINT103_SHIFT (7u)
+#define INTC_ICDISPR16_TINT104_SHIFT (8u)
+#define INTC_ICDISPR16_TINT105_SHIFT (9u)
+#define INTC_ICDISPR16_TINT106_SHIFT (10u)
+#define INTC_ICDISPR16_TINT107_SHIFT (11u)
+#define INTC_ICDISPR16_TINT108_SHIFT (12u)
+#define INTC_ICDISPR16_TINT109_SHIFT (13u)
+#define INTC_ICDISPR16_TINT110_SHIFT (14u)
+#define INTC_ICDISPR16_TINT111_SHIFT (15u)
+#define INTC_ICDISPR16_TINT112_SHIFT (16u)
+#define INTC_ICDISPR16_TINT113_SHIFT (17u)
+#define INTC_ICDISPR16_TINT114_SHIFT (18u)
+#define INTC_ICDISPR16_TINT115_SHIFT (19u)
+#define INTC_ICDISPR16_TINT116_SHIFT (20u)
+#define INTC_ICDISPR16_TINT117_SHIFT (21u)
+#define INTC_ICDISPR16_TINT118_SHIFT (22u)
+#define INTC_ICDISPR16_TINT119_SHIFT (23u)
+#define INTC_ICDISPR16_TINT120_SHIFT (24u)
+#define INTC_ICDISPR16_TINT121_SHIFT (25u)
+#define INTC_ICDISPR16_TINT122_SHIFT (26u)
+#define INTC_ICDISPR16_TINT123_SHIFT (27u)
+#define INTC_ICDISPR16_TINT124_SHIFT (28u)
+#define INTC_ICDISPR16_TINT125_SHIFT (29u)
+#define INTC_ICDISPR16_TINT126_SHIFT (30u)
+#define INTC_ICDISPR16_TINT127_SHIFT (31u)
+
+#define INTC_ICDISPR17_TINT128_SHIFT (0u)
+#define INTC_ICDISPR17_TINT129_SHIFT (1u)
+#define INTC_ICDISPR17_TINT130_SHIFT (2u)
+#define INTC_ICDISPR17_TINT131_SHIFT (3u)
+#define INTC_ICDISPR17_TINT132_SHIFT (4u)
+#define INTC_ICDISPR17_TINT133_SHIFT (5u)
+#define INTC_ICDISPR17_TINT134_SHIFT (6u)
+#define INTC_ICDISPR17_TINT135_SHIFT (7u)
+#define INTC_ICDISPR17_TINT136_SHIFT (8u)
+#define INTC_ICDISPR17_TINT137_SHIFT (9u)
+#define INTC_ICDISPR17_TINT138_SHIFT (10u)
+#define INTC_ICDISPR17_TINT139_SHIFT (11u)
+#define INTC_ICDISPR17_TINT140_SHIFT (12u)
+#define INTC_ICDISPR17_TINT141_SHIFT (13u)
+#define INTC_ICDISPR17_TINT142_SHIFT (14u)
+#define INTC_ICDISPR17_TINT143_SHIFT (15u)
+#define INTC_ICDISPR17_TINT144_SHIFT (16u)
+#define INTC_ICDISPR17_TINT145_SHIFT (17u)
+#define INTC_ICDISPR17_TINT146_SHIFT (18u)
+#define INTC_ICDISPR17_TINT147_SHIFT (19u)
+#define INTC_ICDISPR17_TINT148_SHIFT (20u)
+#define INTC_ICDISPR17_TINT149_SHIFT (21u)
+#define INTC_ICDISPR17_TINT150_SHIFT (22u)
+#define INTC_ICDISPR17_TINT151_SHIFT (23u)
+#define INTC_ICDISPR17_TINT152_SHIFT (24u)
+#define INTC_ICDISPR17_TINT153_SHIFT (25u)
+#define INTC_ICDISPR17_TINT154_SHIFT (26u)
+#define INTC_ICDISPR17_TINT155_SHIFT (27u)
+#define INTC_ICDISPR17_TINT156_SHIFT (28u)
+#define INTC_ICDISPR17_TINT157_SHIFT (29u)
+#define INTC_ICDISPR17_TINT158_SHIFT (30u)
+#define INTC_ICDISPR17_TINT159_SHIFT (31u)
+
+#define INTC_ICDISPR18_TINT160_SHIFT (0u)
+#define INTC_ICDISPR18_TINT161_SHIFT (1u)
+#define INTC_ICDISPR18_TINT162_SHIFT (2u)
+#define INTC_ICDISPR18_TINT163_SHIFT (3u)
+#define INTC_ICDISPR18_TINT164_SHIFT (4u)
+#define INTC_ICDISPR18_TINT165_SHIFT (5u)
+#define INTC_ICDISPR18_TINT166_SHIFT (6u)
+#define INTC_ICDISPR18_TINT167_SHIFT (7u)
+#define INTC_ICDISPR18_TINT168_SHIFT (8u)
+#define INTC_ICDISPR18_TINT169_SHIFT (9u)
+#define INTC_ICDISPR18_TINT170_SHIFT (10u)
+
+#define INTC_ICDICPR0_SW0_SHIFT (0u)
+#define INTC_ICDICPR0_SW1_SHIFT (1u)
+#define INTC_ICDICPR0_SW2_SHIFT (2u)
+#define INTC_ICDICPR0_SW3_SHIFT (3u)
+#define INTC_ICDICPR0_SW4_SHIFT (4u)
+#define INTC_ICDICPR0_SW5_SHIFT (5u)
+#define INTC_ICDICPR0_SW6_SHIFT (6u)
+#define INTC_ICDICPR0_SW7_SHIFT (7u)
+#define INTC_ICDICPR0_SW8_SHIFT (8u)
+#define INTC_ICDICPR0_SW9_SHIFT (9u)
+#define INTC_ICDICPR0_SW10_SHIFT (10u)
+#define INTC_ICDICPR0_SW11_SHIFT (11u)
+#define INTC_ICDICPR0_SW12_SHIFT (12u)
+#define INTC_ICDICPR0_SW13_SHIFT (13u)
+#define INTC_ICDICPR0_SW14_SHIFT (14u)
+#define INTC_ICDICPR0_SW15_SHIFT (15u)
+#define INTC_ICDICPR0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDICPR0_COMMRX0_SHIFT (17u)
+#define INTC_ICDICPR0_COMMTX0_SHIFT (18u)
+#define INTC_ICDICPR0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDICPR1_IRQ0_SHIFT (0u)
+#define INTC_ICDICPR1_IRQ1_SHIFT (1u)
+#define INTC_ICDICPR1_IRQ2_SHIFT (2u)
+#define INTC_ICDICPR1_IRQ3_SHIFT (3u)
+#define INTC_ICDICPR1_IRQ4_SHIFT (4u)
+#define INTC_ICDICPR1_IRQ5_SHIFT (5u)
+#define INTC_ICDICPR1_IRQ6_SHIFT (6u)
+#define INTC_ICDICPR1_IRQ7_SHIFT (7u)
+#define INTC_ICDICPR1_PL310ERR_SHIFT (8u)
+#define INTC_ICDICPR1_DMAINT0_SHIFT (9u)
+#define INTC_ICDICPR1_DMAINT1_SHIFT (10u)
+#define INTC_ICDICPR1_DMAINT2_SHIFT (11u)
+#define INTC_ICDICPR1_DMAINT3_SHIFT (12u)
+#define INTC_ICDICPR1_DMAINT4_SHIFT (13u)
+#define INTC_ICDICPR1_DMAINT5_SHIFT (14u)
+#define INTC_ICDICPR1_DMAINT6_SHIFT (15u)
+#define INTC_ICDICPR1_DMAINT7_SHIFT (16u)
+#define INTC_ICDICPR1_DMAINT8_SHIFT (17u)
+#define INTC_ICDICPR1_DMAINT9_SHIFT (18u)
+#define INTC_ICDICPR1_DMAINT10_SHIFT (19u)
+#define INTC_ICDICPR1_DMAINT11_SHIFT (20u)
+#define INTC_ICDICPR1_DMAINT12_SHIFT (21u)
+#define INTC_ICDICPR1_DMAINT13_SHIFT (22u)
+#define INTC_ICDICPR1_DMAINT14_SHIFT (23u)
+#define INTC_ICDICPR1_DMAINT15_SHIFT (24u)
+#define INTC_ICDICPR1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDICPR2_USBI0_SHIFT (9u)
+#define INTC_ICDICPR2_USBI1_SHIFT (10u)
+#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDICPR2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDICPR2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDICPR2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDICPR2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDICPR2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDICPR3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDICPR3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDICPR3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDICPR3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDICPR3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDICPR3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDICPR3_IMRDI_SHIFT (27u)
+#define INTC_ICDICPR3_IMR2I0_SHIFT (28u)
+#define INTC_ICDICPR3_IMR2I1_SHIFT (29u)
+#define INTC_ICDICPR3_JEDI_SHIFT (30u)
+#define INTC_ICDICPR3_JDTI_SHIFT (31u)
+
+#define INTC_ICDICPR4_CMP0_SHIFT (0u)
+#define INTC_ICDICPR4_CMP1_SHIFT (1u)
+#define INTC_ICDICPR4_INT0_SHIFT (2u)
+#define INTC_ICDICPR4_INT1_SHIFT (3u)
+#define INTC_ICDICPR4_INT2_SHIFT (4u)
+#define INTC_ICDICPR4_INT3_SHIFT (5u)
+#define INTC_ICDICPR4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDICPR4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDICPR4_CMI_SHIFT (8u)
+#define INTC_ICDICPR4_WTOUT_SHIFT (9u)
+#define INTC_ICDICPR4_ITI_SHIFT (10u)
+#define INTC_ICDICPR4_TGI0A_SHIFT (11u)
+#define INTC_ICDICPR4_TGI0B_SHIFT (12u)
+#define INTC_ICDICPR4_TGI0C_SHIFT (13u)
+#define INTC_ICDICPR4_TGI0D_SHIFT (14u)
+#define INTC_ICDICPR4_TGI0V_SHIFT (15u)
+#define INTC_ICDICPR4_TGI0E_SHIFT (16u)
+#define INTC_ICDICPR4_TGI0F_SHIFT (17u)
+#define INTC_ICDICPR4_TGI1A_SHIFT (18u)
+#define INTC_ICDICPR4_TGI1B_SHIFT (19u)
+#define INTC_ICDICPR4_TGI1V_SHIFT (20u)
+#define INTC_ICDICPR4_TGI1U_SHIFT (21u)
+#define INTC_ICDICPR4_TGI2A_SHIFT (22u)
+#define INTC_ICDICPR4_TGI2B_SHIFT (23u)
+#define INTC_ICDICPR4_TGI2V_SHIFT (24u)
+#define INTC_ICDICPR4_TGI2U_SHIFT (25u)
+#define INTC_ICDICPR4_TGI3A_SHIFT (26u)
+#define INTC_ICDICPR4_TGI3B_SHIFT (27u)
+#define INTC_ICDICPR4_TGI3C_SHIFT (28u)
+#define INTC_ICDICPR4_TGI3D_SHIFT (29u)
+#define INTC_ICDICPR4_TGI3V_SHIFT (30u)
+#define INTC_ICDICPR4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDICPR5_TGI4B_SHIFT (0u)
+#define INTC_ICDICPR5_TGI4C_SHIFT (1u)
+#define INTC_ICDICPR5_TGI4D_SHIFT (2u)
+#define INTC_ICDICPR5_TGI4V_SHIFT (3u)
+#define INTC_ICDICPR5_CMI1_SHIFT (4u)
+#define INTC_ICDICPR5_CMI2_SHIFT (5u)
+#define INTC_ICDICPR5_SGDEI0_SHIFT (6u)
+#define INTC_ICDICPR5_SGDEI1_SHIFT (7u)
+#define INTC_ICDICPR5_SGDEI2_SHIFT (8u)
+#define INTC_ICDICPR5_SGDEI3_SHIFT (9u)
+#define INTC_ICDICPR5_ADI_SHIFT (10u)
+#define INTC_ICDICPR5_LMTI_SHIFT (11u)
+#define INTC_ICDICPR5_SSII0_SHIFT (12u)
+#define INTC_ICDICPR5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDICPR5_SSITXI0_SHIFT (14u)
+#define INTC_ICDICPR5_SSII1_SHIFT (15u)
+#define INTC_ICDICPR5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDICPR5_SSITXI1_SHIFT (17u)
+#define INTC_ICDICPR5_SSII2_SHIFT (18u)
+#define INTC_ICDICPR5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDICPR5_SSII3_SHIFT (20u)
+#define INTC_ICDICPR5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDICPR5_SSITXI3_SHIFT (22u)
+#define INTC_ICDICPR5_SSII4_SHIFT (23u)
+#define INTC_ICDICPR5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDICPR5_SSII5_SHIFT (25u)
+#define INTC_ICDICPR5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDICPR5_SSITXI5_SHIFT (27u)
+#define INTC_ICDICPR5_SPDIFI_SHIFT (28u)
+#define INTC_ICDICPR5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDICPR5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDICPR5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDICPR6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDICPR6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDICPR6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDICPR6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDICPR6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDICPR6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDICPR6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDICPR6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDICPR6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDICPR6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDICPR6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDICPR6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDICPR6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDICPR6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDICPR6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDICPR6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDICPR6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDICPR6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDICPR6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDICPR6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDICPR6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDICPR6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDICPR6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDICPR6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDICPR6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDICPR6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDICPR6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDICPR6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDICPR6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDICPR6_BRI0_SHIFT (29u)
+#define INTC_ICDICPR6_ERI0_SHIFT (30u)
+#define INTC_ICDICPR6_RXI0_SHIFT (31u)
+
+#define INTC_ICDICPR7_TXI0_SHIFT (0u)
+#define INTC_ICDICPR7_BRI1_SHIFT (1u)
+#define INTC_ICDICPR7_ERI1_SHIFT (2u)
+#define INTC_ICDICPR7_RXI1_SHIFT (3u)
+#define INTC_ICDICPR7_TXI1_SHIFT (4u)
+#define INTC_ICDICPR7_BRI2_SHIFT (5u)
+#define INTC_ICDICPR7_ERI2_SHIFT (6u)
+#define INTC_ICDICPR7_RXI2_SHIFT (7u)
+#define INTC_ICDICPR7_TXI2_SHIFT (8u)
+#define INTC_ICDICPR7_BRI3_SHIFT (9u)
+#define INTC_ICDICPR7_ERI3_SHIFT (10u)
+#define INTC_ICDICPR7_RXI3_SHIFT (11u)
+#define INTC_ICDICPR7_TXI3_SHIFT (12u)
+#define INTC_ICDICPR7_BRI4_SHIFT (13u)
+#define INTC_ICDICPR7_ERI4_SHIFT (14u)
+#define INTC_ICDICPR7_RXI4_SHIFT (15u)
+#define INTC_ICDICPR7_TXI4_SHIFT (16u)
+#define INTC_ICDICPR7_BRI5_SHIFT (17u)
+#define INTC_ICDICPR7_ERI5_SHIFT (18u)
+#define INTC_ICDICPR7_RXI5_SHIFT (19u)
+#define INTC_ICDICPR7_TXI5_SHIFT (20u)
+#define INTC_ICDICPR7_BRI6_SHIFT (21u)
+#define INTC_ICDICPR7_ERI6_SHIFT (22u)
+#define INTC_ICDICPR7_RXI6_SHIFT (23u)
+#define INTC_ICDICPR7_TXI6_SHIFT (24u)
+#define INTC_ICDICPR7_BRI7_SHIFT (25u)
+#define INTC_ICDICPR7_ERI7_SHIFT (26u)
+#define INTC_ICDICPR7_RXI7_SHIFT (27u)
+#define INTC_ICDICPR7_TXI7_SHIFT (28u)
+#define INTC_ICDICPR7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDICPR7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDICPR7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDICPR8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDICPR8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDICPR8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDICPR8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDICPR8_SPEI0_SHIFT (14u)
+#define INTC_ICDICPR8_SPRI0_SHIFT (15u)
+#define INTC_ICDICPR8_SPTI0_SHIFT (16u)
+#define INTC_ICDICPR8_SPEI1_SHIFT (17u)
+#define INTC_ICDICPR8_SPRI1_SHIFT (18u)
+#define INTC_ICDICPR8_SPTI1_SHIFT (19u)
+#define INTC_ICDICPR8_SPEI2_SHIFT (20u)
+#define INTC_ICDICPR8_SPRI2_SHIFT (21u)
+#define INTC_ICDICPR8_SPTI2_SHIFT (22u)
+#define INTC_ICDICPR8_SPEI3_SHIFT (23u)
+#define INTC_ICDICPR8_SPRI3_SHIFT (24u)
+#define INTC_ICDICPR8_SPTI3_SHIFT (25u)
+#define INTC_ICDICPR8_SPEI4_SHIFT (26u)
+#define INTC_ICDICPR8_SPRI4_SHIFT (27u)
+#define INTC_ICDICPR8_SPTI4_SHIFT (28u)
+#define INTC_ICDICPR8_IEBBTD_SHIFT (29u)
+#define INTC_ICDICPR8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDICPR8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDICPR9_IEBBTV_SHIFT (0u)
+#define INTC_ICDICPR9_ISY_SHIFT (1u)
+#define INTC_ICDICPR9_IERR_SHIFT (2u)
+#define INTC_ICDICPR9_ITARG_SHIFT (3u)
+#define INTC_ICDICPR9_ISEC_SHIFT (4u)
+#define INTC_ICDICPR9_IBUF_SHIFT (5u)
+#define INTC_ICDICPR9_IREADY_SHIFT (6u)
+#define INTC_ICDICPR9_FLSTE_SHIFT (7u)
+#define INTC_ICDICPR9_FLTENDI_SHIFT (8u)
+#define INTC_ICDICPR9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDICPR9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDICPR9_MMC0_SHIFT (11u)
+#define INTC_ICDICPR9_MMC1_SHIFT (12u)
+#define INTC_ICDICPR9_MMC2_SHIFT (13u)
+#define INTC_ICDICPR9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDICPR9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDICPR9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDICPR9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDICPR9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDICPR9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDICPR9_ARM_SHIFT (20u)
+#define INTC_ICDICPR9_PRD_SHIFT (21u)
+#define INTC_ICDICPR9_CUP_SHIFT (22u)
+#define INTC_ICDICPR9_SCUAI0_SHIFT (23u)
+#define INTC_ICDICPR9_SCUAI1_SHIFT (24u)
+#define INTC_ICDICPR9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDICPR9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDICPR9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDICPR9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDICPR9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDICPR9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDICPR9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDICPR10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDICPR10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDICPR10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDICPR10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDICPR10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDICPR10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDICPR10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDICPR10_DRC0_SHIFT (7u)
+#define INTC_ICDICPR10_DRC1_SHIFT (8u)
+#define INTC_ICDICPR10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDICPR10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDICPR10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDICPR10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDICPR10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDICPR10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDICPR10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDICPR10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDICPR10_ERI0_SHIFT (27u)
+#define INTC_ICDICPR10_RXI0_SHIFT (28u)
+#define INTC_ICDICPR10_TXI0_SHIFT (29u)
+#define INTC_ICDICPR10_TEI0_SHIFT (30u)
+#define INTC_ICDICPR10_ERI1_SHIFT (31u)
+
+#define INTC_ICDICPR11_RXI1_SHIFT (0u)
+#define INTC_ICDICPR11_TXI1_SHIFT (1u)
+#define INTC_ICDICPR11_TEI1_SHIFT (2u)
+#define INTC_ICDICPR11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDICPR11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDICPR11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDICPR11_ETHERI_SHIFT (7u)
+#define INTC_ICDICPR11_CEUI_SHIFT (12u)
+#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDICPR12_PRRI_SHIFT (8u)
+#define INTC_ICDICPR12_IFEI0_SHIFT (9u)
+#define INTC_ICDICPR12_OFFI0_SHIFT (10u)
+#define INTC_ICDICPR12_PFVEI0_SHIFT (11u)
+#define INTC_ICDICPR12_IFEI1_SHIFT (12u)
+#define INTC_ICDICPR12_OFFI1_SHIFT (13u)
+#define INTC_ICDICPR12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDICPR13_TINT0_SHIFT (0u)
+#define INTC_ICDICPR13_TINT1_SHIFT (1u)
+#define INTC_ICDICPR13_TINT2_SHIFT (2u)
+#define INTC_ICDICPR13_TINT3_SHIFT (3u)
+#define INTC_ICDICPR13_TINT4_SHIFT (4u)
+#define INTC_ICDICPR13_TINT5_SHIFT (5u)
+#define INTC_ICDICPR13_TINT6_SHIFT (6u)
+#define INTC_ICDICPR13_TINT7_SHIFT (7u)
+#define INTC_ICDICPR13_TINT8_SHIFT (8u)
+#define INTC_ICDICPR13_TINT9_SHIFT (9u)
+#define INTC_ICDICPR13_TINT10_SHIFT (10u)
+#define INTC_ICDICPR13_TINT11_SHIFT (11u)
+#define INTC_ICDICPR13_TINT12_SHIFT (12u)
+#define INTC_ICDICPR13_TINT13_SHIFT (13u)
+#define INTC_ICDICPR13_TINT14_SHIFT (14u)
+#define INTC_ICDICPR13_TINT15_SHIFT (15u)
+#define INTC_ICDICPR13_TINT16_SHIFT (16u)
+#define INTC_ICDICPR13_TINT17_SHIFT (17u)
+#define INTC_ICDICPR13_TINT18_SHIFT (18u)
+#define INTC_ICDICPR13_TINT19_SHIFT (19u)
+#define INTC_ICDICPR13_TINT20_SHIFT (20u)
+#define INTC_ICDICPR13_TINT21_SHIFT (21u)
+#define INTC_ICDICPR13_TINT22_SHIFT (22u)
+#define INTC_ICDICPR13_TINT23_SHIFT (23u)
+#define INTC_ICDICPR13_TINT24_SHIFT (24u)
+#define INTC_ICDICPR13_TINT25_SHIFT (25u)
+#define INTC_ICDICPR13_TINT26_SHIFT (26u)
+#define INTC_ICDICPR13_TINT27_SHIFT (27u)
+#define INTC_ICDICPR13_TINT28_SHIFT (28u)
+#define INTC_ICDICPR13_TINT29_SHIFT (29u)
+#define INTC_ICDICPR13_TINT30_SHIFT (30u)
+#define INTC_ICDICPR13_TINT31_SHIFT (31u)
+
+#define INTC_ICDICPR14_TINT32_SHIFT (0u)
+#define INTC_ICDICPR14_TINT33_SHIFT (1u)
+#define INTC_ICDICPR14_TINT34_SHIFT (2u)
+#define INTC_ICDICPR14_TINT35_SHIFT (3u)
+#define INTC_ICDICPR14_TINT36_SHIFT (4u)
+#define INTC_ICDICPR14_TINT37_SHIFT (5u)
+#define INTC_ICDICPR14_TINT38_SHIFT (6u)
+#define INTC_ICDICPR14_TINT39_SHIFT (7u)
+#define INTC_ICDICPR14_TINT40_SHIFT (8u)
+#define INTC_ICDICPR14_TINT41_SHIFT (9u)
+#define INTC_ICDICPR14_TINT42_SHIFT (10u)
+#define INTC_ICDICPR14_TINT43_SHIFT (11u)
+#define INTC_ICDICPR14_TINT44_SHIFT (12u)
+#define INTC_ICDICPR14_TINT45_SHIFT (13u)
+#define INTC_ICDICPR14_TINT46_SHIFT (14u)
+#define INTC_ICDICPR14_TINT47_SHIFT (15u)
+#define INTC_ICDICPR14_TINT48_SHIFT (16u)
+#define INTC_ICDICPR14_TINT49_SHIFT (17u)
+#define INTC_ICDICPR14_TINT50_SHIFT (18u)
+#define INTC_ICDICPR14_TINT51_SHIFT (19u)
+#define INTC_ICDICPR14_TINT52_SHIFT (20u)
+#define INTC_ICDICPR14_TINT53_SHIFT (21u)
+#define INTC_ICDICPR14_TINT54_SHIFT (22u)
+#define INTC_ICDICPR14_TINT55_SHIFT (23u)
+#define INTC_ICDICPR14_TINT56_SHIFT (24u)
+#define INTC_ICDICPR14_TINT57_SHIFT (25u)
+#define INTC_ICDICPR14_TINT58_SHIFT (26u)
+#define INTC_ICDICPR14_TINT59_SHIFT (27u)
+#define INTC_ICDICPR14_TINT60_SHIFT (28u)
+#define INTC_ICDICPR14_TINT61_SHIFT (29u)
+#define INTC_ICDICPR14_TINT62_SHIFT (30u)
+#define INTC_ICDICPR14_TINT63_SHIFT (31u)
+
+#define INTC_ICDICPR15_TINT64_SHIFT (0u)
+#define INTC_ICDICPR15_TINT65_SHIFT (1u)
+#define INTC_ICDICPR15_TINT66_SHIFT (2u)
+#define INTC_ICDICPR15_TINT67_SHIFT (3u)
+#define INTC_ICDICPR15_TINT68_SHIFT (4u)
+#define INTC_ICDICPR15_TINT69_SHIFT (5u)
+#define INTC_ICDICPR15_TINT70_SHIFT (6u)
+#define INTC_ICDICPR15_TINT71_SHIFT (7u)
+#define INTC_ICDICPR15_TINT72_SHIFT (8u)
+#define INTC_ICDICPR15_TINT73_SHIFT (9u)
+#define INTC_ICDICPR15_TINT74_SHIFT (10u)
+#define INTC_ICDICPR15_TINT75_SHIFT (11u)
+#define INTC_ICDICPR15_TINT76_SHIFT (12u)
+#define INTC_ICDICPR15_TINT77_SHIFT (13u)
+#define INTC_ICDICPR15_TINT78_SHIFT (14u)
+#define INTC_ICDICPR15_TINT79_SHIFT (15u)
+#define INTC_ICDICPR15_TINT80_SHIFT (16u)
+#define INTC_ICDICPR15_TINT81_SHIFT (17u)
+#define INTC_ICDICPR15_TINT82_SHIFT (18u)
+#define INTC_ICDICPR15_TINT83_SHIFT (19u)
+#define INTC_ICDICPR15_TINT84_SHIFT (20u)
+#define INTC_ICDICPR15_TINT85_SHIFT (21u)
+#define INTC_ICDICPR15_TINT86_SHIFT (22u)
+#define INTC_ICDICPR15_TINT87_SHIFT (23u)
+#define INTC_ICDICPR15_TINT88_SHIFT (24u)
+#define INTC_ICDICPR15_TINT89_SHIFT (25u)
+#define INTC_ICDICPR15_TINT90_SHIFT (26u)
+#define INTC_ICDICPR15_TINT91_SHIFT (27u)
+#define INTC_ICDICPR15_TINT92_SHIFT (28u)
+#define INTC_ICDICPR15_TINT93_SHIFT (29u)
+#define INTC_ICDICPR15_TINT94_SHIFT (30u)
+#define INTC_ICDICPR15_TINT95_SHIFT (31u)
+
+#define INTC_ICDICPR16_TINT96_SHIFT (0u)
+#define INTC_ICDICPR16_TINT97_SHIFT (1u)
+#define INTC_ICDICPR16_TINT98_SHIFT (2u)
+#define INTC_ICDICPR16_TINT99_SHIFT (3u)
+#define INTC_ICDICPR16_TINT100_SHIFT (4u)
+#define INTC_ICDICPR16_TINT101_SHIFT (5u)
+#define INTC_ICDICPR16_TINT102_SHIFT (6u)
+#define INTC_ICDICPR16_TINT103_SHIFT (7u)
+#define INTC_ICDICPR16_TINT104_SHIFT (8u)
+#define INTC_ICDICPR16_TINT105_SHIFT (9u)
+#define INTC_ICDICPR16_TINT106_SHIFT (10u)
+#define INTC_ICDICPR16_TINT107_SHIFT (11u)
+#define INTC_ICDICPR16_TINT108_SHIFT (12u)
+#define INTC_ICDICPR16_TINT109_SHIFT (13u)
+#define INTC_ICDICPR16_TINT110_SHIFT (14u)
+#define INTC_ICDICPR16_TINT111_SHIFT (15u)
+#define INTC_ICDICPR16_TINT112_SHIFT (16u)
+#define INTC_ICDICPR16_TINT113_SHIFT (17u)
+#define INTC_ICDICPR16_TINT114_SHIFT (18u)
+#define INTC_ICDICPR16_TINT115_SHIFT (19u)
+#define INTC_ICDICPR16_TINT116_SHIFT (20u)
+#define INTC_ICDICPR16_TINT117_SHIFT (21u)
+#define INTC_ICDICPR16_TINT118_SHIFT (22u)
+#define INTC_ICDICPR16_TINT119_SHIFT (23u)
+#define INTC_ICDICPR16_TINT120_SHIFT (24u)
+#define INTC_ICDICPR16_TINT121_SHIFT (25u)
+#define INTC_ICDICPR16_TINT122_SHIFT (26u)
+#define INTC_ICDICPR16_TINT123_SHIFT (27u)
+#define INTC_ICDICPR16_TINT124_SHIFT (28u)
+#define INTC_ICDICPR16_TINT125_SHIFT (29u)
+#define INTC_ICDICPR16_TINT126_SHIFT (30u)
+#define INTC_ICDICPR16_TINT127_SHIFT (31u)
+
+#define INTC_ICDICPR17_TINT128_SHIFT (0u)
+#define INTC_ICDICPR17_TINT129_SHIFT (1u)
+#define INTC_ICDICPR17_TINT130_SHIFT (2u)
+#define INTC_ICDICPR17_TINT131_SHIFT (3u)
+#define INTC_ICDICPR17_TINT132_SHIFT (4u)
+#define INTC_ICDICPR17_TINT133_SHIFT (5u)
+#define INTC_ICDICPR17_TINT134_SHIFT (6u)
+#define INTC_ICDICPR17_TINT135_SHIFT (7u)
+#define INTC_ICDICPR17_TINT136_SHIFT (8u)
+#define INTC_ICDICPR17_TINT137_SHIFT (9u)
+#define INTC_ICDICPR17_TINT138_SHIFT (10u)
+#define INTC_ICDICPR17_TINT139_SHIFT (11u)
+#define INTC_ICDICPR17_TINT140_SHIFT (12u)
+#define INTC_ICDICPR17_TINT141_SHIFT (13u)
+#define INTC_ICDICPR17_TINT142_SHIFT (14u)
+#define INTC_ICDICPR17_TINT143_SHIFT (15u)
+#define INTC_ICDICPR17_TINT144_SHIFT (16u)
+#define INTC_ICDICPR17_TINT145_SHIFT (17u)
+#define INTC_ICDICPR17_TINT146_SHIFT (18u)
+#define INTC_ICDICPR17_TINT147_SHIFT (19u)
+#define INTC_ICDICPR17_TINT148_SHIFT (20u)
+#define INTC_ICDICPR17_TINT149_SHIFT (21u)
+#define INTC_ICDICPR17_TINT150_SHIFT (22u)
+#define INTC_ICDICPR17_TINT151_SHIFT (23u)
+#define INTC_ICDICPR17_TINT152_SHIFT (24u)
+#define INTC_ICDICPR17_TINT153_SHIFT (25u)
+#define INTC_ICDICPR17_TINT154_SHIFT (26u)
+#define INTC_ICDICPR17_TINT155_SHIFT (27u)
+#define INTC_ICDICPR17_TINT156_SHIFT (28u)
+#define INTC_ICDICPR17_TINT157_SHIFT (29u)
+#define INTC_ICDICPR17_TINT158_SHIFT (30u)
+#define INTC_ICDICPR17_TINT159_SHIFT (31u)
+
+#define INTC_ICDICPR18_TINT160_SHIFT (0u)
+#define INTC_ICDICPR18_TINT161_SHIFT (1u)
+#define INTC_ICDICPR18_TINT162_SHIFT (2u)
+#define INTC_ICDICPR18_TINT163_SHIFT (3u)
+#define INTC_ICDICPR18_TINT164_SHIFT (4u)
+#define INTC_ICDICPR18_TINT165_SHIFT (5u)
+#define INTC_ICDICPR18_TINT166_SHIFT (6u)
+#define INTC_ICDICPR18_TINT167_SHIFT (7u)
+#define INTC_ICDICPR18_TINT168_SHIFT (8u)
+#define INTC_ICDICPR18_TINT169_SHIFT (9u)
+#define INTC_ICDICPR18_TINT170_SHIFT (10u)
+
+#define INTC_ICDABR0_SW0_SHIFT (0u)
+#define INTC_ICDABR0_SW1_SHIFT (1u)
+#define INTC_ICDABR0_SW2_SHIFT (2u)
+#define INTC_ICDABR0_SW3_SHIFT (3u)
+#define INTC_ICDABR0_SW4_SHIFT (4u)
+#define INTC_ICDABR0_SW5_SHIFT (5u)
+#define INTC_ICDABR0_SW6_SHIFT (6u)
+#define INTC_ICDABR0_SW7_SHIFT (7u)
+#define INTC_ICDABR0_SW8_SHIFT (8u)
+#define INTC_ICDABR0_SW9_SHIFT (9u)
+#define INTC_ICDABR0_SW10_SHIFT (10u)
+#define INTC_ICDABR0_SW11_SHIFT (11u)
+#define INTC_ICDABR0_SW12_SHIFT (12u)
+#define INTC_ICDABR0_SW13_SHIFT (13u)
+#define INTC_ICDABR0_SW14_SHIFT (14u)
+#define INTC_ICDABR0_SW15_SHIFT (15u)
+#define INTC_ICDABR0_PMUIRQ0_SHIFT (16u)
+#define INTC_ICDABR0_COMMRX0_SHIFT (17u)
+#define INTC_ICDABR0_COMMTX0_SHIFT (18u)
+#define INTC_ICDABR0_CTIIRQ0_SHIFT (19u)
+
+#define INTC_ICDABR1_IRQ0_SHIFT (0u)
+#define INTC_ICDABR1_IRQ1_SHIFT (1u)
+#define INTC_ICDABR1_IRQ2_SHIFT (2u)
+#define INTC_ICDABR1_IRQ3_SHIFT (3u)
+#define INTC_ICDABR1_IRQ4_SHIFT (4u)
+#define INTC_ICDABR1_IRQ5_SHIFT (5u)
+#define INTC_ICDABR1_IRQ6_SHIFT (6u)
+#define INTC_ICDABR1_IRQ7_SHIFT (7u)
+#define INTC_ICDABR1_PL310ERR_SHIFT (8u)
+#define INTC_ICDABR1_DMAINT0_SHIFT (9u)
+#define INTC_ICDABR1_DMAINT1_SHIFT (10u)
+#define INTC_ICDABR1_DMAINT2_SHIFT (11u)
+#define INTC_ICDABR1_DMAINT3_SHIFT (12u)
+#define INTC_ICDABR1_DMAINT4_SHIFT (13u)
+#define INTC_ICDABR1_DMAINT5_SHIFT (14u)
+#define INTC_ICDABR1_DMAINT6_SHIFT (15u)
+#define INTC_ICDABR1_DMAINT7_SHIFT (16u)
+#define INTC_ICDABR1_DMAINT8_SHIFT (17u)
+#define INTC_ICDABR1_DMAINT9_SHIFT (18u)
+#define INTC_ICDABR1_DMAINT10_SHIFT (19u)
+#define INTC_ICDABR1_DMAINT11_SHIFT (20u)
+#define INTC_ICDABR1_DMAINT12_SHIFT (21u)
+#define INTC_ICDABR1_DMAINT13_SHIFT (22u)
+#define INTC_ICDABR1_DMAINT14_SHIFT (23u)
+#define INTC_ICDABR1_DMAINT15_SHIFT (24u)
+#define INTC_ICDABR1_DMAERR_SHIFT (25u)
+
+#define INTC_ICDABR2_USBI0_SHIFT (9u)
+#define INTC_ICDABR2_USBI1_SHIFT (10u)
+#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT (11u)
+#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT (12u)
+#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT (13u)
+#define INTC_ICDABR2_GR3_VLINE0_SHIFT (14u)
+#define INTC_ICDABR2_S0_VFIELD0_SHIFT (15u)
+#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT (16u)
+#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT (17u)
+#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT (18u)
+#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT (19u)
+#define INTC_ICDABR2_S0_WLINE0_SHIFT (20u)
+#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT (21u)
+#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT (22u)
+#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT (23u)
+#define INTC_ICDABR2_S1_VFIELD0_SHIFT (24u)
+#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT (25u)
+#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT (26u)
+#define INTC_ICDABR2_S1_WLINE0_SHIFT (27u)
+#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT (28u)
+#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT (29u)
+#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT (30u)
+#define INTC_ICDABR2_OIR_VFIELD0_SHIFT (31u)
+
+#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT (1u)
+#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT (3u)
+#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT (4u)
+#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT (5u)
+#define INTC_ICDABR3_GR3_VLINE1_SHIFT (6u)
+#define INTC_ICDABR3_S0_VFIELD1_SHIFT (7u)
+#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT (8u)
+#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT (9u)
+#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT (10u)
+#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT (11u)
+#define INTC_ICDABR3_S0_WLINE1_SHIFT (12u)
+#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT (13u)
+#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT (14u)
+#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT (15u)
+#define INTC_ICDABR3_S1_VFIELD1_SHIFT (16u)
+#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT (17u)
+#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT (18u)
+#define INTC_ICDABR3_S1_WLINE1_SHIFT (19u)
+#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT (20u)
+#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT (21u)
+#define INTC_ICDABR3_OIR_VLINE1_SHIFT (22u)
+#define INTC_ICDABR3_OIR_VFIELD1_SHIFT (23u)
+#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT (24u)
+#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT (25u)
+#define INTC_ICDABR3_IMRDI_SHIFT (27u)
+#define INTC_ICDABR3_IMR2I0_SHIFT (28u)
+#define INTC_ICDABR3_IMR2I1_SHIFT (29u)
+#define INTC_ICDABR3_JEDI_SHIFT (30u)
+#define INTC_ICDABR3_JDTI_SHIFT (31u)
+
+#define INTC_ICDABR4_CMP0_SHIFT (0u)
+#define INTC_ICDABR4_CMP1_SHIFT (1u)
+#define INTC_ICDABR4_INT0_SHIFT (2u)
+#define INTC_ICDABR4_INT1_SHIFT (3u)
+#define INTC_ICDABR4_INT2_SHIFT (4u)
+#define INTC_ICDABR4_INT3_SHIFT (5u)
+#define INTC_ICDABR4_OSTM0TINT_SHIFT (6u)
+#define INTC_ICDABR4_OSTM1TINT_SHIFT (7u)
+#define INTC_ICDABR4_CMI_SHIFT (8u)
+#define INTC_ICDABR4_WTOUT_SHIFT (9u)
+#define INTC_ICDABR4_ITI_SHIFT (10u)
+#define INTC_ICDABR4_TGI0A_SHIFT (11u)
+#define INTC_ICDABR4_TGI0B_SHIFT (12u)
+#define INTC_ICDABR4_TGI0C_SHIFT (13u)
+#define INTC_ICDABR4_TGI0D_SHIFT (14u)
+#define INTC_ICDABR4_TGI0V_SHIFT (15u)
+#define INTC_ICDABR4_TGI0E_SHIFT (16u)
+#define INTC_ICDABR4_TGI0F_SHIFT (17u)
+#define INTC_ICDABR4_TGI1A_SHIFT (18u)
+#define INTC_ICDABR4_TGI1B_SHIFT (19u)
+#define INTC_ICDABR4_TGI1V_SHIFT (20u)
+#define INTC_ICDABR4_TGI1U_SHIFT (21u)
+#define INTC_ICDABR4_TGI2A_SHIFT (22u)
+#define INTC_ICDABR4_TGI2B_SHIFT (23u)
+#define INTC_ICDABR4_TGI2V_SHIFT (24u)
+#define INTC_ICDABR4_TGI2U_SHIFT (25u)
+#define INTC_ICDABR4_TGI3A_SHIFT (26u)
+#define INTC_ICDABR4_TGI3B_SHIFT (27u)
+#define INTC_ICDABR4_TGI3C_SHIFT (28u)
+#define INTC_ICDABR4_TGI3D_SHIFT (29u)
+#define INTC_ICDABR4_TGI3V_SHIFT (30u)
+#define INTC_ICDABR4_TGI4A_SHIFT (31u)
+
+#define INTC_ICDABR5_TGI4B_SHIFT (0u)
+#define INTC_ICDABR5_TGI4C_SHIFT (1u)
+#define INTC_ICDABR5_TGI4D_SHIFT (2u)
+#define INTC_ICDABR5_TGI4V_SHIFT (3u)
+#define INTC_ICDABR5_CMI1_SHIFT (4u)
+#define INTC_ICDABR5_CMI2_SHIFT (5u)
+#define INTC_ICDABR5_SGDEI0_SHIFT (6u)
+#define INTC_ICDABR5_SGDEI1_SHIFT (7u)
+#define INTC_ICDABR5_SGDEI2_SHIFT (8u)
+#define INTC_ICDABR5_SGDEI3_SHIFT (9u)
+#define INTC_ICDABR5_ADI_SHIFT (10u)
+#define INTC_ICDABR5_LMTI_SHIFT (11u)
+#define INTC_ICDABR5_SSII0_SHIFT (12u)
+#define INTC_ICDABR5_SSIRXI0_SHIFT (13u)
+#define INTC_ICDABR5_SSITXI0_SHIFT (14u)
+#define INTC_ICDABR5_SSII1_SHIFT (15u)
+#define INTC_ICDABR5_SSIRXI1_SHIFT (16u)
+#define INTC_ICDABR5_SSITXI1_SHIFT (17u)
+#define INTC_ICDABR5_SSII2_SHIFT (18u)
+#define INTC_ICDABR5_SSIRTI2_SHIFT (19u)
+#define INTC_ICDABR5_SSII3_SHIFT (20u)
+#define INTC_ICDABR5_SSIRXI3_SHIFT (21u)
+#define INTC_ICDABR5_SSITXI3_SHIFT (22u)
+#define INTC_ICDABR5_SSII4_SHIFT (23u)
+#define INTC_ICDABR5_SSIRTI4_SHIFT (24u)
+#define INTC_ICDABR5_SSII5_SHIFT (25u)
+#define INTC_ICDABR5_SSIRXI5_SHIFT (26u)
+#define INTC_ICDABR5_SSITXI5_SHIFT (27u)
+#define INTC_ICDABR5_SPDIFI_SHIFT (28u)
+#define INTC_ICDABR5_INTIICTEI0_SHIFT (29u)
+#define INTC_ICDABR5_INTIICRI0_SHIFT (30u)
+#define INTC_ICDABR5_INTIICTI0_SHIFT (31u)
+
+#define INTC_ICDABR6_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDABR6_INTIICSTI0_SHIFT (1u)
+#define INTC_ICDABR6_INTIICNAKI0_SHIFT (2u)
+#define INTC_ICDABR6_INTIICALI0_SHIFT (3u)
+#define INTC_ICDABR6_INTIICTMOI0_SHIFT (4u)
+#define INTC_ICDABR6_INTIICTEI1_SHIFT (5u)
+#define INTC_ICDABR6_INTIICRI1_SHIFT (6u)
+#define INTC_ICDABR6_INTIICTI1_SHIFT (7u)
+#define INTC_ICDABR6_INTIICSPI1_SHIFT (8u)
+#define INTC_ICDABR6_INTIICSTI1_SHIFT (9u)
+#define INTC_ICDABR6_INTIICNAKI1_SHIFT (10u)
+#define INTC_ICDABR6_INTIICALI1_SHIFT (11u)
+#define INTC_ICDABR6_INTIICTMOI1_SHIFT (12u)
+#define INTC_ICDABR6_INTIICTEI2_SHIFT (13u)
+#define INTC_ICDABR6_INTIICRI2_SHIFT (14u)
+#define INTC_ICDABR6_INTIICTI2_SHIFT (15u)
+#define INTC_ICDABR6_INTIICSPI2_SHIFT (16u)
+#define INTC_ICDABR6_INTIICSTI2_SHIFT (17u)
+#define INTC_ICDABR6_INTIICNAKI2_SHIFT (18u)
+#define INTC_ICDABR6_INTIICALI2_SHIFT (19u)
+#define INTC_ICDABR6_INTIICTMOI2_SHIFT (20u)
+#define INTC_ICDABR6_INTIICTEI3_SHIFT (21u)
+#define INTC_ICDABR6_INTIICRI3_SHIFT (22u)
+#define INTC_ICDABR6_INTIICTI3_SHIFT (23u)
+#define INTC_ICDABR6_INTIICSPI3_SHIFT (24u)
+#define INTC_ICDABR6_INTIICSTI3_SHIFT (25u)
+#define INTC_ICDABR6_INTIICNAKI3_SHIFT (26u)
+#define INTC_ICDABR6_INTIICALI3_SHIFT (27u)
+#define INTC_ICDABR6_INTIICTMOI3_SHIFT (28u)
+#define INTC_ICDABR6_BRI0_SHIFT (29u)
+#define INTC_ICDABR6_ERI0_SHIFT (30u)
+#define INTC_ICDABR6_RXI0_SHIFT (31u)
+
+#define INTC_ICDABR7_TXI0_SHIFT (0u)
+#define INTC_ICDABR7_BRI1_SHIFT (1u)
+#define INTC_ICDABR7_ERI1_SHIFT (2u)
+#define INTC_ICDABR7_RXI1_SHIFT (3u)
+#define INTC_ICDABR7_TXI1_SHIFT (4u)
+#define INTC_ICDABR7_BRI2_SHIFT (5u)
+#define INTC_ICDABR7_ERI2_SHIFT (6u)
+#define INTC_ICDABR7_RXI2_SHIFT (7u)
+#define INTC_ICDABR7_TXI2_SHIFT (8u)
+#define INTC_ICDABR7_BRI3_SHIFT (9u)
+#define INTC_ICDABR7_ERI3_SHIFT (10u)
+#define INTC_ICDABR7_RXI3_SHIFT (11u)
+#define INTC_ICDABR7_TXI3_SHIFT (12u)
+#define INTC_ICDABR7_BRI4_SHIFT (13u)
+#define INTC_ICDABR7_ERI4_SHIFT (14u)
+#define INTC_ICDABR7_RXI4_SHIFT (15u)
+#define INTC_ICDABR7_TXI4_SHIFT (16u)
+#define INTC_ICDABR7_BRI5_SHIFT (17u)
+#define INTC_ICDABR7_ERI5_SHIFT (18u)
+#define INTC_ICDABR7_RXI5_SHIFT (19u)
+#define INTC_ICDABR7_TXI5_SHIFT (20u)
+#define INTC_ICDABR7_BRI6_SHIFT (21u)
+#define INTC_ICDABR7_ERI6_SHIFT (22u)
+#define INTC_ICDABR7_RXI6_SHIFT (23u)
+#define INTC_ICDABR7_TXI6_SHIFT (24u)
+#define INTC_ICDABR7_BRI7_SHIFT (25u)
+#define INTC_ICDABR7_ERI7_SHIFT (26u)
+#define INTC_ICDABR7_RXI7_SHIFT (27u)
+#define INTC_ICDABR7_TXI7_SHIFT (28u)
+#define INTC_ICDABR7_INTRCANGERR_SHIFT (29u)
+#define INTC_ICDABR7_INTRCANGRECC_SHIFT (30u)
+#define INTC_ICDABR7_INTRCAN0REC_SHIFT (31u)
+
+#define INTC_ICDABR8_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDABR8_INTRCAN0TRX_SHIFT (1u)
+#define INTC_ICDABR8_INTRCAN1REC_SHIFT (2u)
+#define INTC_ICDABR8_INTRCAN1ERR_SHIFT (3u)
+#define INTC_ICDABR8_INTRCAN1TRX_SHIFT (4u)
+#define INTC_ICDABR8_INTRCAN2REC_SHIFT (5u)
+#define INTC_ICDABR8_INTRCAN2ERR_SHIFT (6u)
+#define INTC_ICDABR8_INTRCAN2TRX_SHIFT (7u)
+#define INTC_ICDABR8_INTRCAN3REC_SHIFT (8u)
+#define INTC_ICDABR8_INTRCAN3ERR_SHIFT (9u)
+#define INTC_ICDABR8_INTRCAN3TRX_SHIFT (10u)
+#define INTC_ICDABR8_INTRCAN4REC_SHIFT (11u)
+#define INTC_ICDABR8_INTRCAN4ERR_SHIFT (12u)
+#define INTC_ICDABR8_INTRCAN4TRX_SHIFT (13u)
+#define INTC_ICDABR8_SPEI0_SHIFT (14u)
+#define INTC_ICDABR8_SPRI0_SHIFT (15u)
+#define INTC_ICDABR8_SPTI0_SHIFT (16u)
+#define INTC_ICDABR8_SPEI1_SHIFT (17u)
+#define INTC_ICDABR8_SPRI1_SHIFT (18u)
+#define INTC_ICDABR8_SPTI1_SHIFT (19u)
+#define INTC_ICDABR8_SPEI2_SHIFT (20u)
+#define INTC_ICDABR8_SPRI2_SHIFT (21u)
+#define INTC_ICDABR8_SPTI2_SHIFT (22u)
+#define INTC_ICDABR8_SPEI3_SHIFT (23u)
+#define INTC_ICDABR8_SPRI3_SHIFT (24u)
+#define INTC_ICDABR8_SPTI3_SHIFT (25u)
+#define INTC_ICDABR8_SPEI4_SHIFT (26u)
+#define INTC_ICDABR8_SPRI4_SHIFT (27u)
+#define INTC_ICDABR8_SPTI4_SHIFT (28u)
+#define INTC_ICDABR8_IEBBTD_SHIFT (29u)
+#define INTC_ICDABR8_IEBBTERR_SHIFT (30u)
+#define INTC_ICDABR8_IEBBTSTA_SHIFT (31u)
+
+#define INTC_ICDABR9_IEBBTV_SHIFT (0u)
+#define INTC_ICDABR9_ISY_SHIFT (1u)
+#define INTC_ICDABR9_IERR_SHIFT (2u)
+#define INTC_ICDABR9_ITARG_SHIFT (3u)
+#define INTC_ICDABR9_ISEC_SHIFT (4u)
+#define INTC_ICDABR9_IBUF_SHIFT (5u)
+#define INTC_ICDABR9_IREADY_SHIFT (6u)
+#define INTC_ICDABR9_FLSTE_SHIFT (7u)
+#define INTC_ICDABR9_FLTENDI_SHIFT (8u)
+#define INTC_ICDABR9_FLTREQ0I_SHIFT (9u)
+#define INTC_ICDABR9_FLTREQ1I_SHIFT (10u)
+#define INTC_ICDABR9_MMC0_SHIFT (11u)
+#define INTC_ICDABR9_MMC1_SHIFT (12u)
+#define INTC_ICDABR9_MMC2_SHIFT (13u)
+#define INTC_ICDABR9_SDHI0_3_SHIFT (14u)
+#define INTC_ICDABR9_SDHI0_0_SHIFT (15u)
+#define INTC_ICDABR9_SDHI0_1_SHIFT (16u)
+#define INTC_ICDABR9_SDHI1_3_SHIFT (17u)
+#define INTC_ICDABR9_SDHI1_0_SHIFT (18u)
+#define INTC_ICDABR9_SDHI1_1_SHIFT (19u)
+#define INTC_ICDABR9_ARM_SHIFT (20u)
+#define INTC_ICDABR9_PRD_SHIFT (21u)
+#define INTC_ICDABR9_CUP_SHIFT (22u)
+#define INTC_ICDABR9_SCUAI0_SHIFT (23u)
+#define INTC_ICDABR9_SCUAI1_SHIFT (24u)
+#define INTC_ICDABR9_SCUFDI0_SHIFT (25u)
+#define INTC_ICDABR9_SCUFDI1_SHIFT (26u)
+#define INTC_ICDABR9_SCUFDI2_SHIFT (27u)
+#define INTC_ICDABR9_SCUFDI3_SHIFT (28u)
+#define INTC_ICDABR9_SCUFUI0_SHIFT (29u)
+#define INTC_ICDABR9_SCUFUI1_SHIFT (30u)
+#define INTC_ICDABR9_SCUFUI2_SHIFT (31u)
+
+#define INTC_ICDABR10_SCUFUI3_SHIFT (0u)
+#define INTC_ICDABR10_SCUDVI0_SHIFT (1u)
+#define INTC_ICDABR10_SCUDVI1_SHIFT (2u)
+#define INTC_ICDABR10_SCUDVI2_SHIFT (3u)
+#define INTC_ICDABR10_SCUDVI3_SHIFT (4u)
+#define INTC_ICDABR10_MLB_CINT_SHIFT (5u)
+#define INTC_ICDABR10_MLB_SINT_SHIFT (6u)
+#define INTC_ICDABR10_DRC0_SHIFT (7u)
+#define INTC_ICDABR10_DRC1_SHIFT (8u)
+#define INTC_ICDABR10_LINI0_INT_T_SHIFT (11u)
+#define INTC_ICDABR10_LINI0_INT_R_SHIFT (12u)
+#define INTC_ICDABR10_LINI0_INT_S_SHIFT (13u)
+#define INTC_ICDABR10_LINI0_INT_M_SHIFT (14u)
+#define INTC_ICDABR10_LINI1_INT_T_SHIFT (15u)
+#define INTC_ICDABR10_LINI1_INT_R_SHIFT (16u)
+#define INTC_ICDABR10_LINI1_INT_S_SHIFT (17u)
+#define INTC_ICDABR10_LINI1_INT_M_SHIFT (18u)
+#define INTC_ICDABR10_ERI0_SHIFT (27u)
+#define INTC_ICDABR10_RXI0_SHIFT (28u)
+#define INTC_ICDABR10_TXI0_SHIFT (29u)
+#define INTC_ICDABR10_TEI0_SHIFT (30u)
+#define INTC_ICDABR10_ERI1_SHIFT (31u)
+
+#define INTC_ICDABR11_RXI1_SHIFT (0u)
+#define INTC_ICDABR11_TXI1_SHIFT (1u)
+#define INTC_ICDABR11_TEI1_SHIFT (2u)
+#define INTC_ICDABR11_AVBI_DATA_SHIFT (3u)
+#define INTC_ICDABR11_AVBI_ERROR_SHIFT (4u)
+#define INTC_ICDABR11_AVBI_MANAGE_SHIFT (5u)
+#define INTC_ICDABR11_AVBI_MAC_SHIFT (6u)
+#define INTC_ICDABR11_ETHERI_SHIFT (7u)
+#define INTC_ICDABR11_CEUI_SHIFT (12u)
+#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT (29u)
+#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT (30u)
+#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT (31u)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT (1u)
+#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT (2u)
+#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT (3u)
+#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT (4u)
+#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT (5u)
+#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT (6u)
+#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT (7u)
+#define INTC_ICDABR12_PRRI_SHIFT (8u)
+#define INTC_ICDABR12_IFEI0_SHIFT (9u)
+#define INTC_ICDABR12_OFFI0_SHIFT (10u)
+#define INTC_ICDABR12_PFVEI0_SHIFT (11u)
+#define INTC_ICDABR12_IFEI1_SHIFT (12u)
+#define INTC_ICDABR12_OFFI1_SHIFT (13u)
+#define INTC_ICDABR12_PFVEI1_SHIFT (14u)
+
+#define INTC_ICDABR13_TINT0_SHIFT (0u)
+#define INTC_ICDABR13_TINT1_SHIFT (1u)
+#define INTC_ICDABR13_TINT2_SHIFT (2u)
+#define INTC_ICDABR13_TINT3_SHIFT (3u)
+#define INTC_ICDABR13_TINT4_SHIFT (4u)
+#define INTC_ICDABR13_TINT5_SHIFT (5u)
+#define INTC_ICDABR13_TINT6_SHIFT (6u)
+#define INTC_ICDABR13_TINT7_SHIFT (7u)
+#define INTC_ICDABR13_TINT8_SHIFT (8u)
+#define INTC_ICDABR13_TINT9_SHIFT (9u)
+#define INTC_ICDABR13_TINT10_SHIFT (10u)
+#define INTC_ICDABR13_TINT11_SHIFT (11u)
+#define INTC_ICDABR13_TINT12_SHIFT (12u)
+#define INTC_ICDABR13_TINT13_SHIFT (13u)
+#define INTC_ICDABR13_TINT14_SHIFT (14u)
+#define INTC_ICDABR13_TINT15_SHIFT (15u)
+#define INTC_ICDABR13_TINT16_SHIFT (16u)
+#define INTC_ICDABR13_TINT17_SHIFT (17u)
+#define INTC_ICDABR13_TINT18_SHIFT (18u)
+#define INTC_ICDABR13_TINT19_SHIFT (19u)
+#define INTC_ICDABR13_TINT20_SHIFT (20u)
+#define INTC_ICDABR13_TINT21_SHIFT (21u)
+#define INTC_ICDABR13_TINT22_SHIFT (22u)
+#define INTC_ICDABR13_TINT23_SHIFT (23u)
+#define INTC_ICDABR13_TINT24_SHIFT (24u)
+#define INTC_ICDABR13_TINT25_SHIFT (25u)
+#define INTC_ICDABR13_TINT26_SHIFT (26u)
+#define INTC_ICDABR13_TINT27_SHIFT (27u)
+#define INTC_ICDABR13_TINT28_SHIFT (28u)
+#define INTC_ICDABR13_TINT29_SHIFT (29u)
+#define INTC_ICDABR13_TINT30_SHIFT (30u)
+#define INTC_ICDABR13_TINT31_SHIFT (31u)
+
+#define INTC_ICDABR14_TINT32_SHIFT (0u)
+#define INTC_ICDABR14_TINT33_SHIFT (1u)
+#define INTC_ICDABR14_TINT34_SHIFT (2u)
+#define INTC_ICDABR14_TINT35_SHIFT (3u)
+#define INTC_ICDABR14_TINT36_SHIFT (4u)
+#define INTC_ICDABR14_TINT37_SHIFT (5u)
+#define INTC_ICDABR14_TINT38_SHIFT (6u)
+#define INTC_ICDABR14_TINT39_SHIFT (7u)
+#define INTC_ICDABR14_TINT40_SHIFT (8u)
+#define INTC_ICDABR14_TINT41_SHIFT (9u)
+#define INTC_ICDABR14_TINT42_SHIFT (10u)
+#define INTC_ICDABR14_TINT43_SHIFT (11u)
+#define INTC_ICDABR14_TINT44_SHIFT (12u)
+#define INTC_ICDABR14_TINT45_SHIFT (13u)
+#define INTC_ICDABR14_TINT46_SHIFT (14u)
+#define INTC_ICDABR14_TINT47_SHIFT (15u)
+#define INTC_ICDABR14_TINT48_SHIFT (16u)
+#define INTC_ICDABR14_TINT49_SHIFT (17u)
+#define INTC_ICDABR14_TINT50_SHIFT (18u)
+#define INTC_ICDABR14_TINT51_SHIFT (19u)
+#define INTC_ICDABR14_TINT52_SHIFT (20u)
+#define INTC_ICDABR14_TINT53_SHIFT (21u)
+#define INTC_ICDABR14_TINT54_SHIFT (22u)
+#define INTC_ICDABR14_TINT55_SHIFT (23u)
+#define INTC_ICDABR14_TINT56_SHIFT (24u)
+#define INTC_ICDABR14_TINT57_SHIFT (25u)
+#define INTC_ICDABR14_TINT58_SHIFT (26u)
+#define INTC_ICDABR14_TINT59_SHIFT (27u)
+#define INTC_ICDABR14_TINT60_SHIFT (28u)
+#define INTC_ICDABR14_TINT61_SHIFT (29u)
+#define INTC_ICDABR14_TINT62_SHIFT (30u)
+#define INTC_ICDABR14_TINT63_SHIFT (31u)
+
+#define INTC_ICDABR15_TINT64_SHIFT (0u)
+#define INTC_ICDABR15_TINT65_SHIFT (1u)
+#define INTC_ICDABR15_TINT66_SHIFT (2u)
+#define INTC_ICDABR15_TINT67_SHIFT (3u)
+#define INTC_ICDABR15_TINT68_SHIFT (4u)
+#define INTC_ICDABR15_TINT69_SHIFT (5u)
+#define INTC_ICDABR15_TINT70_SHIFT (6u)
+#define INTC_ICDABR15_TINT71_SHIFT (7u)
+#define INTC_ICDABR15_TINT72_SHIFT (8u)
+#define INTC_ICDABR15_TINT73_SHIFT (9u)
+#define INTC_ICDABR15_TINT74_SHIFT (10u)
+#define INTC_ICDABR15_TINT75_SHIFT (11u)
+#define INTC_ICDABR15_TINT76_SHIFT (12u)
+#define INTC_ICDABR15_TINT77_SHIFT (13u)
+#define INTC_ICDABR15_TINT78_SHIFT (14u)
+#define INTC_ICDABR15_TINT79_SHIFT (15u)
+#define INTC_ICDABR15_TINT80_SHIFT (16u)
+#define INTC_ICDABR15_TINT81_SHIFT (17u)
+#define INTC_ICDABR15_TINT82_SHIFT (18u)
+#define INTC_ICDABR15_TINT83_SHIFT (19u)
+#define INTC_ICDABR15_TINT84_SHIFT (20u)
+#define INTC_ICDABR15_TINT85_SHIFT (21u)
+#define INTC_ICDABR15_TINT86_SHIFT (22u)
+#define INTC_ICDABR15_TINT87_SHIFT (23u)
+#define INTC_ICDABR15_TINT88_SHIFT (24u)
+#define INTC_ICDABR15_TINT89_SHIFT (25u)
+#define INTC_ICDABR15_TINT90_SHIFT (26u)
+#define INTC_ICDABR15_TINT91_SHIFT (27u)
+#define INTC_ICDABR15_TINT92_SHIFT (28u)
+#define INTC_ICDABR15_TINT93_SHIFT (29u)
+#define INTC_ICDABR15_TINT94_SHIFT (30u)
+#define INTC_ICDABR15_TINT95_SHIFT (31u)
+
+#define INTC_ICDABR16_TINT96_SHIFT (0u)
+#define INTC_ICDABR16_TINT97_SHIFT (1u)
+#define INTC_ICDABR16_TINT98_SHIFT (2u)
+#define INTC_ICDABR16_TINT99_SHIFT (3u)
+#define INTC_ICDABR16_TINT100_SHIFT (4u)
+#define INTC_ICDABR16_TINT101_SHIFT (5u)
+#define INTC_ICDABR16_TINT102_SHIFT (6u)
+#define INTC_ICDABR16_TINT103_SHIFT (7u)
+#define INTC_ICDABR16_TINT104_SHIFT (8u)
+#define INTC_ICDABR16_TINT105_SHIFT (9u)
+#define INTC_ICDABR16_TINT106_SHIFT (10u)
+#define INTC_ICDABR16_TINT107_SHIFT (11u)
+#define INTC_ICDABR16_TINT108_SHIFT (12u)
+#define INTC_ICDABR16_TINT109_SHIFT (13u)
+#define INTC_ICDABR16_TINT110_SHIFT (14u)
+#define INTC_ICDABR16_TINT111_SHIFT (15u)
+#define INTC_ICDABR16_TINT112_SHIFT (16u)
+#define INTC_ICDABR16_TINT113_SHIFT (17u)
+#define INTC_ICDABR16_TINT114_SHIFT (18u)
+#define INTC_ICDABR16_TINT115_SHIFT (19u)
+#define INTC_ICDABR16_TINT116_SHIFT (20u)
+#define INTC_ICDABR16_TINT117_SHIFT (21u)
+#define INTC_ICDABR16_TINT118_SHIFT (22u)
+#define INTC_ICDABR16_TINT119_SHIFT (23u)
+#define INTC_ICDABR16_TINT120_SHIFT (24u)
+#define INTC_ICDABR16_TINT121_SHIFT (25u)
+#define INTC_ICDABR16_TINT122_SHIFT (26u)
+#define INTC_ICDABR16_TINT123_SHIFT (27u)
+#define INTC_ICDABR16_TINT124_SHIFT (28u)
+#define INTC_ICDABR16_TINT125_SHIFT (29u)
+#define INTC_ICDABR16_TINT126_SHIFT (30u)
+#define INTC_ICDABR16_TINT127_SHIFT (31u)
+
+#define INTC_ICDABR17_TINT128_SHIFT (0u)
+#define INTC_ICDABR17_TINT129_SHIFT (1u)
+#define INTC_ICDABR17_TINT130_SHIFT (2u)
+#define INTC_ICDABR17_TINT131_SHIFT (3u)
+#define INTC_ICDABR17_TINT132_SHIFT (4u)
+#define INTC_ICDABR17_TINT133_SHIFT (5u)
+#define INTC_ICDABR17_TINT134_SHIFT (6u)
+#define INTC_ICDABR17_TINT135_SHIFT (7u)
+#define INTC_ICDABR17_TINT136_SHIFT (8u)
+#define INTC_ICDABR17_TINT137_SHIFT (9u)
+#define INTC_ICDABR17_TINT138_SHIFT (10u)
+#define INTC_ICDABR17_TINT139_SHIFT (11u)
+#define INTC_ICDABR17_TINT140_SHIFT (12u)
+#define INTC_ICDABR17_TINT141_SHIFT (13u)
+#define INTC_ICDABR17_TINT142_SHIFT (14u)
+#define INTC_ICDABR17_TINT143_SHIFT (15u)
+#define INTC_ICDABR17_TINT144_SHIFT (16u)
+#define INTC_ICDABR17_TINT145_SHIFT (17u)
+#define INTC_ICDABR17_TINT146_SHIFT (18u)
+#define INTC_ICDABR17_TINT147_SHIFT (19u)
+#define INTC_ICDABR17_TINT148_SHIFT (20u)
+#define INTC_ICDABR17_TINT149_SHIFT (21u)
+#define INTC_ICDABR17_TINT150_SHIFT (22u)
+#define INTC_ICDABR17_TINT151_SHIFT (23u)
+#define INTC_ICDABR17_TINT152_SHIFT (24u)
+#define INTC_ICDABR17_TINT153_SHIFT (25u)
+#define INTC_ICDABR17_TINT154_SHIFT (26u)
+#define INTC_ICDABR17_TINT155_SHIFT (27u)
+#define INTC_ICDABR17_TINT156_SHIFT (28u)
+#define INTC_ICDABR17_TINT157_SHIFT (29u)
+#define INTC_ICDABR17_TINT158_SHIFT (30u)
+#define INTC_ICDABR17_TINT159_SHIFT (31u)
+
+#define INTC_ICDABR18_TINT160_SHIFT (0u)
+#define INTC_ICDABR18_TINT161_SHIFT (1u)
+#define INTC_ICDABR18_TINT162_SHIFT (2u)
+#define INTC_ICDABR18_TINT163_SHIFT (3u)
+#define INTC_ICDABR18_TINT164_SHIFT (4u)
+#define INTC_ICDABR18_TINT165_SHIFT (5u)
+#define INTC_ICDABR18_TINT166_SHIFT (6u)
+#define INTC_ICDABR18_TINT167_SHIFT (7u)
+#define INTC_ICDABR18_TINT168_SHIFT (8u)
+#define INTC_ICDABR18_TINT169_SHIFT (9u)
+#define INTC_ICDABR18_TINT170_SHIFT (10u)
+
+#define INTC_ICDIPR0_SW0_SHIFT (0u)
+#define INTC_ICDIPR0_SW1_SHIFT (8u)
+#define INTC_ICDIPR0_SW2_SHIFT (16u)
+#define INTC_ICDIPR0_SW3_SHIFT (24u)
+
+#define INTC_ICDIPR1_SW4_SHIFT (0u)
+#define INTC_ICDIPR1_SW5_SHIFT (8u)
+#define INTC_ICDIPR1_SW6_SHIFT (16u)
+#define INTC_ICDIPR1_SW7_SHIFT (24u)
+
+#define INTC_ICDIPR2_SW8_SHIFT (0u)
+#define INTC_ICDIPR2_SW9_SHIFT (8u)
+#define INTC_ICDIPR2_SW10_SHIFT (16u)
+#define INTC_ICDIPR2_SW11_SHIFT (24u)
+
+#define INTC_ICDIPR3_SW12_SHIFT (0u)
+#define INTC_ICDIPR3_SW13_SHIFT (8u)
+#define INTC_ICDIPR3_SW14_SHIFT (16u)
+#define INTC_ICDIPR3_SW15_SHIFT (24u)
+
+#define INTC_ICDIPR4_PMUIRQ0_SHIFT (0u)
+#define INTC_ICDIPR4_COMMRX0_SHIFT (8u)
+#define INTC_ICDIPR4_COMMTX0_SHIFT (16u)
+#define INTC_ICDIPR4_CTIIRQ0_SHIFT (24u)
+
+#define INTC_ICDIPR8_IRQ0_SHIFT (0u)
+#define INTC_ICDIPR8_IRQ1_SHIFT (8u)
+#define INTC_ICDIPR8_IRQ2_SHIFT (16u)
+#define INTC_ICDIPR8_IRQ3_SHIFT (24u)
+
+#define INTC_ICDIPR9_IRQ4_SHIFT (0u)
+#define INTC_ICDIPR9_IRQ5_SHIFT (8u)
+#define INTC_ICDIPR9_IRQ6_SHIFT (16u)
+#define INTC_ICDIPR9_IRQ7_SHIFT (24u)
+
+#define INTC_ICDIPR10_PL310ERR_SHIFT (0u)
+#define INTC_ICDIPR10_DMAINT0_SHIFT (8u)
+#define INTC_ICDIPR10_DMAINT1_SHIFT (16u)
+#define INTC_ICDIPR10_DMAINT2_SHIFT (24u)
+
+#define INTC_ICDIPR11_DMAINT3_SHIFT (0u)
+#define INTC_ICDIPR11_DMAINT4_SHIFT (8u)
+#define INTC_ICDIPR11_DMAINT5_SHIFT (16u)
+#define INTC_ICDIPR11_DMAINT6_SHIFT (24u)
+
+#define INTC_ICDIPR12_DMAINT7_SHIFT (0u)
+#define INTC_ICDIPR12_DMAINT8_SHIFT (8u)
+#define INTC_ICDIPR12_DMAINT9_SHIFT (16u)
+#define INTC_ICDIPR12_DMAINT10_SHIFT (24u)
+
+#define INTC_ICDIPR13_DMAINT11_SHIFT (0u)
+#define INTC_ICDIPR13_DMAINT12_SHIFT (8u)
+#define INTC_ICDIPR13_DMAINT13_SHIFT (16u)
+#define INTC_ICDIPR13_DMAINT14_SHIFT (24u)
+
+#define INTC_ICDIPR14_DMAINT15_SHIFT (0u)
+#define INTC_ICDIPR14_DMAERR_SHIFT (8u)
+
+#define INTC_ICDIPR18_USBI0_SHIFT (8u)
+#define INTC_ICDIPR18_USBI1_SHIFT (16u)
+#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT (24u)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT (0u)
+#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT (8u)
+#define INTC_ICDIPR19_GR3_VLINE0_SHIFT (16u)
+#define INTC_ICDIPR19_S0_VFIELD0_SHIFT (24u)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT (0u)
+#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT (16u)
+#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT (24u)
+
+#define INTC_ICDIPR21_S0_WLINE0_SHIFT (0u)
+#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT (8u)
+#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT (16u)
+#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT (24u)
+
+#define INTC_ICDIPR22_S1_VFIELD0_SHIFT (0u)
+#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT (16u)
+#define INTC_ICDIPR22_S1_WLINE0_SHIFT (24u)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT (0u)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT (8u)
+#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT (16u)
+#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT (24u)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT (24u)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT (0u)
+#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT (8u)
+#define INTC_ICDIPR25_GR3_VLINE1_SHIFT (16u)
+#define INTC_ICDIPR25_S0_VFIELD1_SHIFT (24u)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT (0u)
+#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT (16u)
+#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT (24u)
+
+#define INTC_ICDIPR27_S0_WLINE1_SHIFT (0u)
+#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT (8u)
+#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT (16u)
+#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT (24u)
+
+#define INTC_ICDIPR28_S1_VFIELD1_SHIFT (0u)
+#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT (16u)
+#define INTC_ICDIPR28_S1_WLINE1_SHIFT (24u)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT (0u)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT (8u)
+#define INTC_ICDIPR29_OIR_VLINE1_SHIFT (16u)
+#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT (24u)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT (0u)
+#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPR30_IMRDI_SHIFT (24u)
+
+#define INTC_ICDIPR31_IMR2I0_SHIFT (0u)
+#define INTC_ICDIPR31_IMR2I1_SHIFT (8u)
+#define INTC_ICDIPR31_JEDI_SHIFT (16u)
+#define INTC_ICDIPR31_JDTI_SHIFT (24u)
+
+#define INTC_ICDIPR32_CMP0_SHIFT (0u)
+#define INTC_ICDIPR32_CMP1_SHIFT (8u)
+#define INTC_ICDIPR32_INT0_SHIFT (16u)
+#define INTC_ICDIPR32_INT1_SHIFT (24u)
+
+#define INTC_ICDIPR33_INT2_SHIFT (0u)
+#define INTC_ICDIPR33_INT3_SHIFT (8u)
+#define INTC_ICDIPR33_OSTM0TINT_SHIFT (16u)
+#define INTC_ICDIPR33_OSTM1TINT_SHIFT (24u)
+
+#define INTC_ICDIPR34_CMI_SHIFT (0u)
+#define INTC_ICDIPR34_WTOUT_SHIFT (8u)
+#define INTC_ICDIPR34_ITI_SHIFT (16u)
+#define INTC_ICDIPR34_TGI0A_SHIFT (24u)
+
+#define INTC_ICDIPR35_TGI0B_SHIFT (0u)
+#define INTC_ICDIPR35_TGI0C_SHIFT (8u)
+#define INTC_ICDIPR35_TGI0D_SHIFT (16u)
+#define INTC_ICDIPR35_TGI0V_SHIFT (24u)
+
+#define INTC_ICDIPR36_TGI0E_SHIFT (0u)
+#define INTC_ICDIPR36_TGI0F_SHIFT (8u)
+#define INTC_ICDIPR36_TGI1A_SHIFT (16u)
+#define INTC_ICDIPR36_TGI1B_SHIFT (24u)
+
+#define INTC_ICDIPR37_TGI1V_SHIFT (0u)
+#define INTC_ICDIPR37_TGI1U_SHIFT (8u)
+#define INTC_ICDIPR37_TGI2A_SHIFT (16u)
+#define INTC_ICDIPR37_TGI2B_SHIFT (24u)
+
+#define INTC_ICDIPR38_TGI2V_SHIFT (0u)
+#define INTC_ICDIPR38_TGI2U_SHIFT (8u)
+#define INTC_ICDIPR38_TGI3A_SHIFT (16u)
+#define INTC_ICDIPR38_TGI3B_SHIFT (24u)
+
+#define INTC_ICDIPR39_TGI3C_SHIFT (0u)
+#define INTC_ICDIPR39_TGI3D_SHIFT (8u)
+#define INTC_ICDIPR39_TGI3V_SHIFT (16u)
+#define INTC_ICDIPR39_TGI4A_SHIFT (24u)
+
+#define INTC_ICDIPR40_TGI4B_SHIFT (0u)
+#define INTC_ICDIPR40_TGI4C_SHIFT (8u)
+#define INTC_ICDIPR40_TGI4D_SHIFT (16u)
+#define INTC_ICDIPR40_TGI4V_SHIFT (24u)
+
+#define INTC_ICDIPR41_CMI1_SHIFT (0u)
+#define INTC_ICDIPR41_CMI2_SHIFT (8u)
+#define INTC_ICDIPR41_SGDEI0_SHIFT (16u)
+#define INTC_ICDIPR41_SGDEI1_SHIFT (24u)
+
+#define INTC_ICDIPR42_SGDEI2_SHIFT (0u)
+#define INTC_ICDIPR42_SGDEI3_SHIFT (8u)
+#define INTC_ICDIPR42_ADI_SHIFT (16u)
+#define INTC_ICDIPR42_LMTI_SHIFT (24u)
+
+#define INTC_ICDIPR43_SSII0_SHIFT (0u)
+#define INTC_ICDIPR43_SSIRXI0_SHIFT (8u)
+#define INTC_ICDIPR43_SSITXI0_SHIFT (16u)
+#define INTC_ICDIPR43_SSII1_SHIFT (24u)
+
+#define INTC_ICDIPR44_SSIRXI1_SHIFT (0u)
+#define INTC_ICDIPR44_SSITXI1_SHIFT (8u)
+#define INTC_ICDIPR44_SSII2_SHIFT (16u)
+#define INTC_ICDIPR44_SSIRTI2_SHIFT (24u)
+
+#define INTC_ICDIPR45_SSII3_SHIFT (0u)
+#define INTC_ICDIPR45_SSIRXI3_SHIFT (8u)
+#define INTC_ICDIPR45_SSITXI3_SHIFT (16u)
+#define INTC_ICDIPR45_SSII4_SHIFT (24u)
+
+#define INTC_ICDIPR46_SSIRTI4_SHIFT (0u)
+#define INTC_ICDIPR46_SSII5_SHIFT (8u)
+#define INTC_ICDIPR46_SSIRXI5_SHIFT (16u)
+#define INTC_ICDIPR46_SSITXI5_SHIFT (24u)
+
+#define INTC_ICDIPR47_SPDIFI_SHIFT (0u)
+#define INTC_ICDIPR47_INTIICTEI0_SHIFT (8u)
+#define INTC_ICDIPR47_INTIICRI0_SHIFT (16u)
+#define INTC_ICDIPR47_INTIICTI0_SHIFT (24u)
+
+#define INTC_ICDIPR48_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDIPR48_INTIICSTI0_SHIFT (8u)
+#define INTC_ICDIPR48_INTIICNAKI0_SHIFT (16u)
+#define INTC_ICDIPR48_INTIICALI0_SHIFT (24u)
+
+#define INTC_ICDIPR49_INTIICTMOI0_SHIFT (0u)
+#define INTC_ICDIPR49_INTIICTEI1_SHIFT (8u)
+#define INTC_ICDIPR49_INTIICRI1_SHIFT (16u)
+#define INTC_ICDIPR49_INTIICTI1_SHIFT (24u)
+
+#define INTC_ICDIPR50_INTIICSPI1_SHIFT (0u)
+#define INTC_ICDIPR50_INTIICSTI1_SHIFT (8u)
+#define INTC_ICDIPR50_INTIICNAKI1_SHIFT (16u)
+#define INTC_ICDIPR50_INTIICALI1_SHIFT (24u)
+
+#define INTC_ICDIPR51_INTIICTMOI1_SHIFT (0u)
+#define INTC_ICDIPR51_INTIICTEI2_SHIFT (8u)
+#define INTC_ICDIPR51_INTIICRI2_SHIFT (16u)
+#define INTC_ICDIPR51_INTIICTI2_SHIFT (24u)
+
+#define INTC_ICDIPR52_INTIICSPI2_SHIFT (0u)
+#define INTC_ICDIPR52_INTIICSTI2_SHIFT (8u)
+#define INTC_ICDIPR52_INTIICNAKI2_SHIFT (16u)
+#define INTC_ICDIPR52_INTIICALI2_SHIFT (24u)
+
+#define INTC_ICDIPR53_INTIICTMOI2_SHIFT (0u)
+#define INTC_ICDIPR53_INTIICTEI3_SHIFT (8u)
+#define INTC_ICDIPR53_INTIICRI3_SHIFT (16u)
+#define INTC_ICDIPR53_INTIICTI3_SHIFT (24u)
+
+#define INTC_ICDIPR54_INTIICSPI3_SHIFT (0u)
+#define INTC_ICDIPR54_INTIICSTI3_SHIFT (8u)
+#define INTC_ICDIPR54_INTIICNAKI3_SHIFT (16u)
+#define INTC_ICDIPR54_INTIICALI3_SHIFT (24u)
+
+#define INTC_ICDIPR55_INTIICTMOI3_SHIFT (0u)
+#define INTC_ICDIPR55_BRI0_SHIFT (8u)
+#define INTC_ICDIPR55_ERI0_SHIFT (16u)
+#define INTC_ICDIPR55_RXI0_SHIFT (24u)
+
+#define INTC_ICDIPR56_TXI0_SHIFT (0u)
+#define INTC_ICDIPR56_BRI1_SHIFT (8u)
+#define INTC_ICDIPR56_ERI1_SHIFT (16u)
+#define INTC_ICDIPR56_RXI1_SHIFT (24u)
+
+#define INTC_ICDIPR57_TXI1_SHIFT (0u)
+#define INTC_ICDIPR57_BRI2_SHIFT (8u)
+#define INTC_ICDIPR57_ERI2_SHIFT (16u)
+#define INTC_ICDIPR57_RXI2_SHIFT (24u)
+
+#define INTC_ICDIPR58_TXI2_SHIFT (0u)
+#define INTC_ICDIPR58_BRI3_SHIFT (8u)
+#define INTC_ICDIPR58_ERI3_SHIFT (16u)
+#define INTC_ICDIPR58_RXI3_SHIFT (24u)
+
+#define INTC_ICDIPR59_TXI3_SHIFT (0u)
+#define INTC_ICDIPR59_BRI4_SHIFT (8u)
+#define INTC_ICDIPR59_ERI4_SHIFT (16u)
+#define INTC_ICDIPR59_RXI4_SHIFT (24u)
+
+#define INTC_ICDIPR60_TXI4_SHIFT (0u)
+#define INTC_ICDIPR60_BRI5_SHIFT (8u)
+#define INTC_ICDIPR60_ERI5_SHIFT (16u)
+#define INTC_ICDIPR60_RXI5_SHIFT (24u)
+
+#define INTC_ICDIPR61_TXI5_SHIFT (0u)
+#define INTC_ICDIPR61_BRI6_SHIFT (8u)
+#define INTC_ICDIPR61_ERI6_SHIFT (16u)
+#define INTC_ICDIPR61_RXI6_SHIFT (24u)
+
+#define INTC_ICDIPR62_TXI6_SHIFT (0u)
+#define INTC_ICDIPR62_BRI7_SHIFT (8u)
+#define INTC_ICDIPR62_ERI7_SHIFT (16u)
+#define INTC_ICDIPR62_RXI7_SHIFT (24u)
+
+#define INTC_ICDIPR63_TXI7_SHIFT (0u)
+#define INTC_ICDIPR63_INTRCANGERR_SHIFT (8u)
+#define INTC_ICDIPR63_INTRCANGRECC_SHIFT (16u)
+#define INTC_ICDIPR63_INTRCAN0REC_SHIFT (24u)
+
+#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT (8u)
+#define INTC_ICDIPR64_INTRCAN1REC_SHIFT (16u)
+#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT (24u)
+
+#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT (0u)
+#define INTC_ICDIPR65_INTRCAN2REC_SHIFT (8u)
+#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT (16u)
+#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT (24u)
+
+#define INTC_ICDIPR66_INTRCAN3REC_SHIFT (0u)
+#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT (8u)
+#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT (16u)
+#define INTC_ICDIPR66_INTRCAN4REC_SHIFT (24u)
+
+#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT (0u)
+#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT (8u)
+#define INTC_ICDIPR67_SPEI0_SHIFT (16u)
+#define INTC_ICDIPR67_SPRI0_SHIFT (24u)
+
+#define INTC_ICDIPR68_SPTI0_SHIFT (0u)
+#define INTC_ICDIPR68_SPEI1_SHIFT (8u)
+#define INTC_ICDIPR68_SPRI1_SHIFT (16u)
+#define INTC_ICDIPR68_SPTI1_SHIFT (24u)
+
+#define INTC_ICDIPR69_SPEI2_SHIFT (0u)
+#define INTC_ICDIPR69_SPRI2_SHIFT (8u)
+#define INTC_ICDIPR69_SPTI2_SHIFT (16u)
+#define INTC_ICDIPR69_SPEI3_SHIFT (24u)
+
+#define INTC_ICDIPR70_SPRI3_SHIFT (0u)
+#define INTC_ICDIPR70_SPTI3_SHIFT (8u)
+#define INTC_ICDIPR70_SPEI4_SHIFT (16u)
+#define INTC_ICDIPR70_SPRI4_SHIFT (24u)
+
+#define INTC_ICDIPR71_SPTI4_SHIFT (0u)
+#define INTC_ICDIPR71_IEBBTD_SHIFT (8u)
+#define INTC_ICDIPR71_IEBBTERR_SHIFT (16u)
+#define INTC_ICDIPR71_IEBBTSTA_SHIFT (24u)
+
+#define INTC_ICDIPR72_IEBBTV_SHIFT (0u)
+#define INTC_ICDIPR72_ISY_SHIFT (8u)
+#define INTC_ICDIPR72_IERR_SHIFT (16u)
+#define INTC_ICDIPR72_ITARG_SHIFT (24u)
+
+#define INTC_ICDIPR73_ISEC_SHIFT (0u)
+#define INTC_ICDIPR73_IBUF_SHIFT (8u)
+#define INTC_ICDIPR73_IREADY_SHIFT (16u)
+#define INTC_ICDIPR73_FLSTE_SHIFT (24u)
+
+#define INTC_ICDIPR74_FLTENDI_SHIFT (0u)
+#define INTC_ICDIPR74_FLTREQ0I_SHIFT (8u)
+#define INTC_ICDIPR74_FLTREQ1I_SHIFT (16u)
+#define INTC_ICDIPR74_MMC0_SHIFT (24u)
+
+#define INTC_ICDIPR75_MMC1_SHIFT (0u)
+#define INTC_ICDIPR75_MMC2_SHIFT (8u)
+#define INTC_ICDIPR75_SDHI0_3_SHIFT (16u)
+#define INTC_ICDIPR75_SDHI0_0_SHIFT (24u)
+
+#define INTC_ICDIPR76_SDHI0_1_SHIFT (0u)
+#define INTC_ICDIPR76_SDHI1_3_SHIFT (8u)
+#define INTC_ICDIPR76_SDHI1_0_SHIFT (16u)
+#define INTC_ICDIPR76_SDHI1_1_SHIFT (24u)
+
+#define INTC_ICDIPR77_ARM_SHIFT (0u)
+#define INTC_ICDIPR77_PRD_SHIFT (8u)
+#define INTC_ICDIPR77_CUP_SHIFT (16u)
+#define INTC_ICDIPR77_SCUAI0_SHIFT (24u)
+
+#define INTC_ICDIPR78_SCUAI1_SHIFT (0u)
+#define INTC_ICDIPR78_SCUFDI0_SHIFT (8u)
+#define INTC_ICDIPR78_SCUFDI1_SHIFT (16u)
+#define INTC_ICDIPR78_SCUFDI2_SHIFT (24u)
+
+#define INTC_ICDIPR79_SCUFDI3_SHIFT (0u)
+#define INTC_ICDIPR79_SCUFUI0_SHIFT (8u)
+#define INTC_ICDIPR79_SCUFUI1_SHIFT (16u)
+#define INTC_ICDIPR79_SCUFUI2_SHIFT (24u)
+
+#define INTC_ICDIPR80_SCUFUI3_SHIFT (0u)
+#define INTC_ICDIPR80_SCUDVI0_SHIFT (8u)
+#define INTC_ICDIPR80_SCUDVI1_SHIFT (16u)
+#define INTC_ICDIPR80_SCUDVI2_SHIFT (24u)
+
+#define INTC_ICDIPR81_SCUDVI3_SHIFT (0u)
+#define INTC_ICDIPR81_MLB_CINT_SHIFT (8u)
+#define INTC_ICDIPR81_MLB_SINT_SHIFT (16u)
+#define INTC_ICDIPR81_DRC0_SHIFT (24u)
+
+#define INTC_ICDIPR82_DRC1_SHIFT (0u)
+#define INTC_ICDIPR82_LINI0_INT_T_SHIFT (24u)
+
+#define INTC_ICDIPR83_LINI0_INT_R_SHIFT (0u)
+#define INTC_ICDIPR83_LINI0_INT_S_SHIFT (8u)
+#define INTC_ICDIPR83_LINI0_INT_M_SHIFT (16u)
+#define INTC_ICDIPR83_LINI1_INT_T_SHIFT (24u)
+
+#define INTC_ICDIPR84_LINI1_INT_R_SHIFT (0u)
+#define INTC_ICDIPR84_LINI1_INT_S_SHIFT (8u)
+#define INTC_ICDIPR84_LINI1_INT_M_SHIFT (16u)
+
+#define INTC_ICDIPR86_ERI0_SHIFT (24u)
+
+#define INTC_ICDIPR87_RXI0_SHIFT (0u)
+#define INTC_ICDIPR87_TXI0_SHIFT (8u)
+#define INTC_ICDIPR87_TEI0_SHIFT (16u)
+#define INTC_ICDIPR87_ERI1_SHIFT (24u)
+
+#define INTC_ICDIPR88_RXI1_SHIFT (0u)
+#define INTC_ICDIPR88_TXI1_SHIFT (8u)
+#define INTC_ICDIPR88_TEI1_SHIFT (16u)
+#define INTC_ICDIPR88_AVBI_DATA_SHIFT (24u)
+
+#define INTC_ICDIPR89_AVBI_ERROR_SHIFT (0u)
+#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT (8u)
+#define INTC_ICDIPR89_AVBI_MAC_SHIFT (16u)
+#define INTC_ICDIPR89_ETHERI_SHIFT (24u)
+
+#define INTC_ICDIPR91_CEUI_SHIFT (0u)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT (8u)
+#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT (16u)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT (8u)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT (16u)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT (0u)
+#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT (8u)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT (16u)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPR98_PRRI_SHIFT (0u)
+#define INTC_ICDIPR98_IFEI0_SHIFT (8u)
+#define INTC_ICDIPR98_OFFI0_SHIFT (16u)
+#define INTC_ICDIPR98_PFVEI0_SHIFT (24u)
+
+#define INTC_ICDIPR99_IFEI1_SHIFT (0u)
+#define INTC_ICDIPR99_OFFI1_SHIFT (8u)
+#define INTC_ICDIPR99_PFVEI1_SHIFT (16u)
+
+#define INTC_ICDIPR104_TINT0_SHIFT (0u)
+#define INTC_ICDIPR104_TINT1_SHIFT (8u)
+#define INTC_ICDIPR104_TINT2_SHIFT (16u)
+#define INTC_ICDIPR104_TINT3_SHIFT (24u)
+
+#define INTC_ICDIPR105_TINT4_SHIFT (0u)
+#define INTC_ICDIPR105_TINT5_SHIFT (8u)
+#define INTC_ICDIPR105_TINT6_SHIFT (16u)
+#define INTC_ICDIPR105_TINT7_SHIFT (24u)
+
+#define INTC_ICDIPR106_TINT8_SHIFT (0u)
+#define INTC_ICDIPR106_TINT9_SHIFT (8u)
+#define INTC_ICDIPR106_TINT10_SHIFT (16u)
+#define INTC_ICDIPR106_TINT11_SHIFT (24u)
+
+#define INTC_ICDIPR107_TINT12_SHIFT (0u)
+#define INTC_ICDIPR107_TINT13_SHIFT (8u)
+#define INTC_ICDIPR107_TINT14_SHIFT (16u)
+#define INTC_ICDIPR107_TINT15_SHIFT (24u)
+
+#define INTC_ICDIPR108_TINT16_SHIFT (0u)
+#define INTC_ICDIPR108_TINT17_SHIFT (8u)
+#define INTC_ICDIPR108_TINT18_SHIFT (16u)
+#define INTC_ICDIPR108_TINT19_SHIFT (24u)
+
+#define INTC_ICDIPR109_TINT20_SHIFT (0u)
+#define INTC_ICDIPR109_TINT21_SHIFT (8u)
+#define INTC_ICDIPR109_TINT22_SHIFT (16u)
+#define INTC_ICDIPR109_TINT23_SHIFT (24u)
+
+#define INTC_ICDIPR110_TINT24_SHIFT (0u)
+#define INTC_ICDIPR110_TINT25_SHIFT (8u)
+#define INTC_ICDIPR110_TINT26_SHIFT (16u)
+#define INTC_ICDIPR110_TINT27_SHIFT (24u)
+
+#define INTC_ICDIPR111_TINT28_SHIFT (0u)
+#define INTC_ICDIPR111_TINT29_SHIFT (8u)
+#define INTC_ICDIPR111_TINT30_SHIFT (16u)
+#define INTC_ICDIPR111_TINT31_SHIFT (24u)
+
+#define INTC_ICDIPR112_TINT32_SHIFT (0u)
+#define INTC_ICDIPR112_TINT33_SHIFT (8u)
+#define INTC_ICDIPR112_TINT34_SHIFT (16u)
+#define INTC_ICDIPR112_TINT35_SHIFT (24u)
+
+#define INTC_ICDIPR113_TINT36_SHIFT (0u)
+#define INTC_ICDIPR113_TINT37_SHIFT (8u)
+#define INTC_ICDIPR113_TINT38_SHIFT (16u)
+#define INTC_ICDIPR113_TINT39_SHIFT (24u)
+
+#define INTC_ICDIPR114_TINT40_SHIFT (0u)
+#define INTC_ICDIPR114_TINT41_SHIFT (8u)
+#define INTC_ICDIPR114_TINT42_SHIFT (16u)
+#define INTC_ICDIPR114_TINT43_SHIFT (24u)
+
+#define INTC_ICDIPR115_TINT44_SHIFT (0u)
+#define INTC_ICDIPR115_TINT45_SHIFT (8u)
+#define INTC_ICDIPR115_TINT46_SHIFT (16u)
+#define INTC_ICDIPR115_TINT47_SHIFT (24u)
+
+#define INTC_ICDIPR116_TINT48_SHIFT (0u)
+#define INTC_ICDIPR116_TINT49_SHIFT (8u)
+#define INTC_ICDIPR116_TINT50_SHIFT (16u)
+#define INTC_ICDIPR116_TINT51_SHIFT (24u)
+
+#define INTC_ICDIPR117_TINT52_SHIFT (0u)
+#define INTC_ICDIPR117_TINT53_SHIFT (8u)
+#define INTC_ICDIPR117_TINT54_SHIFT (16u)
+#define INTC_ICDIPR117_TINT55_SHIFT (24u)
+
+#define INTC_ICDIPR118_TINT56_SHIFT (0u)
+#define INTC_ICDIPR118_TINT57_SHIFT (8u)
+#define INTC_ICDIPR118_TINT58_SHIFT (16u)
+#define INTC_ICDIPR118_TINT59_SHIFT (24u)
+
+#define INTC_ICDIPR119_TINT60_SHIFT (0u)
+#define INTC_ICDIPR119_TINT61_SHIFT (8u)
+#define INTC_ICDIPR119_TINT62_SHIFT (16u)
+#define INTC_ICDIPR119_TINT63_SHIFT (24u)
+
+#define INTC_ICDIPR120_TINT64_SHIFT (0u)
+#define INTC_ICDIPR120_TINT65_SHIFT (8u)
+#define INTC_ICDIPR120_TINT66_SHIFT (16u)
+#define INTC_ICDIPR120_TINT67_SHIFT (24u)
+
+#define INTC_ICDIPR121_TINT68_SHIFT (0u)
+#define INTC_ICDIPR121_TINT69_SHIFT (8u)
+#define INTC_ICDIPR121_TINT70_SHIFT (16u)
+#define INTC_ICDIPR121_TINT71_SHIFT (24u)
+
+#define INTC_ICDIPR122_TINT72_SHIFT (0u)
+#define INTC_ICDIPR122_TINT73_SHIFT (8u)
+#define INTC_ICDIPR122_TINT74_SHIFT (16u)
+#define INTC_ICDIPR122_TINT75_SHIFT (24u)
+
+#define INTC_ICDIPR123_TINT76_SHIFT (0u)
+#define INTC_ICDIPR123_TINT77_SHIFT (8u)
+#define INTC_ICDIPR123_TINT78_SHIFT (16u)
+#define INTC_ICDIPR123_TINT79_SHIFT (24u)
+
+#define INTC_ICDIPR124_TINT80_SHIFT (0u)
+#define INTC_ICDIPR124_TINT81_SHIFT (8u)
+#define INTC_ICDIPR124_TINT82_SHIFT (16u)
+#define INTC_ICDIPR124_TINT83_SHIFT (24u)
+
+#define INTC_ICDIPR125_TINT84_SHIFT (0u)
+#define INTC_ICDIPR125_TINT85_SHIFT (8u)
+#define INTC_ICDIPR125_TINT86_SHIFT (16u)
+#define INTC_ICDIPR125_TINT87_SHIFT (24u)
+
+#define INTC_ICDIPR126_TINT88_SHIFT (0u)
+#define INTC_ICDIPR126_TINT89_SHIFT (8u)
+#define INTC_ICDIPR126_TINT90_SHIFT (16u)
+#define INTC_ICDIPR126_TINT91_SHIFT (24u)
+
+#define INTC_ICDIPR127_TINT92_SHIFT (0u)
+#define INTC_ICDIPR127_TINT93_SHIFT (8u)
+#define INTC_ICDIPR127_TINT94_SHIFT (16u)
+#define INTC_ICDIPR127_TINT95_SHIFT (24u)
+
+#define INTC_ICDIPR128_TINT96_SHIFT (0u)
+#define INTC_ICDIPR128_TINT97_SHIFT (8u)
+#define INTC_ICDIPR128_TINT98_SHIFT (16u)
+#define INTC_ICDIPR128_TINT99_SHIFT (24u)
+
+#define INTC_ICDIPR129_TINT100_SHIFT (0u)
+#define INTC_ICDIPR129_TINT101_SHIFT (8u)
+#define INTC_ICDIPR129_TINT102_SHIFT (16u)
+#define INTC_ICDIPR129_TINT103_SHIFT (24u)
+
+#define INTC_ICDIPR130_TINT104_SHIFT (0u)
+#define INTC_ICDIPR130_TINT105_SHIFT (8u)
+#define INTC_ICDIPR130_TINT106_SHIFT (16u)
+#define INTC_ICDIPR130_TINT107_SHIFT (24u)
+
+#define INTC_ICDIPR131_TINT108_SHIFT (0u)
+#define INTC_ICDIPR131_TINT109_SHIFT (8u)
+#define INTC_ICDIPR131_TINT110_SHIFT (16u)
+#define INTC_ICDIPR131_TINT111_SHIFT (24u)
+
+#define INTC_ICDIPR132_TINT112_SHIFT (0u)
+#define INTC_ICDIPR132_TINT113_SHIFT (8u)
+#define INTC_ICDIPR132_TINT114_SHIFT (16u)
+#define INTC_ICDIPR132_TINT115_SHIFT (24u)
+
+#define INTC_ICDIPR133_TINT116_SHIFT (0u)
+#define INTC_ICDIPR133_TINT117_SHIFT (8u)
+#define INTC_ICDIPR133_TINT118_SHIFT (16u)
+#define INTC_ICDIPR133_TINT119_SHIFT (24u)
+
+#define INTC_ICDIPR134_TINT120_SHIFT (0u)
+#define INTC_ICDIPR134_TINT121_SHIFT (8u)
+#define INTC_ICDIPR134_TINT122_SHIFT (16u)
+#define INTC_ICDIPR134_TINT123_SHIFT (24u)
+
+#define INTC_ICDIPR135_TINT124_SHIFT (0u)
+#define INTC_ICDIPR135_TINT125_SHIFT (8u)
+#define INTC_ICDIPR135_TINT126_SHIFT (16u)
+#define INTC_ICDIPR135_TINT127_SHIFT (24u)
+
+#define INTC_ICDIPR136_TINT128_SHIFT (0u)
+#define INTC_ICDIPR136_TINT129_SHIFT (8u)
+#define INTC_ICDIPR136_TINT130_SHIFT (16u)
+#define INTC_ICDIPR136_TINT131_SHIFT (24u)
+
+#define INTC_ICDIPR137_TINT132_SHIFT (0u)
+#define INTC_ICDIPR137_TINT133_SHIFT (8u)
+#define INTC_ICDIPR137_TINT134_SHIFT (16u)
+#define INTC_ICDIPR137_TINT135_SHIFT (24u)
+
+#define INTC_ICDIPR138_TINT136_SHIFT (0u)
+#define INTC_ICDIPR138_TINT137_SHIFT (8u)
+#define INTC_ICDIPR138_TINT138_SHIFT (16u)
+#define INTC_ICDIPR138_TINT139_SHIFT (24u)
+
+#define INTC_ICDIPR139_TINT140_SHIFT (0u)
+#define INTC_ICDIPR139_TINT141_SHIFT (8u)
+#define INTC_ICDIPR139_TINT142_SHIFT (16u)
+#define INTC_ICDIPR139_TINT143_SHIFT (24u)
+
+#define INTC_ICDIPR140_TINT144_SHIFT (0u)
+#define INTC_ICDIPR140_TINT145_SHIFT (8u)
+#define INTC_ICDIPR140_TINT146_SHIFT (16u)
+#define INTC_ICDIPR140_TINT147_SHIFT (24u)
+
+#define INTC_ICDIPR141_TINT148_SHIFT (0u)
+#define INTC_ICDIPR141_TINT149_SHIFT (8u)
+#define INTC_ICDIPR141_TINT150_SHIFT (16u)
+#define INTC_ICDIPR141_TINT151_SHIFT (24u)
+
+#define INTC_ICDIPR142_TINT152_SHIFT (0u)
+#define INTC_ICDIPR142_TINT153_SHIFT (8u)
+#define INTC_ICDIPR142_TINT154_SHIFT (16u)
+#define INTC_ICDIPR142_TINT155_SHIFT (24u)
+
+#define INTC_ICDIPR143_TINT156_SHIFT (0u)
+#define INTC_ICDIPR143_TINT157_SHIFT (8u)
+#define INTC_ICDIPR143_TINT158_SHIFT (16u)
+#define INTC_ICDIPR143_TINT159_SHIFT (24u)
+
+#define INTC_ICDIPR144_TINT160_SHIFT (0u)
+#define INTC_ICDIPR144_TINT161_SHIFT (8u)
+#define INTC_ICDIPR144_TINT162_SHIFT (16u)
+#define INTC_ICDIPR144_TINT163_SHIFT (24u)
+
+#define INTC_ICDIPR145_TINT164_SHIFT (0u)
+#define INTC_ICDIPR145_TINT165_SHIFT (8u)
+#define INTC_ICDIPR145_TINT166_SHIFT (16u)
+#define INTC_ICDIPR145_TINT167_SHIFT (24u)
+
+#define INTC_ICDIPR146_TINT168_SHIFT (0u)
+#define INTC_ICDIPR146_TINT169_SHIFT (8u)
+#define INTC_ICDIPR146_TINT170_SHIFT (16u)
+
+#define INTC_ICDIPTR0_SW0_SHIFT (0u)
+#define INTC_ICDIPTR0_SW1_SHIFT (8u)
+#define INTC_ICDIPTR0_SW2_SHIFT (16u)
+#define INTC_ICDIPTR0_SW3_SHIFT (24u)
+
+#define INTC_ICDIPTR1_SW4_SHIFT (0u)
+#define INTC_ICDIPTR1_SW5_SHIFT (8u)
+#define INTC_ICDIPTR1_SW6_SHIFT (16u)
+#define INTC_ICDIPTR1_SW7_SHIFT (24u)
+
+#define INTC_ICDIPTR2_SW8_SHIFT (0u)
+#define INTC_ICDIPTR2_SW9_SHIFT (8u)
+#define INTC_ICDIPTR2_SW10_SHIFT (16u)
+#define INTC_ICDIPTR2_SW11_SHIFT (24u)
+
+#define INTC_ICDIPTR3_SW12_SHIFT (0u)
+#define INTC_ICDIPTR3_SW13_SHIFT (8u)
+#define INTC_ICDIPTR3_SW14_SHIFT (16u)
+#define INTC_ICDIPTR3_SW15_SHIFT (24u)
+
+#define INTC_ICDIPTR4_PMUIRQ0_SHIFT (0u)
+#define INTC_ICDIPTR4_COMMRX0_SHIFT (8u)
+#define INTC_ICDIPTR4_COMMTX0_SHIFT (16u)
+#define INTC_ICDIPTR4_CTIIRQ0_SHIFT (24u)
+
+#define INTC_ICDIPTR8_IRQ0_SHIFT (0u)
+#define INTC_ICDIPTR8_IRQ1_SHIFT (8u)
+#define INTC_ICDIPTR8_IRQ2_SHIFT (16u)
+#define INTC_ICDIPTR8_IRQ3_SHIFT (24u)
+
+#define INTC_ICDIPTR9_IRQ4_SHIFT (0u)
+#define INTC_ICDIPTR9_IRQ5_SHIFT (8u)
+#define INTC_ICDIPTR9_IRQ6_SHIFT (16u)
+#define INTC_ICDIPTR9_IRQ7_SHIFT (24u)
+
+#define INTC_ICDIPTR10_PL310ERR_SHIFT (0u)
+#define INTC_ICDIPTR10_DMAINT0_SHIFT (8u)
+#define INTC_ICDIPTR10_DMAINT1_SHIFT (16u)
+#define INTC_ICDIPTR10_DMAINT2_SHIFT (24u)
+
+#define INTC_ICDIPTR11_DMAINT3_SHIFT (0u)
+#define INTC_ICDIPTR11_DMAINT4_SHIFT (8u)
+#define INTC_ICDIPTR11_DMAINT5_SHIFT (16u)
+#define INTC_ICDIPTR11_DMAINT6_SHIFT (24u)
+
+#define INTC_ICDIPTR12_DMAINT7_SHIFT (0u)
+#define INTC_ICDIPTR12_DMAINT8_SHIFT (8u)
+#define INTC_ICDIPTR12_DMAINT9_SHIFT (16u)
+#define INTC_ICDIPTR12_DMAINT10_SHIFT (24u)
+
+#define INTC_ICDIPTR13_DMAINT11_SHIFT (0u)
+#define INTC_ICDIPTR13_DMAINT12_SHIFT (8u)
+#define INTC_ICDIPTR13_DMAINT13_SHIFT (16u)
+#define INTC_ICDIPTR13_DMAINT14_SHIFT (24u)
+
+#define INTC_ICDIPTR14_DMAINT15_SHIFT (0u)
+#define INTC_ICDIPTR14_DMAERR_SHIFT (8u)
+
+#define INTC_ICDIPTR18_USBI0_SHIFT (8u)
+#define INTC_ICDIPTR18_USBI1_SHIFT (16u)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT (24u)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT (0u)
+#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT (8u)
+#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT (16u)
+#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT (24u)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT (0u)
+#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT (16u)
+#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT (24u)
+
+#define INTC_ICDIPTR21_S0_WLINE0_SHIFT (0u)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT (8u)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT (16u)
+#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT (24u)
+
+#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT (0u)
+#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT (16u)
+#define INTC_ICDIPTR22_S1_WLINE0_SHIFT (24u)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT (0u)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT (8u)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT (16u)
+#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT (24u)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT (0u)
+#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT (8u)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT (24u)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT (0u)
+#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT (8u)
+#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT (16u)
+#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT (24u)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT (0u)
+#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT (16u)
+#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT (24u)
+
+#define INTC_ICDIPTR27_S0_WLINE1_SHIFT (0u)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT (8u)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT (16u)
+#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT (24u)
+
+#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT (0u)
+#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT (16u)
+#define INTC_ICDIPTR28_S1_WLINE1_SHIFT (24u)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT (0u)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT (8u)
+#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT (16u)
+#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT (24u)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT (0u)
+#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT (8u)
+#define INTC_ICDIPTR30_IMRDI_SHIFT (24u)
+
+#define INTC_ICDIPTR31_IMR2I0_SHIFT (0u)
+#define INTC_ICDIPTR31_IMR2I1_SHIFT (8u)
+#define INTC_ICDIPTR31_JEDI_SHIFT (16u)
+#define INTC_ICDIPTR31_JDTI_SHIFT (24u)
+
+#define INTC_ICDIPTR32_CMP0_SHIFT (0u)
+#define INTC_ICDIPTR32_CMP1_SHIFT (8u)
+#define INTC_ICDIPTR32_INT0_SHIFT (16u)
+#define INTC_ICDIPTR32_INT1_SHIFT (24u)
+
+#define INTC_ICDIPTR33_INT2_SHIFT (0u)
+#define INTC_ICDIPTR33_INT3_SHIFT (8u)
+#define INTC_ICDIPTR33_OSTM0TINT_SHIFT (16u)
+#define INTC_ICDIPTR33_OSTM1TINT_SHIFT (24u)
+
+#define INTC_ICDIPTR34_CMI_SHIFT (0u)
+#define INTC_ICDIPTR34_WTOUT_SHIFT (8u)
+#define INTC_ICDIPTR34_ITI_SHIFT (16u)
+#define INTC_ICDIPTR34_TGI0A_SHIFT (24u)
+
+#define INTC_ICDIPTR35_TGI0B_SHIFT (0u)
+#define INTC_ICDIPTR35_TGI0C_SHIFT (8u)
+#define INTC_ICDIPTR35_TGI0D_SHIFT (16u)
+#define INTC_ICDIPTR35_TGI0V_SHIFT (24u)
+
+#define INTC_ICDIPTR36_TGI0E_SHIFT (0u)
+#define INTC_ICDIPTR36_TGI0F_SHIFT (8u)
+#define INTC_ICDIPTR36_TGI1A_SHIFT (16u)
+#define INTC_ICDIPTR36_TGI1B_SHIFT (24u)
+
+#define INTC_ICDIPTR37_TGI1V_SHIFT (0u)
+#define INTC_ICDIPTR37_TGI1U_SHIFT (8u)
+#define INTC_ICDIPTR37_TGI2A_SHIFT (16u)
+#define INTC_ICDIPTR37_TGI2B_SHIFT (24u)
+
+#define INTC_ICDIPTR38_TGI2V_SHIFT (0u)
+#define INTC_ICDIPTR38_TGI2U_SHIFT (8u)
+#define INTC_ICDIPTR38_TGI3A_SHIFT (16u)
+#define INTC_ICDIPTR38_TGI3B_SHIFT (24u)
+
+#define INTC_ICDIPTR39_TGI3C_SHIFT (0u)
+#define INTC_ICDIPTR39_TGI3D_SHIFT (8u)
+#define INTC_ICDIPTR39_TGI3V_SHIFT (16u)
+#define INTC_ICDIPTR39_TGI4A_SHIFT (24u)
+
+#define INTC_ICDIPTR40_TGI4B_SHIFT (0u)
+#define INTC_ICDIPTR40_TGI4C_SHIFT (8u)
+#define INTC_ICDIPTR40_TGI4D_SHIFT (16u)
+#define INTC_ICDIPTR40_TGI4V_SHIFT (24u)
+
+#define INTC_ICDIPTR41_CMI1_SHIFT (0u)
+#define INTC_ICDIPTR41_CMI2_SHIFT (8u)
+#define INTC_ICDIPTR41_SGDEI0_SHIFT (16u)
+#define INTC_ICDIPTR41_SGDEI1_SHIFT (24u)
+
+#define INTC_ICDIPTR42_SGDEI2_SHIFT (0u)
+#define INTC_ICDIPTR42_SGDEI3_SHIFT (8u)
+#define INTC_ICDIPTR42_ADI_SHIFT (16u)
+#define INTC_ICDIPTR42_LMTI_SHIFT (24u)
+
+#define INTC_ICDIPTR43_SSII0_SHIFT (0u)
+#define INTC_ICDIPTR43_SSIRXI0_SHIFT (8u)
+#define INTC_ICDIPTR43_SSITXI0_SHIFT (16u)
+#define INTC_ICDIPTR43_SSII1_SHIFT (24u)
+
+#define INTC_ICDIPTR44_SSIRXI1_SHIFT (0u)
+#define INTC_ICDIPTR44_SSITXI1_SHIFT (8u)
+#define INTC_ICDIPTR44_SSII2_SHIFT (16u)
+#define INTC_ICDIPTR44_SSIRTI2_SHIFT (24u)
+
+#define INTC_ICDIPTR45_SSII3_SHIFT (0u)
+#define INTC_ICDIPTR45_SSIRXI3_SHIFT (8u)
+#define INTC_ICDIPTR45_SSITXI3_SHIFT (16u)
+#define INTC_ICDIPTR45_SSII4_SHIFT (24u)
+
+#define INTC_ICDIPTR46_SSIRTI4_SHIFT (0u)
+#define INTC_ICDIPTR46_SSII5_SHIFT (8u)
+#define INTC_ICDIPTR46_SSIRXI5_SHIFT (16u)
+#define INTC_ICDIPTR46_SSITXI5_SHIFT (24u)
+
+#define INTC_ICDIPTR47_SPDIFI_SHIFT (0u)
+#define INTC_ICDIPTR47_INTIICTEI0_SHIFT (8u)
+#define INTC_ICDIPTR47_INTIICRI0_SHIFT (16u)
+#define INTC_ICDIPTR47_INTIICTI0_SHIFT (24u)
+
+#define INTC_ICDIPTR48_INTIICSPI0_SHIFT (0u)
+#define INTC_ICDIPTR48_INTIICSTI0_SHIFT (8u)
+#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT (16u)
+#define INTC_ICDIPTR48_INTIICALI0_SHIFT (24u)
+
+#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT (0u)
+#define INTC_ICDIPTR49_INTIICTEI1_SHIFT (8u)
+#define INTC_ICDIPTR49_INTIICRI1_SHIFT (16u)
+#define INTC_ICDIPTR49_INTIICTI1_SHIFT (24u)
+
+#define INTC_ICDIPTR50_INTIICSPI1_SHIFT (0u)
+#define INTC_ICDIPTR50_INTIICSTI1_SHIFT (8u)
+#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT (16u)
+#define INTC_ICDIPTR50_INTIICALI1_SHIFT (24u)
+
+#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT (0u)
+#define INTC_ICDIPTR51_INTIICTEI2_SHIFT (8u)
+#define INTC_ICDIPTR51_INTIICRI2_SHIFT (16u)
+#define INTC_ICDIPTR51_INTIICTI2_SHIFT (24u)
+
+#define INTC_ICDIPTR52_INTIICSPI2_SHIFT (0u)
+#define INTC_ICDIPTR52_INTIICSTI2_SHIFT (8u)
+#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT (16u)
+#define INTC_ICDIPTR52_INTIICALI2_SHIFT (24u)
+
+#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT (0u)
+#define INTC_ICDIPTR53_INTIICTEI3_SHIFT (8u)
+#define INTC_ICDIPTR53_INTIICRI3_SHIFT (16u)
+#define INTC_ICDIPTR53_INTIICTI3_SHIFT (24u)
+
+#define INTC_ICDIPTR54_INTIICSPI3_SHIFT (0u)
+#define INTC_ICDIPTR54_INTIICSTI3_SHIFT (8u)
+#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT (16u)
+#define INTC_ICDIPTR54_INTIICALI3_SHIFT (24u)
+
+#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT (0u)
+#define INTC_ICDIPTR55_BRI0_SHIFT (8u)
+#define INTC_ICDIPTR55_ERI0_SHIFT (16u)
+#define INTC_ICDIPTR55_RXI0_SHIFT (24u)
+
+#define INTC_ICDIPTR56_TXI0_SHIFT (0u)
+#define INTC_ICDIPTR56_BRI1_SHIFT (8u)
+#define INTC_ICDIPTR56_ERI1_SHIFT (16u)
+#define INTC_ICDIPTR56_RXI1_SHIFT (24u)
+
+#define INTC_ICDIPTR57_TXI1_SHIFT (0u)
+#define INTC_ICDIPTR57_BRI2_SHIFT (8u)
+#define INTC_ICDIPTR57_ERI2_SHIFT (16u)
+#define INTC_ICDIPTR57_RXI2_SHIFT (24u)
+
+#define INTC_ICDIPTR58_TXI2_SHIFT (0u)
+#define INTC_ICDIPTR58_BRI3_SHIFT (8u)
+#define INTC_ICDIPTR58_ERI3_SHIFT (16u)
+#define INTC_ICDIPTR58_RXI3_SHIFT (24u)
+
+#define INTC_ICDIPTR59_TXI3_SHIFT (0u)
+#define INTC_ICDIPTR59_BRI4_SHIFT (8u)
+#define INTC_ICDIPTR59_ERI4_SHIFT (16u)
+#define INTC_ICDIPTR59_RXI4_SHIFT (24u)
+
+#define INTC_ICDIPTR60_TXI4_SHIFT (0u)
+#define INTC_ICDIPTR60_BRI5_SHIFT (8u)
+#define INTC_ICDIPTR60_ERI5_SHIFT (16u)
+#define INTC_ICDIPTR60_RXI5_SHIFT (24u)
+
+#define INTC_ICDIPTR61_TXI5_SHIFT (0u)
+#define INTC_ICDIPTR61_BRI6_SHIFT (8u)
+#define INTC_ICDIPTR61_ERI6_SHIFT (16u)
+#define INTC_ICDIPTR61_RXI6_SHIFT (24u)
+
+#define INTC_ICDIPTR62_TXI6_SHIFT (0u)
+#define INTC_ICDIPTR62_BRI7_SHIFT (8u)
+#define INTC_ICDIPTR62_ERI7_SHIFT (16u)
+#define INTC_ICDIPTR62_RXI7_SHIFT (24u)
+
+#define INTC_ICDIPTR63_TXI7_SHIFT (0u)
+#define INTC_ICDIPTR63_INTRCANGERR_SHIFT (8u)
+#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT (16u)
+#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT (24u)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT (0u)
+#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT (8u)
+#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT (16u)
+#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT (24u)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT (0u)
+#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT (8u)
+#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT (16u)
+#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT (24u)
+
+#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT (0u)
+#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT (8u)
+#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT (16u)
+#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT (24u)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT (0u)
+#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT (8u)
+#define INTC_ICDIPTR67_SPEI0_SHIFT (16u)
+#define INTC_ICDIPTR67_SPRI0_SHIFT (24u)
+
+#define INTC_ICDIPTR68_SPTI0_SHIFT (0u)
+#define INTC_ICDIPTR68_SPEI1_SHIFT (8u)
+#define INTC_ICDIPTR68_SPRI1_SHIFT (16u)
+#define INTC_ICDIPTR68_SPTI1_SHIFT (24u)
+
+#define INTC_ICDIPTR69_SPEI2_SHIFT (0u)
+#define INTC_ICDIPTR69_SPRI2_SHIFT (8u)
+#define INTC_ICDIPTR69_SPTI2_SHIFT (16u)
+#define INTC_ICDIPTR69_SPEI3_SHIFT (24u)
+
+#define INTC_ICDIPTR70_SPRI3_SHIFT (0u)
+#define INTC_ICDIPTR70_SPTI3_SHIFT (8u)
+#define INTC_ICDIPTR70_SPEI4_SHIFT (16u)
+#define INTC_ICDIPTR70_SPRI4_SHIFT (24u)
+
+#define INTC_ICDIPTR71_SPTI4_SHIFT (0u)
+#define INTC_ICDIPTR71_IEBBTD_SHIFT (8u)
+#define INTC_ICDIPTR71_IEBBTERR_SHIFT (16u)
+#define INTC_ICDIPTR71_IEBBTSTA_SHIFT (24u)
+
+#define INTC_ICDIPTR72_IEBBTV_SHIFT (0u)
+#define INTC_ICDIPTR72_ISY_SHIFT (8u)
+#define INTC_ICDIPTR72_IERR_SHIFT (16u)
+#define INTC_ICDIPTR72_ITARG_SHIFT (24u)
+
+#define INTC_ICDIPTR73_ISEC_SHIFT (0u)
+#define INTC_ICDIPTR73_IBUF_SHIFT (8u)
+#define INTC_ICDIPTR73_IREADY_SHIFT (16u)
+#define INTC_ICDIPTR73_FLSTE_SHIFT (24u)
+
+#define INTC_ICDIPTR74_FLTENDI_SHIFT (0u)
+#define INTC_ICDIPTR74_FLTREQ0I_SHIFT (8u)
+#define INTC_ICDIPTR74_FLTREQ1I_SHIFT (16u)
+#define INTC_ICDIPTR74_MMC0_SHIFT (24u)
+
+#define INTC_ICDIPTR75_MMC1_SHIFT (0u)
+#define INTC_ICDIPTR75_MMC2_SHIFT (8u)
+#define INTC_ICDIPTR75_SDHI0_3_SHIFT (16u)
+#define INTC_ICDIPTR75_SDHI0_0_SHIFT (24u)
+
+#define INTC_ICDIPTR76_SDHI0_1_SHIFT (0u)
+#define INTC_ICDIPTR76_SDHI1_3_SHIFT (8u)
+#define INTC_ICDIPTR76_SDHI1_0_SHIFT (16u)
+#define INTC_ICDIPTR76_SDHI1_1_SHIFT (24u)
+
+#define INTC_ICDIPTR77_ARM_SHIFT (0u)
+#define INTC_ICDIPTR77_PRD_SHIFT (8u)
+#define INTC_ICDIPTR77_CUP_SHIFT (16u)
+#define INTC_ICDIPTR77_SCUAI0_SHIFT (24u)
+
+#define INTC_ICDIPTR78_SCUAI1_SHIFT (0u)
+#define INTC_ICDIPTR78_SCUFDI0_SHIFT (8u)
+#define INTC_ICDIPTR78_SCUFDI1_SHIFT (16u)
+#define INTC_ICDIPTR78_SCUFDI2_SHIFT (24u)
+
+#define INTC_ICDIPTR79_SCUFDI3_SHIFT (0u)
+#define INTC_ICDIPTR79_SCUFUI0_SHIFT (8u)
+#define INTC_ICDIPTR79_SCUFUI1_SHIFT (16u)
+#define INTC_ICDIPTR79_SCUFUI2_SHIFT (24u)
+
+#define INTC_ICDIPTR80_SCUFUI3_SHIFT (0u)
+#define INTC_ICDIPTR80_SCUDVI0_SHIFT (8u)
+#define INTC_ICDIPTR80_SCUDVI1_SHIFT (16u)
+#define INTC_ICDIPTR80_SCUDVI2_SHIFT (24u)
+
+#define INTC_ICDIPTR81_SCUDVI3_SHIFT (0u)
+#define INTC_ICDIPTR81_MLB_CINT_SHIFT (8u)
+#define INTC_ICDIPTR81_MLB_SINT_SHIFT (16u)
+#define INTC_ICDIPTR81_DRC0_SHIFT (24u)
+
+#define INTC_ICDIPTR82_DRC1_SHIFT (0u)
+#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT (24u)
+
+#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT (0u)
+#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT (8u)
+#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT (16u)
+#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT (24u)
+
+#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT (0u)
+#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT (8u)
+#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT (16u)
+
+#define INTC_ICDIPTR86_ERI0_SHIFT (24u)
+
+#define INTC_ICDIPTR87_RXI0_SHIFT (0u)
+#define INTC_ICDIPTR87_TXI0_SHIFT (8u)
+#define INTC_ICDIPTR87_TEI0_SHIFT (16u)
+#define INTC_ICDIPTR87_ERI1_SHIFT (24u)
+
+#define INTC_ICDIPTR88_RXI1_SHIFT (0u)
+#define INTC_ICDIPTR88_TXI1_SHIFT (8u)
+#define INTC_ICDIPTR88_TEI1_SHIFT (16u)
+#define INTC_ICDIPTR88_AVBI_DATA_SHIFT (24u)
+
+#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT (0u)
+#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT (8u)
+#define INTC_ICDIPTR89_AVBI_MAC_SHIFT (16u)
+#define INTC_ICDIPTR89_ETHERI_SHIFT (24u)
+
+#define INTC_ICDIPTR91_CEUI_SHIFT (0u)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT (8u)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT (16u)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT (0u)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT (8u)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT (16u)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT (0u)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT (8u)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT (16u)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT (24u)
+
+#define INTC_ICDIPTR98_PRRI_SHIFT (0u)
+#define INTC_ICDIPTR98_IFEI0_SHIFT (8u)
+#define INTC_ICDIPTR98_OFFI0_SHIFT (16u)
+#define INTC_ICDIPTR98_PFVEI0_SHIFT (24u)
+
+#define INTC_ICDIPTR99_IFEI1_SHIFT (0u)
+#define INTC_ICDIPTR99_OFFI1_SHIFT (8u)
+#define INTC_ICDIPTR99_PFVEI1_SHIFT (16u)
+
+#define INTC_ICDIPTR104_TINT0_SHIFT (0u)
+#define INTC_ICDIPTR104_TINT1_SHIFT (8u)
+#define INTC_ICDIPTR104_TINT2_SHIFT (16u)
+#define INTC_ICDIPTR104_TINT3_SHIFT (24u)
+
+#define INTC_ICDIPTR105_TINT4_SHIFT (0u)
+#define INTC_ICDIPTR105_TINT5_SHIFT (8u)
+#define INTC_ICDIPTR105_TINT6_SHIFT (16u)
+#define INTC_ICDIPTR105_TINT7_SHIFT (24u)
+
+#define INTC_ICDIPTR106_TINT8_SHIFT (0u)
+#define INTC_ICDIPTR106_TINT9_SHIFT (8u)
+#define INTC_ICDIPTR106_TINT10_SHIFT (16u)
+#define INTC_ICDIPTR106_TINT11_SHIFT (24u)
+
+#define INTC_ICDIPTR107_TINT12_SHIFT (0u)
+#define INTC_ICDIPTR107_TINT13_SHIFT (8u)
+#define INTC_ICDIPTR107_TINT14_SHIFT (16u)
+#define INTC_ICDIPTR107_TINT15_SHIFT (24u)
+
+#define INTC_ICDIPTR108_TINT16_SHIFT (0u)
+#define INTC_ICDIPTR108_TINT17_SHIFT (8u)
+#define INTC_ICDIPTR108_TINT18_SHIFT (16u)
+#define INTC_ICDIPTR108_TINT19_SHIFT (24u)
+
+#define INTC_ICDIPTR109_TINT20_SHIFT (0u)
+#define INTC_ICDIPTR109_TINT21_SHIFT (8u)
+#define INTC_ICDIPTR109_TINT22_SHIFT (16u)
+#define INTC_ICDIPTR109_TINT23_SHIFT (24u)
+
+#define INTC_ICDIPTR110_TINT24_SHIFT (0u)
+#define INTC_ICDIPTR110_TINT25_SHIFT (8u)
+#define INTC_ICDIPTR110_TINT26_SHIFT (16u)
+#define INTC_ICDIPTR110_TINT27_SHIFT (24u)
+
+#define INTC_ICDIPTR111_TINT28_SHIFT (0u)
+#define INTC_ICDIPTR111_TINT29_SHIFT (8u)
+#define INTC_ICDIPTR111_TINT30_SHIFT (16u)
+#define INTC_ICDIPTR111_TINT31_SHIFT (24u)
+
+#define INTC_ICDIPTR112_TINT32_SHIFT (0u)
+#define INTC_ICDIPTR112_TINT33_SHIFT (8u)
+#define INTC_ICDIPTR112_TINT34_SHIFT (16u)
+#define INTC_ICDIPTR112_TINT35_SHIFT (24u)
+
+#define INTC_ICDIPTR113_TINT36_SHIFT (0u)
+#define INTC_ICDIPTR113_TINT37_SHIFT (8u)
+#define INTC_ICDIPTR113_TINT38_SHIFT (16u)
+#define INTC_ICDIPTR113_TINT39_SHIFT (24u)
+
+#define INTC_ICDIPTR114_TINT40_SHIFT (0u)
+#define INTC_ICDIPTR114_TINT41_SHIFT (8u)
+#define INTC_ICDIPTR114_TINT42_SHIFT (16u)
+#define INTC_ICDIPTR114_TINT43_SHIFT (24u)
+
+#define INTC_ICDIPTR115_TINT44_SHIFT (0u)
+#define INTC_ICDIPTR115_TINT45_SHIFT (8u)
+#define INTC_ICDIPTR115_TINT46_SHIFT (16u)
+#define INTC_ICDIPTR115_TINT47_SHIFT (24u)
+
+#define INTC_ICDIPTR116_TINT48_SHIFT (0u)
+#define INTC_ICDIPTR116_TINT49_SHIFT (8u)
+#define INTC_ICDIPTR116_TINT50_SHIFT (16u)
+#define INTC_ICDIPTR116_TINT51_SHIFT (24u)
+
+#define INTC_ICDIPTR117_TINT52_SHIFT (0u)
+#define INTC_ICDIPTR117_TINT53_SHIFT (8u)
+#define INTC_ICDIPTR117_TINT54_SHIFT (16u)
+#define INTC_ICDIPTR117_TINT55_SHIFT (24u)
+
+#define INTC_ICDIPTR118_TINT56_SHIFT (0u)
+#define INTC_ICDIPTR118_TINT57_SHIFT (8u)
+#define INTC_ICDIPTR118_TINT58_SHIFT (16u)
+#define INTC_ICDIPTR118_TINT59_SHIFT (24u)
+
+#define INTC_ICDIPTR119_TINT60_SHIFT (0u)
+#define INTC_ICDIPTR119_TINT61_SHIFT (8u)
+#define INTC_ICDIPTR119_TINT62_SHIFT (16u)
+#define INTC_ICDIPTR119_TINT63_SHIFT (24u)
+
+#define INTC_ICDIPTR120_TINT64_SHIFT (0u)
+#define INTC_ICDIPTR120_TINT65_SHIFT (8u)
+#define INTC_ICDIPTR120_TINT66_SHIFT (16u)
+#define INTC_ICDIPTR120_TINT67_SHIFT (24u)
+
+#define INTC_ICDIPTR121_TINT68_SHIFT (0u)
+#define INTC_ICDIPTR121_TINT69_SHIFT (8u)
+#define INTC_ICDIPTR121_TINT70_SHIFT (16u)
+#define INTC_ICDIPTR121_TINT71_SHIFT (24u)
+
+#define INTC_ICDIPTR122_TINT72_SHIFT (0u)
+#define INTC_ICDIPTR122_TINT73_SHIFT (8u)
+#define INTC_ICDIPTR122_TINT74_SHIFT (16u)
+#define INTC_ICDIPTR122_TINT75_SHIFT (24u)
+
+#define INTC_ICDIPTR123_TINT76_SHIFT (0u)
+#define INTC_ICDIPTR123_TINT77_SHIFT (8u)
+#define INTC_ICDIPTR123_TINT78_SHIFT (16u)
+#define INTC_ICDIPTR123_TINT79_SHIFT (24u)
+
+#define INTC_ICDIPTR124_TINT80_SHIFT (0u)
+#define INTC_ICDIPTR124_TINT81_SHIFT (8u)
+#define INTC_ICDIPTR124_TINT82_SHIFT (16u)
+#define INTC_ICDIPTR124_TINT83_SHIFT (24u)
+
+#define INTC_ICDIPTR125_TINT84_SHIFT (0u)
+#define INTC_ICDIPTR125_TINT85_SHIFT (8u)
+#define INTC_ICDIPTR125_TINT86_SHIFT (16u)
+#define INTC_ICDIPTR125_TINT87_SHIFT (24u)
+
+#define INTC_ICDIPTR126_TINT88_SHIFT (0u)
+#define INTC_ICDIPTR126_TINT89_SHIFT (8u)
+#define INTC_ICDIPTR126_TINT90_SHIFT (16u)
+#define INTC_ICDIPTR126_TINT91_SHIFT (24u)
+
+#define INTC_ICDIPTR127_TINT92_SHIFT (0u)
+#define INTC_ICDIPTR127_TINT93_SHIFT (8u)
+#define INTC_ICDIPTR127_TINT94_SHIFT (16u)
+#define INTC_ICDIPTR127_TINT95_SHIFT (24u)
+
+#define INTC_ICDIPTR128_TINT96_SHIFT (0u)
+#define INTC_ICDIPTR128_TINT97_SHIFT (8u)
+#define INTC_ICDIPTR128_TINT98_SHIFT (16u)
+#define INTC_ICDIPTR128_TINT99_SHIFT (24u)
+
+#define INTC_ICDIPTR129_TINT100_SHIFT (0u)
+#define INTC_ICDIPTR129_TINT101_SHIFT (8u)
+#define INTC_ICDIPTR129_TINT102_SHIFT (16u)
+#define INTC_ICDIPTR129_TINT103_SHIFT (24u)
+
+#define INTC_ICDIPTR130_TINT104_SHIFT (0u)
+#define INTC_ICDIPTR130_TINT105_SHIFT (8u)
+#define INTC_ICDIPTR130_TINT106_SHIFT (16u)
+#define INTC_ICDIPTR130_TINT107_SHIFT (24u)
+
+#define INTC_ICDIPTR131_TINT108_SHIFT (0u)
+#define INTC_ICDIPTR131_TINT109_SHIFT (8u)
+#define INTC_ICDIPTR131_TINT110_SHIFT (16u)
+#define INTC_ICDIPTR131_TINT111_SHIFT (24u)
+
+#define INTC_ICDIPTR132_TINT112_SHIFT (0u)
+#define INTC_ICDIPTR132_TINT113_SHIFT (8u)
+#define INTC_ICDIPTR132_TINT114_SHIFT (16u)
+#define INTC_ICDIPTR132_TINT115_SHIFT (24u)
+
+#define INTC_ICDIPTR133_TINT116_SHIFT (0u)
+#define INTC_ICDIPTR133_TINT117_SHIFT (8u)
+#define INTC_ICDIPTR133_TINT118_SHIFT (16u)
+#define INTC_ICDIPTR133_TINT119_SHIFT (24u)
+
+#define INTC_ICDIPTR134_TINT120_SHIFT (0u)
+#define INTC_ICDIPTR134_TINT121_SHIFT (8u)
+#define INTC_ICDIPTR134_TINT122_SHIFT (16u)
+#define INTC_ICDIPTR134_TINT123_SHIFT (24u)
+
+#define INTC_ICDIPTR135_TINT124_SHIFT (0u)
+#define INTC_ICDIPTR135_TINT125_SHIFT (8u)
+#define INTC_ICDIPTR135_TINT126_SHIFT (16u)
+#define INTC_ICDIPTR135_TINT127_SHIFT (24u)
+
+#define INTC_ICDIPTR136_TINT128_SHIFT (0u)
+#define INTC_ICDIPTR136_TINT129_SHIFT (8u)
+#define INTC_ICDIPTR136_TINT130_SHIFT (16u)
+#define INTC_ICDIPTR136_TINT131_SHIFT (24u)
+
+#define INTC_ICDIPTR137_TINT132_SHIFT (0u)
+#define INTC_ICDIPTR137_TINT133_SHIFT (8u)
+#define INTC_ICDIPTR137_TINT134_SHIFT (16u)
+#define INTC_ICDIPTR137_TINT135_SHIFT (24u)
+
+#define INTC_ICDIPTR138_TINT136_SHIFT (0u)
+#define INTC_ICDIPTR138_TINT137_SHIFT (8u)
+#define INTC_ICDIPTR138_TINT138_SHIFT (16u)
+#define INTC_ICDIPTR138_TINT139_SHIFT (24u)
+
+#define INTC_ICDIPTR139_TINT140_SHIFT (0u)
+#define INTC_ICDIPTR139_TINT141_SHIFT (8u)
+#define INTC_ICDIPTR139_TINT142_SHIFT (16u)
+#define INTC_ICDIPTR139_TINT143_SHIFT (24u)
+
+#define INTC_ICDIPTR140_TINT144_SHIFT (0u)
+#define INTC_ICDIPTR140_TINT145_SHIFT (8u)
+#define INTC_ICDIPTR140_TINT146_SHIFT (16u)
+#define INTC_ICDIPTR140_TINT147_SHIFT (24u)
+
+#define INTC_ICDIPTR141_TINT148_SHIFT (0u)
+#define INTC_ICDIPTR141_TINT149_SHIFT (8u)
+#define INTC_ICDIPTR141_TINT150_SHIFT (16u)
+#define INTC_ICDIPTR141_TINT151_SHIFT (24u)
+
+#define INTC_ICDIPTR142_TINT152_SHIFT (0u)
+#define INTC_ICDIPTR142_TINT153_SHIFT (8u)
+#define INTC_ICDIPTR142_TINT154_SHIFT (16u)
+#define INTC_ICDIPTR142_TINT155_SHIFT (24u)
+
+#define INTC_ICDIPTR143_TINT156_SHIFT (0u)
+#define INTC_ICDIPTR143_TINT157_SHIFT (8u)
+#define INTC_ICDIPTR143_TINT158_SHIFT (16u)
+#define INTC_ICDIPTR143_TINT159_SHIFT (24u)
+
+#define INTC_ICDIPTR144_TINT160_SHIFT (0u)
+#define INTC_ICDIPTR144_TINT161_SHIFT (8u)
+#define INTC_ICDIPTR144_TINT162_SHIFT (16u)
+#define INTC_ICDIPTR144_TINT163_SHIFT (24u)
+
+#define INTC_ICDIPTR145_TINT164_SHIFT (0u)
+#define INTC_ICDIPTR145_TINT165_SHIFT (8u)
+#define INTC_ICDIPTR145_TINT166_SHIFT (16u)
+#define INTC_ICDIPTR145_TINT167_SHIFT (24u)
+
+#define INTC_ICDIPTR146_TINT168_SHIFT (0u)
+#define INTC_ICDIPTR146_TINT169_SHIFT (8u)
+#define INTC_ICDIPTR146_TINT170_SHIFT (16u)
+
+#define INTC_ICDICFR0_SW0_0_SHIFT (0u)
+#define INTC_ICDICFR0_SW0_1_SHIFT (1u)
+#define INTC_ICDICFR0_SW1_0_SHIFT (2u)
+#define INTC_ICDICFR0_SW1_1_SHIFT (3u)
+#define INTC_ICDICFR0_SW2_0_SHIFT (4u)
+#define INTC_ICDICFR0_SW2_1_SHIFT (5u)
+#define INTC_ICDICFR0_SW3_0_SHIFT (6u)
+#define INTC_ICDICFR0_SW3_1_SHIFT (7u)
+#define INTC_ICDICFR0_SW4_0_SHIFT (8u)
+#define INTC_ICDICFR0_SW4_1_SHIFT (9u)
+#define INTC_ICDICFR0_SW5_0_SHIFT (10u)
+#define INTC_ICDICFR0_SW5_1_SHIFT (11u)
+#define INTC_ICDICFR0_SW6_0_SHIFT (12u)
+#define INTC_ICDICFR0_SW6_1_SHIFT (13u)
+#define INTC_ICDICFR0_SW7_0_SHIFT (14u)
+#define INTC_ICDICFR0_SW7_1_SHIFT (15u)
+#define INTC_ICDICFR0_SW8_0_SHIFT (16u)
+#define INTC_ICDICFR0_SW8_1_SHIFT (17u)
+#define INTC_ICDICFR0_SW9_0_SHIFT (18u)
+#define INTC_ICDICFR0_SW9_1_SHIFT (19u)
+#define INTC_ICDICFR0_SW10_0_SHIFT (20u)
+#define INTC_ICDICFR0_SW10_1_SHIFT (21u)
+#define INTC_ICDICFR0_SW11_0_SHIFT (22u)
+#define INTC_ICDICFR0_SW11_1_SHIFT (23u)
+#define INTC_ICDICFR0_SW12_0_SHIFT (24u)
+#define INTC_ICDICFR0_SW12_1_SHIFT (25u)
+#define INTC_ICDICFR0_SW13_0_SHIFT (26u)
+#define INTC_ICDICFR0_SW13_1_SHIFT (27u)
+#define INTC_ICDICFR0_SW14_0_SHIFT (28u)
+#define INTC_ICDICFR0_SW14_1_SHIFT (29u)
+#define INTC_ICDICFR0_SW15_0_SHIFT (30u)
+#define INTC_ICDICFR0_SW15_1_SHIFT (31u)
+
+#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT (0u)
+#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT (1u)
+#define INTC_ICDICFR1_COMMRX0_0_SHIFT (2u)
+#define INTC_ICDICFR1_COMMRX0_1_SHIFT (3u)
+#define INTC_ICDICFR1_COMMTX0_0_SHIFT (4u)
+#define INTC_ICDICFR1_COMMTX0_1_SHIFT (5u)
+#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT (6u)
+#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT (7u)
+
+#define INTC_ICDICFR2_IRQ0_0_SHIFT (0u)
+#define INTC_ICDICFR2_IRQ0_1_SHIFT (1u)
+#define INTC_ICDICFR2_IRQ1_0_SHIFT (2u)
+#define INTC_ICDICFR2_IRQ1_1_SHIFT (3u)
+#define INTC_ICDICFR2_IRQ2_0_SHIFT (4u)
+#define INTC_ICDICFR2_IRQ2_1_SHIFT (5u)
+#define INTC_ICDICFR2_IRQ3_0_SHIFT (6u)
+#define INTC_ICDICFR2_IRQ3_1_SHIFT (7u)
+#define INTC_ICDICFR2_IRQ4_0_SHIFT (8u)
+#define INTC_ICDICFR2_IRQ4_1_SHIFT (9u)
+#define INTC_ICDICFR2_IRQ5_0_SHIFT (10u)
+#define INTC_ICDICFR2_IRQ5_1_SHIFT (11u)
+#define INTC_ICDICFR2_IRQ6_0_SHIFT (12u)
+#define INTC_ICDICFR2_IRQ6_1_SHIFT (13u)
+#define INTC_ICDICFR2_IRQ7_0_SHIFT (14u)
+#define INTC_ICDICFR2_IRQ7_1_SHIFT (15u)
+#define INTC_ICDICFR2_PL310ERR_0_SHIFT (16u)
+#define INTC_ICDICFR2_PL310ERR_1_SHIFT (17u)
+#define INTC_ICDICFR2_DMAINT0_0_SHIFT (18u)
+#define INTC_ICDICFR2_DMAINT0_1_SHIFT (19u)
+#define INTC_ICDICFR2_DMAINT1_0_SHIFT (20u)
+#define INTC_ICDICFR2_DMAINT1_1_SHIFT (21u)
+#define INTC_ICDICFR2_DMAINT2_0_SHIFT (22u)
+#define INTC_ICDICFR2_DMAINT2_1_SHIFT (23u)
+#define INTC_ICDICFR2_DMAINT3_0_SHIFT (24u)
+#define INTC_ICDICFR2_DMAINT3_1_SHIFT (25u)
+#define INTC_ICDICFR2_DMAINT4_0_SHIFT (26u)
+#define INTC_ICDICFR2_DMAINT4_1_SHIFT (27u)
+#define INTC_ICDICFR2_DMAINT5_0_SHIFT (28u)
+#define INTC_ICDICFR2_DMAINT5_1_SHIFT (29u)
+#define INTC_ICDICFR2_DMAINT6_0_SHIFT (30u)
+#define INTC_ICDICFR2_DMAINT6_1_SHIFT (31u)
+
+#define INTC_ICDICFR3_DMAINT7_0_SHIFT (0u)
+#define INTC_ICDICFR3_DMAINT7_1_SHIFT (1u)
+#define INTC_ICDICFR3_DMAINT8_0_SHIFT (2u)
+#define INTC_ICDICFR3_DMAINT8_1_SHIFT (3u)
+#define INTC_ICDICFR3_DMAINT9_0_SHIFT (4u)
+#define INTC_ICDICFR3_DMAINT9_1_SHIFT (5u)
+#define INTC_ICDICFR3_DMAINT10_0_SHIFT (6u)
+#define INTC_ICDICFR3_DMAINT10_1_SHIFT (7u)
+#define INTC_ICDICFR3_DMAINT11_0_SHIFT (8u)
+#define INTC_ICDICFR3_DMAINT11_1_SHIFT (9u)
+#define INTC_ICDICFR3_DMAINT12_0_SHIFT (10u)
+#define INTC_ICDICFR3_DMAINT12_1_SHIFT (11u)
+#define INTC_ICDICFR3_DMAINT13_0_SHIFT (12u)
+#define INTC_ICDICFR3_DMAINT13_1_SHIFT (13u)
+#define INTC_ICDICFR3_DMAINT14_0_SHIFT (14u)
+#define INTC_ICDICFR3_DMAINT14_1_SHIFT (15u)
+#define INTC_ICDICFR3_DMAINT15_0_SHIFT (16u)
+#define INTC_ICDICFR3_DMAINT15_1_SHIFT (17u)
+#define INTC_ICDICFR3_DMAERR_0_SHIFT (18u)
+#define INTC_ICDICFR3_DMAERR_1_SHIFT (19u)
+
+#define INTC_ICDICFR4_USBI0_0_SHIFT (18u)
+#define INTC_ICDICFR4_USBI0_1_SHIFT (19u)
+#define INTC_ICDICFR4_USBI1_0_SHIFT (20u)
+#define INTC_ICDICFR4_USBI1_1_SHIFT (21u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT (22u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT (23u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT (24u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT (25u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT (26u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT (27u)
+#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT (28u)
+#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT (29u)
+#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT (30u)
+#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT (31u)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT (0u)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT (1u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT (2u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT (3u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT (4u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT (5u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT (6u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT (7u)
+#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT (8u)
+#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT (9u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT (10u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT (11u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT (12u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT (13u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT (14u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT (15u)
+#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT (16u)
+#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT (17u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT (18u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT (19u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT (20u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT (21u)
+#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT (22u)
+#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT (23u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT (24u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT (25u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT (26u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT (27u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT (28u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT (29u)
+#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT (30u)
+#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT (31u)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT (0u)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT (1u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT (2u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT (3u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT (6u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT (7u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT (8u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT (9u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT (10u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT (11u)
+#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT (12u)
+#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT (13u)
+#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT (14u)
+#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT (15u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT (16u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT (17u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT (18u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT (19u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT (20u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT (21u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT (22u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT (23u)
+#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT (24u)
+#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT (25u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT (26u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT (27u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT (28u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT (29u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT (30u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT (31u)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT (0u)
+#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT (1u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT (2u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT (3u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT (4u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT (5u)
+#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT (6u)
+#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT (7u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT (8u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT (9u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT (10u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT (11u)
+#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT (12u)
+#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT (13u)
+#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT (14u)
+#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT (15u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT (16u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT (17u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT (18u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT (19u)
+#define INTC_ICDICFR7_IMRDI_0_SHIFT (22u)
+#define INTC_ICDICFR7_IMRDI_1_SHIFT (23u)
+#define INTC_ICDICFR7_IMR2I0_0_SHIFT (24u)
+#define INTC_ICDICFR7_IMR2I0_1_SHIFT (25u)
+#define INTC_ICDICFR7_IMR2I1_0_SHIFT (26u)
+#define INTC_ICDICFR7_IMR2I1_1_SHIFT (27u)
+#define INTC_ICDICFR7_JEDI_0_SHIFT (28u)
+#define INTC_ICDICFR7_JEDI_1_SHIFT (29u)
+#define INTC_ICDICFR7_JDTI_0_SHIFT (30u)
+#define INTC_ICDICFR7_JDTI_1_SHIFT (31u)
+
+#define INTC_ICDICFR8_CMP0_0_SHIFT (0u)
+#define INTC_ICDICFR8_CMP0_1_SHIFT (1u)
+#define INTC_ICDICFR8_CMP1_0_SHIFT (2u)
+#define INTC_ICDICFR8_CMP1_1_SHIFT (3u)
+#define INTC_ICDICFR8_INT0_0_SHIFT (4u)
+#define INTC_ICDICFR8_INT0_1_SHIFT (5u)
+#define INTC_ICDICFR8_INT1_0_SHIFT (6u)
+#define INTC_ICDICFR8_INT1_1_SHIFT (7u)
+#define INTC_ICDICFR8_INT2_0_SHIFT (8u)
+#define INTC_ICDICFR8_INT2_1_SHIFT (9u)
+#define INTC_ICDICFR8_INT3_0_SHIFT (10u)
+#define INTC_ICDICFR8_INT3_1_SHIFT (11u)
+#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT (12u)
+#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT (13u)
+#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT (14u)
+#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT (15u)
+#define INTC_ICDICFR8_CMI_0_SHIFT (16u)
+#define INTC_ICDICFR8_CMI_1_SHIFT (17u)
+#define INTC_ICDICFR8_WTOUT_0_SHIFT (18u)
+#define INTC_ICDICFR8_WTOUT_1_SHIFT (19u)
+#define INTC_ICDICFR8_ITI_0_SHIFT (20u)
+#define INTC_ICDICFR8_ITI_1_SHIFT (21u)
+#define INTC_ICDICFR8_TGI0A_0_SHIFT (22u)
+#define INTC_ICDICFR8_TGI0A_1_SHIFT (23u)
+#define INTC_ICDICFR8_TGI0B_0_SHIFT (24u)
+#define INTC_ICDICFR8_TGI0B_1_SHIFT (25u)
+#define INTC_ICDICFR8_TGI0C_0_SHIFT (26u)
+#define INTC_ICDICFR8_TGI0C_1_SHIFT (27u)
+#define INTC_ICDICFR8_TGI0D_0_SHIFT (28u)
+#define INTC_ICDICFR8_TGI0D_1_SHIFT (29u)
+#define INTC_ICDICFR8_TGI0V_0_SHIFT (30u)
+#define INTC_ICDICFR8_TGI0V_1_SHIFT (31u)
+
+#define INTC_ICDICFR9_TGI0E_0_SHIFT (0u)
+#define INTC_ICDICFR9_TGI0E_1_SHIFT (1u)
+#define INTC_ICDICFR9_TGI0F_0_SHIFT (2u)
+#define INTC_ICDICFR9_TGI0F_1_SHIFT (3u)
+#define INTC_ICDICFR9_TGI1A_0_SHIFT (4u)
+#define INTC_ICDICFR9_TGI1A_1_SHIFT (5u)
+#define INTC_ICDICFR9_TGI1B_0_SHIFT (6u)
+#define INTC_ICDICFR9_TGI1B_1_SHIFT (7u)
+#define INTC_ICDICFR9_TGI1V_0_SHIFT (8u)
+#define INTC_ICDICFR9_TGI1V_1_SHIFT (9u)
+#define INTC_ICDICFR9_TGI1U_0_SHIFT (10u)
+#define INTC_ICDICFR9_TGI1U_1_SHIFT (11u)
+#define INTC_ICDICFR9_TGI2A_0_SHIFT (12u)
+#define INTC_ICDICFR9_TGI2A_1_SHIFT (13u)
+#define INTC_ICDICFR9_TGI2B_0_SHIFT (14u)
+#define INTC_ICDICFR9_TGI2B_1_SHIFT (15u)
+#define INTC_ICDICFR9_TGI2V_0_SHIFT (16u)
+#define INTC_ICDICFR9_TGI2V_1_SHIFT (17u)
+#define INTC_ICDICFR9_TGI2U_0_SHIFT (18u)
+#define INTC_ICDICFR9_TGI2U_1_SHIFT (19u)
+#define INTC_ICDICFR9_TGI3A_0_SHIFT (20u)
+#define INTC_ICDICFR9_TGI3A_1_SHIFT (21u)
+#define INTC_ICDICFR9_TGI3B_0_SHIFT (22u)
+#define INTC_ICDICFR9_TGI3B_1_SHIFT (23u)
+#define INTC_ICDICFR9_TGI3C_0_SHIFT (24u)
+#define INTC_ICDICFR9_TGI3C_1_SHIFT (25u)
+#define INTC_ICDICFR9_TGI3D_0_SHIFT (26u)
+#define INTC_ICDICFR9_TGI3D_1_SHIFT (27u)
+#define INTC_ICDICFR9_TGI3V_0_SHIFT (28u)
+#define INTC_ICDICFR9_TGI3V_1_SHIFT (29u)
+#define INTC_ICDICFR9_TGI4A_0_SHIFT (30u)
+#define INTC_ICDICFR9_TGI4A_1_SHIFT (31u)
+
+#define INTC_ICDICFR10_TGI4B_0_SHIFT (0u)
+#define INTC_ICDICFR10_TGI4B_1_SHIFT (1u)
+#define INTC_ICDICFR10_TGI4C_0_SHIFT (2u)
+#define INTC_ICDICFR10_TGI4C_1_SHIFT (3u)
+#define INTC_ICDICFR10_TGI4D_0_SHIFT (4u)
+#define INTC_ICDICFR10_TGI4D_1_SHIFT (5u)
+#define INTC_ICDICFR10_TGI4V_0_SHIFT (6u)
+#define INTC_ICDICFR10_TGI4V_1_SHIFT (7u)
+#define INTC_ICDICFR10_CMI1_0_SHIFT (8u)
+#define INTC_ICDICFR10_CMI1_1_SHIFT (9u)
+#define INTC_ICDICFR10_CMI2_0_SHIFT (10u)
+#define INTC_ICDICFR10_CMI2_1_SHIFT (11u)
+#define INTC_ICDICFR10_SGDEI0_0_SHIFT (12u)
+#define INTC_ICDICFR10_SGDEI0_1_SHIFT (13u)
+#define INTC_ICDICFR10_SGDEI1_0_SHIFT (14u)
+#define INTC_ICDICFR10_SGDEI1_1_SHIFT (15u)
+#define INTC_ICDICFR10_SGDEI2_0_SHIFT (16u)
+#define INTC_ICDICFR10_SGDEI2_1_SHIFT (17u)
+#define INTC_ICDICFR10_SGDEI3_0_SHIFT (18u)
+#define INTC_ICDICFR10_SGDEI3_1_SHIFT (19u)
+#define INTC_ICDICFR10_ADI_0_SHIFT (20u)
+#define INTC_ICDICFR10_ADI_1_SHIFT (21u)
+#define INTC_ICDICFR10_LMTI_0_SHIFT (22u)
+#define INTC_ICDICFR10_LMTI_1_SHIFT (23u)
+#define INTC_ICDICFR10_SSII0_0_SHIFT (24u)
+#define INTC_ICDICFR10_SSII0_1_SHIFT (25u)
+#define INTC_ICDICFR10_SSIRXI0_0_SHIFT (26u)
+#define INTC_ICDICFR10_SSIRXI0_1_SHIFT (27u)
+#define INTC_ICDICFR10_SSITXI0_0_SHIFT (28u)
+#define INTC_ICDICFR10_SSITXI0_1_SHIFT (29u)
+#define INTC_ICDICFR10_SSII1_0_SHIFT (30u)
+#define INTC_ICDICFR10_SSII1_1_SHIFT (31u)
+
+#define INTC_ICDICFR11_SSIRXI1_0_SHIFT (0u)
+#define INTC_ICDICFR11_SSIRXI1_1_SHIFT (1u)
+#define INTC_ICDICFR11_SSITXI1_0_SHIFT (2u)
+#define INTC_ICDICFR11_SSITXI1_1_SHIFT (3u)
+#define INTC_ICDICFR11_SSII2_0_SHIFT (4u)
+#define INTC_ICDICFR11_SSII2_1_SHIFT (5u)
+#define INTC_ICDICFR11_SSIRTI2_0_SHIFT (6u)
+#define INTC_ICDICFR11_SSIRTI2_1_SHIFT (7u)
+#define INTC_ICDICFR11_SSII3_0_SHIFT (8u)
+#define INTC_ICDICFR11_SSII3_1_SHIFT (9u)
+#define INTC_ICDICFR11_SSIRXI3_0_SHIFT (10u)
+#define INTC_ICDICFR11_SSIRXI3_1_SHIFT (11u)
+#define INTC_ICDICFR11_SSITXI3_0_SHIFT (12u)
+#define INTC_ICDICFR11_SSITXI3_1_SHIFT (13u)
+#define INTC_ICDICFR11_SSII4_0_SHIFT (14u)
+#define INTC_ICDICFR11_SSII4_1_SHIFT (15u)
+#define INTC_ICDICFR11_SSIRTI4_0_SHIFT (16u)
+#define INTC_ICDICFR11_SSIRTI4_1_SHIFT (17u)
+#define INTC_ICDICFR11_SSII5_0_SHIFT (18u)
+#define INTC_ICDICFR11_SSII5_1_SHIFT (19u)
+#define INTC_ICDICFR11_SSIRXI5_0_SHIFT (20u)
+#define INTC_ICDICFR11_SSIRXI5_1_SHIFT (21u)
+#define INTC_ICDICFR11_SSITXI5_0_SHIFT (22u)
+#define INTC_ICDICFR11_SSITXI5_1_SHIFT (23u)
+#define INTC_ICDICFR11_SPDIFI_0_SHIFT (24u)
+#define INTC_ICDICFR11_SPDIFI_1_SHIFT (25u)
+#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT (26u)
+#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT (27u)
+#define INTC_ICDICFR11_INTIICRI0_0_SHIFT (28u)
+#define INTC_ICDICFR11_INTIICRI0_1_SHIFT (29u)
+#define INTC_ICDICFR11_INTIICTI0_0_SHIFT (30u)
+#define INTC_ICDICFR11_INTIICTI0_1_SHIFT (31u)
+
+#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT (0u)
+#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT (1u)
+#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT (2u)
+#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT (3u)
+#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT (4u)
+#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT (5u)
+#define INTC_ICDICFR12_INTIICALI0_0_SHIFT (6u)
+#define INTC_ICDICFR12_INTIICALI0_1_SHIFT (7u)
+#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT (8u)
+#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT (9u)
+#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT (10u)
+#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT (11u)
+#define INTC_ICDICFR12_INTIICRI1_0_SHIFT (12u)
+#define INTC_ICDICFR12_INTIICRI1_1_SHIFT (13u)
+#define INTC_ICDICFR12_INTIICTI1_0_SHIFT (14u)
+#define INTC_ICDICFR12_INTIICTI1_1_SHIFT (15u)
+#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT (16u)
+#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT (17u)
+#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT (18u)
+#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT (19u)
+#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT (20u)
+#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT (21u)
+#define INTC_ICDICFR12_INTIICALI1_0_SHIFT (22u)
+#define INTC_ICDICFR12_INTIICALI1_1_SHIFT (23u)
+#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT (24u)
+#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT (25u)
+#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT (26u)
+#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT (27u)
+#define INTC_ICDICFR12_INTIICRI2_0_SHIFT (28u)
+#define INTC_ICDICFR12_INTIICRI2_1_SHIFT (29u)
+#define INTC_ICDICFR12_INTIICTI2_0_SHIFT (30u)
+#define INTC_ICDICFR12_INTIICTI2_1_SHIFT (31u)
+
+#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT (0u)
+#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT (1u)
+#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT (2u)
+#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT (3u)
+#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT (4u)
+#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT (5u)
+#define INTC_ICDICFR13_INTIICALI2_0_SHIFT (6u)
+#define INTC_ICDICFR13_INTIICALI2_1_SHIFT (7u)
+#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT (8u)
+#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT (9u)
+#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT (10u)
+#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT (11u)
+#define INTC_ICDICFR13_INTIICRI3_0_SHIFT (12u)
+#define INTC_ICDICFR13_INTIICRI3_1_SHIFT (13u)
+#define INTC_ICDICFR13_INTIICTI3_0_SHIFT (14u)
+#define INTC_ICDICFR13_INTIICTI3_1_SHIFT (15u)
+#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT (16u)
+#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT (17u)
+#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT (18u)
+#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT (19u)
+#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT (20u)
+#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT (21u)
+#define INTC_ICDICFR13_INTIICALI3_0_SHIFT (22u)
+#define INTC_ICDICFR13_INTIICALI3_1_SHIFT (23u)
+#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT (24u)
+#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT (25u)
+#define INTC_ICDICFR13_BRI0_0_SHIFT (26u)
+#define INTC_ICDICFR13_BRI0_1_SHIFT (27u)
+#define INTC_ICDICFR13_ERI0_0_SHIFT (28u)
+#define INTC_ICDICFR13_ERI0_1_SHIFT (29u)
+#define INTC_ICDICFR13_RXI0_0_SHIFT (30u)
+#define INTC_ICDICFR13_RXI0_1_SHIFT (31u)
+
+#define INTC_ICDICFR14_TXI0_0_SHIFT (0u)
+#define INTC_ICDICFR14_TXI0_1_SHIFT (1u)
+#define INTC_ICDICFR14_BRI1_0_SHIFT (2u)
+#define INTC_ICDICFR14_BRI1_1_SHIFT (3u)
+#define INTC_ICDICFR14_ERI1_0_SHIFT (4u)
+#define INTC_ICDICFR14_ERI1_1_SHIFT (5u)
+#define INTC_ICDICFR14_RXI1_0_SHIFT (6u)
+#define INTC_ICDICFR14_RXI1_1_SHIFT (7u)
+#define INTC_ICDICFR14_TXI1_0_SHIFT (8u)
+#define INTC_ICDICFR14_TXI1_1_SHIFT (9u)
+#define INTC_ICDICFR14_BRI2_0_SHIFT (10u)
+#define INTC_ICDICFR14_BRI2_1_SHIFT (11u)
+#define INTC_ICDICFR14_ERI2_0_SHIFT (12u)
+#define INTC_ICDICFR14_ERI2_1_SHIFT (13u)
+#define INTC_ICDICFR14_RXI2_0_SHIFT (14u)
+#define INTC_ICDICFR14_RXI2_1_SHIFT (15u)
+#define INTC_ICDICFR14_TXI2_0_SHIFT (16u)
+#define INTC_ICDICFR14_TXI2_1_SHIFT (17u)
+#define INTC_ICDICFR14_BRI3_0_SHIFT (18u)
+#define INTC_ICDICFR14_BRI3_1_SHIFT (19u)
+#define INTC_ICDICFR14_ERI3_0_SHIFT (20u)
+#define INTC_ICDICFR14_ERI3_1_SHIFT (21u)
+#define INTC_ICDICFR14_RXI3_0_SHIFT (22u)
+#define INTC_ICDICFR14_RXI3_1_SHIFT (23u)
+#define INTC_ICDICFR14_TXI3_0_SHIFT (24u)
+#define INTC_ICDICFR14_TXI3_1_SHIFT (25u)
+#define INTC_ICDICFR14_BRI4_0_SHIFT (26u)
+#define INTC_ICDICFR14_BRI4_1_SHIFT (27u)
+#define INTC_ICDICFR14_ERI4_0_SHIFT (28u)
+#define INTC_ICDICFR14_ERI4_1_SHIFT (29u)
+#define INTC_ICDICFR14_RXI4_0_SHIFT (30u)
+#define INTC_ICDICFR14_RXI4_1_SHIFT (31u)
+
+#define INTC_ICDICFR15_TXI4_0_SHIFT (0u)
+#define INTC_ICDICFR15_TXI4_1_SHIFT (1u)
+#define INTC_ICDICFR15_BRI5_0_SHIFT (2u)
+#define INTC_ICDICFR15_BRI5_1_SHIFT (3u)
+#define INTC_ICDICFR15_ERI5_0_SHIFT (4u)
+#define INTC_ICDICFR15_ERI5_1_SHIFT (5u)
+#define INTC_ICDICFR15_RXI5_0_SHIFT (6u)
+#define INTC_ICDICFR15_RXI5_1_SHIFT (7u)
+#define INTC_ICDICFR15_TXI5_0_SHIFT (8u)
+#define INTC_ICDICFR15_TXI5_1_SHIFT (9u)
+#define INTC_ICDICFR15_BRI6_0_SHIFT (10u)
+#define INTC_ICDICFR15_BRI6_1_SHIFT (11u)
+#define INTC_ICDICFR15_ERI6_0_SHIFT (12u)
+#define INTC_ICDICFR15_ERI6_1_SHIFT (13u)
+#define INTC_ICDICFR15_RXI6_0_SHIFT (14u)
+#define INTC_ICDICFR15_RXI6_1_SHIFT (15u)
+#define INTC_ICDICFR15_TXI6_0_SHIFT (16u)
+#define INTC_ICDICFR15_TXI6_1_SHIFT (17u)
+#define INTC_ICDICFR15_BRI7_0_SHIFT (18u)
+#define INTC_ICDICFR15_BRI7_1_SHIFT (19u)
+#define INTC_ICDICFR15_ERI7_0_SHIFT (20u)
+#define INTC_ICDICFR15_ERI7_1_SHIFT (21u)
+#define INTC_ICDICFR15_RXI7_0_SHIFT (22u)
+#define INTC_ICDICFR15_RXI7_1_SHIFT (23u)
+#define INTC_ICDICFR15_TXI7_0_SHIFT (24u)
+#define INTC_ICDICFR15_TXI7_1_SHIFT (25u)
+#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT (26u)
+#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT (27u)
+#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT (28u)
+#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT (29u)
+#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT (30u)
+#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT (31u)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT (0u)
+#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT (1u)
+#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT (2u)
+#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT (3u)
+#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT (4u)
+#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT (5u)
+#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT (6u)
+#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT (7u)
+#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT (8u)
+#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT (9u)
+#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT (10u)
+#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT (11u)
+#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT (12u)
+#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT (13u)
+#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT (14u)
+#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT (15u)
+#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT (16u)
+#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT (17u)
+#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT (18u)
+#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT (19u)
+#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT (20u)
+#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT (21u)
+#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT (22u)
+#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT (23u)
+#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT (24u)
+#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT (25u)
+#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT (26u)
+#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT (27u)
+#define INTC_ICDICFR16_SPEI0_0_SHIFT (28u)
+#define INTC_ICDICFR16_SPEI0_1_SHIFT (29u)
+#define INTC_ICDICFR16_SPRI0_0_SHIFT (30u)
+#define INTC_ICDICFR16_SPRI0_1_SHIFT (31u)
+
+#define INTC_ICDICFR17_SPTI0_0_SHIFT (0u)
+#define INTC_ICDICFR17_SPTI0_1_SHIFT (1u)
+#define INTC_ICDICFR17_SPEI1_0_SHIFT (2u)
+#define INTC_ICDICFR17_SPEI1_1_SHIFT (3u)
+#define INTC_ICDICFR17_SPRI1_0_SHIFT (4u)
+#define INTC_ICDICFR17_SPRI1_1_SHIFT (5u)
+#define INTC_ICDICFR17_SPTI1_0_SHIFT (6u)
+#define INTC_ICDICFR17_SPTI1_1_SHIFT (7u)
+#define INTC_ICDICFR17_SPEI2_0_SHIFT (8u)
+#define INTC_ICDICFR17_SPEI2_1_SHIFT (9u)
+#define INTC_ICDICFR17_SPRI2_0_SHIFT (10u)
+#define INTC_ICDICFR17_SPRI2_1_SHIFT (11u)
+#define INTC_ICDICFR17_SPTI2_0_SHIFT (12u)
+#define INTC_ICDICFR17_SPTI2_1_SHIFT (13u)
+#define INTC_ICDICFR17_SPEI3_0_SHIFT (14u)
+#define INTC_ICDICFR17_SPEI3_1_SHIFT (15u)
+#define INTC_ICDICFR17_SPRI3_0_SHIFT (16u)
+#define INTC_ICDICFR17_SPRI3_1_SHIFT (17u)
+#define INTC_ICDICFR17_SPTI3_0_SHIFT (18u)
+#define INTC_ICDICFR17_SPTI3_1_SHIFT (19u)
+#define INTC_ICDICFR17_SPEI4_0_SHIFT (20u)
+#define INTC_ICDICFR17_SPEI4_1_SHIFT (21u)
+#define INTC_ICDICFR17_SPRI4_0_SHIFT (22u)
+#define INTC_ICDICFR17_SPRI4_1_SHIFT (23u)
+#define INTC_ICDICFR17_SPTI4_0_SHIFT (24u)
+#define INTC_ICDICFR17_SPTI4_1_SHIFT (25u)
+#define INTC_ICDICFR17_IEBBTD_0_SHIFT (26u)
+#define INTC_ICDICFR17_IEBBTD_1_SHIFT (27u)
+#define INTC_ICDICFR17_IEBBTERR_0_SHIFT (28u)
+#define INTC_ICDICFR17_IEBBTERR_1_SHIFT (29u)
+#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT (30u)
+#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT (31u)
+
+#define INTC_ICDICFR18_IEBBTV_0_SHIFT (0u)
+#define INTC_ICDICFR18_IEBBTV_1_SHIFT (1u)
+#define INTC_ICDICFR18_ISY_0_SHIFT (2u)
+#define INTC_ICDICFR18_ISY_1_SHIFT (3u)
+#define INTC_ICDICFR18_IERR_0_SHIFT (4u)
+#define INTC_ICDICFR18_IERR_1_SHIFT (5u)
+#define INTC_ICDICFR18_ITARG_0_SHIFT (6u)
+#define INTC_ICDICFR18_ITARG_1_SHIFT (7u)
+#define INTC_ICDICFR18_ISEC_0_SHIFT (8u)
+#define INTC_ICDICFR18_ISEC_1_SHIFT (9u)
+#define INTC_ICDICFR18_IBUF_0_SHIFT (10u)
+#define INTC_ICDICFR18_IBUF_1_SHIFT (11u)
+#define INTC_ICDICFR18_IREADY_0_SHIFT (12u)
+#define INTC_ICDICFR18_IREADY_1_SHIFT (13u)
+#define INTC_ICDICFR18_FLSTE_0_SHIFT (14u)
+#define INTC_ICDICFR18_FLSTE_1_SHIFT (15u)
+#define INTC_ICDICFR18_FLTENDI_0_SHIFT (16u)
+#define INTC_ICDICFR18_FLTENDI_1_SHIFT (17u)
+#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT (18u)
+#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT (19u)
+#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT (20u)
+#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT (21u)
+#define INTC_ICDICFR18_MMC0_0_SHIFT (22u)
+#define INTC_ICDICFR18_MMC0_1_SHIFT (23u)
+#define INTC_ICDICFR18_MMC1_0_SHIFT (24u)
+#define INTC_ICDICFR18_MMC1_1_SHIFT (25u)
+#define INTC_ICDICFR18_MMC2_0_SHIFT (26u)
+#define INTC_ICDICFR18_MMC2_1_SHIFT (27u)
+#define INTC_ICDICFR18_SDHI0_3_0_SHIFT (28u)
+#define INTC_ICDICFR18_SDHI0_3_1_SHIFT (29u)
+#define INTC_ICDICFR18_SDHI0_0_0_SHIFT (30u)
+#define INTC_ICDICFR18_SDHI0_0_1_SHIFT (31u)
+
+#define INTC_ICDICFR19_SDHI0_1_0_SHIFT (0u)
+#define INTC_ICDICFR19_SDHI0_1_1_SHIFT (1u)
+#define INTC_ICDICFR19_SDHI1_3_0_SHIFT (2u)
+#define INTC_ICDICFR19_SDHI1_3_1_SHIFT (3u)
+#define INTC_ICDICFR19_SDHI1_0_0_SHIFT (4u)
+#define INTC_ICDICFR19_SDHI1_0_1_SHIFT (5u)
+#define INTC_ICDICFR19_SDHI1_1_0_SHIFT (6u)
+#define INTC_ICDICFR19_SDHI1_1_1_SHIFT (7u)
+#define INTC_ICDICFR19_ARM_0_SHIFT (8u)
+#define INTC_ICDICFR19_ARM_1_SHIFT (9u)
+#define INTC_ICDICFR19_PRD_0_SHIFT (10u)
+#define INTC_ICDICFR19_PRD_1_SHIFT (11u)
+#define INTC_ICDICFR19_CUP_0_SHIFT (12u)
+#define INTC_ICDICFR19_CUP_1_SHIFT (13u)
+#define INTC_ICDICFR19_SCUAI0_0_SHIFT (14u)
+#define INTC_ICDICFR19_SCUAI0_1_SHIFT (15u)
+#define INTC_ICDICFR19_SCUAI1_0_SHIFT (16u)
+#define INTC_ICDICFR19_SCUAI1_1_SHIFT (17u)
+#define INTC_ICDICFR19_SCUFDI0_0_SHIFT (18u)
+#define INTC_ICDICFR19_SCUFDI0_1_SHIFT (19u)
+#define INTC_ICDICFR19_SCUFDI1_0_SHIFT (20u)
+#define INTC_ICDICFR19_SCUFDI1_1_SHIFT (21u)
+#define INTC_ICDICFR19_SCUFDI2_0_SHIFT (22u)
+#define INTC_ICDICFR19_SCUFDI2_1_SHIFT (23u)
+#define INTC_ICDICFR19_SCUFDI3_0_SHIFT (24u)
+#define INTC_ICDICFR19_SCUFDI3_1_SHIFT (25u)
+#define INTC_ICDICFR19_SCUFUI0_0_SHIFT (26u)
+#define INTC_ICDICFR19_SCUFUI0_1_SHIFT (27u)
+#define INTC_ICDICFR19_SCUFUI1_0_SHIFT (28u)
+#define INTC_ICDICFR19_SCUFUI1_1_SHIFT (29u)
+#define INTC_ICDICFR19_SCUFUI2_0_SHIFT (30u)
+#define INTC_ICDICFR19_SCUFUI2_1_SHIFT (31u)
+
+#define INTC_ICDICFR20_SCUFUI3_0_SHIFT (0u)
+#define INTC_ICDICFR20_SCUFUI3_1_SHIFT (1u)
+#define INTC_ICDICFR20_SCUDVI0_0_SHIFT (2u)
+#define INTC_ICDICFR20_SCUDVI0_1_SHIFT (3u)
+#define INTC_ICDICFR20_SCUDVI1_0_SHIFT (4u)
+#define INTC_ICDICFR20_SCUDVI1_1_SHIFT (5u)
+#define INTC_ICDICFR20_SCUDVI2_0_SHIFT (6u)
+#define INTC_ICDICFR20_SCUDVI2_1_SHIFT (7u)
+#define INTC_ICDICFR20_SCUDVI3_0_SHIFT (8u)
+#define INTC_ICDICFR20_SCUDVI3_1_SHIFT (9u)
+#define INTC_ICDICFR20_MLB_CINT_0_SHIFT (10u)
+#define INTC_ICDICFR20_MLB_CINT_1_SHIFT (11u)
+#define INTC_ICDICFR20_MLB_SINT_0_SHIFT (12u)
+#define INTC_ICDICFR20_MLB_SINT_1_SHIFT (13u)
+#define INTC_ICDICFR20_DRC0_0_SHIFT (14u)
+#define INTC_ICDICFR20_DRC0_1_SHIFT (15u)
+#define INTC_ICDICFR20_DRC1_0_SHIFT (16u)
+#define INTC_ICDICFR20_DRC1_1_SHIFT (17u)
+#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT (22u)
+#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT (23u)
+#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT (24u)
+#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT (25u)
+#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT (26u)
+#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT (27u)
+#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT (28u)
+#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT (29u)
+#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT (30u)
+#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT (31u)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT (0u)
+#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT (1u)
+#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT (2u)
+#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT (3u)
+#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT (4u)
+#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT (5u)
+#define INTC_ICDICFR21_ERI0_0_SHIFT (22u)
+#define INTC_ICDICFR21_ERI0_1_SHIFT (23u)
+#define INTC_ICDICFR21_RXI0_0_SHIFT (24u)
+#define INTC_ICDICFR21_RXI0_1_SHIFT (25u)
+#define INTC_ICDICFR21_TXI0_0_SHIFT (26u)
+#define INTC_ICDICFR21_TXI0_1_SHIFT (27u)
+#define INTC_ICDICFR21_TEI0_0_SHIFT (28u)
+#define INTC_ICDICFR21_TEI0_1_SHIFT (29u)
+#define INTC_ICDICFR21_ERI1_0_SHIFT (30u)
+#define INTC_ICDICFR21_ERI1_1_SHIFT (31u)
+
+#define INTC_ICDICFR22_RXI1_0_SHIFT (0u)
+#define INTC_ICDICFR22_RXI1_1_SHIFT (1u)
+#define INTC_ICDICFR22_TXI1_0_SHIFT (2u)
+#define INTC_ICDICFR22_TXI1_1_SHIFT (3u)
+#define INTC_ICDICFR22_TEI1_0_SHIFT (4u)
+#define INTC_ICDICFR22_TEI1_1_SHIFT (5u)
+#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT (6u)
+#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT (7u)
+#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT (8u)
+#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT (9u)
+#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT (10u)
+#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT (11u)
+#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT (12u)
+#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT (13u)
+#define INTC_ICDICFR22_ETHERI_0_SHIFT (14u)
+#define INTC_ICDICFR22_ETHERI_1_SHIFT (15u)
+#define INTC_ICDICFR22_CEUI_0_SHIFT (24u)
+#define INTC_ICDICFR22_CEUI_1_SHIFT (25u)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT (26u)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT (27u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT (28u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT (29u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT (30u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT (31u)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT (0u)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT (1u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT (4u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT (5u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT (8u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT (9u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT (10u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT (11u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT (12u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT (13u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT (14u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT (15u)
+#define INTC_ICDICFR24_PRRI_0_SHIFT (16u)
+#define INTC_ICDICFR24_PRRI_1_SHIFT (17u)
+#define INTC_ICDICFR24_IFEI0_0_SHIFT (18u)
+#define INTC_ICDICFR24_IFEI0_1_SHIFT (19u)
+#define INTC_ICDICFR24_OFFI0_0_SHIFT (20u)
+#define INTC_ICDICFR24_OFFI0_1_SHIFT (21u)
+#define INTC_ICDICFR24_PFVEI0_0_SHIFT (22u)
+#define INTC_ICDICFR24_PFVEI0_1_SHIFT (23u)
+#define INTC_ICDICFR24_IFEI1_0_SHIFT (24u)
+#define INTC_ICDICFR24_IFEI1_1_SHIFT (25u)
+#define INTC_ICDICFR24_OFFI1_0_SHIFT (26u)
+#define INTC_ICDICFR24_OFFI1_1_SHIFT (27u)
+#define INTC_ICDICFR24_PFVEI1_0_SHIFT (28u)
+#define INTC_ICDICFR24_PFVEI1_1_SHIFT (29u)
+
+#define INTC_ICDICFR26_TINT0_0_SHIFT (0u)
+#define INTC_ICDICFR26_TINT0_1_SHIFT (1u)
+#define INTC_ICDICFR26_TINT1_0_SHIFT (2u)
+#define INTC_ICDICFR26_TINT1_1_SHIFT (3u)
+#define INTC_ICDICFR26_TINT2_0_SHIFT (4u)
+#define INTC_ICDICFR26_TINT2_1_SHIFT (5u)
+#define INTC_ICDICFR26_TINT3_0_SHIFT (6u)
+#define INTC_ICDICFR26_TINT3_1_SHIFT (7u)
+#define INTC_ICDICFR26_TINT4_0_SHIFT (8u)
+#define INTC_ICDICFR26_TINT4_1_SHIFT (9u)
+#define INTC_ICDICFR26_TINT5_0_SHIFT (10u)
+#define INTC_ICDICFR26_TINT5_1_SHIFT (11u)
+#define INTC_ICDICFR26_TINT6_0_SHIFT (12u)
+#define INTC_ICDICFR26_TINT6_1_SHIFT (13u)
+#define INTC_ICDICFR26_TINT7_0_SHIFT (14u)
+#define INTC_ICDICFR26_TINT7_1_SHIFT (15u)
+#define INTC_ICDICFR26_TINT8_0_SHIFT (16u)
+#define INTC_ICDICFR26_TINT8_1_SHIFT (17u)
+#define INTC_ICDICFR26_TINT9_0_SHIFT (18u)
+#define INTC_ICDICFR26_TINT9_1_SHIFT (19u)
+#define INTC_ICDICFR26_TINT10_0_SHIFT (20u)
+#define INTC_ICDICFR26_TINT10_1_SHIFT (21u)
+#define INTC_ICDICFR26_TINT11_0_SHIFT (22u)
+#define INTC_ICDICFR26_TINT11_1_SHIFT (23u)
+#define INTC_ICDICFR26_TINT12_0_SHIFT (24u)
+#define INTC_ICDICFR26_TINT12_1_SHIFT (25u)
+#define INTC_ICDICFR26_TINT13_0_SHIFT (26u)
+#define INTC_ICDICFR26_TINT13_1_SHIFT (27u)
+#define INTC_ICDICFR26_TINT14_0_SHIFT (28u)
+#define INTC_ICDICFR26_TINT14_1_SHIFT (29u)
+#define INTC_ICDICFR26_TINT15_0_SHIFT (30u)
+#define INTC_ICDICFR26_TINT15_1_SHIFT (31u)
+
+#define INTC_ICDICFR27_TINT16_0_SHIFT (0u)
+#define INTC_ICDICFR27_TINT16_1_SHIFT (1u)
+#define INTC_ICDICFR27_TINT17_0_SHIFT (2u)
+#define INTC_ICDICFR27_TINT17_1_SHIFT (3u)
+#define INTC_ICDICFR27_TINT18_0_SHIFT (4u)
+#define INTC_ICDICFR27_TINT18_1_SHIFT (5u)
+#define INTC_ICDICFR27_TINT19_0_SHIFT (6u)
+#define INTC_ICDICFR27_TINT19_1_SHIFT (7u)
+#define INTC_ICDICFR27_TINT20_0_SHIFT (8u)
+#define INTC_ICDICFR27_TINT20_1_SHIFT (9u)
+#define INTC_ICDICFR27_TINT21_0_SHIFT (10u)
+#define INTC_ICDICFR27_TINT21_1_SHIFT (11u)
+#define INTC_ICDICFR27_TINT22_0_SHIFT (12u)
+#define INTC_ICDICFR27_TINT22_1_SHIFT (13u)
+#define INTC_ICDICFR27_TINT23_0_SHIFT (14u)
+#define INTC_ICDICFR27_TINT23_1_SHIFT (15u)
+#define INTC_ICDICFR27_TINT24_0_SHIFT (16u)
+#define INTC_ICDICFR27_TINT24_1_SHIFT (17u)
+#define INTC_ICDICFR27_TINT25_0_SHIFT (18u)
+#define INTC_ICDICFR27_TINT25_1_SHIFT (19u)
+#define INTC_ICDICFR27_TINT26_0_SHIFT (20u)
+#define INTC_ICDICFR27_TINT26_1_SHIFT (21u)
+#define INTC_ICDICFR27_TINT27_0_SHIFT (22u)
+#define INTC_ICDICFR27_TINT27_1_SHIFT (23u)
+#define INTC_ICDICFR27_TINT28_0_SHIFT (24u)
+#define INTC_ICDICFR27_TINT28_1_SHIFT (25u)
+#define INTC_ICDICFR27_TINT29_0_SHIFT (26u)
+#define INTC_ICDICFR27_TINT29_1_SHIFT (27u)
+#define INTC_ICDICFR27_TINT30_0_SHIFT (28u)
+#define INTC_ICDICFR27_TINT30_1_SHIFT (29u)
+#define INTC_ICDICFR27_TINT31_0_SHIFT (30u)
+#define INTC_ICDICFR27_TINT31_1_SHIFT (31u)
+
+#define INTC_ICDICFR28_TINT32_0_SHIFT (0u)
+#define INTC_ICDICFR28_TINT32_1_SHIFT (1u)
+#define INTC_ICDICFR28_TINT33_0_SHIFT (2u)
+#define INTC_ICDICFR28_TINT33_1_SHIFT (3u)
+#define INTC_ICDICFR28_TINT34_0_SHIFT (4u)
+#define INTC_ICDICFR28_TINT34_1_SHIFT (5u)
+#define INTC_ICDICFR28_TINT35_0_SHIFT (6u)
+#define INTC_ICDICFR28_TINT35_1_SHIFT (7u)
+#define INTC_ICDICFR28_TINT36_0_SHIFT (8u)
+#define INTC_ICDICFR28_TINT36_1_SHIFT (9u)
+#define INTC_ICDICFR28_TINT37_0_SHIFT (10u)
+#define INTC_ICDICFR28_TINT37_1_SHIFT (11u)
+#define INTC_ICDICFR28_TINT38_0_SHIFT (12u)
+#define INTC_ICDICFR28_TINT38_1_SHIFT (13u)
+#define INTC_ICDICFR28_TINT39_0_SHIFT (14u)
+#define INTC_ICDICFR28_TINT39_1_SHIFT (15u)
+#define INTC_ICDICFR28_TINT40_0_SHIFT (16u)
+#define INTC_ICDICFR28_TINT40_1_SHIFT (17u)
+#define INTC_ICDICFR28_TINT41_0_SHIFT (18u)
+#define INTC_ICDICFR28_TINT41_1_SHIFT (19u)
+#define INTC_ICDICFR28_TINT42_0_SHIFT (20u)
+#define INTC_ICDICFR28_TINT42_1_SHIFT (21u)
+#define INTC_ICDICFR28_TINT43_0_SHIFT (22u)
+#define INTC_ICDICFR28_TINT43_1_SHIFT (23u)
+#define INTC_ICDICFR28_TINT44_0_SHIFT (24u)
+#define INTC_ICDICFR28_TINT44_1_SHIFT (25u)
+#define INTC_ICDICFR28_TINT45_0_SHIFT (26u)
+#define INTC_ICDICFR28_TINT45_1_SHIFT (27u)
+#define INTC_ICDICFR28_TINT46_0_SHIFT (28u)
+#define INTC_ICDICFR28_TINT46_1_SHIFT (29u)
+#define INTC_ICDICFR28_TINT47_0_SHIFT (30u)
+#define INTC_ICDICFR28_TINT47_1_SHIFT (31u)
+
+#define INTC_ICDICFR29_TINT48_0_SHIFT (0u)
+#define INTC_ICDICFR29_TINT48_1_SHIFT (1u)
+#define INTC_ICDICFR29_TINT49_0_SHIFT (2u)
+#define INTC_ICDICFR29_TINT49_1_SHIFT (3u)
+#define INTC_ICDICFR29_TINT50_0_SHIFT (4u)
+#define INTC_ICDICFR29_TINT50_1_SHIFT (5u)
+#define INTC_ICDICFR29_TINT51_0_SHIFT (6u)
+#define INTC_ICDICFR29_TINT51_1_SHIFT (7u)
+#define INTC_ICDICFR29_TINT52_0_SHIFT (8u)
+#define INTC_ICDICFR29_TINT52_1_SHIFT (9u)
+#define INTC_ICDICFR29_TINT53_0_SHIFT (10u)
+#define INTC_ICDICFR29_TINT53_1_SHIFT (11u)
+#define INTC_ICDICFR29_TINT54_0_SHIFT (12u)
+#define INTC_ICDICFR29_TINT54_1_SHIFT (13u)
+#define INTC_ICDICFR29_TINT55_0_SHIFT (14u)
+#define INTC_ICDICFR29_TINT55_1_SHIFT (15u)
+#define INTC_ICDICFR29_TINT56_0_SHIFT (16u)
+#define INTC_ICDICFR29_TINT56_1_SHIFT (17u)
+#define INTC_ICDICFR29_TINT57_0_SHIFT (18u)
+#define INTC_ICDICFR29_TINT57_1_SHIFT (19u)
+#define INTC_ICDICFR29_TINT58_0_SHIFT (20u)
+#define INTC_ICDICFR29_TINT58_1_SHIFT (21u)
+#define INTC_ICDICFR29_TINT59_0_SHIFT (22u)
+#define INTC_ICDICFR29_TINT59_1_SHIFT (23u)
+#define INTC_ICDICFR29_TINT60_0_SHIFT (24u)
+#define INTC_ICDICFR29_TINT60_1_SHIFT (25u)
+#define INTC_ICDICFR29_TINT61_0_SHIFT (26u)
+#define INTC_ICDICFR29_TINT61_1_SHIFT (27u)
+#define INTC_ICDICFR29_TINT62_0_SHIFT (28u)
+#define INTC_ICDICFR29_TINT62_1_SHIFT (29u)
+#define INTC_ICDICFR29_TINT63_0_SHIFT (30u)
+#define INTC_ICDICFR29_TINT63_1_SHIFT (31u)
+
+#define INTC_ICDICFR30_TINT64_0_SHIFT (0u)
+#define INTC_ICDICFR30_TINT64_1_SHIFT (1u)
+#define INTC_ICDICFR30_TINT65_0_SHIFT (2u)
+#define INTC_ICDICFR30_TINT65_1_SHIFT (3u)
+#define INTC_ICDICFR30_TINT66_0_SHIFT (4u)
+#define INTC_ICDICFR30_TINT66_1_SHIFT (5u)
+#define INTC_ICDICFR30_TINT67_0_SHIFT (6u)
+#define INTC_ICDICFR30_TINT67_1_SHIFT (7u)
+#define INTC_ICDICFR30_TINT68_0_SHIFT (8u)
+#define INTC_ICDICFR30_TINT68_1_SHIFT (9u)
+#define INTC_ICDICFR30_TINT69_0_SHIFT (10u)
+#define INTC_ICDICFR30_TINT69_1_SHIFT (11u)
+#define INTC_ICDICFR30_TINT70_0_SHIFT (12u)
+#define INTC_ICDICFR30_TINT70_1_SHIFT (13u)
+#define INTC_ICDICFR30_TINT71_0_SHIFT (14u)
+#define INTC_ICDICFR30_TINT71_1_SHIFT (15u)
+#define INTC_ICDICFR30_TINT72_0_SHIFT (16u)
+#define INTC_ICDICFR30_TINT72_1_SHIFT (17u)
+#define INTC_ICDICFR30_TINT73_0_SHIFT (18u)
+#define INTC_ICDICFR30_TINT73_1_SHIFT (19u)
+#define INTC_ICDICFR30_TINT74_0_SHIFT (20u)
+#define INTC_ICDICFR30_TINT74_1_SHIFT (21u)
+#define INTC_ICDICFR30_TINT75_0_SHIFT (22u)
+#define INTC_ICDICFR30_TINT75_1_SHIFT (23u)
+#define INTC_ICDICFR30_TINT76_0_SHIFT (24u)
+#define INTC_ICDICFR30_TINT76_1_SHIFT (25u)
+#define INTC_ICDICFR30_TINT77_0_SHIFT (26u)
+#define INTC_ICDICFR30_TINT77_1_SHIFT (27u)
+#define INTC_ICDICFR30_TINT78_0_SHIFT (28u)
+#define INTC_ICDICFR30_TINT78_1_SHIFT (29u)
+#define INTC_ICDICFR30_TINT79_0_SHIFT (30u)
+#define INTC_ICDICFR30_TINT79_1_SHIFT (31u)
+
+#define INTC_ICDICFR31_TINT80_0_SHIFT (0u)
+#define INTC_ICDICFR31_TINT80_1_SHIFT (1u)
+#define INTC_ICDICFR31_TINT81_0_SHIFT (2u)
+#define INTC_ICDICFR31_TINT81_1_SHIFT (3u)
+#define INTC_ICDICFR31_TINT82_0_SHIFT (4u)
+#define INTC_ICDICFR31_TINT82_1_SHIFT (5u)
+#define INTC_ICDICFR31_TINT83_0_SHIFT (6u)
+#define INTC_ICDICFR31_TINT83_1_SHIFT (7u)
+#define INTC_ICDICFR31_TINT84_0_SHIFT (8u)
+#define INTC_ICDICFR31_TINT84_1_SHIFT (9u)
+#define INTC_ICDICFR31_TINT85_0_SHIFT (10u)
+#define INTC_ICDICFR31_TINT85_1_SHIFT (11u)
+#define INTC_ICDICFR31_TINT86_0_SHIFT (12u)
+#define INTC_ICDICFR31_TINT86_1_SHIFT (13u)
+#define INTC_ICDICFR31_TINT87_0_SHIFT (14u)
+#define INTC_ICDICFR31_TINT87_1_SHIFT (15u)
+#define INTC_ICDICFR31_TINT88_0_SHIFT (16u)
+#define INTC_ICDICFR31_TINT88_1_SHIFT (17u)
+#define INTC_ICDICFR31_TINT89_0_SHIFT (18u)
+#define INTC_ICDICFR31_TINT89_1_SHIFT (19u)
+#define INTC_ICDICFR31_TINT90_0_SHIFT (20u)
+#define INTC_ICDICFR31_TINT90_1_SHIFT (21u)
+#define INTC_ICDICFR31_TINT91_0_SHIFT (22u)
+#define INTC_ICDICFR31_TINT91_1_SHIFT (23u)
+#define INTC_ICDICFR31_TINT92_0_SHIFT (24u)
+#define INTC_ICDICFR31_TINT92_1_SHIFT (25u)
+#define INTC_ICDICFR31_TINT93_0_SHIFT (26u)
+#define INTC_ICDICFR31_TINT93_1_SHIFT (27u)
+#define INTC_ICDICFR31_TINT94_0_SHIFT (28u)
+#define INTC_ICDICFR31_TINT94_1_SHIFT (29u)
+#define INTC_ICDICFR31_TINT95_0_SHIFT (30u)
+#define INTC_ICDICFR31_TINT95_1_SHIFT (31u)
+
+#define INTC_ICDICFR32_TINT96_0_SHIFT (0u)
+#define INTC_ICDICFR32_TINT96_1_SHIFT (1u)
+#define INTC_ICDICFR32_TINT97_0_SHIFT (2u)
+#define INTC_ICDICFR32_TINT97_1_SHIFT (3u)
+#define INTC_ICDICFR32_TINT98_0_SHIFT (4u)
+#define INTC_ICDICFR32_TINT98_1_SHIFT (5u)
+#define INTC_ICDICFR32_TINT99_0_SHIFT (6u)
+#define INTC_ICDICFR32_TINT99_1_SHIFT (7u)
+#define INTC_ICDICFR32_TINT100_0_SHIFT (8u)
+#define INTC_ICDICFR32_TINT100_1_SHIFT (9u)
+#define INTC_ICDICFR32_TINT101_0_SHIFT (10u)
+#define INTC_ICDICFR32_TINT101_1_SHIFT (11u)
+#define INTC_ICDICFR32_TINT102_0_SHIFT (12u)
+#define INTC_ICDICFR32_TINT102_1_SHIFT (13u)
+#define INTC_ICDICFR32_TINT103_0_SHIFT (14u)
+#define INTC_ICDICFR32_TINT103_1_SHIFT (15u)
+#define INTC_ICDICFR32_TINT104_0_SHIFT (16u)
+#define INTC_ICDICFR32_TINT104_1_SHIFT (17u)
+#define INTC_ICDICFR32_TINT105_0_SHIFT (18u)
+#define INTC_ICDICFR32_TINT105_1_SHIFT (19u)
+#define INTC_ICDICFR32_TINT106_0_SHIFT (20u)
+#define INTC_ICDICFR32_TINT106_1_SHIFT (21u)
+#define INTC_ICDICFR32_TINT107_0_SHIFT (22u)
+#define INTC_ICDICFR32_TINT107_1_SHIFT (23u)
+#define INTC_ICDICFR32_TINT108_0_SHIFT (24u)
+#define INTC_ICDICFR32_TINT108_1_SHIFT (25u)
+#define INTC_ICDICFR32_TINT109_0_SHIFT (26u)
+#define INTC_ICDICFR32_TINT109_1_SHIFT (27u)
+#define INTC_ICDICFR32_TINT110_0_SHIFT (28u)
+#define INTC_ICDICFR32_TINT110_1_SHIFT (29u)
+#define INTC_ICDICFR32_TINT111_0_SHIFT (30u)
+#define INTC_ICDICFR32_TINT111_1_SHIFT (31u)
+
+#define INTC_ICDICFR33_TINT112_0_SHIFT (0u)
+#define INTC_ICDICFR33_TINT112_1_SHIFT (1u)
+#define INTC_ICDICFR33_TINT113_0_SHIFT (2u)
+#define INTC_ICDICFR33_TINT113_1_SHIFT (3u)
+#define INTC_ICDICFR33_TINT114_0_SHIFT (4u)
+#define INTC_ICDICFR33_TINT114_1_SHIFT (5u)
+#define INTC_ICDICFR33_TINT115_0_SHIFT (6u)
+#define INTC_ICDICFR33_TINT115_1_SHIFT (7u)
+#define INTC_ICDICFR33_TINT116_0_SHIFT (8u)
+#define INTC_ICDICFR33_TINT116_1_SHIFT (9u)
+#define INTC_ICDICFR33_TINT117_0_SHIFT (10u)
+#define INTC_ICDICFR33_TINT117_1_SHIFT (11u)
+#define INTC_ICDICFR33_TINT118_0_SHIFT (12u)
+#define INTC_ICDICFR33_TINT118_1_SHIFT (13u)
+#define INTC_ICDICFR33_TINT119_0_SHIFT (14u)
+#define INTC_ICDICFR33_TINT119_1_SHIFT (15u)
+#define INTC_ICDICFR33_TINT120_0_SHIFT (16u)
+#define INTC_ICDICFR33_TINT120_1_SHIFT (17u)
+#define INTC_ICDICFR33_TINT121_0_SHIFT (18u)
+#define INTC_ICDICFR33_TINT121_1_SHIFT (19u)
+#define INTC_ICDICFR33_TINT122_0_SHIFT (20u)
+#define INTC_ICDICFR33_TINT122_1_SHIFT (21u)
+#define INTC_ICDICFR33_TINT123_0_SHIFT (22u)
+#define INTC_ICDICFR33_TINT123_1_SHIFT (23u)
+#define INTC_ICDICFR33_TINT124_0_SHIFT (24u)
+#define INTC_ICDICFR33_TINT124_1_SHIFT (25u)
+#define INTC_ICDICFR33_TINT125_0_SHIFT (26u)
+#define INTC_ICDICFR33_TINT125_1_SHIFT (27u)
+#define INTC_ICDICFR33_TINT126_0_SHIFT (28u)
+#define INTC_ICDICFR33_TINT126_1_SHIFT (29u)
+#define INTC_ICDICFR33_TINT127_0_SHIFT (30u)
+#define INTC_ICDICFR33_TINT127_1_SHIFT (31u)
+
+#define INTC_ICDICFR34_TINT128_0_SHIFT (0u)
+#define INTC_ICDICFR34_TINT128_1_SHIFT (1u)
+#define INTC_ICDICFR34_TINT129_0_SHIFT (2u)
+#define INTC_ICDICFR34_TINT129_1_SHIFT (3u)
+#define INTC_ICDICFR34_TINT130_0_SHIFT (4u)
+#define INTC_ICDICFR34_TINT130_1_SHIFT (5u)
+#define INTC_ICDICFR34_TINT131_0_SHIFT (6u)
+#define INTC_ICDICFR34_TINT131_1_SHIFT (7u)
+#define INTC_ICDICFR34_TINT132_0_SHIFT (8u)
+#define INTC_ICDICFR34_TINT132_1_SHIFT (9u)
+#define INTC_ICDICFR34_TINT133_0_SHIFT (10u)
+#define INTC_ICDICFR34_TINT133_1_SHIFT (11u)
+#define INTC_ICDICFR34_TINT134_0_SHIFT (12u)
+#define INTC_ICDICFR34_TINT134_1_SHIFT (13u)
+#define INTC_ICDICFR34_TINT135_0_SHIFT (14u)
+#define INTC_ICDICFR34_TINT135_1_SHIFT (15u)
+#define INTC_ICDICFR34_TINT136_0_SHIFT (16u)
+#define INTC_ICDICFR34_TINT136_1_SHIFT (17u)
+#define INTC_ICDICFR34_TINT137_0_SHIFT (18u)
+#define INTC_ICDICFR34_TINT137_1_SHIFT (19u)
+#define INTC_ICDICFR34_TINT138_0_SHIFT (20u)
+#define INTC_ICDICFR34_TINT138_1_SHIFT (21u)
+#define INTC_ICDICFR34_TINT139_0_SHIFT (22u)
+#define INTC_ICDICFR34_TINT139_1_SHIFT (23u)
+#define INTC_ICDICFR34_TINT140_0_SHIFT (24u)
+#define INTC_ICDICFR34_TINT140_1_SHIFT (25u)
+#define INTC_ICDICFR34_TINT141_0_SHIFT (26u)
+#define INTC_ICDICFR34_TINT141_1_SHIFT (27u)
+#define INTC_ICDICFR34_TINT142_0_SHIFT (28u)
+#define INTC_ICDICFR34_TINT142_1_SHIFT (29u)
+#define INTC_ICDICFR34_TINT143_0_SHIFT (30u)
+#define INTC_ICDICFR34_TINT143_1_SHIFT (31u)
+
+#define INTC_ICDICFR35_TINT144_0_SHIFT (0u)
+#define INTC_ICDICFR35_TINT144_1_SHIFT (1u)
+#define INTC_ICDICFR35_TINT145_0_SHIFT (2u)
+#define INTC_ICDICFR35_TINT145_1_SHIFT (3u)
+#define INTC_ICDICFR35_TINT146_0_SHIFT (4u)
+#define INTC_ICDICFR35_TINT146_1_SHIFT (5u)
+#define INTC_ICDICFR35_TINT147_0_SHIFT (6u)
+#define INTC_ICDICFR35_TINT147_1_SHIFT (7u)
+#define INTC_ICDICFR35_TINT148_0_SHIFT (8u)
+#define INTC_ICDICFR35_TINT148_1_SHIFT (9u)
+#define INTC_ICDICFR35_TINT149_0_SHIFT (10u)
+#define INTC_ICDICFR35_TINT149_1_SHIFT (11u)
+#define INTC_ICDICFR35_TINT150_0_SHIFT (12u)
+#define INTC_ICDICFR35_TINT150_1_SHIFT (13u)
+#define INTC_ICDICFR35_TINT151_0_SHIFT (14u)
+#define INTC_ICDICFR35_TINT151_1_SHIFT (15u)
+#define INTC_ICDICFR35_TINT152_0_SHIFT (16u)
+#define INTC_ICDICFR35_TINT152_1_SHIFT (17u)
+#define INTC_ICDICFR35_TINT153_0_SHIFT (18u)
+#define INTC_ICDICFR35_TINT153_1_SHIFT (19u)
+#define INTC_ICDICFR35_TINT154_0_SHIFT (20u)
+#define INTC_ICDICFR35_TINT154_1_SHIFT (21u)
+#define INTC_ICDICFR35_TINT155_0_SHIFT (22u)
+#define INTC_ICDICFR35_TINT155_1_SHIFT (23u)
+#define INTC_ICDICFR35_TINT156_0_SHIFT (24u)
+#define INTC_ICDICFR35_TINT156_1_SHIFT (25u)
+#define INTC_ICDICFR35_TINT157_0_SHIFT (26u)
+#define INTC_ICDICFR35_TINT157_1_SHIFT (27u)
+#define INTC_ICDICFR35_TINT158_0_SHIFT (28u)
+#define INTC_ICDICFR35_TINT158_1_SHIFT (29u)
+#define INTC_ICDICFR35_TINT159_0_SHIFT (30u)
+#define INTC_ICDICFR35_TINT159_1_SHIFT (31u)
+
+#define INTC_ICDICFR36_TINT160_0_SHIFT (0u)
+#define INTC_ICDICFR36_TINT160_1_SHIFT (1u)
+#define INTC_ICDICFR36_TINT161_0_SHIFT (2u)
+#define INTC_ICDICFR36_TINT161_1_SHIFT (3u)
+#define INTC_ICDICFR36_TINT162_0_SHIFT (4u)
+#define INTC_ICDICFR36_TINT162_1_SHIFT (5u)
+#define INTC_ICDICFR36_TINT163_0_SHIFT (6u)
+#define INTC_ICDICFR36_TINT163_1_SHIFT (7u)
+#define INTC_ICDICFR36_TINT164_0_SHIFT (8u)
+#define INTC_ICDICFR36_TINT164_1_SHIFT (9u)
+#define INTC_ICDICFR36_TINT165_0_SHIFT (10u)
+#define INTC_ICDICFR36_TINT165_1_SHIFT (11u)
+#define INTC_ICDICFR36_TINT166_0_SHIFT (12u)
+#define INTC_ICDICFR36_TINT166_1_SHIFT (13u)
+#define INTC_ICDICFR36_TINT167_0_SHIFT (14u)
+#define INTC_ICDICFR36_TINT167_1_SHIFT (15u)
+#define INTC_ICDICFR36_TINT168_0_SHIFT (16u)
+#define INTC_ICDICFR36_TINT168_1_SHIFT (17u)
+#define INTC_ICDICFR36_TINT169_0_SHIFT (18u)
+#define INTC_ICDICFR36_TINT169_1_SHIFT (19u)
+#define INTC_ICDICFR36_TINT170_0_SHIFT (20u)
+#define INTC_ICDICFR36_TINT170_1_SHIFT (21u)
+
+#define INTC_ICDSGIR_SGIINTID_SHIFT (0u)
+#define INTC_ICDSGIR_SATT_SHIFT (15u)
+#define INTC_ICDSGIR_CPUTargetList_SHIFT (16u)
+#define INTC_ICDSGIR_TargetListFilter_SHIFT (24u)
+
+#define INTC_ICCICR_EnableS_SHIFT (0u)
+#define INTC_ICCICR_EnableNS_SHIFT (1u)
+#define INTC_ICCICR_AckCtl_SHIFT (2u)
+#define INTC_ICCICR_FIQEn_SHIFT (3u)
+#define INTC_ICCICR_SBPR_SHIFT (4u)
+
+#define INTC_ICCPMR_Priority_SHIFT (0u)
+
+#define INTC_ICCBPR_Binarypoint_SHIFT (0u)
+
+#define INTC_ICCIAR_ACKINTID_SHIFT (0u)
+#define INTC_ICCIAR_CPUID_SHIFT (10u)
+
+#define INTC_ICCEOIR_EOIINTID_SHIFT (0u)
+#define INTC_ICCEOIR_CPUID_SHIFT (10u)
+
+#define INTC_ICCRPR_Priority_SHIFT (0u)
+
+#define INTC_ICCHPIR_PENDINTID_SHIFT (0u)
+#define INTC_ICCHPIR_CPUID_SHIFT (10u)
+
+#define INTC_ICCABPR_Binarypoint_SHIFT (0u)
+
+#define INTC_ICCIIDR_Implementer_SHIFT (0u)
+#define INTC_ICCIIDR_Revision_SHIFT (12u)
+#define INTC_ICCIIDR_Architecture_version_SHIFT (16u)
+#define INTC_ICCIIDR_ProductID_SHIFT (20u)
+
+#define INTC_ICR0_NMIF_SHIFT (1u)
+#define INTC_ICR0_NMIE_SHIFT (8u)
+#define INTC_ICR0_NMIL_SHIFT (15u)
+
+#define INTC_ICR1_IRQ00S_SHIFT (0u)
+#define INTC_ICR1_IRQ01S_SHIFT (1u)
+#define INTC_ICR1_IRQ10S_SHIFT (2u)
+#define INTC_ICR1_IRQ11S_SHIFT (3u)
+#define INTC_ICR1_IRQ20S_SHIFT (4u)
+#define INTC_ICR1_IRQ21S_SHIFT (5u)
+#define INTC_ICR1_IRQ30S_SHIFT (6u)
+#define INTC_ICR1_IRQ31S_SHIFT (7u)
+#define INTC_ICR1_IRQ40S_SHIFT (8u)
+#define INTC_ICR1_IRQ41S_SHIFT (9u)
+#define INTC_ICR1_IRQ50S_SHIFT (10u)
+#define INTC_ICR1_IRQ51S_SHIFT (11u)
+#define INTC_ICR1_IRQ60S_SHIFT (12u)
+#define INTC_ICR1_IRQ61S_SHIFT (13u)
+#define INTC_ICR1_IRQ70S_SHIFT (14u)
+#define INTC_ICR1_IRQ71S_SHIFT (15u)
+
+#define INTC_IRQRR_IRQ0F_SHIFT (0u)
+#define INTC_IRQRR_IRQ1F_SHIFT (1u)
+#define INTC_IRQRR_IRQ2F_SHIFT (2u)
+#define INTC_IRQRR_IRQ3F_SHIFT (3u)
+#define INTC_IRQRR_IRQ4F_SHIFT (4u)
+#define INTC_IRQRR_IRQ5F_SHIFT (5u)
+#define INTC_IRQRR_IRQ6F_SHIFT (6u)
+#define INTC_IRQRR_IRQ7F_SHIFT (7u)
+
+
+#endif /* INTC_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h
new file mode 100644
index 000000000..eea92773f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h
@@ -0,0 +1,462 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mtu2_iobitmask.h
+* $Rev: 1138 $
+* $Date:: 2014-08-08 11:03:56 +0900#$
+* Description : MTU2 register define header
+*******************************************************************************/
+#ifndef MTU2_IOBITMASK_H
+#define MTU2_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define MTU2_TCR_n_TPSC (0x07u)
+#define MTU2_TCR_n_CKEG (0x18u)
+#define MTU2_TCR_n_CCLR (0xE0u)
+
+#define MTU2_TMDR_n_MD (0x0Fu)
+
+#define MTU2_TIOR_2_IOA (0x0Fu)
+#define MTU2_TIOR_2_IOB (0xF0u)
+
+#define MTU2_TIER_n_TGIEA (0x01u)
+#define MTU2_TIER_n_TGIEB (0x02u)
+#define MTU2_TIER_n_TCIEV (0x10u)
+#define MTU2_TIER_2_TCIEU (0x20u)
+#define MTU2_TIER_n_TTGE (0x80u)
+
+#define MTU2_TSR_n_TGFA (0x01u)
+#define MTU2_TSR_n_TGFB (0x02u)
+#define MTU2_TSR_n_TCFV (0x10u)
+#define MTU2_TSR_2_TCFU (0x20u)
+#define MTU2_TSR_2_TCFD (0x80u)
+
+#define MTU2_TCNT_n_D (0xFFFFu)
+
+#define MTU2_TGRA_n_D (0xFFFFu)
+
+#define MTU2_TGRB_n_D (0xFFFFu)
+
+#define MTU2_TMDR_3_BFA (0x10u)
+#define MTU2_TMDR_3_BFB (0x20u)
+
+#define MTU2_TMDR_4_BFA (0x10u)
+#define MTU2_TMDR_4_BFB (0x20u)
+
+#define MTU2_TIORH_3_IOA (0x0Fu)
+#define MTU2_TIORH_3_IOB (0xF0u)
+
+#define MTU2_TIORL_3_IOC (0x0Fu)
+#define MTU2_TIORL_3_IOD (0xF0u)
+
+#define MTU2_TIORH_4_IOA (0x0Fu)
+#define MTU2_TIORH_4_IOB (0xF0u)
+
+#define MTU2_TIORL_4_IOC (0x0Fu)
+#define MTU2_TIORL_4_IOD (0xF0u)
+
+#define MTU2_TIER_3_TGIEC (0x04u)
+#define MTU2_TIER_3_TGIED (0x08u)
+
+#define MTU2_TIER_4_TGIEC (0x04u)
+#define MTU2_TIER_4_TGIED (0x08u)
+#define MTU2_TIER_4_TTGE2 (0x40u)
+
+#define MTU2_TOER_OE3B (0x01u)
+#define MTU2_TOER_OE4A (0x02u)
+#define MTU2_TOER_OE4B (0x04u)
+#define MTU2_TOER_OE3D (0x08u)
+#define MTU2_TOER_OE4C (0x10u)
+#define MTU2_TOER_OE4D (0x20u)
+
+#define MTU2_TGCR_UF (0x01u)
+#define MTU2_TGCR_VF (0x02u)
+#define MTU2_TGCR_WF (0x04u)
+#define MTU2_TGCR_FB (0x08u)
+#define MTU2_TGCR_P (0x10u)
+#define MTU2_TGCR_N (0x20u)
+#define MTU2_TGCR_BDC (0x40u)
+
+#define MTU2_TOCR1_OLSP (0x01u)
+#define MTU2_TOCR1_OLSN (0x02u)
+#define MTU2_TOCR1_TOCS (0x04u)
+#define MTU2_TOCR1_TOCL (0x08u)
+#define MTU2_TOCR1_PSYE (0x40u)
+
+#define MTU2_TOCR2_OLS1P (0x01u)
+#define MTU2_TOCR2_OLS1N (0x02u)
+#define MTU2_TOCR2_OLS2P (0x04u)
+#define MTU2_TOCR2_OLS2N (0x08u)
+#define MTU2_TOCR2_OLS3P (0x10u)
+#define MTU2_TOCR2_OLS3N (0x20u)
+#define MTU2_TOCR2_BF (0xC0u)
+
+#define MTU2_TCDR_D (0xFFFFu)
+
+#define MTU2_TDDR_D (0xFFFFu)
+
+#define MTU2_TCNTS_D (0xFFFFu)
+
+#define MTU2_TCBR_D (0xFFFFu)
+
+#define MTU2_TGRC_3_D (0xFFFFu)
+
+#define MTU2_TGRD_3_D (0xFFFFu)
+
+#define MTU2_TGRC_4_D (0xFFFFu)
+
+#define MTU2_TGRD_4_D (0xFFFFu)
+
+#define MTU2_TSR_3_TGFC (0x04u)
+#define MTU2_TSR_3_TGFD (0x08u)
+#define MTU2_TSR_3_TCFD (0x80u)
+
+#define MTU2_TSR_4_TGFC (0x04u)
+#define MTU2_TSR_4_TGFD (0x08u)
+#define MTU2_TSR_4_TCFD (0x80u)
+
+#define MTU2_TITCR_4VCOR (0x07u)
+#define MTU2_TITCR_T4VEN (0x08u)
+#define MTU2_TITCR_3ACOR (0x70u)
+#define MTU2_TITCR_T3AEN (0x80u)
+
+#define MTU2_TITCNT_4VCNT (0x07u)
+#define MTU2_TITCNT_3ACNT (0x70u)
+
+#define MTU2_TBTER_BTE (0x03u)
+
+#define MTU2_TDER_TDER (0x01u)
+
+#define MTU2_TOLBR_OLS1P (0x01u)
+#define MTU2_TOLBR_OLS1N (0x02u)
+#define MTU2_TOLBR_OLS2P (0x04u)
+#define MTU2_TOLBR_OLS2N (0x08u)
+#define MTU2_TOLBR_OLS3P (0x10u)
+#define MTU2_TOLBR_OLS3N (0x20u)
+
+#define MTU2_TBTM_3_TTSA (0x01u)
+#define MTU2_TBTM_3_TTSB (0x02u)
+
+#define MTU2_TBTM_4_TTSA (0x01u)
+#define MTU2_TBTM_4_TTSB (0x02u)
+
+#define MTU2_TADCR_ITB4VE (0x0001u)
+#define MTU2_TADCR_ITB3AE (0x0002u)
+#define MTU2_TADCR_ITA4VE (0x0004u)
+#define MTU2_TADCR_ITA3AE (0x0008u)
+#define MTU2_TADCR_DT4BE (0x0010u)
+#define MTU2_TADCR_UT4BE (0x0020u)
+#define MTU2_TADCR_DT4AE (0x0040u)
+#define MTU2_TADCR_UT4AE (0x0080u)
+#define MTU2_TADCR_BF (0xC000u)
+
+#define MTU2_TADCORA_4_D (0xFFFFu)
+
+#define MTU2_TADCORB_4_D (0xFFFFu)
+
+#define MTU2_TADCOBRA_4_D (0xFFFFu)
+
+#define MTU2_TADCOBRB_4_D (0xFFFFu)
+
+#define MTU2_TWCR_WRE (0x01u)
+#define MTU2_TWCR_CCE (0x80u)
+
+#define MTU2_TSTR_CST0 (0x01u)
+#define MTU2_TSTR_CST1 (0x02u)
+#define MTU2_TSTR_CST2 (0x04u)
+#define MTU2_TSTR_CST3 (0x40u)
+#define MTU2_TSTR_CST4 (0x80u)
+
+#define MTU2_TSYR_SYNC0 (0x01u)
+#define MTU2_TSYR_SYNC1 (0x02u)
+#define MTU2_TSYR_SYNC2 (0x04u)
+#define MTU2_TSYR_SYNC3 (0x40u)
+#define MTU2_TSYR_SYNC4 (0x80u)
+
+#define MTU2_TRWER_RWE (0x01u)
+
+#define MTU2_TMDR_0_BFA (0x10u)
+#define MTU2_TMDR_0_BFB (0x20u)
+#define MTU2_TMDR_0_BFE (0x40u)
+
+#define MTU2_TIORH_0_IOA (0x0Fu)
+#define MTU2_TIORH_0_IOB (0xF0u)
+
+#define MTU2_TIORL_0_IOC (0x0Fu)
+#define MTU2_TIORL_0_IOD (0xF0u)
+
+#define MTU2_TIER_0_TGIEC (0x04u)
+#define MTU2_TIER_0_TGIED (0x08u)
+
+#define MTU2_TSR_0_TGFC (0x04u)
+#define MTU2_TSR_0_TGFD (0x08u)
+
+#define MTU2_TGRC_0_D (0xFFFFu)
+
+#define MTU2_TGRD_0_D (0xFFFFu)
+
+#define MTU2_TGRE_0_D (0xFFFFu)
+
+#define MTU2_TGRF_0_D (0xFFFFu)
+
+#define MTU2_TIER2_0_TGIEE (0x01u)
+#define MTU2_TIER2_0_TGIEF (0x02u)
+
+#define MTU2_TSR2_0_TGFE (0x01u)
+#define MTU2_TSR2_0_TGFF (0x02u)
+
+#define MTU2_TBTM_0_TTSA (0x01u)
+#define MTU2_TBTM_0_TTSB (0x02u)
+#define MTU2_TBTM_0_TTSE (0x04u)
+
+#define MTU2_TIOR_1_IOA (0x0Fu)
+#define MTU2_TIOR_1_IOB (0xF0u)
+
+#define MTU2_TIER_1_TCIEU (0x20u)
+
+#define MTU2_TSR_1_TCFU (0x20u)
+#define MTU2_TSR_1_TCFD (0x80u)
+
+#define MTU2_TICCR_I1AE (0x01u)
+#define MTU2_TICCR_I1BE (0x02u)
+#define MTU2_TICCR_I2AE (0x04u)
+#define MTU2_TICCR_I2BE (0x08u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define MTU2_TCR_n_TPSC_SHIFT (0u)
+#define MTU2_TCR_n_CKEG_SHIFT (3u)
+#define MTU2_TCR_n_CCLR_SHIFT (5u)
+
+#define MTU2_TMDR_n_MD_SHIFT (0u)
+
+#define MTU2_TIOR_2_IOA_SHIFT (0u)
+#define MTU2_TIOR_2_IOB_SHIFT (4u)
+
+#define MTU2_TIER_n_TGIEA_SHIFT (0u)
+#define MTU2_TIER_n_TGIEB_SHIFT (1u)
+#define MTU2_TIER_n_TCIEV_SHIFT (4u)
+#define MTU2_TIER_2_TCIEU_SHIFT (5u)
+#define MTU2_TIER_n_TTGE_SHIFT (7u)
+
+#define MTU2_TSR_n_TGFA_SHIFT (0u)
+#define MTU2_TSR_n_TGFB_SHIFT (1u)
+#define MTU2_TSR_n_TCFV_SHIFT (4u)
+#define MTU2_TSR_2_TCFU_SHIFT (5u)
+#define MTU2_TSR_2_TCFD_SHIFT (7u)
+
+#define MTU2_TCNT_n_D_SHIFT (0u)
+
+#define MTU2_TGRA_n_D_SHIFT (0u)
+
+#define MTU2_TGRB_n_D_SHIFT (0u)
+
+#define MTU2_TMDR_3_BFA_SHIFT (4u)
+#define MTU2_TMDR_3_BFB_SHIFT (5u)
+
+#define MTU2_TMDR_4_BFA_SHIFT (4u)
+#define MTU2_TMDR_4_BFB_SHIFT (5u)
+
+#define MTU2_TIORH_3_IOA_SHIFT (0u)
+#define MTU2_TIORH_3_IOB_SHIFT (4u)
+
+#define MTU2_TIORL_3_IOC_SHIFT (0u)
+#define MTU2_TIORL_3_IOD_SHIFT (4u)
+
+#define MTU2_TIORH_4_IOA_SHIFT (0u)
+#define MTU2_TIORH_4_IOB_SHIFT (4u)
+
+#define MTU2_TIORL_4_IOC_SHIFT (0u)
+#define MTU2_TIORL_4_IOD_SHIFT (4u)
+
+#define MTU2_TIER_3_TGIEC_SHIFT (2u)
+#define MTU2_TIER_3_TGIED_SHIFT (3u)
+
+#define MTU2_TIER_4_TGIEC_SHIFT (2u)
+#define MTU2_TIER_4_TGIED_SHIFT (3u)
+#define MTU2_TIER_4_TTGE2_SHIFT (6u)
+
+#define MTU2_TOER_OE3B_SHIFT (0u)
+#define MTU2_TOER_OE4A_SHIFT (1u)
+#define MTU2_TOER_OE4B_SHIFT (2u)
+#define MTU2_TOER_OE3D_SHIFT (3u)
+#define MTU2_TOER_OE4C_SHIFT (4u)
+#define MTU2_TOER_OE4D_SHIFT (5u)
+
+#define MTU2_TGCR_UF_SHIFT (0u)
+#define MTU2_TGCR_VF_SHIFT (1u)
+#define MTU2_TGCR_WF_SHIFT (2u)
+#define MTU2_TGCR_FB_SHIFT (3u)
+#define MTU2_TGCR_P_SHIFT (4u)
+#define MTU2_TGCR_N_SHIFT (5u)
+#define MTU2_TGCR_BDC_SHIFT (6u)
+
+#define MTU2_TOCR1_OLSP_SHIFT (0u)
+#define MTU2_TOCR1_OLSN_SHIFT (1u)
+#define MTU2_TOCR1_TOCS_SHIFT (2u)
+#define MTU2_TOCR1_TOCL_SHIFT (3u)
+#define MTU2_TOCR1_PSYE_SHIFT (6u)
+
+#define MTU2_TOCR2_OLS1P_SHIFT (0u)
+#define MTU2_TOCR2_OLS1N_SHIFT (1u)
+#define MTU2_TOCR2_OLS2P_SHIFT (2u)
+#define MTU2_TOCR2_OLS2N_SHIFT (3u)
+#define MTU2_TOCR2_OLS3P_SHIFT (4u)
+#define MTU2_TOCR2_OLS3N_SHIFT (5u)
+#define MTU2_TOCR2_BF_SHIFT (6u)
+
+#define MTU2_TCDR_D_SHIFT (0u)
+
+#define MTU2_TDDR_D_SHIFT (0u)
+
+#define MTU2_TCNTS_D_SHIFT (0u)
+
+#define MTU2_TCBR_D_SHIFT (0u)
+
+#define MTU2_TGRC_3_D_SHIFT (0u)
+
+#define MTU2_TGRD_3_D_SHIFT (0u)
+
+#define MTU2_TGRC_4_D_SHIFT (0u)
+
+#define MTU2_TGRD_4_D_SHIFT (0u)
+
+#define MTU2_TSR_3_TGFC_SHIFT (2u)
+#define MTU2_TSR_3_TGFD_SHIFT (3u)
+#define MTU2_TSR_3_TCFD_SHIFT (7u)
+
+#define MTU2_TSR_4_TGFC_SHIFT (2u)
+#define MTU2_TSR_4_TGFD_SHIFT (3u)
+#define MTU2_TSR_4_TCFD_SHIFT (7u)
+
+#define MTU2_TITCR_4VCOR_SHIFT (0u)
+#define MTU2_TITCR_T4VEN_SHIFT (3u)
+#define MTU2_TITCR_3ACOR_SHIFT (4u)
+#define MTU2_TITCR_T3AEN_SHIFT (7u)
+
+#define MTU2_TITCNT_4VCNT_SHIFT (0u)
+#define MTU2_TITCNT_3ACNT_SHIFT (4u)
+
+#define MTU2_TBTER_BTE_SHIFT (0u)
+
+#define MTU2_TDER_TDER_SHIFT (0u)
+
+#define MTU2_TOLBR_OLS1P_SHIFT (0u)
+#define MTU2_TOLBR_OLS1N_SHIFT (1u)
+#define MTU2_TOLBR_OLS2P_SHIFT (2u)
+#define MTU2_TOLBR_OLS2N_SHIFT (3u)
+#define MTU2_TOLBR_OLS3P_SHIFT (4u)
+#define MTU2_TOLBR_OLS3N_SHIFT (5u)
+
+#define MTU2_TBTM_3_TTSA_SHIFT (0u)
+#define MTU2_TBTM_3_TTSB_SHIFT (1u)
+
+#define MTU2_TBTM_4_TTSA_SHIFT (0u)
+#define MTU2_TBTM_4_TTSB_SHIFT (1u)
+
+#define MTU2_TADCR_ITB4VE_SHIFT (0u)
+#define MTU2_TADCR_ITB3AE_SHIFT (1u)
+#define MTU2_TADCR_ITA4VE_SHIFT (2u)
+#define MTU2_TADCR_ITA3AE_SHIFT (3u)
+#define MTU2_TADCR_DT4BE_SHIFT (4u)
+#define MTU2_TADCR_UT4BE_SHIFT (5u)
+#define MTU2_TADCR_DT4AE_SHIFT (6u)
+#define MTU2_TADCR_UT4AE_SHIFT (7u)
+#define MTU2_TADCR_BF_SHIFT (14u)
+
+#define MTU2_TADCORA_4_D_SHIFT (0u)
+
+#define MTU2_TADCORB_4_D_SHIFT (0u)
+
+#define MTU2_TADCOBRA_4_D_SHIFT (0u)
+
+#define MTU2_TADCOBRB_4_D_SHIFT (0u)
+
+#define MTU2_TWCR_WRE_SHIFT (0u)
+#define MTU2_TWCR_CCE_SHIFT (7u)
+
+#define MTU2_TSTR_CST0_SHIFT (0u)
+#define MTU2_TSTR_CST1_SHIFT (1u)
+#define MTU2_TSTR_CST2_SHIFT (2u)
+#define MTU2_TSTR_CST3_SHIFT (6u)
+#define MTU2_TSTR_CST4_SHIFT (7u)
+
+#define MTU2_TSYR_SYNC0_SHIFT (0u)
+#define MTU2_TSYR_SYNC1_SHIFT (1u)
+#define MTU2_TSYR_SYNC2_SHIFT (2u)
+#define MTU2_TSYR_SYNC3_SHIFT (6u)
+#define MTU2_TSYR_SYNC4_SHIFT (7u)
+
+#define MTU2_TRWER_RWE_SHIFT (0u)
+
+#define MTU2_TMDR_0_BFA_SHIFT (4u)
+#define MTU2_TMDR_0_BFB_SHIFT (5u)
+#define MTU2_TMDR_0_BFE_SHIFT (6u)
+
+#define MTU2_TIORH_0_IOA_SHIFT (0u)
+#define MTU2_TIORH_0_IOB_SHIFT (4u)
+
+#define MTU2_TIORL_0_IOC_SHIFT (0u)
+#define MTU2_TIORL_0_IOD_SHIFT (4u)
+
+#define MTU2_TIER_0_TGIEC_SHIFT (2u)
+#define MTU2_TIER_0_TGIED_SHIFT (3u)
+
+#define MTU2_TSR_0_TGFC_SHIFT (2u)
+#define MTU2_TSR_0_TGFD_SHIFT (3u)
+
+#define MTU2_TGRC_0_D_SHIFT (0u)
+
+#define MTU2_TGRD_0_D_SHIFT (0u)
+
+#define MTU2_TGRE_0_D_SHIFT (0u)
+
+#define MTU2_TGRF_0_D_SHIFT (0u)
+
+#define MTU2_TIER2_0_TGIEE_SHIFT (0u)
+#define MTU2_TIER2_0_TGIEF_SHIFT (1u)
+
+#define MTU2_TSR2_0_TGFE_SHIFT (0u)
+#define MTU2_TSR2_0_TGFF_SHIFT (1u)
+
+#define MTU2_TBTM_0_TTSA_SHIFT (0u)
+#define MTU2_TBTM_0_TTSB_SHIFT (1u)
+#define MTU2_TBTM_0_TTSE_SHIFT (2u)
+
+#define MTU2_TIOR_1_IOA_SHIFT (0u)
+#define MTU2_TIOR_1_IOB_SHIFT (4u)
+
+#define MTU2_TIER_1_TCIEU_SHIFT (5u)
+
+#define MTU2_TSR_1_TCFU_SHIFT (5u)
+#define MTU2_TSR_1_TCFD_SHIFT (7u)
+
+#define MTU2_TICCR_I1AE_SHIFT (0u)
+#define MTU2_TICCR_I1BE_SHIFT (1u)
+#define MTU2_TICCR_I2AE_SHIFT (2u)
+#define MTU2_TICCR_I2BE_SHIFT (3u)
+
+
+#endif /* MTU2_IOBITMASK_H */
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h
new file mode 100644
index 000000000..418bca70a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h
@@ -0,0 +1,123 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : OSTM register define header
+*******************************************************************************/
+#ifndef OSTM_IOBITMASK_H
+#define OSTM_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnTE_OSTMnTE (0x01u)
+
+#define OSTM0_OSTMnTS_OSTMnTS (0x01u)
+
+#define OSTM0_OSTMnTT_OSTMnTT (0x01u)
+
+#define OSTM0_OSTMnCTL_MD0 (0x00000001uL)
+#define OSTM0_OSTMnCTL_MD1 (0x00000002uL)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnTE_OSTMnTE (0x01u)
+
+#define OSTM1_OSTMnTS_OSTMnTS (0x01u)
+
+#define OSTM1_OSTMnTT_OSTMnTT (0x01u)
+
+#define OSTM1_OSTMnCTL_MD0 (0x00000001uL)
+#define OSTM1_OSTMnCTL_MD1 (0x00000002uL)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnTE_OSTMnTE (0x01u)
+
+#define OSTMn_OSTMnTS_OSTMnTS (0x01u)
+
+#define OSTMn_OSTMnTT_OSTMnTT (0x01u)
+
+#define OSTMn_OSTMnCTL_MD0 (0x00000001uL)
+#define OSTMn_OSTMnCTL_MD1 (0x00000002uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u)
+
+#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u)
+
+#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u)
+
+#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u)
+
+#define OSTM0_OSTMnCTL_MD0_SHIFT (0u)
+#define OSTM0_OSTMnCTL_MD1_SHIFT (1u)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u)
+
+#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u)
+
+#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u)
+
+#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u)
+
+#define OSTM1_OSTMnCTL_MD0_SHIFT (0u)
+#define OSTM1_OSTMnCTL_MD1_SHIFT (1u)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u)
+
+#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u)
+
+#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u)
+
+#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u)
+
+#define OSTMn_OSTMnCTL_MD0_SHIFT (0u)
+#define OSTMn_OSTMnCTL_MD1_SHIFT (1u)
+
+
+#endif /* OSTM_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/riic_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/riic_iobitmask.h
new file mode 100644
index 000000000..8a2a87133
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/riic_iobitmask.h
@@ -0,0 +1,231 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : RIIC register define header
+*******************************************************************************/
+#ifndef RIIC_IOBITMASK_H
+#define RIIC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI (0x01u)
+#define RIICn_RIICnCR1_SCLI (0x02u)
+#define RIICn_RIICnCR1_SDAO (0x04u)
+#define RIICn_RIICnCR1_SCLO (0x08u)
+#define RIICn_RIICnCR1_SOWP (0x10u)
+#define RIICn_RIICnCR1_CLO (0x20u)
+#define RIICn_RIICnCR1_IICRST (0x40u)
+#define RIICn_RIICnCR1_ICE (0x80u)
+
+#define RIICn_RIICnCR2_ST (0x02u)
+#define RIICn_RIICnCR2_RS (0x04u)
+#define RIICn_RIICnCR2_SP (0x08u)
+#define RIICn_RIICnCR2_TRS (0x20u)
+#define RIICn_RIICnCR2_MST (0x40u)
+#define RIICn_RIICnCR2_BBSY (0x80u)
+
+#define RIICn_RIICnMR1_BC (0x07u)
+#define RIICn_RIICnMR1_BCWP (0x08u)
+#define RIICn_RIICnMR1_CKS (0x70u)
+#define RIICn_RIICnMR1_MTWP (0x80u)
+
+#define RIICn_RIICnMR2_TMOS (0x01u)
+#define RIICn_RIICnMR2_TMOL (0x02u)
+#define RIICn_RIICnMR2_TMOH (0x04u)
+#define RIICn_RIICnMR2_SDDL (0x70u)
+#define RIICn_RIICnMR2_DLCS (0x80u)
+
+#define RIICn_RIICnMR3_NF (0x03u)
+#define RIICn_RIICnMR3_ACKBR (0x04u)
+#define RIICn_RIICnMR3_ACKBT (0x08u)
+#define RIICn_RIICnMR3_ACKWP (0x10u)
+#define RIICn_RIICnMR3_RDRFS (0x20u)
+#define RIICn_RIICnMR3_WAIT (0x40u)
+#define RIICn_RIICnMR3_SMBS (0x80u)
+
+#define RIICn_RIICnFER_TMOE (0x01u)
+#define RIICn_RIICnFER_MALE (0x02u)
+#define RIICn_RIICnFER_NALE (0x04u)
+#define RIICn_RIICnFER_SALE (0x08u)
+#define RIICn_RIICnFER_NACKE (0x10u)
+#define RIICn_RIICnFER_NFE (0x20u)
+#define RIICn_RIICnFER_SCLE (0x40u)
+#define RIICn_RIICnFER_FMPE (0x80u)
+
+#define RIICn_RIICnSER_SAR0E (0x01u)
+#define RIICn_RIICnSER_SAR1E (0x02u)
+#define RIICn_RIICnSER_SAR2E (0x04u)
+#define RIICn_RIICnSER_GCAE (0x08u)
+#define RIICn_RIICnSER_DIDE (0x20u)
+#define RIICn_RIICnSER_HOAE (0x80u)
+
+#define RIICn_RIICnIER_TMOIE (0x01u)
+#define RIICn_RIICnIER_ALIE (0x02u)
+#define RIICn_RIICnIER_STIE (0x04u)
+#define RIICn_RIICnIER_SPIE (0x08u)
+#define RIICn_RIICnIER_NAKIE (0x10u)
+#define RIICn_RIICnIER_RIE (0x20u)
+#define RIICn_RIICnIER_TEIE (0x40u)
+#define RIICn_RIICnIER_TIE (0x80u)
+
+#define RIICn_RIICnSR1_AAS0 (0x01u)
+#define RIICn_RIICnSR1_AAS1 (0x02u)
+#define RIICn_RIICnSR1_AAS2 (0x04u)
+#define RIICn_RIICnSR1_GCA (0x08u)
+#define RIICn_RIICnSR1_DID (0x20u)
+#define RIICn_RIICnSR1_HOA (0x80u)
+
+#define RIICn_RIICnSR2_TMOF (0x01u)
+#define RIICn_RIICnSR2_AL (0x02u)
+#define RIICn_RIICnSR2_START (0x04u)
+#define RIICn_RIICnSR2_STOP (0x08u)
+#define RIICn_RIICnSR2_NACKF (0x10u)
+#define RIICn_RIICnSR2_RDRF (0x20u)
+#define RIICn_RIICnSR2_TEND (0x40u)
+#define RIICn_RIICnSR2_TDRE (0x80u)
+
+#define RIICn_RIICnSAR0_SVA0 (0x0001u)
+#define RIICn_RIICnSAR0_SVA (0x03FEu)
+#define RIICn_RIICnSAR0_FSy (0x8000u)
+
+#define RIICn_RIICnSAR1_SVA0 (0x0001u)
+#define RIICn_RIICnSAR1_SVA (0x03FEu)
+#define RIICn_RIICnSAR1_FSy (0x8000u)
+
+#define RIICn_RIICnSAR2_SVA0 (0x0001u)
+#define RIICn_RIICnSAR2_SVA (0x03FEu)
+#define RIICn_RIICnSAR2_FSy (0x8000u)
+
+#define RIICn_RIICnBRL_BRL (0x1Fu)
+
+#define RIICn_RIICnBRH_BRH (0x1Fu)
+
+#define RIICn_RIICnDRT_DRT (0xFFu)
+
+#define RIICn_RIICnDRR_DRR (0xFFu)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI_SHIFT (0u)
+#define RIICn_RIICnCR1_SCLI_SHIFT (1u)
+#define RIICn_RIICnCR1_SDAO_SHIFT (2u)
+#define RIICn_RIICnCR1_SCLO_SHIFT (3u)
+#define RIICn_RIICnCR1_SOWP_SHIFT (4u)
+#define RIICn_RIICnCR1_CLO_SHIFT (5u)
+#define RIICn_RIICnCR1_IICRST_SHIFT (6u)
+#define RIICn_RIICnCR1_ICE_SHIFT (7u)
+
+#define RIICn_RIICnCR2_ST_SHIFT (1u)
+#define RIICn_RIICnCR2_RS_SHIFT (2u)
+#define RIICn_RIICnCR2_SP_SHIFT (3u)
+#define RIICn_RIICnCR2_TRS_SHIFT (5u)
+#define RIICn_RIICnCR2_MST_SHIFT (6u)
+#define RIICn_RIICnCR2_BBSY_SHIFT (7u)
+
+#define RIICn_RIICnMR1_BC_SHIFT (0u)
+#define RIICn_RIICnMR1_BCWP_SHIFT (3u)
+#define RIICn_RIICnMR1_CKS_SHIFT (4u)
+#define RIICn_RIICnMR1_MTWP_SHIFT (7u)
+
+#define RIICn_RIICnMR2_TMOS_SHIFT (0u)
+#define RIICn_RIICnMR2_TMOL_SHIFT (1u)
+#define RIICn_RIICnMR2_TMOH_SHIFT (2u)
+#define RIICn_RIICnMR2_SDDL_SHIFT (4u)
+#define RIICn_RIICnMR2_DLCS_SHIFT (7u)
+
+#define RIICn_RIICnMR3_NF_SHIFT (0u)
+#define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
+#define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
+#define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
+#define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
+#define RIICn_RIICnMR3_WAIT_SHIFT (6u)
+#define RIICn_RIICnMR3_SMBS_SHIFT (7u)
+
+#define RIICn_RIICnFER_TMOE_SHIFT (0u)
+#define RIICn_RIICnFER_MALE_SHIFT (1u)
+#define RIICn_RIICnFER_NALE_SHIFT (2u)
+#define RIICn_RIICnFER_SALE_SHIFT (3u)
+#define RIICn_RIICnFER_NACKE_SHIFT (4u)
+#define RIICn_RIICnFER_NFE_SHIFT (5u)
+#define RIICn_RIICnFER_SCLE_SHIFT (6u)
+#define RIICn_RIICnFER_FMPE_SHIFT (7u)
+
+#define RIICn_RIICnSER_SAR0E_SHIFT (0u)
+#define RIICn_RIICnSER_SAR1E_SHIFT (1u)
+#define RIICn_RIICnSER_SAR2E_SHIFT (2u)
+#define RIICn_RIICnSER_GCAE_SHIFT (3u)
+#define RIICn_RIICnSER_DIDE_SHIFT (5u)
+#define RIICn_RIICnSER_HOAE_SHIFT (7u)
+
+#define RIICn_RIICnIER_TMOIE_SHIFT (0u)
+#define RIICn_RIICnIER_ALIE_SHIFT (1u)
+#define RIICn_RIICnIER_STIE_SHIFT (2u)
+#define RIICn_RIICnIER_SPIE_SHIFT (3u)
+#define RIICn_RIICnIER_NAKIE_SHIFT (4u)
+#define RIICn_RIICnIER_RIE_SHIFT (5u)
+#define RIICn_RIICnIER_TEIE_SHIFT (6u)
+#define RIICn_RIICnIER_TIE_SHIFT (7u)
+
+#define RIICn_RIICnSR1_AAS0_SHIFT (0u)
+#define RIICn_RIICnSR1_AAS1_SHIFT (1u)
+#define RIICn_RIICnSR1_AAS2_SHIFT (2u)
+#define RIICn_RIICnSR1_GCA_SHIFT (3u)
+#define RIICn_RIICnSR1_DID_SHIFT (5u)
+#define RIICn_RIICnSR1_HOA_SHIFT (7u)
+
+#define RIICn_RIICnSR2_TMOF_SHIFT (0u)
+#define RIICn_RIICnSR2_AL_SHIFT (1u)
+#define RIICn_RIICnSR2_START_SHIFT (2u)
+#define RIICn_RIICnSR2_STOP_SHIFT (3u)
+#define RIICn_RIICnSR2_NACKF_SHIFT (4u)
+#define RIICn_RIICnSR2_RDRF_SHIFT (5u)
+#define RIICn_RIICnSR2_TEND_SHIFT (6u)
+#define RIICn_RIICnSR2_TDRE_SHIFT (7u)
+
+#define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
+#define RIICn_RIICnSAR0_SVA_SHIFT (1u)
+#define RIICn_RIICnSAR0_FSy_SHIFT (15u)
+
+#define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
+#define RIICn_RIICnSAR1_SVA_SHIFT (1u)
+#define RIICn_RIICnSAR1_FSy_SHIFT (15u)
+
+#define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
+#define RIICn_RIICnSAR2_SVA_SHIFT (1u)
+#define RIICn_RIICnSAR2_FSy_SHIFT (15u)
+
+#define RIICn_RIICnBRL_BRL_SHIFT (0u)
+
+#define RIICn_RIICnBRH_BRH_SHIFT (0u)
+
+#define RIICn_RIICnDRT_DRT_SHIFT (0u)
+
+#define RIICn_RIICnDRR_DRR_SHIFT (0u)
+
+
+#endif /* RIIC_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h
new file mode 100644
index 000000000..ca1ba2e8a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h
@@ -0,0 +1,215 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rspi_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : Renesas Serial Peripheral Interface register define header
+*******************************************************************************/
+#ifndef RSPI_IOBITMASK_H
+#define RSPI_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN (0x04u)
+#define RSPIn_SPCR_MSTR (0x08u)
+#define RSPIn_SPCR_SPEIE (0x10u)
+#define RSPIn_SPCR_SPTIE (0x20u)
+#define RSPIn_SPCR_SPE (0x40u)
+#define RSPIn_SPCR_SPRIE (0x80u)
+
+#define RSPIn_SSLP_SSL0P (0x01u)
+
+#define RSPIn_SPPCR_SPLP (0x01u)
+#define RSPIn_SPPCR_MOIFV (0x10u)
+#define RSPIn_SPPCR_MOIFE (0x20u)
+
+#define RSPIn_SPSR_OVRF (0x01u)
+#define RSPIn_SPSR_MODF (0x04u)
+#define RSPIn_SPSR_SPTEF (0x20u)
+#define RSPIn_SPSR_TEND (0x40u)
+#define RSPIn_SPSR_SPRF (0x80u)
+
+#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
+
+#define RSPIn_SPDR_UINT16 (0xFFFFu)
+
+#define RSPIn_SPDR_UINT8 (0xFFu)
+
+#define RSPIn_SPSCR_SPSLN (0x03u)
+
+#define RSPIn_SPSSR_SPCP (0x03u)
+
+#define RSPIn_SPBR_SPR (0xFFu)
+
+#define RSPIn_SPDCR_SPLW (0x60u)
+#define RSPIn_SPDCR_TXDMY (0x80u)
+
+#define RSPIn_SPCKD_SCKDL (0x07u)
+
+#define RSPIn_SSLND_SLNDL (0x07u)
+
+#define RSPIn_SPND_SPNDL (0x07u)
+
+#define RSPIn_SPCMD0_CPHA (0x0001u)
+#define RSPIn_SPCMD0_CPOL (0x0002u)
+#define RSPIn_SPCMD0_BRDV (0x000Cu)
+#define RSPIn_SPCMD0_SSLKP (0x0080u)
+#define RSPIn_SPCMD0_SPB (0x0F00u)
+#define RSPIn_SPCMD0_LSBF (0x1000u)
+#define RSPIn_SPCMD0_SPNDEN (0x2000u)
+#define RSPIn_SPCMD0_SLNDEN (0x4000u)
+#define RSPIn_SPCMD0_SCKDEN (0x8000u)
+
+#define RSPIn_SPCMD1_CPHA (0x0001u)
+#define RSPIn_SPCMD1_CPOL (0x0002u)
+#define RSPIn_SPCMD1_BRDV (0x000Cu)
+#define RSPIn_SPCMD1_SSLKP (0x0080u)
+#define RSPIn_SPCMD1_SPB (0x0F00u)
+#define RSPIn_SPCMD1_LSBF (0x1000u)
+#define RSPIn_SPCMD1_SPNDEN (0x2000u)
+#define RSPIn_SPCMD1_SLNDEN (0x4000u)
+#define RSPIn_SPCMD1_SCKDEN (0x8000u)
+
+#define RSPIn_SPCMD2_CPHA (0x0001u)
+#define RSPIn_SPCMD2_CPOL (0x0002u)
+#define RSPIn_SPCMD2_BRDV (0x000Cu)
+#define RSPIn_SPCMD2_SSLKP (0x0080u)
+#define RSPIn_SPCMD2_SPB (0x0F00u)
+#define RSPIn_SPCMD2_LSBF (0x1000u)
+#define RSPIn_SPCMD2_SPNDEN (0x2000u)
+#define RSPIn_SPCMD2_SLNDEN (0x4000u)
+#define RSPIn_SPCMD2_SCKDEN (0x8000u)
+
+#define RSPIn_SPCMD3_CPHA (0x0001u)
+#define RSPIn_SPCMD3_CPOL (0x0002u)
+#define RSPIn_SPCMD3_BRDV (0x000Cu)
+#define RSPIn_SPCMD3_SSLKP (0x0080u)
+#define RSPIn_SPCMD3_SPB (0x0F00u)
+#define RSPIn_SPCMD3_LSBF (0x1000u)
+#define RSPIn_SPCMD3_SPNDEN (0x2000u)
+#define RSPIn_SPCMD3_SLNDEN (0x4000u)
+#define RSPIn_SPCMD3_SCKDEN (0x8000u)
+
+#define RSPIn_SPBFCR_RXTRG (0x07u)
+#define RSPIn_SPBFCR_TXTRG (0x30u)
+#define RSPIn_SPBFCR_RXRST (0x40u)
+#define RSPIn_SPBFCR_TXRST (0x80u)
+
+#define RSPIn_SPBFDR_R (0x003Fu)
+#define RSPIn_SPBFDR_T (0x0F00u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN_SHIFT (2u)
+#define RSPIn_SPCR_MSTR_SHIFT (3u)
+#define RSPIn_SPCR_SPEIE_SHIFT (4u)
+#define RSPIn_SPCR_SPTIE_SHIFT (5u)
+#define RSPIn_SPCR_SPE_SHIFT (6u)
+#define RSPIn_SPCR_SPRIE_SHIFT (7u)
+
+#define RSPIn_SSLP_SSL0P_SHIFT (0u)
+
+#define RSPIn_SPPCR_SPLP_SHIFT (0u)
+#define RSPIn_SPPCR_MOIFV_SHIFT (4u)
+#define RSPIn_SPPCR_MOIFE_SHIFT (5u)
+
+#define RSPIn_SPSR_OVRF_SHIFT (0u)
+#define RSPIn_SPSR_MODF_SHIFT (2u)
+#define RSPIn_SPSR_SPTEF_SHIFT (5u)
+#define RSPIn_SPSR_TEND_SHIFT (6u)
+#define RSPIn_SPSR_SPRF_SHIFT (7u)
+
+#define RSPIn_SPDR_UINT32_SHIFT (0u)
+
+#define RSPIn_SPDR_UINT16_SHIFT (0u)
+
+#define RSPIn_SPDR_UINT8_SHIFT (0u)
+
+#define RSPIn_SPSCR_SPSLN_SHIFT (0u)
+
+#define RSPIn_SPSSR_SPCP_SHIFT (0u)
+
+#define RSPIn_SPBR_SPR_SHIFT (0u)
+
+#define RSPIn_SPDCR_SPLW_SHIFT (5u)
+#define RSPIn_SPDCR_TXDMY_SHIFT (7u)
+
+#define RSPIn_SPCKD_SCKDL_SHIFT (0u)
+
+#define RSPIn_SSLND_SLNDL_SHIFT (0u)
+
+#define RSPIn_SPND_SPNDL_SHIFT (0u)
+
+#define RSPIn_SPCMD0_CPHA_SHIFT (0u)
+#define RSPIn_SPCMD0_CPOL_SHIFT (1u)
+#define RSPIn_SPCMD0_BRDV_SHIFT (2u)
+#define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
+#define RSPIn_SPCMD0_SPB_SHIFT (8u)
+#define RSPIn_SPCMD0_LSBF_SHIFT (12u)
+#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
+#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
+#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
+
+#define RSPIn_SPCMD1_CPHA_SHIFT (0u)
+#define RSPIn_SPCMD1_CPOL_SHIFT (1u)
+#define RSPIn_SPCMD1_BRDV_SHIFT (2u)
+#define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
+#define RSPIn_SPCMD1_SPB_SHIFT (8u)
+#define RSPIn_SPCMD1_LSBF_SHIFT (12u)
+#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
+#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
+#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
+
+#define RSPIn_SPCMD2_CPHA_SHIFT (0u)
+#define RSPIn_SPCMD2_CPOL_SHIFT (1u)
+#define RSPIn_SPCMD2_BRDV_SHIFT (2u)
+#define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
+#define RSPIn_SPCMD2_SPB_SHIFT (8u)
+#define RSPIn_SPCMD2_LSBF_SHIFT (12u)
+#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
+#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
+#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
+
+#define RSPIn_SPCMD3_CPHA_SHIFT (0u)
+#define RSPIn_SPCMD3_CPOL_SHIFT (1u)
+#define RSPIn_SPCMD3_BRDV_SHIFT (2u)
+#define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
+#define RSPIn_SPCMD3_SPB_SHIFT (8u)
+#define RSPIn_SPCMD3_LSBF_SHIFT (12u)
+#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
+#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
+#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
+
+#define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
+#define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
+#define RSPIn_SPBFCR_RXRST_SHIFT (6u)
+#define RSPIn_SPBFCR_TXRST_SHIFT (7u)
+
+#define RSPIn_SPBFDR_R_SHIFT (0u)
+#define RSPIn_SPBFDR_T_SHIFT (8u)
+
+
+#endif /* RSPI_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/scif_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/scif_iobitmask.h
new file mode 100644
index 000000000..a545d6b4a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/scif_iobitmask.h
@@ -0,0 +1,1065 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : SCIF register define header
+*******************************************************************************/
+#ifndef SCIF_IOBITMASK_H
+#define SCIF_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS (0x0003u)
+#define SCIF0_SCSMR_STOP (0x0008u)
+#define SCIF0_SCSMR_OE (0x0010u)
+#define SCIF0_SCSMR_PE (0x0020u)
+#define SCIF0_SCSMR_CHR (0x0040u)
+#define SCIF0_SCSMR_CA (0x0080u)
+
+#define SCIF0_SCBRR_D (0xFFu)
+
+#define SCIF0_SCSCR_CKE (0x0003u)
+#define SCIF0_SCSCR_REIE (0x0008u)
+#define SCIF0_SCSCR_RE (0x0010u)
+#define SCIF0_SCSCR_TE (0x0020u)
+#define SCIF0_SCSCR_RIE (0x0040u)
+#define SCIF0_SCSCR_TIE (0x0080u)
+
+#define SCIF0_SCFTDR_D (0xFFu)
+
+#define SCIF0_SCFSR_DR (0x0001u)
+#define SCIF0_SCFSR_RDF (0x0002u)
+#define SCIF0_SCFSR_PER (0x0004u)
+#define SCIF0_SCFSR_FER (0x0008u)
+#define SCIF0_SCFSR_BRK (0x0010u)
+#define SCIF0_SCFSR_TDFE (0x0020u)
+#define SCIF0_SCFSR_TEND (0x0040u)
+#define SCIF0_SCFSR_ER (0x0080u)
+#define SCIF0_SCFSR_FERN (0x0F00u)
+#define SCIF0_SCFSR_PERN (0xF000u)
+
+#define SCIF0_SCFRDR_D (0xFFu)
+
+#define SCIF0_SCFCR_LOOP (0x0001u)
+#define SCIF0_SCFCR_RFRST (0x0002u)
+#define SCIF0_SCFCR_TFRST (0x0004u)
+#define SCIF0_SCFCR_MCE (0x0008u)
+#define SCIF0_SCFCR_TTRG (0x0030u)
+#define SCIF0_SCFCR_RTRG (0x00C0u)
+#define SCIF0_SCFCR_RSTRG (0x0700u)
+
+#define SCIF0_SCFDR_R (0x001Fu)
+#define SCIF0_SCFDR_T (0x1F00u)
+
+#define SCIF0_SCSPTR_SPB2DT (0x0001u)
+#define SCIF0_SCSPTR_SPB2IO (0x0002u)
+#define SCIF0_SCSPTR_SCKDT (0x0004u)
+#define SCIF0_SCSPTR_SCKIO (0x0008u)
+#define SCIF0_SCSPTR_CTSDT (0x0010u)
+#define SCIF0_SCSPTR_CTSIO (0x0020u)
+#define SCIF0_SCSPTR_RTSDT (0x0040u)
+#define SCIF0_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF0_SCLSR_ORER (0x0001u)
+
+#define SCIF0_SCEMR_ABCS (0x0001u)
+#define SCIF0_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS (0x0003u)
+#define SCIF1_SCSMR_STOP (0x0008u)
+#define SCIF1_SCSMR_OE (0x0010u)
+#define SCIF1_SCSMR_PE (0x0020u)
+#define SCIF1_SCSMR_CHR (0x0040u)
+#define SCIF1_SCSMR_CA (0x0080u)
+
+#define SCIF1_SCBRR_D (0xFFu)
+
+#define SCIF1_SCSCR_CKE (0x0003u)
+#define SCIF1_SCSCR_REIE (0x0008u)
+#define SCIF1_SCSCR_RE (0x0010u)
+#define SCIF1_SCSCR_TE (0x0020u)
+#define SCIF1_SCSCR_RIE (0x0040u)
+#define SCIF1_SCSCR_TIE (0x0080u)
+
+#define SCIF1_SCFTDR_D (0xFFu)
+
+#define SCIF1_SCFSR_DR (0x0001u)
+#define SCIF1_SCFSR_RDF (0x0002u)
+#define SCIF1_SCFSR_PER (0x0004u)
+#define SCIF1_SCFSR_FER (0x0008u)
+#define SCIF1_SCFSR_BRK (0x0010u)
+#define SCIF1_SCFSR_TDFE (0x0020u)
+#define SCIF1_SCFSR_TEND (0x0040u)
+#define SCIF1_SCFSR_ER (0x0080u)
+#define SCIF1_SCFSR_FERN (0x0F00u)
+#define SCIF1_SCFSR_PERN (0xF000u)
+
+#define SCIF1_SCFRDR_D (0xFFu)
+
+#define SCIF1_SCFCR_LOOP (0x0001u)
+#define SCIF1_SCFCR_RFRST (0x0002u)
+#define SCIF1_SCFCR_TFRST (0x0004u)
+#define SCIF1_SCFCR_MCE (0x0008u)
+#define SCIF1_SCFCR_TTRG (0x0030u)
+#define SCIF1_SCFCR_RTRG (0x00C0u)
+#define SCIF1_SCFCR_RSTRG (0x0700u)
+
+#define SCIF1_SCFDR_R (0x001Fu)
+#define SCIF1_SCFDR_T (0x1F00u)
+
+#define SCIF1_SCSPTR_SPB2DT (0x0001u)
+#define SCIF1_SCSPTR_SPB2IO (0x0002u)
+#define SCIF1_SCSPTR_SCKDT (0x0004u)
+#define SCIF1_SCSPTR_SCKIO (0x0008u)
+#define SCIF1_SCSPTR_CTSDT (0x0010u)
+#define SCIF1_SCSPTR_CTSIO (0x0020u)
+#define SCIF1_SCSPTR_RTSDT (0x0040u)
+#define SCIF1_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF1_SCLSR_ORER (0x0001u)
+
+#define SCIF1_SCEMR_ABCS (0x0001u)
+#define SCIF1_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS (0x0003u)
+#define SCIF2_SCSMR_STOP (0x0008u)
+#define SCIF2_SCSMR_OE (0x0010u)
+#define SCIF2_SCSMR_PE (0x0020u)
+#define SCIF2_SCSMR_CHR (0x0040u)
+#define SCIF2_SCSMR_CA (0x0080u)
+
+#define SCIF2_SCBRR_D (0xFFu)
+
+#define SCIF2_SCSCR_CKE (0x0003u)
+#define SCIF2_SCSCR_REIE (0x0008u)
+#define SCIF2_SCSCR_RE (0x0010u)
+#define SCIF2_SCSCR_TE (0x0020u)
+#define SCIF2_SCSCR_RIE (0x0040u)
+#define SCIF2_SCSCR_TIE (0x0080u)
+
+#define SCIF2_SCFTDR_D (0xFFu)
+
+#define SCIF2_SCFSR_DR (0x0001u)
+#define SCIF2_SCFSR_RDF (0x0002u)
+#define SCIF2_SCFSR_PER (0x0004u)
+#define SCIF2_SCFSR_FER (0x0008u)
+#define SCIF2_SCFSR_BRK (0x0010u)
+#define SCIF2_SCFSR_TDFE (0x0020u)
+#define SCIF2_SCFSR_TEND (0x0040u)
+#define SCIF2_SCFSR_ER (0x0080u)
+#define SCIF2_SCFSR_FERN (0x0F00u)
+#define SCIF2_SCFSR_PERN (0xF000u)
+
+#define SCIF2_SCFRDR_D (0xFFu)
+
+#define SCIF2_SCFCR_LOOP (0x0001u)
+#define SCIF2_SCFCR_RFRST (0x0002u)
+#define SCIF2_SCFCR_TFRST (0x0004u)
+#define SCIF2_SCFCR_MCE (0x0008u)
+#define SCIF2_SCFCR_TTRG (0x0030u)
+#define SCIF2_SCFCR_RTRG (0x00C0u)
+#define SCIF2_SCFCR_RSTRG (0x0700u)
+
+#define SCIF2_SCFDR_R (0x001Fu)
+#define SCIF2_SCFDR_T (0x1F00u)
+
+#define SCIF2_SCSPTR_SPB2DT (0x0001u)
+#define SCIF2_SCSPTR_SPB2IO (0x0002u)
+#define SCIF2_SCSPTR_SCKDT (0x0004u)
+#define SCIF2_SCSPTR_SCKIO (0x0008u)
+#define SCIF2_SCSPTR_CTSDT (0x0010u)
+#define SCIF2_SCSPTR_CTSIO (0x0020u)
+#define SCIF2_SCSPTR_RTSDT (0x0040u)
+#define SCIF2_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF2_SCLSR_ORER (0x0001u)
+
+#define SCIF2_SCEMR_ABCS (0x0001u)
+#define SCIF2_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS (0x0003u)
+#define SCIF3_SCSMR_STOP (0x0008u)
+#define SCIF3_SCSMR_OE (0x0010u)
+#define SCIF3_SCSMR_PE (0x0020u)
+#define SCIF3_SCSMR_CHR (0x0040u)
+#define SCIF3_SCSMR_CA (0x0080u)
+
+#define SCIF3_SCBRR_D (0xFFu)
+
+#define SCIF3_SCSCR_CKE (0x0003u)
+#define SCIF3_SCSCR_REIE (0x0008u)
+#define SCIF3_SCSCR_RE (0x0010u)
+#define SCIF3_SCSCR_TE (0x0020u)
+#define SCIF3_SCSCR_RIE (0x0040u)
+#define SCIF3_SCSCR_TIE (0x0080u)
+
+#define SCIF3_SCFTDR_D (0xFFu)
+
+#define SCIF3_SCFSR_DR (0x0001u)
+#define SCIF3_SCFSR_RDF (0x0002u)
+#define SCIF3_SCFSR_PER (0x0004u)
+#define SCIF3_SCFSR_FER (0x0008u)
+#define SCIF3_SCFSR_BRK (0x0010u)
+#define SCIF3_SCFSR_TDFE (0x0020u)
+#define SCIF3_SCFSR_TEND (0x0040u)
+#define SCIF3_SCFSR_ER (0x0080u)
+#define SCIF3_SCFSR_FERN (0x0F00u)
+#define SCIF3_SCFSR_PERN (0xF000u)
+
+#define SCIF3_SCFRDR_D (0xFFu)
+
+#define SCIF3_SCFCR_LOOP (0x0001u)
+#define SCIF3_SCFCR_RFRST (0x0002u)
+#define SCIF3_SCFCR_TFRST (0x0004u)
+#define SCIF3_SCFCR_MCE (0x0008u)
+#define SCIF3_SCFCR_TTRG (0x0030u)
+#define SCIF3_SCFCR_RTRG (0x00C0u)
+#define SCIF3_SCFCR_RSTRG (0x0700u)
+
+#define SCIF3_SCFDR_R (0x001Fu)
+#define SCIF3_SCFDR_T (0x1F00u)
+
+#define SCIF3_SCSPTR_SPB2DT (0x0001u)
+#define SCIF3_SCSPTR_SPB2IO (0x0002u)
+#define SCIF3_SCSPTR_SCKDT (0x0004u)
+#define SCIF3_SCSPTR_SCKIO (0x0008u)
+#define SCIF3_SCSPTR_CTSDT (0x0010u)
+#define SCIF3_SCSPTR_CTSIO (0x0020u)
+#define SCIF3_SCSPTR_RTSDT (0x0040u)
+#define SCIF3_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF3_SCLSR_ORER (0x0001u)
+
+#define SCIF3_SCEMR_ABCS (0x0001u)
+#define SCIF3_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS (0x0003u)
+#define SCIF4_SCSMR_STOP (0x0008u)
+#define SCIF4_SCSMR_OE (0x0010u)
+#define SCIF4_SCSMR_PE (0x0020u)
+#define SCIF4_SCSMR_CHR (0x0040u)
+#define SCIF4_SCSMR_CA (0x0080u)
+
+#define SCIF4_SCBRR_D (0xFFu)
+
+#define SCIF4_SCSCR_CKE (0x0003u)
+#define SCIF4_SCSCR_REIE (0x0008u)
+#define SCIF4_SCSCR_RE (0x0010u)
+#define SCIF4_SCSCR_TE (0x0020u)
+#define SCIF4_SCSCR_RIE (0x0040u)
+#define SCIF4_SCSCR_TIE (0x0080u)
+
+#define SCIF4_SCFTDR_D (0xFFu)
+
+#define SCIF4_SCFSR_DR (0x0001u)
+#define SCIF4_SCFSR_RDF (0x0002u)
+#define SCIF4_SCFSR_PER (0x0004u)
+#define SCIF4_SCFSR_FER (0x0008u)
+#define SCIF4_SCFSR_BRK (0x0010u)
+#define SCIF4_SCFSR_TDFE (0x0020u)
+#define SCIF4_SCFSR_TEND (0x0040u)
+#define SCIF4_SCFSR_ER (0x0080u)
+#define SCIF4_SCFSR_FERN (0x0F00u)
+#define SCIF4_SCFSR_PERN (0xF000u)
+
+#define SCIF4_SCFRDR_D (0xFFu)
+
+#define SCIF4_SCFCR_LOOP (0x0001u)
+#define SCIF4_SCFCR_RFRST (0x0002u)
+#define SCIF4_SCFCR_TFRST (0x0004u)
+#define SCIF4_SCFCR_MCE (0x0008u)
+#define SCIF4_SCFCR_TTRG (0x0030u)
+#define SCIF4_SCFCR_RTRG (0x00C0u)
+#define SCIF4_SCFCR_RSTRG (0x0700u)
+
+#define SCIF4_SCFDR_R (0x001Fu)
+#define SCIF4_SCFDR_T (0x1F00u)
+
+#define SCIF4_SCSPTR_SPB2DT (0x0001u)
+#define SCIF4_SCSPTR_SPB2IO (0x0002u)
+#define SCIF4_SCSPTR_SCKDT (0x0004u)
+#define SCIF4_SCSPTR_SCKIO (0x0008u)
+#define SCIF4_SCSPTR_CTSDT (0x0010u)
+#define SCIF4_SCSPTR_CTSIO (0x0020u)
+#define SCIF4_SCSPTR_RTSDT (0x0040u)
+#define SCIF4_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF4_SCLSR_ORER (0x0001u)
+
+#define SCIF4_SCEMR_ABCS (0x0001u)
+#define SCIF4_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS (0x0003u)
+#define SCIF5_SCSMR_STOP (0x0008u)
+#define SCIF5_SCSMR_OE (0x0010u)
+#define SCIF5_SCSMR_PE (0x0020u)
+#define SCIF5_SCSMR_CHR (0x0040u)
+#define SCIF5_SCSMR_CA (0x0080u)
+
+#define SCIF5_SCBRR_D (0xFFu)
+
+#define SCIF5_SCSCR_CKE (0x0003u)
+#define SCIF5_SCSCR_REIE (0x0008u)
+#define SCIF5_SCSCR_RE (0x0010u)
+#define SCIF5_SCSCR_TE (0x0020u)
+#define SCIF5_SCSCR_RIE (0x0040u)
+#define SCIF5_SCSCR_TIE (0x0080u)
+
+#define SCIF5_SCFTDR_D (0xFFu)
+
+#define SCIF5_SCFSR_DR (0x0001u)
+#define SCIF5_SCFSR_RDF (0x0002u)
+#define SCIF5_SCFSR_PER (0x0004u)
+#define SCIF5_SCFSR_FER (0x0008u)
+#define SCIF5_SCFSR_BRK (0x0010u)
+#define SCIF5_SCFSR_TDFE (0x0020u)
+#define SCIF5_SCFSR_TEND (0x0040u)
+#define SCIF5_SCFSR_ER (0x0080u)
+#define SCIF5_SCFSR_FERN (0x0F00u)
+#define SCIF5_SCFSR_PERN (0xF000u)
+
+#define SCIF5_SCFRDR_D (0xFFu)
+
+#define SCIF5_SCFCR_LOOP (0x0001u)
+#define SCIF5_SCFCR_RFRST (0x0002u)
+#define SCIF5_SCFCR_TFRST (0x0004u)
+#define SCIF5_SCFCR_MCE (0x0008u)
+#define SCIF5_SCFCR_TTRG (0x0030u)
+#define SCIF5_SCFCR_RTRG (0x00C0u)
+#define SCIF5_SCFCR_RSTRG (0x0700u)
+
+#define SCIF5_SCFDR_R (0x001Fu)
+#define SCIF5_SCFDR_T (0x1F00u)
+
+#define SCIF5_SCSPTR_SPB2DT (0x0001u)
+#define SCIF5_SCSPTR_SPB2IO (0x0002u)
+#define SCIF5_SCSPTR_SCKDT (0x0004u)
+#define SCIF5_SCSPTR_SCKIO (0x0008u)
+#define SCIF5_SCSPTR_CTSDT (0x0010u)
+#define SCIF5_SCSPTR_CTSIO (0x0020u)
+#define SCIF5_SCSPTR_RTSDT (0x0040u)
+#define SCIF5_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF5_SCLSR_ORER (0x0001u)
+
+#define SCIF5_SCEMR_ABCS (0x0001u)
+#define SCIF5_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS (0x0003u)
+#define SCIF6_SCSMR_STOP (0x0008u)
+#define SCIF6_SCSMR_OE (0x0010u)
+#define SCIF6_SCSMR_PE (0x0020u)
+#define SCIF6_SCSMR_CHR (0x0040u)
+#define SCIF6_SCSMR_CA (0x0080u)
+
+#define SCIF6_SCBRR_D (0xFFu)
+
+#define SCIF6_SCSCR_CKE (0x0003u)
+#define SCIF6_SCSCR_REIE (0x0008u)
+#define SCIF6_SCSCR_RE (0x0010u)
+#define SCIF6_SCSCR_TE (0x0020u)
+#define SCIF6_SCSCR_RIE (0x0040u)
+#define SCIF6_SCSCR_TIE (0x0080u)
+
+#define SCIF6_SCFTDR_D (0xFFu)
+
+#define SCIF6_SCFSR_DR (0x0001u)
+#define SCIF6_SCFSR_RDF (0x0002u)
+#define SCIF6_SCFSR_PER (0x0004u)
+#define SCIF6_SCFSR_FER (0x0008u)
+#define SCIF6_SCFSR_BRK (0x0010u)
+#define SCIF6_SCFSR_TDFE (0x0020u)
+#define SCIF6_SCFSR_TEND (0x0040u)
+#define SCIF6_SCFSR_ER (0x0080u)
+#define SCIF6_SCFSR_FERN (0x0F00u)
+#define SCIF6_SCFSR_PERN (0xF000u)
+
+#define SCIF6_SCFRDR_D (0xFFu)
+
+#define SCIF6_SCFCR_LOOP (0x0001u)
+#define SCIF6_SCFCR_RFRST (0x0002u)
+#define SCIF6_SCFCR_TFRST (0x0004u)
+#define SCIF6_SCFCR_MCE (0x0008u)
+#define SCIF6_SCFCR_TTRG (0x0030u)
+#define SCIF6_SCFCR_RTRG (0x00C0u)
+#define SCIF6_SCFCR_RSTRG (0x0700u)
+
+#define SCIF6_SCFDR_R (0x001Fu)
+#define SCIF6_SCFDR_T (0x1F00u)
+
+#define SCIF6_SCSPTR_SPB2DT (0x0001u)
+#define SCIF6_SCSPTR_SPB2IO (0x0002u)
+#define SCIF6_SCSPTR_SCKDT (0x0004u)
+#define SCIF6_SCSPTR_SCKIO (0x0008u)
+#define SCIF6_SCSPTR_CTSDT (0x0010u)
+#define SCIF6_SCSPTR_CTSIO (0x0020u)
+#define SCIF6_SCSPTR_RTSDT (0x0040u)
+#define SCIF6_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF6_SCLSR_ORER (0x0001u)
+
+#define SCIF6_SCEMR_ABCS (0x0001u)
+#define SCIF6_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS (0x0003u)
+#define SCIF7_SCSMR_STOP (0x0008u)
+#define SCIF7_SCSMR_OE (0x0010u)
+#define SCIF7_SCSMR_PE (0x0020u)
+#define SCIF7_SCSMR_CHR (0x0040u)
+#define SCIF7_SCSMR_CA (0x0080u)
+
+#define SCIF7_SCBRR_D (0xFFu)
+
+#define SCIF7_SCSCR_CKE (0x0003u)
+#define SCIF7_SCSCR_REIE (0x0008u)
+#define SCIF7_SCSCR_RE (0x0010u)
+#define SCIF7_SCSCR_TE (0x0020u)
+#define SCIF7_SCSCR_RIE (0x0040u)
+#define SCIF7_SCSCR_TIE (0x0080u)
+
+#define SCIF7_SCFTDR_D (0xFFu)
+
+#define SCIF7_SCFSR_DR (0x0001u)
+#define SCIF7_SCFSR_RDF (0x0002u)
+#define SCIF7_SCFSR_PER (0x0004u)
+#define SCIF7_SCFSR_FER (0x0008u)
+#define SCIF7_SCFSR_BRK (0x0010u)
+#define SCIF7_SCFSR_TDFE (0x0020u)
+#define SCIF7_SCFSR_TEND (0x0040u)
+#define SCIF7_SCFSR_ER (0x0080u)
+#define SCIF7_SCFSR_FERN (0x0F00u)
+#define SCIF7_SCFSR_PERN (0xF000u)
+
+#define SCIF7_SCFRDR_D (0xFFu)
+
+#define SCIF7_SCFCR_LOOP (0x0001u)
+#define SCIF7_SCFCR_RFRST (0x0002u)
+#define SCIF7_SCFCR_TFRST (0x0004u)
+#define SCIF7_SCFCR_MCE (0x0008u)
+#define SCIF7_SCFCR_TTRG (0x0030u)
+#define SCIF7_SCFCR_RTRG (0x00C0u)
+#define SCIF7_SCFCR_RSTRG (0x0700u)
+
+#define SCIF7_SCFDR_R (0x001Fu)
+#define SCIF7_SCFDR_T (0x1F00u)
+
+#define SCIF7_SCSPTR_SPB2DT (0x0001u)
+#define SCIF7_SCSPTR_SPB2IO (0x0002u)
+#define SCIF7_SCSPTR_SCKDT (0x0004u)
+#define SCIF7_SCSPTR_SCKIO (0x0008u)
+#define SCIF7_SCSPTR_CTSDT (0x0010u)
+#define SCIF7_SCSPTR_CTSIO (0x0020u)
+#define SCIF7_SCSPTR_RTSDT (0x0040u)
+#define SCIF7_SCSPTR_RTSIO (0x0080u)
+
+#define SCIF7_SCLSR_ORER (0x0001u)
+
+#define SCIF7_SCEMR_ABCS (0x0001u)
+#define SCIF7_SCEMR_BGDM (0x0080u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS (0x0003u)
+#define SCIFn_SCSMR_STOP (0x0008u)
+#define SCIFn_SCSMR_OE (0x0010u)
+#define SCIFn_SCSMR_PE (0x0020u)
+#define SCIFn_SCSMR_CHR (0x0040u)
+#define SCIFn_SCSMR_CA (0x0080u)
+
+#define SCIFn_SCBRR_D (0xFFu)
+
+#define SCIFn_SCSCR_CKE (0x0003u)
+#define SCIFn_SCSCR_REIE (0x0008u)
+#define SCIFn_SCSCR_RE (0x0010u)
+#define SCIFn_SCSCR_TE (0x0020u)
+#define SCIFn_SCSCR_RIE (0x0040u)
+#define SCIFn_SCSCR_TIE (0x0080u)
+
+#define SCIFn_SCFTDR_D (0xFFu)
+
+#define SCIFn_SCFSR_DR (0x0001u)
+#define SCIFn_SCFSR_RDF (0x0002u)
+#define SCIFn_SCFSR_PER (0x0004u)
+#define SCIFn_SCFSR_FER (0x0008u)
+#define SCIFn_SCFSR_BRK (0x0010u)
+#define SCIFn_SCFSR_TDFE (0x0020u)
+#define SCIFn_SCFSR_TEND (0x0040u)
+#define SCIFn_SCFSR_ER (0x0080u)
+#define SCIFn_SCFSR_FERN (0x0F00u)
+#define SCIFn_SCFSR_PERN (0xF000u)
+
+#define SCIFn_SCFRDR_D (0xFFu)
+
+#define SCIFn_SCFCR_LOOP (0x0001u)
+#define SCIFn_SCFCR_RFRST (0x0002u)
+#define SCIFn_SCFCR_TFRST (0x0004u)
+#define SCIFn_SCFCR_MCE (0x0008u)
+#define SCIFn_SCFCR_TTRG (0x0030u)
+#define SCIFn_SCFCR_RTRG (0x00C0u)
+#define SCIFn_SCFCR_RSTRG (0x0700u)
+
+#define SCIFn_SCFDR_R (0x001Fu)
+#define SCIFn_SCFDR_T (0x1F00u)
+
+#define SCIFn_SCSPTR_SPB2DT (0x0001u)
+#define SCIFn_SCSPTR_SPB2IO (0x0002u)
+#define SCIFn_SCSPTR_SCKDT (0x0004u)
+#define SCIFn_SCSPTR_SCKIO (0x0008u)
+#define SCIFn_SCSPTR_CTSDT (0x0010u)
+#define SCIFn_SCSPTR_CTSIO (0x0020u)
+#define SCIFn_SCSPTR_RTSDT (0x0040u)
+#define SCIFn_SCSPTR_RTSIO (0x0080u)
+
+#define SCIFn_SCLSR_ORER (0x0001u)
+
+#define SCIFn_SCEMR_ABCS (0x0001u)
+#define SCIFn_SCEMR_BGDM (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS_SHIFT (0u)
+#define SCIF0_SCSMR_STOP_SHIFT (3u)
+#define SCIF0_SCSMR_OE_SHIFT (4u)
+#define SCIF0_SCSMR_PE_SHIFT (5u)
+#define SCIF0_SCSMR_CHR_SHIFT (6u)
+#define SCIF0_SCSMR_CA_SHIFT (7u)
+
+#define SCIF0_SCBRR_D_SHIFT (0u)
+
+#define SCIF0_SCSCR_CKE_SHIFT (0u)
+#define SCIF0_SCSCR_REIE_SHIFT (3u)
+#define SCIF0_SCSCR_RE_SHIFT (4u)
+#define SCIF0_SCSCR_TE_SHIFT (5u)
+#define SCIF0_SCSCR_RIE_SHIFT (6u)
+#define SCIF0_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF0_SCFTDR_D_SHIFT (0u)
+
+#define SCIF0_SCFSR_DR_SHIFT (0u)
+#define SCIF0_SCFSR_RDF_SHIFT (1u)
+#define SCIF0_SCFSR_PER_SHIFT (2u)
+#define SCIF0_SCFSR_FER_SHIFT (3u)
+#define SCIF0_SCFSR_BRK_SHIFT (4u)
+#define SCIF0_SCFSR_TDFE_SHIFT (5u)
+#define SCIF0_SCFSR_TEND_SHIFT (6u)
+#define SCIF0_SCFSR_ER_SHIFT (7u)
+#define SCIF0_SCFSR_FERN_SHIFT (8u)
+#define SCIF0_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF0_SCFRDR_D_SHIFT (0u)
+
+#define SCIF0_SCFCR_LOOP_SHIFT (0u)
+#define SCIF0_SCFCR_RFRST_SHIFT (1u)
+#define SCIF0_SCFCR_TFRST_SHIFT (2u)
+#define SCIF0_SCFCR_MCE_SHIFT (3u)
+#define SCIF0_SCFCR_TTRG_SHIFT (4u)
+#define SCIF0_SCFCR_RTRG_SHIFT (6u)
+#define SCIF0_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF0_SCFDR_R_SHIFT (0u)
+#define SCIF0_SCFDR_T_SHIFT (8u)
+
+#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF0_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF0_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF0_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF0_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF0_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF0_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF0_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF0_SCEMR_ABCS_SHIFT (0u)
+#define SCIF0_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS_SHIFT (0u)
+#define SCIF1_SCSMR_STOP_SHIFT (3u)
+#define SCIF1_SCSMR_OE_SHIFT (4u)
+#define SCIF1_SCSMR_PE_SHIFT (5u)
+#define SCIF1_SCSMR_CHR_SHIFT (6u)
+#define SCIF1_SCSMR_CA_SHIFT (7u)
+
+#define SCIF1_SCBRR_D_SHIFT (0u)
+
+#define SCIF1_SCSCR_CKE_SHIFT (0u)
+#define SCIF1_SCSCR_REIE_SHIFT (3u)
+#define SCIF1_SCSCR_RE_SHIFT (4u)
+#define SCIF1_SCSCR_TE_SHIFT (5u)
+#define SCIF1_SCSCR_RIE_SHIFT (6u)
+#define SCIF1_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF1_SCFTDR_D_SHIFT (0u)
+
+#define SCIF1_SCFSR_DR_SHIFT (0u)
+#define SCIF1_SCFSR_RDF_SHIFT (1u)
+#define SCIF1_SCFSR_PER_SHIFT (2u)
+#define SCIF1_SCFSR_FER_SHIFT (3u)
+#define SCIF1_SCFSR_BRK_SHIFT (4u)
+#define SCIF1_SCFSR_TDFE_SHIFT (5u)
+#define SCIF1_SCFSR_TEND_SHIFT (6u)
+#define SCIF1_SCFSR_ER_SHIFT (7u)
+#define SCIF1_SCFSR_FERN_SHIFT (8u)
+#define SCIF1_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF1_SCFRDR_D_SHIFT (0u)
+
+#define SCIF1_SCFCR_LOOP_SHIFT (0u)
+#define SCIF1_SCFCR_RFRST_SHIFT (1u)
+#define SCIF1_SCFCR_TFRST_SHIFT (2u)
+#define SCIF1_SCFCR_MCE_SHIFT (3u)
+#define SCIF1_SCFCR_TTRG_SHIFT (4u)
+#define SCIF1_SCFCR_RTRG_SHIFT (6u)
+#define SCIF1_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF1_SCFDR_R_SHIFT (0u)
+#define SCIF1_SCFDR_T_SHIFT (8u)
+
+#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF1_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF1_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF1_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF1_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF1_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF1_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF1_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF1_SCEMR_ABCS_SHIFT (0u)
+#define SCIF1_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS_SHIFT (0u)
+#define SCIF2_SCSMR_STOP_SHIFT (3u)
+#define SCIF2_SCSMR_OE_SHIFT (4u)
+#define SCIF2_SCSMR_PE_SHIFT (5u)
+#define SCIF2_SCSMR_CHR_SHIFT (6u)
+#define SCIF2_SCSMR_CA_SHIFT (7u)
+
+#define SCIF2_SCBRR_D_SHIFT (0u)
+
+#define SCIF2_SCSCR_CKE_SHIFT (0u)
+#define SCIF2_SCSCR_REIE_SHIFT (3u)
+#define SCIF2_SCSCR_RE_SHIFT (4u)
+#define SCIF2_SCSCR_TE_SHIFT (5u)
+#define SCIF2_SCSCR_RIE_SHIFT (6u)
+#define SCIF2_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF2_SCFTDR_D_SHIFT (0u)
+
+#define SCIF2_SCFSR_DR_SHIFT (0u)
+#define SCIF2_SCFSR_RDF_SHIFT (1u)
+#define SCIF2_SCFSR_PER_SHIFT (2u)
+#define SCIF2_SCFSR_FER_SHIFT (3u)
+#define SCIF2_SCFSR_BRK_SHIFT (4u)
+#define SCIF2_SCFSR_TDFE_SHIFT (5u)
+#define SCIF2_SCFSR_TEND_SHIFT (6u)
+#define SCIF2_SCFSR_ER_SHIFT (7u)
+#define SCIF2_SCFSR_FERN_SHIFT (8u)
+#define SCIF2_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF2_SCFRDR_D_SHIFT (0u)
+
+#define SCIF2_SCFCR_LOOP_SHIFT (0u)
+#define SCIF2_SCFCR_RFRST_SHIFT (1u)
+#define SCIF2_SCFCR_TFRST_SHIFT (2u)
+#define SCIF2_SCFCR_MCE_SHIFT (3u)
+#define SCIF2_SCFCR_TTRG_SHIFT (4u)
+#define SCIF2_SCFCR_RTRG_SHIFT (6u)
+#define SCIF2_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF2_SCFDR_R_SHIFT (0u)
+#define SCIF2_SCFDR_T_SHIFT (8u)
+
+#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF2_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF2_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF2_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF2_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF2_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF2_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF2_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF2_SCEMR_ABCS_SHIFT (0u)
+#define SCIF2_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS_SHIFT (0u)
+#define SCIF3_SCSMR_STOP_SHIFT (3u)
+#define SCIF3_SCSMR_OE_SHIFT (4u)
+#define SCIF3_SCSMR_PE_SHIFT (5u)
+#define SCIF3_SCSMR_CHR_SHIFT (6u)
+#define SCIF3_SCSMR_CA_SHIFT (7u)
+
+#define SCIF3_SCBRR_D_SHIFT (0u)
+
+#define SCIF3_SCSCR_CKE_SHIFT (0u)
+#define SCIF3_SCSCR_REIE_SHIFT (3u)
+#define SCIF3_SCSCR_RE_SHIFT (4u)
+#define SCIF3_SCSCR_TE_SHIFT (5u)
+#define SCIF3_SCSCR_RIE_SHIFT (6u)
+#define SCIF3_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF3_SCFTDR_D_SHIFT (0u)
+
+#define SCIF3_SCFSR_DR_SHIFT (0u)
+#define SCIF3_SCFSR_RDF_SHIFT (1u)
+#define SCIF3_SCFSR_PER_SHIFT (2u)
+#define SCIF3_SCFSR_FER_SHIFT (3u)
+#define SCIF3_SCFSR_BRK_SHIFT (4u)
+#define SCIF3_SCFSR_TDFE_SHIFT (5u)
+#define SCIF3_SCFSR_TEND_SHIFT (6u)
+#define SCIF3_SCFSR_ER_SHIFT (7u)
+#define SCIF3_SCFSR_FERN_SHIFT (8u)
+#define SCIF3_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF3_SCFRDR_D_SHIFT (0u)
+
+#define SCIF3_SCFCR_LOOP_SHIFT (0u)
+#define SCIF3_SCFCR_RFRST_SHIFT (1u)
+#define SCIF3_SCFCR_TFRST_SHIFT (2u)
+#define SCIF3_SCFCR_MCE_SHIFT (3u)
+#define SCIF3_SCFCR_TTRG_SHIFT (4u)
+#define SCIF3_SCFCR_RTRG_SHIFT (6u)
+#define SCIF3_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF3_SCFDR_R_SHIFT (0u)
+#define SCIF3_SCFDR_T_SHIFT (8u)
+
+#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF3_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF3_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF3_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF3_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF3_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF3_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF3_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF3_SCEMR_ABCS_SHIFT (0u)
+#define SCIF3_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS_SHIFT (0u)
+#define SCIF4_SCSMR_STOP_SHIFT (3u)
+#define SCIF4_SCSMR_OE_SHIFT (4u)
+#define SCIF4_SCSMR_PE_SHIFT (5u)
+#define SCIF4_SCSMR_CHR_SHIFT (6u)
+#define SCIF4_SCSMR_CA_SHIFT (7u)
+
+#define SCIF4_SCBRR_D_SHIFT (0u)
+
+#define SCIF4_SCSCR_CKE_SHIFT (0u)
+#define SCIF4_SCSCR_REIE_SHIFT (3u)
+#define SCIF4_SCSCR_RE_SHIFT (4u)
+#define SCIF4_SCSCR_TE_SHIFT (5u)
+#define SCIF4_SCSCR_RIE_SHIFT (6u)
+#define SCIF4_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF4_SCFTDR_D_SHIFT (0u)
+
+#define SCIF4_SCFSR_DR_SHIFT (0u)
+#define SCIF4_SCFSR_RDF_SHIFT (1u)
+#define SCIF4_SCFSR_PER_SHIFT (2u)
+#define SCIF4_SCFSR_FER_SHIFT (3u)
+#define SCIF4_SCFSR_BRK_SHIFT (4u)
+#define SCIF4_SCFSR_TDFE_SHIFT (5u)
+#define SCIF4_SCFSR_TEND_SHIFT (6u)
+#define SCIF4_SCFSR_ER_SHIFT (7u)
+#define SCIF4_SCFSR_FERN_SHIFT (8u)
+#define SCIF4_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF4_SCFRDR_D_SHIFT (0u)
+
+#define SCIF4_SCFCR_LOOP_SHIFT (0u)
+#define SCIF4_SCFCR_RFRST_SHIFT (1u)
+#define SCIF4_SCFCR_TFRST_SHIFT (2u)
+#define SCIF4_SCFCR_MCE_SHIFT (3u)
+#define SCIF4_SCFCR_TTRG_SHIFT (4u)
+#define SCIF4_SCFCR_RTRG_SHIFT (6u)
+#define SCIF4_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF4_SCFDR_R_SHIFT (0u)
+#define SCIF4_SCFDR_T_SHIFT (8u)
+
+#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF4_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF4_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF4_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF4_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF4_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF4_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF4_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF4_SCEMR_ABCS_SHIFT (0u)
+#define SCIF4_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS_SHIFT (0u)
+#define SCIF5_SCSMR_STOP_SHIFT (3u)
+#define SCIF5_SCSMR_OE_SHIFT (4u)
+#define SCIF5_SCSMR_PE_SHIFT (5u)
+#define SCIF5_SCSMR_CHR_SHIFT (6u)
+#define SCIF5_SCSMR_CA_SHIFT (7u)
+
+#define SCIF5_SCBRR_D_SHIFT (0u)
+
+#define SCIF5_SCSCR_CKE_SHIFT (0u)
+#define SCIF5_SCSCR_REIE_SHIFT (3u)
+#define SCIF5_SCSCR_RE_SHIFT (4u)
+#define SCIF5_SCSCR_TE_SHIFT (5u)
+#define SCIF5_SCSCR_RIE_SHIFT (6u)
+#define SCIF5_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF5_SCFTDR_D_SHIFT (0u)
+
+#define SCIF5_SCFSR_DR_SHIFT (0u)
+#define SCIF5_SCFSR_RDF_SHIFT (1u)
+#define SCIF5_SCFSR_PER_SHIFT (2u)
+#define SCIF5_SCFSR_FER_SHIFT (3u)
+#define SCIF5_SCFSR_BRK_SHIFT (4u)
+#define SCIF5_SCFSR_TDFE_SHIFT (5u)
+#define SCIF5_SCFSR_TEND_SHIFT (6u)
+#define SCIF5_SCFSR_ER_SHIFT (7u)
+#define SCIF5_SCFSR_FERN_SHIFT (8u)
+#define SCIF5_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF5_SCFRDR_D_SHIFT (0u)
+
+#define SCIF5_SCFCR_LOOP_SHIFT (0u)
+#define SCIF5_SCFCR_RFRST_SHIFT (1u)
+#define SCIF5_SCFCR_TFRST_SHIFT (2u)
+#define SCIF5_SCFCR_MCE_SHIFT (3u)
+#define SCIF5_SCFCR_TTRG_SHIFT (4u)
+#define SCIF5_SCFCR_RTRG_SHIFT (6u)
+#define SCIF5_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF5_SCFDR_R_SHIFT (0u)
+#define SCIF5_SCFDR_T_SHIFT (8u)
+
+#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF5_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF5_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF5_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF5_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF5_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF5_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF5_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF5_SCEMR_ABCS_SHIFT (0u)
+#define SCIF5_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS_SHIFT (0u)
+#define SCIF6_SCSMR_STOP_SHIFT (3u)
+#define SCIF6_SCSMR_OE_SHIFT (4u)
+#define SCIF6_SCSMR_PE_SHIFT (5u)
+#define SCIF6_SCSMR_CHR_SHIFT (6u)
+#define SCIF6_SCSMR_CA_SHIFT (7u)
+
+#define SCIF6_SCBRR_D_SHIFT (0u)
+
+#define SCIF6_SCSCR_CKE_SHIFT (0u)
+#define SCIF6_SCSCR_REIE_SHIFT (3u)
+#define SCIF6_SCSCR_RE_SHIFT (4u)
+#define SCIF6_SCSCR_TE_SHIFT (5u)
+#define SCIF6_SCSCR_RIE_SHIFT (6u)
+#define SCIF6_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF6_SCFTDR_D_SHIFT (0u)
+
+#define SCIF6_SCFSR_DR_SHIFT (0u)
+#define SCIF6_SCFSR_RDF_SHIFT (1u)
+#define SCIF6_SCFSR_PER_SHIFT (2u)
+#define SCIF6_SCFSR_FER_SHIFT (3u)
+#define SCIF6_SCFSR_BRK_SHIFT (4u)
+#define SCIF6_SCFSR_TDFE_SHIFT (5u)
+#define SCIF6_SCFSR_TEND_SHIFT (6u)
+#define SCIF6_SCFSR_ER_SHIFT (7u)
+#define SCIF6_SCFSR_FERN_SHIFT (8u)
+#define SCIF6_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF6_SCFRDR_D_SHIFT (0u)
+
+#define SCIF6_SCFCR_LOOP_SHIFT (0u)
+#define SCIF6_SCFCR_RFRST_SHIFT (1u)
+#define SCIF6_SCFCR_TFRST_SHIFT (2u)
+#define SCIF6_SCFCR_MCE_SHIFT (3u)
+#define SCIF6_SCFCR_TTRG_SHIFT (4u)
+#define SCIF6_SCFCR_RTRG_SHIFT (6u)
+#define SCIF6_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF6_SCFDR_R_SHIFT (0u)
+#define SCIF6_SCFDR_T_SHIFT (8u)
+
+#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF6_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF6_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF6_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF6_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF6_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF6_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF6_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF6_SCEMR_ABCS_SHIFT (0u)
+#define SCIF6_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS_SHIFT (0u)
+#define SCIF7_SCSMR_STOP_SHIFT (3u)
+#define SCIF7_SCSMR_OE_SHIFT (4u)
+#define SCIF7_SCSMR_PE_SHIFT (5u)
+#define SCIF7_SCSMR_CHR_SHIFT (6u)
+#define SCIF7_SCSMR_CA_SHIFT (7u)
+
+#define SCIF7_SCBRR_D_SHIFT (0u)
+
+#define SCIF7_SCSCR_CKE_SHIFT (0u)
+#define SCIF7_SCSCR_REIE_SHIFT (3u)
+#define SCIF7_SCSCR_RE_SHIFT (4u)
+#define SCIF7_SCSCR_TE_SHIFT (5u)
+#define SCIF7_SCSCR_RIE_SHIFT (6u)
+#define SCIF7_SCSCR_TIE_SHIFT (7u)
+
+#define SCIF7_SCFTDR_D_SHIFT (0u)
+
+#define SCIF7_SCFSR_DR_SHIFT (0u)
+#define SCIF7_SCFSR_RDF_SHIFT (1u)
+#define SCIF7_SCFSR_PER_SHIFT (2u)
+#define SCIF7_SCFSR_FER_SHIFT (3u)
+#define SCIF7_SCFSR_BRK_SHIFT (4u)
+#define SCIF7_SCFSR_TDFE_SHIFT (5u)
+#define SCIF7_SCFSR_TEND_SHIFT (6u)
+#define SCIF7_SCFSR_ER_SHIFT (7u)
+#define SCIF7_SCFSR_FERN_SHIFT (8u)
+#define SCIF7_SCFSR_PERN_SHIFT (12u)
+
+#define SCIF7_SCFRDR_D_SHIFT (0u)
+
+#define SCIF7_SCFCR_LOOP_SHIFT (0u)
+#define SCIF7_SCFCR_RFRST_SHIFT (1u)
+#define SCIF7_SCFCR_TFRST_SHIFT (2u)
+#define SCIF7_SCFCR_MCE_SHIFT (3u)
+#define SCIF7_SCFCR_TTRG_SHIFT (4u)
+#define SCIF7_SCFCR_RTRG_SHIFT (6u)
+#define SCIF7_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIF7_SCFDR_R_SHIFT (0u)
+#define SCIF7_SCFDR_T_SHIFT (8u)
+
+#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIF7_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIF7_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIF7_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIF7_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIF7_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIF7_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIF7_SCLSR_ORER_SHIFT (0u)
+
+#define SCIF7_SCEMR_ABCS_SHIFT (0u)
+#define SCIF7_SCEMR_BGDM_SHIFT (7u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS_SHIFT (0u)
+#define SCIFn_SCSMR_STOP_SHIFT (3u)
+#define SCIFn_SCSMR_OE_SHIFT (4u)
+#define SCIFn_SCSMR_PE_SHIFT (5u)
+#define SCIFn_SCSMR_CHR_SHIFT (6u)
+#define SCIFn_SCSMR_CA_SHIFT (7u)
+
+#define SCIFn_SCBRR_D_SHIFT (0u)
+
+#define SCIFn_SCSCR_CKE_SHIFT (0u)
+#define SCIFn_SCSCR_REIE_SHIFT (3u)
+#define SCIFn_SCSCR_RE_SHIFT (4u)
+#define SCIFn_SCSCR_TE_SHIFT (5u)
+#define SCIFn_SCSCR_RIE_SHIFT (6u)
+#define SCIFn_SCSCR_TIE_SHIFT (7u)
+
+#define SCIFn_SCFTDR_D_SHIFT (0u)
+
+#define SCIFn_SCFSR_DR_SHIFT (0u)
+#define SCIFn_SCFSR_RDF_SHIFT (1u)
+#define SCIFn_SCFSR_PER_SHIFT (2u)
+#define SCIFn_SCFSR_FER_SHIFT (3u)
+#define SCIFn_SCFSR_BRK_SHIFT (4u)
+#define SCIFn_SCFSR_TDFE_SHIFT (5u)
+#define SCIFn_SCFSR_TEND_SHIFT (6u)
+#define SCIFn_SCFSR_ER_SHIFT (7u)
+#define SCIFn_SCFSR_FERN_SHIFT (8u)
+#define SCIFn_SCFSR_PERN_SHIFT (12u)
+
+#define SCIFn_SCFRDR_D_SHIFT (0u)
+
+#define SCIFn_SCFCR_LOOP_SHIFT (0u)
+#define SCIFn_SCFCR_RFRST_SHIFT (1u)
+#define SCIFn_SCFCR_TFRST_SHIFT (2u)
+#define SCIFn_SCFCR_MCE_SHIFT (3u)
+#define SCIFn_SCFCR_TTRG_SHIFT (4u)
+#define SCIFn_SCFCR_RTRG_SHIFT (6u)
+#define SCIFn_SCFCR_RSTRG_SHIFT (8u)
+
+#define SCIFn_SCFDR_R_SHIFT (0u)
+#define SCIFn_SCFDR_T_SHIFT (8u)
+
+#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u)
+#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u)
+#define SCIFn_SCSPTR_SCKDT_SHIFT (2u)
+#define SCIFn_SCSPTR_SCKIO_SHIFT (3u)
+#define SCIFn_SCSPTR_CTSDT_SHIFT (4u)
+#define SCIFn_SCSPTR_CTSIO_SHIFT (5u)
+#define SCIFn_SCSPTR_RTSDT_SHIFT (6u)
+#define SCIFn_SCSPTR_RTSIO_SHIFT (7u)
+
+#define SCIFn_SCLSR_ORER_SHIFT (0u)
+
+#define SCIFn_SCEMR_ABCS_SHIFT (0u)
+#define SCIFn_SCEMR_BGDM_SHIFT (7u)
+
+
+#endif /* SCIF_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/usb_iobitmask.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/usb_iobitmask.h
new file mode 100644
index 000000000..cd671e699
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/usb_iobitmask.h
@@ -0,0 +1,731 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_iobitmask.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : USB register define header
+*******************************************************************************/
+#ifndef USB_IOBITMASK_H
+#define USB_IOBITMASK_H
+
+/*==============================================*/
+/* SYSCFG */
+/*==============================================*/
+#define USB_SYSCFG_USBE (0x0001u)
+#define USB_SYSCFG_UPLLE (0x0002u)
+#define USB_SYSCFG_UCKSEL (0x0004u)
+/* #define USB_SYSCFG_RESERVED1 (0x0008u) */
+#define USB_SYSCFG_DPRPU (0x0010u)
+#define USB_SYSCFG_DRPD (0x0020u)
+#define USB_SYSCFG_DCFM (0x0040u)
+#define USB_SYSCFG_HSE (0x0080u)
+/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */
+
+#define USB_SYSCFG_USBE_SHIFT (0)
+#define USB_SYSCFG_UPLLE_SHIFT (1)
+#define USB_SYSCFG_UCKSEL_SHIFT (2)
+/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */
+#define USB_SYSCFG_DPRPU_SHIFT (4)
+#define USB_SYSCFG_DRPD_SHIFT (5)
+#define USB_SYSCFG_DCFM_SHIFT (6)
+#define USB_SYSCFG_HSE_SHIFT (7)
+/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */
+
+/*==============================================*/
+/* BUSWAIT */
+/*==============================================*/
+#define USB_BUSWAIT_BWAIT (0x003Fu)
+
+#define USB_BUSWAIT_BWAIT_SHIFT (0)
+
+/*==============================================*/
+/* SYSSTS0 */
+/*==============================================*/
+#define USB_SYSSTS0_LNST (0x0003u)
+#define USB_SYSSTS0_SOFEA (0x0020u)
+#define USB_SYSSTS0_HTACT (0x0040u)
+
+#define USB_SYSSTS0_LNST_SHIFT (0)
+#define USB_SYSSTS0_SOFEA_SHIFT (5)
+#define USB_SYSSTS0_HTACT_SHIFT (6)
+
+/*==============================================*/
+/* DVSTCTR0 */
+/*==============================================*/
+#define USB_DVSTCTR0_RHST (0x0007u)
+/* #define USB_DVSTCTR0_RESERVED (0x0008u) */
+#define USB_DVSTCTR0_UACT (0x0010u)
+#define USB_DVSTCTR0_RESUME (0x0020u)
+#define USB_DVSTCTR0_USBRST (0x0040u)
+#define USB_DVSTCTR0_RWUPE (0x0080u)
+#define USB_DVSTCTR0_WKUP (0x0100u)
+
+#define USB_DVSTCTR0_RHST_SHIFT (0)
+/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */
+#define USB_DVSTCTR0_UACT_SHIFT (4)
+#define USB_DVSTCTR0_RESUME_SHIFT (5)
+#define USB_DVSTCTR0_USBRST_SHIFT (6)
+#define USB_DVSTCTR0_RWUPE_SHIFT (7)
+#define USB_DVSTCTR0_WKUP_SHIFT (8)
+
+/*==============================================*/
+/* TESTMODE */
+/*==============================================*/
+#define USB_TESTMODE_UTST (0x000Fu)
+/* #define USB_TESTMODE_RESERVED (0xFFF0u) */
+
+#define USB_TESTMODE_UTST_SHIFT (0)
+/* #define USB_TESTMODE_RESERVED_SHIFT (4) */
+
+/*==============================================*/
+/* DnFBCFG */
+/*==============================================*/
+/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */
+#define USB_DnFBCFG_TENDE (0x0010u)
+/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */
+#define USB_DnFBCFG_DFACC (0x3000u)
+/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */
+
+/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */
+#define USB_DnFBCFG_TENDE_SHIFT (4)
+/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */
+#define USB_DnFBCFG_DFACC_SHIFT (12)
+/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */
+
+/*==============================================*/
+/* CFIFO */
+/*==============================================*/
+#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL)
+
+#define USB_CFIFO_FIFOPORT_SHIFT (0)
+
+/*==============================================*/
+/* DnFIFO */
+/*==============================================*/
+#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL)
+
+#define USB_DnFIFO_FIFOPORT_SHIFT (0)
+
+/*==============================================*/
+/* CFIFOSEL */
+/*==============================================*/
+#define USB_CFIFOSEL_CURPIPE (0x000Fu)
+/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */
+#define USB_CFIFOSEL_ISEL_ (0x0020u)
+/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */
+#define USB_CFIFOSEL_BIGEND (0x0100u)
+/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */
+#define USB_CFIFOSEL_MBW (0x0C00u)
+/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */
+#define USB_CFIFOSEL_REW (0x4000u)
+#define USB_CFIFOSEL_RCNT (0x8000u)
+
+#define USB_CFIFOSEL_CURPIPE_SHIFT (0)
+/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */
+#define USB_CFIFOSEL_ISEL_SHIFT_ (5)
+/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */
+#define USB_CFIFOSEL_BIGEND_SHIFT (8)
+/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */
+#define USB_CFIFOSEL_MBW_SHIFT (10)
+/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */
+#define USB_CFIFOSEL_REW_SHIFT (14)
+#define USB_CFIFOSEL_RCNT_SHIFT (15)
+
+/*==============================================*/
+/* DnFIFOSEL */
+/*==============================================*/
+#define USB_DnFIFOSEL_CURPIPE (0x000Fu)
+/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */
+#define USB_DnFIFOSEL_BIGEND (0x0100u)
+/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */
+#define USB_DnFIFOSEL_MBW (0x0C00u)
+#define USB_DnFIFOSEL_DREQE (0x1000u)
+#define USB_DnFIFOSEL_DCLRM (0x2000u)
+#define USB_DnFIFOSEL_REW (0x4000u)
+#define USB_DnFIFOSEL_RCNT (0x8000u)
+
+#define USB_DnFIFOSEL_CURPIPE_SHIFT (0)
+/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */
+#define USB_DnFIFOSEL_BIGEND_SHIFT (8)
+/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */
+#define USB_DnFIFOSEL_MBW_SHIFT (10)
+#define USB_DnFIFOSEL_DREQE_SHIFT (12)
+#define USB_DnFIFOSEL_DCLRM_SHIFT (13)
+#define USB_DnFIFOSEL_REW_SHIFT (14)
+#define USB_DnFIFOSEL_RCNT_SHIFT (15)
+
+/*==============================================*/
+/* CFIFOCTR */
+/*==============================================*/
+#define USB_CFIFOCTR_DTLN (0x0FFFu)
+/* #define USB_CFIFOCTR_RESERVED (0x1000u) */
+#define USB_CFIFOCTR_FRDY (0x2000u)
+#define USB_CFIFOCTR_BCLR (0x4000u)
+#define USB_CFIFOCTR_BVAL (0x8000u)
+
+#define USB_CFIFOCTR_DTLN_SHIFT (0)
+/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */
+#define USB_CFIFOCTR_FRDY_SHIFT (13)
+#define USB_CFIFOCTR_BCLR_SHIFT (14)
+#define USB_CFIFOCTR_BVAL_SHIFT (15)
+
+/*==============================================*/
+/* DnFIFOCTR */
+/*==============================================*/
+#define USB_DnFIFOCTR_DTLN (0x0FFFu)
+/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */
+#define USB_DnFIFOCTR_FRDY (0x2000u)
+#define USB_DnFIFOCTR_BCLR (0x4000u)
+#define USB_DnFIFOCTR_BVAL (0x8000u)
+
+#define USB_DnFIFOCTR_DTLN_SHIFT (0)
+/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */
+#define USB_DnFIFOCTR_FRDY_SHIFT (13)
+#define USB_DnFIFOCTR_BCLR_SHIFT (14)
+#define USB_DnFIFOCTR_BVAL_SHIFT (15)
+
+/*==============================================*/
+/* INTENB0 */
+/*==============================================*/
+/* #define USB_INTENB0_RESERVED (0x00FFu) */
+#define USB_INTENB0_BRDYE (0x0100u)
+#define USB_INTENB0_NRDYE (0x0200u)
+#define USB_INTENB0_BEMPE (0x0400u)
+#define USB_INTENB0_CTRE (0x0800u)
+#define USB_INTENB0_DVSE (0x1000u)
+#define USB_INTENB0_SOFE (0x2000u)
+#define USB_INTENB0_RSME (0x4000u)
+#define USB_INTENB0_VBSE (0x8000u)
+
+/* #define USB_INTENB0_RESERVED_SHIFT (0) */
+#define USB_INTENB0_BRDYE_SHIFT (8)
+#define USB_INTENB0_NRDYE_SHIFT (9)
+#define USB_INTENB0_BEMPE_SHIFT (10)
+#define USB_INTENB0_CTRE_SHIFT (11)
+#define USB_INTENB0_DVSE_SHIFT (12)
+#define USB_INTENB0_SOFE_SHIFT (13)
+#define USB_INTENB0_RSME_SHIFT (14)
+#define USB_INTENB0_VBSE_SHIFT (15)
+
+/*==============================================*/
+/* INTENB1 */
+/*==============================================*/
+/* #define USB_INTENB1_RESERVED1 (0x000Fu) */
+#define USB_INTENB1_SACKE (0x0010u)
+#define USB_INTENB1_SIGNE (0x0020u)
+#define USB_INTENB1_EOFERRE (0x0040u)
+/* #define USB_INTENB1_RESERVED2 (0x0780u) */
+#define USB_INTENB1_ATTCHE (0x0800u)
+#define USB_INTENB1_DTCHE (0x1000u)
+/* #define USB_INTENB1_RESERVED3 (0x2000u) */
+#define USB_INTENB1_BCHGE (0x4000u)
+/* #define USB_INTENB1_RESERVED4 (0x8000u) */
+
+/* #define USB_INTENB1_RESERVED1_SHIFT (0) */
+#define USB_INTENB1_SACKE_SHIFT (4)
+#define USB_INTENB1_SIGNE_SHIFT (5)
+#define USB_INTENB1_EOFERRE_SHIFT (6)
+/* #define USB_INTENB1_RESERVED2_SHIFT (7) */
+#define USB_INTENB1_ATTCHE_SHIFT (11)
+#define USB_INTENB1_DTCHE_SHIFT (12)
+/* #define USB_INTENB1_RESERVED3_SHIFT (13) */
+#define USB_INTENB1_BCHGE_SHIFT (14)
+/* #define USB_INTENB1_RESERVED4_SHIFT (15) */
+
+/*==============================================*/
+/* BRDYENB */
+/*==============================================*/
+#define USB_BRDYENB (0xFFFFu)
+
+#define USB_BRDYENB_SHIFT (0)
+
+/*==============================================*/
+/* NRDYENB */
+/*==============================================*/
+#define USB_NRDYENB (0xFFFFu)
+
+#define USB_NRDYENB_SHIFT (0)
+
+/*==============================================*/
+/* BEMPENB */
+/*==============================================*/
+#define USB_BEMPENB (0xFFFFu)
+
+#define USB_BEMPENB_SHIFT (0)
+
+/*==============================================*/
+/* SOFCFG */
+/*==============================================*/
+/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */
+#define USB_SOFCFG_BRDYM (0x0040u)
+/* #define USB_SOFCFG_RESERVED2 (0x0080u) */
+#define USB_SOFCFG_TRNENSEL (0x0100u)
+/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */
+
+/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */
+#define USB_SOFCFG_BRDYM_SHIFT (6)
+/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */
+#define USB_SOFCFG_TRNENSEL_SHIFT (8)
+/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */
+
+/*==============================================*/
+/* INTSTS0 */
+/*==============================================*/
+#define USB_INTSTS0_CTSQ (0x0007u)
+#define USB_INTSTS0_VALID (0x0008u)
+#define USB_INTSTS0_DVSQ (0x0070u)
+#define USB_INTSTS0_VBSTS (0x0080u)
+#define USB_INTSTS0_BRDY (0x0100u)
+#define USB_INTSTS0_NRDY (0x0200u)
+#define USB_INTSTS0_BEMP (0x0400u)
+#define USB_INTSTS0_CTRT (0x0800u)
+#define USB_INTSTS0_DVST (0x1000u)
+#define USB_INTSTS0_SOFR (0x2000u)
+#define USB_INTSTS0_RESM (0x4000u)
+#define USB_INTSTS0_VBINT (0x8000u)
+
+#define USB_INTSTS0_CTSQ_SHIFT (0)
+#define USB_INTSTS0_VALID_SHIFT (3)
+#define USB_INTSTS0_DVSQ_SHIFT (4)
+#define USB_INTSTS0_VBSTS_SHIFT (7)
+#define USB_INTSTS0_BRDY_SHIFT (8)
+#define USB_INTSTS0_NRDY_SHIFT (9)
+#define USB_INTSTS0_BEMP_SHIFT (10)
+#define USB_INTSTS0_CTRT_SHIFT (11)
+#define USB_INTSTS0_DVST_SHIFT (12)
+#define USB_INTSTS0_SOFR_SHIFT (13)
+#define USB_INTSTS0_RESM_SHIFT (14)
+#define USB_INTSTS0_VBINT_SHIFT (15)
+
+/*==============================================*/
+/* INTSTS1 */
+/*==============================================*/
+/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */
+#define USB_INTSTS1_SACK (0x0010u)
+#define USB_INTSTS1_SIGN (0x0020u)
+#define USB_INTSTS1_EOFERR (0x0040u)
+/* #define USB_INTSTS1_RESERVED2 (0x0780u) */
+#define USB_INTSTS1_ATTCH (0x0800u)
+#define USB_INTSTS1_DTCH (0x1000u)
+/* #define USB_INTSTS1_RESERVED3 (0x2000u) */
+#define USB_INTSTS1_BCHG (0x4000u)
+/* #define USB_INTSTS1_RESERVED4 (0x8000u) */
+
+/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */
+#define USB_INTSTS1_SACK_SHIFT (4)
+#define USB_INTSTS1_SIGN_SHIFT (5)
+#define USB_INTSTS1_EOFERR_SHIFT (6)
+/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */
+#define USB_INTSTS1_ATTCH_SHIFT (11)
+#define USB_INTSTS1_DTCH_SHIFT (12)
+/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */
+#define USB_INTSTS1_BCHG_SHIFT (14)
+/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */
+
+/*==============================================*/
+/* BRDYSTS */
+/*==============================================*/
+#define USB_BRDYSTS (0xFFFFu)
+
+#define USB_BRDYSTS_SHIFT (0)
+
+/*==============================================*/
+/* NRDYSTS */
+/*==============================================*/
+#define USB_NRDYSTS (0xFFFFu)
+
+#define USB_NRDYSTS_SHIFT (0)
+
+/*==============================================*/
+/* BEMPSTS */
+/*==============================================*/
+#define USB_BEMPSTS (0xFFFFu)
+
+#define USB_BEMPSTS_SHIFT (0)
+
+/*==============================================*/
+/* FRMNUM */
+/*==============================================*/
+#define USB_FRMNUM_FRNM (0x07FFu)
+/* #define USB_FRMNUM_RESERVED (0x3800u) */
+#define USB_FRMNUM_CRCE (0x4000u)
+#define USB_FRMNUM_OVRN (0x8000u)
+
+#define USB_FRMNUM_FRNM_SHIFT (0)
+/* #define USB_FRMNUM_RESERVED_SHIFT (11) */
+#define USB_FRMNUM_CRCE_SHIFT (14)
+#define USB_FRMNUM_OVRN_SHIFT (15)
+
+/*==============================================*/
+/* UFRMNUM */
+/*==============================================*/
+#define USB_UFRMNUM_UFRNM (0x0007u)
+/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */
+
+#define USB_UFRMNUM_UFRNM_SHIFT (0)
+/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */
+
+/*==============================================*/
+/* USBADDR */
+/*==============================================*/
+#define USB_USBADDR_USBADDR (0x007Fu)
+/* #define USB_USBADDR_RESERVED (0xFF80u) */
+
+#define USB_USBADDR_USBADDR_SHIFT (0)
+/* #define USB_USBADDR_RESERVED_SHIFT (7) */
+
+/*==============================================*/
+/* USBREQ */
+/*==============================================*/
+#define USB_USBREQ_BMREQUESTTYPE (0x00FFu)
+#define USB_USBREQ_BREQUEST (0xFF00u)
+
+#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0)
+#define USB_USBREQ_BREQUEST_SHIFT (8)
+
+/*==============================================*/
+/* USBVAL */
+/*==============================================*/
+#define USB_USBVAL (0xFFFFu)
+
+#define USB_USBVAL_SHIFT (0)
+
+/*==============================================*/
+/* USBINDX */
+/*==============================================*/
+#define USB_USBINDX (0xFFFFu)
+
+#define USB_USBINDX_SHIFT (0)
+
+/*==============================================*/
+/* USBLENG */
+/*==============================================*/
+#define USB_USBLENG (0xFFFFu)
+
+#define USB_USBLENG_SHIFT (0)
+
+/*==============================================*/
+/* DCPCFG */
+/*==============================================*/
+/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */
+#define USB_DCPCFG_DIR (0x0010u)
+/* #define USB_DCPCFG_RESERVED2 (0x0060u) */
+#define USB_DCPCFG_SHTNAK (0x0080u)
+#define USB_DCPCFG_CNTMD (0x0100u)
+/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */
+
+/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */
+#define USB_DCPCFG_DIR_SHIFT (4)
+/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */
+#define USB_DCPCFG_SHTNK_SHIFT (7)
+#define USB_DCPCFG_CNTMD_SHIFT (8)
+/* #define USB_DCPCFG_RESERVED3 (9) */
+
+/*==============================================*/
+/* DCPMAXP */
+/*==============================================*/
+#define USB_DCPMAXP_MXPS (0x007Fu)
+/* #define USB_DCPMAXP_RESERVED (0x0F80u) */
+#define USB_DCPMAXP_DEVSEL (0xF000u)
+
+#define USB_DCPMAXP_MXPS_SHIFT (0)
+/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */
+#define USB_DCPMAXP_DEVSEL_SHIFT (12)
+
+/*==============================================*/
+/* DCPCTR */
+/*==============================================*/
+#define USB_DCPCTR_PID (0x0003u)
+#define USB_DCPCTR_CCPL (0x0004u)
+/* #define USB_DCPCTR_RESERVED1 (0x0008u) */
+#define USB_DCPCTR_PINGE (0x0010u)
+#define USB_DCPCTR_PBUSY (0x0020u)
+#define USB_DCPCTR_SQMON (0x0040u)
+#define USB_DCPCTR_SQSET (0x0080u)
+#define USB_DCPCTR_SQCLR (0x0100u)
+/* #define USB_DCPCTR_RESERVED2 (0x0600u) */
+#define USB_DCPCTR_SUREQCLR (0x0800u)
+#define USB_DCPCTR_CSSTS (0x1000u)
+#define USB_DCPCTR_CSCLR (0x2000u)
+#define USB_DCPCTR_SUREQ (0x4000u)
+#define USB_DCPCTR_BSTS (0x8000u)
+
+#define USB_DCPCTR_PID_SHIFT (0)
+#define USB_DCPCTR_CCPL_SHIFT (2)
+/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */
+#define USB_DCPCTR_PINGE_SHIFT (4)
+#define USB_DCPCTR_PBUSY_SHIFT (5)
+#define USB_DCPCTR_SQMON_SHIFT (6)
+#define USB_DCPCTR_SQSET_SHIFT (7)
+#define USB_DCPCTR_SQCLR_SHIFT (8)
+/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */
+#define USB_DCPCTR_SUREQCLR_SHIFT (11)
+#define USB_DCPCTR_CSSTS_SHIFT (12)
+#define USB_DCPCTR_CSCLR_SHIFT (13)
+#define USB_DCPCTR_SUREQ_SHIFT (14)
+#define USB_DCPCTR_BSTS_SHIFT (15)
+
+/*==============================================*/
+/* PIPESEL */
+/*==============================================*/
+#define USB_PIPESEL_PIPESEL (0x000Fu)
+/* #define USB_PIPESEL_RESERVED (0xFFF0u) */
+
+#define USB_PIPESEL_PIPESEL_SHIFT (0)
+/* #define USB_PIPESEL_RESERVED_SHIFT (4) */
+
+/*==============================================*/
+/* PIPECFG */
+/*==============================================*/
+#define USB_PIPECFG_EPNUM (0x000Fu)
+#define USB_PIPECFG_DIR (0x0010u)
+/* #define USB_PIPECFG_RESERVED1 (0x0060u) */
+#define USB_PIPECFG_SHTNAK (0x0080u)
+#define USB_PIPECFG_CNTMD (0x0100u)
+#define USB_PIPECFG_DBLB (0x0200u)
+#define USB_PIPECFG_BFRE (0x0400u)
+/* #define USB_PIPECFG_RESERVED2 (0x3800u) */
+#define USB_PIPECFG_TYPE (0xC000u)
+
+#define USB_PIPECFG_EPNUM_SHIFT (0)
+#define USB_PIPECFG_DIR_SHIFT (4)
+/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */
+#define USB_PIPECFG_SHTNAK_SHIFT (7)
+#define USB_PIPECFG_CNTMD_SHIFT (8)
+#define USB_PIPECFG_DBLB_SHIFT (9)
+#define USB_PIPECFG_BFRE_SHIFT (10)
+/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */
+#define USB_PIPECFG_TYPE_SHIFT (14)
+
+/*==============================================*/
+/* PIPEBUF */
+/*==============================================*/
+#define USB_PIPEBUF_BUFNMB (0x00FFu)
+/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */
+#define USB_PIPEBUF_BUFSIZE (0x7C00u)
+/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */
+
+#define USB_PIPEBUF_BUFNMB_SHIFT (0)
+/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */
+#define USB_PIPEBUF_BUFSIZE_SHIFT (10)
+/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */
+
+/*==============================================*/
+/* PIPEMAXP */
+/*==============================================*/
+#define USB_PIPEMAXP_MXPS (0x07FFu)
+/* #define USB_PIPEMAXP_RESERVED (0x0800u) */
+#define USB_PIPEMAXP_DEVSEL (0xF000u)
+
+#define USB_PIPEMAXP_MXPS_SHIFT (0)
+/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */
+#define USB_PIPEMAXP_DEVSEL_SHIFT (12)
+
+/*==============================================*/
+/* PIPEPERI */
+/*==============================================*/
+#define USB_PIPEPERI_IITV (0x0007u)
+/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */
+#define USB_PIPEPERI_IFIS (0x1000u)
+/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */
+
+#define USB_PIPEPERI_IITV_SHIFT (0)
+/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */
+#define USB_PIPEPERI_IFIS_SHIFT (12)
+/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */
+
+/*==============================================*/
+/* PIPEnCTR_1_5 */
+/*==============================================*/
+#define USB_PIPEnCTR_1_5_PID (0x0003u)
+/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */
+#define USB_PIPEnCTR_1_5_PBUSY (0x0020u)
+#define USB_PIPEnCTR_1_5_SQMON (0x0040u)
+#define USB_PIPEnCTR_1_5_SQSET (0x0080u)
+#define USB_PIPEnCTR_1_5_SQCLR (0x0100u)
+#define USB_PIPEnCTR_1_5_ACLRM (0x0200u)
+#define USB_PIPEnCTR_1_5_ATREPM (0x0400u)
+/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */
+#define USB_PIPEnCTR_1_5_CSSTS (0x1000u)
+#define USB_PIPEnCTR_1_5_CSCLR (0x2000u)
+#define USB_PIPEnCTR_1_5_INBUFM (0x4000u)
+#define USB_PIPEnCTR_1_5_BSTS (0x8000u)
+
+#define USB_PIPEnCTR_1_5_PID_SHIFT (0)
+/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */
+#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5)
+#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6)
+#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7)
+#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8)
+#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9)
+#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10)
+/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */
+#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12)
+#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13)
+#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14)
+#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15)
+
+/*==============================================*/
+/* PIPEnCTR_6_8 */
+/*==============================================*/
+#define USB_PIPEnCTR_6_8_PID (0x0003u)
+/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */
+#define USB_PIPEnCTR_6_8_PBUSY (0x0020u)
+#define USB_PIPEnCTR_6_8_SQMON (0x0040u)
+#define USB_PIPEnCTR_6_8_SQSET (0x0080u)
+#define USB_PIPEnCTR_6_8_SQCLR (0x0100u)
+#define USB_PIPEnCTR_6_8_ACLRM (0x0200u)
+/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */
+#define USB_PIPEnCTR_6_8_CSSTS (0x1000u)
+#define USB_PIPEnCTR_6_8_CSCLR (0x2000u)
+/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */
+#define USB_PIPEnCTR_6_8_BSTS (0x8000u)
+
+#define USB_PIPEnCTR_6_8_PID_SHIFT (0)
+/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */
+#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5)
+#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6)
+#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7)
+#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8)
+#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9)
+/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */
+#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12)
+#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13)
+/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */
+#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15)
+
+/*==============================================*/
+/* PIPEnCTR_9 */
+/*==============================================*/
+#define USB_PIPEnCTR_9_PID (0x0003u)
+/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */
+#define USB_PIPEnCTR_9_PBUSY (0x0020u)
+#define USB_PIPEnCTR_9_SQMON (0x0040u)
+#define USB_PIPEnCTR_9_SQSET (0x0080u)
+#define USB_PIPEnCTR_9_SQCLR (0x0100u)
+#define USB_PIPEnCTR_9_ACLRM (0x0200u)
+#define USB_PIPEnCTR_9_ATREPM (0x0400u)
+/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */
+#define USB_PIPEnCTR_9_CSSTS (0x1000u)
+#define USB_PIPEnCTR_9_CSCLR (0x2000u)
+#define USB_PIPEnCTR_9_INBUFM (0x4000u)
+#define USB_PIPEnCTR_9_BSTS (0x8000u)
+
+#define USB_PIPEnCTR_9_PID_SHIFT (0)
+/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */
+#define USB_PIPEnCTR_9_PBUSY_SHIFT (5)
+#define USB_PIPEnCTR_9_SQMON_SHIFT (6)
+#define USB_PIPEnCTR_9_SQSET_SHIFT (7)
+#define USB_PIPEnCTR_9_SQCLR_SHIFT (8)
+#define USB_PIPEnCTR_9_ACLRM_SHIFT (9)
+#define USB_PIPEnCTR_9_ATREPM_SHIFT (10)
+/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */
+#define USB_PIPEnCTR_9_CSSTS_SHIFT (12)
+#define USB_PIPEnCTR_9_CSCLR_SHIFT (13)
+#define USB_PIPEnCTR_9_INBUFM_SHIFT (14)
+#define USB_PIPEnCTR_9_BSTS_SHIFT (15)
+
+/*==============================================*/
+/* PIPEnCTR_A_F */
+/*==============================================*/
+#define USB_PIPEnCTR_A_F_PID (0x0003u)
+/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */
+#define USB_PIPEnCTR_A_F_PBUSY (0x0020u)
+#define USB_PIPEnCTR_A_F_SQMON (0x0040u)
+#define USB_PIPEnCTR_A_F_SQSET (0x0080u)
+#define USB_PIPEnCTR_A_F_SQCLR (0x0100u)
+#define USB_PIPEnCTR_A_F_ACLRM (0x0200u)
+#define USB_PIPEnCTR_A_F_ATREPM (0x0400u)
+/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */
+#define USB_PIPEnCTR_A_F_INBUFM (0x4000u)
+#define USB_PIPEnCTR_A_F_BSTS (0x8000u)
+
+#define USB_PIPEnCTR_A_F_PID_SHIFT (0)
+/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */
+#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5)
+#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6)
+#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7)
+#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8)
+#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9)
+#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10)
+/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */
+#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14)
+#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15)
+
+/*==============================================*/
+/* PIPEnTRE */
+/*==============================================*/
+/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */
+#define USB_PIPEnTRE_TRCLR (0x0100u)
+#define USB_PIPEnTRE_TRENB (0x0200u)
+/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */
+
+/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */
+#define USB_PIPEnTRE_TRCLR_SHIFT (8)
+#define USB_PIPEnTRE_TRENB_SHIFT (9)
+/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */
+
+/*==============================================*/
+/* PIPEnTRN */
+/*==============================================*/
+#define USB_PIPEnTRN (0xFFFFu)
+
+#define USB_PIPEnTRN_SHIFT (0)
+
+/*==============================================*/
+/* DEVADDn */
+/*==============================================*/
+/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */
+#define USB_DEVADDn_USBSPD (0x00C0u)
+#define USB_DEVADDn_HUBPORT (0x0700u)
+#define USB_DEVADDn_UPPHUB (0x7800u)
+/* #define USB_DEVADDn_RESERVED2 (0x8000u) */
+
+/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */
+#define USB_DEVADDn_USBSPD_SHIFT (6)
+#define USB_DEVADDn_HUBPORT_SHIFT (8)
+#define USB_DEVADDn_UPPHUB_SHIFT (11)
+/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */
+
+/*==============================================*/
+/* SUSPMODE */
+/*==============================================*/
+/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */
+#define USB_SUSPMODE_SUSPM (0x4000u)
+/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */
+
+/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */
+#define USB_SUSPMODE_SUSPM_SHIFT (14)
+/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */
+
+/*==============================================*/
+/* DnFIFOBm */
+/*==============================================*/
+#define USB_DnFIFOBm (0xFFFFu)
+
+#define USB_DnFIFOBm_SHIFT (0)
+
+#endif /* USB_IOBITMASK_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h
new file mode 100644
index 000000000..2d1855998
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef R7S72100_IODEFINE_H
+#define R7S72100_IODEFINE_H
+#define IODEFINE_H_VERSION 100
+
+enum iodefine_byte_select_t
+{
+ L = 0, H = 1,
+ LL= 0, LH = 1, HL = 2, HH = 3
+};
+
+/***********************************************************************
+ <<< [iodefine_reg32_t] >>>
+- Padding : sizeof(iodefine_reg32_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_t
+{
+ volatile uint32_t UINT32; /* 32-bit Access */
+ volatile uint16_t UINT16[2]; /* 16-bit Access */
+ volatile uint8_t UINT8[4]; /* 8-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+ <<< [iodefine_reg32_16_t] >>>
+- Padding : sizeof(iodefine_reg32_16_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_16_t
+{
+ volatile uint32_t UINT32; /* 32-bit Access */
+ volatile uint16_t UINT16[2]; /* 16-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+ <<< [iodefine_reg16_8_t] >>>
+- Padding : sizeof(iodefine_reg16_8_t) == 2
+- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg16_8_t
+{
+ volatile uint16_t UINT16; /* 16-bit Access */
+ volatile uint8_t UINT8[2]; /* 8-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+
+
+
+
+
+#include "adc_iodefine.h" /* (V1.00a) */
+#include "bsc_iodefine.h" /* (V1.00a) */
+#include "ceu_iodefine.h" /* (V1.00a) */
+#include "cpg_iodefine.h" /* (V1.00a) */
+#include "disc_iodefine.h" /* (V1.00a) */
+#include "dmac_iodefine.h" /* (V1.00a) */
+#include "dvdec_iodefine.h" /* (V1.00a) */
+#include "ether_iodefine.h" /* (V1.00a) */
+#include "flctl_iodefine.h" /* (V1.00a) */
+#include "gpio_iodefine.h" /* (V1.00a) */
+#include "ieb_iodefine.h" /* (V1.00a) */
+#include "inb_iodefine.h" /* (V1.00a) */
+#include "intc_iodefine.h" /* (V1.00a) */
+#include "irda_iodefine.h" /* (V1.00a) */
+#include "jcu_iodefine.h" /* (V1.00a) */
+#include "l2c_iodefine.h" /* (V1.00a) */
+#include "lin_iodefine.h" /* (V1.00a) */
+#include "lvds_iodefine.h" /* (V1.00a) */
+#include "mlb_iodefine.h" /* (V1.00a) */
+#include "mmc_iodefine.h" /* (V1.00a) */
+#include "mtu2_iodefine.h" /* (V1.00a) */
+#include "ostm_iodefine.h" /* (V1.00a) */
+#include "pfv_iodefine.h" /* (V1.00a) */
+#include "pwm_iodefine.h" /* (V1.00a) */
+#include "riic_iodefine.h" /* (V1.00a) */
+#include "romdec_iodefine.h" /* (V1.00a) */
+#include "rscan0_iodefine.h" /* (V1.00a) */
+#include "rspi_iodefine.h" /* (V1.00a) */
+#include "rtc_iodefine.h" /* (V1.00a) */
+#include "scif_iodefine.h" /* (V1.00a) */
+#include "scim_iodefine.h" /* (V1.00a) */
+#include "scux_iodefine.h" /* (V1.00a) */
+#include "sdg_iodefine.h" /* (V1.00a) */
+#include "spdif_iodefine.h" /* (V1.00a) */
+#include "spibsc_iodefine.h" /* (V1.00a) */
+#include "ssif_iodefine.h" /* (V1.00a) */
+#include "usb20_iodefine.h" /* (V1.00a) */
+#include "vdc5_iodefine.h" /* (V1.00a) */
+#include "wdt_iodefine.h" /* (V1.00a) */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h
new file mode 100644
index 000000000..55bc7ddd2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h
@@ -0,0 +1,98 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : adc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ADC_IODEFINE_H
+#define ADC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_adc
+{ /* ADC */
+ volatile uint16_t ADDRA; /* ADDRA */
+ volatile uint16_t ADDRB; /* ADDRB */
+ volatile uint16_t ADDRC; /* ADDRC */
+ volatile uint16_t ADDRD; /* ADDRD */
+ volatile uint16_t ADDRE; /* ADDRE */
+ volatile uint16_t ADDRF; /* ADDRF */
+ volatile uint16_t ADDRG; /* ADDRG */
+ volatile uint16_t ADDRH; /* ADDRH */
+ volatile uint8_t dummy32[16]; /* */
+ volatile uint16_t ADCMPHA; /* ADCMPHA */
+ volatile uint16_t ADCMPLA; /* ADCMPLA */
+ volatile uint16_t ADCMPHB; /* ADCMPHB */
+ volatile uint16_t ADCMPLB; /* ADCMPLB */
+ volatile uint16_t ADCMPHC; /* ADCMPHC */
+ volatile uint16_t ADCMPLC; /* ADCMPLC */
+ volatile uint16_t ADCMPHD; /* ADCMPHD */
+ volatile uint16_t ADCMPLD; /* ADCMPLD */
+ volatile uint16_t ADCMPHE; /* ADCMPHE */
+ volatile uint16_t ADCMPLE; /* ADCMPLE */
+ volatile uint16_t ADCMPHF; /* ADCMPHF */
+ volatile uint16_t ADCMPLF; /* ADCMPLF */
+ volatile uint16_t ADCMPHG; /* ADCMPHG */
+ volatile uint16_t ADCMPLG; /* ADCMPLG */
+ volatile uint16_t ADCMPHH; /* ADCMPHH */
+ volatile uint16_t ADCMPLH; /* ADCMPLH */
+ volatile uint8_t dummy33[32]; /* */
+ volatile uint16_t ADCSR; /* ADCSR */
+ volatile uint16_t ADCMPER; /* ADCMPER */
+ volatile uint16_t ADCMPSR; /* ADCMPSR */
+};
+
+
+#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA ADC.ADDRA
+#define ADCADDRB ADC.ADDRB
+#define ADCADDRC ADC.ADDRC
+#define ADCADDRD ADC.ADDRD
+#define ADCADDRE ADC.ADDRE
+#define ADCADDRF ADC.ADDRF
+#define ADCADDRG ADC.ADDRG
+#define ADCADDRH ADC.ADDRH
+#define ADCADCMPHA ADC.ADCMPHA
+#define ADCADCMPLA ADC.ADCMPLA
+#define ADCADCMPHB ADC.ADCMPHB
+#define ADCADCMPLB ADC.ADCMPLB
+#define ADCADCMPHC ADC.ADCMPHC
+#define ADCADCMPLC ADC.ADCMPLC
+#define ADCADCMPHD ADC.ADCMPHD
+#define ADCADCMPLD ADC.ADCMPLD
+#define ADCADCMPHE ADC.ADCMPHE
+#define ADCADCMPLE ADC.ADCMPLE
+#define ADCADCMPHF ADC.ADCMPHF
+#define ADCADCMPLF ADC.ADCMPLF
+#define ADCADCMPHG ADC.ADCMPHG
+#define ADCADCMPLG ADC.ADCMPLG
+#define ADCADCMPHH ADC.ADCMPHH
+#define ADCADCMPLH ADC.ADCMPLH
+#define ADCADCSR ADC.ADCSR
+#define ADCADCMPER ADC.ADCMPER
+#define ADCADCMPSR ADC.ADCMPSR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h
new file mode 100644
index 000000000..0d327ac76
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef BSC_IODEFINE_H
+#define BSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_bsc
+{ /* BSC */
+ volatile uint32_t CMNCR; /* CMNCR */
+#define BSC_CSnBCR_COUNT 6
+ volatile uint32_t CS0BCR; /* CS0BCR */
+ volatile uint32_t CS1BCR; /* CS1BCR */
+ volatile uint32_t CS2BCR; /* CS2BCR */
+ volatile uint32_t CS3BCR; /* CS3BCR */
+ volatile uint32_t CS4BCR; /* CS4BCR */
+ volatile uint32_t CS5BCR; /* CS5BCR */
+ volatile uint8_t dummy4[12]; /* */
+#define BSC_CSnWCR_COUNT 6
+ volatile uint32_t CS0WCR; /* CS0WCR */
+ volatile uint32_t CS1WCR; /* CS1WCR */
+ volatile uint32_t CS2WCR; /* CS2WCR */
+ volatile uint32_t CS3WCR; /* CS3WCR */
+ volatile uint32_t CS4WCR; /* CS4WCR */
+ volatile uint32_t CS5WCR; /* CS5WCR */
+ volatile uint8_t dummy5[12]; /* */
+ volatile uint32_t SDCR; /* SDCR */
+ volatile uint32_t RTCSR; /* RTCSR */
+ volatile uint32_t RTCNT; /* RTCNT */
+ volatile uint32_t RTCOR; /* RTCOR */
+ volatile uint8_t dummy6[4]; /* */
+#define BSC_TOSCORn_COUNT 6
+ volatile uint32_t TOSCOR0; /* TOSCOR0 */
+ volatile uint32_t TOSCOR1; /* TOSCOR1 */
+ volatile uint32_t TOSCOR2; /* TOSCOR2 */
+ volatile uint32_t TOSCOR3; /* TOSCOR3 */
+ volatile uint32_t TOSCOR4; /* TOSCOR4 */
+ volatile uint32_t TOSCOR5; /* TOSCOR5 */
+ volatile uint8_t dummy7[8]; /* */
+ volatile uint32_t TOSTR; /* TOSTR */
+ volatile uint32_t TOENR; /* TOENR */
+};
+
+
+#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR BSC.CMNCR
+#define BSCCS0BCR BSC.CS0BCR
+#define BSCCS1BCR BSC.CS1BCR
+#define BSCCS2BCR BSC.CS2BCR
+#define BSCCS3BCR BSC.CS3BCR
+#define BSCCS4BCR BSC.CS4BCR
+#define BSCCS5BCR BSC.CS5BCR
+#define BSCCS0WCR BSC.CS0WCR
+#define BSCCS1WCR BSC.CS1WCR
+#define BSCCS2WCR BSC.CS2WCR
+#define BSCCS3WCR BSC.CS3WCR
+#define BSCCS4WCR BSC.CS4WCR
+#define BSCCS5WCR BSC.CS5WCR
+#define BSCSDCR BSC.SDCR
+#define BSCRTCSR BSC.RTCSR
+#define BSCRTCNT BSC.RTCNT
+#define BSCRTCOR BSC.RTCOR
+#define BSCTOSCOR0 BSC.TOSCOR0
+#define BSCTOSCOR1 BSC.TOSCOR1
+#define BSCTOSCOR2 BSC.TOSCOR2
+#define BSCTOSCOR3 BSC.TOSCOR3
+#define BSCTOSCOR4 BSC.TOSCOR4
+#define BSCTOSCOR5 BSC.TOSCOR5
+#define BSCTOSTR BSC.TOSTR
+#define BSCTOENR BSC.TOENR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h
new file mode 100644
index 000000000..535b18bed
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h
@@ -0,0 +1,269 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ceu_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CEU_IODEFINE_H
+#define CEU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ceu
+{ /* CEU */
+/* start of struct st_ceu_n */
+ volatile uint32_t CAPSR; /* CAPSR */
+ volatile uint32_t CAPCR; /* CAPCR */
+ volatile uint32_t CAMCR; /* CAMCR */
+ volatile uint32_t CMCYR; /* CMCYR */
+ volatile uint32_t CAMOR_A; /* CAMOR_A */
+ volatile uint32_t CAPWR_A; /* CAPWR_A */
+ volatile uint32_t CAIFR; /* CAIFR */
+ volatile uint8_t dummy305[12]; /* */
+ volatile uint32_t CRCNTR; /* CRCNTR */
+ volatile uint32_t CRCMPR; /* CRCMPR */
+ volatile uint32_t CFLCR_A; /* CFLCR_A */
+ volatile uint32_t CFSZR_A; /* CFSZR_A */
+ volatile uint32_t CDWDR_A; /* CDWDR_A */
+ volatile uint32_t CDAYR_A; /* CDAYR_A */
+ volatile uint32_t CDACR_A; /* CDACR_A */
+ volatile uint32_t CDBYR_A; /* CDBYR_A */
+ volatile uint32_t CDBCR_A; /* CDBCR_A */
+ volatile uint32_t CBDSR_A; /* CBDSR_A */
+ volatile uint8_t dummy306[12]; /* */
+ volatile uint32_t CFWCR; /* CFWCR */
+ volatile uint32_t CLFCR_A; /* CLFCR_A */
+ volatile uint32_t CDOCR_A; /* CDOCR_A */
+ volatile uint8_t dummy307[8]; /* */
+ volatile uint32_t CEIER; /* CEIER */
+ volatile uint32_t CETCR; /* CETCR */
+ volatile uint8_t dummy308[4]; /* */
+ volatile uint32_t CSTSR; /* CSTSR */
+ volatile uint8_t dummy309[4]; /* */
+ volatile uint32_t CDSSR; /* CDSSR */
+ volatile uint8_t dummy310[8]; /* */
+ volatile uint32_t CDAYR2_A; /* CDAYR2_A */
+ volatile uint32_t CDACR2_A; /* CDACR2_A */
+ volatile uint32_t CDBYR2_A; /* CDBYR2_A */
+ volatile uint32_t CDBCR2_A; /* CDBCR2_A */
+/* end of struct st_ceu_n */
+ volatile uint8_t dummy3110[3936]; /* */
+/* start of struct st_ceu_n */
+ volatile uint8_t dummy3111[4]; /* */
+ volatile uint8_t dummy3112[4]; /* */
+ volatile uint8_t dummy3113[4]; /* */
+ volatile uint8_t dummy3114[4]; /* */
+ volatile uint32_t CAMOR_B; /* CAMOR_B */
+ volatile uint32_t CAPWR_B; /* CAPWR_B */
+ volatile uint8_t dummy3120[4]; /* */
+ volatile uint8_t dummy3121[12]; /* */
+ volatile uint8_t dummy3122[4]; /* */
+ volatile uint8_t dummy3123[4]; /* */
+ volatile uint32_t CFLCR_B; /* CFLCR_B */
+ volatile uint32_t CFSZR_B; /* CFSZR_B */
+ volatile uint32_t CDWDR_B; /* CDWDR_B */
+ volatile uint32_t CDAYR_B; /* CDAYR_B */
+ volatile uint32_t CDACR_B; /* CDACR_B */
+ volatile uint32_t CDBYR_B; /* CDBYR_B */
+ volatile uint32_t CDBCR_B; /* CDBCR_B */
+ volatile uint32_t CBDSR_B; /* CBDSR_B */
+ volatile uint8_t dummy3130[12]; /* */
+ volatile uint8_t dummy3131[4]; /* */
+ volatile uint32_t CLFCR_B; /* CLFCR_B */
+ volatile uint32_t CDOCR_B; /* CDOCR_B */
+ volatile uint8_t dummy3140[8]; /* */
+ volatile uint8_t dummy3141[4]; /* */
+ volatile uint8_t dummy3142[4]; /* */
+ volatile uint8_t dummy3143[4]; /* */
+ volatile uint8_t dummy3144[4]; /* */
+ volatile uint8_t dummy3145[4]; /* */
+ volatile uint8_t dummy3146[4]; /* */
+ volatile uint8_t dummy3147[8]; /* */
+ volatile uint32_t CDAYR2_B; /* CDAYR2_B */
+ volatile uint32_t CDACR2_B; /* CDACR2_B */
+ volatile uint32_t CDBYR2_B; /* CDBYR2_B */
+ volatile uint32_t CDBCR2_B; /* CDBCR2_B */
+/* end of struct st_ceu_n */
+ volatile uint8_t dummy3150[3936]; /* */
+/* start of struct st_ceu_n */
+ volatile uint8_t dummy3151[4]; /* */
+ volatile uint8_t dummy3152[4]; /* */
+ volatile uint8_t dummy3153[4]; /* */
+ volatile uint8_t dummy3154[4]; /* */
+ volatile uint32_t CAMOR_M; /* CAMOR_M */
+ volatile uint32_t CAPWR_M; /* CAPWR_M */
+ volatile uint8_t dummy3160[4]; /* */
+ volatile uint8_t dummy3161[12]; /* */
+ volatile uint8_t dummy3162[4]; /* */
+ volatile uint8_t dummy3163[4]; /* */
+ volatile uint32_t CFLCR_M; /* CFLCR_M */
+ volatile uint32_t CFSZR_M; /* CFSZR_M */
+ volatile uint32_t CDWDR_M; /* CDWDR_M */
+ volatile uint32_t CDAYR_M; /* CDAYR_M */
+ volatile uint32_t CDACR_M; /* CDACR_M */
+ volatile uint32_t CDBYR_M; /* CDBYR_M */
+ volatile uint32_t CDBCR_M; /* CDBCR_M */
+ volatile uint32_t CBDSR_M; /* CBDSR_M */
+ volatile uint8_t dummy3170[12]; /* */
+ volatile uint8_t dummy3171[4]; /* */
+ volatile uint32_t CLFCR_M; /* CLFCR_M */
+ volatile uint32_t CDOCR_M; /* CDOCR_M */
+ volatile uint8_t dummy3180[8]; /* */
+ volatile uint8_t dummy3181[4]; /* */
+ volatile uint8_t dummy3182[4]; /* */
+ volatile uint8_t dummy3183[4]; /* */
+ volatile uint8_t dummy3184[4]; /* */
+ volatile uint8_t dummy3185[4]; /* */
+ volatile uint8_t dummy3186[4]; /* */
+ volatile uint8_t dummy3187[8]; /* */
+ volatile uint32_t CDAYR2_M; /* CDAYR2_M */
+ volatile uint32_t CDACR2_M; /* CDACR2_M */
+ volatile uint32_t CDBYR2_M; /* CDBYR2_M */
+ volatile uint32_t CDBCR2_M; /* CDBCR2_M */
+/* end of struct st_ceu_n */
+};
+
+
+struct st_ceu_n
+{
+ volatile uint32_t not_common1; /* */
+ volatile uint32_t not_common2; /* */
+ volatile uint32_t not_common3; /* */
+ volatile uint32_t not_common4; /* */
+ volatile uint32_t CAMOR; /* CAMOR */
+ volatile uint32_t CAPWR; /* CAPWR */
+ volatile uint32_t not_common5; /* */
+ volatile uint8_t dummy322[12]; /* */
+ volatile uint32_t not_common6; /* */
+ volatile uint32_t not_common7; /* */
+ volatile uint32_t CFLCR; /* CFLCR */
+ volatile uint32_t CFSZR; /* CFSZR */
+ volatile uint32_t CDWDR; /* CDWDR */
+ volatile uint32_t CDAYR; /* CDAYR */
+ volatile uint32_t CDACR; /* CDACR */
+ volatile uint32_t CDBYR; /* CDBYR */
+ volatile uint32_t CDBCR; /* CDBCR */
+ volatile uint32_t CBDSR; /* CBDSR */
+ volatile uint8_t dummy323[12]; /* */
+ volatile uint32_t not_common8; /* */
+ volatile uint32_t CLFCR; /* CLFCR */
+ volatile uint32_t CDOCR; /* CDOCR */
+ volatile uint8_t dummy324[8]; /* */
+ volatile uint32_t not_common9; /* */
+ volatile uint32_t not_common10; /* */
+ volatile uint8_t dummy325[4]; /* */
+ volatile uint32_t not_common11; /* */
+ volatile uint8_t dummy326[4]; /* */
+ volatile uint32_t not_common12; /* */
+ volatile uint8_t dummy327[8]; /* */
+ volatile uint32_t CDAYR2; /* CDAYR2 */
+ volatile uint32_t CDACR2; /* CDACR2 */
+ volatile uint32_t CDBYR2; /* CDBYR2 */
+ volatile uint32_t CDBCR2; /* CDBCR2 */
+};
+
+
+#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
+
+
+/* Start of channnel array defines of CEU */
+
+/* Channnel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT 3
+#define CEUn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ (volatile struct st_ceu_n*)&CEU_A, \
+ (volatile struct st_ceu_n*)&CEU_B, \
+ (volatile struct st_ceu_n*)&CEU_M \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
+#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
+#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
+
+/* End of channnel array defines of CEU */
+
+
+#define CEUCAPSR CEU.CAPSR
+#define CEUCAPCR CEU.CAPCR
+#define CEUCAMCR CEU.CAMCR
+#define CEUCMCYR CEU.CMCYR
+#define CEUCAMOR_A CEU.CAMOR_A
+#define CEUCAPWR_A CEU.CAPWR_A
+#define CEUCAIFR CEU.CAIFR
+#define CEUCRCNTR CEU.CRCNTR
+#define CEUCRCMPR CEU.CRCMPR
+#define CEUCFLCR_A CEU.CFLCR_A
+#define CEUCFSZR_A CEU.CFSZR_A
+#define CEUCDWDR_A CEU.CDWDR_A
+#define CEUCDAYR_A CEU.CDAYR_A
+#define CEUCDACR_A CEU.CDACR_A
+#define CEUCDBYR_A CEU.CDBYR_A
+#define CEUCDBCR_A CEU.CDBCR_A
+#define CEUCBDSR_A CEU.CBDSR_A
+#define CEUCFWCR CEU.CFWCR
+#define CEUCLFCR_A CEU.CLFCR_A
+#define CEUCDOCR_A CEU.CDOCR_A
+#define CEUCEIER CEU.CEIER
+#define CEUCETCR CEU.CETCR
+#define CEUCSTSR CEU.CSTSR
+#define CEUCDSSR CEU.CDSSR
+#define CEUCDAYR2_A CEU.CDAYR2_A
+#define CEUCDACR2_A CEU.CDACR2_A
+#define CEUCDBYR2_A CEU.CDBYR2_A
+#define CEUCDBCR2_A CEU.CDBCR2_A
+#define CEUCAMOR_B CEU.CAMOR_B
+#define CEUCAPWR_B CEU.CAPWR_B
+#define CEUCFLCR_B CEU.CFLCR_B
+#define CEUCFSZR_B CEU.CFSZR_B
+#define CEUCDWDR_B CEU.CDWDR_B
+#define CEUCDAYR_B CEU.CDAYR_B
+#define CEUCDACR_B CEU.CDACR_B
+#define CEUCDBYR_B CEU.CDBYR_B
+#define CEUCDBCR_B CEU.CDBCR_B
+#define CEUCBDSR_B CEU.CBDSR_B
+#define CEUCLFCR_B CEU.CLFCR_B
+#define CEUCDOCR_B CEU.CDOCR_B
+#define CEUCDAYR2_B CEU.CDAYR2_B
+#define CEUCDACR2_B CEU.CDACR2_B
+#define CEUCDBYR2_B CEU.CDBYR2_B
+#define CEUCDBCR2_B CEU.CDBCR2_B
+#define CEUCAMOR_M CEU.CAMOR_M
+#define CEUCAPWR_M CEU.CAPWR_M
+#define CEUCFLCR_M CEU.CFLCR_M
+#define CEUCFSZR_M CEU.CFSZR_M
+#define CEUCDWDR_M CEU.CDWDR_M
+#define CEUCDAYR_M CEU.CDAYR_M
+#define CEUCDACR_M CEU.CDACR_M
+#define CEUCDBYR_M CEU.CDBYR_M
+#define CEUCDBCR_M CEU.CDBCR_M
+#define CEUCBDSR_M CEU.CBDSR_M
+#define CEUCLFCR_M CEU.CLFCR_M
+#define CEUCDOCR_M CEU.CDOCR_M
+#define CEUCDAYR2_M CEU.CDAYR2_M
+#define CEUCDACR2_M CEU.CDACR2_M
+#define CEUCDBYR2_M CEU.CDBYR2_M
+#define CEUCDBCR2_M CEU.CDBCR2_M
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h
new file mode 100644
index 000000000..5fc9890ff
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h
@@ -0,0 +1,239 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CPG_IODEFINE_H
+#define CPG_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_cpg
+{ /* CPG */
+ volatile uint16_t FRQCR; /* FRQCR */
+ volatile uint8_t dummy319[2]; /* */
+ volatile uint16_t FRQCR2; /* FRQCR2 */
+ volatile uint8_t dummy320[2]; /* */
+ volatile uint8_t CPUSTS; /* CPUSTS */
+ volatile uint8_t dummy321[7]; /* */
+ volatile uint8_t STBCR1; /* STBCR1 */
+ volatile uint8_t dummy322[3]; /* */
+ volatile uint8_t STBCR2; /* STBCR2 */
+ volatile uint8_t dummy323[11]; /* */
+ volatile uint8_t STBREQ1; /* STBREQ1 */
+ volatile uint8_t dummy324[3]; /* */
+ volatile uint8_t STBREQ2; /* STBREQ2 */
+ volatile uint8_t dummy325[11]; /* */
+ volatile uint8_t STBACK1; /* STBACK1 */
+ volatile uint8_t dummy326[3]; /* */
+ volatile uint8_t STBACK2; /* STBACK2 */
+ volatile uint8_t dummy327[955]; /* */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR1; /* SYSCR1 */
+ volatile uint8_t dummy328[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR2; /* SYSCR2 */
+ volatile uint8_t dummy329[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR3; /* SYSCR3 */
+ volatile uint8_t dummy3300[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+ volatile uint8_t dummy3301[20]; /* */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR3; /* STBCR3 */
+ volatile uint8_t dummy331[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR4; /* STBCR4 */
+ volatile uint8_t dummy332[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR5; /* STBCR5 */
+ volatile uint8_t dummy333[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR6; /* STBCR6 */
+ volatile uint8_t dummy334[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR7; /* STBCR7 */
+ volatile uint8_t dummy335[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR8; /* STBCR8 */
+ volatile uint8_t dummy336[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR9; /* STBCR9 */
+ volatile uint8_t dummy337[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR10; /* STBCR10 */
+ volatile uint8_t dummy338[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR11; /* STBCR11 */
+ volatile uint8_t dummy339[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR12; /* STBCR12 */
+ volatile uint8_t dummy3400[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+ volatile uint8_t dummy3401[24]; /* */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
+ volatile uint8_t dummy341[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
+ volatile uint8_t dummy342[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
+ volatile uint8_t dummy3430[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t dummy3431[4]; /* */
+ volatile uint8_t STBCR13; /* STBCR13 */
+ volatile uint8_t dummy344[70543]; /* */
+ volatile uint8_t RRAMKP; /* RRAMKP */
+ volatile uint8_t dummy345[1]; /* */
+ volatile uint8_t DSCTR; /* DSCTR */
+ volatile uint8_t dummy346[1]; /* */
+ volatile uint16_t DSSSR; /* DSSSR */
+ volatile uint16_t DSESR; /* DSESR */
+ volatile uint16_t DSFR; /* DSFR */
+ volatile uint8_t dummy347[6]; /* */
+ volatile uint8_t XTALCTR; /* XTALCTR */
+};
+
+
+struct st_cpg_from_syscr1
+{
+ volatile uint8_t SYSCR1; /* SYSCR1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_cpg_from_stbcr3
+{
+ volatile uint8_t STBCR3; /* STBCR3 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_cpg_from_swrstcr1
+{
+ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channnel array defines of CPG */
+
+/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT 10
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+ &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT 3
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channnel array defines of CPG */
+
+
+#define CPGFRQCR CPG.FRQCR
+#define CPGFRQCR2 CPG.FRQCR2
+#define CPGCPUSTS CPG.CPUSTS
+#define CPGSTBCR1 CPG.STBCR1
+#define CPGSTBCR2 CPG.STBCR2
+#define CPGSTBREQ1 CPG.STBREQ1
+#define CPGSTBREQ2 CPG.STBREQ2
+#define CPGSTBACK1 CPG.STBACK1
+#define CPGSTBACK2 CPG.STBACK2
+#define CPGSYSCR1 CPG.SYSCR1
+#define CPGSYSCR2 CPG.SYSCR2
+#define CPGSYSCR3 CPG.SYSCR3
+#define CPGSTBCR3 CPG.STBCR3
+#define CPGSTBCR4 CPG.STBCR4
+#define CPGSTBCR5 CPG.STBCR5
+#define CPGSTBCR6 CPG.STBCR6
+#define CPGSTBCR7 CPG.STBCR7
+#define CPGSTBCR8 CPG.STBCR8
+#define CPGSTBCR9 CPG.STBCR9
+#define CPGSTBCR10 CPG.STBCR10
+#define CPGSTBCR11 CPG.STBCR11
+#define CPGSTBCR12 CPG.STBCR12
+#define CPGSWRSTCR1 CPG.SWRSTCR1
+#define CPGSWRSTCR2 CPG.SWRSTCR2
+#define CPGSWRSTCR3 CPG.SWRSTCR3
+#define CPGSTBCR13 CPG.STBCR13
+#define CPGRRAMKP CPG.RRAMKP
+#define CPGDSCTR CPG.DSCTR
+#define CPGDSSSR CPG.DSSSR
+#define CPGDSESR CPG.DSESR
+#define CPGDSFR CPG.DSFR
+#define CPGXTALCTR CPG.XTALCTR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h
new file mode 100644
index 000000000..8844fa2af
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : disc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DISC_IODEFINE_H
+#define DISC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_disc
+{ /* DISC */
+ volatile uint32_t DOCMCR; /* DOCMCR */
+ volatile uint32_t DOCMSTR; /* DOCMSTR */
+ volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
+ volatile uint32_t DOCMIENR; /* DOCMIENR */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t DOCMPMR; /* DOCMPMR */
+ volatile uint32_t DOCMECRCR; /* DOCMECRCR */
+ volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */
+ volatile uint32_t DOCMSPXR; /* DOCMSPXR */
+ volatile uint32_t DOCMSPYR; /* DOCMSPYR */
+ volatile uint32_t DOCMSZXR; /* DOCMSZXR */
+ volatile uint32_t DOCMSZYR; /* DOCMSZYR */
+ volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
+};
+
+
+#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
+#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channnel array defines of DISC */
+
+/* Channnel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT 2
+#define DISC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DISC0, &DISC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DISC */
+
+
+#define DISC0DOCMCR DISC0.DOCMCR
+#define DISC0DOCMSTR DISC0.DOCMSTR
+#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
+#define DISC0DOCMIENR DISC0.DOCMIENR
+#define DISC0DOCMPMR DISC0.DOCMPMR
+#define DISC0DOCMECRCR DISC0.DOCMECRCR
+#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
+#define DISC0DOCMSPXR DISC0.DOCMSPXR
+#define DISC0DOCMSPYR DISC0.DOCMSPYR
+#define DISC0DOCMSZXR DISC0.DOCMSZXR
+#define DISC0DOCMSZYR DISC0.DOCMSZYR
+#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
+#define DISC1DOCMCR DISC1.DOCMCR
+#define DISC1DOCMSTR DISC1.DOCMSTR
+#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
+#define DISC1DOCMIENR DISC1.DOCMIENR
+#define DISC1DOCMPMR DISC1.DOCMPMR
+#define DISC1DOCMECRCR DISC1.DOCMECRCR
+#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
+#define DISC1DOCMSPXR DISC1.DOCMSPXR
+#define DISC1DOCMSPYR DISC1.DOCMSPYR
+#define DISC1DOCMSZXR DISC1.DOCMSZXR
+#define DISC1DOCMSZYR DISC1.DOCMSZYR
+#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h
new file mode 100644
index 000000000..0faf27fbe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h
@@ -0,0 +1,733 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dmac_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DMAC_IODEFINE_H
+#define DMAC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dmac
+{ /* DMAC */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_0; /* N0SA_0 */
+ volatile uint32_t N0DA_0; /* N0DA_0 */
+ volatile uint32_t N0TB_0; /* N0TB_0 */
+ volatile uint32_t N1SA_0; /* N1SA_0 */
+ volatile uint32_t N1DA_0; /* N1DA_0 */
+ volatile uint32_t N1TB_0; /* N1TB_0 */
+ volatile uint32_t CRSA_0; /* CRSA_0 */
+ volatile uint32_t CRDA_0; /* CRDA_0 */
+ volatile uint32_t CRTB_0; /* CRTB_0 */
+ volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
+ volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
+ volatile uint32_t CHCFG_0; /* CHCFG_0 */
+ volatile uint32_t CHITVL_0; /* CHITVL_0 */
+ volatile uint32_t CHEXT_0; /* CHEXT_0 */
+ volatile uint32_t NXLA_0; /* NXLA_0 */
+ volatile uint32_t CRLA_0; /* CRLA_0 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_1; /* N0SA_1 */
+ volatile uint32_t N0DA_1; /* N0DA_1 */
+ volatile uint32_t N0TB_1; /* N0TB_1 */
+ volatile uint32_t N1SA_1; /* N1SA_1 */
+ volatile uint32_t N1DA_1; /* N1DA_1 */
+ volatile uint32_t N1TB_1; /* N1TB_1 */
+ volatile uint32_t CRSA_1; /* CRSA_1 */
+ volatile uint32_t CRDA_1; /* CRDA_1 */
+ volatile uint32_t CRTB_1; /* CRTB_1 */
+ volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
+ volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
+ volatile uint32_t CHCFG_1; /* CHCFG_1 */
+ volatile uint32_t CHITVL_1; /* CHITVL_1 */
+ volatile uint32_t CHEXT_1; /* CHEXT_1 */
+ volatile uint32_t NXLA_1; /* NXLA_1 */
+ volatile uint32_t CRLA_1; /* CRLA_1 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_2; /* N0SA_2 */
+ volatile uint32_t N0DA_2; /* N0DA_2 */
+ volatile uint32_t N0TB_2; /* N0TB_2 */
+ volatile uint32_t N1SA_2; /* N1SA_2 */
+ volatile uint32_t N1DA_2; /* N1DA_2 */
+ volatile uint32_t N1TB_2; /* N1TB_2 */
+ volatile uint32_t CRSA_2; /* CRSA_2 */
+ volatile uint32_t CRDA_2; /* CRDA_2 */
+ volatile uint32_t CRTB_2; /* CRTB_2 */
+ volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
+ volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
+ volatile uint32_t CHCFG_2; /* CHCFG_2 */
+ volatile uint32_t CHITVL_2; /* CHITVL_2 */
+ volatile uint32_t CHEXT_2; /* CHEXT_2 */
+ volatile uint32_t NXLA_2; /* NXLA_2 */
+ volatile uint32_t CRLA_2; /* CRLA_2 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_3; /* N0SA_3 */
+ volatile uint32_t N0DA_3; /* N0DA_3 */
+ volatile uint32_t N0TB_3; /* N0TB_3 */
+ volatile uint32_t N1SA_3; /* N1SA_3 */
+ volatile uint32_t N1DA_3; /* N1DA_3 */
+ volatile uint32_t N1TB_3; /* N1TB_3 */
+ volatile uint32_t CRSA_3; /* CRSA_3 */
+ volatile uint32_t CRDA_3; /* CRDA_3 */
+ volatile uint32_t CRTB_3; /* CRTB_3 */
+ volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
+ volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
+ volatile uint32_t CHCFG_3; /* CHCFG_3 */
+ volatile uint32_t CHITVL_3; /* CHITVL_3 */
+ volatile uint32_t CHEXT_3; /* CHEXT_3 */
+ volatile uint32_t NXLA_3; /* NXLA_3 */
+ volatile uint32_t CRLA_3; /* CRLA_3 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_4; /* N0SA_4 */
+ volatile uint32_t N0DA_4; /* N0DA_4 */
+ volatile uint32_t N0TB_4; /* N0TB_4 */
+ volatile uint32_t N1SA_4; /* N1SA_4 */
+ volatile uint32_t N1DA_4; /* N1DA_4 */
+ volatile uint32_t N1TB_4; /* N1TB_4 */
+ volatile uint32_t CRSA_4; /* CRSA_4 */
+ volatile uint32_t CRDA_4; /* CRDA_4 */
+ volatile uint32_t CRTB_4; /* CRTB_4 */
+ volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
+ volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
+ volatile uint32_t CHCFG_4; /* CHCFG_4 */
+ volatile uint32_t CHITVL_4; /* CHITVL_4 */
+ volatile uint32_t CHEXT_4; /* CHEXT_4 */
+ volatile uint32_t NXLA_4; /* NXLA_4 */
+ volatile uint32_t CRLA_4; /* CRLA_4 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_5; /* N0SA_5 */
+ volatile uint32_t N0DA_5; /* N0DA_5 */
+ volatile uint32_t N0TB_5; /* N0TB_5 */
+ volatile uint32_t N1SA_5; /* N1SA_5 */
+ volatile uint32_t N1DA_5; /* N1DA_5 */
+ volatile uint32_t N1TB_5; /* N1TB_5 */
+ volatile uint32_t CRSA_5; /* CRSA_5 */
+ volatile uint32_t CRDA_5; /* CRDA_5 */
+ volatile uint32_t CRTB_5; /* CRTB_5 */
+ volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
+ volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
+ volatile uint32_t CHCFG_5; /* CHCFG_5 */
+ volatile uint32_t CHITVL_5; /* CHITVL_5 */
+ volatile uint32_t CHEXT_5; /* CHEXT_5 */
+ volatile uint32_t NXLA_5; /* NXLA_5 */
+ volatile uint32_t CRLA_5; /* CRLA_5 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_6; /* N0SA_6 */
+ volatile uint32_t N0DA_6; /* N0DA_6 */
+ volatile uint32_t N0TB_6; /* N0TB_6 */
+ volatile uint32_t N1SA_6; /* N1SA_6 */
+ volatile uint32_t N1DA_6; /* N1DA_6 */
+ volatile uint32_t N1TB_6; /* N1TB_6 */
+ volatile uint32_t CRSA_6; /* CRSA_6 */
+ volatile uint32_t CRDA_6; /* CRDA_6 */
+ volatile uint32_t CRTB_6; /* CRTB_6 */
+ volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
+ volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
+ volatile uint32_t CHCFG_6; /* CHCFG_6 */
+ volatile uint32_t CHITVL_6; /* CHITVL_6 */
+ volatile uint32_t CHEXT_6; /* CHEXT_6 */
+ volatile uint32_t NXLA_6; /* NXLA_6 */
+ volatile uint32_t CRLA_6; /* CRLA_6 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_7; /* N0SA_7 */
+ volatile uint32_t N0DA_7; /* N0DA_7 */
+ volatile uint32_t N0TB_7; /* N0TB_7 */
+ volatile uint32_t N1SA_7; /* N1SA_7 */
+ volatile uint32_t N1DA_7; /* N1DA_7 */
+ volatile uint32_t N1TB_7; /* N1TB_7 */
+ volatile uint32_t CRSA_7; /* CRSA_7 */
+ volatile uint32_t CRDA_7; /* CRDA_7 */
+ volatile uint32_t CRTB_7; /* CRTB_7 */
+ volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
+ volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
+ volatile uint32_t CHCFG_7; /* CHCFG_7 */
+ volatile uint32_t CHITVL_7; /* CHITVL_7 */
+ volatile uint32_t CHEXT_7; /* CHEXT_7 */
+ volatile uint32_t NXLA_7; /* NXLA_7 */
+ volatile uint32_t CRLA_7; /* CRLA_7 */
+/* end of struct st_dmac_n */
+ volatile uint8_t dummy187[256]; /* */
+/* start of struct st_dmaccommon_n */
+ volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
+ volatile uint8_t dummy188[12]; /* */
+ volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
+ volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
+ volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
+ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
+ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
+/* end of struct st_dmaccommon_n */
+ volatile uint8_t dummy189[220]; /* */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_8; /* N0SA_8 */
+ volatile uint32_t N0DA_8; /* N0DA_8 */
+ volatile uint32_t N0TB_8; /* N0TB_8 */
+ volatile uint32_t N1SA_8; /* N1SA_8 */
+ volatile uint32_t N1DA_8; /* N1DA_8 */
+ volatile uint32_t N1TB_8; /* N1TB_8 */
+ volatile uint32_t CRSA_8; /* CRSA_8 */
+ volatile uint32_t CRDA_8; /* CRDA_8 */
+ volatile uint32_t CRTB_8; /* CRTB_8 */
+ volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
+ volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
+ volatile uint32_t CHCFG_8; /* CHCFG_8 */
+ volatile uint32_t CHITVL_8; /* CHITVL_8 */
+ volatile uint32_t CHEXT_8; /* CHEXT_8 */
+ volatile uint32_t NXLA_8; /* NXLA_8 */
+ volatile uint32_t CRLA_8; /* CRLA_8 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_9; /* N0SA_9 */
+ volatile uint32_t N0DA_9; /* N0DA_9 */
+ volatile uint32_t N0TB_9; /* N0TB_9 */
+ volatile uint32_t N1SA_9; /* N1SA_9 */
+ volatile uint32_t N1DA_9; /* N1DA_9 */
+ volatile uint32_t N1TB_9; /* N1TB_9 */
+ volatile uint32_t CRSA_9; /* CRSA_9 */
+ volatile uint32_t CRDA_9; /* CRDA_9 */
+ volatile uint32_t CRTB_9; /* CRTB_9 */
+ volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
+ volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
+ volatile uint32_t CHCFG_9; /* CHCFG_9 */
+ volatile uint32_t CHITVL_9; /* CHITVL_9 */
+ volatile uint32_t CHEXT_9; /* CHEXT_9 */
+ volatile uint32_t NXLA_9; /* NXLA_9 */
+ volatile uint32_t CRLA_9; /* CRLA_9 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_10; /* N0SA_10 */
+ volatile uint32_t N0DA_10; /* N0DA_10 */
+ volatile uint32_t N0TB_10; /* N0TB_10 */
+ volatile uint32_t N1SA_10; /* N1SA_10 */
+ volatile uint32_t N1DA_10; /* N1DA_10 */
+ volatile uint32_t N1TB_10; /* N1TB_10 */
+ volatile uint32_t CRSA_10; /* CRSA_10 */
+ volatile uint32_t CRDA_10; /* CRDA_10 */
+ volatile uint32_t CRTB_10; /* CRTB_10 */
+ volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
+ volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
+ volatile uint32_t CHCFG_10; /* CHCFG_10 */
+ volatile uint32_t CHITVL_10; /* CHITVL_10 */
+ volatile uint32_t CHEXT_10; /* CHEXT_10 */
+ volatile uint32_t NXLA_10; /* NXLA_10 */
+ volatile uint32_t CRLA_10; /* CRLA_10 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_11; /* N0SA_11 */
+ volatile uint32_t N0DA_11; /* N0DA_11 */
+ volatile uint32_t N0TB_11; /* N0TB_11 */
+ volatile uint32_t N1SA_11; /* N1SA_11 */
+ volatile uint32_t N1DA_11; /* N1DA_11 */
+ volatile uint32_t N1TB_11; /* N1TB_11 */
+ volatile uint32_t CRSA_11; /* CRSA_11 */
+ volatile uint32_t CRDA_11; /* CRDA_11 */
+ volatile uint32_t CRTB_11; /* CRTB_11 */
+ volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
+ volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
+ volatile uint32_t CHCFG_11; /* CHCFG_11 */
+ volatile uint32_t CHITVL_11; /* CHITVL_11 */
+ volatile uint32_t CHEXT_11; /* CHEXT_11 */
+ volatile uint32_t NXLA_11; /* NXLA_11 */
+ volatile uint32_t CRLA_11; /* CRLA_11 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_12; /* N0SA_12 */
+ volatile uint32_t N0DA_12; /* N0DA_12 */
+ volatile uint32_t N0TB_12; /* N0TB_12 */
+ volatile uint32_t N1SA_12; /* N1SA_12 */
+ volatile uint32_t N1DA_12; /* N1DA_12 */
+ volatile uint32_t N1TB_12; /* N1TB_12 */
+ volatile uint32_t CRSA_12; /* CRSA_12 */
+ volatile uint32_t CRDA_12; /* CRDA_12 */
+ volatile uint32_t CRTB_12; /* CRTB_12 */
+ volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
+ volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
+ volatile uint32_t CHCFG_12; /* CHCFG_12 */
+ volatile uint32_t CHITVL_12; /* CHITVL_12 */
+ volatile uint32_t CHEXT_12; /* CHEXT_12 */
+ volatile uint32_t NXLA_12; /* NXLA_12 */
+ volatile uint32_t CRLA_12; /* CRLA_12 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_13; /* N0SA_13 */
+ volatile uint32_t N0DA_13; /* N0DA_13 */
+ volatile uint32_t N0TB_13; /* N0TB_13 */
+ volatile uint32_t N1SA_13; /* N1SA_13 */
+ volatile uint32_t N1DA_13; /* N1DA_13 */
+ volatile uint32_t N1TB_13; /* N1TB_13 */
+ volatile uint32_t CRSA_13; /* CRSA_13 */
+ volatile uint32_t CRDA_13; /* CRDA_13 */
+ volatile uint32_t CRTB_13; /* CRTB_13 */
+ volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
+ volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
+ volatile uint32_t CHCFG_13; /* CHCFG_13 */
+ volatile uint32_t CHITVL_13; /* CHITVL_13 */
+ volatile uint32_t CHEXT_13; /* CHEXT_13 */
+ volatile uint32_t NXLA_13; /* NXLA_13 */
+ volatile uint32_t CRLA_13; /* CRLA_13 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_14; /* N0SA_14 */
+ volatile uint32_t N0DA_14; /* N0DA_14 */
+ volatile uint32_t N0TB_14; /* N0TB_14 */
+ volatile uint32_t N1SA_14; /* N1SA_14 */
+ volatile uint32_t N1DA_14; /* N1DA_14 */
+ volatile uint32_t N1TB_14; /* N1TB_14 */
+ volatile uint32_t CRSA_14; /* CRSA_14 */
+ volatile uint32_t CRDA_14; /* CRDA_14 */
+ volatile uint32_t CRTB_14; /* CRTB_14 */
+ volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
+ volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
+ volatile uint32_t CHCFG_14; /* CHCFG_14 */
+ volatile uint32_t CHITVL_14; /* CHITVL_14 */
+ volatile uint32_t CHEXT_14; /* CHEXT_14 */
+ volatile uint32_t NXLA_14; /* NXLA_14 */
+ volatile uint32_t CRLA_14; /* CRLA_14 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_15; /* N0SA_15 */
+ volatile uint32_t N0DA_15; /* N0DA_15 */
+ volatile uint32_t N0TB_15; /* N0TB_15 */
+ volatile uint32_t N1SA_15; /* N1SA_15 */
+ volatile uint32_t N1DA_15; /* N1DA_15 */
+ volatile uint32_t N1TB_15; /* N1TB_15 */
+ volatile uint32_t CRSA_15; /* CRSA_15 */
+ volatile uint32_t CRDA_15; /* CRDA_15 */
+ volatile uint32_t CRTB_15; /* CRTB_15 */
+ volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
+ volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
+ volatile uint32_t CHCFG_15; /* CHCFG_15 */
+ volatile uint32_t CHITVL_15; /* CHITVL_15 */
+ volatile uint32_t CHEXT_15; /* CHEXT_15 */
+ volatile uint32_t NXLA_15; /* NXLA_15 */
+ volatile uint32_t CRLA_15; /* CRLA_15 */
+/* end of struct st_dmac_n */
+ volatile uint8_t dummy190[256]; /* */
+/* start of struct st_dmaccommon_n */
+ volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
+ volatile uint8_t dummy191[12]; /* */
+ volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
+ volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
+ volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
+ volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
+ volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
+/* end of struct st_dmaccommon_n */
+ volatile uint8_t dummy192[350095580]; /* */
+ volatile uint32_t DMARS0; /* DMARS0 */
+ volatile uint32_t DMARS1; /* DMARS1 */
+ volatile uint32_t DMARS2; /* DMARS2 */
+ volatile uint32_t DMARS3; /* DMARS3 */
+ volatile uint32_t DMARS4; /* DMARS4 */
+ volatile uint32_t DMARS5; /* DMARS5 */
+ volatile uint32_t DMARS6; /* DMARS6 */
+ volatile uint32_t DMARS7; /* DMARS7 */
+};
+
+
+struct st_dmaccommon_n
+{
+ volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
+ volatile uint8_t dummy1[12]; /* */
+ volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
+ volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
+ volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
+ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
+ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
+};
+
+
+struct st_dmac_n
+{
+ volatile uint32_t N0SA_n; /* N0SA_n */
+ volatile uint32_t N0DA_n; /* N0DA_n */
+ volatile uint32_t N0TB_n; /* N0TB_n */
+ volatile uint32_t N1SA_n; /* N1SA_n */
+ volatile uint32_t N1DA_n; /* N1DA_n */
+ volatile uint32_t N1TB_n; /* N1TB_n */
+ volatile uint32_t CRSA_n; /* CRSA_n */
+ volatile uint32_t CRDA_n; /* CRDA_n */
+ volatile uint32_t CRTB_n; /* CRTB_n */
+ volatile uint32_t CHSTAT_n; /* CHSTAT_n */
+ volatile uint32_t CHCTRL_n; /* CHCTRL_n */
+ volatile uint32_t CHCFG_n; /* CHCFG_n */
+ volatile uint32_t CHITVL_n; /* CHITVL_n */
+ volatile uint32_t CHEXT_n; /* CHEXT_n */
+ volatile uint32_t NXLA_n; /* NXLA_n */
+ volatile uint32_t CRLA_n; /* CRLA_n */
+};
+
+
+#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
+
+
+/* Start of channnel array defines of DMAC */
+
+/* Channnel array defines of DMACn */
+/*(Sample) value = DMACn[ channel ]->N0SA_n; */
+#define DMACn_COUNT 16
+#define DMACn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
+ &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
+#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
+#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
+#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
+#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
+#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
+#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
+#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
+#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
+#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
+#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
+#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
+#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
+#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
+#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
+#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
+
+
+/* Channnel array defines of DMACnn */
+/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
+#define DMACnn_COUNT 2
+#define DMACnn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC07, &DMAC815 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
+#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
+
+
+/* Channnel array defines of DMACmm */
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
+struct st_dmars_mm
+{
+ uint32_t DMARS; /* DMARS */
+};
+#define DMACmm_COUNT 8
+#define DMACmm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
+#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
+#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
+#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
+#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
+#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
+#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
+#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
+
+/* End of channnel array defines of DMAC */
+
+
+#define DMACN0SA_0 DMAC.N0SA_0
+#define DMACN0DA_0 DMAC.N0DA_0
+#define DMACN0TB_0 DMAC.N0TB_0
+#define DMACN1SA_0 DMAC.N1SA_0
+#define DMACN1DA_0 DMAC.N1DA_0
+#define DMACN1TB_0 DMAC.N1TB_0
+#define DMACCRSA_0 DMAC.CRSA_0
+#define DMACCRDA_0 DMAC.CRDA_0
+#define DMACCRTB_0 DMAC.CRTB_0
+#define DMACCHSTAT_0 DMAC.CHSTAT_0
+#define DMACCHCTRL_0 DMAC.CHCTRL_0
+#define DMACCHCFG_0 DMAC.CHCFG_0
+#define DMACCHITVL_0 DMAC.CHITVL_0
+#define DMACCHEXT_0 DMAC.CHEXT_0
+#define DMACNXLA_0 DMAC.NXLA_0
+#define DMACCRLA_0 DMAC.CRLA_0
+#define DMACN0SA_1 DMAC.N0SA_1
+#define DMACN0DA_1 DMAC.N0DA_1
+#define DMACN0TB_1 DMAC.N0TB_1
+#define DMACN1SA_1 DMAC.N1SA_1
+#define DMACN1DA_1 DMAC.N1DA_1
+#define DMACN1TB_1 DMAC.N1TB_1
+#define DMACCRSA_1 DMAC.CRSA_1
+#define DMACCRDA_1 DMAC.CRDA_1
+#define DMACCRTB_1 DMAC.CRTB_1
+#define DMACCHSTAT_1 DMAC.CHSTAT_1
+#define DMACCHCTRL_1 DMAC.CHCTRL_1
+#define DMACCHCFG_1 DMAC.CHCFG_1
+#define DMACCHITVL_1 DMAC.CHITVL_1
+#define DMACCHEXT_1 DMAC.CHEXT_1
+#define DMACNXLA_1 DMAC.NXLA_1
+#define DMACCRLA_1 DMAC.CRLA_1
+#define DMACN0SA_2 DMAC.N0SA_2
+#define DMACN0DA_2 DMAC.N0DA_2
+#define DMACN0TB_2 DMAC.N0TB_2
+#define DMACN1SA_2 DMAC.N1SA_2
+#define DMACN1DA_2 DMAC.N1DA_2
+#define DMACN1TB_2 DMAC.N1TB_2
+#define DMACCRSA_2 DMAC.CRSA_2
+#define DMACCRDA_2 DMAC.CRDA_2
+#define DMACCRTB_2 DMAC.CRTB_2
+#define DMACCHSTAT_2 DMAC.CHSTAT_2
+#define DMACCHCTRL_2 DMAC.CHCTRL_2
+#define DMACCHCFG_2 DMAC.CHCFG_2
+#define DMACCHITVL_2 DMAC.CHITVL_2
+#define DMACCHEXT_2 DMAC.CHEXT_2
+#define DMACNXLA_2 DMAC.NXLA_2
+#define DMACCRLA_2 DMAC.CRLA_2
+#define DMACN0SA_3 DMAC.N0SA_3
+#define DMACN0DA_3 DMAC.N0DA_3
+#define DMACN0TB_3 DMAC.N0TB_3
+#define DMACN1SA_3 DMAC.N1SA_3
+#define DMACN1DA_3 DMAC.N1DA_3
+#define DMACN1TB_3 DMAC.N1TB_3
+#define DMACCRSA_3 DMAC.CRSA_3
+#define DMACCRDA_3 DMAC.CRDA_3
+#define DMACCRTB_3 DMAC.CRTB_3
+#define DMACCHSTAT_3 DMAC.CHSTAT_3
+#define DMACCHCTRL_3 DMAC.CHCTRL_3
+#define DMACCHCFG_3 DMAC.CHCFG_3
+#define DMACCHITVL_3 DMAC.CHITVL_3
+#define DMACCHEXT_3 DMAC.CHEXT_3
+#define DMACNXLA_3 DMAC.NXLA_3
+#define DMACCRLA_3 DMAC.CRLA_3
+#define DMACN0SA_4 DMAC.N0SA_4
+#define DMACN0DA_4 DMAC.N0DA_4
+#define DMACN0TB_4 DMAC.N0TB_4
+#define DMACN1SA_4 DMAC.N1SA_4
+#define DMACN1DA_4 DMAC.N1DA_4
+#define DMACN1TB_4 DMAC.N1TB_4
+#define DMACCRSA_4 DMAC.CRSA_4
+#define DMACCRDA_4 DMAC.CRDA_4
+#define DMACCRTB_4 DMAC.CRTB_4
+#define DMACCHSTAT_4 DMAC.CHSTAT_4
+#define DMACCHCTRL_4 DMAC.CHCTRL_4
+#define DMACCHCFG_4 DMAC.CHCFG_4
+#define DMACCHITVL_4 DMAC.CHITVL_4
+#define DMACCHEXT_4 DMAC.CHEXT_4
+#define DMACNXLA_4 DMAC.NXLA_4
+#define DMACCRLA_4 DMAC.CRLA_4
+#define DMACN0SA_5 DMAC.N0SA_5
+#define DMACN0DA_5 DMAC.N0DA_5
+#define DMACN0TB_5 DMAC.N0TB_5
+#define DMACN1SA_5 DMAC.N1SA_5
+#define DMACN1DA_5 DMAC.N1DA_5
+#define DMACN1TB_5 DMAC.N1TB_5
+#define DMACCRSA_5 DMAC.CRSA_5
+#define DMACCRDA_5 DMAC.CRDA_5
+#define DMACCRTB_5 DMAC.CRTB_5
+#define DMACCHSTAT_5 DMAC.CHSTAT_5
+#define DMACCHCTRL_5 DMAC.CHCTRL_5
+#define DMACCHCFG_5 DMAC.CHCFG_5
+#define DMACCHITVL_5 DMAC.CHITVL_5
+#define DMACCHEXT_5 DMAC.CHEXT_5
+#define DMACNXLA_5 DMAC.NXLA_5
+#define DMACCRLA_5 DMAC.CRLA_5
+#define DMACN0SA_6 DMAC.N0SA_6
+#define DMACN0DA_6 DMAC.N0DA_6
+#define DMACN0TB_6 DMAC.N0TB_6
+#define DMACN1SA_6 DMAC.N1SA_6
+#define DMACN1DA_6 DMAC.N1DA_6
+#define DMACN1TB_6 DMAC.N1TB_6
+#define DMACCRSA_6 DMAC.CRSA_6
+#define DMACCRDA_6 DMAC.CRDA_6
+#define DMACCRTB_6 DMAC.CRTB_6
+#define DMACCHSTAT_6 DMAC.CHSTAT_6
+#define DMACCHCTRL_6 DMAC.CHCTRL_6
+#define DMACCHCFG_6 DMAC.CHCFG_6
+#define DMACCHITVL_6 DMAC.CHITVL_6
+#define DMACCHEXT_6 DMAC.CHEXT_6
+#define DMACNXLA_6 DMAC.NXLA_6
+#define DMACCRLA_6 DMAC.CRLA_6
+#define DMACN0SA_7 DMAC.N0SA_7
+#define DMACN0DA_7 DMAC.N0DA_7
+#define DMACN0TB_7 DMAC.N0TB_7
+#define DMACN1SA_7 DMAC.N1SA_7
+#define DMACN1DA_7 DMAC.N1DA_7
+#define DMACN1TB_7 DMAC.N1TB_7
+#define DMACCRSA_7 DMAC.CRSA_7
+#define DMACCRDA_7 DMAC.CRDA_7
+#define DMACCRTB_7 DMAC.CRTB_7
+#define DMACCHSTAT_7 DMAC.CHSTAT_7
+#define DMACCHCTRL_7 DMAC.CHCTRL_7
+#define DMACCHCFG_7 DMAC.CHCFG_7
+#define DMACCHITVL_7 DMAC.CHITVL_7
+#define DMACCHEXT_7 DMAC.CHEXT_7
+#define DMACNXLA_7 DMAC.NXLA_7
+#define DMACCRLA_7 DMAC.CRLA_7
+#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
+#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
+#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
+#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
+#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
+#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
+#define DMACN0SA_8 DMAC.N0SA_8
+#define DMACN0DA_8 DMAC.N0DA_8
+#define DMACN0TB_8 DMAC.N0TB_8
+#define DMACN1SA_8 DMAC.N1SA_8
+#define DMACN1DA_8 DMAC.N1DA_8
+#define DMACN1TB_8 DMAC.N1TB_8
+#define DMACCRSA_8 DMAC.CRSA_8
+#define DMACCRDA_8 DMAC.CRDA_8
+#define DMACCRTB_8 DMAC.CRTB_8
+#define DMACCHSTAT_8 DMAC.CHSTAT_8
+#define DMACCHCTRL_8 DMAC.CHCTRL_8
+#define DMACCHCFG_8 DMAC.CHCFG_8
+#define DMACCHITVL_8 DMAC.CHITVL_8
+#define DMACCHEXT_8 DMAC.CHEXT_8
+#define DMACNXLA_8 DMAC.NXLA_8
+#define DMACCRLA_8 DMAC.CRLA_8
+#define DMACN0SA_9 DMAC.N0SA_9
+#define DMACN0DA_9 DMAC.N0DA_9
+#define DMACN0TB_9 DMAC.N0TB_9
+#define DMACN1SA_9 DMAC.N1SA_9
+#define DMACN1DA_9 DMAC.N1DA_9
+#define DMACN1TB_9 DMAC.N1TB_9
+#define DMACCRSA_9 DMAC.CRSA_9
+#define DMACCRDA_9 DMAC.CRDA_9
+#define DMACCRTB_9 DMAC.CRTB_9
+#define DMACCHSTAT_9 DMAC.CHSTAT_9
+#define DMACCHCTRL_9 DMAC.CHCTRL_9
+#define DMACCHCFG_9 DMAC.CHCFG_9
+#define DMACCHITVL_9 DMAC.CHITVL_9
+#define DMACCHEXT_9 DMAC.CHEXT_9
+#define DMACNXLA_9 DMAC.NXLA_9
+#define DMACCRLA_9 DMAC.CRLA_9
+#define DMACN0SA_10 DMAC.N0SA_10
+#define DMACN0DA_10 DMAC.N0DA_10
+#define DMACN0TB_10 DMAC.N0TB_10
+#define DMACN1SA_10 DMAC.N1SA_10
+#define DMACN1DA_10 DMAC.N1DA_10
+#define DMACN1TB_10 DMAC.N1TB_10
+#define DMACCRSA_10 DMAC.CRSA_10
+#define DMACCRDA_10 DMAC.CRDA_10
+#define DMACCRTB_10 DMAC.CRTB_10
+#define DMACCHSTAT_10 DMAC.CHSTAT_10
+#define DMACCHCTRL_10 DMAC.CHCTRL_10
+#define DMACCHCFG_10 DMAC.CHCFG_10
+#define DMACCHITVL_10 DMAC.CHITVL_10
+#define DMACCHEXT_10 DMAC.CHEXT_10
+#define DMACNXLA_10 DMAC.NXLA_10
+#define DMACCRLA_10 DMAC.CRLA_10
+#define DMACN0SA_11 DMAC.N0SA_11
+#define DMACN0DA_11 DMAC.N0DA_11
+#define DMACN0TB_11 DMAC.N0TB_11
+#define DMACN1SA_11 DMAC.N1SA_11
+#define DMACN1DA_11 DMAC.N1DA_11
+#define DMACN1TB_11 DMAC.N1TB_11
+#define DMACCRSA_11 DMAC.CRSA_11
+#define DMACCRDA_11 DMAC.CRDA_11
+#define DMACCRTB_11 DMAC.CRTB_11
+#define DMACCHSTAT_11 DMAC.CHSTAT_11
+#define DMACCHCTRL_11 DMAC.CHCTRL_11
+#define DMACCHCFG_11 DMAC.CHCFG_11
+#define DMACCHITVL_11 DMAC.CHITVL_11
+#define DMACCHEXT_11 DMAC.CHEXT_11
+#define DMACNXLA_11 DMAC.NXLA_11
+#define DMACCRLA_11 DMAC.CRLA_11
+#define DMACN0SA_12 DMAC.N0SA_12
+#define DMACN0DA_12 DMAC.N0DA_12
+#define DMACN0TB_12 DMAC.N0TB_12
+#define DMACN1SA_12 DMAC.N1SA_12
+#define DMACN1DA_12 DMAC.N1DA_12
+#define DMACN1TB_12 DMAC.N1TB_12
+#define DMACCRSA_12 DMAC.CRSA_12
+#define DMACCRDA_12 DMAC.CRDA_12
+#define DMACCRTB_12 DMAC.CRTB_12
+#define DMACCHSTAT_12 DMAC.CHSTAT_12
+#define DMACCHCTRL_12 DMAC.CHCTRL_12
+#define DMACCHCFG_12 DMAC.CHCFG_12
+#define DMACCHITVL_12 DMAC.CHITVL_12
+#define DMACCHEXT_12 DMAC.CHEXT_12
+#define DMACNXLA_12 DMAC.NXLA_12
+#define DMACCRLA_12 DMAC.CRLA_12
+#define DMACN0SA_13 DMAC.N0SA_13
+#define DMACN0DA_13 DMAC.N0DA_13
+#define DMACN0TB_13 DMAC.N0TB_13
+#define DMACN1SA_13 DMAC.N1SA_13
+#define DMACN1DA_13 DMAC.N1DA_13
+#define DMACN1TB_13 DMAC.N1TB_13
+#define DMACCRSA_13 DMAC.CRSA_13
+#define DMACCRDA_13 DMAC.CRDA_13
+#define DMACCRTB_13 DMAC.CRTB_13
+#define DMACCHSTAT_13 DMAC.CHSTAT_13
+#define DMACCHCTRL_13 DMAC.CHCTRL_13
+#define DMACCHCFG_13 DMAC.CHCFG_13
+#define DMACCHITVL_13 DMAC.CHITVL_13
+#define DMACCHEXT_13 DMAC.CHEXT_13
+#define DMACNXLA_13 DMAC.NXLA_13
+#define DMACCRLA_13 DMAC.CRLA_13
+#define DMACN0SA_14 DMAC.N0SA_14
+#define DMACN0DA_14 DMAC.N0DA_14
+#define DMACN0TB_14 DMAC.N0TB_14
+#define DMACN1SA_14 DMAC.N1SA_14
+#define DMACN1DA_14 DMAC.N1DA_14
+#define DMACN1TB_14 DMAC.N1TB_14
+#define DMACCRSA_14 DMAC.CRSA_14
+#define DMACCRDA_14 DMAC.CRDA_14
+#define DMACCRTB_14 DMAC.CRTB_14
+#define DMACCHSTAT_14 DMAC.CHSTAT_14
+#define DMACCHCTRL_14 DMAC.CHCTRL_14
+#define DMACCHCFG_14 DMAC.CHCFG_14
+#define DMACCHITVL_14 DMAC.CHITVL_14
+#define DMACCHEXT_14 DMAC.CHEXT_14
+#define DMACNXLA_14 DMAC.NXLA_14
+#define DMACCRLA_14 DMAC.CRLA_14
+#define DMACN0SA_15 DMAC.N0SA_15
+#define DMACN0DA_15 DMAC.N0DA_15
+#define DMACN0TB_15 DMAC.N0TB_15
+#define DMACN1SA_15 DMAC.N1SA_15
+#define DMACN1DA_15 DMAC.N1DA_15
+#define DMACN1TB_15 DMAC.N1TB_15
+#define DMACCRSA_15 DMAC.CRSA_15
+#define DMACCRDA_15 DMAC.CRDA_15
+#define DMACCRTB_15 DMAC.CRTB_15
+#define DMACCHSTAT_15 DMAC.CHSTAT_15
+#define DMACCHCTRL_15 DMAC.CHCTRL_15
+#define DMACCHCFG_15 DMAC.CHCFG_15
+#define DMACCHITVL_15 DMAC.CHITVL_15
+#define DMACCHEXT_15 DMAC.CHEXT_15
+#define DMACNXLA_15 DMAC.NXLA_15
+#define DMACCRLA_15 DMAC.CRLA_15
+#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
+#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
+#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
+#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
+#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
+#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
+#define DMACDMARS0 DMAC.DMARS0
+#define DMACDMARS1 DMAC.DMARS1
+#define DMACDMARS2 DMAC.DMARS2
+#define DMACDMARS3 DMAC.DMARS3
+#define DMACDMARS4 DMAC.DMARS4
+#define DMACDMARS5 DMAC.DMARS5
+#define DMACDMARS6 DMAC.DMARS6
+#define DMACDMARS7 DMAC.DMARS7
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h
new file mode 100644
index 000000000..6c28acb00
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h
@@ -0,0 +1,391 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dvdec_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DVDEC_IODEFINE_H
+#define DVDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dvdec
+{ /* DVDEC */
+ volatile uint16_t ADCCR1; /* ADCCR1 */
+ volatile uint8_t dummy1[4]; /* */
+#define DVDEC_TGCRn_COUNT 3
+ volatile uint16_t TGCR1; /* TGCR1 */
+ volatile uint16_t TGCR2; /* TGCR2 */
+ volatile uint16_t TGCR3; /* TGCR3 */
+ volatile uint8_t dummy2[6]; /* */
+#define DVDEC_SYNSCRn_COUNT 5
+ volatile uint16_t SYNSCR1; /* SYNSCR1 */
+ volatile uint16_t SYNSCR2; /* SYNSCR2 */
+ volatile uint16_t SYNSCR3; /* SYNSCR3 */
+ volatile uint16_t SYNSCR4; /* SYNSCR4 */
+ volatile uint16_t SYNSCR5; /* SYNSCR5 */
+#define DVDEC_HAFCCRn_COUNT 3
+ volatile uint16_t HAFCCR1; /* HAFCCR1 */
+ volatile uint16_t HAFCCR2; /* HAFCCR2 */
+ volatile uint16_t HAFCCR3; /* HAFCCR3 */
+ volatile uint16_t VCDWCR1; /* VCDWCR1 */
+ volatile uint8_t dummy3[4]; /* */
+#define DVDEC_DCPCRn_COUNT 8
+ volatile uint16_t DCPCR1; /* DCPCR1 */
+ volatile uint16_t DCPCR2; /* DCPCR2 */
+ volatile uint16_t DCPCR3; /* DCPCR3 */
+ volatile uint16_t DCPCR4; /* DCPCR4 */
+ volatile uint16_t DCPCR5; /* DCPCR5 */
+ volatile uint16_t DCPCR6; /* DCPCR6 */
+ volatile uint16_t DCPCR7; /* DCPCR7 */
+ volatile uint16_t DCPCR8; /* DCPCR8 */
+ volatile uint16_t NSDCR; /* NSDCR */
+ volatile uint16_t BTLCR; /* BTLCR */
+ volatile uint16_t BTGPCR; /* BTGPCR */
+#define DVDEC_ACCCRn_COUNT 3
+ volatile uint16_t ACCCR1; /* ACCCR1 */
+ volatile uint16_t ACCCR2; /* ACCCR2 */
+ volatile uint16_t ACCCR3; /* ACCCR3 */
+ volatile uint16_t TINTCR; /* TINTCR */
+ volatile uint16_t YCDCR; /* YCDCR */
+#define DVDEC_AGCCRn_COUNT 2
+ volatile uint16_t AGCCR1; /* AGCCR1 */
+ volatile uint16_t AGCCR2; /* AGCCR2 */
+ volatile uint16_t PKLIMITCR; /* PKLIMITCR */
+#define DVDEC_RGORCRn_COUNT 7
+ volatile uint16_t RGORCR1; /* RGORCR1 */
+ volatile uint16_t RGORCR2; /* RGORCR2 */
+ volatile uint16_t RGORCR3; /* RGORCR3 */
+ volatile uint16_t RGORCR4; /* RGORCR4 */
+ volatile uint16_t RGORCR5; /* RGORCR5 */
+ volatile uint16_t RGORCR6; /* RGORCR6 */
+ volatile uint16_t RGORCR7; /* RGORCR7 */
+ volatile uint8_t dummy4[24]; /* */
+ volatile uint16_t AFCPFCR; /* AFCPFCR */
+ volatile uint16_t RUPDCR; /* RUPDCR */
+ volatile uint16_t VSYNCSR; /* VSYNCSR */
+ volatile uint16_t HSYNCSR; /* HSYNCSR */
+#define DVDEC_DCPSRn_COUNT 2
+ volatile uint16_t DCPSR1; /* DCPSR1 */
+ volatile uint16_t DCPSR2; /* DCPSR2 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint16_t NSDSR; /* NSDSR */
+#define DVDEC_CROMASRn_COUNT 2
+ volatile uint16_t CROMASR1; /* CROMASR1 */
+ volatile uint16_t CROMASR2; /* CROMASR2 */
+ volatile uint16_t SYNCSSR; /* SYNCSSR */
+#define DVDEC_AGCCSRn_COUNT 2
+ volatile uint16_t AGCCSR1; /* AGCCSR1 */
+ volatile uint16_t AGCCSR2; /* AGCCSR2 */
+ volatile uint8_t dummy6[108]; /* */
+#define DVDEC_YCSCRn_COUNT 7
+ volatile uint16_t YCSCR3; /* YCSCR3 */
+ volatile uint16_t YCSCR4; /* YCSCR4 */
+ volatile uint16_t YCSCR5; /* YCSCR5 */
+ volatile uint16_t YCSCR6; /* YCSCR6 */
+ volatile uint16_t YCSCR7; /* YCSCR7 */
+ volatile uint16_t YCSCR8; /* YCSCR8 */
+ volatile uint16_t YCSCR9; /* YCSCR9 */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t YCSCR11; /* YCSCR11 */
+ volatile uint16_t YCSCR12; /* YCSCR12 */
+ volatile uint8_t dummy8[104]; /* */
+ volatile uint16_t DCPCR9; /* DCPCR9 */
+ volatile uint8_t dummy9[16]; /* */
+#define DVDEC_YCTWA_Fn_COUNT 9
+ volatile uint16_t YCTWA_F0; /* YCTWA_F0 */
+ volatile uint16_t YCTWA_F1; /* YCTWA_F1 */
+ volatile uint16_t YCTWA_F2; /* YCTWA_F2 */
+ volatile uint16_t YCTWA_F3; /* YCTWA_F3 */
+ volatile uint16_t YCTWA_F4; /* YCTWA_F4 */
+ volatile uint16_t YCTWA_F5; /* YCTWA_F5 */
+ volatile uint16_t YCTWA_F6; /* YCTWA_F6 */
+ volatile uint16_t YCTWA_F7; /* YCTWA_F7 */
+ volatile uint16_t YCTWA_F8; /* YCTWA_F8 */
+#define DVDEC_YCTWB_Fn_COUNT 9
+ volatile uint16_t YCTWB_F0; /* YCTWB_F0 */
+ volatile uint16_t YCTWB_F1; /* YCTWB_F1 */
+ volatile uint16_t YCTWB_F2; /* YCTWB_F2 */
+ volatile uint16_t YCTWB_F3; /* YCTWB_F3 */
+ volatile uint16_t YCTWB_F4; /* YCTWB_F4 */
+ volatile uint16_t YCTWB_F5; /* YCTWB_F5 */
+ volatile uint16_t YCTWB_F6; /* YCTWB_F6 */
+ volatile uint16_t YCTWB_F7; /* YCTWB_F7 */
+ volatile uint16_t YCTWB_F8; /* YCTWB_F8 */
+#define DVDEC_YCTNA_Fn_COUNT 9
+ volatile uint16_t YCTNA_F0; /* YCTNA_F0 */
+ volatile uint16_t YCTNA_F1; /* YCTNA_F1 */
+ volatile uint16_t YCTNA_F2; /* YCTNA_F2 */
+ volatile uint16_t YCTNA_F3; /* YCTNA_F3 */
+ volatile uint16_t YCTNA_F4; /* YCTNA_F4 */
+ volatile uint16_t YCTNA_F5; /* YCTNA_F5 */
+ volatile uint16_t YCTNA_F6; /* YCTNA_F6 */
+ volatile uint16_t YCTNA_F7; /* YCTNA_F7 */
+ volatile uint16_t YCTNA_F8; /* YCTNA_F8 */
+#define DVDEC_YCTNB_Fn_COUNT 9
+ volatile uint16_t YCTNB_F0; /* YCTNB_F0 */
+ volatile uint16_t YCTNB_F1; /* YCTNB_F1 */
+ volatile uint16_t YCTNB_F2; /* YCTNB_F2 */
+ volatile uint16_t YCTNB_F3; /* YCTNB_F3 */
+ volatile uint16_t YCTNB_F4; /* YCTNB_F4 */
+ volatile uint16_t YCTNB_F5; /* YCTNB_F5 */
+ volatile uint16_t YCTNB_F6; /* YCTNB_F6 */
+ volatile uint16_t YCTNB_F7; /* YCTNB_F7 */
+ volatile uint16_t YCTNB_F8; /* YCTNB_F8 */
+ volatile uint8_t dummy10[38]; /* */
+ volatile uint16_t YGAINCR; /* YGAINCR */
+ volatile uint16_t CBGAINCR; /* CBGAINCR */
+ volatile uint16_t CRGAINCR; /* CRGAINCR */
+ volatile uint8_t dummy11[122]; /* */
+ volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */
+ volatile uint16_t PGACR; /* PGACR */
+ volatile uint16_t ADCCR2; /* ADCCR2 */
+};
+
+
+#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channnel array defines of DVDEC */
+
+/* Channnel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT 2
+#define DVDEC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DVDEC0, &DVDEC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DVDEC */
+
+
+#define ADCCR1_1 DVDEC1.ADCCR1
+#define TGCR1_1 DVDEC1.TGCR1
+#define TGCR2_1 DVDEC1.TGCR2
+#define TGCR3_1 DVDEC1.TGCR3
+#define SYNSCR1_1 DVDEC1.SYNSCR1
+#define SYNSCR2_1 DVDEC1.SYNSCR2
+#define SYNSCR3_1 DVDEC1.SYNSCR3
+#define SYNSCR4_1 DVDEC1.SYNSCR4
+#define SYNSCR5_1 DVDEC1.SYNSCR5
+#define HAFCCR1_1 DVDEC1.HAFCCR1
+#define HAFCCR2_1 DVDEC1.HAFCCR2
+#define HAFCCR3_1 DVDEC1.HAFCCR3
+#define VCDWCR1_1 DVDEC1.VCDWCR1
+#define DCPCR1_1 DVDEC1.DCPCR1
+#define DCPCR2_1 DVDEC1.DCPCR2
+#define DCPCR3_1 DVDEC1.DCPCR3
+#define DCPCR4_1 DVDEC1.DCPCR4
+#define DCPCR5_1 DVDEC1.DCPCR5
+#define DCPCR6_1 DVDEC1.DCPCR6
+#define DCPCR7_1 DVDEC1.DCPCR7
+#define DCPCR8_1 DVDEC1.DCPCR8
+#define NSDCR_1 DVDEC1.NSDCR
+#define BTLCR_1 DVDEC1.BTLCR
+#define BTGPCR_1 DVDEC1.BTGPCR
+#define ACCCR1_1 DVDEC1.ACCCR1
+#define ACCCR2_1 DVDEC1.ACCCR2
+#define ACCCR3_1 DVDEC1.ACCCR3
+#define TINTCR_1 DVDEC1.TINTCR
+#define YCDCR_1 DVDEC1.YCDCR
+#define AGCCR1_1 DVDEC1.AGCCR1
+#define AGCCR2_1 DVDEC1.AGCCR2
+#define PKLIMITCR_1 DVDEC1.PKLIMITCR
+#define RGORCR1_1 DVDEC1.RGORCR1
+#define RGORCR2_1 DVDEC1.RGORCR2
+#define RGORCR3_1 DVDEC1.RGORCR3
+#define RGORCR4_1 DVDEC1.RGORCR4
+#define RGORCR5_1 DVDEC1.RGORCR5
+#define RGORCR6_1 DVDEC1.RGORCR6
+#define RGORCR7_1 DVDEC1.RGORCR7
+#define AFCPFCR_1 DVDEC1.AFCPFCR
+#define RUPDCR_1 DVDEC1.RUPDCR
+#define VSYNCSR_1 DVDEC1.VSYNCSR
+#define HSYNCSR_1 DVDEC1.HSYNCSR
+#define DCPSR1_1 DVDEC1.DCPSR1
+#define DCPSR2_1 DVDEC1.DCPSR2
+#define NSDSR_1 DVDEC1.NSDSR
+#define CROMASR1_1 DVDEC1.CROMASR1
+#define CROMASR2_1 DVDEC1.CROMASR2
+#define SYNCSSR_1 DVDEC1.SYNCSSR
+#define AGCCSR1_1 DVDEC1.AGCCSR1
+#define AGCCSR2_1 DVDEC1.AGCCSR2
+#define YCSCR3_1 DVDEC1.YCSCR3
+#define YCSCR4_1 DVDEC1.YCSCR4
+#define YCSCR5_1 DVDEC1.YCSCR5
+#define YCSCR6_1 DVDEC1.YCSCR6
+#define YCSCR7_1 DVDEC1.YCSCR7
+#define YCSCR8_1 DVDEC1.YCSCR8
+#define YCSCR9_1 DVDEC1.YCSCR9
+#define YCSCR11_1 DVDEC1.YCSCR11
+#define YCSCR12_1 DVDEC1.YCSCR12
+#define DCPCR9_1 DVDEC1.DCPCR9
+#define YCTWA_F0_1 DVDEC1.YCTWA_F0
+#define YCTWA_F1_1 DVDEC1.YCTWA_F1
+#define YCTWA_F2_1 DVDEC1.YCTWA_F2
+#define YCTWA_F3_1 DVDEC1.YCTWA_F3
+#define YCTWA_F4_1 DVDEC1.YCTWA_F4
+#define YCTWA_F5_1 DVDEC1.YCTWA_F5
+#define YCTWA_F6_1 DVDEC1.YCTWA_F6
+#define YCTWA_F7_1 DVDEC1.YCTWA_F7
+#define YCTWA_F8_1 DVDEC1.YCTWA_F8
+#define YCTWB_F0_1 DVDEC1.YCTWB_F0
+#define YCTWB_F1_1 DVDEC1.YCTWB_F1
+#define YCTWB_F2_1 DVDEC1.YCTWB_F2
+#define YCTWB_F3_1 DVDEC1.YCTWB_F3
+#define YCTWB_F4_1 DVDEC1.YCTWB_F4
+#define YCTWB_F5_1 DVDEC1.YCTWB_F5
+#define YCTWB_F6_1 DVDEC1.YCTWB_F6
+#define YCTWB_F7_1 DVDEC1.YCTWB_F7
+#define YCTWB_F8_1 DVDEC1.YCTWB_F8
+#define YCTNA_F0_1 DVDEC1.YCTNA_F0
+#define YCTNA_F1_1 DVDEC1.YCTNA_F1
+#define YCTNA_F2_1 DVDEC1.YCTNA_F2
+#define YCTNA_F3_1 DVDEC1.YCTNA_F3
+#define YCTNA_F4_1 DVDEC1.YCTNA_F4
+#define YCTNA_F5_1 DVDEC1.YCTNA_F5
+#define YCTNA_F6_1 DVDEC1.YCTNA_F6
+#define YCTNA_F7_1 DVDEC1.YCTNA_F7
+#define YCTNA_F8_1 DVDEC1.YCTNA_F8
+#define YCTNB_F0_1 DVDEC1.YCTNB_F0
+#define YCTNB_F1_1 DVDEC1.YCTNB_F1
+#define YCTNB_F2_1 DVDEC1.YCTNB_F2
+#define YCTNB_F3_1 DVDEC1.YCTNB_F3
+#define YCTNB_F4_1 DVDEC1.YCTNB_F4
+#define YCTNB_F5_1 DVDEC1.YCTNB_F5
+#define YCTNB_F6_1 DVDEC1.YCTNB_F6
+#define YCTNB_F7_1 DVDEC1.YCTNB_F7
+#define YCTNB_F8_1 DVDEC1.YCTNB_F8
+#define YGAINCR_1 DVDEC1.YGAINCR
+#define CBGAINCR_1 DVDEC1.CBGAINCR
+#define CRGAINCR_1 DVDEC1.CRGAINCR
+#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
+#define PGACR_1 DVDEC1.PGACR
+#define ADCCR2_1 DVDEC1.ADCCR2
+#define ADCCR1_0 DVDEC0.ADCCR1
+#define TGCR1_0 DVDEC0.TGCR1
+#define TGCR2_0 DVDEC0.TGCR2
+#define TGCR3_0 DVDEC0.TGCR3
+#define SYNSCR1_0 DVDEC0.SYNSCR1
+#define SYNSCR2_0 DVDEC0.SYNSCR2
+#define SYNSCR3_0 DVDEC0.SYNSCR3
+#define SYNSCR4_0 DVDEC0.SYNSCR4
+#define SYNSCR5_0 DVDEC0.SYNSCR5
+#define HAFCCR1_0 DVDEC0.HAFCCR1
+#define HAFCCR2_0 DVDEC0.HAFCCR2
+#define HAFCCR3_0 DVDEC0.HAFCCR3
+#define VCDWCR1_0 DVDEC0.VCDWCR1
+#define DCPCR1_0 DVDEC0.DCPCR1
+#define DCPCR2_0 DVDEC0.DCPCR2
+#define DCPCR3_0 DVDEC0.DCPCR3
+#define DCPCR4_0 DVDEC0.DCPCR4
+#define DCPCR5_0 DVDEC0.DCPCR5
+#define DCPCR6_0 DVDEC0.DCPCR6
+#define DCPCR7_0 DVDEC0.DCPCR7
+#define DCPCR8_0 DVDEC0.DCPCR8
+#define NSDCR_0 DVDEC0.NSDCR
+#define BTLCR_0 DVDEC0.BTLCR
+#define BTGPCR_0 DVDEC0.BTGPCR
+#define ACCCR1_0 DVDEC0.ACCCR1
+#define ACCCR2_0 DVDEC0.ACCCR2
+#define ACCCR3_0 DVDEC0.ACCCR3
+#define TINTCR_0 DVDEC0.TINTCR
+#define YCDCR_0 DVDEC0.YCDCR
+#define AGCCR1_0 DVDEC0.AGCCR1
+#define AGCCR2_0 DVDEC0.AGCCR2
+#define PKLIMITCR_0 DVDEC0.PKLIMITCR
+#define RGORCR1_0 DVDEC0.RGORCR1
+#define RGORCR2_0 DVDEC0.RGORCR2
+#define RGORCR3_0 DVDEC0.RGORCR3
+#define RGORCR4_0 DVDEC0.RGORCR4
+#define RGORCR5_0 DVDEC0.RGORCR5
+#define RGORCR6_0 DVDEC0.RGORCR6
+#define RGORCR7_0 DVDEC0.RGORCR7
+#define AFCPFCR_0 DVDEC0.AFCPFCR
+#define RUPDCR_0 DVDEC0.RUPDCR
+#define VSYNCSR_0 DVDEC0.VSYNCSR
+#define HSYNCSR_0 DVDEC0.HSYNCSR
+#define DCPSR1_0 DVDEC0.DCPSR1
+#define DCPSR2_0 DVDEC0.DCPSR2
+#define NSDSR_0 DVDEC0.NSDSR
+#define CROMASR1_0 DVDEC0.CROMASR1
+#define CROMASR2_0 DVDEC0.CROMASR2
+#define SYNCSSR_0 DVDEC0.SYNCSSR
+#define AGCCSR1_0 DVDEC0.AGCCSR1
+#define AGCCSR2_0 DVDEC0.AGCCSR2
+#define YCSCR3_0 DVDEC0.YCSCR3
+#define YCSCR4_0 DVDEC0.YCSCR4
+#define YCSCR5_0 DVDEC0.YCSCR5
+#define YCSCR6_0 DVDEC0.YCSCR6
+#define YCSCR7_0 DVDEC0.YCSCR7
+#define YCSCR8_0 DVDEC0.YCSCR8
+#define YCSCR9_0 DVDEC0.YCSCR9
+#define YCSCR11_0 DVDEC0.YCSCR11
+#define YCSCR12_0 DVDEC0.YCSCR12
+#define DCPCR9_0 DVDEC0.DCPCR9
+#define YCTWA_F0_0 DVDEC0.YCTWA_F0
+#define YCTWA_F1_0 DVDEC0.YCTWA_F1
+#define YCTWA_F2_0 DVDEC0.YCTWA_F2
+#define YCTWA_F3_0 DVDEC0.YCTWA_F3
+#define YCTWA_F4_0 DVDEC0.YCTWA_F4
+#define YCTWA_F5_0 DVDEC0.YCTWA_F5
+#define YCTWA_F6_0 DVDEC0.YCTWA_F6
+#define YCTWA_F7_0 DVDEC0.YCTWA_F7
+#define YCTWA_F8_0 DVDEC0.YCTWA_F8
+#define YCTWB_F0_0 DVDEC0.YCTWB_F0
+#define YCTWB_F1_0 DVDEC0.YCTWB_F1
+#define YCTWB_F2_0 DVDEC0.YCTWB_F2
+#define YCTWB_F3_0 DVDEC0.YCTWB_F3
+#define YCTWB_F4_0 DVDEC0.YCTWB_F4
+#define YCTWB_F5_0 DVDEC0.YCTWB_F5
+#define YCTWB_F6_0 DVDEC0.YCTWB_F6
+#define YCTWB_F7_0 DVDEC0.YCTWB_F7
+#define YCTWB_F8_0 DVDEC0.YCTWB_F8
+#define YCTNA_F0_0 DVDEC0.YCTNA_F0
+#define YCTNA_F1_0 DVDEC0.YCTNA_F1
+#define YCTNA_F2_0 DVDEC0.YCTNA_F2
+#define YCTNA_F3_0 DVDEC0.YCTNA_F3
+#define YCTNA_F4_0 DVDEC0.YCTNA_F4
+#define YCTNA_F5_0 DVDEC0.YCTNA_F5
+#define YCTNA_F6_0 DVDEC0.YCTNA_F6
+#define YCTNA_F7_0 DVDEC0.YCTNA_F7
+#define YCTNA_F8_0 DVDEC0.YCTNA_F8
+#define YCTNB_F0_0 DVDEC0.YCTNB_F0
+#define YCTNB_F1_0 DVDEC0.YCTNB_F1
+#define YCTNB_F2_0 DVDEC0.YCTNB_F2
+#define YCTNB_F3_0 DVDEC0.YCTNB_F3
+#define YCTNB_F4_0 DVDEC0.YCTNB_F4
+#define YCTNB_F5_0 DVDEC0.YCTNB_F5
+#define YCTNB_F6_0 DVDEC0.YCTNB_F6
+#define YCTNB_F7_0 DVDEC0.YCTNB_F7
+#define YCTNB_F8_0 DVDEC0.YCTNB_F8
+#define YGAINCR_0 DVDEC0.YGAINCR
+#define CBGAINCR_0 DVDEC0.CBGAINCR
+#define CRGAINCR_0 DVDEC0.CRGAINCR
+#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
+#define PGACR_0 DVDEC0.PGACR
+#define ADCCR2_0 DVDEC0.ADCCR2
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h
new file mode 100644
index 000000000..88b268ec7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h
@@ -0,0 +1,427 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ether_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ETHER_IODEFINE_H
+#define ETHER_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ether
+{ /* ETHER */
+ volatile uint32_t EDSR0; /* EDSR0 */
+ volatile uint8_t dummy207[12]; /* */
+ volatile uint32_t TDLAR0; /* TDLAR0 */
+ volatile uint32_t TDFAR0; /* TDFAR0 */
+ volatile uint32_t TDFXR0; /* TDFXR0 */
+ volatile uint32_t TDFFR0; /* TDFFR0 */
+ volatile uint8_t dummy208[16]; /* */
+ volatile uint32_t RDLAR0; /* RDLAR0 */
+ volatile uint32_t RDFAR0; /* RDFAR0 */
+ volatile uint32_t RDFXR0; /* RDFXR0 */
+ volatile uint32_t RDFFR0; /* RDFFR0 */
+ volatile uint8_t dummy209[960]; /* */
+ volatile uint32_t EDMR0; /* EDMR0 */
+ volatile uint8_t dummy210[4]; /* */
+ volatile uint32_t EDTRR0; /* EDTRR0 */
+ volatile uint8_t dummy211[4]; /* */
+ volatile uint32_t EDRRR0; /* EDRRR0 */
+ volatile uint8_t dummy212[20]; /* */
+ volatile uint32_t EESR0; /* EESR0 */
+ volatile uint8_t dummy213[4]; /* */
+ volatile uint32_t EESIPR0; /* EESIPR0 */
+ volatile uint8_t dummy214[4]; /* */
+ volatile uint32_t TRSCER0; /* TRSCER0 */
+ volatile uint8_t dummy215[4]; /* */
+ volatile uint32_t RMFCR0; /* RMFCR0 */
+ volatile uint8_t dummy216[4]; /* */
+ volatile uint32_t TFTR0; /* TFTR0 */
+ volatile uint8_t dummy217[4]; /* */
+ volatile uint32_t FDR0; /* FDR0 */
+ volatile uint8_t dummy218[4]; /* */
+ volatile uint32_t RMCR0; /* RMCR0 */
+ volatile uint8_t dummy219[4]; /* */
+ volatile uint32_t RPADIR0; /* RPADIR0 */
+ volatile uint8_t dummy220[4]; /* */
+ volatile uint32_t FCFTR0; /* FCFTR0 */
+ volatile uint8_t dummy221[120]; /* */
+ volatile uint32_t CSMR; /* CSMR */
+ volatile uint32_t CSSBM; /* CSSBM */
+ volatile uint32_t CSSMR; /* CSSMR */
+ volatile uint8_t dummy222[16]; /* */
+ volatile uint32_t ECMR0; /* ECMR0 */
+ volatile uint8_t dummy223[4]; /* */
+ volatile uint32_t RFLR0; /* RFLR0 */
+ volatile uint8_t dummy224[4]; /* */
+ volatile uint32_t ECSR0; /* ECSR0 */
+ volatile uint8_t dummy225[4]; /* */
+ volatile uint32_t ECSIPR0; /* ECSIPR0 */
+ volatile uint8_t dummy226[4]; /* */
+ volatile uint32_t PIR0; /* PIR0 */
+ volatile uint8_t dummy227[48]; /* */
+ volatile uint32_t APR0; /* APR0 */
+ volatile uint32_t MPR0; /* MPR0 */
+ volatile uint32_t PFTCR0; /* PFTCR0 */
+ volatile uint32_t PFRCR0; /* PFRCR0 */
+ volatile uint32_t TPAUSER0; /* TPAUSER0 */
+ volatile uint8_t dummy228[88]; /* */
+ volatile uint32_t MAHR0; /* MAHR0 */
+ volatile uint8_t dummy229[4]; /* */
+ volatile uint32_t MALR0; /* MALR0 */
+ volatile uint8_t dummy230[372]; /* */
+ volatile uint32_t CEFCR0; /* CEFCR0 */
+ volatile uint8_t dummy231[4]; /* */
+ volatile uint32_t FRECR0; /* FRECR0 */
+ volatile uint8_t dummy232[4]; /* */
+ volatile uint32_t TSFRCR0; /* TSFRCR0 */
+ volatile uint8_t dummy233[4]; /* */
+ volatile uint32_t TLFRCR0; /* TLFRCR0 */
+ volatile uint8_t dummy234[4]; /* */
+ volatile uint32_t RFCR0; /* RFCR0 */
+ volatile uint8_t dummy235[20]; /* */
+ volatile uint32_t MAFCR0; /* MAFCR0 */
+ volatile uint8_t dummy236[4228]; /* */
+ volatile uint32_t ARSTR; /* ARSTR */
+ volatile uint32_t TSU_CTRST; /* TSU_CTRST */
+ volatile uint8_t dummy237[80]; /* */
+ volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */
+ volatile uint8_t dummy238[4]; /* */
+ volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */
+ volatile uint32_t TSU_TEN; /* TSU_TEN */
+ volatile uint8_t dummy239[24]; /* */
+ volatile uint32_t TXNLCR0; /* TXNLCR0 */
+ volatile uint32_t TXALCR0; /* TXALCR0 */
+ volatile uint32_t RXNLCR0; /* RXNLCR0 */
+ volatile uint32_t RXALCR0; /* RXALCR0 */
+ volatile uint8_t dummy240[112]; /* */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
+ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */
+ volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */
+ volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */
+ volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */
+ volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */
+ volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */
+ volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */
+ volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */
+ volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */
+ volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */
+ volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */
+ volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */
+ volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */
+ volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */
+ volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */
+ volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */
+ volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */
+ volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */
+ volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */
+ volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */
+ volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */
+ volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */
+ volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */
+ volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */
+ volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */
+ volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */
+ volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */
+ volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */
+ volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */
+ volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */
+ volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */
+ volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */
+/* end of struct st_ether_from_tsu_adrh0 */
+};
+
+
+struct st_ether_from_tsu_adrh0
+{
+ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
+ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
+};
+
+
+#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channnel array defines of ETHER */
+
+/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
+ &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
+ &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
+ &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channnel array defines of ETHER */
+
+
+#define ETHEREDSR0 ETHER.EDSR0
+#define ETHERTDLAR0 ETHER.TDLAR0
+#define ETHERTDFAR0 ETHER.TDFAR0
+#define ETHERTDFXR0 ETHER.TDFXR0
+#define ETHERTDFFR0 ETHER.TDFFR0
+#define ETHERRDLAR0 ETHER.RDLAR0
+#define ETHERRDFAR0 ETHER.RDFAR0
+#define ETHERRDFXR0 ETHER.RDFXR0
+#define ETHERRDFFR0 ETHER.RDFFR0
+#define ETHEREDMR0 ETHER.EDMR0
+#define ETHEREDTRR0 ETHER.EDTRR0
+#define ETHEREDRRR0 ETHER.EDRRR0
+#define ETHEREESR0 ETHER.EESR0
+#define ETHEREESIPR0 ETHER.EESIPR0
+#define ETHERTRSCER0 ETHER.TRSCER0
+#define ETHERRMFCR0 ETHER.RMFCR0
+#define ETHERTFTR0 ETHER.TFTR0
+#define ETHERFDR0 ETHER.FDR0
+#define ETHERRMCR0 ETHER.RMCR0
+#define ETHERRPADIR0 ETHER.RPADIR0
+#define ETHERFCFTR0 ETHER.FCFTR0
+#define ETHERCSMR ETHER.CSMR
+#define ETHERCSSBM ETHER.CSSBM
+#define ETHERCSSMR ETHER.CSSMR
+#define ETHERECMR0 ETHER.ECMR0
+#define ETHERRFLR0 ETHER.RFLR0
+#define ETHERECSR0 ETHER.ECSR0
+#define ETHERECSIPR0 ETHER.ECSIPR0
+#define ETHERPIR0 ETHER.PIR0
+#define ETHERAPR0 ETHER.APR0
+#define ETHERMPR0 ETHER.MPR0
+#define ETHERPFTCR0 ETHER.PFTCR0
+#define ETHERPFRCR0 ETHER.PFRCR0
+#define ETHERTPAUSER0 ETHER.TPAUSER0
+#define ETHERMAHR0 ETHER.MAHR0
+#define ETHERMALR0 ETHER.MALR0
+#define ETHERCEFCR0 ETHER.CEFCR0
+#define ETHERFRECR0 ETHER.FRECR0
+#define ETHERTSFRCR0 ETHER.TSFRCR0
+#define ETHERTLFRCR0 ETHER.TLFRCR0
+#define ETHERRFCR0 ETHER.RFCR0
+#define ETHERMAFCR0 ETHER.MAFCR0
+#define ETHERARSTR ETHER.ARSTR
+#define ETHERTSU_CTRST ETHER.TSU_CTRST
+#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
+#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
+#define ETHERTSU_TEN ETHER.TSU_TEN
+#define ETHERTXNLCR0 ETHER.TXNLCR0
+#define ETHERTXALCR0 ETHER.TXALCR0
+#define ETHERRXNLCR0 ETHER.RXNLCR0
+#define ETHERRXALCR0 ETHER.RXALCR0
+#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
+#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
+#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
+#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
+#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
+#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
+#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
+#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
+#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
+#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
+#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
+#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
+#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
+#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
+#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
+#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
+#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
+#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
+#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
+#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
+#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
+#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
+#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
+#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
+#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
+#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
+#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
+#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
+#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
+#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
+#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
+#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
+#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
+#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
+#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
+#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
+#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
+#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
+#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
+#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
+#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
+#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
+#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
+#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
+#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
+#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
+#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
+#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
+#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
+#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
+#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
+#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
+#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
+#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
+#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
+#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
+#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
+#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
+#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
+#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
+#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
+#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
+#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
+#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h
new file mode 100644
index 000000000..3f8ec183c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : flctl_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef FLCTL_IODEFINE_H
+#define FLCTL_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_flctl
+{ /* FLCTL */
+ volatile uint32_t FLCMNCR; /* FLCMNCR */
+ volatile uint32_t FLCMDCR; /* FLCMDCR */
+ volatile uint32_t FLCMCDR; /* FLCMCDR */
+ volatile uint32_t FLADR; /* FLADR */
+ volatile uint32_t FLDATAR; /* FLDATAR */
+ volatile uint32_t FLDTCNTR; /* FLDTCNTR */
+ volatile uint32_t FLINTDMACR; /* FLINTDMACR */
+ volatile uint32_t FLBSYTMR; /* FLBSYTMR */
+ volatile uint32_t FLBSYCNT; /* FLBSYCNT */
+ volatile uint8_t dummy555[8]; /* */
+ volatile uint8_t FLTRCR; /* FLTRCR */
+ volatile uint8_t dummy556[15]; /* */
+ volatile uint32_t FLADR2; /* FLADR2 */
+ volatile uint8_t dummy557[16]; /* */
+ volatile uint32_t FLDTFIFO; /* FLDTFIFO */
+ volatile uint8_t dummy558[12]; /* */
+ volatile uint32_t FLECFIFO; /* FLECFIFO */
+};
+
+
+#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR FLCTL.FLCMNCR
+#define FLCTLFLCMDCR FLCTL.FLCMDCR
+#define FLCTLFLCMCDR FLCTL.FLCMCDR
+#define FLCTLFLADR FLCTL.FLADR
+#define FLCTLFLDATAR FLCTL.FLDATAR
+#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
+#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
+#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
+#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
+#define FLCTLFLTRCR FLCTL.FLTRCR
+#define FLCTLFLADR2 FLCTL.FLADR2
+#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
+#define FLCTLFLECFIFO FLCTL.FLECFIFO
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h
new file mode 100644
index 000000000..8bedb518f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h
@@ -0,0 +1,1074 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : gpio_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef GPIO_IODEFINE_H
+#define GPIO_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_gpio
+{ /* GPIO */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P1; /* P1 */
+ volatile uint8_t dummy348[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P2; /* P2 */
+ volatile uint8_t dummy349[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P3; /* P3 */
+ volatile uint8_t dummy350[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P4; /* P4 */
+ volatile uint8_t dummy351[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P5; /* P5 */
+ volatile uint8_t dummy352[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P6; /* P6 */
+ volatile uint8_t dummy353[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P7; /* P7 */
+ volatile uint8_t dummy354[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P8; /* P8 */
+ volatile uint8_t dummy355[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P9; /* P9 */
+ volatile uint8_t dummy356[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P10; /* P10 */
+ volatile uint8_t dummy357[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P11; /* P11 */
+ volatile uint8_t dummy3580[2]; /* */
+/* end of struct st_gpio_from_p1 */
+ volatile uint8_t dummy3581[212]; /* */
+#define GPIO_PSRn_COUNT 11
+ volatile uint32_t PSR1; /* PSR1 */
+ volatile uint32_t PSR2; /* PSR2 */
+ volatile uint32_t PSR3; /* PSR3 */
+ volatile uint32_t PSR4; /* PSR4 */
+ volatile uint32_t PSR5; /* PSR5 */
+ volatile uint32_t PSR6; /* PSR6 */
+ volatile uint32_t PSR7; /* PSR7 */
+ volatile uint32_t PSR8; /* PSR8 */
+ volatile uint32_t PSR9; /* PSR9 */
+ volatile uint32_t PSR10; /* PSR10 */
+ volatile uint32_t PSR11; /* PSR11 */
+ volatile uint8_t dummy359[208]; /* */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR0; /* PPR0 */
+ volatile uint8_t dummy360[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR1; /* PPR1 */
+ volatile uint8_t dummy361[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR2; /* PPR2 */
+ volatile uint8_t dummy362[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR3; /* PPR3 */
+ volatile uint8_t dummy363[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR4; /* PPR4 */
+ volatile uint8_t dummy364[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR5; /* PPR5 */
+ volatile uint8_t dummy365[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR6; /* PPR6 */
+ volatile uint8_t dummy366[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR7; /* PPR7 */
+ volatile uint8_t dummy367[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR8; /* PPR8 */
+ volatile uint8_t dummy368[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR9; /* PPR9 */
+ volatile uint8_t dummy369[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR10; /* PPR10 */
+ volatile uint8_t dummy370[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR11; /* PPR11 */
+ volatile uint8_t dummy3710[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+ volatile uint8_t dummy3711[212]; /* */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM1; /* PM1 */
+ volatile uint8_t dummy372[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM2; /* PM2 */
+ volatile uint8_t dummy373[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM3; /* PM3 */
+ volatile uint8_t dummy374[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM4; /* PM4 */
+ volatile uint8_t dummy375[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM5; /* PM5 */
+ volatile uint8_t dummy376[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM6; /* PM6 */
+ volatile uint8_t dummy377[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM7; /* PM7 */
+ volatile uint8_t dummy378[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM8; /* PM8 */
+ volatile uint8_t dummy379[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM9; /* PM9 */
+ volatile uint8_t dummy380[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM10; /* PM10 */
+ volatile uint8_t dummy381[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM11; /* PM11 */
+ volatile uint8_t dummy3820[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+ volatile uint8_t dummy3821[208]; /* */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC0; /* PMC0 */
+ volatile uint8_t dummy383[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC1; /* PMC1 */
+ volatile uint8_t dummy384[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC2; /* PMC2 */
+ volatile uint8_t dummy385[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC3; /* PMC3 */
+ volatile uint8_t dummy386[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC4; /* PMC4 */
+ volatile uint8_t dummy387[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC5; /* PMC5 */
+ volatile uint8_t dummy388[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC6; /* PMC6 */
+ volatile uint8_t dummy389[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC7; /* PMC7 */
+ volatile uint8_t dummy390[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC8; /* PMC8 */
+ volatile uint8_t dummy391[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC9; /* PMC9 */
+ volatile uint8_t dummy392[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC10; /* PMC10 */
+ volatile uint8_t dummy393[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC11; /* PMC11 */
+ volatile uint8_t dummy3940[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+ volatile uint8_t dummy3941[212]; /* */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC1; /* PFC1 */
+ volatile uint8_t dummy395[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC2; /* PFC2 */
+ volatile uint8_t dummy396[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC3; /* PFC3 */
+ volatile uint8_t dummy397[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC4; /* PFC4 */
+ volatile uint8_t dummy398[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC5; /* PFC5 */
+ volatile uint8_t dummy399[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC6; /* PFC6 */
+ volatile uint8_t dummy400[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC7; /* PFC7 */
+ volatile uint8_t dummy401[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC8; /* PFC8 */
+ volatile uint8_t dummy402[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC9; /* PFC9 */
+ volatile uint8_t dummy403[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC10; /* PFC10 */
+ volatile uint8_t dummy404[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC11; /* PFC11 */
+ volatile uint8_t dummy4050[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+ volatile uint8_t dummy4051[212]; /* */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE1; /* PFCE1 */
+ volatile uint8_t dummy406[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE2; /* PFCE2 */
+ volatile uint8_t dummy407[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE3; /* PFCE3 */
+ volatile uint8_t dummy408[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE4; /* PFCE4 */
+ volatile uint8_t dummy409[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE5; /* PFCE5 */
+ volatile uint8_t dummy410[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE6; /* PFCE6 */
+ volatile uint8_t dummy411[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE7; /* PFCE7 */
+ volatile uint8_t dummy412[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE8; /* PFCE8 */
+ volatile uint8_t dummy413[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE9; /* PFCE9 */
+ volatile uint8_t dummy414[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE10; /* PFCE10 */
+ volatile uint8_t dummy415[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE11; /* PFCE11 */
+ volatile uint8_t dummy4160[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+ volatile uint8_t dummy4161[212]; /* */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT1; /* PNOT1 */
+ volatile uint8_t dummy417[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT2; /* PNOT2 */
+ volatile uint8_t dummy418[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT3; /* PNOT3 */
+ volatile uint8_t dummy419[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT4; /* PNOT4 */
+ volatile uint8_t dummy420[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT5; /* PNOT5 */
+ volatile uint8_t dummy421[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT6; /* PNOT6 */
+ volatile uint8_t dummy422[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT7; /* PNOT7 */
+ volatile uint8_t dummy423[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT8; /* PNOT8 */
+ volatile uint8_t dummy424[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT9; /* PNOT9 */
+ volatile uint8_t dummy425[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT10; /* PNOT10 */
+ volatile uint8_t dummy426[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT11; /* PNOT11 */
+ volatile uint8_t dummy4270[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+ volatile uint8_t dummy4271[212]; /* */
+#define GPIO_PMSRn_COUNT 11
+ volatile uint32_t PMSR1; /* PMSR1 */
+ volatile uint32_t PMSR2; /* PMSR2 */
+ volatile uint32_t PMSR3; /* PMSR3 */
+ volatile uint32_t PMSR4; /* PMSR4 */
+ volatile uint32_t PMSR5; /* PMSR5 */
+ volatile uint32_t PMSR6; /* PMSR6 */
+ volatile uint32_t PMSR7; /* PMSR7 */
+ volatile uint32_t PMSR8; /* PMSR8 */
+ volatile uint32_t PMSR9; /* PMSR9 */
+ volatile uint32_t PMSR10; /* PMSR10 */
+ volatile uint32_t PMSR11; /* PMSR11 */
+ volatile uint8_t dummy428[208]; /* */
+#define GPIO_PMCSRn_COUNT 12
+ volatile uint32_t PMCSR0; /* PMCSR0 */
+ volatile uint32_t PMCSR1; /* PMCSR1 */
+ volatile uint32_t PMCSR2; /* PMCSR2 */
+ volatile uint32_t PMCSR3; /* PMCSR3 */
+ volatile uint32_t PMCSR4; /* PMCSR4 */
+ volatile uint32_t PMCSR5; /* PMCSR5 */
+ volatile uint32_t PMCSR6; /* PMCSR6 */
+ volatile uint32_t PMCSR7; /* PMCSR7 */
+ volatile uint32_t PMCSR8; /* PMCSR8 */
+ volatile uint32_t PMCSR9; /* PMCSR9 */
+ volatile uint32_t PMCSR10; /* PMCSR10 */
+ volatile uint32_t PMCSR11; /* PMCSR11 */
+ volatile uint8_t dummy429[212]; /* */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE1; /* PFCAE1 */
+ volatile uint8_t dummy430[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE2; /* PFCAE2 */
+ volatile uint8_t dummy431[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE3; /* PFCAE3 */
+ volatile uint8_t dummy432[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE4; /* PFCAE4 */
+ volatile uint8_t dummy433[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE5; /* PFCAE5 */
+ volatile uint8_t dummy434[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE6; /* PFCAE6 */
+ volatile uint8_t dummy435[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE7; /* PFCAE7 */
+ volatile uint8_t dummy436[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE8; /* PFCAE8 */
+ volatile uint8_t dummy437[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE9; /* PFCAE9 */
+ volatile uint8_t dummy438[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE10; /* PFCAE10 */
+ volatile uint8_t dummy439[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE11; /* PFCAE11 */
+ volatile uint8_t dummy4400[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+ volatile uint8_t dummy4401[464]; /* */
+ volatile uint32_t SNCR; /* SNCR */
+ volatile uint8_t dummy441[13308]; /* */
+ volatile uint16_t PIBC0; /* PIBC0 */
+ volatile uint8_t dummy442[2]; /* */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC1; /* PIBC1 */
+ volatile uint8_t dummy443[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC2; /* PIBC2 */
+ volatile uint8_t dummy444[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC3; /* PIBC3 */
+ volatile uint8_t dummy445[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC4; /* PIBC4 */
+ volatile uint8_t dummy446[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC5; /* PIBC5 */
+ volatile uint8_t dummy447[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC6; /* PIBC6 */
+ volatile uint8_t dummy448[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC7; /* PIBC7 */
+ volatile uint8_t dummy449[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC8; /* PIBC8 */
+ volatile uint8_t dummy450[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC9; /* PIBC9 */
+ volatile uint8_t dummy451[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC10; /* PIBC10 */
+ volatile uint8_t dummy452[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC11; /* PIBC11 */
+ volatile uint8_t dummy4530[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+ volatile uint8_t dummy4531[212]; /* */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC1; /* PBDC1 */
+ volatile uint8_t dummy454[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC2; /* PBDC2 */
+ volatile uint8_t dummy455[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC3; /* PBDC3 */
+ volatile uint8_t dummy456[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC4; /* PBDC4 */
+ volatile uint8_t dummy457[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC5; /* PBDC5 */
+ volatile uint8_t dummy458[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC6; /* PBDC6 */
+ volatile uint8_t dummy459[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC7; /* PBDC7 */
+ volatile uint8_t dummy460[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC8; /* PBDC8 */
+ volatile uint8_t dummy461[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC9; /* PBDC9 */
+ volatile uint8_t dummy462[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC10; /* PBDC10 */
+ volatile uint8_t dummy463[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC11; /* PBDC11 */
+ volatile uint8_t dummy4640[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+ volatile uint8_t dummy4641[212]; /* */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC1; /* PIPC1 */
+ volatile uint8_t dummy465[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC2; /* PIPC2 */
+ volatile uint8_t dummy466[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC3; /* PIPC3 */
+ volatile uint8_t dummy467[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC4; /* PIPC4 */
+ volatile uint8_t dummy468[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC5; /* PIPC5 */
+ volatile uint8_t dummy469[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC6; /* PIPC6 */
+ volatile uint8_t dummy470[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC7; /* PIPC7 */
+ volatile uint8_t dummy471[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC8; /* PIPC8 */
+ volatile uint8_t dummy472[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC9; /* PIPC9 */
+ volatile uint8_t dummy473[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC10; /* PIPC10 */
+ volatile uint8_t dummy474[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC11; /* PIPC11 */
+ volatile uint8_t dummy4750[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+ volatile uint8_t dummy4751[2288]; /* */
+ volatile uint16_t JPPR0; /* JPPR0 */
+ volatile uint8_t dummy476[30]; /* */
+ volatile uint16_t JPMC0; /* JPMC0 */
+ volatile uint8_t dummy477[78]; /* */
+ volatile uint32_t JPMCSR0; /* JPMCSR0 */
+ volatile uint8_t dummy478[876]; /* */
+ volatile uint16_t JPIBC0; /* JPIBC0 */
+};
+
+
+struct st_gpio_from_p1
+{
+ volatile uint16_t P1; /* P1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_gpio_from_ppr0
+{
+ volatile uint16_t PPR0; /* PPR0 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pm1
+{
+ volatile uint16_t PM1; /* PM1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pmc0
+{
+ volatile uint16_t PMC0; /* PMC0 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfc1
+{
+ volatile uint16_t PFC1; /* PFC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfce1
+{
+ volatile uint16_t PFCE1; /* PFCE1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pnot1
+{
+ volatile uint16_t PNOT1; /* PNOT1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfcae1
+{
+ volatile uint16_t PFCAE1; /* PFCAE1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pibc1
+{
+ volatile uint16_t PIBC1; /* PIBC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pbdc1
+{
+ volatile uint16_t PBDC1; /* PBDC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pipc1
+{
+ volatile uint16_t PIPC1; /* PIPC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */
+
+/* Start of channnel array defines of GPIO */
+
+/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
+#define GPIO_FROM_PIPC1_ARRAY_COUNT 11
+#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
+ &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */
+#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */
+#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */
+#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */
+#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */
+#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */
+#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */
+#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */
+#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */
+#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */
+#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
+#define GPIO_FROM_PBDC1_ARRAY_COUNT 11
+#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
+ &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */
+#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */
+#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */
+#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */
+#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */
+#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */
+#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */
+#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */
+#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */
+#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */
+#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
+#define GPIO_FROM_PIBC1_ARRAY_COUNT 11
+#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
+ &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
+#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
+#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
+#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */
+#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */
+#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */
+#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */
+#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */
+#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */
+#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */
+#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11
+#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
+ &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */
+#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */
+#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */
+#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */
+#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */
+#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */
+#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */
+#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */
+#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */
+#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */
+#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
+/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
+#define GPIO_FROM_PNOT1_ARRAY_COUNT 11
+#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
+ &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */
+#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */
+#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */
+#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */
+#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */
+#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */
+#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */
+#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */
+#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */
+#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */
+#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
+#define GPIO_FROM_PFCE1_ARRAY_COUNT 11
+#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
+ &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */
+#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */
+#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */
+#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */
+#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */
+#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */
+#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */
+#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */
+#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */
+#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */
+#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
+#define GPIO_FROM_PFC1_ARRAY_COUNT 11
+#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
+ &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */
+#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */
+#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */
+#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */
+#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */
+#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */
+#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */
+#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */
+#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */
+#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */
+#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
+/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
+#define GPIO_FROM_PMC0_ARRAY_COUNT 12
+#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
+ &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */
+#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */
+#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */
+#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */
+#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */
+#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */
+#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */
+#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */
+#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */
+#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */
+#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */
+#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PM1_ARRAY */
+/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
+#define GPIO_FROM_PM1_ARRAY_COUNT 11
+#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
+ &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */
+#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */
+#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */
+#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */
+#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */
+#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */
+#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */
+#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */
+#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */
+#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */
+#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */
+
+
+/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
+/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
+#define GPIO_FROM_PPR0_ARRAY_COUNT 12
+#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
+ &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */
+#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */
+#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */
+#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */
+#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */
+#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */
+#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */
+#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */
+#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */
+#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */
+#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */
+#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
+
+
+/* Channnel array defines of GPIO_FROM_P1_ARRAY */
+/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
+#define GPIO_FROM_P1_ARRAY_COUNT 11
+#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
+ &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */
+#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */
+#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */
+#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */
+#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */
+#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */
+#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */
+#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */
+#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */
+#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */
+#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */
+
+/* End of channnel array defines of GPIO */
+
+
+#define GPIOP1 GPIO.P1
+#define GPIOP2 GPIO.P2
+#define GPIOP3 GPIO.P3
+#define GPIOP4 GPIO.P4
+#define GPIOP5 GPIO.P5
+#define GPIOP6 GPIO.P6
+#define GPIOP7 GPIO.P7
+#define GPIOP8 GPIO.P8
+#define GPIOP9 GPIO.P9
+#define GPIOP10 GPIO.P10
+#define GPIOP11 GPIO.P11
+#define GPIOPSR1 GPIO.PSR1
+#define GPIOPSR2 GPIO.PSR2
+#define GPIOPSR3 GPIO.PSR3
+#define GPIOPSR4 GPIO.PSR4
+#define GPIOPSR5 GPIO.PSR5
+#define GPIOPSR6 GPIO.PSR6
+#define GPIOPSR7 GPIO.PSR7
+#define GPIOPSR8 GPIO.PSR8
+#define GPIOPSR9 GPIO.PSR9
+#define GPIOPSR10 GPIO.PSR10
+#define GPIOPSR11 GPIO.PSR11
+#define GPIOPPR0 GPIO.PPR0
+#define GPIOPPR1 GPIO.PPR1
+#define GPIOPPR2 GPIO.PPR2
+#define GPIOPPR3 GPIO.PPR3
+#define GPIOPPR4 GPIO.PPR4
+#define GPIOPPR5 GPIO.PPR5
+#define GPIOPPR6 GPIO.PPR6
+#define GPIOPPR7 GPIO.PPR7
+#define GPIOPPR8 GPIO.PPR8
+#define GPIOPPR9 GPIO.PPR9
+#define GPIOPPR10 GPIO.PPR10
+#define GPIOPPR11 GPIO.PPR11
+#define GPIOPM1 GPIO.PM1
+#define GPIOPM2 GPIO.PM2
+#define GPIOPM3 GPIO.PM3
+#define GPIOPM4 GPIO.PM4
+#define GPIOPM5 GPIO.PM5
+#define GPIOPM6 GPIO.PM6
+#define GPIOPM7 GPIO.PM7
+#define GPIOPM8 GPIO.PM8
+#define GPIOPM9 GPIO.PM9
+#define GPIOPM10 GPIO.PM10
+#define GPIOPM11 GPIO.PM11
+#define GPIOPMC0 GPIO.PMC0
+#define GPIOPMC1 GPIO.PMC1
+#define GPIOPMC2 GPIO.PMC2
+#define GPIOPMC3 GPIO.PMC3
+#define GPIOPMC4 GPIO.PMC4
+#define GPIOPMC5 GPIO.PMC5
+#define GPIOPMC6 GPIO.PMC6
+#define GPIOPMC7 GPIO.PMC7
+#define GPIOPMC8 GPIO.PMC8
+#define GPIOPMC9 GPIO.PMC9
+#define GPIOPMC10 GPIO.PMC10
+#define GPIOPMC11 GPIO.PMC11
+#define GPIOPFC1 GPIO.PFC1
+#define GPIOPFC2 GPIO.PFC2
+#define GPIOPFC3 GPIO.PFC3
+#define GPIOPFC4 GPIO.PFC4
+#define GPIOPFC5 GPIO.PFC5
+#define GPIOPFC6 GPIO.PFC6
+#define GPIOPFC7 GPIO.PFC7
+#define GPIOPFC8 GPIO.PFC8
+#define GPIOPFC9 GPIO.PFC9
+#define GPIOPFC10 GPIO.PFC10
+#define GPIOPFC11 GPIO.PFC11
+#define GPIOPFCE1 GPIO.PFCE1
+#define GPIOPFCE2 GPIO.PFCE2
+#define GPIOPFCE3 GPIO.PFCE3
+#define GPIOPFCE4 GPIO.PFCE4
+#define GPIOPFCE5 GPIO.PFCE5
+#define GPIOPFCE6 GPIO.PFCE6
+#define GPIOPFCE7 GPIO.PFCE7
+#define GPIOPFCE8 GPIO.PFCE8
+#define GPIOPFCE9 GPIO.PFCE9
+#define GPIOPFCE10 GPIO.PFCE10
+#define GPIOPFCE11 GPIO.PFCE11
+#define GPIOPNOT1 GPIO.PNOT1
+#define GPIOPNOT2 GPIO.PNOT2
+#define GPIOPNOT3 GPIO.PNOT3
+#define GPIOPNOT4 GPIO.PNOT4
+#define GPIOPNOT5 GPIO.PNOT5
+#define GPIOPNOT6 GPIO.PNOT6
+#define GPIOPNOT7 GPIO.PNOT7
+#define GPIOPNOT8 GPIO.PNOT8
+#define GPIOPNOT9 GPIO.PNOT9
+#define GPIOPNOT10 GPIO.PNOT10
+#define GPIOPNOT11 GPIO.PNOT11
+#define GPIOPMSR1 GPIO.PMSR1
+#define GPIOPMSR2 GPIO.PMSR2
+#define GPIOPMSR3 GPIO.PMSR3
+#define GPIOPMSR4 GPIO.PMSR4
+#define GPIOPMSR5 GPIO.PMSR5
+#define GPIOPMSR6 GPIO.PMSR6
+#define GPIOPMSR7 GPIO.PMSR7
+#define GPIOPMSR8 GPIO.PMSR8
+#define GPIOPMSR9 GPIO.PMSR9
+#define GPIOPMSR10 GPIO.PMSR10
+#define GPIOPMSR11 GPIO.PMSR11
+#define GPIOPMCSR0 GPIO.PMCSR0
+#define GPIOPMCSR1 GPIO.PMCSR1
+#define GPIOPMCSR2 GPIO.PMCSR2
+#define GPIOPMCSR3 GPIO.PMCSR3
+#define GPIOPMCSR4 GPIO.PMCSR4
+#define GPIOPMCSR5 GPIO.PMCSR5
+#define GPIOPMCSR6 GPIO.PMCSR6
+#define GPIOPMCSR7 GPIO.PMCSR7
+#define GPIOPMCSR8 GPIO.PMCSR8
+#define GPIOPMCSR9 GPIO.PMCSR9
+#define GPIOPMCSR10 GPIO.PMCSR10
+#define GPIOPMCSR11 GPIO.PMCSR11
+#define GPIOPFCAE1 GPIO.PFCAE1
+#define GPIOPFCAE2 GPIO.PFCAE2
+#define GPIOPFCAE3 GPIO.PFCAE3
+#define GPIOPFCAE4 GPIO.PFCAE4
+#define GPIOPFCAE5 GPIO.PFCAE5
+#define GPIOPFCAE6 GPIO.PFCAE6
+#define GPIOPFCAE7 GPIO.PFCAE7
+#define GPIOPFCAE8 GPIO.PFCAE8
+#define GPIOPFCAE9 GPIO.PFCAE9
+#define GPIOPFCAE10 GPIO.PFCAE10
+#define GPIOPFCAE11 GPIO.PFCAE11
+#define GPIOSNCR GPIO.SNCR
+#define GPIOPIBC0 GPIO.PIBC0
+#define GPIOPIBC1 GPIO.PIBC1
+#define GPIOPIBC2 GPIO.PIBC2
+#define GPIOPIBC3 GPIO.PIBC3
+#define GPIOPIBC4 GPIO.PIBC4
+#define GPIOPIBC5 GPIO.PIBC5
+#define GPIOPIBC6 GPIO.PIBC6
+#define GPIOPIBC7 GPIO.PIBC7
+#define GPIOPIBC8 GPIO.PIBC8
+#define GPIOPIBC9 GPIO.PIBC9
+#define GPIOPIBC10 GPIO.PIBC10
+#define GPIOPIBC11 GPIO.PIBC11
+#define GPIOPBDC1 GPIO.PBDC1
+#define GPIOPBDC2 GPIO.PBDC2
+#define GPIOPBDC3 GPIO.PBDC3
+#define GPIOPBDC4 GPIO.PBDC4
+#define GPIOPBDC5 GPIO.PBDC5
+#define GPIOPBDC6 GPIO.PBDC6
+#define GPIOPBDC7 GPIO.PBDC7
+#define GPIOPBDC8 GPIO.PBDC8
+#define GPIOPBDC9 GPIO.PBDC9
+#define GPIOPBDC10 GPIO.PBDC10
+#define GPIOPBDC11 GPIO.PBDC11
+#define GPIOPIPC1 GPIO.PIPC1
+#define GPIOPIPC2 GPIO.PIPC2
+#define GPIOPIPC3 GPIO.PIPC3
+#define GPIOPIPC4 GPIO.PIPC4
+#define GPIOPIPC5 GPIO.PIPC5
+#define GPIOPIPC6 GPIO.PIPC6
+#define GPIOPIPC7 GPIO.PIPC7
+#define GPIOPIPC8 GPIO.PIPC8
+#define GPIOPIPC9 GPIO.PIPC9
+#define GPIOPIPC10 GPIO.PIPC10
+#define GPIOPIPC11 GPIO.PIPC11
+#define GPIOJPPR0 GPIO.JPPR0
+#define GPIOJPMC0 GPIO.JPMC0
+#define GPIOJPMCSR0 GPIO.JPMCSR0
+#define GPIOJPIBC0 GPIO.JPIBC0
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h
new file mode 100644
index 000000000..8b76e23c6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h
@@ -0,0 +1,119 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ieb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IEB_IODEFINE_H
+#define IEB_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ieb
+{ /* IEB */
+ volatile uint8_t B0BCR; /* B0BCR */
+ volatile uint8_t dummy495[3]; /* */
+ volatile uint8_t B0PSR; /* B0PSR */
+ volatile uint8_t dummy496[3]; /* */
+ volatile uint16_t B0UAR; /* B0UAR */
+ volatile uint8_t dummy497[2]; /* */
+ volatile uint16_t B0SAR; /* B0SAR */
+ volatile uint8_t dummy498[2]; /* */
+ volatile uint16_t B0PAR; /* B0PAR */
+ volatile uint8_t dummy499[2]; /* */
+ volatile uint16_t B0RSA; /* B0RSA */
+ volatile uint8_t dummy500[2]; /* */
+ volatile uint8_t B0CDR; /* B0CDR */
+ volatile uint8_t dummy501[3]; /* */
+ volatile uint8_t B0TCD; /* B0TCD */
+ volatile uint8_t dummy502[3]; /* */
+ volatile uint8_t B0RCD; /* B0RCD */
+ volatile uint8_t dummy503[3]; /* */
+ volatile uint8_t B0DLR; /* B0DLR */
+ volatile uint8_t dummy504[3]; /* */
+ volatile uint8_t B0TDL; /* B0TDL */
+ volatile uint8_t dummy505[3]; /* */
+ volatile uint8_t B0RDL; /* B0RDL */
+ volatile uint8_t dummy506[3]; /* */
+ volatile uint8_t B0CKS; /* B0CKS */
+ volatile uint8_t dummy507[3]; /* */
+ volatile uint8_t B0TMS; /* B0TMS */
+ volatile uint8_t dummy508[3]; /* */
+ volatile uint8_t B0PCR; /* B0PCR */
+ volatile uint8_t dummy509[3]; /* */
+ volatile uint16_t B0BSR; /* B0BSR */
+ volatile uint8_t dummy510[2]; /* */
+ volatile uint8_t B0SSR; /* B0SSR */
+ volatile uint8_t dummy511[3]; /* */
+ volatile uint8_t B0USR; /* B0USR */
+ volatile uint8_t dummy512[3]; /* */
+ volatile uint8_t B0ISR; /* B0ISR */
+ volatile uint8_t dummy513[3]; /* */
+ volatile uint8_t B0ESR; /* B0ESR */
+ volatile uint8_t dummy514[3]; /* */
+ volatile uint8_t B0FSR; /* B0FSR */
+ volatile uint8_t dummy515[3]; /* */
+ volatile uint8_t B0SCR; /* B0SCR */
+ volatile uint8_t dummy516[3]; /* */
+ volatile uint8_t B0CCR; /* B0CCR */
+ volatile uint8_t dummy517[3]; /* */
+ volatile uint8_t B0STC0; /* B0STC0 */
+ volatile uint8_t dummy518[3]; /* */
+ volatile uint8_t B0STC1; /* B0STC1 */
+ volatile uint8_t dummy519[3]; /* */
+ volatile uint8_t B0DR; /* B0DR */
+};
+
+
+#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR IEB.B0BCR
+#define IEBB0PSR IEB.B0PSR
+#define IEBB0UAR IEB.B0UAR
+#define IEBB0SAR IEB.B0SAR
+#define IEBB0PAR IEB.B0PAR
+#define IEBB0RSA IEB.B0RSA
+#define IEBB0CDR IEB.B0CDR
+#define IEBB0TCD IEB.B0TCD
+#define IEBB0RCD IEB.B0RCD
+#define IEBB0DLR IEB.B0DLR
+#define IEBB0TDL IEB.B0TDL
+#define IEBB0RDL IEB.B0RDL
+#define IEBB0CKS IEB.B0CKS
+#define IEBB0TMS IEB.B0TMS
+#define IEBB0PCR IEB.B0PCR
+#define IEBB0BSR IEB.B0BSR
+#define IEBB0SSR IEB.B0SSR
+#define IEBB0USR IEB.B0USR
+#define IEBB0ISR IEB.B0ISR
+#define IEBB0ESR IEB.B0ESR
+#define IEBB0FSR IEB.B0FSR
+#define IEBB0SCR IEB.B0SCR
+#define IEBB0CCR IEB.B0CCR
+#define IEBB0STC0 IEB.B0STC0
+#define IEBB0STC1 IEB.B0STC1
+#define IEBB0DR IEB.B0DR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h
new file mode 100644
index 000000000..f8175a697
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h
@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : inb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INB_IODEFINE_H
+#define INB_IODEFINE_H
+
+struct st_inb
+{ /* INB */
+ volatile uint32_t RMPR; /* RMPR */
+#define INB_AXIBUSCTLn_COUNT 11
+ volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
+ volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
+ volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
+ volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
+ volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
+ volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
+ volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
+ volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
+ volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
+ volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
+ volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
+#define INB_AXIRERRCTLn_COUNT 4
+ volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
+ volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
+ volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
+ volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
+#define INB_AXIRERRSTn_COUNT 4
+ volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
+ volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
+ volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
+ volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
+#define INB_AXIRERRCLRn_COUNT 4
+ volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
+ volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
+ volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
+ volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
+};
+
+
+#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR INB.RMPR
+#define INBAXIBUSCTL0 INB.AXIBUSCTL0
+#define INBAXIBUSCTL1 INB.AXIBUSCTL1
+#define INBAXIBUSCTL2 INB.AXIBUSCTL2
+#define INBAXIBUSCTL3 INB.AXIBUSCTL3
+#define INBAXIBUSCTL4 INB.AXIBUSCTL4
+#define INBAXIBUSCTL5 INB.AXIBUSCTL5
+#define INBAXIBUSCTL6 INB.AXIBUSCTL6
+#define INBAXIBUSCTL7 INB.AXIBUSCTL7
+#define INBAXIBUSCTL8 INB.AXIBUSCTL8
+#define INBAXIBUSCTL9 INB.AXIBUSCTL9
+#define INBAXIBUSCTL10 INB.AXIBUSCTL10
+#define INBAXIRERRCTL0 INB.AXIRERRCTL0
+#define INBAXIRERRCTL1 INB.AXIRERRCTL1
+#define INBAXIRERRCTL2 INB.AXIRERRCTL2
+#define INBAXIRERRCTL3 INB.AXIRERRCTL3
+#define INBAXIRERRST0 INB.AXIRERRST0
+#define INBAXIRERRST1 INB.AXIRERRST1
+#define INBAXIRERRST2 INB.AXIRERRST2
+#define INBAXIRERRST3 INB.AXIRERRST3
+#define INBAXIRERRCLR0 INB.AXIRERRCLR0
+#define INBAXIRERRCLR1 INB.AXIRERRCLR1
+#define INBAXIRERRCLR2 INB.AXIRERRCLR2
+#define INBAXIRERRCLR3 INB.AXIRERRCLR3
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h
new file mode 100644
index 000000000..253d4b939
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h
@@ -0,0 +1,1026 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INTC_IODEFINE_H
+#define INTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_intc
+{ /* INTC */
+ volatile uint32_t ICDDCR; /* ICDDCR */
+ volatile uint32_t ICDICTR; /* ICDICTR */
+ volatile uint32_t ICDIIDR; /* ICDIIDR */
+ volatile uint8_t dummy193[116]; /* */
+#define INTC_ICDISR0_COUNT 19
+ volatile uint32_t ICDISR0; /* ICDISR0 */
+ volatile uint32_t ICDISR1; /* ICDISR1 */
+ volatile uint32_t ICDISR2; /* ICDISR2 */
+ volatile uint32_t ICDISR3; /* ICDISR3 */
+ volatile uint32_t ICDISR4; /* ICDISR4 */
+ volatile uint32_t ICDISR5; /* ICDISR5 */
+ volatile uint32_t ICDISR6; /* ICDISR6 */
+ volatile uint32_t ICDISR7; /* ICDISR7 */
+ volatile uint32_t ICDISR8; /* ICDISR8 */
+ volatile uint32_t ICDISR9; /* ICDISR9 */
+ volatile uint32_t ICDISR10; /* ICDISR10 */
+ volatile uint32_t ICDISR11; /* ICDISR11 */
+ volatile uint32_t ICDISR12; /* ICDISR12 */
+ volatile uint32_t ICDISR13; /* ICDISR13 */
+ volatile uint32_t ICDISR14; /* ICDISR14 */
+ volatile uint32_t ICDISR15; /* ICDISR15 */
+ volatile uint32_t ICDISR16; /* ICDISR16 */
+ volatile uint32_t ICDISR17; /* ICDISR17 */
+ volatile uint32_t ICDISR18; /* ICDISR18 */
+ volatile uint8_t dummy194[52]; /* */
+#define INTC_ICDISER0_COUNT 19
+ volatile uint32_t ICDISER0; /* ICDISER0 */
+ volatile uint32_t ICDISER1; /* ICDISER1 */
+ volatile uint32_t ICDISER2; /* ICDISER2 */
+ volatile uint32_t ICDISER3; /* ICDISER3 */
+ volatile uint32_t ICDISER4; /* ICDISER4 */
+ volatile uint32_t ICDISER5; /* ICDISER5 */
+ volatile uint32_t ICDISER6; /* ICDISER6 */
+ volatile uint32_t ICDISER7; /* ICDISER7 */
+ volatile uint32_t ICDISER8; /* ICDISER8 */
+ volatile uint32_t ICDISER9; /* ICDISER9 */
+ volatile uint32_t ICDISER10; /* ICDISER10 */
+ volatile uint32_t ICDISER11; /* ICDISER11 */
+ volatile uint32_t ICDISER12; /* ICDISER12 */
+ volatile uint32_t ICDISER13; /* ICDISER13 */
+ volatile uint32_t ICDISER14; /* ICDISER14 */
+ volatile uint32_t ICDISER15; /* ICDISER15 */
+ volatile uint32_t ICDISER16; /* ICDISER16 */
+ volatile uint32_t ICDISER17; /* ICDISER17 */
+ volatile uint32_t ICDISER18; /* ICDISER18 */
+ volatile uint8_t dummy195[52]; /* */
+#define INTC_ICDICER0_COUNT 19
+ volatile uint32_t ICDICER0; /* ICDICER0 */
+ volatile uint32_t ICDICER1; /* ICDICER1 */
+ volatile uint32_t ICDICER2; /* ICDICER2 */
+ volatile uint32_t ICDICER3; /* ICDICER3 */
+ volatile uint32_t ICDICER4; /* ICDICER4 */
+ volatile uint32_t ICDICER5; /* ICDICER5 */
+ volatile uint32_t ICDICER6; /* ICDICER6 */
+ volatile uint32_t ICDICER7; /* ICDICER7 */
+ volatile uint32_t ICDICER8; /* ICDICER8 */
+ volatile uint32_t ICDICER9; /* ICDICER9 */
+ volatile uint32_t ICDICER10; /* ICDICER10 */
+ volatile uint32_t ICDICER11; /* ICDICER11 */
+ volatile uint32_t ICDICER12; /* ICDICER12 */
+ volatile uint32_t ICDICER13; /* ICDICER13 */
+ volatile uint32_t ICDICER14; /* ICDICER14 */
+ volatile uint32_t ICDICER15; /* ICDICER15 */
+ volatile uint32_t ICDICER16; /* ICDICER16 */
+ volatile uint32_t ICDICER17; /* ICDICER17 */
+ volatile uint32_t ICDICER18; /* ICDICER18 */
+ volatile uint8_t dummy196[52]; /* */
+#define INTC_ICDISPR0_COUNT 19
+ volatile uint32_t ICDISPR0; /* ICDISPR0 */
+ volatile uint32_t ICDISPR1; /* ICDISPR1 */
+ volatile uint32_t ICDISPR2; /* ICDISPR2 */
+ volatile uint32_t ICDISPR3; /* ICDISPR3 */
+ volatile uint32_t ICDISPR4; /* ICDISPR4 */
+ volatile uint32_t ICDISPR5; /* ICDISPR5 */
+ volatile uint32_t ICDISPR6; /* ICDISPR6 */
+ volatile uint32_t ICDISPR7; /* ICDISPR7 */
+ volatile uint32_t ICDISPR8; /* ICDISPR8 */
+ volatile uint32_t ICDISPR9; /* ICDISPR9 */
+ volatile uint32_t ICDISPR10; /* ICDISPR10 */
+ volatile uint32_t ICDISPR11; /* ICDISPR11 */
+ volatile uint32_t ICDISPR12; /* ICDISPR12 */
+ volatile uint32_t ICDISPR13; /* ICDISPR13 */
+ volatile uint32_t ICDISPR14; /* ICDISPR14 */
+ volatile uint32_t ICDISPR15; /* ICDISPR15 */
+ volatile uint32_t ICDISPR16; /* ICDISPR16 */
+ volatile uint32_t ICDISPR17; /* ICDISPR17 */
+ volatile uint32_t ICDISPR18; /* ICDISPR18 */
+ volatile uint8_t dummy197[52]; /* */
+#define INTC_ICDICPR0_COUNT 19
+ volatile uint32_t ICDICPR0; /* ICDICPR0 */
+ volatile uint32_t ICDICPR1; /* ICDICPR1 */
+ volatile uint32_t ICDICPR2; /* ICDICPR2 */
+ volatile uint32_t ICDICPR3; /* ICDICPR3 */
+ volatile uint32_t ICDICPR4; /* ICDICPR4 */
+ volatile uint32_t ICDICPR5; /* ICDICPR5 */
+ volatile uint32_t ICDICPR6; /* ICDICPR6 */
+ volatile uint32_t ICDICPR7; /* ICDICPR7 */
+ volatile uint32_t ICDICPR8; /* ICDICPR8 */
+ volatile uint32_t ICDICPR9; /* ICDICPR9 */
+ volatile uint32_t ICDICPR10; /* ICDICPR10 */
+ volatile uint32_t ICDICPR11; /* ICDICPR11 */
+ volatile uint32_t ICDICPR12; /* ICDICPR12 */
+ volatile uint32_t ICDICPR13; /* ICDICPR13 */
+ volatile uint32_t ICDICPR14; /* ICDICPR14 */
+ volatile uint32_t ICDICPR15; /* ICDICPR15 */
+ volatile uint32_t ICDICPR16; /* ICDICPR16 */
+ volatile uint32_t ICDICPR17; /* ICDICPR17 */
+ volatile uint32_t ICDICPR18; /* ICDICPR18 */
+ volatile uint8_t dummy198[52]; /* */
+#define INTC_ICDABR0_COUNT 19
+ volatile uint32_t ICDABR0; /* ICDABR0 */
+ volatile uint32_t ICDABR1; /* ICDABR1 */
+ volatile uint32_t ICDABR2; /* ICDABR2 */
+ volatile uint32_t ICDABR3; /* ICDABR3 */
+ volatile uint32_t ICDABR4; /* ICDABR4 */
+ volatile uint32_t ICDABR5; /* ICDABR5 */
+ volatile uint32_t ICDABR6; /* ICDABR6 */
+ volatile uint32_t ICDABR7; /* ICDABR7 */
+ volatile uint32_t ICDABR8; /* ICDABR8 */
+ volatile uint32_t ICDABR9; /* ICDABR9 */
+ volatile uint32_t ICDABR10; /* ICDABR10 */
+ volatile uint32_t ICDABR11; /* ICDABR11 */
+ volatile uint32_t ICDABR12; /* ICDABR12 */
+ volatile uint32_t ICDABR13; /* ICDABR13 */
+ volatile uint32_t ICDABR14; /* ICDABR14 */
+ volatile uint32_t ICDABR15; /* ICDABR15 */
+ volatile uint32_t ICDABR16; /* ICDABR16 */
+ volatile uint32_t ICDABR17; /* ICDABR17 */
+ volatile uint32_t ICDABR18; /* ICDABR18 */
+ volatile uint8_t dummy199[180]; /* */
+#define INTC_ICDIPR0_COUNT 147
+ volatile uint32_t ICDIPR0; /* ICDIPR0 */
+ volatile uint32_t ICDIPR1; /* ICDIPR1 */
+ volatile uint32_t ICDIPR2; /* ICDIPR2 */
+ volatile uint32_t ICDIPR3; /* ICDIPR3 */
+ volatile uint32_t ICDIPR4; /* ICDIPR4 */
+ volatile uint32_t ICDIPR5; /* ICDIPR5 */
+ volatile uint32_t ICDIPR6; /* ICDIPR6 */
+ volatile uint32_t ICDIPR7; /* ICDIPR7 */
+ volatile uint32_t ICDIPR8; /* ICDIPR8 */
+ volatile uint32_t ICDIPR9; /* ICDIPR9 */
+ volatile uint32_t ICDIPR10; /* ICDIPR10 */
+ volatile uint32_t ICDIPR11; /* ICDIPR11 */
+ volatile uint32_t ICDIPR12; /* ICDIPR12 */
+ volatile uint32_t ICDIPR13; /* ICDIPR13 */
+ volatile uint32_t ICDIPR14; /* ICDIPR14 */
+ volatile uint32_t ICDIPR15; /* ICDIPR15 */
+ volatile uint32_t ICDIPR16; /* ICDIPR16 */
+ volatile uint32_t ICDIPR17; /* ICDIPR17 */
+ volatile uint32_t ICDIPR18; /* ICDIPR18 */
+ volatile uint32_t ICDIPR19; /* ICDIPR19 */
+ volatile uint32_t ICDIPR20; /* ICDIPR20 */
+ volatile uint32_t ICDIPR21; /* ICDIPR21 */
+ volatile uint32_t ICDIPR22; /* ICDIPR22 */
+ volatile uint32_t ICDIPR23; /* ICDIPR23 */
+ volatile uint32_t ICDIPR24; /* ICDIPR24 */
+ volatile uint32_t ICDIPR25; /* ICDIPR25 */
+ volatile uint32_t ICDIPR26; /* ICDIPR26 */
+ volatile uint32_t ICDIPR27; /* ICDIPR27 */
+ volatile uint32_t ICDIPR28; /* ICDIPR28 */
+ volatile uint32_t ICDIPR29; /* ICDIPR29 */
+ volatile uint32_t ICDIPR30; /* ICDIPR30 */
+ volatile uint32_t ICDIPR31; /* ICDIPR31 */
+ volatile uint32_t ICDIPR32; /* ICDIPR32 */
+ volatile uint32_t ICDIPR33; /* ICDIPR33 */
+ volatile uint32_t ICDIPR34; /* ICDIPR34 */
+ volatile uint32_t ICDIPR35; /* ICDIPR35 */
+ volatile uint32_t ICDIPR36; /* ICDIPR36 */
+ volatile uint32_t ICDIPR37; /* ICDIPR37 */
+ volatile uint32_t ICDIPR38; /* ICDIPR38 */
+ volatile uint32_t ICDIPR39; /* ICDIPR39 */
+ volatile uint32_t ICDIPR40; /* ICDIPR40 */
+ volatile uint32_t ICDIPR41; /* ICDIPR41 */
+ volatile uint32_t ICDIPR42; /* ICDIPR42 */
+ volatile uint32_t ICDIPR43; /* ICDIPR43 */
+ volatile uint32_t ICDIPR44; /* ICDIPR44 */
+ volatile uint32_t ICDIPR45; /* ICDIPR45 */
+ volatile uint32_t ICDIPR46; /* ICDIPR46 */
+ volatile uint32_t ICDIPR47; /* ICDIPR47 */
+ volatile uint32_t ICDIPR48; /* ICDIPR48 */
+ volatile uint32_t ICDIPR49; /* ICDIPR49 */
+ volatile uint32_t ICDIPR50; /* ICDIPR50 */
+ volatile uint32_t ICDIPR51; /* ICDIPR51 */
+ volatile uint32_t ICDIPR52; /* ICDIPR52 */
+ volatile uint32_t ICDIPR53; /* ICDIPR53 */
+ volatile uint32_t ICDIPR54; /* ICDIPR54 */
+ volatile uint32_t ICDIPR55; /* ICDIPR55 */
+ volatile uint32_t ICDIPR56; /* ICDIPR56 */
+ volatile uint32_t ICDIPR57; /* ICDIPR57 */
+ volatile uint32_t ICDIPR58; /* ICDIPR58 */
+ volatile uint32_t ICDIPR59; /* ICDIPR59 */
+ volatile uint32_t ICDIPR60; /* ICDIPR60 */
+ volatile uint32_t ICDIPR61; /* ICDIPR61 */
+ volatile uint32_t ICDIPR62; /* ICDIPR62 */
+ volatile uint32_t ICDIPR63; /* ICDIPR63 */
+ volatile uint32_t ICDIPR64; /* ICDIPR64 */
+ volatile uint32_t ICDIPR65; /* ICDIPR65 */
+ volatile uint32_t ICDIPR66; /* ICDIPR66 */
+ volatile uint32_t ICDIPR67; /* ICDIPR67 */
+ volatile uint32_t ICDIPR68; /* ICDIPR68 */
+ volatile uint32_t ICDIPR69; /* ICDIPR69 */
+ volatile uint32_t ICDIPR70; /* ICDIPR70 */
+ volatile uint32_t ICDIPR71; /* ICDIPR71 */
+ volatile uint32_t ICDIPR72; /* ICDIPR72 */
+ volatile uint32_t ICDIPR73; /* ICDIPR73 */
+ volatile uint32_t ICDIPR74; /* ICDIPR74 */
+ volatile uint32_t ICDIPR75; /* ICDIPR75 */
+ volatile uint32_t ICDIPR76; /* ICDIPR76 */
+ volatile uint32_t ICDIPR77; /* ICDIPR77 */
+ volatile uint32_t ICDIPR78; /* ICDIPR78 */
+ volatile uint32_t ICDIPR79; /* ICDIPR79 */
+ volatile uint32_t ICDIPR80; /* ICDIPR80 */
+ volatile uint32_t ICDIPR81; /* ICDIPR81 */
+ volatile uint32_t ICDIPR82; /* ICDIPR82 */
+ volatile uint32_t ICDIPR83; /* ICDIPR83 */
+ volatile uint32_t ICDIPR84; /* ICDIPR84 */
+ volatile uint32_t ICDIPR85; /* ICDIPR85 */
+ volatile uint32_t ICDIPR86; /* ICDIPR86 */
+ volatile uint32_t ICDIPR87; /* ICDIPR87 */
+ volatile uint32_t ICDIPR88; /* ICDIPR88 */
+ volatile uint32_t ICDIPR89; /* ICDIPR89 */
+ volatile uint32_t ICDIPR90; /* ICDIPR90 */
+ volatile uint32_t ICDIPR91; /* ICDIPR91 */
+ volatile uint32_t ICDIPR92; /* ICDIPR92 */
+ volatile uint32_t ICDIPR93; /* ICDIPR93 */
+ volatile uint32_t ICDIPR94; /* ICDIPR94 */
+ volatile uint32_t ICDIPR95; /* ICDIPR95 */
+ volatile uint32_t ICDIPR96; /* ICDIPR96 */
+ volatile uint32_t ICDIPR97; /* ICDIPR97 */
+ volatile uint32_t ICDIPR98; /* ICDIPR98 */
+ volatile uint32_t ICDIPR99; /* ICDIPR99 */
+ volatile uint32_t ICDIPR100; /* ICDIPR100 */
+ volatile uint32_t ICDIPR101; /* ICDIPR101 */
+ volatile uint32_t ICDIPR102; /* ICDIPR102 */
+ volatile uint32_t ICDIPR103; /* ICDIPR103 */
+ volatile uint32_t ICDIPR104; /* ICDIPR104 */
+ volatile uint32_t ICDIPR105; /* ICDIPR105 */
+ volatile uint32_t ICDIPR106; /* ICDIPR106 */
+ volatile uint32_t ICDIPR107; /* ICDIPR107 */
+ volatile uint32_t ICDIPR108; /* ICDIPR108 */
+ volatile uint32_t ICDIPR109; /* ICDIPR109 */
+ volatile uint32_t ICDIPR110; /* ICDIPR110 */
+ volatile uint32_t ICDIPR111; /* ICDIPR111 */
+ volatile uint32_t ICDIPR112; /* ICDIPR112 */
+ volatile uint32_t ICDIPR113; /* ICDIPR113 */
+ volatile uint32_t ICDIPR114; /* ICDIPR114 */
+ volatile uint32_t ICDIPR115; /* ICDIPR115 */
+ volatile uint32_t ICDIPR116; /* ICDIPR116 */
+ volatile uint32_t ICDIPR117; /* ICDIPR117 */
+ volatile uint32_t ICDIPR118; /* ICDIPR118 */
+ volatile uint32_t ICDIPR119; /* ICDIPR119 */
+ volatile uint32_t ICDIPR120; /* ICDIPR120 */
+ volatile uint32_t ICDIPR121; /* ICDIPR121 */
+ volatile uint32_t ICDIPR122; /* ICDIPR122 */
+ volatile uint32_t ICDIPR123; /* ICDIPR123 */
+ volatile uint32_t ICDIPR124; /* ICDIPR124 */
+ volatile uint32_t ICDIPR125; /* ICDIPR125 */
+ volatile uint32_t ICDIPR126; /* ICDIPR126 */
+ volatile uint32_t ICDIPR127; /* ICDIPR127 */
+ volatile uint32_t ICDIPR128; /* ICDIPR128 */
+ volatile uint32_t ICDIPR129; /* ICDIPR129 */
+ volatile uint32_t ICDIPR130; /* ICDIPR130 */
+ volatile uint32_t ICDIPR131; /* ICDIPR131 */
+ volatile uint32_t ICDIPR132; /* ICDIPR132 */
+ volatile uint32_t ICDIPR133; /* ICDIPR133 */
+ volatile uint32_t ICDIPR134; /* ICDIPR134 */
+ volatile uint32_t ICDIPR135; /* ICDIPR135 */
+ volatile uint32_t ICDIPR136; /* ICDIPR136 */
+ volatile uint32_t ICDIPR137; /* ICDIPR137 */
+ volatile uint32_t ICDIPR138; /* ICDIPR138 */
+ volatile uint32_t ICDIPR139; /* ICDIPR139 */
+ volatile uint32_t ICDIPR140; /* ICDIPR140 */
+ volatile uint32_t ICDIPR141; /* ICDIPR141 */
+ volatile uint32_t ICDIPR142; /* ICDIPR142 */
+ volatile uint32_t ICDIPR143; /* ICDIPR143 */
+ volatile uint32_t ICDIPR144; /* ICDIPR144 */
+ volatile uint32_t ICDIPR145; /* ICDIPR145 */
+ volatile uint32_t ICDIPR146; /* ICDIPR146 */
+ volatile uint8_t dummy200[436]; /* */
+#define INTC_ICDIPTR0_COUNT 147
+ volatile uint32_t ICDIPTR0; /* ICDIPTR0 */
+ volatile uint32_t ICDIPTR1; /* ICDIPTR1 */
+ volatile uint32_t ICDIPTR2; /* ICDIPTR2 */
+ volatile uint32_t ICDIPTR3; /* ICDIPTR3 */
+ volatile uint32_t ICDIPTR4; /* ICDIPTR4 */
+ volatile uint32_t ICDIPTR5; /* ICDIPTR5 */
+ volatile uint32_t ICDIPTR6; /* ICDIPTR6 */
+ volatile uint32_t ICDIPTR7; /* ICDIPTR7 */
+ volatile uint32_t ICDIPTR8; /* ICDIPTR8 */
+ volatile uint32_t ICDIPTR9; /* ICDIPTR9 */
+ volatile uint32_t ICDIPTR10; /* ICDIPTR10 */
+ volatile uint32_t ICDIPTR11; /* ICDIPTR11 */
+ volatile uint32_t ICDIPTR12; /* ICDIPTR12 */
+ volatile uint32_t ICDIPTR13; /* ICDIPTR13 */
+ volatile uint32_t ICDIPTR14; /* ICDIPTR14 */
+ volatile uint32_t ICDIPTR15; /* ICDIPTR15 */
+ volatile uint32_t ICDIPTR16; /* ICDIPTR16 */
+ volatile uint32_t ICDIPTR17; /* ICDIPTR17 */
+ volatile uint32_t ICDIPTR18; /* ICDIPTR18 */
+ volatile uint32_t ICDIPTR19; /* ICDIPTR19 */
+ volatile uint32_t ICDIPTR20; /* ICDIPTR20 */
+ volatile uint32_t ICDIPTR21; /* ICDIPTR21 */
+ volatile uint32_t ICDIPTR22; /* ICDIPTR22 */
+ volatile uint32_t ICDIPTR23; /* ICDIPTR23 */
+ volatile uint32_t ICDIPTR24; /* ICDIPTR24 */
+ volatile uint32_t ICDIPTR25; /* ICDIPTR25 */
+ volatile uint32_t ICDIPTR26; /* ICDIPTR26 */
+ volatile uint32_t ICDIPTR27; /* ICDIPTR27 */
+ volatile uint32_t ICDIPTR28; /* ICDIPTR28 */
+ volatile uint32_t ICDIPTR29; /* ICDIPTR29 */
+ volatile uint32_t ICDIPTR30; /* ICDIPTR30 */
+ volatile uint32_t ICDIPTR31; /* ICDIPTR31 */
+ volatile uint32_t ICDIPTR32; /* ICDIPTR32 */
+ volatile uint32_t ICDIPTR33; /* ICDIPTR33 */
+ volatile uint32_t ICDIPTR34; /* ICDIPTR34 */
+ volatile uint32_t ICDIPTR35; /* ICDIPTR35 */
+ volatile uint32_t ICDIPTR36; /* ICDIPTR36 */
+ volatile uint32_t ICDIPTR37; /* ICDIPTR37 */
+ volatile uint32_t ICDIPTR38; /* ICDIPTR38 */
+ volatile uint32_t ICDIPTR39; /* ICDIPTR39 */
+ volatile uint32_t ICDIPTR40; /* ICDIPTR40 */
+ volatile uint32_t ICDIPTR41; /* ICDIPTR41 */
+ volatile uint32_t ICDIPTR42; /* ICDIPTR42 */
+ volatile uint32_t ICDIPTR43; /* ICDIPTR43 */
+ volatile uint32_t ICDIPTR44; /* ICDIPTR44 */
+ volatile uint32_t ICDIPTR45; /* ICDIPTR45 */
+ volatile uint32_t ICDIPTR46; /* ICDIPTR46 */
+ volatile uint32_t ICDIPTR47; /* ICDIPTR47 */
+ volatile uint32_t ICDIPTR48; /* ICDIPTR48 */
+ volatile uint32_t ICDIPTR49; /* ICDIPTR49 */
+ volatile uint32_t ICDIPTR50; /* ICDIPTR50 */
+ volatile uint32_t ICDIPTR51; /* ICDIPTR51 */
+ volatile uint32_t ICDIPTR52; /* ICDIPTR52 */
+ volatile uint32_t ICDIPTR53; /* ICDIPTR53 */
+ volatile uint32_t ICDIPTR54; /* ICDIPTR54 */
+ volatile uint32_t ICDIPTR55; /* ICDIPTR55 */
+ volatile uint32_t ICDIPTR56; /* ICDIPTR56 */
+ volatile uint32_t ICDIPTR57; /* ICDIPTR57 */
+ volatile uint32_t ICDIPTR58; /* ICDIPTR58 */
+ volatile uint32_t ICDIPTR59; /* ICDIPTR59 */
+ volatile uint32_t ICDIPTR60; /* ICDIPTR60 */
+ volatile uint32_t ICDIPTR61; /* ICDIPTR61 */
+ volatile uint32_t ICDIPTR62; /* ICDIPTR62 */
+ volatile uint32_t ICDIPTR63; /* ICDIPTR63 */
+ volatile uint32_t ICDIPTR64; /* ICDIPTR64 */
+ volatile uint32_t ICDIPTR65; /* ICDIPTR65 */
+ volatile uint32_t ICDIPTR66; /* ICDIPTR66 */
+ volatile uint32_t ICDIPTR67; /* ICDIPTR67 */
+ volatile uint32_t ICDIPTR68; /* ICDIPTR68 */
+ volatile uint32_t ICDIPTR69; /* ICDIPTR69 */
+ volatile uint32_t ICDIPTR70; /* ICDIPTR70 */
+ volatile uint32_t ICDIPTR71; /* ICDIPTR71 */
+ volatile uint32_t ICDIPTR72; /* ICDIPTR72 */
+ volatile uint32_t ICDIPTR73; /* ICDIPTR73 */
+ volatile uint32_t ICDIPTR74; /* ICDIPTR74 */
+ volatile uint32_t ICDIPTR75; /* ICDIPTR75 */
+ volatile uint32_t ICDIPTR76; /* ICDIPTR76 */
+ volatile uint32_t ICDIPTR77; /* ICDIPTR77 */
+ volatile uint32_t ICDIPTR78; /* ICDIPTR78 */
+ volatile uint32_t ICDIPTR79; /* ICDIPTR79 */
+ volatile uint32_t ICDIPTR80; /* ICDIPTR80 */
+ volatile uint32_t ICDIPTR81; /* ICDIPTR81 */
+ volatile uint32_t ICDIPTR82; /* ICDIPTR82 */
+ volatile uint32_t ICDIPTR83; /* ICDIPTR83 */
+ volatile uint32_t ICDIPTR84; /* ICDIPTR84 */
+ volatile uint32_t ICDIPTR85; /* ICDIPTR85 */
+ volatile uint32_t ICDIPTR86; /* ICDIPTR86 */
+ volatile uint32_t ICDIPTR87; /* ICDIPTR87 */
+ volatile uint32_t ICDIPTR88; /* ICDIPTR88 */
+ volatile uint32_t ICDIPTR89; /* ICDIPTR89 */
+ volatile uint32_t ICDIPTR90; /* ICDIPTR90 */
+ volatile uint32_t ICDIPTR91; /* ICDIPTR91 */
+ volatile uint32_t ICDIPTR92; /* ICDIPTR92 */
+ volatile uint32_t ICDIPTR93; /* ICDIPTR93 */
+ volatile uint32_t ICDIPTR94; /* ICDIPTR94 */
+ volatile uint32_t ICDIPTR95; /* ICDIPTR95 */
+ volatile uint32_t ICDIPTR96; /* ICDIPTR96 */
+ volatile uint32_t ICDIPTR97; /* ICDIPTR97 */
+ volatile uint32_t ICDIPTR98; /* ICDIPTR98 */
+ volatile uint32_t ICDIPTR99; /* ICDIPTR99 */
+ volatile uint32_t ICDIPTR100; /* ICDIPTR100 */
+ volatile uint32_t ICDIPTR101; /* ICDIPTR101 */
+ volatile uint32_t ICDIPTR102; /* ICDIPTR102 */
+ volatile uint32_t ICDIPTR103; /* ICDIPTR103 */
+ volatile uint32_t ICDIPTR104; /* ICDIPTR104 */
+ volatile uint32_t ICDIPTR105; /* ICDIPTR105 */
+ volatile uint32_t ICDIPTR106; /* ICDIPTR106 */
+ volatile uint32_t ICDIPTR107; /* ICDIPTR107 */
+ volatile uint32_t ICDIPTR108; /* ICDIPTR108 */
+ volatile uint32_t ICDIPTR109; /* ICDIPTR109 */
+ volatile uint32_t ICDIPTR110; /* ICDIPTR110 */
+ volatile uint32_t ICDIPTR111; /* ICDIPTR111 */
+ volatile uint32_t ICDIPTR112; /* ICDIPTR112 */
+ volatile uint32_t ICDIPTR113; /* ICDIPTR113 */
+ volatile uint32_t ICDIPTR114; /* ICDIPTR114 */
+ volatile uint32_t ICDIPTR115; /* ICDIPTR115 */
+ volatile uint32_t ICDIPTR116; /* ICDIPTR116 */
+ volatile uint32_t ICDIPTR117; /* ICDIPTR117 */
+ volatile uint32_t ICDIPTR118; /* ICDIPTR118 */
+ volatile uint32_t ICDIPTR119; /* ICDIPTR119 */
+ volatile uint32_t ICDIPTR120; /* ICDIPTR120 */
+ volatile uint32_t ICDIPTR121; /* ICDIPTR121 */
+ volatile uint32_t ICDIPTR122; /* ICDIPTR122 */
+ volatile uint32_t ICDIPTR123; /* ICDIPTR123 */
+ volatile uint32_t ICDIPTR124; /* ICDIPTR124 */
+ volatile uint32_t ICDIPTR125; /* ICDIPTR125 */
+ volatile uint32_t ICDIPTR126; /* ICDIPTR126 */
+ volatile uint32_t ICDIPTR127; /* ICDIPTR127 */
+ volatile uint32_t ICDIPTR128; /* ICDIPTR128 */
+ volatile uint32_t ICDIPTR129; /* ICDIPTR129 */
+ volatile uint32_t ICDIPTR130; /* ICDIPTR130 */
+ volatile uint32_t ICDIPTR131; /* ICDIPTR131 */
+ volatile uint32_t ICDIPTR132; /* ICDIPTR132 */
+ volatile uint32_t ICDIPTR133; /* ICDIPTR133 */
+ volatile uint32_t ICDIPTR134; /* ICDIPTR134 */
+ volatile uint32_t ICDIPTR135; /* ICDIPTR135 */
+ volatile uint32_t ICDIPTR136; /* ICDIPTR136 */
+ volatile uint32_t ICDIPTR137; /* ICDIPTR137 */
+ volatile uint32_t ICDIPTR138; /* ICDIPTR138 */
+ volatile uint32_t ICDIPTR139; /* ICDIPTR139 */
+ volatile uint32_t ICDIPTR140; /* ICDIPTR140 */
+ volatile uint32_t ICDIPTR141; /* ICDIPTR141 */
+ volatile uint32_t ICDIPTR142; /* ICDIPTR142 */
+ volatile uint32_t ICDIPTR143; /* ICDIPTR143 */
+ volatile uint32_t ICDIPTR144; /* ICDIPTR144 */
+ volatile uint32_t ICDIPTR145; /* ICDIPTR145 */
+ volatile uint32_t ICDIPTR146; /* ICDIPTR146 */
+ volatile uint8_t dummy201[436]; /* */
+#define INTC_ICDICFR0_COUNT 37
+ volatile uint32_t ICDICFR0; /* ICDICFR0 */
+ volatile uint32_t ICDICFR1; /* ICDICFR1 */
+ volatile uint32_t ICDICFR2; /* ICDICFR2 */
+ volatile uint32_t ICDICFR3; /* ICDICFR3 */
+ volatile uint32_t ICDICFR4; /* ICDICFR4 */
+ volatile uint32_t ICDICFR5; /* ICDICFR5 */
+ volatile uint32_t ICDICFR6; /* ICDICFR6 */
+ volatile uint32_t ICDICFR7; /* ICDICFR7 */
+ volatile uint32_t ICDICFR8; /* ICDICFR8 */
+ volatile uint32_t ICDICFR9; /* ICDICFR9 */
+ volatile uint32_t ICDICFR10; /* ICDICFR10 */
+ volatile uint32_t ICDICFR11; /* ICDICFR11 */
+ volatile uint32_t ICDICFR12; /* ICDICFR12 */
+ volatile uint32_t ICDICFR13; /* ICDICFR13 */
+ volatile uint32_t ICDICFR14; /* ICDICFR14 */
+ volatile uint32_t ICDICFR15; /* ICDICFR15 */
+ volatile uint32_t ICDICFR16; /* ICDICFR16 */
+ volatile uint32_t ICDICFR17; /* ICDICFR17 */
+ volatile uint32_t ICDICFR18; /* ICDICFR18 */
+ volatile uint32_t ICDICFR19; /* ICDICFR19 */
+ volatile uint32_t ICDICFR20; /* ICDICFR20 */
+ volatile uint32_t ICDICFR21; /* ICDICFR21 */
+ volatile uint32_t ICDICFR22; /* ICDICFR22 */
+ volatile uint32_t ICDICFR23; /* ICDICFR23 */
+ volatile uint32_t ICDICFR24; /* ICDICFR24 */
+ volatile uint32_t ICDICFR25; /* ICDICFR25 */
+ volatile uint32_t ICDICFR26; /* ICDICFR26 */
+ volatile uint32_t ICDICFR27; /* ICDICFR27 */
+ volatile uint32_t ICDICFR28; /* ICDICFR28 */
+ volatile uint32_t ICDICFR29; /* ICDICFR29 */
+ volatile uint32_t ICDICFR30; /* ICDICFR30 */
+ volatile uint32_t ICDICFR31; /* ICDICFR31 */
+ volatile uint32_t ICDICFR32; /* ICDICFR32 */
+ volatile uint32_t ICDICFR33; /* ICDICFR33 */
+ volatile uint32_t ICDICFR34; /* ICDICFR34 */
+ volatile uint32_t ICDICFR35; /* ICDICFR35 */
+ volatile uint32_t ICDICFR36; /* ICDICFR36 */
+ volatile uint8_t dummy202[108]; /* */
+ volatile uint32_t PPI_STATUS; /* PPI_STATUS */
+#define INTC_SPI_STATUS0_COUNT 17
+ volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */
+ volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */
+ volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */
+ volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */
+ volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */
+ volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */
+ volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */
+ volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */
+ volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */
+ volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */
+ volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */
+ volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */
+ volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */
+ volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */
+ volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */
+ volatile uint32_t SPI_STATUS15; /* SPI_STATUS15 */
+ volatile uint32_t SPI_STATUS16; /* SPI_STATUS16 */
+ volatile uint8_t dummy203[440]; /* */
+ volatile uint32_t ICDSGIR; /* ICDSGIR */
+ volatile uint8_t dummy204[252]; /* */
+ volatile uint32_t ICCICR; /* ICCICR */
+ volatile uint32_t ICCPMR; /* ICCPMR */
+ volatile uint32_t ICCBPR; /* ICCBPR */
+ volatile uint32_t ICCIAR; /* ICCIAR */
+ volatile uint32_t ICCEOIR; /* ICCEOIR */
+ volatile uint32_t ICCRPR; /* ICCRPR */
+ volatile uint32_t ICCHPIR; /* ICCHPIR */
+ volatile uint32_t ICCABPR; /* ICCABPR */
+ volatile uint8_t dummy205[220]; /* */
+ volatile uint32_t ICCIIDR; /* ICCIIDR */
+ volatile uint8_t dummy206[350148352]; /* */
+ volatile uint16_t ICR0; /* ICR0 */
+ volatile uint16_t ICR1; /* ICR1 */
+ volatile uint16_t IRQRR; /* IRQRR */
+};
+
+
+#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR INTC.ICDDCR
+#define INTCICDICTR INTC.ICDICTR
+#define INTCICDIIDR INTC.ICDIIDR
+#define INTCICDISR0 INTC.ICDISR0
+#define INTCICDISR1 INTC.ICDISR1
+#define INTCICDISR2 INTC.ICDISR2
+#define INTCICDISR3 INTC.ICDISR3
+#define INTCICDISR4 INTC.ICDISR4
+#define INTCICDISR5 INTC.ICDISR5
+#define INTCICDISR6 INTC.ICDISR6
+#define INTCICDISR7 INTC.ICDISR7
+#define INTCICDISR8 INTC.ICDISR8
+#define INTCICDISR9 INTC.ICDISR9
+#define INTCICDISR10 INTC.ICDISR10
+#define INTCICDISR11 INTC.ICDISR11
+#define INTCICDISR12 INTC.ICDISR12
+#define INTCICDISR13 INTC.ICDISR13
+#define INTCICDISR14 INTC.ICDISR14
+#define INTCICDISR15 INTC.ICDISR15
+#define INTCICDISR16 INTC.ICDISR16
+#define INTCICDISR17 INTC.ICDISR17
+#define INTCICDISR18 INTC.ICDISR18
+#define INTCICDISER0 INTC.ICDISER0
+#define INTCICDISER1 INTC.ICDISER1
+#define INTCICDISER2 INTC.ICDISER2
+#define INTCICDISER3 INTC.ICDISER3
+#define INTCICDISER4 INTC.ICDISER4
+#define INTCICDISER5 INTC.ICDISER5
+#define INTCICDISER6 INTC.ICDISER6
+#define INTCICDISER7 INTC.ICDISER7
+#define INTCICDISER8 INTC.ICDISER8
+#define INTCICDISER9 INTC.ICDISER9
+#define INTCICDISER10 INTC.ICDISER10
+#define INTCICDISER11 INTC.ICDISER11
+#define INTCICDISER12 INTC.ICDISER12
+#define INTCICDISER13 INTC.ICDISER13
+#define INTCICDISER14 INTC.ICDISER14
+#define INTCICDISER15 INTC.ICDISER15
+#define INTCICDISER16 INTC.ICDISER16
+#define INTCICDISER17 INTC.ICDISER17
+#define INTCICDISER18 INTC.ICDISER18
+#define INTCICDICER0 INTC.ICDICER0
+#define INTCICDICER1 INTC.ICDICER1
+#define INTCICDICER2 INTC.ICDICER2
+#define INTCICDICER3 INTC.ICDICER3
+#define INTCICDICER4 INTC.ICDICER4
+#define INTCICDICER5 INTC.ICDICER5
+#define INTCICDICER6 INTC.ICDICER6
+#define INTCICDICER7 INTC.ICDICER7
+#define INTCICDICER8 INTC.ICDICER8
+#define INTCICDICER9 INTC.ICDICER9
+#define INTCICDICER10 INTC.ICDICER10
+#define INTCICDICER11 INTC.ICDICER11
+#define INTCICDICER12 INTC.ICDICER12
+#define INTCICDICER13 INTC.ICDICER13
+#define INTCICDICER14 INTC.ICDICER14
+#define INTCICDICER15 INTC.ICDICER15
+#define INTCICDICER16 INTC.ICDICER16
+#define INTCICDICER17 INTC.ICDICER17
+#define INTCICDICER18 INTC.ICDICER18
+#define INTCICDISPR0 INTC.ICDISPR0
+#define INTCICDISPR1 INTC.ICDISPR1
+#define INTCICDISPR2 INTC.ICDISPR2
+#define INTCICDISPR3 INTC.ICDISPR3
+#define INTCICDISPR4 INTC.ICDISPR4
+#define INTCICDISPR5 INTC.ICDISPR5
+#define INTCICDISPR6 INTC.ICDISPR6
+#define INTCICDISPR7 INTC.ICDISPR7
+#define INTCICDISPR8 INTC.ICDISPR8
+#define INTCICDISPR9 INTC.ICDISPR9
+#define INTCICDISPR10 INTC.ICDISPR10
+#define INTCICDISPR11 INTC.ICDISPR11
+#define INTCICDISPR12 INTC.ICDISPR12
+#define INTCICDISPR13 INTC.ICDISPR13
+#define INTCICDISPR14 INTC.ICDISPR14
+#define INTCICDISPR15 INTC.ICDISPR15
+#define INTCICDISPR16 INTC.ICDISPR16
+#define INTCICDISPR17 INTC.ICDISPR17
+#define INTCICDISPR18 INTC.ICDISPR18
+#define INTCICDICPR0 INTC.ICDICPR0
+#define INTCICDICPR1 INTC.ICDICPR1
+#define INTCICDICPR2 INTC.ICDICPR2
+#define INTCICDICPR3 INTC.ICDICPR3
+#define INTCICDICPR4 INTC.ICDICPR4
+#define INTCICDICPR5 INTC.ICDICPR5
+#define INTCICDICPR6 INTC.ICDICPR6
+#define INTCICDICPR7 INTC.ICDICPR7
+#define INTCICDICPR8 INTC.ICDICPR8
+#define INTCICDICPR9 INTC.ICDICPR9
+#define INTCICDICPR10 INTC.ICDICPR10
+#define INTCICDICPR11 INTC.ICDICPR11
+#define INTCICDICPR12 INTC.ICDICPR12
+#define INTCICDICPR13 INTC.ICDICPR13
+#define INTCICDICPR14 INTC.ICDICPR14
+#define INTCICDICPR15 INTC.ICDICPR15
+#define INTCICDICPR16 INTC.ICDICPR16
+#define INTCICDICPR17 INTC.ICDICPR17
+#define INTCICDICPR18 INTC.ICDICPR18
+#define INTCICDABR0 INTC.ICDABR0
+#define INTCICDABR1 INTC.ICDABR1
+#define INTCICDABR2 INTC.ICDABR2
+#define INTCICDABR3 INTC.ICDABR3
+#define INTCICDABR4 INTC.ICDABR4
+#define INTCICDABR5 INTC.ICDABR5
+#define INTCICDABR6 INTC.ICDABR6
+#define INTCICDABR7 INTC.ICDABR7
+#define INTCICDABR8 INTC.ICDABR8
+#define INTCICDABR9 INTC.ICDABR9
+#define INTCICDABR10 INTC.ICDABR10
+#define INTCICDABR11 INTC.ICDABR11
+#define INTCICDABR12 INTC.ICDABR12
+#define INTCICDABR13 INTC.ICDABR13
+#define INTCICDABR14 INTC.ICDABR14
+#define INTCICDABR15 INTC.ICDABR15
+#define INTCICDABR16 INTC.ICDABR16
+#define INTCICDABR17 INTC.ICDABR17
+#define INTCICDABR18 INTC.ICDABR18
+#define INTCICDIPR0 INTC.ICDIPR0
+#define INTCICDIPR1 INTC.ICDIPR1
+#define INTCICDIPR2 INTC.ICDIPR2
+#define INTCICDIPR3 INTC.ICDIPR3
+#define INTCICDIPR4 INTC.ICDIPR4
+#define INTCICDIPR5 INTC.ICDIPR5
+#define INTCICDIPR6 INTC.ICDIPR6
+#define INTCICDIPR7 INTC.ICDIPR7
+#define INTCICDIPR8 INTC.ICDIPR8
+#define INTCICDIPR9 INTC.ICDIPR9
+#define INTCICDIPR10 INTC.ICDIPR10
+#define INTCICDIPR11 INTC.ICDIPR11
+#define INTCICDIPR12 INTC.ICDIPR12
+#define INTCICDIPR13 INTC.ICDIPR13
+#define INTCICDIPR14 INTC.ICDIPR14
+#define INTCICDIPR15 INTC.ICDIPR15
+#define INTCICDIPR16 INTC.ICDIPR16
+#define INTCICDIPR17 INTC.ICDIPR17
+#define INTCICDIPR18 INTC.ICDIPR18
+#define INTCICDIPR19 INTC.ICDIPR19
+#define INTCICDIPR20 INTC.ICDIPR20
+#define INTCICDIPR21 INTC.ICDIPR21
+#define INTCICDIPR22 INTC.ICDIPR22
+#define INTCICDIPR23 INTC.ICDIPR23
+#define INTCICDIPR24 INTC.ICDIPR24
+#define INTCICDIPR25 INTC.ICDIPR25
+#define INTCICDIPR26 INTC.ICDIPR26
+#define INTCICDIPR27 INTC.ICDIPR27
+#define INTCICDIPR28 INTC.ICDIPR28
+#define INTCICDIPR29 INTC.ICDIPR29
+#define INTCICDIPR30 INTC.ICDIPR30
+#define INTCICDIPR31 INTC.ICDIPR31
+#define INTCICDIPR32 INTC.ICDIPR32
+#define INTCICDIPR33 INTC.ICDIPR33
+#define INTCICDIPR34 INTC.ICDIPR34
+#define INTCICDIPR35 INTC.ICDIPR35
+#define INTCICDIPR36 INTC.ICDIPR36
+#define INTCICDIPR37 INTC.ICDIPR37
+#define INTCICDIPR38 INTC.ICDIPR38
+#define INTCICDIPR39 INTC.ICDIPR39
+#define INTCICDIPR40 INTC.ICDIPR40
+#define INTCICDIPR41 INTC.ICDIPR41
+#define INTCICDIPR42 INTC.ICDIPR42
+#define INTCICDIPR43 INTC.ICDIPR43
+#define INTCICDIPR44 INTC.ICDIPR44
+#define INTCICDIPR45 INTC.ICDIPR45
+#define INTCICDIPR46 INTC.ICDIPR46
+#define INTCICDIPR47 INTC.ICDIPR47
+#define INTCICDIPR48 INTC.ICDIPR48
+#define INTCICDIPR49 INTC.ICDIPR49
+#define INTCICDIPR50 INTC.ICDIPR50
+#define INTCICDIPR51 INTC.ICDIPR51
+#define INTCICDIPR52 INTC.ICDIPR52
+#define INTCICDIPR53 INTC.ICDIPR53
+#define INTCICDIPR54 INTC.ICDIPR54
+#define INTCICDIPR55 INTC.ICDIPR55
+#define INTCICDIPR56 INTC.ICDIPR56
+#define INTCICDIPR57 INTC.ICDIPR57
+#define INTCICDIPR58 INTC.ICDIPR58
+#define INTCICDIPR59 INTC.ICDIPR59
+#define INTCICDIPR60 INTC.ICDIPR60
+#define INTCICDIPR61 INTC.ICDIPR61
+#define INTCICDIPR62 INTC.ICDIPR62
+#define INTCICDIPR63 INTC.ICDIPR63
+#define INTCICDIPR64 INTC.ICDIPR64
+#define INTCICDIPR65 INTC.ICDIPR65
+#define INTCICDIPR66 INTC.ICDIPR66
+#define INTCICDIPR67 INTC.ICDIPR67
+#define INTCICDIPR68 INTC.ICDIPR68
+#define INTCICDIPR69 INTC.ICDIPR69
+#define INTCICDIPR70 INTC.ICDIPR70
+#define INTCICDIPR71 INTC.ICDIPR71
+#define INTCICDIPR72 INTC.ICDIPR72
+#define INTCICDIPR73 INTC.ICDIPR73
+#define INTCICDIPR74 INTC.ICDIPR74
+#define INTCICDIPR75 INTC.ICDIPR75
+#define INTCICDIPR76 INTC.ICDIPR76
+#define INTCICDIPR77 INTC.ICDIPR77
+#define INTCICDIPR78 INTC.ICDIPR78
+#define INTCICDIPR79 INTC.ICDIPR79
+#define INTCICDIPR80 INTC.ICDIPR80
+#define INTCICDIPR81 INTC.ICDIPR81
+#define INTCICDIPR82 INTC.ICDIPR82
+#define INTCICDIPR83 INTC.ICDIPR83
+#define INTCICDIPR84 INTC.ICDIPR84
+#define INTCICDIPR85 INTC.ICDIPR85
+#define INTCICDIPR86 INTC.ICDIPR86
+#define INTCICDIPR87 INTC.ICDIPR87
+#define INTCICDIPR88 INTC.ICDIPR88
+#define INTCICDIPR89 INTC.ICDIPR89
+#define INTCICDIPR90 INTC.ICDIPR90
+#define INTCICDIPR91 INTC.ICDIPR91
+#define INTCICDIPR92 INTC.ICDIPR92
+#define INTCICDIPR93 INTC.ICDIPR93
+#define INTCICDIPR94 INTC.ICDIPR94
+#define INTCICDIPR95 INTC.ICDIPR95
+#define INTCICDIPR96 INTC.ICDIPR96
+#define INTCICDIPR97 INTC.ICDIPR97
+#define INTCICDIPR98 INTC.ICDIPR98
+#define INTCICDIPR99 INTC.ICDIPR99
+#define INTCICDIPR100 INTC.ICDIPR100
+#define INTCICDIPR101 INTC.ICDIPR101
+#define INTCICDIPR102 INTC.ICDIPR102
+#define INTCICDIPR103 INTC.ICDIPR103
+#define INTCICDIPR104 INTC.ICDIPR104
+#define INTCICDIPR105 INTC.ICDIPR105
+#define INTCICDIPR106 INTC.ICDIPR106
+#define INTCICDIPR107 INTC.ICDIPR107
+#define INTCICDIPR108 INTC.ICDIPR108
+#define INTCICDIPR109 INTC.ICDIPR109
+#define INTCICDIPR110 INTC.ICDIPR110
+#define INTCICDIPR111 INTC.ICDIPR111
+#define INTCICDIPR112 INTC.ICDIPR112
+#define INTCICDIPR113 INTC.ICDIPR113
+#define INTCICDIPR114 INTC.ICDIPR114
+#define INTCICDIPR115 INTC.ICDIPR115
+#define INTCICDIPR116 INTC.ICDIPR116
+#define INTCICDIPR117 INTC.ICDIPR117
+#define INTCICDIPR118 INTC.ICDIPR118
+#define INTCICDIPR119 INTC.ICDIPR119
+#define INTCICDIPR120 INTC.ICDIPR120
+#define INTCICDIPR121 INTC.ICDIPR121
+#define INTCICDIPR122 INTC.ICDIPR122
+#define INTCICDIPR123 INTC.ICDIPR123
+#define INTCICDIPR124 INTC.ICDIPR124
+#define INTCICDIPR125 INTC.ICDIPR125
+#define INTCICDIPR126 INTC.ICDIPR126
+#define INTCICDIPR127 INTC.ICDIPR127
+#define INTCICDIPR128 INTC.ICDIPR128
+#define INTCICDIPR129 INTC.ICDIPR129
+#define INTCICDIPR130 INTC.ICDIPR130
+#define INTCICDIPR131 INTC.ICDIPR131
+#define INTCICDIPR132 INTC.ICDIPR132
+#define INTCICDIPR133 INTC.ICDIPR133
+#define INTCICDIPR134 INTC.ICDIPR134
+#define INTCICDIPR135 INTC.ICDIPR135
+#define INTCICDIPR136 INTC.ICDIPR136
+#define INTCICDIPR137 INTC.ICDIPR137
+#define INTCICDIPR138 INTC.ICDIPR138
+#define INTCICDIPR139 INTC.ICDIPR139
+#define INTCICDIPR140 INTC.ICDIPR140
+#define INTCICDIPR141 INTC.ICDIPR141
+#define INTCICDIPR142 INTC.ICDIPR142
+#define INTCICDIPR143 INTC.ICDIPR143
+#define INTCICDIPR144 INTC.ICDIPR144
+#define INTCICDIPR145 INTC.ICDIPR145
+#define INTCICDIPR146 INTC.ICDIPR146
+#define INTCICDIPTR0 INTC.ICDIPTR0
+#define INTCICDIPTR1 INTC.ICDIPTR1
+#define INTCICDIPTR2 INTC.ICDIPTR2
+#define INTCICDIPTR3 INTC.ICDIPTR3
+#define INTCICDIPTR4 INTC.ICDIPTR4
+#define INTCICDIPTR5 INTC.ICDIPTR5
+#define INTCICDIPTR6 INTC.ICDIPTR6
+#define INTCICDIPTR7 INTC.ICDIPTR7
+#define INTCICDIPTR8 INTC.ICDIPTR8
+#define INTCICDIPTR9 INTC.ICDIPTR9
+#define INTCICDIPTR10 INTC.ICDIPTR10
+#define INTCICDIPTR11 INTC.ICDIPTR11
+#define INTCICDIPTR12 INTC.ICDIPTR12
+#define INTCICDIPTR13 INTC.ICDIPTR13
+#define INTCICDIPTR14 INTC.ICDIPTR14
+#define INTCICDIPTR15 INTC.ICDIPTR15
+#define INTCICDIPTR16 INTC.ICDIPTR16
+#define INTCICDIPTR17 INTC.ICDIPTR17
+#define INTCICDIPTR18 INTC.ICDIPTR18
+#define INTCICDIPTR19 INTC.ICDIPTR19
+#define INTCICDIPTR20 INTC.ICDIPTR20
+#define INTCICDIPTR21 INTC.ICDIPTR21
+#define INTCICDIPTR22 INTC.ICDIPTR22
+#define INTCICDIPTR23 INTC.ICDIPTR23
+#define INTCICDIPTR24 INTC.ICDIPTR24
+#define INTCICDIPTR25 INTC.ICDIPTR25
+#define INTCICDIPTR26 INTC.ICDIPTR26
+#define INTCICDIPTR27 INTC.ICDIPTR27
+#define INTCICDIPTR28 INTC.ICDIPTR28
+#define INTCICDIPTR29 INTC.ICDIPTR29
+#define INTCICDIPTR30 INTC.ICDIPTR30
+#define INTCICDIPTR31 INTC.ICDIPTR31
+#define INTCICDIPTR32 INTC.ICDIPTR32
+#define INTCICDIPTR33 INTC.ICDIPTR33
+#define INTCICDIPTR34 INTC.ICDIPTR34
+#define INTCICDIPTR35 INTC.ICDIPTR35
+#define INTCICDIPTR36 INTC.ICDIPTR36
+#define INTCICDIPTR37 INTC.ICDIPTR37
+#define INTCICDIPTR38 INTC.ICDIPTR38
+#define INTCICDIPTR39 INTC.ICDIPTR39
+#define INTCICDIPTR40 INTC.ICDIPTR40
+#define INTCICDIPTR41 INTC.ICDIPTR41
+#define INTCICDIPTR42 INTC.ICDIPTR42
+#define INTCICDIPTR43 INTC.ICDIPTR43
+#define INTCICDIPTR44 INTC.ICDIPTR44
+#define INTCICDIPTR45 INTC.ICDIPTR45
+#define INTCICDIPTR46 INTC.ICDIPTR46
+#define INTCICDIPTR47 INTC.ICDIPTR47
+#define INTCICDIPTR48 INTC.ICDIPTR48
+#define INTCICDIPTR49 INTC.ICDIPTR49
+#define INTCICDIPTR50 INTC.ICDIPTR50
+#define INTCICDIPTR51 INTC.ICDIPTR51
+#define INTCICDIPTR52 INTC.ICDIPTR52
+#define INTCICDIPTR53 INTC.ICDIPTR53
+#define INTCICDIPTR54 INTC.ICDIPTR54
+#define INTCICDIPTR55 INTC.ICDIPTR55
+#define INTCICDIPTR56 INTC.ICDIPTR56
+#define INTCICDIPTR57 INTC.ICDIPTR57
+#define INTCICDIPTR58 INTC.ICDIPTR58
+#define INTCICDIPTR59 INTC.ICDIPTR59
+#define INTCICDIPTR60 INTC.ICDIPTR60
+#define INTCICDIPTR61 INTC.ICDIPTR61
+#define INTCICDIPTR62 INTC.ICDIPTR62
+#define INTCICDIPTR63 INTC.ICDIPTR63
+#define INTCICDIPTR64 INTC.ICDIPTR64
+#define INTCICDIPTR65 INTC.ICDIPTR65
+#define INTCICDIPTR66 INTC.ICDIPTR66
+#define INTCICDIPTR67 INTC.ICDIPTR67
+#define INTCICDIPTR68 INTC.ICDIPTR68
+#define INTCICDIPTR69 INTC.ICDIPTR69
+#define INTCICDIPTR70 INTC.ICDIPTR70
+#define INTCICDIPTR71 INTC.ICDIPTR71
+#define INTCICDIPTR72 INTC.ICDIPTR72
+#define INTCICDIPTR73 INTC.ICDIPTR73
+#define INTCICDIPTR74 INTC.ICDIPTR74
+#define INTCICDIPTR75 INTC.ICDIPTR75
+#define INTCICDIPTR76 INTC.ICDIPTR76
+#define INTCICDIPTR77 INTC.ICDIPTR77
+#define INTCICDIPTR78 INTC.ICDIPTR78
+#define INTCICDIPTR79 INTC.ICDIPTR79
+#define INTCICDIPTR80 INTC.ICDIPTR80
+#define INTCICDIPTR81 INTC.ICDIPTR81
+#define INTCICDIPTR82 INTC.ICDIPTR82
+#define INTCICDIPTR83 INTC.ICDIPTR83
+#define INTCICDIPTR84 INTC.ICDIPTR84
+#define INTCICDIPTR85 INTC.ICDIPTR85
+#define INTCICDIPTR86 INTC.ICDIPTR86
+#define INTCICDIPTR87 INTC.ICDIPTR87
+#define INTCICDIPTR88 INTC.ICDIPTR88
+#define INTCICDIPTR89 INTC.ICDIPTR89
+#define INTCICDIPTR90 INTC.ICDIPTR90
+#define INTCICDIPTR91 INTC.ICDIPTR91
+#define INTCICDIPTR92 INTC.ICDIPTR92
+#define INTCICDIPTR93 INTC.ICDIPTR93
+#define INTCICDIPTR94 INTC.ICDIPTR94
+#define INTCICDIPTR95 INTC.ICDIPTR95
+#define INTCICDIPTR96 INTC.ICDIPTR96
+#define INTCICDIPTR97 INTC.ICDIPTR97
+#define INTCICDIPTR98 INTC.ICDIPTR98
+#define INTCICDIPTR99 INTC.ICDIPTR99
+#define INTCICDIPTR100 INTC.ICDIPTR100
+#define INTCICDIPTR101 INTC.ICDIPTR101
+#define INTCICDIPTR102 INTC.ICDIPTR102
+#define INTCICDIPTR103 INTC.ICDIPTR103
+#define INTCICDIPTR104 INTC.ICDIPTR104
+#define INTCICDIPTR105 INTC.ICDIPTR105
+#define INTCICDIPTR106 INTC.ICDIPTR106
+#define INTCICDIPTR107 INTC.ICDIPTR107
+#define INTCICDIPTR108 INTC.ICDIPTR108
+#define INTCICDIPTR109 INTC.ICDIPTR109
+#define INTCICDIPTR110 INTC.ICDIPTR110
+#define INTCICDIPTR111 INTC.ICDIPTR111
+#define INTCICDIPTR112 INTC.ICDIPTR112
+#define INTCICDIPTR113 INTC.ICDIPTR113
+#define INTCICDIPTR114 INTC.ICDIPTR114
+#define INTCICDIPTR115 INTC.ICDIPTR115
+#define INTCICDIPTR116 INTC.ICDIPTR116
+#define INTCICDIPTR117 INTC.ICDIPTR117
+#define INTCICDIPTR118 INTC.ICDIPTR118
+#define INTCICDIPTR119 INTC.ICDIPTR119
+#define INTCICDIPTR120 INTC.ICDIPTR120
+#define INTCICDIPTR121 INTC.ICDIPTR121
+#define INTCICDIPTR122 INTC.ICDIPTR122
+#define INTCICDIPTR123 INTC.ICDIPTR123
+#define INTCICDIPTR124 INTC.ICDIPTR124
+#define INTCICDIPTR125 INTC.ICDIPTR125
+#define INTCICDIPTR126 INTC.ICDIPTR126
+#define INTCICDIPTR127 INTC.ICDIPTR127
+#define INTCICDIPTR128 INTC.ICDIPTR128
+#define INTCICDIPTR129 INTC.ICDIPTR129
+#define INTCICDIPTR130 INTC.ICDIPTR130
+#define INTCICDIPTR131 INTC.ICDIPTR131
+#define INTCICDIPTR132 INTC.ICDIPTR132
+#define INTCICDIPTR133 INTC.ICDIPTR133
+#define INTCICDIPTR134 INTC.ICDIPTR134
+#define INTCICDIPTR135 INTC.ICDIPTR135
+#define INTCICDIPTR136 INTC.ICDIPTR136
+#define INTCICDIPTR137 INTC.ICDIPTR137
+#define INTCICDIPTR138 INTC.ICDIPTR138
+#define INTCICDIPTR139 INTC.ICDIPTR139
+#define INTCICDIPTR140 INTC.ICDIPTR140
+#define INTCICDIPTR141 INTC.ICDIPTR141
+#define INTCICDIPTR142 INTC.ICDIPTR142
+#define INTCICDIPTR143 INTC.ICDIPTR143
+#define INTCICDIPTR144 INTC.ICDIPTR144
+#define INTCICDIPTR145 INTC.ICDIPTR145
+#define INTCICDIPTR146 INTC.ICDIPTR146
+#define INTCICDICFR0 INTC.ICDICFR0
+#define INTCICDICFR1 INTC.ICDICFR1
+#define INTCICDICFR2 INTC.ICDICFR2
+#define INTCICDICFR3 INTC.ICDICFR3
+#define INTCICDICFR4 INTC.ICDICFR4
+#define INTCICDICFR5 INTC.ICDICFR5
+#define INTCICDICFR6 INTC.ICDICFR6
+#define INTCICDICFR7 INTC.ICDICFR7
+#define INTCICDICFR8 INTC.ICDICFR8
+#define INTCICDICFR9 INTC.ICDICFR9
+#define INTCICDICFR10 INTC.ICDICFR10
+#define INTCICDICFR11 INTC.ICDICFR11
+#define INTCICDICFR12 INTC.ICDICFR12
+#define INTCICDICFR13 INTC.ICDICFR13
+#define INTCICDICFR14 INTC.ICDICFR14
+#define INTCICDICFR15 INTC.ICDICFR15
+#define INTCICDICFR16 INTC.ICDICFR16
+#define INTCICDICFR17 INTC.ICDICFR17
+#define INTCICDICFR18 INTC.ICDICFR18
+#define INTCICDICFR19 INTC.ICDICFR19
+#define INTCICDICFR20 INTC.ICDICFR20
+#define INTCICDICFR21 INTC.ICDICFR21
+#define INTCICDICFR22 INTC.ICDICFR22
+#define INTCICDICFR23 INTC.ICDICFR23
+#define INTCICDICFR24 INTC.ICDICFR24
+#define INTCICDICFR25 INTC.ICDICFR25
+#define INTCICDICFR26 INTC.ICDICFR26
+#define INTCICDICFR27 INTC.ICDICFR27
+#define INTCICDICFR28 INTC.ICDICFR28
+#define INTCICDICFR29 INTC.ICDICFR29
+#define INTCICDICFR30 INTC.ICDICFR30
+#define INTCICDICFR31 INTC.ICDICFR31
+#define INTCICDICFR32 INTC.ICDICFR32
+#define INTCICDICFR33 INTC.ICDICFR33
+#define INTCICDICFR34 INTC.ICDICFR34
+#define INTCICDICFR35 INTC.ICDICFR35
+#define INTCICDICFR36 INTC.ICDICFR36
+#define INTCPPI_STATUS INTC.PPI_STATUS
+#define INTCSPI_STATUS0 INTC.SPI_STATUS0
+#define INTCSPI_STATUS1 INTC.SPI_STATUS1
+#define INTCSPI_STATUS2 INTC.SPI_STATUS2
+#define INTCSPI_STATUS3 INTC.SPI_STATUS3
+#define INTCSPI_STATUS4 INTC.SPI_STATUS4
+#define INTCSPI_STATUS5 INTC.SPI_STATUS5
+#define INTCSPI_STATUS6 INTC.SPI_STATUS6
+#define INTCSPI_STATUS7 INTC.SPI_STATUS7
+#define INTCSPI_STATUS8 INTC.SPI_STATUS8
+#define INTCSPI_STATUS9 INTC.SPI_STATUS9
+#define INTCSPI_STATUS10 INTC.SPI_STATUS10
+#define INTCSPI_STATUS11 INTC.SPI_STATUS11
+#define INTCSPI_STATUS12 INTC.SPI_STATUS12
+#define INTCSPI_STATUS13 INTC.SPI_STATUS13
+#define INTCSPI_STATUS14 INTC.SPI_STATUS14
+#define INTCSPI_STATUS15 INTC.SPI_STATUS15
+#define INTCSPI_STATUS16 INTC.SPI_STATUS16
+#define INTCICDSGIR INTC.ICDSGIR
+#define INTCICCICR INTC.ICCICR
+#define INTCICCPMR INTC.ICCPMR
+#define INTCICCBPR INTC.ICCBPR
+#define INTCICCIAR INTC.ICCIAR
+#define INTCICCEOIR INTC.ICCEOIR
+#define INTCICCRPR INTC.ICCRPR
+#define INTCICCHPIR INTC.ICCHPIR
+#define INTCICCABPR INTC.ICCABPR
+#define INTCICCIIDR INTC.ICCIIDR
+#define INTCICR0 INTC.ICR0
+#define INTCICR1 INTC.ICR1
+#define INTCIRQRR INTC.IRQRR
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h
new file mode 100644
index 000000000..14665ef2d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h
@@ -0,0 +1,42 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : irda_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IRDA_IODEFINE_H
+#define IRDA_IODEFINE_H
+
+struct st_irda
+{ /* IRDA */
+ volatile uint8_t IRCR; /* IRCR */
+};
+
+
+#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */
+
+
+#define IRDAIRCR IRDA.IRCR
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h
new file mode 100644
index 000000000..fa34ce215
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h
@@ -0,0 +1,169 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : jcu_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef JCU_IODEFINE_H
+#define JCU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_jcu
+{ /* JCU */
+ volatile uint8_t JCMOD; /* JCMOD */
+ volatile uint8_t JCCMD; /* JCCMD */
+ volatile uint8_t dummy145[1]; /* */
+ volatile uint8_t JCQTN; /* JCQTN */
+ volatile uint8_t JCHTN; /* JCHTN */
+ volatile uint8_t JCDRIU; /* JCDRIU */
+ volatile uint8_t JCDRID; /* JCDRID */
+ volatile uint8_t JCVSZU; /* JCVSZU */
+ volatile uint8_t JCVSZD; /* JCVSZD */
+ volatile uint8_t JCHSZU; /* JCHSZU */
+ volatile uint8_t JCHSZD; /* JCHSZD */
+ volatile uint8_t JCDTCU; /* JCDTCU */
+ volatile uint8_t JCDTCM; /* JCDTCM */
+ volatile uint8_t JCDTCD; /* JCDTCD */
+ volatile uint8_t JINTE0; /* JINTE0 */
+ volatile uint8_t JINTS0; /* JINTS0 */
+ volatile uint8_t JCDERR; /* JCDERR */
+ volatile uint8_t JCRST; /* JCRST */
+ volatile uint8_t dummy146[46]; /* */
+ volatile uint32_t JIFECNT; /* JIFECNT */
+ volatile uint32_t JIFESA; /* JIFESA */
+ volatile uint32_t JIFESOFST; /* JIFESOFST */
+ volatile uint32_t JIFEDA; /* JIFEDA */
+ volatile uint32_t JIFESLC; /* JIFESLC */
+ volatile uint32_t JIFEDDC; /* JIFEDDC */
+ volatile uint32_t JIFDCNT; /* JIFDCNT */
+ volatile uint32_t JIFDSA; /* JIFDSA */
+ volatile uint32_t JIFDDOFST; /* JIFDDOFST */
+ volatile uint32_t JIFDDA; /* JIFDDA */
+ volatile uint32_t JIFDSDC; /* JIFDSDC */
+ volatile uint32_t JIFDDLC; /* JIFDDLC */
+ volatile uint32_t JIFDADT; /* JIFDADT */
+ volatile uint8_t dummy147[24]; /* */
+ volatile uint32_t JINTE1; /* JINTE1 */
+ volatile uint32_t JINTS1; /* JINTS1 */
+ volatile uint32_t JIFESVSZ; /* JIFESVSZ */
+ volatile uint32_t JIFESHSZ; /* JIFESHSZ */
+ volatile uint8_t dummy148[100]; /* */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL0; /* JCQTBL0 */
+ volatile uint8_t dummy149[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL1; /* JCQTBL1 */
+ volatile uint8_t dummy150[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL2; /* JCQTBL2 */
+ volatile uint8_t dummy151[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL3; /* JCQTBL3 */
+ volatile uint8_t dummy152[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCHTBD0; /* JCHTBD0 */
+ volatile uint8_t dummy153[31]; /* */
+ volatile uint8_t JCHTBA0; /* JCHTBA0 */
+ volatile uint8_t dummy154[223]; /* */
+ volatile uint8_t JCHTBD1; /* JCHTBD1 */
+ volatile uint8_t dummy155[31]; /* */
+ volatile uint8_t JCHTBA1; /* JCHTBA1 */
+};
+
+
+struct st_jcu_from_jcqtbl0
+{
+ volatile uint8_t JCQTBL0; /* JCQTBL0 */
+ volatile uint8_t dummy1[63]; /* */
+};
+
+
+#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
+
+
+/* Start of channnel array defines of JCU */
+
+/* Channnel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT 4
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channnel array defines of JCU */
+
+
+#define JCUJCMOD JCU.JCMOD
+#define JCUJCCMD JCU.JCCMD
+#define JCUJCQTN JCU.JCQTN
+#define JCUJCHTN JCU.JCHTN
+#define JCUJCDRIU JCU.JCDRIU
+#define JCUJCDRID JCU.JCDRID
+#define JCUJCVSZU JCU.JCVSZU
+#define JCUJCVSZD JCU.JCVSZD
+#define JCUJCHSZU JCU.JCHSZU
+#define JCUJCHSZD JCU.JCHSZD
+#define JCUJCDTCU JCU.JCDTCU
+#define JCUJCDTCM JCU.JCDTCM
+#define JCUJCDTCD JCU.JCDTCD
+#define JCUJINTE0 JCU.JINTE0
+#define JCUJINTS0 JCU.JINTS0
+#define JCUJCDERR JCU.JCDERR
+#define JCUJCRST JCU.JCRST
+#define JCUJIFECNT JCU.JIFECNT
+#define JCUJIFESA JCU.JIFESA
+#define JCUJIFESOFST JCU.JIFESOFST
+#define JCUJIFEDA JCU.JIFEDA
+#define JCUJIFESLC JCU.JIFESLC
+#define JCUJIFEDDC JCU.JIFEDDC
+#define JCUJIFDCNT JCU.JIFDCNT
+#define JCUJIFDSA JCU.JIFDSA
+#define JCUJIFDDOFST JCU.JIFDDOFST
+#define JCUJIFDDA JCU.JIFDDA
+#define JCUJIFDSDC JCU.JIFDSDC
+#define JCUJIFDDLC JCU.JIFDDLC
+#define JCUJIFDADT JCU.JIFDADT
+#define JCUJINTE1 JCU.JINTE1
+#define JCUJINTS1 JCU.JINTS1
+#define JCUJIFESVSZ JCU.JIFESVSZ
+#define JCUJIFESHSZ JCU.JIFESHSZ
+#define JCUJCQTBL0 JCU.JCQTBL0
+#define JCUJCQTBL1 JCU.JCQTBL1
+#define JCUJCQTBL2 JCU.JCQTBL2
+#define JCUJCQTBL3 JCU.JCQTBL3
+#define JCUJCHTBD0 JCU.JCHTBD0
+#define JCUJCHTBA0 JCU.JCHTBA0
+#define JCUJCHTBD1 JCU.JCHTBD1
+#define JCUJCHTBA1 JCU.JCHTBA1
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h
new file mode 100644
index 000000000..ba6cb180b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h
@@ -0,0 +1,195 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : l2c_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef L2C_IODEFINE_H
+#define L2C_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_l2c
+{ /* L2C */
+ volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
+ volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
+ volatile uint8_t dummy8[248]; /* */
+ volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
+ volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
+ volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
+ volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
+ volatile uint8_t dummy9[240]; /* */
+ volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
+ volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
+ volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
+ volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
+ volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
+ volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
+ volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
+ volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
+ volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
+ volatile uint8_t dummy10[1292]; /* */
+ volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
+ volatile uint8_t dummy11[60]; /* */
+ volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
+ volatile uint8_t dummy12[8]; /* */
+ volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
+ volatile uint8_t dummy13[48]; /* */
+ volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
+ volatile uint8_t dummy14[4]; /* */
+ volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
+ volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
+ volatile uint8_t dummy15[48]; /* */
+ volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
+ volatile uint8_t dummy16[4]; /* */
+ volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
+ volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
+ volatile uint8_t dummy17[256]; /* */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
+ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
+ volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
+ volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
+ volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
+ volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
+ volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
+ volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
+ volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint8_t dummy18[16]; /* */
+ volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
+ volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
+ volatile uint8_t dummy19[680]; /* */
+ volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
+ volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
+ volatile uint8_t dummy20[824]; /* */
+ volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
+ volatile uint8_t dummy21[28]; /* */
+ volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
+ volatile uint8_t dummy22[28]; /* */
+ volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
+};
+
+
+struct st_l2c_from_reg9_d_lockdown0
+{
+ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
+ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
+};
+
+
+#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channnel array defines of L2C */
+
+/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channnel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
+#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
+#define L2CREG1_CONTROL L2C.REG1_CONTROL
+#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
+#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
+#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
+#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
+#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
+#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
+#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
+#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
+#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
+#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
+#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
+#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
+#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
+#define L2CREG7_INV_PA L2C.REG7_INV_PA
+#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
+#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
+#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
+#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
+#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
+#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
+#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
+#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
+#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
+#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
+#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
+#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
+#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
+#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
+#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
+#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
+#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
+#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
+#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
+#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
+#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
+#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
+#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
+#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
+#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
+#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
+#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
+#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
+#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
+#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h
new file mode 100644
index 000000000..d46e7770b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h
@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lin_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef LIN_IODEFINE_H
+#define LIN_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lin
+{ /* LIN */
+ volatile uint8_t dummy1[1]; /* */
+ volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */
+ union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */
+
+ volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint8_t RLN3nLMD; /* RLN3nLMD */
+ volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */
+ volatile uint8_t RLN3nLSC; /* RLN3nLSC */
+ volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */
+ volatile uint8_t RLN3nLIE; /* RLN3nLIE */
+ volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */
+ volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */
+ volatile uint8_t dummy3[1]; /* */
+ volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */
+ volatile uint8_t RLN3nLMST; /* RLN3nLMST */
+ volatile uint8_t RLN3nLST; /* RLN3nLST */
+ volatile uint8_t RLN3nLEST; /* RLN3nLEST */
+ volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */
+ volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */
+ volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */
+ volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */
+#define LIN_LDBn_COUNT 8
+ volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */
+ volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */
+ volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */
+ volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */
+ volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */
+ volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */
+ volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */
+ volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */
+ volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */
+ volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */
+ volatile uint8_t dummy4[2]; /* */
+ union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */
+ union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */
+ union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */
+
+};
+
+
+#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
+#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channnel array defines of LIN */
+
+/* Channnel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT 2
+#define LIN_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &LIN0, &LIN1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of LIN */
+
+
+#define LIN0RLN30LWBR LIN0.RLN3nLWBR
+#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
+#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
+#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
+#define LIN0RLN30LSTC LIN0.RLN3nLSTC
+#define LIN0RLN30LMD LIN0.RLN3nLMD
+#define LIN0RLN30LBFC LIN0.RLN3nLBFC
+#define LIN0RLN30LSC LIN0.RLN3nLSC
+#define LIN0RLN30LWUP LIN0.RLN3nLWUP
+#define LIN0RLN30LIE LIN0.RLN3nLIE
+#define LIN0RLN30LEDE LIN0.RLN3nLEDE
+#define LIN0RLN30LCUC LIN0.RLN3nLCUC
+#define LIN0RLN30LTRC LIN0.RLN3nLTRC
+#define LIN0RLN30LMST LIN0.RLN3nLMST
+#define LIN0RLN30LST LIN0.RLN3nLST
+#define LIN0RLN30LEST LIN0.RLN3nLEST
+#define LIN0RLN30LDFC LIN0.RLN3nLDFC
+#define LIN0RLN30LIDB LIN0.RLN3nLIDB
+#define LIN0RLN30LCBR LIN0.RLN3nLCBR
+#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
+#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
+#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
+#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
+#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
+#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
+#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
+#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
+#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
+#define LIN0RLN30LUOER LIN0.RLN3nLUOER
+#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
+#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
+#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
+#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
+#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
+#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
+#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
+#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
+#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
+#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
+#define LIN1RLN31LWBR LIN1.RLN3nLWBR
+#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
+#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
+#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
+#define LIN1RLN31LSTC LIN1.RLN3nLSTC
+#define LIN1RLN31LMD LIN1.RLN3nLMD
+#define LIN1RLN31LBFC LIN1.RLN3nLBFC
+#define LIN1RLN31LSC LIN1.RLN3nLSC
+#define LIN1RLN31LWUP LIN1.RLN3nLWUP
+#define LIN1RLN31LIE LIN1.RLN3nLIE
+#define LIN1RLN31LEDE LIN1.RLN3nLEDE
+#define LIN1RLN31LCUC LIN1.RLN3nLCUC
+#define LIN1RLN31LTRC LIN1.RLN3nLTRC
+#define LIN1RLN31LMST LIN1.RLN3nLMST
+#define LIN1RLN31LST LIN1.RLN3nLST
+#define LIN1RLN31LEST LIN1.RLN3nLEST
+#define LIN1RLN31LDFC LIN1.RLN3nLDFC
+#define LIN1RLN31LIDB LIN1.RLN3nLIDB
+#define LIN1RLN31LCBR LIN1.RLN3nLCBR
+#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
+#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
+#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
+#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
+#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
+#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
+#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
+#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
+#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
+#define LIN1RLN31LUOER LIN1.RLN3nLUOER
+#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
+#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
+#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
+#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
+#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
+#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
+#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
+#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
+#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
+#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h
new file mode 100644
index 000000000..797c58a02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lvds_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef LVDS_IODEFINE_H
+#define LVDS_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lvds
+{ /* LVDS */
+ volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */
+ volatile uint32_t LVDSFCL; /* LVDSFCL */
+ volatile uint8_t dummy608[24]; /* */
+ volatile uint32_t LCLKSELR; /* LCLKSELR */
+ volatile uint32_t LPLLSETR; /* LPLLSETR */
+ volatile uint32_t LPLLMONR; /* LPLLMONR */
+};
+
+
+#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
+#define LVDSLVDSFCL LVDS.LVDSFCL
+#define LVDSLCLKSELR LVDS.LCLKSELR
+#define LVDSLPLLSETR LVDS.LPLLSETR
+#define LVDSLPLLMONR LVDS.LPLLMONR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h
new file mode 100644
index 000000000..ae9736587
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h
@@ -0,0 +1,498 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mlb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MLB_IODEFINE_H
+#define MLB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mlb
+{ /* MLB */
+ volatile uint32_t DCCR; /* DCCR */
+ volatile uint32_t SSCR; /* SSCR */
+ volatile uint32_t SDCR; /* SDCR */
+ volatile uint32_t SMCR; /* SMCR */
+ volatile uint8_t dummy156[12]; /* */
+ volatile uint32_t VCCR; /* VCCR */
+ volatile uint32_t SBCR; /* SBCR */
+ volatile uint32_t ABCR; /* ABCR */
+ volatile uint32_t CBCR; /* CBCR */
+ volatile uint32_t IBCR; /* IBCR */
+ volatile uint32_t CICR; /* CICR */
+ volatile uint8_t dummy157[12]; /* */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR0; /* CECR0 */
+ volatile uint32_t CSCR0; /* CSCR0 */
+ volatile uint32_t CCBCR0; /* CCBCR0 */
+ volatile uint32_t CNBCR0; /* CNBCR0 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR1; /* CECR1 */
+ volatile uint32_t CSCR1; /* CSCR1 */
+ volatile uint32_t CCBCR1; /* CCBCR1 */
+ volatile uint32_t CNBCR1; /* CNBCR1 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR2; /* CECR2 */
+ volatile uint32_t CSCR2; /* CSCR2 */
+ volatile uint32_t CCBCR2; /* CCBCR2 */
+ volatile uint32_t CNBCR2; /* CNBCR2 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR3; /* CECR3 */
+ volatile uint32_t CSCR3; /* CSCR3 */
+ volatile uint32_t CCBCR3; /* CCBCR3 */
+ volatile uint32_t CNBCR3; /* CNBCR3 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR4; /* CECR4 */
+ volatile uint32_t CSCR4; /* CSCR4 */
+ volatile uint32_t CCBCR4; /* CCBCR4 */
+ volatile uint32_t CNBCR4; /* CNBCR4 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR5; /* CECR5 */
+ volatile uint32_t CSCR5; /* CSCR5 */
+ volatile uint32_t CCBCR5; /* CCBCR5 */
+ volatile uint32_t CNBCR5; /* CNBCR5 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR6; /* CECR6 */
+ volatile uint32_t CSCR6; /* CSCR6 */
+ volatile uint32_t CCBCR6; /* CCBCR6 */
+ volatile uint32_t CNBCR6; /* CNBCR6 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR7; /* CECR7 */
+ volatile uint32_t CSCR7; /* CSCR7 */
+ volatile uint32_t CCBCR7; /* CCBCR7 */
+ volatile uint32_t CNBCR7; /* CNBCR7 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR8; /* CECR8 */
+ volatile uint32_t CSCR8; /* CSCR8 */
+ volatile uint32_t CCBCR8; /* CCBCR8 */
+ volatile uint32_t CNBCR8; /* CNBCR8 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR9; /* CECR9 */
+ volatile uint32_t CSCR9; /* CSCR9 */
+ volatile uint32_t CCBCR9; /* CCBCR9 */
+ volatile uint32_t CNBCR9; /* CNBCR9 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR10; /* CECR10 */
+ volatile uint32_t CSCR10; /* CSCR10 */
+ volatile uint32_t CCBCR10; /* CCBCR10 */
+ volatile uint32_t CNBCR10; /* CNBCR10 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR11; /* CECR11 */
+ volatile uint32_t CSCR11; /* CSCR11 */
+ volatile uint32_t CCBCR11; /* CCBCR11 */
+ volatile uint32_t CNBCR11; /* CNBCR11 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR12; /* CECR12 */
+ volatile uint32_t CSCR12; /* CSCR12 */
+ volatile uint32_t CCBCR12; /* CCBCR12 */
+ volatile uint32_t CNBCR12; /* CNBCR12 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR13; /* CECR13 */
+ volatile uint32_t CSCR13; /* CSCR13 */
+ volatile uint32_t CCBCR13; /* CCBCR13 */
+ volatile uint32_t CNBCR13; /* CNBCR13 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR14; /* CECR14 */
+ volatile uint32_t CSCR14; /* CSCR14 */
+ volatile uint32_t CCBCR14; /* CCBCR14 */
+ volatile uint32_t CNBCR14; /* CNBCR14 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR15; /* CECR15 */
+ volatile uint32_t CSCR15; /* CSCR15 */
+ volatile uint32_t CCBCR15; /* CCBCR15 */
+ volatile uint32_t CNBCR15; /* CNBCR15 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR16; /* CECR16 */
+ volatile uint32_t CSCR16; /* CSCR16 */
+ volatile uint32_t CCBCR16; /* CCBCR16 */
+ volatile uint32_t CNBCR16; /* CNBCR16 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR17; /* CECR17 */
+ volatile uint32_t CSCR17; /* CSCR17 */
+ volatile uint32_t CCBCR17; /* CCBCR17 */
+ volatile uint32_t CNBCR17; /* CNBCR17 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR18; /* CECR18 */
+ volatile uint32_t CSCR18; /* CSCR18 */
+ volatile uint32_t CCBCR18; /* CCBCR18 */
+ volatile uint32_t CNBCR18; /* CNBCR18 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR19; /* CECR19 */
+ volatile uint32_t CSCR19; /* CSCR19 */
+ volatile uint32_t CCBCR19; /* CCBCR19 */
+ volatile uint32_t CNBCR19; /* CNBCR19 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR20; /* CECR20 */
+ volatile uint32_t CSCR20; /* CSCR20 */
+ volatile uint32_t CCBCR20; /* CCBCR20 */
+ volatile uint32_t CNBCR20; /* CNBCR20 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR21; /* CECR21 */
+ volatile uint32_t CSCR21; /* CSCR21 */
+ volatile uint32_t CCBCR21; /* CCBCR21 */
+ volatile uint32_t CNBCR21; /* CNBCR21 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR22; /* CECR22 */
+ volatile uint32_t CSCR22; /* CSCR22 */
+ volatile uint32_t CCBCR22; /* CCBCR22 */
+ volatile uint32_t CNBCR22; /* CNBCR22 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR23; /* CECR23 */
+ volatile uint32_t CSCR23; /* CSCR23 */
+ volatile uint32_t CCBCR23; /* CCBCR23 */
+ volatile uint32_t CNBCR23; /* CNBCR23 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR24; /* CECR24 */
+ volatile uint32_t CSCR24; /* CSCR24 */
+ volatile uint32_t CCBCR24; /* CCBCR24 */
+ volatile uint32_t CNBCR24; /* CNBCR24 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR25; /* CECR25 */
+ volatile uint32_t CSCR25; /* CSCR25 */
+ volatile uint32_t CCBCR25; /* CCBCR25 */
+ volatile uint32_t CNBCR25; /* CNBCR25 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR26; /* CECR26 */
+ volatile uint32_t CSCR26; /* CSCR26 */
+ volatile uint32_t CCBCR26; /* CCBCR26 */
+ volatile uint32_t CNBCR26; /* CNBCR26 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR27; /* CECR27 */
+ volatile uint32_t CSCR27; /* CSCR27 */
+ volatile uint32_t CCBCR27; /* CCBCR27 */
+ volatile uint32_t CNBCR27; /* CNBCR27 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR28; /* CECR28 */
+ volatile uint32_t CSCR28; /* CSCR28 */
+ volatile uint32_t CCBCR28; /* CCBCR28 */
+ volatile uint32_t CNBCR28; /* CNBCR28 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR29; /* CECR29 */
+ volatile uint32_t CSCR29; /* CSCR29 */
+ volatile uint32_t CCBCR29; /* CCBCR29 */
+ volatile uint32_t CNBCR29; /* CNBCR29 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR30; /* CECR30 */
+ volatile uint32_t CSCR30; /* CSCR30 */
+ volatile uint32_t CCBCR30; /* CCBCR30 */
+ volatile uint32_t CNBCR30; /* CNBCR30 */
+/* end of struct st_mlb_from_cecr0 */
+ volatile uint8_t dummy158[80]; /* */
+#define MLB_LCBCR0_COUNT 31
+ volatile uint32_t LCBCR0; /* LCBCR0 */
+ volatile uint32_t LCBCR1; /* LCBCR1 */
+ volatile uint32_t LCBCR2; /* LCBCR2 */
+ volatile uint32_t LCBCR3; /* LCBCR3 */
+ volatile uint32_t LCBCR4; /* LCBCR4 */
+ volatile uint32_t LCBCR5; /* LCBCR5 */
+ volatile uint32_t LCBCR6; /* LCBCR6 */
+ volatile uint32_t LCBCR7; /* LCBCR7 */
+ volatile uint32_t LCBCR8; /* LCBCR8 */
+ volatile uint32_t LCBCR9; /* LCBCR9 */
+ volatile uint32_t LCBCR10; /* LCBCR10 */
+ volatile uint32_t LCBCR11; /* LCBCR11 */
+ volatile uint32_t LCBCR12; /* LCBCR12 */
+ volatile uint32_t LCBCR13; /* LCBCR13 */
+ volatile uint32_t LCBCR14; /* LCBCR14 */
+ volatile uint32_t LCBCR15; /* LCBCR15 */
+ volatile uint32_t LCBCR16; /* LCBCR16 */
+ volatile uint32_t LCBCR17; /* LCBCR17 */
+ volatile uint32_t LCBCR18; /* LCBCR18 */
+ volatile uint32_t LCBCR19; /* LCBCR19 */
+ volatile uint32_t LCBCR20; /* LCBCR20 */
+ volatile uint32_t LCBCR21; /* LCBCR21 */
+ volatile uint32_t LCBCR22; /* LCBCR22 */
+ volatile uint32_t LCBCR23; /* LCBCR23 */
+ volatile uint32_t LCBCR24; /* LCBCR24 */
+ volatile uint32_t LCBCR25; /* LCBCR25 */
+ volatile uint32_t LCBCR26; /* LCBCR26 */
+ volatile uint32_t LCBCR27; /* LCBCR27 */
+ volatile uint32_t LCBCR28; /* LCBCR28 */
+ volatile uint32_t LCBCR29; /* LCBCR29 */
+ volatile uint32_t LCBCR30; /* LCBCR30 */
+};
+
+
+struct st_mlb_from_cecr0
+{
+ volatile uint32_t CECR0; /* CECR0 */
+ volatile uint32_t CSCR0; /* CSCR0 */
+ volatile uint32_t CCBCR0; /* CCBCR0 */
+ volatile uint32_t CNBCR0; /* CNBCR0 */
+};
+
+
+#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */
+
+
+/* Start of channnel array defines of MLB */
+
+/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
+/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
+#define MLB_FROM_CECR0_ARRAY_COUNT 31
+#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
+ &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
+ &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
+ &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
+#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
+#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
+#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
+#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
+#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
+#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
+#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
+#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
+#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
+#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
+#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
+#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
+#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
+#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
+#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
+#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
+#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
+#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
+#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
+#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
+#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
+#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
+#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
+#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
+#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
+#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
+#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
+#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
+#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
+#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
+
+/* End of channnel array defines of MLB */
+
+
+#define MLBDCCR MLB.DCCR
+#define MLBSSCR MLB.SSCR
+#define MLBSDCR MLB.SDCR
+#define MLBSMCR MLB.SMCR
+#define MLBVCCR MLB.VCCR
+#define MLBSBCR MLB.SBCR
+#define MLBABCR MLB.ABCR
+#define MLBCBCR MLB.CBCR
+#define MLBIBCR MLB.IBCR
+#define MLBCICR MLB.CICR
+#define MLBCECR0 MLB.CECR0
+#define MLBCSCR0 MLB.CSCR0
+#define MLBCCBCR0 MLB.CCBCR0
+#define MLBCNBCR0 MLB.CNBCR0
+#define MLBCECR1 MLB.CECR1
+#define MLBCSCR1 MLB.CSCR1
+#define MLBCCBCR1 MLB.CCBCR1
+#define MLBCNBCR1 MLB.CNBCR1
+#define MLBCECR2 MLB.CECR2
+#define MLBCSCR2 MLB.CSCR2
+#define MLBCCBCR2 MLB.CCBCR2
+#define MLBCNBCR2 MLB.CNBCR2
+#define MLBCECR3 MLB.CECR3
+#define MLBCSCR3 MLB.CSCR3
+#define MLBCCBCR3 MLB.CCBCR3
+#define MLBCNBCR3 MLB.CNBCR3
+#define MLBCECR4 MLB.CECR4
+#define MLBCSCR4 MLB.CSCR4
+#define MLBCCBCR4 MLB.CCBCR4
+#define MLBCNBCR4 MLB.CNBCR4
+#define MLBCECR5 MLB.CECR5
+#define MLBCSCR5 MLB.CSCR5
+#define MLBCCBCR5 MLB.CCBCR5
+#define MLBCNBCR5 MLB.CNBCR5
+#define MLBCECR6 MLB.CECR6
+#define MLBCSCR6 MLB.CSCR6
+#define MLBCCBCR6 MLB.CCBCR6
+#define MLBCNBCR6 MLB.CNBCR6
+#define MLBCECR7 MLB.CECR7
+#define MLBCSCR7 MLB.CSCR7
+#define MLBCCBCR7 MLB.CCBCR7
+#define MLBCNBCR7 MLB.CNBCR7
+#define MLBCECR8 MLB.CECR8
+#define MLBCSCR8 MLB.CSCR8
+#define MLBCCBCR8 MLB.CCBCR8
+#define MLBCNBCR8 MLB.CNBCR8
+#define MLBCECR9 MLB.CECR9
+#define MLBCSCR9 MLB.CSCR9
+#define MLBCCBCR9 MLB.CCBCR9
+#define MLBCNBCR9 MLB.CNBCR9
+#define MLBCECR10 MLB.CECR10
+#define MLBCSCR10 MLB.CSCR10
+#define MLBCCBCR10 MLB.CCBCR10
+#define MLBCNBCR10 MLB.CNBCR10
+#define MLBCECR11 MLB.CECR11
+#define MLBCSCR11 MLB.CSCR11
+#define MLBCCBCR11 MLB.CCBCR11
+#define MLBCNBCR11 MLB.CNBCR11
+#define MLBCECR12 MLB.CECR12
+#define MLBCSCR12 MLB.CSCR12
+#define MLBCCBCR12 MLB.CCBCR12
+#define MLBCNBCR12 MLB.CNBCR12
+#define MLBCECR13 MLB.CECR13
+#define MLBCSCR13 MLB.CSCR13
+#define MLBCCBCR13 MLB.CCBCR13
+#define MLBCNBCR13 MLB.CNBCR13
+#define MLBCECR14 MLB.CECR14
+#define MLBCSCR14 MLB.CSCR14
+#define MLBCCBCR14 MLB.CCBCR14
+#define MLBCNBCR14 MLB.CNBCR14
+#define MLBCECR15 MLB.CECR15
+#define MLBCSCR15 MLB.CSCR15
+#define MLBCCBCR15 MLB.CCBCR15
+#define MLBCNBCR15 MLB.CNBCR15
+#define MLBCECR16 MLB.CECR16
+#define MLBCSCR16 MLB.CSCR16
+#define MLBCCBCR16 MLB.CCBCR16
+#define MLBCNBCR16 MLB.CNBCR16
+#define MLBCECR17 MLB.CECR17
+#define MLBCSCR17 MLB.CSCR17
+#define MLBCCBCR17 MLB.CCBCR17
+#define MLBCNBCR17 MLB.CNBCR17
+#define MLBCECR18 MLB.CECR18
+#define MLBCSCR18 MLB.CSCR18
+#define MLBCCBCR18 MLB.CCBCR18
+#define MLBCNBCR18 MLB.CNBCR18
+#define MLBCECR19 MLB.CECR19
+#define MLBCSCR19 MLB.CSCR19
+#define MLBCCBCR19 MLB.CCBCR19
+#define MLBCNBCR19 MLB.CNBCR19
+#define MLBCECR20 MLB.CECR20
+#define MLBCSCR20 MLB.CSCR20
+#define MLBCCBCR20 MLB.CCBCR20
+#define MLBCNBCR20 MLB.CNBCR20
+#define MLBCECR21 MLB.CECR21
+#define MLBCSCR21 MLB.CSCR21
+#define MLBCCBCR21 MLB.CCBCR21
+#define MLBCNBCR21 MLB.CNBCR21
+#define MLBCECR22 MLB.CECR22
+#define MLBCSCR22 MLB.CSCR22
+#define MLBCCBCR22 MLB.CCBCR22
+#define MLBCNBCR22 MLB.CNBCR22
+#define MLBCECR23 MLB.CECR23
+#define MLBCSCR23 MLB.CSCR23
+#define MLBCCBCR23 MLB.CCBCR23
+#define MLBCNBCR23 MLB.CNBCR23
+#define MLBCECR24 MLB.CECR24
+#define MLBCSCR24 MLB.CSCR24
+#define MLBCCBCR24 MLB.CCBCR24
+#define MLBCNBCR24 MLB.CNBCR24
+#define MLBCECR25 MLB.CECR25
+#define MLBCSCR25 MLB.CSCR25
+#define MLBCCBCR25 MLB.CCBCR25
+#define MLBCNBCR25 MLB.CNBCR25
+#define MLBCECR26 MLB.CECR26
+#define MLBCSCR26 MLB.CSCR26
+#define MLBCCBCR26 MLB.CCBCR26
+#define MLBCNBCR26 MLB.CNBCR26
+#define MLBCECR27 MLB.CECR27
+#define MLBCSCR27 MLB.CSCR27
+#define MLBCCBCR27 MLB.CCBCR27
+#define MLBCNBCR27 MLB.CNBCR27
+#define MLBCECR28 MLB.CECR28
+#define MLBCSCR28 MLB.CSCR28
+#define MLBCCBCR28 MLB.CCBCR28
+#define MLBCNBCR28 MLB.CNBCR28
+#define MLBCECR29 MLB.CECR29
+#define MLBCSCR29 MLB.CSCR29
+#define MLBCCBCR29 MLB.CCBCR29
+#define MLBCNBCR29 MLB.CNBCR29
+#define MLBCECR30 MLB.CECR30
+#define MLBCSCR30 MLB.CSCR30
+#define MLBCCBCR30 MLB.CCBCR30
+#define MLBCNBCR30 MLB.CNBCR30
+#define MLBLCBCR0 MLB.LCBCR0
+#define MLBLCBCR1 MLB.LCBCR1
+#define MLBLCBCR2 MLB.LCBCR2
+#define MLBLCBCR3 MLB.LCBCR3
+#define MLBLCBCR4 MLB.LCBCR4
+#define MLBLCBCR5 MLB.LCBCR5
+#define MLBLCBCR6 MLB.LCBCR6
+#define MLBLCBCR7 MLB.LCBCR7
+#define MLBLCBCR8 MLB.LCBCR8
+#define MLBLCBCR9 MLB.LCBCR9
+#define MLBLCBCR10 MLB.LCBCR10
+#define MLBLCBCR11 MLB.LCBCR11
+#define MLBLCBCR12 MLB.LCBCR12
+#define MLBLCBCR13 MLB.LCBCR13
+#define MLBLCBCR14 MLB.LCBCR14
+#define MLBLCBCR15 MLB.LCBCR15
+#define MLBLCBCR16 MLB.LCBCR16
+#define MLBLCBCR17 MLB.LCBCR17
+#define MLBLCBCR18 MLB.LCBCR18
+#define MLBLCBCR19 MLB.LCBCR19
+#define MLBLCBCR20 MLB.LCBCR20
+#define MLBLCBCR21 MLB.LCBCR21
+#define MLBLCBCR22 MLB.LCBCR22
+#define MLBLCBCR23 MLB.LCBCR23
+#define MLBLCBCR24 MLB.LCBCR24
+#define MLBLCBCR25 MLB.LCBCR25
+#define MLBLCBCR26 MLB.LCBCR26
+#define MLBLCBCR27 MLB.LCBCR27
+#define MLBLCBCR28 MLB.LCBCR28
+#define MLBLCBCR29 MLB.LCBCR29
+#define MLBLCBCR30 MLB.LCBCR30
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h
new file mode 100644
index 000000000..43a23670d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h
@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MMC_IODEFINE_H
+#define MMC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mmc
+{ /* MMC */
+ volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
+ volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
+ volatile uint8_t dummy182[4]; /* */
+ volatile uint32_t CE_ARG; /* CE_ARG */
+ volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
+ volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
+ volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
+ volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
+ volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
+#define MMC_CE_RESPn_COUNT 4
+ volatile uint32_t CE_RESP3; /* CE_RESP3 */
+ volatile uint32_t CE_RESP2; /* CE_RESP2 */
+ volatile uint32_t CE_RESP1; /* CE_RESP1 */
+ volatile uint32_t CE_RESP0; /* CE_RESP0 */
+ volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
+ volatile uint32_t CE_DATA; /* CE_DATA */
+ volatile uint8_t dummy183[8]; /* */
+ volatile uint32_t CE_INT; /* CE_INT */
+ volatile uint32_t CE_INT_EN; /* CE_INT_EN */
+ volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
+ volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
+ volatile uint8_t dummy184[12]; /* */
+ volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
+ volatile uint8_t dummy185[16]; /* */
+ volatile uint32_t CE_DETECT; /* CE_DETECT */
+ volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
+ volatile uint8_t dummy186[4]; /* */
+ volatile uint32_t CE_VERSION; /* CE_VERSION */
+};
+
+
+#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
+#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
+#define MMCCE_ARG MMC.CE_ARG
+#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
+#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
+#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
+#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
+#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
+#define MMCCE_RESP3 MMC.CE_RESP3
+#define MMCCE_RESP2 MMC.CE_RESP2
+#define MMCCE_RESP1 MMC.CE_RESP1
+#define MMCCE_RESP0 MMC.CE_RESP0
+#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
+#define MMCCE_DATA MMC.CE_DATA
+#define MMCCE_INT MMC.CE_INT
+#define MMCCE_INT_EN MMC.CE_INT_EN
+#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
+#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
+#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
+#define MMCCE_DETECT MMC.CE_DETECT
+#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
+#define MMCCE_VERSION MMC.CE_VERSION
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h
new file mode 100644
index 000000000..c2d0aeec8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h
@@ -0,0 +1,217 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mtu2_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MTU2_IODEFINE_H
+#define MTU2_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mtu2
+{ /* MTU2 */
+ volatile uint8_t TCR_2; /* TCR_2 */
+ volatile uint8_t TMDR_2; /* TMDR_2 */
+ volatile uint8_t TIOR_2; /* TIOR_2 */
+ volatile uint8_t dummy520[1]; /* */
+ volatile uint8_t TIER_2; /* TIER_2 */
+ volatile uint8_t TSR_2; /* TSR_2 */
+ volatile uint16_t TCNT_2; /* TCNT_2 */
+ volatile uint16_t TGRA_2; /* TGRA_2 */
+ volatile uint16_t TGRB_2; /* TGRB_2 */
+ volatile uint8_t dummy521[500]; /* */
+ volatile uint8_t TCR_3; /* TCR_3 */
+ volatile uint8_t TCR_4; /* TCR_4 */
+ volatile uint8_t TMDR_3; /* TMDR_3 */
+ volatile uint8_t TMDR_4; /* TMDR_4 */
+ volatile uint8_t TIORH_3; /* TIORH_3 */
+ volatile uint8_t TIORL_3; /* TIORL_3 */
+ volatile uint8_t TIORH_4; /* TIORH_4 */
+ volatile uint8_t TIORL_4; /* TIORL_4 */
+ volatile uint8_t TIER_3; /* TIER_3 */
+ volatile uint8_t TIER_4; /* TIER_4 */
+ volatile uint8_t TOER; /* TOER */
+ volatile uint8_t dummy522[2]; /* */
+ volatile uint8_t TGCR; /* TGCR */
+ volatile uint8_t TOCR1; /* TOCR1 */
+ volatile uint8_t TOCR2; /* TOCR2 */
+ volatile uint16_t TCNT_3; /* TCNT_3 */
+ volatile uint16_t TCNT_4; /* TCNT_4 */
+ volatile uint16_t TCDR; /* TCDR */
+ volatile uint16_t TDDR; /* TDDR */
+ volatile uint16_t TGRA_3; /* TGRA_3 */
+ volatile uint16_t TGRB_3; /* TGRB_3 */
+ volatile uint16_t TGRA_4; /* TGRA_4 */
+ volatile uint16_t TGRB_4; /* TGRB_4 */
+ volatile uint16_t TCNTS; /* TCNTS */
+ volatile uint16_t TCBR; /* TCBR */
+ volatile uint16_t TGRC_3; /* TGRC_3 */
+ volatile uint16_t TGRD_3; /* TGRD_3 */
+ volatile uint16_t TGRC_4; /* TGRC_4 */
+ volatile uint16_t TGRD_4; /* TGRD_4 */
+ volatile uint8_t TSR_3; /* TSR_3 */
+ volatile uint8_t TSR_4; /* TSR_4 */
+ volatile uint8_t dummy523[2]; /* */
+ volatile uint8_t TITCR; /* TITCR */
+ volatile uint8_t TITCNT; /* TITCNT */
+ volatile uint8_t TBTER; /* TBTER */
+ volatile uint8_t dummy524[1]; /* */
+ volatile uint8_t TDER; /* TDER */
+ volatile uint8_t dummy525[1]; /* */
+ volatile uint8_t TOLBR; /* TOLBR */
+ volatile uint8_t dummy526[1]; /* */
+ volatile uint8_t TBTM_3; /* TBTM_3 */
+ volatile uint8_t TBTM_4; /* TBTM_4 */
+ volatile uint8_t dummy527[6]; /* */
+ volatile uint16_t TADCR; /* TADCR */
+ volatile uint8_t dummy528[2]; /* */
+ volatile uint16_t TADCORA_4; /* TADCORA_4 */
+ volatile uint16_t TADCORB_4; /* TADCORB_4 */
+ volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
+ volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
+ volatile uint8_t dummy529[20]; /* */
+ volatile uint8_t TWCR; /* TWCR */
+ volatile uint8_t dummy530[31]; /* */
+ volatile uint8_t TSTR; /* TSTR */
+ volatile uint8_t TSYR; /* TSYR */
+ volatile uint8_t dummy531[2]; /* */
+ volatile uint8_t TRWER; /* TRWER */
+ volatile uint8_t dummy532[123]; /* */
+ volatile uint8_t TCR_0; /* TCR_0 */
+ volatile uint8_t TMDR_0; /* TMDR_0 */
+ volatile uint8_t TIORH_0; /* TIORH_0 */
+ volatile uint8_t TIORL_0; /* TIORL_0 */
+ volatile uint8_t TIER_0; /* TIER_0 */
+ volatile uint8_t TSR_0; /* TSR_0 */
+ volatile uint16_t TCNT_0; /* TCNT_0 */
+ volatile uint16_t TGRA_0; /* TGRA_0 */
+ volatile uint16_t TGRB_0; /* TGRB_0 */
+ volatile uint16_t TGRC_0; /* TGRC_0 */
+ volatile uint16_t TGRD_0; /* TGRD_0 */
+ volatile uint8_t dummy533[16]; /* */
+ volatile uint16_t TGRE_0; /* TGRE_0 */
+ volatile uint16_t TGRF_0; /* TGRF_0 */
+ volatile uint8_t TIER2_0; /* TIER2_0 */
+ volatile uint8_t TSR2_0; /* TSR2_0 */
+ volatile uint8_t TBTM_0; /* TBTM_0 */
+ volatile uint8_t dummy534[89]; /* */
+ volatile uint8_t TCR_1; /* TCR_1 */
+ volatile uint8_t TMDR_1; /* TMDR_1 */
+ volatile uint8_t TIOR_1; /* TIOR_1 */
+ volatile uint8_t dummy535[1]; /* */
+ volatile uint8_t TIER_1; /* TIER_1 */
+ volatile uint8_t TSR_1; /* TSR_1 */
+ volatile uint16_t TCNT_1; /* TCNT_1 */
+ volatile uint16_t TGRA_1; /* TGRA_1 */
+ volatile uint16_t TGRB_1; /* TGRB_1 */
+ volatile uint8_t dummy536[4]; /* */
+ volatile uint8_t TICCR; /* TICCR */
+};
+
+
+#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 MTU2.TCR_2
+#define MTU2TMDR_2 MTU2.TMDR_2
+#define MTU2TIOR_2 MTU2.TIOR_2
+#define MTU2TIER_2 MTU2.TIER_2
+#define MTU2TSR_2 MTU2.TSR_2
+#define MTU2TCNT_2 MTU2.TCNT_2
+#define MTU2TGRA_2 MTU2.TGRA_2
+#define MTU2TGRB_2 MTU2.TGRB_2
+#define MTU2TCR_3 MTU2.TCR_3
+#define MTU2TCR_4 MTU2.TCR_4
+#define MTU2TMDR_3 MTU2.TMDR_3
+#define MTU2TMDR_4 MTU2.TMDR_4
+#define MTU2TIORH_3 MTU2.TIORH_3
+#define MTU2TIORL_3 MTU2.TIORL_3
+#define MTU2TIORH_4 MTU2.TIORH_4
+#define MTU2TIORL_4 MTU2.TIORL_4
+#define MTU2TIER_3 MTU2.TIER_3
+#define MTU2TIER_4 MTU2.TIER_4
+#define MTU2TOER MTU2.TOER
+#define MTU2TGCR MTU2.TGCR
+#define MTU2TOCR1 MTU2.TOCR1
+#define MTU2TOCR2 MTU2.TOCR2
+#define MTU2TCNT_3 MTU2.TCNT_3
+#define MTU2TCNT_4 MTU2.TCNT_4
+#define MTU2TCDR MTU2.TCDR
+#define MTU2TDDR MTU2.TDDR
+#define MTU2TGRA_3 MTU2.TGRA_3
+#define MTU2TGRB_3 MTU2.TGRB_3
+#define MTU2TGRA_4 MTU2.TGRA_4
+#define MTU2TGRB_4 MTU2.TGRB_4
+#define MTU2TCNTS MTU2.TCNTS
+#define MTU2TCBR MTU2.TCBR
+#define MTU2TGRC_3 MTU2.TGRC_3
+#define MTU2TGRD_3 MTU2.TGRD_3
+#define MTU2TGRC_4 MTU2.TGRC_4
+#define MTU2TGRD_4 MTU2.TGRD_4
+#define MTU2TSR_3 MTU2.TSR_3
+#define MTU2TSR_4 MTU2.TSR_4
+#define MTU2TITCR MTU2.TITCR
+#define MTU2TITCNT MTU2.TITCNT
+#define MTU2TBTER MTU2.TBTER
+#define MTU2TDER MTU2.TDER
+#define MTU2TOLBR MTU2.TOLBR
+#define MTU2TBTM_3 MTU2.TBTM_3
+#define MTU2TBTM_4 MTU2.TBTM_4
+#define MTU2TADCR MTU2.TADCR
+#define MTU2TADCORA_4 MTU2.TADCORA_4
+#define MTU2TADCORB_4 MTU2.TADCORB_4
+#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
+#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
+#define MTU2TWCR MTU2.TWCR
+#define MTU2TSTR MTU2.TSTR
+#define MTU2TSYR MTU2.TSYR
+#define MTU2TRWER MTU2.TRWER
+#define MTU2TCR_0 MTU2.TCR_0
+#define MTU2TMDR_0 MTU2.TMDR_0
+#define MTU2TIORH_0 MTU2.TIORH_0
+#define MTU2TIORL_0 MTU2.TIORL_0
+#define MTU2TIER_0 MTU2.TIER_0
+#define MTU2TSR_0 MTU2.TSR_0
+#define MTU2TCNT_0 MTU2.TCNT_0
+#define MTU2TGRA_0 MTU2.TGRA_0
+#define MTU2TGRB_0 MTU2.TGRB_0
+#define MTU2TGRC_0 MTU2.TGRC_0
+#define MTU2TGRD_0 MTU2.TGRD_0
+#define MTU2TGRE_0 MTU2.TGRE_0
+#define MTU2TGRF_0 MTU2.TGRF_0
+#define MTU2TIER2_0 MTU2.TIER2_0
+#define MTU2TSR2_0 MTU2.TSR2_0
+#define MTU2TBTM_0 MTU2.TBTM_0
+#define MTU2TCR_1 MTU2.TCR_1
+#define MTU2TMDR_1 MTU2.TMDR_1
+#define MTU2TIOR_1 MTU2.TIOR_1
+#define MTU2TIER_1 MTU2.TIER_1
+#define MTU2TSR_1 MTU2.TSR_1
+#define MTU2TCNT_1 MTU2.TCNT_1
+#define MTU2TGRA_1 MTU2.TGRA_1
+#define MTU2TGRB_1 MTU2.TGRB_1
+#define MTU2TICCR MTU2.TICCR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h
new file mode 100644
index 000000000..b0aa5587d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef OSTM_IODEFINE_H
+#define OSTM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ostm
+{ /* OSTM */
+ volatile uint32_t OSTMnCMP; /* OSTMnCMP */
+ volatile uint32_t OSTMnCNT; /* OSTMnCNT */
+ volatile uint8_t dummy1[8]; /* */
+ volatile uint8_t OSTMnTE; /* OSTMnTE */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint8_t OSTMnTS; /* OSTMnTS */
+ volatile uint8_t dummy3[3]; /* */
+ volatile uint8_t OSTMnTT; /* OSTMnTT */
+ volatile uint8_t dummy4[7]; /* */
+ volatile uint8_t OSTMnCTL; /* OSTMnCTL */
+};
+
+
+#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channnel array defines of OSTM */
+
+/* Channnel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT 2
+#define OSTM_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &OSTM0, &OSTM1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of OSTM */
+
+
+#define OSTM0CMP OSTM0.OSTMnCMP
+#define OSTM0CNT OSTM0.OSTMnCNT
+#define OSTM0TE OSTM0.OSTMnTE
+#define OSTM0TS OSTM0.OSTMnTS
+#define OSTM0TT OSTM0.OSTMnTT
+#define OSTM0CTL OSTM0.OSTMnCTL
+#define OSTM1CMP OSTM1.OSTMnCMP
+#define OSTM1CNT OSTM1.OSTMnCNT
+#define OSTM1TE OSTM1.OSTMnTE
+#define OSTM1TS OSTM1.OSTMnTS
+#define OSTM1TT OSTM1.OSTMnTT
+#define OSTM1CTL OSTM1.OSTMnCTL
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h
new file mode 100644
index 000000000..230dd6294
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h
@@ -0,0 +1,150 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pfv_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PFV_IODEFINE_H
+#define PFV_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_pfv
+{ /* PFV */
+ volatile uint32_t PFVCR; /* PFVCR */
+ volatile uint32_t PFVICR; /* PFVICR */
+ volatile uint32_t PFVISR; /* PFVISR */
+ volatile uint8_t dummy1[20]; /* */
+#define PFVID_COUNT 8
+ volatile uint32_t PFVID0; /* PFVID0 */
+ volatile uint32_t PFVID1; /* PFVID1 */
+ volatile uint32_t PFVID2; /* PFVID2 */
+ volatile uint32_t PFVID3; /* PFVID3 */
+ volatile uint32_t PFVID4; /* PFVID4 */
+ volatile uint32_t PFVID5; /* PFVID5 */
+ volatile uint32_t PFVID6; /* PFVID6 */
+ volatile uint32_t PFVID7; /* PFVID7 */
+#define PFVOD_COUNT 8
+ volatile uint32_t PFVOD0; /* PFVOD0 */
+ volatile uint32_t PFVOD1; /* PFVOD1 */
+ volatile uint32_t PFVOD2; /* PFVOD2 */
+ volatile uint32_t PFVOD3; /* PFVOD3 */
+ volatile uint32_t PFVOD4; /* PFVOD4 */
+ volatile uint32_t PFVOD5; /* PFVOD5 */
+ volatile uint32_t PFVOD6; /* PFVOD6 */
+ volatile uint32_t PFVOD7; /* PFVOD7 */
+ volatile uint8_t dummy2[4]; /* */
+ volatile uint32_t PFVIFSR; /* PFVIFSR */
+ volatile uint32_t PFVOFSR; /* PFVOFSR */
+ volatile uint32_t PFVACR; /* PFVACR */
+ volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
+ volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
+ volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
+ volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
+ volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
+ volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
+ volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
+ volatile uint32_t PFVSZR; /* PFVSZR */
+};
+
+
+#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
+#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channnel array defines of PFV */
+
+/* Channnel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT 2
+#define PFV_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &PFV0, &PFV1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of PFV */
+
+
+#define PFV0PFVCR PFV0.PFVCR
+#define PFV0PFVICR PFV0.PFVICR
+#define PFV0PFVISR PFV0.PFVISR
+#define PFV0PFVID0 PFV0.PFVID0
+#define PFV0PFVID1 PFV0.PFVID1
+#define PFV0PFVID2 PFV0.PFVID2
+#define PFV0PFVID3 PFV0.PFVID3
+#define PFV0PFVID4 PFV0.PFVID4
+#define PFV0PFVID5 PFV0.PFVID5
+#define PFV0PFVID6 PFV0.PFVID6
+#define PFV0PFVID7 PFV0.PFVID7
+#define PFV0PFVOD0 PFV0.PFVOD0
+#define PFV0PFVOD1 PFV0.PFVOD1
+#define PFV0PFVOD2 PFV0.PFVOD2
+#define PFV0PFVOD3 PFV0.PFVOD3
+#define PFV0PFVOD4 PFV0.PFVOD4
+#define PFV0PFVOD5 PFV0.PFVOD5
+#define PFV0PFVOD6 PFV0.PFVOD6
+#define PFV0PFVOD7 PFV0.PFVOD7
+#define PFV0PFVIFSR PFV0.PFVIFSR
+#define PFV0PFVOFSR PFV0.PFVOFSR
+#define PFV0PFVACR PFV0.PFVACR
+#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
+#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
+#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
+#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
+#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
+#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
+#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
+#define PFV0PFVSZR PFV0.PFVSZR
+#define PFV1PFVCR PFV1.PFVCR
+#define PFV1PFVICR PFV1.PFVICR
+#define PFV1PFVISR PFV1.PFVISR
+#define PFV1PFVID0 PFV1.PFVID0
+#define PFV1PFVID1 PFV1.PFVID1
+#define PFV1PFVID2 PFV1.PFVID2
+#define PFV1PFVID3 PFV1.PFVID3
+#define PFV1PFVID4 PFV1.PFVID4
+#define PFV1PFVID5 PFV1.PFVID5
+#define PFV1PFVID6 PFV1.PFVID6
+#define PFV1PFVID7 PFV1.PFVID7
+#define PFV1PFVOD0 PFV1.PFVOD0
+#define PFV1PFVOD1 PFV1.PFVOD1
+#define PFV1PFVOD2 PFV1.PFVOD2
+#define PFV1PFVOD3 PFV1.PFVOD3
+#define PFV1PFVOD4 PFV1.PFVOD4
+#define PFV1PFVOD5 PFV1.PFVOD5
+#define PFV1PFVOD6 PFV1.PFVOD6
+#define PFV1PFVOD7 PFV1.PFVOD7
+#define PFV1PFVIFSR PFV1.PFVIFSR
+#define PFV1PFVOFSR PFV1.PFVOFSR
+#define PFV1PFVACR PFV1.PFVACR
+#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
+#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
+#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
+#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
+#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
+#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
+#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
+#define PFV1PFVSZR PFV1.PFVSZR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h
new file mode 100644
index 000000000..a7143d481
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pwm_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PWM_IODEFINE_H
+#define PWM_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+union reg16_8_t
+{
+ volatile uint16_t UINT16; /* 16-bit Access */
+ volatile uint8_t UINT8[2]; /* 8-bit Access */
+};
+
+struct st_pwm
+{ /* PWM */
+ volatile uint8_t dummy559[2]; /* */
+ union reg16_8_t PWBTCR; /* PWBTCR */
+
+ volatile uint8_t dummy560[216]; /* */
+
+/* start of struct st_pwm_common */
+ union reg16_8_t PWCR_1; /* PWCR_1 */
+
+ volatile uint8_t dummy561[2]; /* */
+ union reg16_8_t PWPR_1; /* PWPR_1 */
+
+ volatile uint16_t PWCYR_1; /* PWCYR_1 */
+ volatile uint16_t PWBFR_1A; /* PWBFR_1A */
+ volatile uint16_t PWBFR_1C; /* PWBFR_1C */
+ volatile uint16_t PWBFR_1E; /* PWBFR_1E */
+ volatile uint16_t PWBFR_1G; /* PWBFR_1G */
+/* end of struct st_pwm_common */
+
+/* start of struct st_pwm_common */
+ union reg16_8_t PWCR_2; /* PWCR_2 */
+
+ volatile uint8_t dummy562[2]; /* */
+ union reg16_8_t PWPR_2; /* PWPR_2 */
+
+ volatile uint16_t PWCYR_2; /* PWCYR_2 */
+ volatile uint16_t PWBFR_2A; /* PWBFR_2A */
+ volatile uint16_t PWBFR_2C; /* PWBFR_2C */
+ volatile uint16_t PWBFR_2E; /* PWBFR_2E */
+ volatile uint16_t PWBFR_2G; /* PWBFR_2G */
+/* end of struct st_pwm_common */
+};
+
+
+struct st_pwm_common
+{
+ union reg16_8_t PWCR_1; /* PWCR_1 */
+
+ volatile uint8_t dummy572[2]; /* */
+ union reg16_8_t PWPR_1; /* PWPR_1 */
+
+ volatile uint16_t PWCYR_1; /* PWCYR_1 */
+ volatile uint16_t PWBFR_1A; /* PWBFR_1A */
+ volatile uint16_t PWBFR_1C; /* PWBFR_1C */
+ volatile uint16_t PWBFR_1E; /* PWBFR_1E */
+ volatile uint16_t PWBFR_1G; /* PWBFR_1G */
+};
+
+
+#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
+
+
+/* Start of channnel array defines of PWM */
+
+/* Channnel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
+#define PWMn_COUNT 2
+#define PWMn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &PWM1, &PWM2 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
+#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
+
+/* End of channnel array defines of PWM */
+
+
+#define PWMPWBTCR PWM.PWBTCR.UINT16
+#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
+#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
+#define PWMPWCR_1 PWM.PWCR_1.UINT16
+#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
+#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
+#define PWMPWPR_1 PWM.PWPR_1.UINT16
+#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
+#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
+#define PWMPWCYR_1 PWM.PWCYR_1
+#define PWMPWBFR_1A PWM.PWBFR_1A
+#define PWMPWBFR_1C PWM.PWBFR_1C
+#define PWMPWBFR_1E PWM.PWBFR_1E
+#define PWMPWBFR_1G PWM.PWBFR_1G
+#define PWMPWCR_2 PWM.PWCR_2.UINT16
+#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
+#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
+#define PWMPWPR_2 PWM.PWPR_2.UINT16
+#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
+#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
+#define PWMPWCYR_2 PWM.PWCYR_2
+#define PWMPWBFR_2A PWM.PWBFR_2A
+#define PWMPWBFR_2C PWM.PWBFR_2C
+#define PWMPWBFR_2E PWM.PWBFR_2E
+#define PWMPWBFR_2G PWM.PWBFR_2G
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h
new file mode 100644
index 000000000..9daefe447
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h
@@ -0,0 +1,556 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RIIC_IODEFINE_H
+#define RIIC_IODEFINE_H
+
+#include "reg32_t.h"
+
+struct st_riic
+{ /* RIIC */
+#define RIICnCRm_COUNT 2
+ union reg32_t RIICnCR1; /* RIICnCR1 */
+ union reg32_t RIICnCR2; /* RIICnCR2 */
+#define RIICnMRm_COUNT 3
+ union reg32_t RIICnMR1; /* RIICnMR1 */
+ union reg32_t RIICnMR2; /* RIICnMR2 */
+ union reg32_t RIICnMR3; /* RIICnMR3 */
+ union reg32_t RIICnFER; /* RIICnFER */
+ union reg32_t RIICnSER; /* RIICnSER */
+ union reg32_t RIICnIER; /* RIICnIER */
+#define RIICnSRm_COUNT 2
+ union reg32_t RIICnSR1; /* RIICnSR1 */
+ union reg32_t RIICnSR2; /* RIICnSR2 */
+#define RIICnSARm_COUNT 3
+ union reg32_t RIICnSAR0; /* RIICnSAR0 */
+ union reg32_t RIICnSAR1; /* RIICnSAR1 */
+ union reg32_t RIICnSAR2; /* RIICnSAR2 */
+ union reg32_t RIICnBRL; /* RIICnBRL */
+ union reg32_t RIICnBRH; /* RIICnBRH */
+ union reg32_t RIICnDRT; /* RIICnDRT */
+ union reg32_t RIICnDRR; /* RIICnDRR */
+
+};
+
+
+#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */
+#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */
+#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */
+#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */
+
+
+/* Start of channnel array defines of RIIC */
+
+/* Channnel array defines of RIIC */
+/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
+#define RIIC_COUNT 4
+#define RIIC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RIIC */
+
+
+#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
+#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
+#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
+#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
+#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
+#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
+#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
+#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
+#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
+#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
+#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
+#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
+#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
+#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
+#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
+#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
+#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
+#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
+#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
+#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
+#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
+#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
+#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
+#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
+#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
+#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
+#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
+#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
+#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
+#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
+#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
+#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
+#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
+#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
+#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
+#define RIIC0FER RIIC0.RIICnFER.UINT32
+#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
+#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
+#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
+#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
+#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
+#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
+#define RIIC0SER RIIC0.RIICnSER.UINT32
+#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
+#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
+#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
+#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
+#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
+#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
+#define RIIC0IER RIIC0.RIICnIER.UINT32
+#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
+#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
+#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
+#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
+#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
+#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
+#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
+#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
+#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
+#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
+#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
+#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
+#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
+#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
+#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
+#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
+#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
+#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
+#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
+#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
+#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
+#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
+#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
+#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
+#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
+#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
+#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
+#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
+#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
+#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
+#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
+#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
+#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
+#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
+#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
+#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
+#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
+#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
+#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
+#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
+#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
+#define RIIC0BRL RIIC0.RIICnBRL.UINT32
+#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
+#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
+#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
+#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
+#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
+#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
+#define RIIC0BRH RIIC0.RIICnBRH.UINT32
+#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
+#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
+#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
+#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
+#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
+#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
+#define RIIC0DRT RIIC0.RIICnDRT.UINT32
+#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
+#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
+#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
+#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
+#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
+#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
+#define RIIC0DRR RIIC0.RIICnDRR.UINT32
+#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
+#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
+#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
+#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
+#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
+#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
+#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
+#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
+#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
+#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
+#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
+#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
+#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
+#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
+#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
+#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
+#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
+#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
+#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
+#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
+#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
+#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
+#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
+#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
+#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
+#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
+#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
+#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
+#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
+#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
+#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
+#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
+#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
+#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
+#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
+#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
+#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
+#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
+#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
+#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
+#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
+#define RIIC1FER RIIC1.RIICnFER.UINT32
+#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
+#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
+#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
+#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
+#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
+#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
+#define RIIC1SER RIIC1.RIICnSER.UINT32
+#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
+#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
+#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
+#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
+#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
+#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
+#define RIIC1IER RIIC1.RIICnIER.UINT32
+#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
+#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
+#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
+#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
+#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
+#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
+#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
+#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
+#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
+#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
+#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
+#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
+#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
+#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
+#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
+#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
+#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
+#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
+#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
+#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
+#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
+#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
+#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
+#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
+#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
+#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
+#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
+#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
+#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
+#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
+#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
+#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
+#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
+#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
+#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
+#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
+#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
+#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
+#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
+#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
+#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
+#define RIIC1BRL RIIC1.RIICnBRL.UINT32
+#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
+#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
+#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
+#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
+#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
+#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
+#define RIIC1BRH RIIC1.RIICnBRH.UINT32
+#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
+#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
+#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
+#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
+#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
+#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
+#define RIIC1DRT RIIC1.RIICnDRT.UINT32
+#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
+#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
+#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
+#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
+#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
+#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
+#define RIIC1DRR RIIC1.RIICnDRR.UINT32
+#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
+#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
+#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
+#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
+#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
+#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
+#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
+#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
+#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
+#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
+#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
+#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
+#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
+#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
+#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
+#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
+#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
+#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
+#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
+#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
+#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
+#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
+#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
+#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
+#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
+#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
+#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
+#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
+#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
+#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
+#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
+#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
+#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
+#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
+#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
+#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
+#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
+#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
+#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
+#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
+#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
+#define RIIC2FER RIIC2.RIICnFER.UINT32
+#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
+#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
+#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
+#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
+#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
+#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
+#define RIIC2SER RIIC2.RIICnSER.UINT32
+#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
+#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
+#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
+#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
+#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
+#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
+#define RIIC2IER RIIC2.RIICnIER.UINT32
+#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
+#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
+#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
+#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
+#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
+#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
+#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
+#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
+#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
+#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
+#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
+#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
+#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
+#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
+#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
+#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
+#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
+#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
+#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
+#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
+#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
+#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
+#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
+#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
+#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
+#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
+#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
+#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
+#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
+#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
+#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
+#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
+#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
+#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
+#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
+#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
+#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
+#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
+#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
+#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
+#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
+#define RIIC2BRL RIIC2.RIICnBRL.UINT32
+#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
+#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
+#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
+#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
+#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
+#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
+#define RIIC2BRH RIIC2.RIICnBRH.UINT32
+#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
+#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
+#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
+#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
+#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
+#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
+#define RIIC2DRT RIIC2.RIICnDRT.UINT32
+#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
+#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
+#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
+#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
+#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
+#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
+#define RIIC2DRR RIIC2.RIICnDRR.UINT32
+#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
+#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
+#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
+#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
+#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
+#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
+#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
+#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
+#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
+#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
+#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
+#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
+#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
+#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
+#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
+#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
+#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
+#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
+#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
+#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
+#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
+#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
+#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
+#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
+#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
+#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
+#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
+#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
+#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
+#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
+#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
+#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
+#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
+#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
+#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
+#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
+#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
+#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
+#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
+#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
+#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
+#define RIIC3FER RIIC3.RIICnFER.UINT32
+#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
+#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
+#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
+#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
+#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
+#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
+#define RIIC3SER RIIC3.RIICnSER.UINT32
+#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
+#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
+#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
+#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
+#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
+#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
+#define RIIC3IER RIIC3.RIICnIER.UINT32
+#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
+#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
+#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
+#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
+#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
+#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
+#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
+#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
+#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
+#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
+#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
+#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
+#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
+#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
+#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
+#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
+#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
+#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
+#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
+#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
+#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
+#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
+#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
+#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
+#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
+#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
+#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
+#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
+#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
+#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
+#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
+#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
+#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
+#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
+#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
+#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
+#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
+#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
+#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
+#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
+#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
+#define RIIC3BRL RIIC3.RIICnBRL.UINT32
+#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
+#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
+#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
+#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
+#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
+#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
+#define RIIC3BRH RIIC3.RIICnBRH.UINT32
+#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
+#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
+#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
+#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
+#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
+#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
+#define RIIC3DRT RIIC3.RIICnDRT.UINT32
+#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
+#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
+#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
+#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
+#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
+#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
+#define RIIC3DRR RIIC3.RIICnDRR.UINT32
+#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
+#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
+#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
+#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
+#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
+#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h
new file mode 100644
index 000000000..cfcfda568
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h
@@ -0,0 +1,166 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : romdec_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ROMDEC_IODEFINE_H
+#define ROMDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_romdec
+{ /* ROMDEC */
+ volatile uint8_t CROMEN; /* CROMEN */
+ volatile uint8_t CROMSY0; /* CROMSY0 */
+#define ROMDEC_CROMCTL0_COUNT 2
+ volatile uint8_t CROMCTL0; /* CROMCTL0 */
+ volatile uint8_t CROMCTL1; /* CROMCTL1 */
+ volatile uint8_t dummy23[1]; /* */
+ volatile uint8_t CROMCTL3; /* CROMCTL3 */
+ volatile uint8_t CROMCTL4; /* CROMCTL4 */
+ volatile uint8_t CROMCTL5; /* CROMCTL5 */
+#define ROMDEC_CROMST0_COUNT 2
+ volatile uint8_t CROMST0; /* CROMST0 */
+ volatile uint8_t CROMST1; /* CROMST1 */
+ volatile uint8_t dummy24[1]; /* */
+ volatile uint8_t CROMST3; /* CROMST3 */
+ volatile uint8_t CROMST4; /* CROMST4 */
+ volatile uint8_t CROMST5; /* CROMST5 */
+ volatile uint8_t CROMST6; /* CROMST6 */
+ volatile uint8_t dummy25[5]; /* */
+#define ROMDEC_CBUFST0_COUNT 3
+ volatile uint8_t CBUFST0; /* CBUFST0 */
+ volatile uint8_t CBUFST1; /* CBUFST1 */
+ volatile uint8_t CBUFST2; /* CBUFST2 */
+ volatile uint8_t dummy26[1]; /* */
+#define ROMDEC_HEAD00_COUNT 4
+ volatile uint8_t HEAD00; /* HEAD00 */
+ volatile uint8_t HEAD01; /* HEAD01 */
+ volatile uint8_t HEAD02; /* HEAD02 */
+ volatile uint8_t HEAD03; /* HEAD03 */
+#define ROMDEC_SHEAD00_COUNT 8
+ volatile uint8_t SHEAD00; /* SHEAD00 */
+ volatile uint8_t SHEAD01; /* SHEAD01 */
+ volatile uint8_t SHEAD02; /* SHEAD02 */
+ volatile uint8_t SHEAD03; /* SHEAD03 */
+ volatile uint8_t SHEAD04; /* SHEAD04 */
+ volatile uint8_t SHEAD05; /* SHEAD05 */
+ volatile uint8_t SHEAD06; /* SHEAD06 */
+ volatile uint8_t SHEAD07; /* SHEAD07 */
+#define ROMDEC_HEAD20_COUNT 4
+ volatile uint8_t HEAD20; /* HEAD20 */
+ volatile uint8_t HEAD21; /* HEAD21 */
+ volatile uint8_t HEAD22; /* HEAD22 */
+ volatile uint8_t HEAD23; /* HEAD23 */
+#define ROMDEC_SHEAD20_COUNT 8
+ volatile uint8_t SHEAD20; /* SHEAD20 */
+ volatile uint8_t SHEAD21; /* SHEAD21 */
+ volatile uint8_t SHEAD22; /* SHEAD22 */
+ volatile uint8_t SHEAD23; /* SHEAD23 */
+ volatile uint8_t SHEAD24; /* SHEAD24 */
+ volatile uint8_t SHEAD25; /* SHEAD25 */
+ volatile uint8_t SHEAD26; /* SHEAD26 */
+ volatile uint8_t SHEAD27; /* SHEAD27 */
+ volatile uint8_t dummy27[16]; /* */
+#define ROMDEC_CBUFCTL0_COUNT 4
+ volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
+ volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
+ volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
+ volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
+ volatile uint8_t dummy28[1]; /* */
+ volatile uint8_t CROMST0M; /* CROMST0M */
+ volatile uint8_t dummy29[186]; /* */
+ volatile uint8_t ROMDECRST; /* ROMDECRST */
+ volatile uint8_t RSTSTAT; /* RSTSTAT */
+ volatile uint8_t SSI; /* SSI */
+ volatile uint8_t dummy30[5]; /* */
+ volatile uint8_t INTHOLD; /* INTHOLD */
+ volatile uint8_t INHINT; /* INHINT */
+ volatile uint8_t dummy31[246]; /* */
+#define ROMDEC_STRMDIN0_COUNT 2
+ volatile uint16_t STRMDIN0; /* STRMDIN0 */
+ volatile uint16_t STRMDIN2; /* STRMDIN2 */
+ volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
+};
+
+
+#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN ROMDEC.CROMEN
+#define ROMDECCROMSY0 ROMDEC.CROMSY0
+#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
+#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
+#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
+#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
+#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
+#define ROMDECCROMST0 ROMDEC.CROMST0
+#define ROMDECCROMST1 ROMDEC.CROMST1
+#define ROMDECCROMST3 ROMDEC.CROMST3
+#define ROMDECCROMST4 ROMDEC.CROMST4
+#define ROMDECCROMST5 ROMDEC.CROMST5
+#define ROMDECCROMST6 ROMDEC.CROMST6
+#define ROMDECCBUFST0 ROMDEC.CBUFST0
+#define ROMDECCBUFST1 ROMDEC.CBUFST1
+#define ROMDECCBUFST2 ROMDEC.CBUFST2
+#define ROMDECHEAD00 ROMDEC.HEAD00
+#define ROMDECHEAD01 ROMDEC.HEAD01
+#define ROMDECHEAD02 ROMDEC.HEAD02
+#define ROMDECHEAD03 ROMDEC.HEAD03
+#define ROMDECSHEAD00 ROMDEC.SHEAD00
+#define ROMDECSHEAD01 ROMDEC.SHEAD01
+#define ROMDECSHEAD02 ROMDEC.SHEAD02
+#define ROMDECSHEAD03 ROMDEC.SHEAD03
+#define ROMDECSHEAD04 ROMDEC.SHEAD04
+#define ROMDECSHEAD05 ROMDEC.SHEAD05
+#define ROMDECSHEAD06 ROMDEC.SHEAD06
+#define ROMDECSHEAD07 ROMDEC.SHEAD07
+#define ROMDECHEAD20 ROMDEC.HEAD20
+#define ROMDECHEAD21 ROMDEC.HEAD21
+#define ROMDECHEAD22 ROMDEC.HEAD22
+#define ROMDECHEAD23 ROMDEC.HEAD23
+#define ROMDECSHEAD20 ROMDEC.SHEAD20
+#define ROMDECSHEAD21 ROMDEC.SHEAD21
+#define ROMDECSHEAD22 ROMDEC.SHEAD22
+#define ROMDECSHEAD23 ROMDEC.SHEAD23
+#define ROMDECSHEAD24 ROMDEC.SHEAD24
+#define ROMDECSHEAD25 ROMDEC.SHEAD25
+#define ROMDECSHEAD26 ROMDEC.SHEAD26
+#define ROMDECSHEAD27 ROMDEC.SHEAD27
+#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
+#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
+#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
+#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
+#define ROMDECCROMST0M ROMDEC.CROMST0M
+#define ROMDECROMDECRST ROMDEC.ROMDECRST
+#define ROMDECRSTSTAT ROMDEC.RSTSTAT
+#define ROMDECSSI ROMDEC.SSI
+#define ROMDECINTHOLD ROMDEC.INTHOLD
+#define ROMDECINHINT ROMDEC.INHINT
+#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
+#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
+#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h
new file mode 100644
index 000000000..1698f027c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h
@@ -0,0 +1,9038 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rscan0_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSCAN0_IODEFINE_H
+#define RSCAN0_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rscan0
+{ /* RSCAN0 */
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C0CFG; /* C0CFG */
+ union iodefine_reg32_t C0CTR; /* C0CTR */
+ union iodefine_reg32_t C0STS; /* C0STS */
+ union iodefine_reg32_t C0ERFL; /* C0ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C1CFG; /* C1CFG */
+ union iodefine_reg32_t C1CTR; /* C1CTR */
+ union iodefine_reg32_t C1STS; /* C1STS */
+ union iodefine_reg32_t C1ERFL; /* C1ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C2CFG; /* C2CFG */
+ union iodefine_reg32_t C2CTR; /* C2CTR */
+ union iodefine_reg32_t C2STS; /* C2STS */
+ union iodefine_reg32_t C2ERFL; /* C2ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C3CFG; /* C3CFG */
+ union iodefine_reg32_t C3CTR; /* C3CTR */
+ union iodefine_reg32_t C3STS; /* C3STS */
+ union iodefine_reg32_t C3ERFL; /* C3ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C4CFG; /* C4CFG */
+ union iodefine_reg32_t C4CTR; /* C4CTR */
+ union iodefine_reg32_t C4STS; /* C4STS */
+ union iodefine_reg32_t C4ERFL; /* C4ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+ volatile uint8_t dummy159[52]; /* */
+ union iodefine_reg32_t GCFG; /* GCFG */
+ union iodefine_reg32_t GCTR; /* GCTR */
+ union iodefine_reg32_t GSTS; /* GSTS */
+ union iodefine_reg32_t GERFL; /* GERFL */
+ union iodefine_reg32_16_t GTSC; /* GTSC */
+ union iodefine_reg32_t GAFLECTR; /* GAFLECTR */
+#define RSCAN0_GAFLCFG0_COUNT 2
+ union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */
+ union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */
+ union iodefine_reg32_t RMNB; /* RMNB */
+#define RSCAN0_RMND0_COUNT 3
+ union iodefine_reg32_t RMND0; /* RMND0 */
+ union iodefine_reg32_t RMND1; /* RMND1 */
+ union iodefine_reg32_t RMND2; /* RMND2 */
+
+ volatile uint8_t dummy160[4]; /* */
+#define RSCAN0_RFCC0_COUNT 8
+ union iodefine_reg32_t RFCC0; /* RFCC0 */
+ union iodefine_reg32_t RFCC1; /* RFCC1 */
+ union iodefine_reg32_t RFCC2; /* RFCC2 */
+ union iodefine_reg32_t RFCC3; /* RFCC3 */
+ union iodefine_reg32_t RFCC4; /* RFCC4 */
+ union iodefine_reg32_t RFCC5; /* RFCC5 */
+ union iodefine_reg32_t RFCC6; /* RFCC6 */
+ union iodefine_reg32_t RFCC7; /* RFCC7 */
+#define RSCAN0_RFSTS0_COUNT 8
+ union iodefine_reg32_t RFSTS0; /* RFSTS0 */
+ union iodefine_reg32_t RFSTS1; /* RFSTS1 */
+ union iodefine_reg32_t RFSTS2; /* RFSTS2 */
+ union iodefine_reg32_t RFSTS3; /* RFSTS3 */
+ union iodefine_reg32_t RFSTS4; /* RFSTS4 */
+ union iodefine_reg32_t RFSTS5; /* RFSTS5 */
+ union iodefine_reg32_t RFSTS6; /* RFSTS6 */
+ union iodefine_reg32_t RFSTS7; /* RFSTS7 */
+#define RSCAN0_RFPCTR0_COUNT 8
+ union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */
+ union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */
+ union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */
+ union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */
+ union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */
+ union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */
+ union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */
+ union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */
+#define RSCAN0_CFCC0_COUNT 15
+ union iodefine_reg32_t CFCC0; /* CFCC0 */
+ union iodefine_reg32_t CFCC1; /* CFCC1 */
+ union iodefine_reg32_t CFCC2; /* CFCC2 */
+ union iodefine_reg32_t CFCC3; /* CFCC3 */
+ union iodefine_reg32_t CFCC4; /* CFCC4 */
+ union iodefine_reg32_t CFCC5; /* CFCC5 */
+ union iodefine_reg32_t CFCC6; /* CFCC6 */
+ union iodefine_reg32_t CFCC7; /* CFCC7 */
+ union iodefine_reg32_t CFCC8; /* CFCC8 */
+ union iodefine_reg32_t CFCC9; /* CFCC9 */
+ union iodefine_reg32_t CFCC10; /* CFCC10 */
+ union iodefine_reg32_t CFCC11; /* CFCC11 */
+ union iodefine_reg32_t CFCC12; /* CFCC12 */
+ union iodefine_reg32_t CFCC13; /* CFCC13 */
+ union iodefine_reg32_t CFCC14; /* CFCC14 */
+
+ volatile uint8_t dummy161[36]; /* */
+#define RSCAN0_CFSTS0_COUNT 15
+ union iodefine_reg32_t CFSTS0; /* CFSTS0 */
+ union iodefine_reg32_t CFSTS1; /* CFSTS1 */
+ union iodefine_reg32_t CFSTS2; /* CFSTS2 */
+ union iodefine_reg32_t CFSTS3; /* CFSTS3 */
+ union iodefine_reg32_t CFSTS4; /* CFSTS4 */
+ union iodefine_reg32_t CFSTS5; /* CFSTS5 */
+ union iodefine_reg32_t CFSTS6; /* CFSTS6 */
+ union iodefine_reg32_t CFSTS7; /* CFSTS7 */
+ union iodefine_reg32_t CFSTS8; /* CFSTS8 */
+ union iodefine_reg32_t CFSTS9; /* CFSTS9 */
+ union iodefine_reg32_t CFSTS10; /* CFSTS10 */
+ union iodefine_reg32_t CFSTS11; /* CFSTS11 */
+ union iodefine_reg32_t CFSTS12; /* CFSTS12 */
+ union iodefine_reg32_t CFSTS13; /* CFSTS13 */
+ union iodefine_reg32_t CFSTS14; /* CFSTS14 */
+
+ volatile uint8_t dummy162[36]; /* */
+#define RSCAN0_CFPCTR0_COUNT 15
+ union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */
+ union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */
+ union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */
+ union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */
+ union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */
+ union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */
+ union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */
+ union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */
+ union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */
+ union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */
+ union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */
+ union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */
+ union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */
+ union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */
+ union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */
+
+ volatile uint8_t dummy163[36]; /* */
+ union iodefine_reg32_t FESTS; /* FESTS */
+ union iodefine_reg32_t FFSTS; /* FFSTS */
+ union iodefine_reg32_t FMSTS; /* FMSTS */
+ union iodefine_reg32_t RFISTS; /* RFISTS */
+ union iodefine_reg32_t CFRISTS; /* CFRISTS */
+ union iodefine_reg32_t CFTISTS; /* CFTISTS */
+
+#define RSCAN0_TMC0_COUNT 80
+ volatile uint8_t TMC0; /* TMC0 */
+ volatile uint8_t TMC1; /* TMC1 */
+ volatile uint8_t TMC2; /* TMC2 */
+ volatile uint8_t TMC3; /* TMC3 */
+ volatile uint8_t TMC4; /* TMC4 */
+ volatile uint8_t TMC5; /* TMC5 */
+ volatile uint8_t TMC6; /* TMC6 */
+ volatile uint8_t TMC7; /* TMC7 */
+ volatile uint8_t TMC8; /* TMC8 */
+ volatile uint8_t TMC9; /* TMC9 */
+ volatile uint8_t TMC10; /* TMC10 */
+ volatile uint8_t TMC11; /* TMC11 */
+ volatile uint8_t TMC12; /* TMC12 */
+ volatile uint8_t TMC13; /* TMC13 */
+ volatile uint8_t TMC14; /* TMC14 */
+ volatile uint8_t TMC15; /* TMC15 */
+ volatile uint8_t TMC16; /* TMC16 */
+ volatile uint8_t TMC17; /* TMC17 */
+ volatile uint8_t TMC18; /* TMC18 */
+ volatile uint8_t TMC19; /* TMC19 */
+ volatile uint8_t TMC20; /* TMC20 */
+ volatile uint8_t TMC21; /* TMC21 */
+ volatile uint8_t TMC22; /* TMC22 */
+ volatile uint8_t TMC23; /* TMC23 */
+ volatile uint8_t TMC24; /* TMC24 */
+ volatile uint8_t TMC25; /* TMC25 */
+ volatile uint8_t TMC26; /* TMC26 */
+ volatile uint8_t TMC27; /* TMC27 */
+ volatile uint8_t TMC28; /* TMC28 */
+ volatile uint8_t TMC29; /* TMC29 */
+ volatile uint8_t TMC30; /* TMC30 */
+ volatile uint8_t TMC31; /* TMC31 */
+ volatile uint8_t TMC32; /* TMC32 */
+ volatile uint8_t TMC33; /* TMC33 */
+ volatile uint8_t TMC34; /* TMC34 */
+ volatile uint8_t TMC35; /* TMC35 */
+ volatile uint8_t TMC36; /* TMC36 */
+ volatile uint8_t TMC37; /* TMC37 */
+ volatile uint8_t TMC38; /* TMC38 */
+ volatile uint8_t TMC39; /* TMC39 */
+ volatile uint8_t TMC40; /* TMC40 */
+ volatile uint8_t TMC41; /* TMC41 */
+ volatile uint8_t TMC42; /* TMC42 */
+ volatile uint8_t TMC43; /* TMC43 */
+ volatile uint8_t TMC44; /* TMC44 */
+ volatile uint8_t TMC45; /* TMC45 */
+ volatile uint8_t TMC46; /* TMC46 */
+ volatile uint8_t TMC47; /* TMC47 */
+ volatile uint8_t TMC48; /* TMC48 */
+ volatile uint8_t TMC49; /* TMC49 */
+ volatile uint8_t TMC50; /* TMC50 */
+ volatile uint8_t TMC51; /* TMC51 */
+ volatile uint8_t TMC52; /* TMC52 */
+ volatile uint8_t TMC53; /* TMC53 */
+ volatile uint8_t TMC54; /* TMC54 */
+ volatile uint8_t TMC55; /* TMC55 */
+ volatile uint8_t TMC56; /* TMC56 */
+ volatile uint8_t TMC57; /* TMC57 */
+ volatile uint8_t TMC58; /* TMC58 */
+ volatile uint8_t TMC59; /* TMC59 */
+ volatile uint8_t TMC60; /* TMC60 */
+ volatile uint8_t TMC61; /* TMC61 */
+ volatile uint8_t TMC62; /* TMC62 */
+ volatile uint8_t TMC63; /* TMC63 */
+ volatile uint8_t TMC64; /* TMC64 */
+ volatile uint8_t TMC65; /* TMC65 */
+ volatile uint8_t TMC66; /* TMC66 */
+ volatile uint8_t TMC67; /* TMC67 */
+ volatile uint8_t TMC68; /* TMC68 */
+ volatile uint8_t TMC69; /* TMC69 */
+ volatile uint8_t TMC70; /* TMC70 */
+ volatile uint8_t TMC71; /* TMC71 */
+ volatile uint8_t TMC72; /* TMC72 */
+ volatile uint8_t TMC73; /* TMC73 */
+ volatile uint8_t TMC74; /* TMC74 */
+ volatile uint8_t TMC75; /* TMC75 */
+ volatile uint8_t TMC76; /* TMC76 */
+ volatile uint8_t TMC77; /* TMC77 */
+ volatile uint8_t TMC78; /* TMC78 */
+ volatile uint8_t TMC79; /* TMC79 */
+ volatile uint8_t dummy164[48]; /* */
+#define RSCAN0_TMSTS0_COUNT 80
+ volatile uint8_t TMSTS0; /* TMSTS0 */
+ volatile uint8_t TMSTS1; /* TMSTS1 */
+ volatile uint8_t TMSTS2; /* TMSTS2 */
+ volatile uint8_t TMSTS3; /* TMSTS3 */
+ volatile uint8_t TMSTS4; /* TMSTS4 */
+ volatile uint8_t TMSTS5; /* TMSTS5 */
+ volatile uint8_t TMSTS6; /* TMSTS6 */
+ volatile uint8_t TMSTS7; /* TMSTS7 */
+ volatile uint8_t TMSTS8; /* TMSTS8 */
+ volatile uint8_t TMSTS9; /* TMSTS9 */
+ volatile uint8_t TMSTS10; /* TMSTS10 */
+ volatile uint8_t TMSTS11; /* TMSTS11 */
+ volatile uint8_t TMSTS12; /* TMSTS12 */
+ volatile uint8_t TMSTS13; /* TMSTS13 */
+ volatile uint8_t TMSTS14; /* TMSTS14 */
+ volatile uint8_t TMSTS15; /* TMSTS15 */
+ volatile uint8_t TMSTS16; /* TMSTS16 */
+ volatile uint8_t TMSTS17; /* TMSTS17 */
+ volatile uint8_t TMSTS18; /* TMSTS18 */
+ volatile uint8_t TMSTS19; /* TMSTS19 */
+ volatile uint8_t TMSTS20; /* TMSTS20 */
+ volatile uint8_t TMSTS21; /* TMSTS21 */
+ volatile uint8_t TMSTS22; /* TMSTS22 */
+ volatile uint8_t TMSTS23; /* TMSTS23 */
+ volatile uint8_t TMSTS24; /* TMSTS24 */
+ volatile uint8_t TMSTS25; /* TMSTS25 */
+ volatile uint8_t TMSTS26; /* TMSTS26 */
+ volatile uint8_t TMSTS27; /* TMSTS27 */
+ volatile uint8_t TMSTS28; /* TMSTS28 */
+ volatile uint8_t TMSTS29; /* TMSTS29 */
+ volatile uint8_t TMSTS30; /* TMSTS30 */
+ volatile uint8_t TMSTS31; /* TMSTS31 */
+ volatile uint8_t TMSTS32; /* TMSTS32 */
+ volatile uint8_t TMSTS33; /* TMSTS33 */
+ volatile uint8_t TMSTS34; /* TMSTS34 */
+ volatile uint8_t TMSTS35; /* TMSTS35 */
+ volatile uint8_t TMSTS36; /* TMSTS36 */
+ volatile uint8_t TMSTS37; /* TMSTS37 */
+ volatile uint8_t TMSTS38; /* TMSTS38 */
+ volatile uint8_t TMSTS39; /* TMSTS39 */
+ volatile uint8_t TMSTS40; /* TMSTS40 */
+ volatile uint8_t TMSTS41; /* TMSTS41 */
+ volatile uint8_t TMSTS42; /* TMSTS42 */
+ volatile uint8_t TMSTS43; /* TMSTS43 */
+ volatile uint8_t TMSTS44; /* TMSTS44 */
+ volatile uint8_t TMSTS45; /* TMSTS45 */
+ volatile uint8_t TMSTS46; /* TMSTS46 */
+ volatile uint8_t TMSTS47; /* TMSTS47 */
+ volatile uint8_t TMSTS48; /* TMSTS48 */
+ volatile uint8_t TMSTS49; /* TMSTS49 */
+ volatile uint8_t TMSTS50; /* TMSTS50 */
+ volatile uint8_t TMSTS51; /* TMSTS51 */
+ volatile uint8_t TMSTS52; /* TMSTS52 */
+ volatile uint8_t TMSTS53; /* TMSTS53 */
+ volatile uint8_t TMSTS54; /* TMSTS54 */
+ volatile uint8_t TMSTS55; /* TMSTS55 */
+ volatile uint8_t TMSTS56; /* TMSTS56 */
+ volatile uint8_t TMSTS57; /* TMSTS57 */
+ volatile uint8_t TMSTS58; /* TMSTS58 */
+ volatile uint8_t TMSTS59; /* TMSTS59 */
+ volatile uint8_t TMSTS60; /* TMSTS60 */
+ volatile uint8_t TMSTS61; /* TMSTS61 */
+ volatile uint8_t TMSTS62; /* TMSTS62 */
+ volatile uint8_t TMSTS63; /* TMSTS63 */
+ volatile uint8_t TMSTS64; /* TMSTS64 */
+ volatile uint8_t TMSTS65; /* TMSTS65 */
+ volatile uint8_t TMSTS66; /* TMSTS66 */
+ volatile uint8_t TMSTS67; /* TMSTS67 */
+ volatile uint8_t TMSTS68; /* TMSTS68 */
+ volatile uint8_t TMSTS69; /* TMSTS69 */
+ volatile uint8_t TMSTS70; /* TMSTS70 */
+ volatile uint8_t TMSTS71; /* TMSTS71 */
+ volatile uint8_t TMSTS72; /* TMSTS72 */
+ volatile uint8_t TMSTS73; /* TMSTS73 */
+ volatile uint8_t TMSTS74; /* TMSTS74 */
+ volatile uint8_t TMSTS75; /* TMSTS75 */
+ volatile uint8_t TMSTS76; /* TMSTS76 */
+ volatile uint8_t TMSTS77; /* TMSTS77 */
+ volatile uint8_t TMSTS78; /* TMSTS78 */
+ volatile uint8_t TMSTS79; /* TMSTS79 */
+ volatile uint8_t dummy165[48]; /* */
+#define RSCAN0_TMTRSTS0_COUNT 3
+ union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */
+ union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */
+ union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */
+
+ volatile uint8_t dummy166[4]; /* */
+#define RSCAN0_TMTARSTS0_COUNT 3
+ union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */
+ union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */
+ union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */
+
+ volatile uint8_t dummy167[4]; /* */
+#define RSCAN0_TMTCSTS0_COUNT 3
+ union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */
+ union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */
+ union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */
+
+ volatile uint8_t dummy168[4]; /* */
+#define RSCAN0_TMTASTS0_COUNT 3
+ union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */
+ union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */
+ union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */
+
+ volatile uint8_t dummy169[4]; /* */
+#define RSCAN0_TMIEC0_COUNT 3
+ union iodefine_reg32_t TMIEC0; /* TMIEC0 */
+ union iodefine_reg32_t TMIEC1; /* TMIEC1 */
+ union iodefine_reg32_t TMIEC2; /* TMIEC2 */
+
+ volatile uint8_t dummy170[4]; /* */
+#define RSCAN0_TXQCC0_COUNT 5
+ union iodefine_reg32_t TXQCC0; /* TXQCC0 */
+ union iodefine_reg32_t TXQCC1; /* TXQCC1 */
+ union iodefine_reg32_t TXQCC2; /* TXQCC2 */
+ union iodefine_reg32_t TXQCC3; /* TXQCC3 */
+ union iodefine_reg32_t TXQCC4; /* TXQCC4 */
+
+ volatile uint8_t dummy171[12]; /* */
+#define RSCAN0_TXQSTS0_COUNT 5
+ union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */
+ union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */
+ union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */
+ union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */
+ union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */
+
+ volatile uint8_t dummy172[12]; /* */
+#define RSCAN0_TXQPCTR0_COUNT 5
+ union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */
+ union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */
+ union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */
+ union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */
+ union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */
+
+ volatile uint8_t dummy173[12]; /* */
+#define RSCAN0_THLCC0_COUNT 5
+ union iodefine_reg32_t THLCC0; /* THLCC0 */
+ union iodefine_reg32_t THLCC1; /* THLCC1 */
+ union iodefine_reg32_t THLCC2; /* THLCC2 */
+ union iodefine_reg32_t THLCC3; /* THLCC3 */
+ union iodefine_reg32_t THLCC4; /* THLCC4 */
+
+ volatile uint8_t dummy174[12]; /* */
+#define RSCAN0_THLSTS0_COUNT 5
+ union iodefine_reg32_t THLSTS0; /* THLSTS0 */
+ union iodefine_reg32_t THLSTS1; /* THLSTS1 */
+ union iodefine_reg32_t THLSTS2; /* THLSTS2 */
+ union iodefine_reg32_t THLSTS3; /* THLSTS3 */
+ union iodefine_reg32_t THLSTS4; /* THLSTS4 */
+
+ volatile uint8_t dummy175[12]; /* */
+#define RSCAN0_THLPCTR0_COUNT 5
+ union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */
+ union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */
+ union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */
+ union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */
+ union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */
+
+ volatile uint8_t dummy176[12]; /* */
+#define RSCAN0_GTINTSTS0_COUNT 2
+ union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */
+ union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */
+ union iodefine_reg32_t GTSTCFG; /* GTSTCFG */
+ union iodefine_reg32_t GTSTCTR; /* GTSTCTR */
+
+ volatile uint8_t dummy177[12]; /* */
+ union iodefine_reg32_16_t GLOCKK; /* GLOCKK */
+
+ volatile uint8_t dummy178[128]; /* */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID0; /* GAFLID0 */
+ union iodefine_reg32_t GAFLM0; /* GAFLM0 */
+ union iodefine_reg32_t GAFLP00; /* GAFLP00 */
+ union iodefine_reg32_t GAFLP10; /* GAFLP10 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID1; /* GAFLID1 */
+ union iodefine_reg32_t GAFLM1; /* GAFLM1 */
+ union iodefine_reg32_t GAFLP01; /* GAFLP01 */
+ union iodefine_reg32_t GAFLP11; /* GAFLP11 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID2; /* GAFLID2 */
+ union iodefine_reg32_t GAFLM2; /* GAFLM2 */
+ union iodefine_reg32_t GAFLP02; /* GAFLP02 */
+ union iodefine_reg32_t GAFLP12; /* GAFLP12 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID3; /* GAFLID3 */
+ union iodefine_reg32_t GAFLM3; /* GAFLM3 */
+ union iodefine_reg32_t GAFLP03; /* GAFLP03 */
+ union iodefine_reg32_t GAFLP13; /* GAFLP13 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID4; /* GAFLID4 */
+ union iodefine_reg32_t GAFLM4; /* GAFLM4 */
+ union iodefine_reg32_t GAFLP04; /* GAFLP04 */
+ union iodefine_reg32_t GAFLP14; /* GAFLP14 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID5; /* GAFLID5 */
+ union iodefine_reg32_t GAFLM5; /* GAFLM5 */
+ union iodefine_reg32_t GAFLP05; /* GAFLP05 */
+ union iodefine_reg32_t GAFLP15; /* GAFLP15 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID6; /* GAFLID6 */
+ union iodefine_reg32_t GAFLM6; /* GAFLM6 */
+ union iodefine_reg32_t GAFLP06; /* GAFLP06 */
+ union iodefine_reg32_t GAFLP16; /* GAFLP16 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID7; /* GAFLID7 */
+ union iodefine_reg32_t GAFLM7; /* GAFLM7 */
+ union iodefine_reg32_t GAFLP07; /* GAFLP07 */
+ union iodefine_reg32_t GAFLP17; /* GAFLP17 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID8; /* GAFLID8 */
+ union iodefine_reg32_t GAFLM8; /* GAFLM8 */
+ union iodefine_reg32_t GAFLP08; /* GAFLP08 */
+ union iodefine_reg32_t GAFLP18; /* GAFLP18 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID9; /* GAFLID9 */
+ union iodefine_reg32_t GAFLM9; /* GAFLM9 */
+ union iodefine_reg32_t GAFLP09; /* GAFLP09 */
+ union iodefine_reg32_t GAFLP19; /* GAFLP19 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID10; /* GAFLID10 */
+ union iodefine_reg32_t GAFLM10; /* GAFLM10 */
+ union iodefine_reg32_t GAFLP010; /* GAFLP010 */
+ union iodefine_reg32_t GAFLP110; /* GAFLP110 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID11; /* GAFLID11 */
+ union iodefine_reg32_t GAFLM11; /* GAFLM11 */
+ union iodefine_reg32_t GAFLP011; /* GAFLP011 */
+ union iodefine_reg32_t GAFLP111; /* GAFLP111 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID12; /* GAFLID12 */
+ union iodefine_reg32_t GAFLM12; /* GAFLM12 */
+ union iodefine_reg32_t GAFLP012; /* GAFLP012 */
+ union iodefine_reg32_t GAFLP112; /* GAFLP112 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID13; /* GAFLID13 */
+ union iodefine_reg32_t GAFLM13; /* GAFLM13 */
+ union iodefine_reg32_t GAFLP013; /* GAFLP013 */
+ union iodefine_reg32_t GAFLP113; /* GAFLP113 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID14; /* GAFLID14 */
+ union iodefine_reg32_t GAFLM14; /* GAFLM14 */
+ union iodefine_reg32_t GAFLP014; /* GAFLP014 */
+ union iodefine_reg32_t GAFLP114; /* GAFLP114 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID15; /* GAFLID15 */
+ union iodefine_reg32_t GAFLM15; /* GAFLM15 */
+ union iodefine_reg32_t GAFLP015; /* GAFLP015 */
+ union iodefine_reg32_t GAFLP115; /* GAFLP115 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID0; /* RMID0 */
+ union iodefine_reg32_t RMPTR0; /* RMPTR0 */
+ union iodefine_reg32_t RMDF00; /* RMDF00 */
+ union iodefine_reg32_t RMDF10; /* RMDF10 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID1; /* RMID1 */
+ union iodefine_reg32_t RMPTR1; /* RMPTR1 */
+ union iodefine_reg32_t RMDF01; /* RMDF01 */
+ union iodefine_reg32_t RMDF11; /* RMDF11 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID2; /* RMID2 */
+ union iodefine_reg32_t RMPTR2; /* RMPTR2 */
+ union iodefine_reg32_t RMDF02; /* RMDF02 */
+ union iodefine_reg32_t RMDF12; /* RMDF12 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID3; /* RMID3 */
+ union iodefine_reg32_t RMPTR3; /* RMPTR3 */
+ union iodefine_reg32_t RMDF03; /* RMDF03 */
+ union iodefine_reg32_t RMDF13; /* RMDF13 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID4; /* RMID4 */
+ union iodefine_reg32_t RMPTR4; /* RMPTR4 */
+ union iodefine_reg32_t RMDF04; /* RMDF04 */
+ union iodefine_reg32_t RMDF14; /* RMDF14 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID5; /* RMID5 */
+ union iodefine_reg32_t RMPTR5; /* RMPTR5 */
+ union iodefine_reg32_t RMDF05; /* RMDF05 */
+ union iodefine_reg32_t RMDF15; /* RMDF15 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID6; /* RMID6 */
+ union iodefine_reg32_t RMPTR6; /* RMPTR6 */
+ union iodefine_reg32_t RMDF06; /* RMDF06 */
+ union iodefine_reg32_t RMDF16; /* RMDF16 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID7; /* RMID7 */
+ union iodefine_reg32_t RMPTR7; /* RMPTR7 */
+ union iodefine_reg32_t RMDF07; /* RMDF07 */
+ union iodefine_reg32_t RMDF17; /* RMDF17 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID8; /* RMID8 */
+ union iodefine_reg32_t RMPTR8; /* RMPTR8 */
+ union iodefine_reg32_t RMDF08; /* RMDF08 */
+ union iodefine_reg32_t RMDF18; /* RMDF18 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID9; /* RMID9 */
+ union iodefine_reg32_t RMPTR9; /* RMPTR9 */
+ union iodefine_reg32_t RMDF09; /* RMDF09 */
+ union iodefine_reg32_t RMDF19; /* RMDF19 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID10; /* RMID10 */
+ union iodefine_reg32_t RMPTR10; /* RMPTR10 */
+ union iodefine_reg32_t RMDF010; /* RMDF010 */
+ union iodefine_reg32_t RMDF110; /* RMDF110 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID11; /* RMID11 */
+ union iodefine_reg32_t RMPTR11; /* RMPTR11 */
+ union iodefine_reg32_t RMDF011; /* RMDF011 */
+ union iodefine_reg32_t RMDF111; /* RMDF111 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID12; /* RMID12 */
+ union iodefine_reg32_t RMPTR12; /* RMPTR12 */
+ union iodefine_reg32_t RMDF012; /* RMDF012 */
+ union iodefine_reg32_t RMDF112; /* RMDF112 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID13; /* RMID13 */
+ union iodefine_reg32_t RMPTR13; /* RMPTR13 */
+ union iodefine_reg32_t RMDF013; /* RMDF013 */
+ union iodefine_reg32_t RMDF113; /* RMDF113 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID14; /* RMID14 */
+ union iodefine_reg32_t RMPTR14; /* RMPTR14 */
+ union iodefine_reg32_t RMDF014; /* RMDF014 */
+ union iodefine_reg32_t RMDF114; /* RMDF114 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID15; /* RMID15 */
+ union iodefine_reg32_t RMPTR15; /* RMPTR15 */
+ union iodefine_reg32_t RMDF015; /* RMDF015 */
+ union iodefine_reg32_t RMDF115; /* RMDF115 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID16; /* RMID16 */
+ union iodefine_reg32_t RMPTR16; /* RMPTR16 */
+ union iodefine_reg32_t RMDF016; /* RMDF016 */
+ union iodefine_reg32_t RMDF116; /* RMDF116 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID17; /* RMID17 */
+ union iodefine_reg32_t RMPTR17; /* RMPTR17 */
+ union iodefine_reg32_t RMDF017; /* RMDF017 */
+ union iodefine_reg32_t RMDF117; /* RMDF117 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID18; /* RMID18 */
+ union iodefine_reg32_t RMPTR18; /* RMPTR18 */
+ union iodefine_reg32_t RMDF018; /* RMDF018 */
+ union iodefine_reg32_t RMDF118; /* RMDF118 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID19; /* RMID19 */
+ union iodefine_reg32_t RMPTR19; /* RMPTR19 */
+ union iodefine_reg32_t RMDF019; /* RMDF019 */
+ union iodefine_reg32_t RMDF119; /* RMDF119 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID20; /* RMID20 */
+ union iodefine_reg32_t RMPTR20; /* RMPTR20 */
+ union iodefine_reg32_t RMDF020; /* RMDF020 */
+ union iodefine_reg32_t RMDF120; /* RMDF120 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID21; /* RMID21 */
+ union iodefine_reg32_t RMPTR21; /* RMPTR21 */
+ union iodefine_reg32_t RMDF021; /* RMDF021 */
+ union iodefine_reg32_t RMDF121; /* RMDF121 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID22; /* RMID22 */
+ union iodefine_reg32_t RMPTR22; /* RMPTR22 */
+ union iodefine_reg32_t RMDF022; /* RMDF022 */
+ union iodefine_reg32_t RMDF122; /* RMDF122 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID23; /* RMID23 */
+ union iodefine_reg32_t RMPTR23; /* RMPTR23 */
+ union iodefine_reg32_t RMDF023; /* RMDF023 */
+ union iodefine_reg32_t RMDF123; /* RMDF123 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID24; /* RMID24 */
+ union iodefine_reg32_t RMPTR24; /* RMPTR24 */
+ union iodefine_reg32_t RMDF024; /* RMDF024 */
+ union iodefine_reg32_t RMDF124; /* RMDF124 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID25; /* RMID25 */
+ union iodefine_reg32_t RMPTR25; /* RMPTR25 */
+ union iodefine_reg32_t RMDF025; /* RMDF025 */
+ union iodefine_reg32_t RMDF125; /* RMDF125 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID26; /* RMID26 */
+ union iodefine_reg32_t RMPTR26; /* RMPTR26 */
+ union iodefine_reg32_t RMDF026; /* RMDF026 */
+ union iodefine_reg32_t RMDF126; /* RMDF126 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID27; /* RMID27 */
+ union iodefine_reg32_t RMPTR27; /* RMPTR27 */
+ union iodefine_reg32_t RMDF027; /* RMDF027 */
+ union iodefine_reg32_t RMDF127; /* RMDF127 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID28; /* RMID28 */
+ union iodefine_reg32_t RMPTR28; /* RMPTR28 */
+ union iodefine_reg32_t RMDF028; /* RMDF028 */
+ union iodefine_reg32_t RMDF128; /* RMDF128 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID29; /* RMID29 */
+ union iodefine_reg32_t RMPTR29; /* RMPTR29 */
+ union iodefine_reg32_t RMDF029; /* RMDF029 */
+ union iodefine_reg32_t RMDF129; /* RMDF129 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID30; /* RMID30 */
+ union iodefine_reg32_t RMPTR30; /* RMPTR30 */
+ union iodefine_reg32_t RMDF030; /* RMDF030 */
+ union iodefine_reg32_t RMDF130; /* RMDF130 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID31; /* RMID31 */
+ union iodefine_reg32_t RMPTR31; /* RMPTR31 */
+ union iodefine_reg32_t RMDF031; /* RMDF031 */
+ union iodefine_reg32_t RMDF131; /* RMDF131 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID32; /* RMID32 */
+ union iodefine_reg32_t RMPTR32; /* RMPTR32 */
+ union iodefine_reg32_t RMDF032; /* RMDF032 */
+ union iodefine_reg32_t RMDF132; /* RMDF132 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID33; /* RMID33 */
+ union iodefine_reg32_t RMPTR33; /* RMPTR33 */
+ union iodefine_reg32_t RMDF033; /* RMDF033 */
+ union iodefine_reg32_t RMDF133; /* RMDF133 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID34; /* RMID34 */
+ union iodefine_reg32_t RMPTR34; /* RMPTR34 */
+ union iodefine_reg32_t RMDF034; /* RMDF034 */
+ union iodefine_reg32_t RMDF134; /* RMDF134 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID35; /* RMID35 */
+ union iodefine_reg32_t RMPTR35; /* RMPTR35 */
+ union iodefine_reg32_t RMDF035; /* RMDF035 */
+ union iodefine_reg32_t RMDF135; /* RMDF135 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID36; /* RMID36 */
+ union iodefine_reg32_t RMPTR36; /* RMPTR36 */
+ union iodefine_reg32_t RMDF036; /* RMDF036 */
+ union iodefine_reg32_t RMDF136; /* RMDF136 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID37; /* RMID37 */
+ union iodefine_reg32_t RMPTR37; /* RMPTR37 */
+ union iodefine_reg32_t RMDF037; /* RMDF037 */
+ union iodefine_reg32_t RMDF137; /* RMDF137 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID38; /* RMID38 */
+ union iodefine_reg32_t RMPTR38; /* RMPTR38 */
+ union iodefine_reg32_t RMDF038; /* RMDF038 */
+ union iodefine_reg32_t RMDF138; /* RMDF138 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID39; /* RMID39 */
+ union iodefine_reg32_t RMPTR39; /* RMPTR39 */
+ union iodefine_reg32_t RMDF039; /* RMDF039 */
+ union iodefine_reg32_t RMDF139; /* RMDF139 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID40; /* RMID40 */
+ union iodefine_reg32_t RMPTR40; /* RMPTR40 */
+ union iodefine_reg32_t RMDF040; /* RMDF040 */
+ union iodefine_reg32_t RMDF140; /* RMDF140 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID41; /* RMID41 */
+ union iodefine_reg32_t RMPTR41; /* RMPTR41 */
+ union iodefine_reg32_t RMDF041; /* RMDF041 */
+ union iodefine_reg32_t RMDF141; /* RMDF141 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID42; /* RMID42 */
+ union iodefine_reg32_t RMPTR42; /* RMPTR42 */
+ union iodefine_reg32_t RMDF042; /* RMDF042 */
+ union iodefine_reg32_t RMDF142; /* RMDF142 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID43; /* RMID43 */
+ union iodefine_reg32_t RMPTR43; /* RMPTR43 */
+ union iodefine_reg32_t RMDF043; /* RMDF043 */
+ union iodefine_reg32_t RMDF143; /* RMDF143 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID44; /* RMID44 */
+ union iodefine_reg32_t RMPTR44; /* RMPTR44 */
+ union iodefine_reg32_t RMDF044; /* RMDF044 */
+ union iodefine_reg32_t RMDF144; /* RMDF144 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID45; /* RMID45 */
+ union iodefine_reg32_t RMPTR45; /* RMPTR45 */
+ union iodefine_reg32_t RMDF045; /* RMDF045 */
+ union iodefine_reg32_t RMDF145; /* RMDF145 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID46; /* RMID46 */
+ union iodefine_reg32_t RMPTR46; /* RMPTR46 */
+ union iodefine_reg32_t RMDF046; /* RMDF046 */
+ union iodefine_reg32_t RMDF146; /* RMDF146 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID47; /* RMID47 */
+ union iodefine_reg32_t RMPTR47; /* RMPTR47 */
+ union iodefine_reg32_t RMDF047; /* RMDF047 */
+ union iodefine_reg32_t RMDF147; /* RMDF147 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID48; /* RMID48 */
+ union iodefine_reg32_t RMPTR48; /* RMPTR48 */
+ union iodefine_reg32_t RMDF048; /* RMDF048 */
+ union iodefine_reg32_t RMDF148; /* RMDF148 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID49; /* RMID49 */
+ union iodefine_reg32_t RMPTR49; /* RMPTR49 */
+ union iodefine_reg32_t RMDF049; /* RMDF049 */
+ union iodefine_reg32_t RMDF149; /* RMDF149 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID50; /* RMID50 */
+ union iodefine_reg32_t RMPTR50; /* RMPTR50 */
+ union iodefine_reg32_t RMDF050; /* RMDF050 */
+ union iodefine_reg32_t RMDF150; /* RMDF150 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID51; /* RMID51 */
+ union iodefine_reg32_t RMPTR51; /* RMPTR51 */
+ union iodefine_reg32_t RMDF051; /* RMDF051 */
+ union iodefine_reg32_t RMDF151; /* RMDF151 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID52; /* RMID52 */
+ union iodefine_reg32_t RMPTR52; /* RMPTR52 */
+ union iodefine_reg32_t RMDF052; /* RMDF052 */
+ union iodefine_reg32_t RMDF152; /* RMDF152 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID53; /* RMID53 */
+ union iodefine_reg32_t RMPTR53; /* RMPTR53 */
+ union iodefine_reg32_t RMDF053; /* RMDF053 */
+ union iodefine_reg32_t RMDF153; /* RMDF153 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID54; /* RMID54 */
+ union iodefine_reg32_t RMPTR54; /* RMPTR54 */
+ union iodefine_reg32_t RMDF054; /* RMDF054 */
+ union iodefine_reg32_t RMDF154; /* RMDF154 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID55; /* RMID55 */
+ union iodefine_reg32_t RMPTR55; /* RMPTR55 */
+ union iodefine_reg32_t RMDF055; /* RMDF055 */
+ union iodefine_reg32_t RMDF155; /* RMDF155 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID56; /* RMID56 */
+ union iodefine_reg32_t RMPTR56; /* RMPTR56 */
+ union iodefine_reg32_t RMDF056; /* RMDF056 */
+ union iodefine_reg32_t RMDF156; /* RMDF156 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID57; /* RMID57 */
+ union iodefine_reg32_t RMPTR57; /* RMPTR57 */
+ union iodefine_reg32_t RMDF057; /* RMDF057 */
+ union iodefine_reg32_t RMDF157; /* RMDF157 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID58; /* RMID58 */
+ union iodefine_reg32_t RMPTR58; /* RMPTR58 */
+ union iodefine_reg32_t RMDF058; /* RMDF058 */
+ union iodefine_reg32_t RMDF158; /* RMDF158 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID59; /* RMID59 */
+ union iodefine_reg32_t RMPTR59; /* RMPTR59 */
+ union iodefine_reg32_t RMDF059; /* RMDF059 */
+ union iodefine_reg32_t RMDF159; /* RMDF159 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID60; /* RMID60 */
+ union iodefine_reg32_t RMPTR60; /* RMPTR60 */
+ union iodefine_reg32_t RMDF060; /* RMDF060 */
+ union iodefine_reg32_t RMDF160; /* RMDF160 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID61; /* RMID61 */
+ union iodefine_reg32_t RMPTR61; /* RMPTR61 */
+ union iodefine_reg32_t RMDF061; /* RMDF061 */
+ union iodefine_reg32_t RMDF161; /* RMDF161 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID62; /* RMID62 */
+ union iodefine_reg32_t RMPTR62; /* RMPTR62 */
+ union iodefine_reg32_t RMDF062; /* RMDF062 */
+ union iodefine_reg32_t RMDF162; /* RMDF162 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID63; /* RMID63 */
+ union iodefine_reg32_t RMPTR63; /* RMPTR63 */
+ union iodefine_reg32_t RMDF063; /* RMDF063 */
+ union iodefine_reg32_t RMDF163; /* RMDF163 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID64; /* RMID64 */
+ union iodefine_reg32_t RMPTR64; /* RMPTR64 */
+ union iodefine_reg32_t RMDF064; /* RMDF064 */
+ union iodefine_reg32_t RMDF164; /* RMDF164 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID65; /* RMID65 */
+ union iodefine_reg32_t RMPTR65; /* RMPTR65 */
+ union iodefine_reg32_t RMDF065; /* RMDF065 */
+ union iodefine_reg32_t RMDF165; /* RMDF165 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID66; /* RMID66 */
+ union iodefine_reg32_t RMPTR66; /* RMPTR66 */
+ union iodefine_reg32_t RMDF066; /* RMDF066 */
+ union iodefine_reg32_t RMDF166; /* RMDF166 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID67; /* RMID67 */
+ union iodefine_reg32_t RMPTR67; /* RMPTR67 */
+ union iodefine_reg32_t RMDF067; /* RMDF067 */
+ union iodefine_reg32_t RMDF167; /* RMDF167 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID68; /* RMID68 */
+ union iodefine_reg32_t RMPTR68; /* RMPTR68 */
+ union iodefine_reg32_t RMDF068; /* RMDF068 */
+ union iodefine_reg32_t RMDF168; /* RMDF168 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID69; /* RMID69 */
+ union iodefine_reg32_t RMPTR69; /* RMPTR69 */
+ union iodefine_reg32_t RMDF069; /* RMDF069 */
+ union iodefine_reg32_t RMDF169; /* RMDF169 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID70; /* RMID70 */
+ union iodefine_reg32_t RMPTR70; /* RMPTR70 */
+ union iodefine_reg32_t RMDF070; /* RMDF070 */
+ union iodefine_reg32_t RMDF170; /* RMDF170 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID71; /* RMID71 */
+ union iodefine_reg32_t RMPTR71; /* RMPTR71 */
+ union iodefine_reg32_t RMDF071; /* RMDF071 */
+ union iodefine_reg32_t RMDF171; /* RMDF171 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID72; /* RMID72 */
+ union iodefine_reg32_t RMPTR72; /* RMPTR72 */
+ union iodefine_reg32_t RMDF072; /* RMDF072 */
+ union iodefine_reg32_t RMDF172; /* RMDF172 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID73; /* RMID73 */
+ union iodefine_reg32_t RMPTR73; /* RMPTR73 */
+ union iodefine_reg32_t RMDF073; /* RMDF073 */
+ union iodefine_reg32_t RMDF173; /* RMDF173 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID74; /* RMID74 */
+ union iodefine_reg32_t RMPTR74; /* RMPTR74 */
+ union iodefine_reg32_t RMDF074; /* RMDF074 */
+ union iodefine_reg32_t RMDF174; /* RMDF174 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID75; /* RMID75 */
+ union iodefine_reg32_t RMPTR75; /* RMPTR75 */
+ union iodefine_reg32_t RMDF075; /* RMDF075 */
+ union iodefine_reg32_t RMDF175; /* RMDF175 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID76; /* RMID76 */
+ union iodefine_reg32_t RMPTR76; /* RMPTR76 */
+ union iodefine_reg32_t RMDF076; /* RMDF076 */
+ union iodefine_reg32_t RMDF176; /* RMDF176 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID77; /* RMID77 */
+ union iodefine_reg32_t RMPTR77; /* RMPTR77 */
+ union iodefine_reg32_t RMDF077; /* RMDF077 */
+ union iodefine_reg32_t RMDF177; /* RMDF177 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID78; /* RMID78 */
+ union iodefine_reg32_t RMPTR78; /* RMPTR78 */
+ union iodefine_reg32_t RMDF078; /* RMDF078 */
+ union iodefine_reg32_t RMDF178; /* RMDF178 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID79; /* RMID79 */
+ union iodefine_reg32_t RMPTR79; /* RMPTR79 */
+ union iodefine_reg32_t RMDF079; /* RMDF079 */
+ union iodefine_reg32_t RMDF179; /* RMDF179 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+ volatile uint8_t dummy179[768]; /* */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID0; /* RFID0 */
+ union iodefine_reg32_t RFPTR0; /* RFPTR0 */
+ union iodefine_reg32_t RFDF00; /* RFDF00 */
+ union iodefine_reg32_t RFDF10; /* RFDF10 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID1; /* RFID1 */
+ union iodefine_reg32_t RFPTR1; /* RFPTR1 */
+ union iodefine_reg32_t RFDF01; /* RFDF01 */
+ union iodefine_reg32_t RFDF11; /* RFDF11 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID2; /* RFID2 */
+ union iodefine_reg32_t RFPTR2; /* RFPTR2 */
+ union iodefine_reg32_t RFDF02; /* RFDF02 */
+ union iodefine_reg32_t RFDF12; /* RFDF12 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID3; /* RFID3 */
+ union iodefine_reg32_t RFPTR3; /* RFPTR3 */
+ union iodefine_reg32_t RFDF03; /* RFDF03 */
+ union iodefine_reg32_t RFDF13; /* RFDF13 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID4; /* RFID4 */
+ union iodefine_reg32_t RFPTR4; /* RFPTR4 */
+ union iodefine_reg32_t RFDF04; /* RFDF04 */
+ union iodefine_reg32_t RFDF14; /* RFDF14 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID5; /* RFID5 */
+ union iodefine_reg32_t RFPTR5; /* RFPTR5 */
+ union iodefine_reg32_t RFDF05; /* RFDF05 */
+ union iodefine_reg32_t RFDF15; /* RFDF15 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID6; /* RFID6 */
+ union iodefine_reg32_t RFPTR6; /* RFPTR6 */
+ union iodefine_reg32_t RFDF06; /* RFDF06 */
+ union iodefine_reg32_t RFDF16; /* RFDF16 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID7; /* RFID7 */
+ union iodefine_reg32_t RFPTR7; /* RFPTR7 */
+ union iodefine_reg32_t RFDF07; /* RFDF07 */
+ union iodefine_reg32_t RFDF17; /* RFDF17 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID0; /* CFID0 */
+ union iodefine_reg32_t CFPTR0; /* CFPTR0 */
+ union iodefine_reg32_t CFDF00; /* CFDF00 */
+ union iodefine_reg32_t CFDF10; /* CFDF10 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID1; /* CFID1 */
+ union iodefine_reg32_t CFPTR1; /* CFPTR1 */
+ union iodefine_reg32_t CFDF01; /* CFDF01 */
+ union iodefine_reg32_t CFDF11; /* CFDF11 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID2; /* CFID2 */
+ union iodefine_reg32_t CFPTR2; /* CFPTR2 */
+ union iodefine_reg32_t CFDF02; /* CFDF02 */
+ union iodefine_reg32_t CFDF12; /* CFDF12 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID3; /* CFID3 */
+ union iodefine_reg32_t CFPTR3; /* CFPTR3 */
+ union iodefine_reg32_t CFDF03; /* CFDF03 */
+ union iodefine_reg32_t CFDF13; /* CFDF13 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID4; /* CFID4 */
+ union iodefine_reg32_t CFPTR4; /* CFPTR4 */
+ union iodefine_reg32_t CFDF04; /* CFDF04 */
+ union iodefine_reg32_t CFDF14; /* CFDF14 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID5; /* CFID5 */
+ union iodefine_reg32_t CFPTR5; /* CFPTR5 */
+ union iodefine_reg32_t CFDF05; /* CFDF05 */
+ union iodefine_reg32_t CFDF15; /* CFDF15 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID6; /* CFID6 */
+ union iodefine_reg32_t CFPTR6; /* CFPTR6 */
+ union iodefine_reg32_t CFDF06; /* CFDF06 */
+ union iodefine_reg32_t CFDF16; /* CFDF16 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID7; /* CFID7 */
+ union iodefine_reg32_t CFPTR7; /* CFPTR7 */
+ union iodefine_reg32_t CFDF07; /* CFDF07 */
+ union iodefine_reg32_t CFDF17; /* CFDF17 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID8; /* CFID8 */
+ union iodefine_reg32_t CFPTR8; /* CFPTR8 */
+ union iodefine_reg32_t CFDF08; /* CFDF08 */
+ union iodefine_reg32_t CFDF18; /* CFDF18 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID9; /* CFID9 */
+ union iodefine_reg32_t CFPTR9; /* CFPTR9 */
+ union iodefine_reg32_t CFDF09; /* CFDF09 */
+ union iodefine_reg32_t CFDF19; /* CFDF19 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID10; /* CFID10 */
+ union iodefine_reg32_t CFPTR10; /* CFPTR10 */
+ union iodefine_reg32_t CFDF010; /* CFDF010 */
+ union iodefine_reg32_t CFDF110; /* CFDF110 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID11; /* CFID11 */
+ union iodefine_reg32_t CFPTR11; /* CFPTR11 */
+ union iodefine_reg32_t CFDF011; /* CFDF011 */
+ union iodefine_reg32_t CFDF111; /* CFDF111 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID12; /* CFID12 */
+ union iodefine_reg32_t CFPTR12; /* CFPTR12 */
+ union iodefine_reg32_t CFDF012; /* CFDF012 */
+ union iodefine_reg32_t CFDF112; /* CFDF112 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID13; /* CFID13 */
+ union iodefine_reg32_t CFPTR13; /* CFPTR13 */
+ union iodefine_reg32_t CFDF013; /* CFDF013 */
+ union iodefine_reg32_t CFDF113; /* CFDF113 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID14; /* CFID14 */
+ union iodefine_reg32_t CFPTR14; /* CFPTR14 */
+ union iodefine_reg32_t CFDF014; /* CFDF014 */
+ union iodefine_reg32_t CFDF114; /* CFDF114 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+ volatile uint8_t dummy180[144]; /* */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID0; /* TMID0 */
+ union iodefine_reg32_t TMPTR0; /* TMPTR0 */
+ union iodefine_reg32_t TMDF00; /* TMDF00 */
+ union iodefine_reg32_t TMDF10; /* TMDF10 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID1; /* TMID1 */
+ union iodefine_reg32_t TMPTR1; /* TMPTR1 */
+ union iodefine_reg32_t TMDF01; /* TMDF01 */
+ union iodefine_reg32_t TMDF11; /* TMDF11 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID2; /* TMID2 */
+ union iodefine_reg32_t TMPTR2; /* TMPTR2 */
+ union iodefine_reg32_t TMDF02; /* TMDF02 */
+ union iodefine_reg32_t TMDF12; /* TMDF12 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID3; /* TMID3 */
+ union iodefine_reg32_t TMPTR3; /* TMPTR3 */
+ union iodefine_reg32_t TMDF03; /* TMDF03 */
+ union iodefine_reg32_t TMDF13; /* TMDF13 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID4; /* TMID4 */
+ union iodefine_reg32_t TMPTR4; /* TMPTR4 */
+ union iodefine_reg32_t TMDF04; /* TMDF04 */
+ union iodefine_reg32_t TMDF14; /* TMDF14 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID5; /* TMID5 */
+ union iodefine_reg32_t TMPTR5; /* TMPTR5 */
+ union iodefine_reg32_t TMDF05; /* TMDF05 */
+ union iodefine_reg32_t TMDF15; /* TMDF15 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID6; /* TMID6 */
+ union iodefine_reg32_t TMPTR6; /* TMPTR6 */
+ union iodefine_reg32_t TMDF06; /* TMDF06 */
+ union iodefine_reg32_t TMDF16; /* TMDF16 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID7; /* TMID7 */
+ union iodefine_reg32_t TMPTR7; /* TMPTR7 */
+ union iodefine_reg32_t TMDF07; /* TMDF07 */
+ union iodefine_reg32_t TMDF17; /* TMDF17 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID8; /* TMID8 */
+ union iodefine_reg32_t TMPTR8; /* TMPTR8 */
+ union iodefine_reg32_t TMDF08; /* TMDF08 */
+ union iodefine_reg32_t TMDF18; /* TMDF18 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID9; /* TMID9 */
+ union iodefine_reg32_t TMPTR9; /* TMPTR9 */
+ union iodefine_reg32_t TMDF09; /* TMDF09 */
+ union iodefine_reg32_t TMDF19; /* TMDF19 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID10; /* TMID10 */
+ union iodefine_reg32_t TMPTR10; /* TMPTR10 */
+ union iodefine_reg32_t TMDF010; /* TMDF010 */
+ union iodefine_reg32_t TMDF110; /* TMDF110 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID11; /* TMID11 */
+ union iodefine_reg32_t TMPTR11; /* TMPTR11 */
+ union iodefine_reg32_t TMDF011; /* TMDF011 */
+ union iodefine_reg32_t TMDF111; /* TMDF111 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID12; /* TMID12 */
+ union iodefine_reg32_t TMPTR12; /* TMPTR12 */
+ union iodefine_reg32_t TMDF012; /* TMDF012 */
+ union iodefine_reg32_t TMDF112; /* TMDF112 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID13; /* TMID13 */
+ union iodefine_reg32_t TMPTR13; /* TMPTR13 */
+ union iodefine_reg32_t TMDF013; /* TMDF013 */
+ union iodefine_reg32_t TMDF113; /* TMDF113 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID14; /* TMID14 */
+ union iodefine_reg32_t TMPTR14; /* TMPTR14 */
+ union iodefine_reg32_t TMDF014; /* TMDF014 */
+ union iodefine_reg32_t TMDF114; /* TMDF114 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID15; /* TMID15 */
+ union iodefine_reg32_t TMPTR15; /* TMPTR15 */
+ union iodefine_reg32_t TMDF015; /* TMDF015 */
+ union iodefine_reg32_t TMDF115; /* TMDF115 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID16; /* TMID16 */
+ union iodefine_reg32_t TMPTR16; /* TMPTR16 */
+ union iodefine_reg32_t TMDF016; /* TMDF016 */
+ union iodefine_reg32_t TMDF116; /* TMDF116 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID17; /* TMID17 */
+ union iodefine_reg32_t TMPTR17; /* TMPTR17 */
+ union iodefine_reg32_t TMDF017; /* TMDF017 */
+ union iodefine_reg32_t TMDF117; /* TMDF117 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID18; /* TMID18 */
+ union iodefine_reg32_t TMPTR18; /* TMPTR18 */
+ union iodefine_reg32_t TMDF018; /* TMDF018 */
+ union iodefine_reg32_t TMDF118; /* TMDF118 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID19; /* TMID19 */
+ union iodefine_reg32_t TMPTR19; /* TMPTR19 */
+ union iodefine_reg32_t TMDF019; /* TMDF019 */
+ union iodefine_reg32_t TMDF119; /* TMDF119 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID20; /* TMID20 */
+ union iodefine_reg32_t TMPTR20; /* TMPTR20 */
+ union iodefine_reg32_t TMDF020; /* TMDF020 */
+ union iodefine_reg32_t TMDF120; /* TMDF120 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID21; /* TMID21 */
+ union iodefine_reg32_t TMPTR21; /* TMPTR21 */
+ union iodefine_reg32_t TMDF021; /* TMDF021 */
+ union iodefine_reg32_t TMDF121; /* TMDF121 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID22; /* TMID22 */
+ union iodefine_reg32_t TMPTR22; /* TMPTR22 */
+ union iodefine_reg32_t TMDF022; /* TMDF022 */
+ union iodefine_reg32_t TMDF122; /* TMDF122 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID23; /* TMID23 */
+ union iodefine_reg32_t TMPTR23; /* TMPTR23 */
+ union iodefine_reg32_t TMDF023; /* TMDF023 */
+ union iodefine_reg32_t TMDF123; /* TMDF123 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID24; /* TMID24 */
+ union iodefine_reg32_t TMPTR24; /* TMPTR24 */
+ union iodefine_reg32_t TMDF024; /* TMDF024 */
+ union iodefine_reg32_t TMDF124; /* TMDF124 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID25; /* TMID25 */
+ union iodefine_reg32_t TMPTR25; /* TMPTR25 */
+ union iodefine_reg32_t TMDF025; /* TMDF025 */
+ union iodefine_reg32_t TMDF125; /* TMDF125 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID26; /* TMID26 */
+ union iodefine_reg32_t TMPTR26; /* TMPTR26 */
+ union iodefine_reg32_t TMDF026; /* TMDF026 */
+ union iodefine_reg32_t TMDF126; /* TMDF126 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID27; /* TMID27 */
+ union iodefine_reg32_t TMPTR27; /* TMPTR27 */
+ union iodefine_reg32_t TMDF027; /* TMDF027 */
+ union iodefine_reg32_t TMDF127; /* TMDF127 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID28; /* TMID28 */
+ union iodefine_reg32_t TMPTR28; /* TMPTR28 */
+ union iodefine_reg32_t TMDF028; /* TMDF028 */
+ union iodefine_reg32_t TMDF128; /* TMDF128 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID29; /* TMID29 */
+ union iodefine_reg32_t TMPTR29; /* TMPTR29 */
+ union iodefine_reg32_t TMDF029; /* TMDF029 */
+ union iodefine_reg32_t TMDF129; /* TMDF129 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID30; /* TMID30 */
+ union iodefine_reg32_t TMPTR30; /* TMPTR30 */
+ union iodefine_reg32_t TMDF030; /* TMDF030 */
+ union iodefine_reg32_t TMDF130; /* TMDF130 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID31; /* TMID31 */
+ union iodefine_reg32_t TMPTR31; /* TMPTR31 */
+ union iodefine_reg32_t TMDF031; /* TMDF031 */
+ union iodefine_reg32_t TMDF131; /* TMDF131 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID32; /* TMID32 */
+ union iodefine_reg32_t TMPTR32; /* TMPTR32 */
+ union iodefine_reg32_t TMDF032; /* TMDF032 */
+ union iodefine_reg32_t TMDF132; /* TMDF132 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID33; /* TMID33 */
+ union iodefine_reg32_t TMPTR33; /* TMPTR33 */
+ union iodefine_reg32_t TMDF033; /* TMDF033 */
+ union iodefine_reg32_t TMDF133; /* TMDF133 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID34; /* TMID34 */
+ union iodefine_reg32_t TMPTR34; /* TMPTR34 */
+ union iodefine_reg32_t TMDF034; /* TMDF034 */
+ union iodefine_reg32_t TMDF134; /* TMDF134 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID35; /* TMID35 */
+ union iodefine_reg32_t TMPTR35; /* TMPTR35 */
+ union iodefine_reg32_t TMDF035; /* TMDF035 */
+ union iodefine_reg32_t TMDF135; /* TMDF135 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID36; /* TMID36 */
+ union iodefine_reg32_t TMPTR36; /* TMPTR36 */
+ union iodefine_reg32_t TMDF036; /* TMDF036 */
+ union iodefine_reg32_t TMDF136; /* TMDF136 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID37; /* TMID37 */
+ union iodefine_reg32_t TMPTR37; /* TMPTR37 */
+ union iodefine_reg32_t TMDF037; /* TMDF037 */
+ union iodefine_reg32_t TMDF137; /* TMDF137 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID38; /* TMID38 */
+ union iodefine_reg32_t TMPTR38; /* TMPTR38 */
+ union iodefine_reg32_t TMDF038; /* TMDF038 */
+ union iodefine_reg32_t TMDF138; /* TMDF138 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID39; /* TMID39 */
+ union iodefine_reg32_t TMPTR39; /* TMPTR39 */
+ union iodefine_reg32_t TMDF039; /* TMDF039 */
+ union iodefine_reg32_t TMDF139; /* TMDF139 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID40; /* TMID40 */
+ union iodefine_reg32_t TMPTR40; /* TMPTR40 */
+ union iodefine_reg32_t TMDF040; /* TMDF040 */
+ union iodefine_reg32_t TMDF140; /* TMDF140 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID41; /* TMID41 */
+ union iodefine_reg32_t TMPTR41; /* TMPTR41 */
+ union iodefine_reg32_t TMDF041; /* TMDF041 */
+ union iodefine_reg32_t TMDF141; /* TMDF141 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID42; /* TMID42 */
+ union iodefine_reg32_t TMPTR42; /* TMPTR42 */
+ union iodefine_reg32_t TMDF042; /* TMDF042 */
+ union iodefine_reg32_t TMDF142; /* TMDF142 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID43; /* TMID43 */
+ union iodefine_reg32_t TMPTR43; /* TMPTR43 */
+ union iodefine_reg32_t TMDF043; /* TMDF043 */
+ union iodefine_reg32_t TMDF143; /* TMDF143 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID44; /* TMID44 */
+ union iodefine_reg32_t TMPTR44; /* TMPTR44 */
+ union iodefine_reg32_t TMDF044; /* TMDF044 */
+ union iodefine_reg32_t TMDF144; /* TMDF144 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID45; /* TMID45 */
+ union iodefine_reg32_t TMPTR45; /* TMPTR45 */
+ union iodefine_reg32_t TMDF045; /* TMDF045 */
+ union iodefine_reg32_t TMDF145; /* TMDF145 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID46; /* TMID46 */
+ union iodefine_reg32_t TMPTR46; /* TMPTR46 */
+ union iodefine_reg32_t TMDF046; /* TMDF046 */
+ union iodefine_reg32_t TMDF146; /* TMDF146 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID47; /* TMID47 */
+ union iodefine_reg32_t TMPTR47; /* TMPTR47 */
+ union iodefine_reg32_t TMDF047; /* TMDF047 */
+ union iodefine_reg32_t TMDF147; /* TMDF147 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID48; /* TMID48 */
+ union iodefine_reg32_t TMPTR48; /* TMPTR48 */
+ union iodefine_reg32_t TMDF048; /* TMDF048 */
+ union iodefine_reg32_t TMDF148; /* TMDF148 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID49; /* TMID49 */
+ union iodefine_reg32_t TMPTR49; /* TMPTR49 */
+ union iodefine_reg32_t TMDF049; /* TMDF049 */
+ union iodefine_reg32_t TMDF149; /* TMDF149 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID50; /* TMID50 */
+ union iodefine_reg32_t TMPTR50; /* TMPTR50 */
+ union iodefine_reg32_t TMDF050; /* TMDF050 */
+ union iodefine_reg32_t TMDF150; /* TMDF150 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID51; /* TMID51 */
+ union iodefine_reg32_t TMPTR51; /* TMPTR51 */
+ union iodefine_reg32_t TMDF051; /* TMDF051 */
+ union iodefine_reg32_t TMDF151; /* TMDF151 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID52; /* TMID52 */
+ union iodefine_reg32_t TMPTR52; /* TMPTR52 */
+ union iodefine_reg32_t TMDF052; /* TMDF052 */
+ union iodefine_reg32_t TMDF152; /* TMDF152 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID53; /* TMID53 */
+ union iodefine_reg32_t TMPTR53; /* TMPTR53 */
+ union iodefine_reg32_t TMDF053; /* TMDF053 */
+ union iodefine_reg32_t TMDF153; /* TMDF153 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID54; /* TMID54 */
+ union iodefine_reg32_t TMPTR54; /* TMPTR54 */
+ union iodefine_reg32_t TMDF054; /* TMDF054 */
+ union iodefine_reg32_t TMDF154; /* TMDF154 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID55; /* TMID55 */
+ union iodefine_reg32_t TMPTR55; /* TMPTR55 */
+ union iodefine_reg32_t TMDF055; /* TMDF055 */
+ union iodefine_reg32_t TMDF155; /* TMDF155 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID56; /* TMID56 */
+ union iodefine_reg32_t TMPTR56; /* TMPTR56 */
+ union iodefine_reg32_t TMDF056; /* TMDF056 */
+ union iodefine_reg32_t TMDF156; /* TMDF156 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID57; /* TMID57 */
+ union iodefine_reg32_t TMPTR57; /* TMPTR57 */
+ union iodefine_reg32_t TMDF057; /* TMDF057 */
+ union iodefine_reg32_t TMDF157; /* TMDF157 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID58; /* TMID58 */
+ union iodefine_reg32_t TMPTR58; /* TMPTR58 */
+ union iodefine_reg32_t TMDF058; /* TMDF058 */
+ union iodefine_reg32_t TMDF158; /* TMDF158 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID59; /* TMID59 */
+ union iodefine_reg32_t TMPTR59; /* TMPTR59 */
+ union iodefine_reg32_t TMDF059; /* TMDF059 */
+ union iodefine_reg32_t TMDF159; /* TMDF159 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID60; /* TMID60 */
+ union iodefine_reg32_t TMPTR60; /* TMPTR60 */
+ union iodefine_reg32_t TMDF060; /* TMDF060 */
+ union iodefine_reg32_t TMDF160; /* TMDF160 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID61; /* TMID61 */
+ union iodefine_reg32_t TMPTR61; /* TMPTR61 */
+ union iodefine_reg32_t TMDF061; /* TMDF061 */
+ union iodefine_reg32_t TMDF161; /* TMDF161 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID62; /* TMID62 */
+ union iodefine_reg32_t TMPTR62; /* TMPTR62 */
+ union iodefine_reg32_t TMDF062; /* TMDF062 */
+ union iodefine_reg32_t TMDF162; /* TMDF162 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID63; /* TMID63 */
+ union iodefine_reg32_t TMPTR63; /* TMPTR63 */
+ union iodefine_reg32_t TMDF063; /* TMDF063 */
+ union iodefine_reg32_t TMDF163; /* TMDF163 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID64; /* TMID64 */
+ union iodefine_reg32_t TMPTR64; /* TMPTR64 */
+ union iodefine_reg32_t TMDF064; /* TMDF064 */
+ union iodefine_reg32_t TMDF164; /* TMDF164 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID65; /* TMID65 */
+ union iodefine_reg32_t TMPTR65; /* TMPTR65 */
+ union iodefine_reg32_t TMDF065; /* TMDF065 */
+ union iodefine_reg32_t TMDF165; /* TMDF165 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID66; /* TMID66 */
+ union iodefine_reg32_t TMPTR66; /* TMPTR66 */
+ union iodefine_reg32_t TMDF066; /* TMDF066 */
+ union iodefine_reg32_t TMDF166; /* TMDF166 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID67; /* TMID67 */
+ union iodefine_reg32_t TMPTR67; /* TMPTR67 */
+ union iodefine_reg32_t TMDF067; /* TMDF067 */
+ union iodefine_reg32_t TMDF167; /* TMDF167 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID68; /* TMID68 */
+ union iodefine_reg32_t TMPTR68; /* TMPTR68 */
+ union iodefine_reg32_t TMDF068; /* TMDF068 */
+ union iodefine_reg32_t TMDF168; /* TMDF168 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID69; /* TMID69 */
+ union iodefine_reg32_t TMPTR69; /* TMPTR69 */
+ union iodefine_reg32_t TMDF069; /* TMDF069 */
+ union iodefine_reg32_t TMDF169; /* TMDF169 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID70; /* TMID70 */
+ union iodefine_reg32_t TMPTR70; /* TMPTR70 */
+ union iodefine_reg32_t TMDF070; /* TMDF070 */
+ union iodefine_reg32_t TMDF170; /* TMDF170 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID71; /* TMID71 */
+ union iodefine_reg32_t TMPTR71; /* TMPTR71 */
+ union iodefine_reg32_t TMDF071; /* TMDF071 */
+ union iodefine_reg32_t TMDF171; /* TMDF171 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID72; /* TMID72 */
+ union iodefine_reg32_t TMPTR72; /* TMPTR72 */
+ union iodefine_reg32_t TMDF072; /* TMDF072 */
+ union iodefine_reg32_t TMDF172; /* TMDF172 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID73; /* TMID73 */
+ union iodefine_reg32_t TMPTR73; /* TMPTR73 */
+ union iodefine_reg32_t TMDF073; /* TMDF073 */
+ union iodefine_reg32_t TMDF173; /* TMDF173 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID74; /* TMID74 */
+ union iodefine_reg32_t TMPTR74; /* TMPTR74 */
+ union iodefine_reg32_t TMDF074; /* TMDF074 */
+ union iodefine_reg32_t TMDF174; /* TMDF174 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID75; /* TMID75 */
+ union iodefine_reg32_t TMPTR75; /* TMPTR75 */
+ union iodefine_reg32_t TMDF075; /* TMDF075 */
+ union iodefine_reg32_t TMDF175; /* TMDF175 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID76; /* TMID76 */
+ union iodefine_reg32_t TMPTR76; /* TMPTR76 */
+ union iodefine_reg32_t TMDF076; /* TMDF076 */
+ union iodefine_reg32_t TMDF176; /* TMDF176 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID77; /* TMID77 */
+ union iodefine_reg32_t TMPTR77; /* TMPTR77 */
+ union iodefine_reg32_t TMDF077; /* TMDF077 */
+ union iodefine_reg32_t TMDF177; /* TMDF177 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID78; /* TMID78 */
+ union iodefine_reg32_t TMPTR78; /* TMPTR78 */
+ union iodefine_reg32_t TMDF078; /* TMDF078 */
+ union iodefine_reg32_t TMDF178; /* TMDF178 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID79; /* TMID79 */
+ union iodefine_reg32_t TMPTR79; /* TMPTR79 */
+ union iodefine_reg32_t TMDF079; /* TMDF079 */
+ union iodefine_reg32_t TMDF179; /* TMDF179 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+ volatile uint8_t dummy181[768]; /* */
+#define RSCAN0_THLACC0_COUNT 5
+ union iodefine_reg32_t THLACC0; /* THLACC0 */
+ union iodefine_reg32_t THLACC1; /* THLACC1 */
+ union iodefine_reg32_t THLACC2; /* THLACC2 */
+ union iodefine_reg32_t THLACC3; /* THLACC3 */
+ union iodefine_reg32_t THLACC4; /* THLACC4 */
+
+};
+
+
+struct st_rscan_from_rscan0cncfg
+{
+ union iodefine_reg32_t CnCFG; /* CnCFG */
+ union iodefine_reg32_t CnCTR; /* CnCTR */
+ union iodefine_reg32_t CnSTS; /* CnSTS */
+ union iodefine_reg32_t CnERFL; /* CnERFL */
+};
+
+
+struct st_rscan_from_rscan0gaflidj
+{
+ union iodefine_reg32_t GAFLIDj; /* GAFLIDj */
+ union iodefine_reg32_t GAFLMj; /* GAFLMj */
+ union iodefine_reg32_t GAFLP0j; /* GAFLP0j */
+ union iodefine_reg32_t GAFLP1j; /* GAFLP1j */
+};
+
+
+struct st_rscan_from_rscan0rmidp
+{
+ union iodefine_reg32_t RMIDp; /* RMIDp */
+ union iodefine_reg32_t RMPTRp; /* RMPTRp */
+ union iodefine_reg32_t RMDF0p; /* RMDF0p */
+ union iodefine_reg32_t RMDF1p; /* RMDF1p */
+};
+
+
+struct st_rscan_from_rscan0rfidm
+{
+ union iodefine_reg32_t RFIDm; /* RFIDm */
+ union iodefine_reg32_t RFPTRm; /* RFPTRm */
+ union iodefine_reg32_t RFDF0m; /* RFDF0m */
+ union iodefine_reg32_t RFDF1m; /* RFDF1m */
+};
+
+
+struct st_rscan_from_rscan0tmidp
+{
+ union iodefine_reg32_t TMIDp; /* TMIDp */
+ union iodefine_reg32_t TMPTRp; /* TMPTRp */
+ union iodefine_reg32_t TMDF0p; /* TMDF0p */
+ union iodefine_reg32_t TMDF1p; /* TMDF1p */
+};
+
+
+struct st_rscan_from_rscan0cfidm
+{
+ union iodefine_reg32_t CFIDm; /* CFIDm */
+ union iodefine_reg32_t CFPTRm; /* CFPTRm */
+ union iodefine_reg32_t CFDF0m; /* CFDF0m */
+ union iodefine_reg32_t CFDF1m; /* CFDF1m */
+};
+
+
+#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */
+
+
+/* Start of channnel array defines of RSCAN0 */
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15
+#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
+ &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */
+#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */
+#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */
+#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */
+#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */
+#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */
+#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */
+#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */
+#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */
+#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */
+#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */
+#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */
+#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */
+#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */
+#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80
+#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
+ &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
+ &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \
+ &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \
+ &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \
+ &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \
+ &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \
+ &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \
+ &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \
+ &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */
+#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */
+#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */
+#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */
+#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */
+#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */
+#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */
+#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */
+#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */
+#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */
+#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */
+#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */
+#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */
+#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */
+#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */
+#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */
+#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */
+#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */
+#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */
+#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */
+#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */
+#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */
+#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */
+#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */
+#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */
+#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */
+#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */
+#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */
+#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */
+#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */
+#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */
+#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */
+#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */
+#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */
+#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */
+#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */
+#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */
+#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */
+#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */
+#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */
+#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */
+#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */
+#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */
+#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */
+#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */
+#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */
+#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */
+#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */
+#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */
+#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */
+#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */
+#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */
+#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */
+#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */
+#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */
+#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */
+#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */
+#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */
+#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */
+#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */
+#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */
+#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */
+#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */
+#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */
+#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */
+#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */
+#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */
+#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */
+#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */
+#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */
+#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */
+#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */
+#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */
+#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */
+#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */
+#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */
+#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */
+#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */
+#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */
+#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8
+#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */
+#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */
+#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */
+#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */
+#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */
+#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */
+#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */
+#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80
+#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
+ &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
+ &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \
+ &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \
+ &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \
+ &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \
+ &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \
+ &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \
+ &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \
+ &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */
+#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */
+#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */
+#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */
+#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */
+#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */
+#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */
+#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */
+#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */
+#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */
+#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */
+#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */
+#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */
+#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */
+#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */
+#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */
+#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */
+#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */
+#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */
+#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */
+#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */
+#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */
+#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */
+#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */
+#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */
+#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */
+#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */
+#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */
+#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */
+#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */
+#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */
+#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */
+#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */
+#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */
+#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */
+#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */
+#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */
+#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */
+#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */
+#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */
+#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */
+#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */
+#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */
+#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */
+#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */
+#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */
+#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */
+#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */
+#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */
+#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */
+#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */
+#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */
+#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */
+#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */
+#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */
+#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */
+#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */
+#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */
+#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */
+#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */
+#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */
+#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */
+#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */
+#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */
+#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */
+#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */
+#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */
+#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */
+#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */
+#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */
+#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */
+#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */
+#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */
+#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */
+#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */
+#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */
+#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */
+#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */
+#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */
+#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16
+#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
+ &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */
+#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */
+#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */
+#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */
+#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */
+#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */
+#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */
+#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */
+#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */
+#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */
+#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */
+#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */
+#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */
+#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */
+#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */
+#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5
+#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */
+#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */
+#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */
+#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
+#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
+
+/* End of channnel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
+#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
+#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
+#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
+#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
+#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
+#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
+#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
+#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
+#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
+#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
+#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
+#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
+#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
+#define RSCAN0C0STS RSCAN0.C0STS.UINT32
+#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
+#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
+#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
+#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
+#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
+#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
+#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
+#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
+#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
+#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
+#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
+#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
+#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
+#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
+#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
+#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
+#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
+#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
+#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
+#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
+#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
+#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
+#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
+#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
+#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
+#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
+#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
+#define RSCAN0C1STS RSCAN0.C1STS.UINT32
+#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
+#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
+#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
+#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
+#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
+#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
+#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
+#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
+#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
+#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
+#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
+#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
+#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
+#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
+#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
+#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
+#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
+#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
+#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
+#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
+#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
+#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
+#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
+#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
+#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
+#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
+#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
+#define RSCAN0C2STS RSCAN0.C2STS.UINT32
+#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
+#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
+#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
+#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
+#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
+#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
+#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
+#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
+#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
+#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
+#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
+#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
+#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
+#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
+#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
+#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
+#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
+#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
+#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
+#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
+#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
+#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
+#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
+#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
+#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
+#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
+#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
+#define RSCAN0C3STS RSCAN0.C3STS.UINT32
+#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
+#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
+#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
+#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
+#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
+#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
+#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
+#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
+#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
+#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
+#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
+#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
+#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
+#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
+#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
+#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
+#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
+#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
+#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
+#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
+#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
+#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
+#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
+#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
+#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
+#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
+#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
+#define RSCAN0C4STS RSCAN0.C4STS.UINT32
+#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
+#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
+#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
+#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
+#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
+#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
+#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
+#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
+#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
+#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
+#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
+#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
+#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
+#define RSCAN0GCFG RSCAN0.GCFG.UINT32
+#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
+#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
+#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
+#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
+#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
+#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
+#define RSCAN0GCTR RSCAN0.GCTR.UINT32
+#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
+#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
+#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
+#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
+#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
+#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
+#define RSCAN0GSTS RSCAN0.GSTS.UINT32
+#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
+#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
+#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
+#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
+#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
+#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
+#define RSCAN0GERFL RSCAN0.GERFL.UINT32
+#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
+#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
+#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
+#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
+#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
+#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
+#define RSCAN0GTSC RSCAN0.GTSC.UINT32
+#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
+#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
+#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
+#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
+#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
+#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
+#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
+#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
+#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
+#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
+#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
+#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
+#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
+#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
+#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
+#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
+#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
+#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
+#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
+#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
+#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
+#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
+#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
+#define RSCAN0RMNB RSCAN0.RMNB.UINT32
+#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
+#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
+#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
+#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
+#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
+#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
+#define RSCAN0RMND0 RSCAN0.RMND0.UINT32
+#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
+#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
+#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
+#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
+#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
+#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
+#define RSCAN0RMND1 RSCAN0.RMND1.UINT32
+#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
+#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
+#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
+#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
+#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
+#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
+#define RSCAN0RMND2 RSCAN0.RMND2.UINT32
+#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
+#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
+#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
+#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
+#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
+#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
+#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
+#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
+#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
+#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
+#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
+#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
+#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
+#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
+#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
+#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
+#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
+#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
+#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
+#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
+#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
+#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
+#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
+#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
+#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
+#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
+#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
+#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
+#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
+#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
+#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
+#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
+#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
+#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
+#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
+#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
+#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
+#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
+#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
+#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
+#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
+#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
+#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
+#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
+#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
+#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
+#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
+#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
+#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
+#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
+#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
+#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
+#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
+#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
+#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
+#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
+#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
+#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
+#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
+#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
+#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
+#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
+#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
+#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
+#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
+#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
+#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
+#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
+#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
+#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
+#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
+#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
+#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
+#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
+#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
+#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
+#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
+#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
+#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
+#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
+#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
+#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
+#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
+#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
+#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
+#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
+#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
+#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
+#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
+#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
+#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
+#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
+#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
+#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
+#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
+#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
+#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
+#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
+#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
+#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
+#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
+#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
+#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
+#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
+#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
+#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
+#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
+#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
+#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
+#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
+#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
+#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
+#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
+#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
+#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
+#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
+#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
+#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
+#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
+#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
+#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
+#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
+#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
+#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
+#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
+#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
+#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
+#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
+#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
+#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
+#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
+#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
+#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
+#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
+#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
+#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
+#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
+#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
+#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
+#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
+#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
+#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
+#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
+#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
+#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
+#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
+#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
+#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
+#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
+#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
+#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
+#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
+#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
+#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
+#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
+#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
+#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
+#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
+#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
+#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
+#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
+#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
+#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
+#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
+#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
+#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
+#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
+#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
+#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
+#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
+#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
+#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
+#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
+#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
+#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
+#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
+#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
+#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
+#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
+#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
+#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
+#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
+#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
+#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
+#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
+#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
+#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
+#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
+#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
+#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
+#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
+#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
+#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
+#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
+#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
+#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
+#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
+#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
+#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
+#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
+#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
+#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
+#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
+#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
+#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
+#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
+#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
+#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
+#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
+#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
+#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
+#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
+#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
+#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
+#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
+#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
+#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
+#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
+#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
+#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
+#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
+#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
+#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
+#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
+#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
+#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
+#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
+#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
+#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
+#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
+#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
+#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
+#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
+#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
+#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
+#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
+#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
+#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
+#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
+#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
+#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
+#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
+#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
+#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
+#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
+#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
+#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
+#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
+#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
+#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
+#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
+#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
+#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
+#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
+#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
+#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
+#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
+#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
+#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
+#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
+#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
+#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
+#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
+#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
+#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
+#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
+#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
+#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
+#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
+#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
+#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
+#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
+#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
+#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
+#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
+#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
+#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
+#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
+#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
+#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
+#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
+#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
+#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
+#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
+#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
+#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
+#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
+#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
+#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
+#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
+#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
+#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
+#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
+#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
+#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
+#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
+#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
+#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
+#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
+#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
+#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
+#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
+#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
+#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
+#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
+#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
+#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
+#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
+#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
+#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
+#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
+#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
+#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
+#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
+#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
+#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
+#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
+#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
+#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
+#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
+#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
+#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
+#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
+#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
+#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
+#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
+#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
+#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
+#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
+#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
+#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
+#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
+#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
+#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
+#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
+#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
+#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
+#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
+#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
+#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
+#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
+#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
+#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
+#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
+#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
+#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
+#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
+#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
+#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
+#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
+#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
+#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
+#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
+#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
+#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
+#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
+#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
+#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
+#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
+#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
+#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
+#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
+#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
+#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
+#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
+#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
+#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
+#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
+#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
+#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
+#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
+#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
+#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
+#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
+#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
+#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
+#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
+#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
+#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
+#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
+#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
+#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
+#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
+#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
+#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
+#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
+#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
+#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
+#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
+#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
+#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
+#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
+#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
+#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
+#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
+#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
+#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
+#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
+#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
+#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
+#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
+#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
+#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
+#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
+#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
+#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
+#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
+#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
+#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
+#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
+#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
+#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
+#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
+#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
+#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
+#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
+#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
+#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
+#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
+#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
+#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
+#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
+#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
+#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
+#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
+#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
+#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
+#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
+#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
+#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
+#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
+#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
+#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
+#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
+#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
+#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
+#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
+#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
+#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
+#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
+#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
+#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
+#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
+#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
+#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
+#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
+#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
+#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
+#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
+#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
+#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
+#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
+#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
+#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
+#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
+#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
+#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
+#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
+#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
+#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
+#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
+#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
+#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
+#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
+#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
+#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
+#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
+#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
+#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
+#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
+#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
+#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
+#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
+#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
+#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
+#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
+#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
+#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
+#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
+#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
+#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
+#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
+#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
+#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
+#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
+#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
+#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
+#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
+#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
+#define RSCAN0FESTS RSCAN0.FESTS.UINT32
+#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
+#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
+#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
+#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
+#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
+#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
+#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
+#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
+#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
+#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
+#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
+#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
+#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
+#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
+#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
+#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
+#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
+#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
+#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
+#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
+#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
+#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
+#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
+#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
+#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
+#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
+#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
+#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
+#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
+#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
+#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
+#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
+#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
+#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
+#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
+#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
+#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
+#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
+#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
+#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
+#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
+#define RSCAN0TMC0 RSCAN0.TMC0
+#define RSCAN0TMC1 RSCAN0.TMC1
+#define RSCAN0TMC2 RSCAN0.TMC2
+#define RSCAN0TMC3 RSCAN0.TMC3
+#define RSCAN0TMC4 RSCAN0.TMC4
+#define RSCAN0TMC5 RSCAN0.TMC5
+#define RSCAN0TMC6 RSCAN0.TMC6
+#define RSCAN0TMC7 RSCAN0.TMC7
+#define RSCAN0TMC8 RSCAN0.TMC8
+#define RSCAN0TMC9 RSCAN0.TMC9
+#define RSCAN0TMC10 RSCAN0.TMC10
+#define RSCAN0TMC11 RSCAN0.TMC11
+#define RSCAN0TMC12 RSCAN0.TMC12
+#define RSCAN0TMC13 RSCAN0.TMC13
+#define RSCAN0TMC14 RSCAN0.TMC14
+#define RSCAN0TMC15 RSCAN0.TMC15
+#define RSCAN0TMC16 RSCAN0.TMC16
+#define RSCAN0TMC17 RSCAN0.TMC17
+#define RSCAN0TMC18 RSCAN0.TMC18
+#define RSCAN0TMC19 RSCAN0.TMC19
+#define RSCAN0TMC20 RSCAN0.TMC20
+#define RSCAN0TMC21 RSCAN0.TMC21
+#define RSCAN0TMC22 RSCAN0.TMC22
+#define RSCAN0TMC23 RSCAN0.TMC23
+#define RSCAN0TMC24 RSCAN0.TMC24
+#define RSCAN0TMC25 RSCAN0.TMC25
+#define RSCAN0TMC26 RSCAN0.TMC26
+#define RSCAN0TMC27 RSCAN0.TMC27
+#define RSCAN0TMC28 RSCAN0.TMC28
+#define RSCAN0TMC29 RSCAN0.TMC29
+#define RSCAN0TMC30 RSCAN0.TMC30
+#define RSCAN0TMC31 RSCAN0.TMC31
+#define RSCAN0TMC32 RSCAN0.TMC32
+#define RSCAN0TMC33 RSCAN0.TMC33
+#define RSCAN0TMC34 RSCAN0.TMC34
+#define RSCAN0TMC35 RSCAN0.TMC35
+#define RSCAN0TMC36 RSCAN0.TMC36
+#define RSCAN0TMC37 RSCAN0.TMC37
+#define RSCAN0TMC38 RSCAN0.TMC38
+#define RSCAN0TMC39 RSCAN0.TMC39
+#define RSCAN0TMC40 RSCAN0.TMC40
+#define RSCAN0TMC41 RSCAN0.TMC41
+#define RSCAN0TMC42 RSCAN0.TMC42
+#define RSCAN0TMC43 RSCAN0.TMC43
+#define RSCAN0TMC44 RSCAN0.TMC44
+#define RSCAN0TMC45 RSCAN0.TMC45
+#define RSCAN0TMC46 RSCAN0.TMC46
+#define RSCAN0TMC47 RSCAN0.TMC47
+#define RSCAN0TMC48 RSCAN0.TMC48
+#define RSCAN0TMC49 RSCAN0.TMC49
+#define RSCAN0TMC50 RSCAN0.TMC50
+#define RSCAN0TMC51 RSCAN0.TMC51
+#define RSCAN0TMC52 RSCAN0.TMC52
+#define RSCAN0TMC53 RSCAN0.TMC53
+#define RSCAN0TMC54 RSCAN0.TMC54
+#define RSCAN0TMC55 RSCAN0.TMC55
+#define RSCAN0TMC56 RSCAN0.TMC56
+#define RSCAN0TMC57 RSCAN0.TMC57
+#define RSCAN0TMC58 RSCAN0.TMC58
+#define RSCAN0TMC59 RSCAN0.TMC59
+#define RSCAN0TMC60 RSCAN0.TMC60
+#define RSCAN0TMC61 RSCAN0.TMC61
+#define RSCAN0TMC62 RSCAN0.TMC62
+#define RSCAN0TMC63 RSCAN0.TMC63
+#define RSCAN0TMC64 RSCAN0.TMC64
+#define RSCAN0TMC65 RSCAN0.TMC65
+#define RSCAN0TMC66 RSCAN0.TMC66
+#define RSCAN0TMC67 RSCAN0.TMC67
+#define RSCAN0TMC68 RSCAN0.TMC68
+#define RSCAN0TMC69 RSCAN0.TMC69
+#define RSCAN0TMC70 RSCAN0.TMC70
+#define RSCAN0TMC71 RSCAN0.TMC71
+#define RSCAN0TMC72 RSCAN0.TMC72
+#define RSCAN0TMC73 RSCAN0.TMC73
+#define RSCAN0TMC74 RSCAN0.TMC74
+#define RSCAN0TMC75 RSCAN0.TMC75
+#define RSCAN0TMC76 RSCAN0.TMC76
+#define RSCAN0TMC77 RSCAN0.TMC77
+#define RSCAN0TMC78 RSCAN0.TMC78
+#define RSCAN0TMC79 RSCAN0.TMC79
+#define RSCAN0TMSTS0 RSCAN0.TMSTS0
+#define RSCAN0TMSTS1 RSCAN0.TMSTS1
+#define RSCAN0TMSTS2 RSCAN0.TMSTS2
+#define RSCAN0TMSTS3 RSCAN0.TMSTS3
+#define RSCAN0TMSTS4 RSCAN0.TMSTS4
+#define RSCAN0TMSTS5 RSCAN0.TMSTS5
+#define RSCAN0TMSTS6 RSCAN0.TMSTS6
+#define RSCAN0TMSTS7 RSCAN0.TMSTS7
+#define RSCAN0TMSTS8 RSCAN0.TMSTS8
+#define RSCAN0TMSTS9 RSCAN0.TMSTS9
+#define RSCAN0TMSTS10 RSCAN0.TMSTS10
+#define RSCAN0TMSTS11 RSCAN0.TMSTS11
+#define RSCAN0TMSTS12 RSCAN0.TMSTS12
+#define RSCAN0TMSTS13 RSCAN0.TMSTS13
+#define RSCAN0TMSTS14 RSCAN0.TMSTS14
+#define RSCAN0TMSTS15 RSCAN0.TMSTS15
+#define RSCAN0TMSTS16 RSCAN0.TMSTS16
+#define RSCAN0TMSTS17 RSCAN0.TMSTS17
+#define RSCAN0TMSTS18 RSCAN0.TMSTS18
+#define RSCAN0TMSTS19 RSCAN0.TMSTS19
+#define RSCAN0TMSTS20 RSCAN0.TMSTS20
+#define RSCAN0TMSTS21 RSCAN0.TMSTS21
+#define RSCAN0TMSTS22 RSCAN0.TMSTS22
+#define RSCAN0TMSTS23 RSCAN0.TMSTS23
+#define RSCAN0TMSTS24 RSCAN0.TMSTS24
+#define RSCAN0TMSTS25 RSCAN0.TMSTS25
+#define RSCAN0TMSTS26 RSCAN0.TMSTS26
+#define RSCAN0TMSTS27 RSCAN0.TMSTS27
+#define RSCAN0TMSTS28 RSCAN0.TMSTS28
+#define RSCAN0TMSTS29 RSCAN0.TMSTS29
+#define RSCAN0TMSTS30 RSCAN0.TMSTS30
+#define RSCAN0TMSTS31 RSCAN0.TMSTS31
+#define RSCAN0TMSTS32 RSCAN0.TMSTS32
+#define RSCAN0TMSTS33 RSCAN0.TMSTS33
+#define RSCAN0TMSTS34 RSCAN0.TMSTS34
+#define RSCAN0TMSTS35 RSCAN0.TMSTS35
+#define RSCAN0TMSTS36 RSCAN0.TMSTS36
+#define RSCAN0TMSTS37 RSCAN0.TMSTS37
+#define RSCAN0TMSTS38 RSCAN0.TMSTS38
+#define RSCAN0TMSTS39 RSCAN0.TMSTS39
+#define RSCAN0TMSTS40 RSCAN0.TMSTS40
+#define RSCAN0TMSTS41 RSCAN0.TMSTS41
+#define RSCAN0TMSTS42 RSCAN0.TMSTS42
+#define RSCAN0TMSTS43 RSCAN0.TMSTS43
+#define RSCAN0TMSTS44 RSCAN0.TMSTS44
+#define RSCAN0TMSTS45 RSCAN0.TMSTS45
+#define RSCAN0TMSTS46 RSCAN0.TMSTS46
+#define RSCAN0TMSTS47 RSCAN0.TMSTS47
+#define RSCAN0TMSTS48 RSCAN0.TMSTS48
+#define RSCAN0TMSTS49 RSCAN0.TMSTS49
+#define RSCAN0TMSTS50 RSCAN0.TMSTS50
+#define RSCAN0TMSTS51 RSCAN0.TMSTS51
+#define RSCAN0TMSTS52 RSCAN0.TMSTS52
+#define RSCAN0TMSTS53 RSCAN0.TMSTS53
+#define RSCAN0TMSTS54 RSCAN0.TMSTS54
+#define RSCAN0TMSTS55 RSCAN0.TMSTS55
+#define RSCAN0TMSTS56 RSCAN0.TMSTS56
+#define RSCAN0TMSTS57 RSCAN0.TMSTS57
+#define RSCAN0TMSTS58 RSCAN0.TMSTS58
+#define RSCAN0TMSTS59 RSCAN0.TMSTS59
+#define RSCAN0TMSTS60 RSCAN0.TMSTS60
+#define RSCAN0TMSTS61 RSCAN0.TMSTS61
+#define RSCAN0TMSTS62 RSCAN0.TMSTS62
+#define RSCAN0TMSTS63 RSCAN0.TMSTS63
+#define RSCAN0TMSTS64 RSCAN0.TMSTS64
+#define RSCAN0TMSTS65 RSCAN0.TMSTS65
+#define RSCAN0TMSTS66 RSCAN0.TMSTS66
+#define RSCAN0TMSTS67 RSCAN0.TMSTS67
+#define RSCAN0TMSTS68 RSCAN0.TMSTS68
+#define RSCAN0TMSTS69 RSCAN0.TMSTS69
+#define RSCAN0TMSTS70 RSCAN0.TMSTS70
+#define RSCAN0TMSTS71 RSCAN0.TMSTS71
+#define RSCAN0TMSTS72 RSCAN0.TMSTS72
+#define RSCAN0TMSTS73 RSCAN0.TMSTS73
+#define RSCAN0TMSTS74 RSCAN0.TMSTS74
+#define RSCAN0TMSTS75 RSCAN0.TMSTS75
+#define RSCAN0TMSTS76 RSCAN0.TMSTS76
+#define RSCAN0TMSTS77 RSCAN0.TMSTS77
+#define RSCAN0TMSTS78 RSCAN0.TMSTS78
+#define RSCAN0TMSTS79 RSCAN0.TMSTS79
+#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
+#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
+#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
+#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
+#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
+#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
+#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
+#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
+#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
+#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
+#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
+#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
+#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
+#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
+#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
+#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
+#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
+#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
+#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
+#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
+#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
+#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
+#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
+#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
+#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
+#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
+#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
+#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
+#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
+#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
+#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
+#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
+#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
+#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
+#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
+#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
+#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
+#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
+#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
+#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
+#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
+#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
+#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
+#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
+#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
+#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
+#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
+#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
+#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
+#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
+#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
+#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
+#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
+#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
+#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
+#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
+#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
+#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
+#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
+#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
+#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
+#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
+#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
+#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
+#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
+#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
+#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
+#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
+#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
+#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
+#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
+#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
+#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
+#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
+#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
+#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
+#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
+#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
+#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
+#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
+#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
+#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
+#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
+#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
+#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
+#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
+#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
+#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
+#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
+#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
+#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
+#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
+#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
+#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
+#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
+#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
+#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
+#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
+#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
+#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
+#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
+#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
+#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
+#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
+#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
+#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
+#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
+#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
+#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
+#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
+#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
+#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
+#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
+#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
+#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
+#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
+#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
+#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
+#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
+#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
+#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
+#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
+#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
+#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
+#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
+#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
+#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
+#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
+#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
+#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
+#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
+#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
+#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
+#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
+#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
+#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
+#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
+#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
+#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
+#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
+#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
+#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
+#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
+#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
+#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
+#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
+#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
+#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
+#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
+#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
+#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
+#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
+#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
+#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
+#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
+#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
+#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
+#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
+#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
+#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
+#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
+#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
+#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
+#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
+#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
+#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
+#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
+#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
+#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
+#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
+#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
+#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
+#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
+#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
+#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
+#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
+#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
+#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
+#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
+#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
+#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
+#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
+#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
+#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
+#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
+#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
+#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
+#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
+#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
+#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
+#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
+#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
+#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
+#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
+#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
+#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
+#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
+#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
+#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
+#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
+#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
+#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
+#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
+#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
+#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
+#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
+#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
+#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
+#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
+#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
+#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
+#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
+#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
+#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
+#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
+#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
+#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
+#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
+#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
+#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
+#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
+#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
+#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
+#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
+#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
+#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
+#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
+#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
+#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
+#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
+#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
+#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
+#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
+#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
+#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
+#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
+#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
+#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
+#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
+#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
+#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
+#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
+#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
+#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
+#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
+#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
+#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
+#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
+#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
+#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
+#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
+#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
+#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
+#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
+#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
+#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
+#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
+#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
+#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
+#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
+#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
+#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
+#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
+#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
+#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
+#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
+#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
+#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
+#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
+#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
+#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
+#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
+#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
+#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
+#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
+#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
+#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
+#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
+#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
+#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
+#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
+#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
+#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
+#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
+#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
+#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
+#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
+#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
+#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
+#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
+#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
+#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
+#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
+#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
+#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
+#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
+#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
+#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
+#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
+#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
+#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
+#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
+#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
+#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
+#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
+#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
+#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
+#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
+#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
+#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
+#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
+#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
+#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
+#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
+#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
+#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
+#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
+#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
+#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
+#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
+#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
+#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
+#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
+#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
+#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
+#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
+#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
+#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
+#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
+#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
+#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
+#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
+#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
+#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
+#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
+#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
+#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
+#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
+#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
+#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
+#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
+#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
+#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
+#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
+#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
+#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
+#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
+#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
+#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
+#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
+#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
+#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
+#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
+#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
+#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
+#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
+#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
+#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
+#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
+#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
+#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
+#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
+#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
+#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
+#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
+#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
+#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
+#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
+#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
+#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
+#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
+#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
+#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
+#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
+#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
+#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
+#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
+#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
+#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
+#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
+#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
+#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
+#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
+#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
+#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
+#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
+#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
+#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
+#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
+#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
+#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
+#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
+#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
+#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
+#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
+#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
+#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
+#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
+#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
+#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
+#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
+#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
+#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
+#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
+#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
+#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
+#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
+#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
+#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
+#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
+#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
+#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
+#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
+#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
+#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
+#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
+#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
+#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
+#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
+#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
+#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
+#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
+#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
+#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
+#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
+#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
+#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
+#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
+#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
+#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
+#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
+#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
+#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
+#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
+#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
+#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
+#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
+#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
+#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
+#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
+#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
+#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
+#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
+#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
+#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
+#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
+#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
+#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
+#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
+#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
+#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
+#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
+#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
+#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
+#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
+#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
+#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
+#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
+#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
+#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
+#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
+#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
+#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
+#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
+#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
+#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
+#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
+#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
+#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
+#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
+#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
+#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
+#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
+#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
+#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
+#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
+#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
+#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
+#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
+#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
+#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
+#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
+#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
+#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
+#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
+#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
+#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
+#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
+#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
+#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
+#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
+#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
+#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
+#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
+#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
+#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
+#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
+#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
+#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
+#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
+#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
+#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
+#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
+#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
+#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
+#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
+#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
+#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
+#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
+#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
+#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
+#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
+#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
+#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
+#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
+#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
+#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
+#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
+#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
+#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
+#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
+#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
+#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
+#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
+#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
+#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
+#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
+#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
+#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
+#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
+#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
+#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
+#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
+#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
+#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
+#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
+#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
+#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
+#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
+#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
+#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
+#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
+#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
+#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
+#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
+#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
+#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
+#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
+#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
+#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
+#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
+#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
+#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
+#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
+#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
+#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
+#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
+#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
+#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
+#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
+#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
+#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
+#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
+#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
+#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
+#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
+#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
+#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
+#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
+#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
+#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
+#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
+#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
+#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
+#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
+#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
+#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
+#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
+#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
+#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
+#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
+#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
+#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
+#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
+#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
+#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
+#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
+#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
+#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
+#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
+#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
+#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
+#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
+#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
+#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
+#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
+#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
+#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
+#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
+#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
+#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
+#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
+#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
+#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
+#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
+#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
+#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
+#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
+#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
+#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
+#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
+#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
+#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
+#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
+#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
+#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
+#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
+#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
+#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
+#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
+#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
+#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
+#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
+#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
+#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
+#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
+#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
+#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
+#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
+#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
+#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
+#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
+#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
+#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
+#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
+#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
+#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
+#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
+#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
+#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
+#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
+#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
+#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
+#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
+#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
+#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
+#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
+#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
+#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
+#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
+#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
+#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
+#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
+#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
+#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
+#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
+#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
+#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
+#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
+#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
+#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
+#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
+#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
+#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
+#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
+#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
+#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
+#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
+#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
+#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
+#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
+#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
+#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
+#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
+#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
+#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
+#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
+#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
+#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
+#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
+#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
+#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
+#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
+#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
+#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
+#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
+#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
+#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
+#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
+#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
+#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
+#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
+#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
+#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
+#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
+#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
+#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
+#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
+#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
+#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
+#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
+#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
+#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
+#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
+#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
+#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
+#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
+#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
+#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
+#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
+#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
+#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
+#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
+#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
+#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
+#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
+#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
+#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
+#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
+#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
+#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
+#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
+#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
+#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
+#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
+#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
+#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
+#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
+#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
+#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
+#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
+#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
+#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
+#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
+#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
+#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
+#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
+#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
+#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
+#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
+#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
+#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
+#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
+#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
+#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
+#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
+#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
+#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
+#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
+#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
+#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
+#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
+#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
+#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
+#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
+#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
+#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
+#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
+#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
+#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
+#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
+#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
+#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
+#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
+#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
+#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
+#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
+#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
+#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
+#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
+#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
+#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
+#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
+#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
+#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
+#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
+#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
+#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
+#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
+#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
+#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
+#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
+#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
+#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
+#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
+#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
+#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
+#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
+#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
+#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
+#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
+#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
+#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
+#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
+#define RSCAN0RMID0 RSCAN0.RMID0.UINT32
+#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
+#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
+#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
+#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
+#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
+#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
+#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
+#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
+#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
+#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
+#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
+#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
+#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
+#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
+#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
+#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
+#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
+#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
+#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
+#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
+#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
+#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
+#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
+#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
+#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
+#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
+#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
+#define RSCAN0RMID1 RSCAN0.RMID1.UINT32
+#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
+#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
+#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
+#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
+#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
+#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
+#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
+#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
+#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
+#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
+#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
+#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
+#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
+#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
+#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
+#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
+#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
+#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
+#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
+#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
+#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
+#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
+#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
+#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
+#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
+#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
+#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
+#define RSCAN0RMID2 RSCAN0.RMID2.UINT32
+#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
+#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
+#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
+#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
+#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
+#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
+#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
+#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
+#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
+#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
+#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
+#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
+#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
+#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
+#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
+#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
+#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
+#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
+#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
+#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
+#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
+#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
+#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
+#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
+#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
+#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
+#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
+#define RSCAN0RMID3 RSCAN0.RMID3.UINT32
+#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
+#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
+#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
+#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
+#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
+#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
+#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
+#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
+#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
+#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
+#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
+#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
+#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
+#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
+#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
+#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
+#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
+#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
+#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
+#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
+#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
+#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
+#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
+#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
+#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
+#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
+#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
+#define RSCAN0RMID4 RSCAN0.RMID4.UINT32
+#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
+#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
+#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
+#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
+#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
+#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
+#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
+#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
+#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
+#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
+#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
+#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
+#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
+#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
+#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
+#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
+#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
+#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
+#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
+#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
+#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
+#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
+#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
+#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
+#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
+#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
+#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
+#define RSCAN0RMID5 RSCAN0.RMID5.UINT32
+#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
+#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
+#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
+#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
+#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
+#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
+#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
+#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
+#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
+#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
+#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
+#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
+#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
+#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
+#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
+#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
+#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
+#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
+#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
+#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
+#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
+#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
+#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
+#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
+#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
+#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
+#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
+#define RSCAN0RMID6 RSCAN0.RMID6.UINT32
+#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
+#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
+#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
+#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
+#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
+#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
+#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
+#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
+#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
+#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
+#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
+#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
+#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
+#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
+#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
+#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
+#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
+#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
+#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
+#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
+#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
+#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
+#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
+#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
+#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
+#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
+#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
+#define RSCAN0RMID7 RSCAN0.RMID7.UINT32
+#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
+#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
+#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
+#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
+#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
+#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
+#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
+#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
+#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
+#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
+#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
+#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
+#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
+#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
+#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
+#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
+#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
+#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
+#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
+#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
+#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
+#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
+#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
+#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
+#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
+#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
+#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
+#define RSCAN0RMID8 RSCAN0.RMID8.UINT32
+#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
+#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
+#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
+#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
+#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
+#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
+#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
+#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
+#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
+#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
+#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
+#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
+#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
+#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
+#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
+#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
+#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
+#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
+#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
+#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
+#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
+#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
+#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
+#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
+#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
+#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
+#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
+#define RSCAN0RMID9 RSCAN0.RMID9.UINT32
+#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
+#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
+#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
+#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
+#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
+#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
+#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
+#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
+#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
+#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
+#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
+#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
+#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
+#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
+#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
+#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
+#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
+#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
+#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
+#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
+#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
+#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
+#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
+#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
+#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
+#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
+#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
+#define RSCAN0RMID10 RSCAN0.RMID10.UINT32
+#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
+#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
+#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
+#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
+#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
+#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
+#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
+#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
+#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
+#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
+#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
+#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
+#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
+#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
+#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
+#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
+#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
+#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
+#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
+#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
+#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
+#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
+#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
+#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
+#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
+#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
+#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
+#define RSCAN0RMID11 RSCAN0.RMID11.UINT32
+#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
+#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
+#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
+#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
+#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
+#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
+#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
+#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
+#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
+#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
+#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
+#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
+#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
+#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
+#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
+#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
+#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
+#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
+#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
+#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
+#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
+#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
+#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
+#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
+#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
+#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
+#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
+#define RSCAN0RMID12 RSCAN0.RMID12.UINT32
+#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
+#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
+#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
+#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
+#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
+#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
+#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
+#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
+#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
+#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
+#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
+#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
+#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
+#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
+#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
+#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
+#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
+#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
+#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
+#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
+#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
+#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
+#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
+#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
+#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
+#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
+#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
+#define RSCAN0RMID13 RSCAN0.RMID13.UINT32
+#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
+#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
+#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
+#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
+#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
+#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
+#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
+#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
+#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
+#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
+#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
+#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
+#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
+#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
+#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
+#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
+#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
+#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
+#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
+#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
+#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
+#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
+#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
+#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
+#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
+#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
+#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
+#define RSCAN0RMID14 RSCAN0.RMID14.UINT32
+#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
+#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
+#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
+#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
+#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
+#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
+#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
+#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
+#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
+#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
+#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
+#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
+#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
+#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
+#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
+#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
+#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
+#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
+#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
+#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
+#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
+#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
+#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
+#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
+#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
+#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
+#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
+#define RSCAN0RMID15 RSCAN0.RMID15.UINT32
+#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
+#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
+#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
+#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
+#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
+#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
+#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
+#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
+#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
+#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
+#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
+#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
+#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
+#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
+#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
+#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
+#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
+#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
+#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
+#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
+#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
+#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
+#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
+#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
+#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
+#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
+#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
+#define RSCAN0RMID16 RSCAN0.RMID16.UINT32
+#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
+#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
+#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
+#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
+#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
+#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
+#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
+#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
+#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
+#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
+#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
+#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
+#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
+#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
+#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
+#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
+#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
+#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
+#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
+#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
+#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
+#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
+#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
+#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
+#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
+#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
+#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
+#define RSCAN0RMID17 RSCAN0.RMID17.UINT32
+#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
+#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
+#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
+#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
+#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
+#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
+#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
+#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
+#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
+#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
+#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
+#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
+#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
+#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
+#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
+#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
+#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
+#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
+#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
+#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
+#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
+#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
+#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
+#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
+#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
+#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
+#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
+#define RSCAN0RMID18 RSCAN0.RMID18.UINT32
+#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
+#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
+#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
+#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
+#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
+#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
+#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
+#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
+#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
+#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
+#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
+#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
+#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
+#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
+#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
+#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
+#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
+#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
+#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
+#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
+#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
+#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
+#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
+#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
+#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
+#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
+#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
+#define RSCAN0RMID19 RSCAN0.RMID19.UINT32
+#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
+#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
+#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
+#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
+#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
+#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
+#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
+#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
+#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
+#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
+#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
+#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
+#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
+#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
+#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
+#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
+#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
+#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
+#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
+#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
+#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
+#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
+#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
+#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
+#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
+#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
+#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
+#define RSCAN0RMID20 RSCAN0.RMID20.UINT32
+#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
+#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
+#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
+#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
+#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
+#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
+#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
+#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
+#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
+#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
+#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
+#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
+#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
+#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
+#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
+#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
+#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
+#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
+#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
+#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
+#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
+#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
+#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
+#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
+#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
+#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
+#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
+#define RSCAN0RMID21 RSCAN0.RMID21.UINT32
+#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
+#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
+#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
+#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
+#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
+#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
+#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
+#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
+#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
+#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
+#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
+#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
+#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
+#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
+#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
+#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
+#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
+#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
+#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
+#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
+#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
+#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
+#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
+#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
+#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
+#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
+#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
+#define RSCAN0RMID22 RSCAN0.RMID22.UINT32
+#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
+#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
+#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
+#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
+#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
+#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
+#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
+#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
+#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
+#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
+#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
+#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
+#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
+#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
+#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
+#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
+#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
+#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
+#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
+#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
+#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
+#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
+#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
+#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
+#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
+#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
+#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
+#define RSCAN0RMID23 RSCAN0.RMID23.UINT32
+#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
+#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
+#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
+#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
+#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
+#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
+#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
+#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
+#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
+#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
+#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
+#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
+#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
+#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
+#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
+#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
+#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
+#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
+#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
+#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
+#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
+#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
+#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
+#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
+#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
+#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
+#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
+#define RSCAN0RMID24 RSCAN0.RMID24.UINT32
+#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
+#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
+#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
+#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
+#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
+#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
+#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
+#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
+#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
+#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
+#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
+#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
+#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
+#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
+#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
+#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
+#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
+#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
+#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
+#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
+#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
+#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
+#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
+#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
+#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
+#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
+#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
+#define RSCAN0RMID25 RSCAN0.RMID25.UINT32
+#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
+#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
+#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
+#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
+#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
+#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
+#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
+#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
+#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
+#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
+#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
+#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
+#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
+#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
+#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
+#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
+#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
+#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
+#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
+#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
+#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
+#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
+#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
+#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
+#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
+#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
+#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
+#define RSCAN0RMID26 RSCAN0.RMID26.UINT32
+#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
+#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
+#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
+#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
+#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
+#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
+#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
+#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
+#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
+#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
+#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
+#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
+#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
+#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
+#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
+#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
+#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
+#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
+#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
+#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
+#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
+#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
+#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
+#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
+#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
+#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
+#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
+#define RSCAN0RMID27 RSCAN0.RMID27.UINT32
+#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
+#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
+#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
+#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
+#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
+#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
+#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
+#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
+#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
+#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
+#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
+#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
+#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
+#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
+#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
+#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
+#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
+#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
+#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
+#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
+#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
+#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
+#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
+#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
+#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
+#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
+#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
+#define RSCAN0RMID28 RSCAN0.RMID28.UINT32
+#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
+#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
+#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
+#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
+#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
+#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
+#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
+#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
+#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
+#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
+#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
+#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
+#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
+#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
+#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
+#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
+#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
+#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
+#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
+#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
+#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
+#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
+#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
+#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
+#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
+#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
+#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
+#define RSCAN0RMID29 RSCAN0.RMID29.UINT32
+#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
+#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
+#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
+#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
+#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
+#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
+#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
+#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
+#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
+#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
+#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
+#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
+#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
+#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
+#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
+#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
+#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
+#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
+#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
+#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
+#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
+#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
+#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
+#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
+#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
+#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
+#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
+#define RSCAN0RMID30 RSCAN0.RMID30.UINT32
+#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
+#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
+#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
+#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
+#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
+#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
+#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
+#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
+#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
+#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
+#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
+#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
+#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
+#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
+#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
+#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
+#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
+#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
+#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
+#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
+#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
+#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
+#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
+#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
+#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
+#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
+#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
+#define RSCAN0RMID31 RSCAN0.RMID31.UINT32
+#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
+#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
+#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
+#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
+#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
+#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
+#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
+#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
+#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
+#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
+#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
+#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
+#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
+#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
+#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
+#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
+#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
+#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
+#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
+#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
+#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
+#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
+#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
+#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
+#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
+#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
+#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
+#define RSCAN0RMID32 RSCAN0.RMID32.UINT32
+#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
+#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
+#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
+#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
+#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
+#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
+#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
+#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
+#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
+#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
+#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
+#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
+#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
+#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
+#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
+#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
+#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
+#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
+#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
+#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
+#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
+#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
+#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
+#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
+#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
+#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
+#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
+#define RSCAN0RMID33 RSCAN0.RMID33.UINT32
+#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
+#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
+#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
+#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
+#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
+#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
+#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
+#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
+#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
+#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
+#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
+#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
+#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
+#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
+#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
+#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
+#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
+#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
+#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
+#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
+#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
+#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
+#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
+#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
+#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
+#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
+#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
+#define RSCAN0RMID34 RSCAN0.RMID34.UINT32
+#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
+#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
+#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
+#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
+#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
+#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
+#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
+#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
+#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
+#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
+#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
+#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
+#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
+#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
+#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
+#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
+#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
+#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
+#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
+#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
+#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
+#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
+#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
+#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
+#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
+#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
+#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
+#define RSCAN0RMID35 RSCAN0.RMID35.UINT32
+#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
+#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
+#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
+#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
+#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
+#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
+#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
+#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
+#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
+#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
+#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
+#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
+#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
+#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
+#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
+#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
+#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
+#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
+#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
+#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
+#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
+#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
+#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
+#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
+#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
+#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
+#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
+#define RSCAN0RMID36 RSCAN0.RMID36.UINT32
+#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
+#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
+#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
+#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
+#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
+#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
+#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
+#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
+#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
+#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
+#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
+#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
+#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
+#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
+#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
+#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
+#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
+#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
+#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
+#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
+#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
+#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
+#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
+#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
+#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
+#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
+#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
+#define RSCAN0RMID37 RSCAN0.RMID37.UINT32
+#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
+#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
+#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
+#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
+#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
+#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
+#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
+#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
+#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
+#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
+#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
+#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
+#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
+#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
+#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
+#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
+#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
+#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
+#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
+#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
+#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
+#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
+#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
+#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
+#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
+#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
+#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
+#define RSCAN0RMID38 RSCAN0.RMID38.UINT32
+#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
+#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
+#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
+#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
+#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
+#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
+#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
+#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
+#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
+#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
+#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
+#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
+#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
+#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
+#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
+#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
+#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
+#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
+#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
+#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
+#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
+#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
+#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
+#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
+#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
+#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
+#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
+#define RSCAN0RMID39 RSCAN0.RMID39.UINT32
+#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
+#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
+#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
+#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
+#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
+#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
+#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
+#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
+#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
+#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
+#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
+#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
+#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
+#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
+#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
+#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
+#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
+#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
+#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
+#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
+#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
+#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
+#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
+#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
+#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
+#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
+#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
+#define RSCAN0RMID40 RSCAN0.RMID40.UINT32
+#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
+#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
+#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
+#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
+#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
+#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
+#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
+#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
+#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
+#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
+#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
+#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
+#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
+#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
+#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
+#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
+#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
+#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
+#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
+#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
+#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
+#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
+#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
+#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
+#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
+#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
+#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
+#define RSCAN0RMID41 RSCAN0.RMID41.UINT32
+#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
+#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
+#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
+#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
+#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
+#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
+#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
+#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
+#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
+#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
+#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
+#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
+#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
+#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
+#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
+#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
+#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
+#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
+#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
+#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
+#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
+#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
+#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
+#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
+#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
+#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
+#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
+#define RSCAN0RMID42 RSCAN0.RMID42.UINT32
+#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
+#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
+#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
+#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
+#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
+#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
+#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
+#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
+#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
+#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
+#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
+#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
+#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
+#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
+#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
+#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
+#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
+#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
+#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
+#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
+#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
+#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
+#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
+#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
+#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
+#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
+#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
+#define RSCAN0RMID43 RSCAN0.RMID43.UINT32
+#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
+#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
+#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
+#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
+#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
+#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
+#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
+#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
+#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
+#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
+#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
+#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
+#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
+#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
+#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
+#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
+#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
+#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
+#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
+#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
+#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
+#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
+#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
+#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
+#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
+#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
+#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
+#define RSCAN0RMID44 RSCAN0.RMID44.UINT32
+#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
+#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
+#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
+#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
+#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
+#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
+#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
+#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
+#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
+#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
+#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
+#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
+#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
+#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
+#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
+#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
+#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
+#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
+#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
+#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
+#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
+#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
+#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
+#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
+#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
+#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
+#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
+#define RSCAN0RMID45 RSCAN0.RMID45.UINT32
+#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
+#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
+#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
+#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
+#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
+#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
+#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
+#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
+#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
+#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
+#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
+#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
+#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
+#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
+#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
+#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
+#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
+#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
+#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
+#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
+#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
+#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
+#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
+#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
+#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
+#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
+#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
+#define RSCAN0RMID46 RSCAN0.RMID46.UINT32
+#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
+#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
+#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
+#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
+#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
+#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
+#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
+#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
+#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
+#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
+#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
+#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
+#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
+#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
+#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
+#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
+#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
+#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
+#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
+#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
+#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
+#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
+#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
+#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
+#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
+#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
+#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
+#define RSCAN0RMID47 RSCAN0.RMID47.UINT32
+#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
+#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
+#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
+#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
+#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
+#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
+#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
+#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
+#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
+#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
+#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
+#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
+#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
+#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
+#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
+#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
+#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
+#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
+#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
+#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
+#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
+#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
+#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
+#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
+#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
+#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
+#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
+#define RSCAN0RMID48 RSCAN0.RMID48.UINT32
+#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
+#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
+#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
+#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
+#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
+#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
+#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
+#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
+#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
+#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
+#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
+#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
+#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
+#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
+#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
+#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
+#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
+#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
+#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
+#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
+#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
+#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
+#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
+#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
+#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
+#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
+#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
+#define RSCAN0RMID49 RSCAN0.RMID49.UINT32
+#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
+#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
+#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
+#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
+#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
+#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
+#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
+#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
+#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
+#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
+#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
+#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
+#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
+#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
+#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
+#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
+#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
+#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
+#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
+#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
+#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
+#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
+#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
+#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
+#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
+#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
+#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
+#define RSCAN0RMID50 RSCAN0.RMID50.UINT32
+#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
+#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
+#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
+#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
+#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
+#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
+#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
+#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
+#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
+#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
+#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
+#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
+#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
+#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
+#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
+#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
+#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
+#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
+#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
+#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
+#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
+#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
+#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
+#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
+#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
+#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
+#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
+#define RSCAN0RMID51 RSCAN0.RMID51.UINT32
+#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
+#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
+#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
+#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
+#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
+#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
+#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
+#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
+#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
+#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
+#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
+#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
+#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
+#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
+#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
+#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
+#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
+#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
+#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
+#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
+#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
+#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
+#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
+#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
+#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
+#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
+#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
+#define RSCAN0RMID52 RSCAN0.RMID52.UINT32
+#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
+#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
+#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
+#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
+#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
+#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
+#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
+#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
+#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
+#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
+#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
+#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
+#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
+#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
+#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
+#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
+#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
+#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
+#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
+#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
+#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
+#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
+#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
+#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
+#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
+#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
+#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
+#define RSCAN0RMID53 RSCAN0.RMID53.UINT32
+#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
+#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
+#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
+#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
+#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
+#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
+#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
+#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
+#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
+#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
+#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
+#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
+#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
+#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
+#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
+#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
+#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
+#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
+#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
+#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
+#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
+#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
+#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
+#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
+#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
+#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
+#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
+#define RSCAN0RMID54 RSCAN0.RMID54.UINT32
+#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
+#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
+#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
+#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
+#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
+#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
+#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
+#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
+#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
+#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
+#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
+#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
+#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
+#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
+#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
+#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
+#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
+#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
+#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
+#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
+#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
+#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
+#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
+#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
+#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
+#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
+#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
+#define RSCAN0RMID55 RSCAN0.RMID55.UINT32
+#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
+#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
+#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
+#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
+#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
+#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
+#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
+#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
+#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
+#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
+#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
+#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
+#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
+#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
+#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
+#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
+#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
+#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
+#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
+#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
+#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
+#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
+#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
+#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
+#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
+#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
+#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
+#define RSCAN0RMID56 RSCAN0.RMID56.UINT32
+#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
+#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
+#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
+#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
+#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
+#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
+#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
+#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
+#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
+#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
+#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
+#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
+#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
+#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
+#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
+#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
+#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
+#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
+#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
+#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
+#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
+#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
+#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
+#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
+#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
+#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
+#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
+#define RSCAN0RMID57 RSCAN0.RMID57.UINT32
+#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
+#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
+#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
+#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
+#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
+#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
+#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
+#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
+#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
+#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
+#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
+#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
+#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
+#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
+#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
+#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
+#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
+#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
+#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
+#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
+#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
+#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
+#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
+#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
+#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
+#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
+#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
+#define RSCAN0RMID58 RSCAN0.RMID58.UINT32
+#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
+#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
+#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
+#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
+#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
+#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
+#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
+#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
+#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
+#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
+#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
+#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
+#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
+#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
+#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
+#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
+#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
+#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
+#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
+#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
+#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
+#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
+#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
+#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
+#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
+#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
+#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
+#define RSCAN0RMID59 RSCAN0.RMID59.UINT32
+#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
+#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
+#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
+#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
+#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
+#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
+#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
+#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
+#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
+#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
+#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
+#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
+#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
+#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
+#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
+#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
+#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
+#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
+#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
+#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
+#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
+#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
+#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
+#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
+#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
+#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
+#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
+#define RSCAN0RMID60 RSCAN0.RMID60.UINT32
+#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
+#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
+#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
+#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
+#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
+#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
+#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
+#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
+#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
+#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
+#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
+#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
+#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
+#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
+#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
+#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
+#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
+#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
+#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
+#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
+#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
+#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
+#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
+#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
+#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
+#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
+#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
+#define RSCAN0RMID61 RSCAN0.RMID61.UINT32
+#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
+#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
+#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
+#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
+#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
+#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
+#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
+#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
+#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
+#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
+#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
+#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
+#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
+#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
+#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
+#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
+#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
+#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
+#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
+#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
+#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
+#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
+#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
+#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
+#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
+#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
+#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
+#define RSCAN0RMID62 RSCAN0.RMID62.UINT32
+#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
+#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
+#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
+#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
+#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
+#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
+#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
+#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
+#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
+#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
+#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
+#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
+#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
+#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
+#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
+#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
+#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
+#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
+#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
+#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
+#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
+#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
+#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
+#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
+#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
+#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
+#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
+#define RSCAN0RMID63 RSCAN0.RMID63.UINT32
+#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
+#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
+#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
+#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
+#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
+#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
+#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
+#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
+#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
+#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
+#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
+#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
+#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
+#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
+#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
+#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
+#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
+#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
+#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
+#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
+#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
+#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
+#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
+#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
+#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
+#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
+#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
+#define RSCAN0RMID64 RSCAN0.RMID64.UINT32
+#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
+#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
+#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
+#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
+#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
+#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
+#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
+#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
+#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
+#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
+#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
+#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
+#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
+#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
+#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
+#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
+#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
+#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
+#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
+#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
+#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
+#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
+#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
+#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
+#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
+#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
+#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
+#define RSCAN0RMID65 RSCAN0.RMID65.UINT32
+#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
+#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
+#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
+#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
+#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
+#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
+#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
+#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
+#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
+#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
+#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
+#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
+#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
+#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
+#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
+#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
+#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
+#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
+#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
+#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
+#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
+#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
+#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
+#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
+#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
+#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
+#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
+#define RSCAN0RMID66 RSCAN0.RMID66.UINT32
+#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
+#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
+#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
+#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
+#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
+#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
+#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
+#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
+#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
+#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
+#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
+#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
+#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
+#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
+#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
+#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
+#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
+#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
+#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
+#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
+#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
+#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
+#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
+#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
+#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
+#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
+#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
+#define RSCAN0RMID67 RSCAN0.RMID67.UINT32
+#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
+#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
+#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
+#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
+#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
+#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
+#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
+#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
+#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
+#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
+#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
+#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
+#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
+#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
+#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
+#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
+#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
+#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
+#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
+#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
+#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
+#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
+#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
+#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
+#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
+#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
+#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
+#define RSCAN0RMID68 RSCAN0.RMID68.UINT32
+#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
+#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
+#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
+#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
+#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
+#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
+#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
+#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
+#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
+#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
+#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
+#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
+#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
+#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
+#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
+#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
+#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
+#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
+#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
+#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
+#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
+#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
+#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
+#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
+#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
+#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
+#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
+#define RSCAN0RMID69 RSCAN0.RMID69.UINT32
+#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
+#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
+#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
+#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
+#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
+#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
+#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
+#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
+#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
+#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
+#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
+#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
+#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
+#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
+#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
+#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
+#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
+#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
+#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
+#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
+#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
+#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
+#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
+#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
+#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
+#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
+#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
+#define RSCAN0RMID70 RSCAN0.RMID70.UINT32
+#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
+#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
+#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
+#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
+#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
+#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
+#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
+#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
+#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
+#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
+#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
+#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
+#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
+#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
+#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
+#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
+#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
+#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
+#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
+#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
+#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
+#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
+#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
+#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
+#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
+#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
+#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
+#define RSCAN0RMID71 RSCAN0.RMID71.UINT32
+#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
+#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
+#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
+#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
+#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
+#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
+#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
+#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
+#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
+#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
+#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
+#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
+#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
+#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
+#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
+#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
+#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
+#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
+#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
+#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
+#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
+#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
+#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
+#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
+#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
+#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
+#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
+#define RSCAN0RMID72 RSCAN0.RMID72.UINT32
+#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
+#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
+#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
+#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
+#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
+#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
+#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
+#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
+#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
+#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
+#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
+#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
+#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
+#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
+#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
+#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
+#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
+#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
+#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
+#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
+#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
+#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
+#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
+#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
+#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
+#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
+#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
+#define RSCAN0RMID73 RSCAN0.RMID73.UINT32
+#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
+#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
+#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
+#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
+#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
+#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
+#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
+#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
+#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
+#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
+#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
+#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
+#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
+#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
+#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
+#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
+#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
+#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
+#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
+#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
+#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
+#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
+#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
+#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
+#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
+#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
+#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
+#define RSCAN0RMID74 RSCAN0.RMID74.UINT32
+#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
+#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
+#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
+#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
+#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
+#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
+#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
+#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
+#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
+#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
+#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
+#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
+#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
+#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
+#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
+#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
+#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
+#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
+#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
+#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
+#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
+#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
+#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
+#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
+#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
+#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
+#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
+#define RSCAN0RMID75 RSCAN0.RMID75.UINT32
+#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
+#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
+#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
+#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
+#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
+#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
+#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
+#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
+#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
+#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
+#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
+#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
+#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
+#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
+#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
+#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
+#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
+#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
+#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
+#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
+#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
+#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
+#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
+#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
+#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
+#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
+#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
+#define RSCAN0RMID76 RSCAN0.RMID76.UINT32
+#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
+#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
+#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
+#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
+#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
+#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
+#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
+#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
+#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
+#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
+#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
+#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
+#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
+#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
+#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
+#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
+#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
+#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
+#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
+#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
+#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
+#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
+#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
+#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
+#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
+#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
+#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
+#define RSCAN0RMID77 RSCAN0.RMID77.UINT32
+#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
+#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
+#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
+#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
+#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
+#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
+#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
+#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
+#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
+#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
+#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
+#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
+#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
+#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
+#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
+#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
+#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
+#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
+#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
+#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
+#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
+#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
+#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
+#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
+#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
+#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
+#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
+#define RSCAN0RMID78 RSCAN0.RMID78.UINT32
+#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
+#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
+#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
+#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
+#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
+#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
+#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
+#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
+#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
+#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
+#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
+#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
+#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
+#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
+#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
+#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
+#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
+#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
+#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
+#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
+#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
+#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
+#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
+#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
+#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
+#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
+#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
+#define RSCAN0RMID79 RSCAN0.RMID79.UINT32
+#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
+#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
+#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
+#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
+#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
+#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
+#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
+#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
+#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
+#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
+#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
+#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
+#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
+#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
+#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
+#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
+#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
+#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
+#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
+#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
+#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
+#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
+#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
+#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
+#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
+#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
+#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
+#define RSCAN0RFID0 RSCAN0.RFID0.UINT32
+#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
+#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
+#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
+#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
+#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
+#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
+#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
+#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
+#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
+#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
+#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
+#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
+#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
+#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
+#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
+#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
+#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
+#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
+#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
+#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
+#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
+#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
+#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
+#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
+#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
+#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
+#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
+#define RSCAN0RFID1 RSCAN0.RFID1.UINT32
+#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
+#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
+#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
+#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
+#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
+#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
+#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
+#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
+#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
+#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
+#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
+#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
+#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
+#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
+#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
+#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
+#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
+#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
+#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
+#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
+#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
+#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
+#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
+#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
+#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
+#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
+#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
+#define RSCAN0RFID2 RSCAN0.RFID2.UINT32
+#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
+#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
+#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
+#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
+#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
+#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
+#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
+#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
+#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
+#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
+#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
+#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
+#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
+#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
+#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
+#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
+#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
+#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
+#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
+#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
+#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
+#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
+#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
+#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
+#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
+#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
+#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
+#define RSCAN0RFID3 RSCAN0.RFID3.UINT32
+#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
+#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
+#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
+#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
+#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
+#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
+#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
+#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
+#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
+#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
+#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
+#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
+#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
+#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
+#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
+#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
+#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
+#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
+#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
+#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
+#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
+#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
+#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
+#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
+#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
+#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
+#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
+#define RSCAN0RFID4 RSCAN0.RFID4.UINT32
+#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
+#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
+#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
+#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
+#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
+#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
+#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
+#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
+#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
+#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
+#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
+#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
+#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
+#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
+#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
+#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
+#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
+#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
+#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
+#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
+#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
+#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
+#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
+#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
+#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
+#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
+#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
+#define RSCAN0RFID5 RSCAN0.RFID5.UINT32
+#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
+#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
+#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
+#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
+#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
+#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
+#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
+#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
+#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
+#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
+#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
+#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
+#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
+#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
+#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
+#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
+#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
+#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
+#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
+#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
+#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
+#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
+#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
+#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
+#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
+#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
+#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
+#define RSCAN0RFID6 RSCAN0.RFID6.UINT32
+#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
+#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
+#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
+#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
+#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
+#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
+#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
+#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
+#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
+#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
+#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
+#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
+#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
+#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
+#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
+#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
+#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
+#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
+#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
+#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
+#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
+#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
+#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
+#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
+#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
+#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
+#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
+#define RSCAN0RFID7 RSCAN0.RFID7.UINT32
+#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
+#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
+#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
+#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
+#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
+#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
+#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
+#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
+#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
+#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
+#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
+#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
+#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
+#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
+#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
+#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
+#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
+#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
+#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
+#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
+#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
+#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
+#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
+#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
+#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
+#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
+#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
+#define RSCAN0CFID0 RSCAN0.CFID0.UINT32
+#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
+#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
+#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
+#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
+#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
+#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
+#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
+#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
+#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
+#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
+#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
+#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
+#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
+#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
+#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
+#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
+#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
+#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
+#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
+#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
+#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
+#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
+#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
+#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
+#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
+#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
+#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
+#define RSCAN0CFID1 RSCAN0.CFID1.UINT32
+#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
+#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
+#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
+#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
+#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
+#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
+#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
+#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
+#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
+#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
+#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
+#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
+#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
+#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
+#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
+#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
+#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
+#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
+#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
+#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
+#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
+#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
+#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
+#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
+#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
+#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
+#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
+#define RSCAN0CFID2 RSCAN0.CFID2.UINT32
+#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
+#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
+#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
+#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
+#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
+#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
+#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
+#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
+#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
+#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
+#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
+#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
+#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
+#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
+#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
+#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
+#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
+#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
+#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
+#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
+#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
+#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
+#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
+#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
+#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
+#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
+#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
+#define RSCAN0CFID3 RSCAN0.CFID3.UINT32
+#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
+#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
+#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
+#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
+#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
+#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
+#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
+#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
+#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
+#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
+#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
+#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
+#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
+#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
+#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
+#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
+#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
+#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
+#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
+#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
+#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
+#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
+#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
+#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
+#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
+#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
+#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
+#define RSCAN0CFID4 RSCAN0.CFID4.UINT32
+#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
+#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
+#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
+#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
+#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
+#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
+#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
+#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
+#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
+#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
+#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
+#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
+#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
+#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
+#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
+#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
+#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
+#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
+#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
+#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
+#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
+#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
+#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
+#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
+#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
+#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
+#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
+#define RSCAN0CFID5 RSCAN0.CFID5.UINT32
+#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
+#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
+#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
+#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
+#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
+#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
+#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
+#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
+#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
+#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
+#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
+#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
+#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
+#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
+#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
+#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
+#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
+#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
+#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
+#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
+#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
+#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
+#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
+#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
+#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
+#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
+#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
+#define RSCAN0CFID6 RSCAN0.CFID6.UINT32
+#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
+#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
+#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
+#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
+#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
+#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
+#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
+#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
+#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
+#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
+#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
+#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
+#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
+#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
+#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
+#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
+#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
+#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
+#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
+#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
+#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
+#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
+#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
+#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
+#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
+#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
+#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
+#define RSCAN0CFID7 RSCAN0.CFID7.UINT32
+#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
+#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
+#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
+#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
+#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
+#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
+#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
+#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
+#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
+#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
+#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
+#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
+#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
+#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
+#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
+#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
+#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
+#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
+#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
+#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
+#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
+#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
+#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
+#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
+#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
+#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
+#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
+#define RSCAN0CFID8 RSCAN0.CFID8.UINT32
+#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
+#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
+#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
+#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
+#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
+#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
+#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
+#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
+#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
+#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
+#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
+#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
+#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
+#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
+#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
+#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
+#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
+#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
+#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
+#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
+#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
+#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
+#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
+#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
+#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
+#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
+#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
+#define RSCAN0CFID9 RSCAN0.CFID9.UINT32
+#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
+#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
+#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
+#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
+#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
+#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
+#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
+#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
+#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
+#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
+#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
+#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
+#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
+#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
+#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
+#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
+#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
+#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
+#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
+#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
+#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
+#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
+#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
+#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
+#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
+#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
+#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
+#define RSCAN0CFID10 RSCAN0.CFID10.UINT32
+#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
+#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
+#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
+#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
+#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
+#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
+#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
+#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
+#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
+#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
+#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
+#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
+#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
+#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
+#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
+#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
+#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
+#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
+#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
+#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
+#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
+#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
+#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
+#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
+#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
+#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
+#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
+#define RSCAN0CFID11 RSCAN0.CFID11.UINT32
+#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
+#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
+#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
+#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
+#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
+#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
+#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
+#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
+#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
+#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
+#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
+#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
+#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
+#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
+#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
+#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
+#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
+#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
+#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
+#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
+#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
+#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
+#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
+#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
+#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
+#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
+#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
+#define RSCAN0CFID12 RSCAN0.CFID12.UINT32
+#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
+#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
+#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
+#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
+#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
+#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
+#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
+#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
+#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
+#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
+#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
+#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
+#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
+#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
+#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
+#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
+#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
+#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
+#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
+#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
+#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
+#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
+#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
+#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
+#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
+#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
+#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
+#define RSCAN0CFID13 RSCAN0.CFID13.UINT32
+#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
+#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
+#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
+#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
+#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
+#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
+#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
+#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
+#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
+#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
+#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
+#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
+#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
+#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
+#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
+#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
+#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
+#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
+#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
+#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
+#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
+#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
+#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
+#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
+#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
+#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
+#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
+#define RSCAN0CFID14 RSCAN0.CFID14.UINT32
+#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
+#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
+#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
+#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
+#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
+#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
+#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
+#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
+#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
+#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
+#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
+#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
+#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
+#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
+#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
+#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
+#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
+#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
+#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
+#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
+#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
+#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
+#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
+#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
+#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
+#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
+#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
+#define RSCAN0TMID0 RSCAN0.TMID0.UINT32
+#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
+#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
+#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
+#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
+#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
+#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
+#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
+#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
+#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
+#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
+#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
+#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
+#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
+#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
+#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
+#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
+#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
+#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
+#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
+#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
+#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
+#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
+#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
+#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
+#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
+#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
+#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
+#define RSCAN0TMID1 RSCAN0.TMID1.UINT32
+#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
+#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
+#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
+#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
+#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
+#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
+#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
+#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
+#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
+#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
+#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
+#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
+#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
+#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
+#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
+#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
+#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
+#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
+#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
+#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
+#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
+#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
+#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
+#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
+#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
+#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
+#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
+#define RSCAN0TMID2 RSCAN0.TMID2.UINT32
+#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
+#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
+#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
+#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
+#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
+#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
+#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
+#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
+#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
+#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
+#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
+#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
+#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
+#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
+#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
+#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
+#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
+#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
+#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
+#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
+#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
+#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
+#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
+#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
+#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
+#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
+#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
+#define RSCAN0TMID3 RSCAN0.TMID3.UINT32
+#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
+#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
+#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
+#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
+#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
+#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
+#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
+#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
+#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
+#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
+#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
+#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
+#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
+#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
+#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
+#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
+#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
+#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
+#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
+#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
+#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
+#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
+#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
+#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
+#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
+#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
+#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
+#define RSCAN0TMID4 RSCAN0.TMID4.UINT32
+#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
+#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
+#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
+#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
+#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
+#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
+#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
+#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
+#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
+#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
+#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
+#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
+#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
+#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
+#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
+#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
+#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
+#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
+#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
+#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
+#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
+#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
+#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
+#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
+#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
+#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
+#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
+#define RSCAN0TMID5 RSCAN0.TMID5.UINT32
+#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
+#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
+#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
+#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
+#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
+#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
+#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
+#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
+#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
+#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
+#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
+#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
+#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
+#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
+#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
+#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
+#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
+#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
+#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
+#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
+#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
+#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
+#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
+#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
+#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
+#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
+#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
+#define RSCAN0TMID6 RSCAN0.TMID6.UINT32
+#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
+#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
+#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
+#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
+#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
+#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
+#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
+#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
+#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
+#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
+#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
+#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
+#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
+#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
+#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
+#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
+#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
+#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
+#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
+#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
+#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
+#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
+#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
+#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
+#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
+#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
+#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
+#define RSCAN0TMID7 RSCAN0.TMID7.UINT32
+#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
+#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
+#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
+#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
+#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
+#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
+#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
+#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
+#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
+#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
+#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
+#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
+#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
+#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
+#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
+#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
+#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
+#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
+#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
+#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
+#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
+#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
+#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
+#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
+#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
+#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
+#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
+#define RSCAN0TMID8 RSCAN0.TMID8.UINT32
+#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
+#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
+#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
+#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
+#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
+#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
+#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
+#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
+#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
+#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
+#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
+#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
+#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
+#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
+#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
+#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
+#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
+#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
+#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
+#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
+#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
+#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
+#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
+#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
+#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
+#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
+#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
+#define RSCAN0TMID9 RSCAN0.TMID9.UINT32
+#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
+#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
+#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
+#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
+#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
+#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
+#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
+#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
+#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
+#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
+#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
+#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
+#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
+#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
+#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
+#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
+#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
+#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
+#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
+#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
+#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
+#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
+#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
+#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
+#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
+#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
+#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
+#define RSCAN0TMID10 RSCAN0.TMID10.UINT32
+#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
+#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
+#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
+#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
+#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
+#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
+#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
+#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
+#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
+#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
+#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
+#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
+#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
+#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
+#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
+#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
+#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
+#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
+#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
+#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
+#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
+#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
+#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
+#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
+#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
+#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
+#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
+#define RSCAN0TMID11 RSCAN0.TMID11.UINT32
+#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
+#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
+#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
+#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
+#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
+#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
+#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
+#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
+#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
+#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
+#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
+#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
+#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
+#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
+#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
+#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
+#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
+#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
+#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
+#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
+#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
+#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
+#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
+#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
+#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
+#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
+#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
+#define RSCAN0TMID12 RSCAN0.TMID12.UINT32
+#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
+#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
+#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
+#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
+#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
+#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
+#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
+#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
+#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
+#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
+#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
+#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
+#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
+#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
+#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
+#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
+#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
+#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
+#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
+#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
+#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
+#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
+#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
+#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
+#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
+#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
+#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
+#define RSCAN0TMID13 RSCAN0.TMID13.UINT32
+#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
+#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
+#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
+#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
+#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
+#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
+#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
+#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
+#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
+#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
+#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
+#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
+#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
+#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
+#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
+#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
+#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
+#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
+#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
+#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
+#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
+#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
+#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
+#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
+#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
+#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
+#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
+#define RSCAN0TMID14 RSCAN0.TMID14.UINT32
+#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
+#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
+#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
+#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
+#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
+#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
+#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
+#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
+#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
+#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
+#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
+#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
+#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
+#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
+#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
+#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
+#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
+#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
+#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
+#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
+#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
+#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
+#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
+#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
+#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
+#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
+#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
+#define RSCAN0TMID15 RSCAN0.TMID15.UINT32
+#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
+#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
+#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
+#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
+#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
+#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
+#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
+#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
+#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
+#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
+#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
+#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
+#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
+#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
+#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
+#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
+#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
+#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
+#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
+#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
+#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
+#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
+#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
+#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
+#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
+#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
+#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
+#define RSCAN0TMID16 RSCAN0.TMID16.UINT32
+#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
+#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
+#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
+#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
+#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
+#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
+#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
+#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
+#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
+#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
+#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
+#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
+#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
+#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
+#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
+#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
+#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
+#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
+#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
+#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
+#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
+#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
+#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
+#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
+#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
+#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
+#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
+#define RSCAN0TMID17 RSCAN0.TMID17.UINT32
+#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
+#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
+#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
+#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
+#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
+#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
+#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
+#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
+#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
+#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
+#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
+#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
+#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
+#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
+#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
+#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
+#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
+#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
+#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
+#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
+#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
+#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
+#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
+#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
+#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
+#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
+#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
+#define RSCAN0TMID18 RSCAN0.TMID18.UINT32
+#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
+#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
+#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
+#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
+#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
+#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
+#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
+#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
+#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
+#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
+#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
+#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
+#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
+#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
+#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
+#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
+#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
+#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
+#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
+#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
+#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
+#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
+#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
+#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
+#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
+#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
+#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
+#define RSCAN0TMID19 RSCAN0.TMID19.UINT32
+#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
+#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
+#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
+#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
+#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
+#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
+#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
+#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
+#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
+#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
+#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
+#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
+#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
+#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
+#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
+#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
+#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
+#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
+#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
+#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
+#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
+#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
+#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
+#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
+#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
+#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
+#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
+#define RSCAN0TMID20 RSCAN0.TMID20.UINT32
+#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
+#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
+#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
+#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
+#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
+#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
+#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
+#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
+#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
+#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
+#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
+#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
+#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
+#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
+#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
+#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
+#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
+#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
+#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
+#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
+#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
+#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
+#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
+#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
+#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
+#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
+#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
+#define RSCAN0TMID21 RSCAN0.TMID21.UINT32
+#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
+#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
+#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
+#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
+#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
+#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
+#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
+#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
+#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
+#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
+#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
+#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
+#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
+#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
+#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
+#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
+#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
+#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
+#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
+#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
+#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
+#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
+#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
+#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
+#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
+#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
+#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
+#define RSCAN0TMID22 RSCAN0.TMID22.UINT32
+#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
+#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
+#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
+#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
+#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
+#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
+#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
+#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
+#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
+#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
+#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
+#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
+#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
+#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
+#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
+#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
+#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
+#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
+#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
+#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
+#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
+#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
+#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
+#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
+#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
+#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
+#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
+#define RSCAN0TMID23 RSCAN0.TMID23.UINT32
+#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
+#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
+#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
+#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
+#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
+#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
+#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
+#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
+#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
+#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
+#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
+#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
+#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
+#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
+#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
+#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
+#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
+#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
+#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
+#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
+#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
+#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
+#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
+#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
+#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
+#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
+#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
+#define RSCAN0TMID24 RSCAN0.TMID24.UINT32
+#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
+#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
+#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
+#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
+#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
+#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
+#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
+#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
+#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
+#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
+#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
+#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
+#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
+#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
+#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
+#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
+#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
+#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
+#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
+#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
+#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
+#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
+#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
+#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
+#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
+#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
+#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
+#define RSCAN0TMID25 RSCAN0.TMID25.UINT32
+#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
+#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
+#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
+#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
+#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
+#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
+#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
+#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
+#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
+#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
+#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
+#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
+#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
+#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
+#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
+#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
+#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
+#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
+#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
+#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
+#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
+#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
+#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
+#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
+#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
+#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
+#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
+#define RSCAN0TMID26 RSCAN0.TMID26.UINT32
+#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
+#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
+#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
+#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
+#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
+#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
+#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
+#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
+#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
+#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
+#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
+#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
+#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
+#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
+#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
+#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
+#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
+#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
+#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
+#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
+#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
+#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
+#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
+#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
+#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
+#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
+#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
+#define RSCAN0TMID27 RSCAN0.TMID27.UINT32
+#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
+#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
+#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
+#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
+#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
+#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
+#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
+#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
+#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
+#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
+#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
+#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
+#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
+#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
+#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
+#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
+#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
+#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
+#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
+#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
+#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
+#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
+#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
+#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
+#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
+#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
+#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
+#define RSCAN0TMID28 RSCAN0.TMID28.UINT32
+#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
+#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
+#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
+#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
+#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
+#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
+#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
+#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
+#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
+#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
+#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
+#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
+#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
+#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
+#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
+#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
+#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
+#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
+#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
+#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
+#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
+#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
+#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
+#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
+#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
+#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
+#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
+#define RSCAN0TMID29 RSCAN0.TMID29.UINT32
+#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
+#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
+#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
+#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
+#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
+#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
+#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
+#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
+#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
+#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
+#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
+#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
+#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
+#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
+#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
+#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
+#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
+#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
+#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
+#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
+#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
+#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
+#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
+#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
+#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
+#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
+#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
+#define RSCAN0TMID30 RSCAN0.TMID30.UINT32
+#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
+#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
+#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
+#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
+#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
+#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
+#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
+#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
+#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
+#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
+#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
+#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
+#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
+#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
+#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
+#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
+#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
+#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
+#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
+#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
+#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
+#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
+#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
+#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
+#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
+#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
+#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
+#define RSCAN0TMID31 RSCAN0.TMID31.UINT32
+#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
+#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
+#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
+#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
+#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
+#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
+#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
+#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
+#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
+#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
+#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
+#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
+#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
+#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
+#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
+#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
+#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
+#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
+#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
+#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
+#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
+#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
+#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
+#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
+#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
+#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
+#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
+#define RSCAN0TMID32 RSCAN0.TMID32.UINT32
+#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
+#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
+#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
+#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
+#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
+#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
+#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
+#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
+#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
+#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
+#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
+#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
+#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
+#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
+#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
+#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
+#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
+#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
+#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
+#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
+#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
+#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
+#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
+#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
+#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
+#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
+#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
+#define RSCAN0TMID33 RSCAN0.TMID33.UINT32
+#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
+#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
+#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
+#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
+#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
+#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
+#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
+#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
+#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
+#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
+#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
+#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
+#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
+#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
+#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
+#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
+#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
+#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
+#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
+#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
+#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
+#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
+#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
+#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
+#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
+#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
+#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
+#define RSCAN0TMID34 RSCAN0.TMID34.UINT32
+#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
+#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
+#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
+#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
+#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
+#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
+#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
+#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
+#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
+#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
+#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
+#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
+#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
+#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
+#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
+#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
+#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
+#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
+#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
+#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
+#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
+#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
+#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
+#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
+#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
+#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
+#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
+#define RSCAN0TMID35 RSCAN0.TMID35.UINT32
+#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
+#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
+#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
+#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
+#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
+#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
+#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
+#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
+#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
+#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
+#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
+#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
+#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
+#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
+#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
+#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
+#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
+#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
+#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
+#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
+#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
+#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
+#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
+#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
+#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
+#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
+#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
+#define RSCAN0TMID36 RSCAN0.TMID36.UINT32
+#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
+#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
+#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
+#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
+#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
+#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
+#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
+#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
+#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
+#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
+#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
+#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
+#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
+#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
+#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
+#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
+#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
+#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
+#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
+#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
+#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
+#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
+#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
+#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
+#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
+#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
+#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
+#define RSCAN0TMID37 RSCAN0.TMID37.UINT32
+#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
+#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
+#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
+#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
+#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
+#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
+#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
+#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
+#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
+#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
+#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
+#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
+#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
+#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
+#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
+#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
+#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
+#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
+#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
+#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
+#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
+#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
+#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
+#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
+#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
+#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
+#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
+#define RSCAN0TMID38 RSCAN0.TMID38.UINT32
+#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
+#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
+#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
+#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
+#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
+#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
+#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
+#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
+#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
+#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
+#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
+#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
+#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
+#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
+#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
+#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
+#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
+#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
+#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
+#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
+#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
+#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
+#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
+#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
+#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
+#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
+#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
+#define RSCAN0TMID39 RSCAN0.TMID39.UINT32
+#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
+#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
+#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
+#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
+#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
+#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
+#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
+#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
+#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
+#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
+#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
+#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
+#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
+#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
+#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
+#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
+#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
+#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
+#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
+#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
+#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
+#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
+#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
+#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
+#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
+#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
+#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
+#define RSCAN0TMID40 RSCAN0.TMID40.UINT32
+#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
+#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
+#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
+#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
+#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
+#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
+#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
+#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
+#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
+#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
+#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
+#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
+#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
+#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
+#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
+#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
+#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
+#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
+#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
+#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
+#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
+#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
+#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
+#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
+#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
+#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
+#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
+#define RSCAN0TMID41 RSCAN0.TMID41.UINT32
+#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
+#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
+#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
+#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
+#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
+#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
+#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
+#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
+#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
+#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
+#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
+#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
+#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
+#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
+#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
+#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
+#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
+#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
+#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
+#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
+#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
+#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
+#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
+#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
+#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
+#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
+#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
+#define RSCAN0TMID42 RSCAN0.TMID42.UINT32
+#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
+#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
+#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
+#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
+#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
+#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
+#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
+#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
+#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
+#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
+#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
+#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
+#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
+#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
+#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
+#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
+#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
+#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
+#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
+#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
+#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
+#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
+#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
+#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
+#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
+#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
+#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
+#define RSCAN0TMID43 RSCAN0.TMID43.UINT32
+#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
+#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
+#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
+#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
+#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
+#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
+#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
+#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
+#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
+#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
+#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
+#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
+#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
+#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
+#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
+#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
+#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
+#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
+#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
+#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
+#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
+#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
+#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
+#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
+#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
+#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
+#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
+#define RSCAN0TMID44 RSCAN0.TMID44.UINT32
+#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
+#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
+#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
+#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
+#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
+#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
+#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
+#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
+#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
+#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
+#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
+#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
+#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
+#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
+#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
+#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
+#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
+#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
+#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
+#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
+#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
+#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
+#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
+#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
+#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
+#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
+#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
+#define RSCAN0TMID45 RSCAN0.TMID45.UINT32
+#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
+#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
+#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
+#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
+#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
+#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
+#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
+#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
+#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
+#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
+#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
+#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
+#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
+#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
+#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
+#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
+#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
+#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
+#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
+#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
+#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
+#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
+#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
+#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
+#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
+#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
+#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
+#define RSCAN0TMID46 RSCAN0.TMID46.UINT32
+#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
+#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
+#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
+#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
+#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
+#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
+#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
+#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
+#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
+#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
+#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
+#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
+#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
+#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
+#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
+#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
+#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
+#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
+#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
+#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
+#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
+#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
+#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
+#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
+#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
+#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
+#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
+#define RSCAN0TMID47 RSCAN0.TMID47.UINT32
+#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
+#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
+#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
+#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
+#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
+#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
+#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
+#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
+#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
+#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
+#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
+#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
+#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
+#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
+#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
+#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
+#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
+#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
+#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
+#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
+#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
+#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
+#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
+#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
+#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
+#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
+#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
+#define RSCAN0TMID48 RSCAN0.TMID48.UINT32
+#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
+#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
+#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
+#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
+#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
+#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
+#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
+#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
+#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
+#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
+#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
+#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
+#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
+#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
+#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
+#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
+#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
+#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
+#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
+#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
+#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
+#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
+#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
+#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
+#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
+#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
+#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
+#define RSCAN0TMID49 RSCAN0.TMID49.UINT32
+#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
+#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
+#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
+#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
+#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
+#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
+#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
+#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
+#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
+#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
+#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
+#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
+#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
+#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
+#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
+#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
+#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
+#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
+#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
+#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
+#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
+#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
+#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
+#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
+#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
+#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
+#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
+#define RSCAN0TMID50 RSCAN0.TMID50.UINT32
+#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
+#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
+#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
+#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
+#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
+#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
+#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
+#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
+#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
+#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
+#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
+#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
+#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
+#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
+#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
+#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
+#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
+#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
+#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
+#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
+#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
+#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
+#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
+#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
+#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
+#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
+#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
+#define RSCAN0TMID51 RSCAN0.TMID51.UINT32
+#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
+#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
+#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
+#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
+#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
+#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
+#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
+#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
+#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
+#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
+#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
+#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
+#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
+#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
+#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
+#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
+#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
+#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
+#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
+#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
+#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
+#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
+#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
+#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
+#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
+#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
+#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
+#define RSCAN0TMID52 RSCAN0.TMID52.UINT32
+#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
+#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
+#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
+#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
+#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
+#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
+#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
+#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
+#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
+#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
+#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
+#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
+#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
+#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
+#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
+#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
+#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
+#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
+#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
+#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
+#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
+#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
+#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
+#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
+#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
+#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
+#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
+#define RSCAN0TMID53 RSCAN0.TMID53.UINT32
+#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
+#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
+#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
+#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
+#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
+#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
+#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
+#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
+#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
+#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
+#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
+#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
+#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
+#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
+#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
+#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
+#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
+#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
+#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
+#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
+#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
+#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
+#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
+#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
+#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
+#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
+#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
+#define RSCAN0TMID54 RSCAN0.TMID54.UINT32
+#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
+#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
+#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
+#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
+#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
+#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
+#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
+#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
+#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
+#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
+#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
+#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
+#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
+#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
+#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
+#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
+#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
+#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
+#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
+#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
+#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
+#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
+#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
+#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
+#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
+#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
+#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
+#define RSCAN0TMID55 RSCAN0.TMID55.UINT32
+#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
+#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
+#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
+#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
+#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
+#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
+#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
+#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
+#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
+#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
+#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
+#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
+#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
+#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
+#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
+#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
+#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
+#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
+#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
+#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
+#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
+#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
+#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
+#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
+#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
+#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
+#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
+#define RSCAN0TMID56 RSCAN0.TMID56.UINT32
+#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
+#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
+#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
+#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
+#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
+#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
+#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
+#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
+#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
+#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
+#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
+#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
+#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
+#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
+#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
+#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
+#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
+#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
+#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
+#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
+#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
+#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
+#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
+#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
+#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
+#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
+#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
+#define RSCAN0TMID57 RSCAN0.TMID57.UINT32
+#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
+#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
+#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
+#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
+#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
+#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
+#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
+#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
+#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
+#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
+#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
+#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
+#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
+#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
+#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
+#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
+#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
+#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
+#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
+#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
+#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
+#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
+#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
+#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
+#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
+#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
+#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
+#define RSCAN0TMID58 RSCAN0.TMID58.UINT32
+#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
+#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
+#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
+#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
+#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
+#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
+#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
+#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
+#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
+#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
+#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
+#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
+#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
+#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
+#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
+#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
+#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
+#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
+#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
+#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
+#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
+#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
+#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
+#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
+#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
+#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
+#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
+#define RSCAN0TMID59 RSCAN0.TMID59.UINT32
+#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
+#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
+#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
+#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
+#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
+#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
+#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
+#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
+#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
+#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
+#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
+#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
+#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
+#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
+#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
+#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
+#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
+#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
+#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
+#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
+#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
+#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
+#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
+#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
+#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
+#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
+#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
+#define RSCAN0TMID60 RSCAN0.TMID60.UINT32
+#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
+#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
+#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
+#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
+#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
+#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
+#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
+#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
+#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
+#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
+#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
+#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
+#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
+#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
+#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
+#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
+#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
+#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
+#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
+#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
+#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
+#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
+#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
+#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
+#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
+#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
+#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
+#define RSCAN0TMID61 RSCAN0.TMID61.UINT32
+#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
+#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
+#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
+#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
+#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
+#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
+#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
+#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
+#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
+#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
+#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
+#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
+#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
+#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
+#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
+#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
+#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
+#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
+#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
+#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
+#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
+#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
+#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
+#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
+#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
+#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
+#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
+#define RSCAN0TMID62 RSCAN0.TMID62.UINT32
+#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
+#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
+#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
+#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
+#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
+#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
+#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
+#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
+#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
+#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
+#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
+#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
+#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
+#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
+#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
+#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
+#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
+#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
+#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
+#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
+#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
+#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
+#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
+#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
+#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
+#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
+#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
+#define RSCAN0TMID63 RSCAN0.TMID63.UINT32
+#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
+#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
+#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
+#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
+#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
+#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
+#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
+#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
+#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
+#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
+#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
+#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
+#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
+#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
+#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
+#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
+#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
+#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
+#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
+#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
+#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
+#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
+#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
+#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
+#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
+#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
+#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
+#define RSCAN0TMID64 RSCAN0.TMID64.UINT32
+#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
+#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
+#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
+#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
+#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
+#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
+#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
+#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
+#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
+#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
+#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
+#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
+#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
+#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
+#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
+#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
+#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
+#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
+#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
+#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
+#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
+#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
+#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
+#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
+#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
+#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
+#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
+#define RSCAN0TMID65 RSCAN0.TMID65.UINT32
+#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
+#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
+#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
+#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
+#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
+#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
+#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
+#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
+#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
+#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
+#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
+#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
+#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
+#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
+#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
+#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
+#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
+#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
+#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
+#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
+#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
+#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
+#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
+#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
+#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
+#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
+#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
+#define RSCAN0TMID66 RSCAN0.TMID66.UINT32
+#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
+#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
+#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
+#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
+#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
+#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
+#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
+#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
+#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
+#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
+#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
+#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
+#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
+#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
+#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
+#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
+#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
+#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
+#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
+#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
+#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
+#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
+#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
+#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
+#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
+#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
+#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
+#define RSCAN0TMID67 RSCAN0.TMID67.UINT32
+#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
+#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
+#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
+#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
+#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
+#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
+#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
+#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
+#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
+#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
+#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
+#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
+#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
+#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
+#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
+#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
+#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
+#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
+#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
+#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
+#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
+#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
+#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
+#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
+#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
+#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
+#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
+#define RSCAN0TMID68 RSCAN0.TMID68.UINT32
+#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
+#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
+#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
+#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
+#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
+#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
+#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
+#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
+#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
+#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
+#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
+#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
+#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
+#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
+#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
+#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
+#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
+#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
+#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
+#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
+#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
+#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
+#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
+#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
+#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
+#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
+#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
+#define RSCAN0TMID69 RSCAN0.TMID69.UINT32
+#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
+#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
+#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
+#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
+#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
+#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
+#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
+#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
+#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
+#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
+#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
+#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
+#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
+#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
+#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
+#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
+#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
+#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
+#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
+#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
+#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
+#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
+#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
+#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
+#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
+#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
+#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
+#define RSCAN0TMID70 RSCAN0.TMID70.UINT32
+#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
+#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
+#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
+#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
+#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
+#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
+#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
+#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
+#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
+#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
+#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
+#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
+#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
+#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
+#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
+#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
+#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
+#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
+#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
+#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
+#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
+#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
+#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
+#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
+#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
+#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
+#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
+#define RSCAN0TMID71 RSCAN0.TMID71.UINT32
+#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
+#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
+#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
+#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
+#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
+#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
+#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
+#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
+#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
+#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
+#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
+#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
+#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
+#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
+#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
+#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
+#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
+#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
+#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
+#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
+#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
+#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
+#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
+#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
+#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
+#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
+#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
+#define RSCAN0TMID72 RSCAN0.TMID72.UINT32
+#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
+#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
+#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
+#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
+#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
+#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
+#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
+#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
+#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
+#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
+#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
+#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
+#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
+#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
+#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
+#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
+#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
+#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
+#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
+#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
+#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
+#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
+#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
+#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
+#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
+#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
+#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
+#define RSCAN0TMID73 RSCAN0.TMID73.UINT32
+#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
+#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
+#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
+#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
+#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
+#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
+#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
+#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
+#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
+#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
+#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
+#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
+#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
+#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
+#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
+#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
+#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
+#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
+#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
+#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
+#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
+#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
+#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
+#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
+#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
+#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
+#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
+#define RSCAN0TMID74 RSCAN0.TMID74.UINT32
+#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
+#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
+#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
+#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
+#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
+#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
+#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
+#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
+#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
+#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
+#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
+#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
+#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
+#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
+#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
+#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
+#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
+#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
+#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
+#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
+#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
+#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
+#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
+#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
+#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
+#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
+#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
+#define RSCAN0TMID75 RSCAN0.TMID75.UINT32
+#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
+#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
+#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
+#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
+#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
+#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
+#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
+#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
+#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
+#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
+#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
+#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
+#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
+#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
+#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
+#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
+#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
+#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
+#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
+#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
+#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
+#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
+#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
+#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
+#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
+#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
+#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
+#define RSCAN0TMID76 RSCAN0.TMID76.UINT32
+#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
+#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
+#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
+#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
+#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
+#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
+#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
+#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
+#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
+#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
+#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
+#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
+#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
+#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
+#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
+#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
+#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
+#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
+#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
+#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
+#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
+#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
+#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
+#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
+#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
+#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
+#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
+#define RSCAN0TMID77 RSCAN0.TMID77.UINT32
+#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
+#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
+#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
+#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
+#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
+#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
+#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
+#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
+#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
+#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
+#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
+#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
+#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
+#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
+#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
+#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
+#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
+#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
+#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
+#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
+#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
+#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
+#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
+#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
+#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
+#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
+#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
+#define RSCAN0TMID78 RSCAN0.TMID78.UINT32
+#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
+#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
+#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
+#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
+#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
+#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
+#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
+#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
+#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
+#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
+#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
+#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
+#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
+#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
+#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
+#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
+#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
+#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
+#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
+#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
+#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
+#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
+#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
+#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
+#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
+#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
+#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
+#define RSCAN0TMID79 RSCAN0.TMID79.UINT32
+#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
+#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
+#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
+#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
+#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
+#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
+#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
+#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
+#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
+#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
+#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
+#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
+#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
+#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
+#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
+#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
+#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
+#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
+#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
+#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
+#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
+#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
+#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
+#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
+#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
+#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
+#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
+#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
+#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
+#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
+#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
+#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
+#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
+#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
+#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
+#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
+#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
+#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
+#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
+#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
+#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
+#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
+#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
+#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
+#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
+#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
+#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
+#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
+#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
+#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
+#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
+#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
+#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
+#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
+#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
+#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
+#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
+#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
+#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
+#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
+#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
+#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h
new file mode 100644
index 000000000..0fbd14e70
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h
@@ -0,0 +1,204 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rspi_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSPI_IODEFINE_H
+#define RSPI_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+#include "reg32_t.h"
+
+struct st_rspi
+{ /* RSPI */
+ volatile uint8_t SPCR; /* SPCR */
+ volatile uint8_t SSLP; /* SSLP */
+ volatile uint8_t SPPCR; /* SPPCR */
+ volatile uint8_t SPSR; /* SPSR */
+ union reg32_t SPDR; /* SPDR */
+
+ volatile uint8_t SPSCR; /* SPSCR */
+ volatile uint8_t SPSSR; /* SPSSR */
+ volatile uint8_t SPBR; /* SPBR */
+ volatile uint8_t SPDCR; /* SPDCR */
+ volatile uint8_t SPCKD; /* SPCKD */
+ volatile uint8_t SSLND; /* SSLND */
+ volatile uint8_t SPND; /* SPND */
+ volatile uint8_t dummy1[1]; /* */
+#define SPCMD_COUNT 4
+ volatile uint16_t SPCMD0; /* SPCMD0 */
+ volatile uint16_t SPCMD1; /* SPCMD1 */
+ volatile uint16_t SPCMD2; /* SPCMD2 */
+ volatile uint16_t SPCMD3; /* SPCMD3 */
+ volatile uint8_t dummy2[8]; /* */
+ volatile uint8_t SPBFCR; /* SPBFCR */
+ volatile uint8_t dummy3[1]; /* */
+ volatile uint16_t SPBFDR; /* SPBFDR */
+};
+
+
+#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
+#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
+#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
+#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
+#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channnel array defines of RSPI */
+
+/* Channnel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT 5
+#define RSPI_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RSPI */
+
+
+#define SPCR_0 RSPI0.SPCR
+#define SSLP_0 RSPI0.SSLP
+#define SPPCR_0 RSPI0.SPPCR
+#define SPSR_0 RSPI0.SPSR
+#define SPDR_0 RSPI0.SPDR.UINT32
+#define SPDR_0L RSPI0.SPDR.UINT16[L]
+#define SPDR_0H RSPI0.SPDR.UINT16[H]
+#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
+#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
+#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
+#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
+#define SPSCR_0 RSPI0.SPSCR
+#define SPSSR_0 RSPI0.SPSSR
+#define SPBR_0 RSPI0.SPBR
+#define SPDCR_0 RSPI0.SPDCR
+#define SPCKD_0 RSPI0.SPCKD
+#define SSLND_0 RSPI0.SSLND
+#define SPND_0 RSPI0.SPND
+#define SPCMD0_0 RSPI0.SPCMD0
+#define SPCMD1_0 RSPI0.SPCMD1
+#define SPCMD2_0 RSPI0.SPCMD2
+#define SPCMD3_0 RSPI0.SPCMD3
+#define SPBFCR_0 RSPI0.SPBFCR
+#define SPBFDR_0 RSPI0.SPBFDR
+#define SPCR_1 RSPI1.SPCR
+#define SSLP_1 RSPI1.SSLP
+#define SPPCR_1 RSPI1.SPPCR
+#define SPSR_1 RSPI1.SPSR
+#define SPDR_1 RSPI1.SPDR.UINT32
+#define SPDR_1L RSPI1.SPDR.UINT16[L]
+#define SPDR_1H RSPI1.SPDR.UINT16[H]
+#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
+#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
+#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
+#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
+#define SPSCR_1 RSPI1.SPSCR
+#define SPSSR_1 RSPI1.SPSSR
+#define SPBR_1 RSPI1.SPBR
+#define SPDCR_1 RSPI1.SPDCR
+#define SPCKD_1 RSPI1.SPCKD
+#define SSLND_1 RSPI1.SSLND
+#define SPND_1 RSPI1.SPND
+#define SPCMD0_1 RSPI1.SPCMD0
+#define SPCMD1_1 RSPI1.SPCMD1
+#define SPCMD2_1 RSPI1.SPCMD2
+#define SPCMD3_1 RSPI1.SPCMD3
+#define SPBFCR_1 RSPI1.SPBFCR
+#define SPBFDR_1 RSPI1.SPBFDR
+#define SPCR_2 RSPI2.SPCR
+#define SSLP_2 RSPI2.SSLP
+#define SPPCR_2 RSPI2.SPPCR
+#define SPSR_2 RSPI2.SPSR
+#define SPDR_2 RSPI2.SPDR.UINT32
+#define SPDR_2L RSPI2.SPDR.UINT16[L]
+#define SPDR_2H RSPI2.SPDR.UINT16[H]
+#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
+#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
+#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
+#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
+#define SPSCR_2 RSPI2.SPSCR
+#define SPSSR_2 RSPI2.SPSSR
+#define SPBR_2 RSPI2.SPBR
+#define SPDCR_2 RSPI2.SPDCR
+#define SPCKD_2 RSPI2.SPCKD
+#define SSLND_2 RSPI2.SSLND
+#define SPND_2 RSPI2.SPND
+#define SPCMD0_2 RSPI2.SPCMD0
+#define SPCMD1_2 RSPI2.SPCMD1
+#define SPCMD2_2 RSPI2.SPCMD2
+#define SPCMD3_2 RSPI2.SPCMD3
+#define SPBFCR_2 RSPI2.SPBFCR
+#define SPBFDR_2 RSPI2.SPBFDR
+#define SPCR_3 RSPI3.SPCR
+#define SSLP_3 RSPI3.SSLP
+#define SPPCR_3 RSPI3.SPPCR
+#define SPSR_3 RSPI3.SPSR
+#define SPDR_3 RSPI3.SPDR.UINT32
+#define SPDR_3L RSPI3.SPDR.UINT16[L]
+#define SPDR_3H RSPI3.SPDR.UINT16[H]
+#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
+#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
+#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
+#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
+#define SPSCR_3 RSPI3.SPSCR
+#define SPSSR_3 RSPI3.SPSSR
+#define SPBR_3 RSPI3.SPBR
+#define SPDCR_3 RSPI3.SPDCR
+#define SPCKD_3 RSPI3.SPCKD
+#define SSLND_3 RSPI3.SSLND
+#define SPND_3 RSPI3.SPND
+#define SPCMD0_3 RSPI3.SPCMD0
+#define SPCMD1_3 RSPI3.SPCMD1
+#define SPCMD2_3 RSPI3.SPCMD2
+#define SPCMD3_3 RSPI3.SPCMD3
+#define SPBFCR_3 RSPI3.SPBFCR
+#define SPBFDR_3 RSPI3.SPBFDR
+#define SPCR_4 RSPI4.SPCR
+#define SSLP_4 RSPI4.SSLP
+#define SPPCR_4 RSPI4.SPPCR
+#define SPSR_4 RSPI4.SPSR
+#define SPDR_4 RSPI4.SPDR.UINT32
+#define SPDR_4L RSPI4.SPDR.UINT16[L]
+#define SPDR_4H RSPI4.SPDR.UINT16[H]
+#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
+#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
+#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
+#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
+#define SPSCR_4 RSPI4.SPSCR
+#define SPSSR_4 RSPI4.SPSSR
+#define SPBR_4 RSPI4.SPBR
+#define SPDCR_4 RSPI4.SPDCR
+#define SPCKD_4 RSPI4.SPCKD
+#define SSLND_4 RSPI4.SSLND
+#define SPND_4 RSPI4.SPND
+#define SPCMD0_4 RSPI4.SPCMD0
+#define SPCMD1_4 RSPI4.SPCMD1
+#define SPCMD2_4 RSPI4.SPCMD2
+#define SPCMD3_4 RSPI4.SPCMD3
+#define SPBFCR_4 RSPI4.SPBFCR
+#define SPBFDR_4 RSPI4.SPBFDR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h
new file mode 100644
index 000000000..6cfb46dde
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h
@@ -0,0 +1,102 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rtc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RTC_IODEFINE_H
+#define RTC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rtc
+{ /* RTC */
+ volatile uint8_t R64CNT; /* R64CNT */
+ volatile uint8_t dummy537[1]; /* */
+ volatile uint8_t RSECCNT; /* RSECCNT */
+ volatile uint8_t dummy538[1]; /* */
+ volatile uint8_t RMINCNT; /* RMINCNT */
+ volatile uint8_t dummy539[1]; /* */
+ volatile uint8_t RHRCNT; /* RHRCNT */
+ volatile uint8_t dummy540[1]; /* */
+ volatile uint8_t RWKCNT; /* RWKCNT */
+ volatile uint8_t dummy541[1]; /* */
+ volatile uint8_t RDAYCNT; /* RDAYCNT */
+ volatile uint8_t dummy542[1]; /* */
+ volatile uint8_t RMONCNT; /* RMONCNT */
+ volatile uint8_t dummy543[1]; /* */
+ volatile uint16_t RYRCNT; /* RYRCNT */
+ volatile uint8_t RSECAR; /* RSECAR */
+ volatile uint8_t dummy544[1]; /* */
+ volatile uint8_t RMINAR; /* RMINAR */
+ volatile uint8_t dummy545[1]; /* */
+ volatile uint8_t RHRAR; /* RHRAR */
+ volatile uint8_t dummy546[1]; /* */
+ volatile uint8_t RWKAR; /* RWKAR */
+ volatile uint8_t dummy547[1]; /* */
+ volatile uint8_t RDAYAR; /* RDAYAR */
+ volatile uint8_t dummy548[1]; /* */
+ volatile uint8_t RMONAR; /* RMONAR */
+ volatile uint8_t dummy549[1]; /* */
+ volatile uint8_t RCR1; /* RCR1 */
+ volatile uint8_t dummy550[1]; /* */
+ volatile uint8_t RCR2; /* RCR2 */
+ volatile uint8_t dummy551[1]; /* */
+ volatile uint16_t RYRAR; /* RYRAR */
+ volatile uint8_t dummy552[2]; /* */
+ volatile uint8_t RCR3; /* RCR3 */
+ volatile uint8_t dummy553[1]; /* */
+ volatile uint8_t RCR5; /* RCR5 */
+ volatile uint8_t dummy554[3]; /* */
+ volatile uint16_t RFRH; /* RFRH */
+ volatile uint16_t RFRL; /* RFRL */
+};
+
+
+#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT RTC.R64CNT
+#define RTCRSECCNT RTC.RSECCNT
+#define RTCRMINCNT RTC.RMINCNT
+#define RTCRHRCNT RTC.RHRCNT
+#define RTCRWKCNT RTC.RWKCNT
+#define RTCRDAYCNT RTC.RDAYCNT
+#define RTCRMONCNT RTC.RMONCNT
+#define RTCRYRCNT RTC.RYRCNT
+#define RTCRSECAR RTC.RSECAR
+#define RTCRMINAR RTC.RMINAR
+#define RTCRHRAR RTC.RHRAR
+#define RTCRWKAR RTC.RWKAR
+#define RTCRDAYAR RTC.RDAYAR
+#define RTCRMONAR RTC.RMONAR
+#define RTCRCR1 RTC.RCR1
+#define RTCRCR2 RTC.RCR2
+#define RTCRYRAR RTC.RYRAR
+#define RTCRCR3 RTC.RCR3
+#define RTCRCR5 RTC.RCR5
+#define RTCRFRH RTC.RFRH
+#define RTCRFRL RTC.RFRL
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h
new file mode 100644
index 000000000..9a710604c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h
@@ -0,0 +1,182 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIF_IODEFINE_H
+#define SCIF_IODEFINE_H
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scif
+{ /* SCIF */
+ volatile uint16_t SCSMR; /* SCSMR */
+ volatile uint8_t dummy1[2]; /* */
+ volatile uint8_t SCBRR; /* SCBRR */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint16_t SCSCR; /* SCSCR */
+ volatile uint8_t dummy3[2]; /* */
+ volatile uint8_t SCFTDR; /* SCFTDR */
+ volatile uint8_t dummy4[3]; /* */
+ volatile uint16_t SCFSR; /* SCFSR */
+ volatile uint8_t dummy5[2]; /* */
+ volatile uint8_t SCFRDR; /* SCFRDR */
+ volatile uint8_t dummy6[3]; /* */
+ volatile uint16_t SCFCR; /* SCFCR */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t SCFDR; /* SCFDR */
+ volatile uint8_t dummy8[2]; /* */
+ volatile uint16_t SCSPTR; /* SCSPTR */
+ volatile uint8_t dummy9[2]; /* */
+ volatile uint16_t SCLSR; /* SCLSR */
+ volatile uint8_t dummy10[2]; /* */
+ volatile uint16_t SCEMR; /* SCEMR */
+};
+
+
+#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
+#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
+#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
+#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
+#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
+#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
+#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
+#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
+
+#define P_SCIF0 (0xE8007000uL) /* SCIF0 */
+#define P_SCIF1 (0xE8007800uL) /* SCIF1 */
+#define P_SCIF2 (0xE8008000uL) /* SCIF2 */
+#define P_SCIF3 (0xE8008800uL) /* SCIF3 */
+#define P_SCIF4 (0xE8009000uL) /* SCIF4 */
+#define P_SCIF5 (0xE8009800uL) /* SCIF5 */
+#define P_SCIF6 (0xE800A000uL) /* SCIF6 */
+#define P_SCIF7 (0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channnel array defines of SCIF */
+
+/* Channnel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT 8
+#define SCIF_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIF */
+
+
+#define SCSMR_0 SCIF0.SCSMR
+#define SCBRR_0 SCIF0.SCBRR
+#define SCSCR_0 SCIF0.SCSCR
+#define SCFTDR_0 SCIF0.SCFTDR
+#define SCFSR_0 SCIF0.SCFSR
+#define SCFRDR_0 SCIF0.SCFRDR
+#define SCFCR_0 SCIF0.SCFCR
+#define SCFDR_0 SCIF0.SCFDR
+#define SCSPTR_0 SCIF0.SCSPTR
+#define SCLSR_0 SCIF0.SCLSR
+#define SCEMR_0 SCIF0.SCEMR
+#define SCSMR_1 SCIF1.SCSMR
+#define SCBRR_1 SCIF1.SCBRR
+#define SCSCR_1 SCIF1.SCSCR
+#define SCFTDR_1 SCIF1.SCFTDR
+#define SCFSR_1 SCIF1.SCFSR
+#define SCFRDR_1 SCIF1.SCFRDR
+#define SCFCR_1 SCIF1.SCFCR
+#define SCFDR_1 SCIF1.SCFDR
+#define SCSPTR_1 SCIF1.SCSPTR
+#define SCLSR_1 SCIF1.SCLSR
+#define SCEMR_1 SCIF1.SCEMR
+#define SCSMR_2 SCIF2.SCSMR
+#define SCBRR_2 SCIF2.SCBRR
+#define SCSCR_2 SCIF2.SCSCR
+#define SCFTDR_2 SCIF2.SCFTDR
+#define SCFSR_2 SCIF2.SCFSR
+#define SCFRDR_2 SCIF2.SCFRDR
+#define SCFCR_2 SCIF2.SCFCR
+#define SCFDR_2 SCIF2.SCFDR
+#define SCSPTR_2 SCIF2.SCSPTR
+#define SCLSR_2 SCIF2.SCLSR
+#define SCEMR_2 SCIF2.SCEMR
+#define SCSMR_3 SCIF3.SCSMR
+#define SCBRR_3 SCIF3.SCBRR
+#define SCSCR_3 SCIF3.SCSCR
+#define SCFTDR_3 SCIF3.SCFTDR
+#define SCFSR_3 SCIF3.SCFSR
+#define SCFRDR_3 SCIF3.SCFRDR
+#define SCFCR_3 SCIF3.SCFCR
+#define SCFDR_3 SCIF3.SCFDR
+#define SCSPTR_3 SCIF3.SCSPTR
+#define SCLSR_3 SCIF3.SCLSR
+#define SCEMR_3 SCIF3.SCEMR
+#define SCSMR_4 SCIF4.SCSMR
+#define SCBRR_4 SCIF4.SCBRR
+#define SCSCR_4 SCIF4.SCSCR
+#define SCFTDR_4 SCIF4.SCFTDR
+#define SCFSR_4 SCIF4.SCFSR
+#define SCFRDR_4 SCIF4.SCFRDR
+#define SCFCR_4 SCIF4.SCFCR
+#define SCFDR_4 SCIF4.SCFDR
+#define SCSPTR_4 SCIF4.SCSPTR
+#define SCLSR_4 SCIF4.SCLSR
+#define SCEMR_4 SCIF4.SCEMR
+#define SCSMR_5 SCIF5.SCSMR
+#define SCBRR_5 SCIF5.SCBRR
+#define SCSCR_5 SCIF5.SCSCR
+#define SCFTDR_5 SCIF5.SCFTDR
+#define SCFSR_5 SCIF5.SCFSR
+#define SCFRDR_5 SCIF5.SCFRDR
+#define SCFCR_5 SCIF5.SCFCR
+#define SCFDR_5 SCIF5.SCFDR
+#define SCSPTR_5 SCIF5.SCSPTR
+#define SCLSR_5 SCIF5.SCLSR
+#define SCEMR_5 SCIF5.SCEMR
+#define SCSMR_6 SCIF6.SCSMR
+#define SCBRR_6 SCIF6.SCBRR
+#define SCSCR_6 SCIF6.SCSCR
+#define SCFTDR_6 SCIF6.SCFTDR
+#define SCFSR_6 SCIF6.SCFSR
+#define SCFRDR_6 SCIF6.SCFRDR
+#define SCFCR_6 SCIF6.SCFCR
+#define SCFDR_6 SCIF6.SCFDR
+#define SCSPTR_6 SCIF6.SCSPTR
+#define SCLSR_6 SCIF6.SCLSR
+#define SCEMR_6 SCIF6.SCEMR
+#define SCSMR_7 SCIF7.SCSMR
+#define SCBRR_7 SCIF7.SCBRR
+#define SCSCR_7 SCIF7.SCSCR
+#define SCFTDR_7 SCIF7.SCFTDR
+#define SCFSR_7 SCIF7.SCFSR
+#define SCFRDR_7 SCIF7.SCFRDR
+#define SCFCR_7 SCIF7.SCFCR
+#define SCFDR_7 SCIF7.SCFDR
+#define SCSPTR_7 SCIF7.SCSPTR
+#define SCLSR_7 SCIF7.SCLSR
+#define SCEMR_7 SCIF7.SCEMR
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h
new file mode 100644
index 000000000..2ddf1e61d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scim_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIM_IODEFINE_H
+#define SCIM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scim
+{ /* SCIM */
+ volatile uint8_t SMR; /* SMR */
+ volatile uint8_t BRR; /* BRR */
+ volatile uint8_t SCR; /* SCR */
+ volatile uint8_t TDR; /* TDR */
+ volatile uint8_t SSR; /* SSR */
+ volatile uint8_t RDR; /* RDR */
+ volatile uint8_t SCMR; /* SCMR */
+ volatile uint8_t SEMR; /* SEMR */
+ volatile uint8_t SNFR; /* SNFR */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint8_t SECR; /* SECR */
+};
+
+
+#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
+#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channnel array defines of SCIM */
+
+/* Channnel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT 2
+#define SCIM_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCIM0, &SCIM1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIM */
+
+
+#define SMR0 SCIM0.SMR
+#define BRR0 SCIM0.BRR
+#define SCR0 SCIM0.SCR
+#define TDR0 SCIM0.TDR
+#define SSR0 SCIM0.SSR
+#define RDR0 SCIM0.RDR
+#define SCMR0 SCIM0.SCMR
+#define SEMR0 SCIM0.SEMR
+#define SNFR0 SCIM0.SNFR
+#define SECR0 SCIM0.SECR
+#define SMR1 SCIM1.SMR
+#define BRR1 SCIM1.BRR
+#define SCR1 SCIM1.SCR
+#define TDR1 SCIM1.TDR
+#define SSR1 SCIM1.SSR
+#define RDR1 SCIM1.RDR
+#define SCMR1 SCIM1.SCMR
+#define SEMR1 SCIM1.SEMR
+#define SNFR1 SCIM1.SNFR
+#define SECR1 SCIM1.SECR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h
new file mode 100644
index 000000000..a6d5646dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h
@@ -0,0 +1,808 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scux_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCUX_IODEFINE_H
+#define SCUX_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scux
+{ /* SCUX */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
+ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
+ volatile uint8_t dummy259[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
+ volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
+ volatile uint8_t dummy260[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
+ volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
+ volatile uint8_t dummy261[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
+ volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
+ volatile uint8_t dummy262[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
+ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
+ volatile uint8_t dummy263[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
+ volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
+ volatile uint8_t dummy264[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
+ volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
+ volatile uint8_t dummy265[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
+ volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
+ volatile uint8_t dummy266[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
+ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
+ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
+ volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
+ volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
+ volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
+ volatile uint8_t dummy267[4]; /* */
+ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy268[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
+ volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
+ volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
+ volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
+ volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
+ volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
+ volatile uint8_t dummy269[4]; /* */
+ volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy270[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
+ volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
+ volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
+ volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
+ volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
+ volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
+ volatile uint8_t dummy271[4]; /* */
+ volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy272[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
+ volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
+ volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
+ volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
+ volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
+ volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
+ volatile uint8_t dummy273[4]; /* */
+ volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy274[224]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
+ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
+ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
+ volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
+ volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
+ volatile uint8_t dummy275[4]; /* */
+ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy276[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
+ volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
+ volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
+ volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
+ volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
+ volatile uint8_t dummy277[4]; /* */
+ volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy278[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
+ volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
+ volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
+ volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
+ volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
+ volatile uint8_t dummy279[4]; /* */
+ volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy280[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
+ volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
+ volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
+ volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
+ volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
+ volatile uint8_t dummy281[4]; /* */
+ volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy282[228]; /* */
+/* start of struct st_scux_from_srcir0_2src0_n */
+ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
+ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
+ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
+ volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
+ volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
+ volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
+ volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
+ volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
+ volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
+ volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
+ volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
+ volatile uint8_t dummy283[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
+ volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
+ volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
+ volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
+ volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
+ volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
+ volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
+ volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
+ volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
+ volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
+ volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
+ volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
+ volatile uint8_t dummy284[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
+ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
+/* end of struct st_scux_from_srcir0_2src0_n */
+ volatile uint8_t dummy285[148]; /* */
+/* start of struct st_scux_from_srcir0_2src0_n */
+ volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
+ volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
+ volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
+ volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
+ volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
+ volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
+ volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
+ volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
+ volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
+ volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
+ volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
+ volatile uint8_t dummy286[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
+ volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
+ volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
+ volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
+ volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
+ volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
+ volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
+ volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
+ volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
+ volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
+ volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
+ volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
+ volatile uint8_t dummy287[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
+ volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
+/* end of struct st_scux_from_srcir0_2src0_n */
+ volatile uint8_t dummy288[148]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
+ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
+ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
+ volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
+ volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
+ volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
+ volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
+ volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
+ volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
+ volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
+ volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
+ volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
+ volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
+ volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
+ volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
+ volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
+ volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
+ volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
+ volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
+ volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
+ volatile uint8_t dummy289[4]; /* */
+ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy290[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
+ volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
+ volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
+ volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
+ volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
+ volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
+ volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
+ volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
+ volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
+ volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
+ volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
+ volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
+ volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
+ volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
+ volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
+ volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
+ volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
+ volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
+ volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
+ volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
+ volatile uint8_t dummy291[4]; /* */
+ volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy292[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
+ volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
+ volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
+ volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
+ volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
+ volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
+ volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
+ volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
+ volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
+ volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
+ volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
+ volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
+ volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
+ volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
+ volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
+ volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
+ volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
+ volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
+ volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
+ volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
+ volatile uint8_t dummy293[4]; /* */
+ volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy294[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
+ volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
+ volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
+ volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
+ volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
+ volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
+ volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
+ volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
+ volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
+ volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
+ volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
+ volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
+ volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
+ volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
+ volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
+ volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
+ volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
+ volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
+ volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
+ volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
+ volatile uint8_t dummy295[4]; /* */
+ volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy296[168]; /* */
+ volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
+ volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
+ volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
+ volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
+ volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
+ volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
+ volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
+ volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
+ volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
+ volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
+ volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
+ volatile uint8_t dummy297[212]; /* */
+ volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
+ volatile uint32_t DMACR_CIM; /* DMACR_CIM */
+#define SCUX_DMATDn_CIM_COUNT 4
+ union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
+ union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
+ union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
+ union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
+#define SCUX_DMATUn_CIM_COUNT 4
+ union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
+ union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
+ union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
+ union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
+
+ volatile uint8_t dummy298[16]; /* */
+ volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
+#define SCUX_FDTSELn_CIM_COUNT 4
+ volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
+ volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
+ volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
+ volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
+#define SCUX_FUTSELn_CIM_COUNT 4
+ volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
+ volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
+ volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
+ volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
+ volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
+ volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
+#define SCUX_SRCRSELn_CIM_COUNT 4
+ volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
+ volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
+ volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
+ volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
+ volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
+};
+
+
+struct st_scux_from_ipcir_ipc0_n
+{
+ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
+ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
+ volatile uint8_t dummy1[248]; /* */
+};
+
+
+struct st_scux_from_opcir_opc0_n
+{
+ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
+ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
+ volatile uint8_t dummy1[248]; /* */
+};
+
+
+struct st_scux_from_ffdir_ffd0_n
+{
+ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
+ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
+ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
+ volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
+ volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
+ volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
+};
+
+
+struct st_scux_from_ffuir_ffu0_n
+{
+ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
+ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
+ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
+ volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
+ volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
+};
+
+
+struct st_scux_from_srcir0_2src0_n
+{
+ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
+ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
+ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
+ volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
+ volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
+ volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
+ volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
+ volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
+ volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
+ volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
+ volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
+ volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
+ volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
+ volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
+ volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
+ volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
+ volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
+ volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
+ volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
+ volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
+ volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
+ volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
+ volatile uint8_t dummy2[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
+ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
+};
+
+
+struct st_scux_from_dvuir_dvu0_n
+{
+ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
+ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
+ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
+ volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
+ volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
+ volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
+ volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
+ volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
+ volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
+ volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
+ volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
+ volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
+ volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
+ volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
+ volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
+ volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
+ volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
+ volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
+ volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
+ volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
+};
+
+
+#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channnel array defines of SCUX */
+
+/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channnel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
+#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
+#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
+#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
+#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
+#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
+#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
+#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
+#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
+#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
+#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
+#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
+#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
+#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
+#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
+#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
+#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
+#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
+#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
+#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
+#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
+#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
+#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
+#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
+#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
+#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
+#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
+#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
+#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
+#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
+#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
+#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
+#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
+#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
+#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
+#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
+#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
+#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
+#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
+#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
+#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
+#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
+#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
+#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
+#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
+#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
+#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
+#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
+#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
+#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
+#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
+#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
+#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
+#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
+#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
+#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
+#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
+#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
+#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
+#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
+#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
+#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
+#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
+#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
+#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
+#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
+#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
+#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
+#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
+#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
+#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
+#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
+#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
+#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
+#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
+#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
+#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
+#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
+#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
+#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
+#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
+#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
+#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
+#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
+#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
+#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
+#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
+#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
+#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
+#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
+#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
+#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
+#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
+#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
+#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
+#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
+#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
+#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
+#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
+#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
+#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
+#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
+#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
+#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
+#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
+#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
+#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
+#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
+#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
+#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
+#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
+#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
+#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
+#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
+#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
+#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
+#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
+#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
+#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
+#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
+#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
+#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
+#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
+#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
+#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
+#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
+#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
+#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
+#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
+#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
+#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
+#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
+#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
+#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
+#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
+#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
+#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
+#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
+#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
+#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
+#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
+#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
+#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
+#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
+#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
+#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
+#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
+#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
+#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
+#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
+#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
+#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
+#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
+#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
+#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
+#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
+#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
+#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
+#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
+#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
+#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
+#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
+#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
+#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
+#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
+#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
+#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
+#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
+#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
+#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
+#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
+#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
+#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
+#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
+#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
+#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
+#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
+#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
+#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
+#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
+#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
+#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
+#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
+#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
+#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
+#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
+#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
+#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
+#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
+#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
+#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
+#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
+#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
+#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
+#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
+#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
+#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
+#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
+#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
+#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
+#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
+#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
+#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
+#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
+#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
+#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
+#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
+#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
+#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
+#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
+#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
+#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
+#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
+#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
+#define SCUXDMACR_CIM SCUX.DMACR_CIM
+#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
+#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
+#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
+#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
+#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
+#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
+#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
+#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
+#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
+#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
+#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
+#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
+#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
+#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
+#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
+#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
+#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
+#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
+#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
+#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
+#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
+#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
+#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
+#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
+#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
+#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
+#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
+#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
+#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
+#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
+#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
+#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
+#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
+#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
+#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
+#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
+#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
+#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
+#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
+#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h
new file mode 100644
index 000000000..78abfc08e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sdg_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SDG_IODEFINE_H
+#define SDG_IODEFINE_H
+
+struct st_sdg
+{ /* SDG */
+ volatile uint8_t SGCR1; /* SGCR1 */
+ volatile uint8_t SGCSR; /* SGCSR */
+ volatile uint8_t SGCR2; /* SGCR2 */
+ volatile uint8_t SGLR; /* SGLR */
+ volatile uint8_t SGTFR; /* SGTFR */
+ volatile uint8_t SGSFR; /* SGSFR */
+};
+
+
+#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
+#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
+#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
+#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
+
+
+/* Start of channnel array defines of SDG */
+
+/* Channnel array defines of SDG */
+/*(Sample) value = SDG[ channel ]->SGCR1; */
+#define SDG_COUNT 4
+#define SDG_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SDG0, &SDG1, &SDG2, &SDG3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SDG */
+
+
+#define SGCR1_0 SDG0.SGCR1
+#define SGCSR_0 SDG0.SGCSR
+#define SGCR2_0 SDG0.SGCR2
+#define SGLR_0 SDG0.SGLR
+#define SGTFR_0 SDG0.SGTFR
+#define SGSFR_0 SDG0.SGSFR
+#define SGCR1_1 SDG1.SGCR1
+#define SGCSR_1 SDG1.SGCSR
+#define SGCR2_1 SDG1.SGCR2
+#define SGLR_1 SDG1.SGLR
+#define SGTFR_1 SDG1.SGTFR
+#define SGSFR_1 SDG1.SGSFR
+#define SGCR1_2 SDG2.SGCR1
+#define SGCSR_2 SDG2.SGCSR
+#define SGCR2_2 SDG2.SGCR2
+#define SGLR_2 SDG2.SGLR
+#define SGTFR_2 SDG2.SGTFR
+#define SGSFR_2 SDG2.SGSFR
+#define SGCR1_3 SDG3.SGCR1
+#define SGCSR_3 SDG3.SGCSR
+#define SGCR2_3 SDG3.SGCR2
+#define SGLR_3 SDG3.SGLR
+#define SGTFR_3 SDG3.SGTFR
+#define SGSFR_3 SDG3.SGSFR
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h
new file mode 100644
index 000000000..6f69f8085
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h
@@ -0,0 +1,68 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spdif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPDIF_IODEFINE_H
+#define SPDIF_IODEFINE_H
+
+struct st_spdif
+{ /* SPDIF */
+ volatile uint32_t TLCA; /* TLCA */
+ volatile uint32_t TRCA; /* TRCA */
+ volatile uint32_t TLCS; /* TLCS */
+ volatile uint32_t TRCS; /* TRCS */
+ volatile uint32_t TUI; /* TUI */
+ volatile uint32_t RLCA; /* RLCA */
+ volatile uint32_t RRCA; /* RRCA */
+ volatile uint32_t RLCS; /* RLCS */
+ volatile uint32_t RRCS; /* RRCS */
+ volatile uint32_t RUI; /* RUI */
+ volatile uint32_t CTRL; /* CTRL */
+ volatile uint32_t STAT; /* STAT */
+ volatile uint32_t TDAD; /* TDAD */
+ volatile uint32_t RDAD; /* RDAD */
+};
+
+
+#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA SPDIF.TLCA
+#define SPDIFTRCA SPDIF.TRCA
+#define SPDIFTLCS SPDIF.TLCS
+#define SPDIFTRCS SPDIF.TRCS
+#define SPDIFTUI SPDIF.TUI
+#define SPDIFRLCA SPDIF.RLCA
+#define SPDIFRRCA SPDIF.RRCA
+#define SPDIFRLCS SPDIF.RLCS
+#define SPDIFRRCS SPDIF.RRCS
+#define SPDIFRUI SPDIF.RUI
+#define SPDIFCTRL SPDIF.CTRL
+#define SPDIFSTAT SPDIF.STAT
+#define SPDIFTDAD SPDIF.TDAD
+#define SPDIFRDAD SPDIF.RDAD
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h
new file mode 100644
index 000000000..d25b903b8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spibsc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPIBSC_IODEFINE_H
+#define SPIBSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_spibsc
+{ /* SPIBSC */
+ volatile uint32_t CMNCR; /* CMNCR */
+ volatile uint32_t SSLDR; /* SSLDR */
+ volatile uint32_t SPBCR; /* SPBCR */
+ volatile uint32_t DRCR; /* DRCR */
+ volatile uint32_t DRCMR; /* DRCMR */
+ volatile uint32_t DREAR; /* DREAR */
+ volatile uint32_t DROPR; /* DROPR */
+ volatile uint32_t DRENR; /* DRENR */
+ volatile uint32_t SMCR; /* SMCR */
+ volatile uint32_t SMCMR; /* SMCMR */
+ volatile uint32_t SMADR; /* SMADR */
+ volatile uint32_t SMOPR; /* SMOPR */
+ volatile uint32_t SMENR; /* SMENR */
+ volatile uint8_t dummy1[4]; /* */
+ union iodefine_reg32_t SMRDR0; /* SMRDR0 */
+ union iodefine_reg32_t SMRDR1; /* SMRDR1 */
+ union iodefine_reg32_t SMWDR0; /* SMWDR0 */
+ union iodefine_reg32_t SMWDR1; /* SMWDR1 */
+
+ volatile uint32_t CMNSR; /* CMNSR */
+ volatile uint8_t dummy2[12]; /* */
+ volatile uint32_t DRDMCR; /* DRDMCR */
+ volatile uint32_t DRDRENR; /* DRDRENR */
+ volatile uint32_t SMDMCR; /* SMDMCR */
+ volatile uint32_t SMDRENR; /* SMDRENR */
+};
+
+
+#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channnel array defines of SPIBSC */
+
+/* Channnel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT 2
+#define SPIBSC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SPIBSC0, &SPIBSC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SPIBSC */
+
+
+#define CMNCR_0 SPIBSC0.CMNCR
+#define SSLDR_0 SPIBSC0.SSLDR
+#define SPBCR_0 SPIBSC0.SPBCR
+#define DRCR_0 SPIBSC0.DRCR
+#define DRCMR_0 SPIBSC0.DRCMR
+#define DREAR_0 SPIBSC0.DREAR
+#define DROPR_0 SPIBSC0.DROPR
+#define DRENR_0 SPIBSC0.DRENR
+#define SMCR_0 SPIBSC0.SMCR
+#define SMCMR_0 SPIBSC0.SMCMR
+#define SMADR_0 SPIBSC0.SMADR
+#define SMOPR_0 SPIBSC0.SMOPR
+#define SMENR_0 SPIBSC0.SMENR
+#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
+#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
+#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
+#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
+#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
+#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
+#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
+#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
+#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
+#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
+#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
+#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
+#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
+#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
+#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
+#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
+#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
+#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
+#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
+#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
+#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
+#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
+#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
+#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
+#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
+#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
+#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
+#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
+#define CMNSR_0 SPIBSC0.CMNSR
+#define DRDMCR_0 SPIBSC0.DRDMCR
+#define DRDRENR_0 SPIBSC0.DRDRENR
+#define SMDMCR_0 SPIBSC0.SMDMCR
+#define SMDRENR_0 SPIBSC0.SMDRENR
+#define CMNCR_1 SPIBSC1.CMNCR
+#define SSLDR_1 SPIBSC1.SSLDR
+#define SPBCR_1 SPIBSC1.SPBCR
+#define DRCR_1 SPIBSC1.DRCR
+#define DRCMR_1 SPIBSC1.DRCMR
+#define DREAR_1 SPIBSC1.DREAR
+#define DROPR_1 SPIBSC1.DROPR
+#define DRENR_1 SPIBSC1.DRENR
+#define SMCR_1 SPIBSC1.SMCR
+#define SMCMR_1 SPIBSC1.SMCMR
+#define SMADR_1 SPIBSC1.SMADR
+#define SMOPR_1 SPIBSC1.SMOPR
+#define SMENR_1 SPIBSC1.SMENR
+#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
+#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
+#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
+#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
+#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
+#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
+#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
+#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
+#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
+#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
+#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
+#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
+#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
+#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
+#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
+#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
+#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
+#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
+#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
+#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
+#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
+#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
+#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
+#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
+#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
+#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
+#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
+#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
+#define CMNSR_1 SPIBSC1.CMNSR
+#define DRDMCR_1 SPIBSC1.DRDMCR
+#define DRDRENR_1 SPIBSC1.DRDRENR
+#define SMDMCR_1 SPIBSC1.SMDMCR
+#define SMDRENR_1 SPIBSC1.SMDRENR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h
new file mode 100644
index 000000000..045551c9f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h
@@ -0,0 +1,131 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ssif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SSIF_IODEFINE_H
+#define SSIF_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ssif
+{ /* SSIF */
+ volatile uint32_t SSICR; /* SSICR */
+ volatile uint32_t SSISR; /* SSISR */
+ volatile uint8_t dummy1[8]; /* */
+ volatile uint32_t SSIFCR; /* SSIFCR */
+ volatile uint32_t SSIFSR; /* SSIFSR */
+ volatile uint32_t SSIFTDR; /* SSIFTDR */
+ volatile uint32_t SSIFRDR; /* SSIFRDR */
+ volatile uint32_t SSITDMR; /* SSITDMR */
+ volatile uint32_t SSIFCCR; /* SSIFCCR */
+ volatile uint32_t SSIFCMR; /* SSIFCMR */
+ volatile uint32_t SSIFCSR; /* SSIFCSR */
+};
+
+
+#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
+#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
+#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
+#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
+#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
+#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channnel array defines of SSIF */
+
+/* Channnel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT 6
+#define SSIF_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SSIF */
+
+
+#define SSICR_0 SSIF0.SSICR
+#define SSISR_0 SSIF0.SSISR
+#define SSIFCR_0 SSIF0.SSIFCR
+#define SSIFSR_0 SSIF0.SSIFSR
+#define SSIFTDR_0 SSIF0.SSIFTDR
+#define SSIFRDR_0 SSIF0.SSIFRDR
+#define SSITDMR_0 SSIF0.SSITDMR
+#define SSIFCCR_0 SSIF0.SSIFCCR
+#define SSIFCMR_0 SSIF0.SSIFCMR
+#define SSIFCSR_0 SSIF0.SSIFCSR
+#define SSICR_1 SSIF1.SSICR
+#define SSISR_1 SSIF1.SSISR
+#define SSIFCR_1 SSIF1.SSIFCR
+#define SSIFSR_1 SSIF1.SSIFSR
+#define SSIFTDR_1 SSIF1.SSIFTDR
+#define SSIFRDR_1 SSIF1.SSIFRDR
+#define SSITDMR_1 SSIF1.SSITDMR
+#define SSIFCCR_1 SSIF1.SSIFCCR
+#define SSIFCMR_1 SSIF1.SSIFCMR
+#define SSIFCSR_1 SSIF1.SSIFCSR
+#define SSICR_2 SSIF2.SSICR
+#define SSISR_2 SSIF2.SSISR
+#define SSIFCR_2 SSIF2.SSIFCR
+#define SSIFSR_2 SSIF2.SSIFSR
+#define SSIFTDR_2 SSIF2.SSIFTDR
+#define SSIFRDR_2 SSIF2.SSIFRDR
+#define SSITDMR_2 SSIF2.SSITDMR
+#define SSIFCCR_2 SSIF2.SSIFCCR
+#define SSIFCMR_2 SSIF2.SSIFCMR
+#define SSIFCSR_2 SSIF2.SSIFCSR
+#define SSICR_3 SSIF3.SSICR
+#define SSISR_3 SSIF3.SSISR
+#define SSIFCR_3 SSIF3.SSIFCR
+#define SSIFSR_3 SSIF3.SSIFSR
+#define SSIFTDR_3 SSIF3.SSIFTDR
+#define SSIFRDR_3 SSIF3.SSIFRDR
+#define SSITDMR_3 SSIF3.SSITDMR
+#define SSIFCCR_3 SSIF3.SSIFCCR
+#define SSIFCMR_3 SSIF3.SSIFCMR
+#define SSIFCSR_3 SSIF3.SSIFCSR
+#define SSICR_4 SSIF4.SSICR
+#define SSISR_4 SSIF4.SSISR
+#define SSIFCR_4 SSIF4.SSIFCR
+#define SSIFSR_4 SSIF4.SSIFSR
+#define SSIFTDR_4 SSIF4.SSIFTDR
+#define SSIFRDR_4 SSIF4.SSIFRDR
+#define SSITDMR_4 SSIF4.SSITDMR
+#define SSIFCCR_4 SSIF4.SSIFCCR
+#define SSIFCMR_4 SSIF4.SSIFCMR
+#define SSIFCSR_4 SSIF4.SSIFCSR
+#define SSICR_5 SSIF5.SSICR
+#define SSISR_5 SSIF5.SSISR
+#define SSIFCR_5 SSIF5.SSIFCR
+#define SSIFSR_5 SSIF5.SSIFSR
+#define SSIFTDR_5 SSIF5.SSIFTDR
+#define SSIFRDR_5 SSIF5.SSIFRDR
+#define SSITDMR_5 SSIF5.SSITDMR
+#define SSIFCCR_5 SSIF5.SSIFCCR
+#define SSIFCMR_5 SSIF5.SSIFCMR
+#define SSIFCSR_5 SSIF5.SSIFCSR
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h
new file mode 100644
index 000000000..97e15c845
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h
@@ -0,0 +1,546 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb20_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef USB20_IODEFINE_H
+#define USB20_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_usb20
+{ /* USB20 */
+ volatile uint16_t SYSCFG0; /* SYSCFG0 */
+ volatile uint16_t BUSWAIT; /* BUSWAIT */
+ volatile uint16_t SYSSTS0; /* SYSSTS0 */
+ volatile uint8_t dummy1[2]; /* */
+ volatile uint16_t DVSTCTR0; /* DVSTCTR0 */
+ volatile uint8_t dummy2[2]; /* */
+ volatile uint16_t TESTMODE; /* TESTMODE */
+ volatile uint8_t dummy3[2]; /* */
+#define USB20_D0FBCFG_COUNT 2
+ volatile uint16_t D0FBCFG; /* D0FBCFG */
+ volatile uint16_t D1FBCFG; /* D1FBCFG */
+ union iodefine_reg32_t CFIFO; /* CFIFO */
+#define USB20_D0FIFO_COUNT 2
+ union iodefine_reg32_t D0FIFO; /* D0FIFO */
+ union iodefine_reg32_t D1FIFO; /* D1FIFO */
+
+ volatile uint16_t CFIFOSEL; /* CFIFOSEL */
+ volatile uint16_t CFIFOCTR; /* CFIFOCTR */
+ volatile uint8_t dummy4[4]; /* */
+/* start of struct st_usb20_from_d0fifosel */
+ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
+ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
+/* end of struct st_usb20_from_d0fifosel */
+/* start of struct st_usb20_from_d0fifosel */
+ volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */
+ volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */
+/* end of struct st_usb20_from_d0fifosel */
+#define USB20_INTENB0_COUNT 2
+ volatile uint16_t INTENB0; /* INTENB0 */
+ volatile uint16_t INTENB1; /* INTENB1 */
+ volatile uint8_t dummy5[2]; /* */
+ volatile uint16_t BRDYENB; /* BRDYENB */
+ volatile uint16_t NRDYENB; /* NRDYENB */
+ volatile uint16_t BEMPENB; /* BEMPENB */
+ volatile uint16_t SOFCFG; /* SOFCFG */
+ volatile uint8_t dummy6[2]; /* */
+#define USB20_INTSTS0_COUNT 2
+ volatile uint16_t INTSTS0; /* INTSTS0 */
+ volatile uint16_t INTSTS1; /* INTSTS1 */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t BRDYSTS; /* BRDYSTS */
+ volatile uint16_t NRDYSTS; /* NRDYSTS */
+ volatile uint16_t BEMPSTS; /* BEMPSTS */
+ volatile uint16_t FRMNUM; /* FRMNUM */
+ volatile uint16_t UFRMNUM; /* UFRMNUM */
+ volatile uint16_t USBADDR; /* USBADDR */
+ volatile uint8_t dummy8[2]; /* */
+ volatile uint16_t USBREQ; /* USBREQ */
+ volatile uint16_t USBVAL; /* USBVAL */
+ volatile uint16_t USBINDX; /* USBINDX */
+ volatile uint16_t USBLENG; /* USBLENG */
+ volatile uint16_t DCPCFG; /* DCPCFG */
+ volatile uint16_t DCPMAXP; /* DCPMAXP */
+ volatile uint16_t DCPCTR; /* DCPCTR */
+ volatile uint8_t dummy9[2]; /* */
+ volatile uint16_t PIPESEL; /* PIPESEL */
+ volatile uint8_t dummy10[2]; /* */
+ volatile uint16_t PIPECFG; /* PIPECFG */
+ volatile uint16_t PIPEBUF; /* PIPEBUF */
+ volatile uint16_t PIPEMAXP; /* PIPEMAXP */
+ volatile uint16_t PIPEPERI; /* PIPEPERI */
+#define USB20_PIPE1CTR_COUNT 0xF
+ volatile uint16_t PIPE1CTR; /* PIPE1CTR */
+ volatile uint16_t PIPE2CTR; /* PIPE2CTR */
+ volatile uint16_t PIPE3CTR; /* PIPE3CTR */
+ volatile uint16_t PIPE4CTR; /* PIPE4CTR */
+ volatile uint16_t PIPE5CTR; /* PIPE5CTR */
+ volatile uint16_t PIPE6CTR; /* PIPE6CTR */
+ volatile uint16_t PIPE7CTR; /* PIPE7CTR */
+ volatile uint16_t PIPE8CTR; /* PIPE8CTR */
+ volatile uint16_t PIPE9CTR; /* PIPE9CTR */
+ volatile uint16_t PIPEACTR; /* PIPEACTR */
+ volatile uint16_t PIPEBCTR; /* PIPEBCTR */
+ volatile uint16_t PIPECCTR; /* PIPECCTR */
+ volatile uint16_t PIPEDCTR; /* PIPEDCTR */
+ volatile uint16_t PIPEECTR; /* PIPEECTR */
+ volatile uint16_t PIPEFCTR; /* PIPEFCTR */
+ volatile uint8_t dummy11[2]; /* */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE1TRE; /* PIPE1TRE */
+ volatile uint16_t PIPE1TRN; /* PIPE1TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE2TRE; /* PIPE2TRE */
+ volatile uint16_t PIPE2TRN; /* PIPE2TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE3TRE; /* PIPE3TRE */
+ volatile uint16_t PIPE3TRN; /* PIPE3TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE4TRE; /* PIPE4TRE */
+ volatile uint16_t PIPE4TRN; /* PIPE4TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE5TRE; /* PIPE5TRE */
+ volatile uint16_t PIPE5TRN; /* PIPE5TRN */
+/* end of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPEBTRE; /* PIPEBTRE */
+ volatile uint16_t PIPEBTRN; /* PIPEBTRN */
+ volatile uint16_t PIPECTRE; /* PIPECTRE */
+ volatile uint16_t PIPECTRN; /* PIPECTRN */
+ volatile uint16_t PIPEDTRE; /* PIPEDTRE */
+ volatile uint16_t PIPEDTRN; /* PIPEDTRN */
+ volatile uint16_t PIPEETRE; /* PIPEETRE */
+ volatile uint16_t PIPEETRN; /* PIPEETRN */
+ volatile uint16_t PIPEFTRE; /* PIPEFTRE */
+ volatile uint16_t PIPEFTRN; /* PIPEFTRN */
+ volatile uint16_t PIPE9TRE; /* PIPE9TRE */
+ volatile uint16_t PIPE9TRN; /* PIPE9TRN */
+ volatile uint16_t PIPEATRE; /* PIPEATRE */
+ volatile uint16_t PIPEATRN; /* PIPEATRN */
+ volatile uint8_t dummy12[16]; /* */
+#define USB20_DEVADD0_COUNT 0xB
+ volatile uint16_t DEVADD0; /* DEVADD0 */
+ volatile uint16_t DEVADD1; /* DEVADD1 */
+ volatile uint16_t DEVADD2; /* DEVADD2 */
+ volatile uint16_t DEVADD3; /* DEVADD3 */
+ volatile uint16_t DEVADD4; /* DEVADD4 */
+ volatile uint16_t DEVADD5; /* DEVADD5 */
+ volatile uint16_t DEVADD6; /* DEVADD6 */
+ volatile uint16_t DEVADD7; /* DEVADD7 */
+ volatile uint16_t DEVADD8; /* DEVADD8 */
+ volatile uint16_t DEVADD9; /* DEVADD9 */
+ volatile uint16_t DEVADDA; /* DEVADDA */
+ volatile uint8_t dummy13[28]; /* */
+ volatile uint16_t SUSPMODE; /* SUSPMODE */
+ volatile uint8_t dummy14[92]; /* */
+/* start of struct st_usb20_from_dmfifob0 */
+ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
+ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
+ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
+ volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
+ volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
+ volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
+ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
+ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
+/* end of struct st_usb20_from_dmfifob0 */
+/* start of struct st_usb20_from_dmfifob0 */
+ volatile uint32_t D1FIFOB0; /* D1FIFOB0 */
+ volatile uint32_t D1FIFOB1; /* D1FIFOB1 */
+ volatile uint32_t D1FIFOB2; /* D1FIFOB2 */
+ volatile uint32_t D1FIFOB3; /* D1FIFOB3 */
+ volatile uint32_t D1FIFOB4; /* D1FIFOB4 */
+ volatile uint32_t D1FIFOB5; /* D1FIFOB5 */
+ volatile uint32_t D1FIFOB6; /* D1FIFOB6 */
+ volatile uint32_t D1FIFOB7; /* D1FIFOB7 */
+/* end of struct st_usb20_from_dmfifob0 */
+};
+
+
+struct st_usb20_from_d0fifosel
+{
+ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
+ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
+};
+
+
+struct st_usb20_from_pipe1tre
+{
+ volatile uint16_t PIPE1TRE; /* PIPE1TRE */
+ volatile uint16_t PIPE1TRN; /* PIPE1TRN */
+};
+
+
+struct st_usb20_from_dmfifob0
+{
+#define USB20_D0FIFOB0_COUNT 0x8
+ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
+ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
+ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
+ volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
+ volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
+ volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
+ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
+ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
+};
+
+
+#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
+#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channnel array defines of USB20 */
+
+/* Channnel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT 2
+#define USB20_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &USB200, &USB201 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT 2
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+ &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channnel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT 5
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+ &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT 2
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+ &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channnel array defines of USB20 */
+
+
+#define SYSCFG0_0 USB200.SYSCFG0
+#define BUSWAIT_0 USB200.BUSWAIT
+#define SYSSTS0_0 USB200.SYSSTS0
+#define DVSTCTR0_0 USB200.DVSTCTR0
+#define TESTMODE_0 USB200.TESTMODE
+#define D0FBCFG_0 USB200.D0FBCFG
+#define D1FBCFG_0 USB200.D1FBCFG
+#define CFIFO_0 USB200.CFIFO.UINT32
+#define CFIFO_0L USB200.CFIFO.UINT16[L]
+#define CFIFO_0H USB200.CFIFO.UINT16[H]
+#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
+#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
+#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
+#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
+#define D0FIFO_0 USB200.D0FIFO.UINT32
+#define D0FIFO_0L USB200.D0FIFO.UINT16[L]
+#define D0FIFO_0H USB200.D0FIFO.UINT16[H]
+#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
+#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
+#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
+#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
+#define D1FIFO_0 USB200.D1FIFO.UINT32
+#define D1FIFO_0L USB200.D1FIFO.UINT16[L]
+#define D1FIFO_0H USB200.D1FIFO.UINT16[H]
+#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
+#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
+#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
+#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
+#define CFIFOSEL_0 USB200.CFIFOSEL
+#define CFIFOCTR_0 USB200.CFIFOCTR
+#define D0FIFOSEL_0 USB200.D0FIFOSEL
+#define D0FIFOCTR_0 USB200.D0FIFOCTR
+#define D1FIFOSEL_0 USB200.D1FIFOSEL
+#define D1FIFOCTR_0 USB200.D1FIFOCTR
+#define INTENB0_0 USB200.INTENB0
+#define INTENB1_0 USB200.INTENB1
+#define BRDYENB_0 USB200.BRDYENB
+#define NRDYENB_0 USB200.NRDYENB
+#define BEMPENB_0 USB200.BEMPENB
+#define SOFCFG_0 USB200.SOFCFG
+#define INTSTS0_0 USB200.INTSTS0
+#define INTSTS1_0 USB200.INTSTS1
+#define BRDYSTS_0 USB200.BRDYSTS
+#define NRDYSTS_0 USB200.NRDYSTS
+#define BEMPSTS_0 USB200.BEMPSTS
+#define FRMNUM_0 USB200.FRMNUM
+#define UFRMNUM_0 USB200.UFRMNUM
+#define USBADDR_0 USB200.USBADDR
+#define USBREQ_0 USB200.USBREQ
+#define USBVAL_0 USB200.USBVAL
+#define USBINDX_0 USB200.USBINDX
+#define USBLENG_0 USB200.USBLENG
+#define DCPCFG_0 USB200.DCPCFG
+#define DCPMAXP_0 USB200.DCPMAXP
+#define DCPCTR_0 USB200.DCPCTR
+#define PIPESEL_0 USB200.PIPESEL
+#define PIPECFG_0 USB200.PIPECFG
+#define PIPEBUF_0 USB200.PIPEBUF
+#define PIPEMAXP_0 USB200.PIPEMAXP
+#define PIPEPERI_0 USB200.PIPEPERI
+#define PIPE1CTR_0 USB200.PIPE1CTR
+#define PIPE2CTR_0 USB200.PIPE2CTR
+#define PIPE3CTR_0 USB200.PIPE3CTR
+#define PIPE4CTR_0 USB200.PIPE4CTR
+#define PIPE5CTR_0 USB200.PIPE5CTR
+#define PIPE6CTR_0 USB200.PIPE6CTR
+#define PIPE7CTR_0 USB200.PIPE7CTR
+#define PIPE8CTR_0 USB200.PIPE8CTR
+#define PIPE9CTR_0 USB200.PIPE9CTR
+#define PIPEACTR_0 USB200.PIPEACTR
+#define PIPEBCTR_0 USB200.PIPEBCTR
+#define PIPECCTR_0 USB200.PIPECCTR
+#define PIPEDCTR_0 USB200.PIPEDCTR
+#define PIPEECTR_0 USB200.PIPEECTR
+#define PIPEFCTR_0 USB200.PIPEFCTR
+#define PIPE1TRE_0 USB200.PIPE1TRE
+#define PIPE1TRN_0 USB200.PIPE1TRN
+#define PIPE2TRE_0 USB200.PIPE2TRE
+#define PIPE2TRN_0 USB200.PIPE2TRN
+#define PIPE3TRE_0 USB200.PIPE3TRE
+#define PIPE3TRN_0 USB200.PIPE3TRN
+#define PIPE4TRE_0 USB200.PIPE4TRE
+#define PIPE4TRN_0 USB200.PIPE4TRN
+#define PIPE5TRE_0 USB200.PIPE5TRE
+#define PIPE5TRN_0 USB200.PIPE5TRN
+#define PIPEBTRE_0 USB200.PIPEBTRE
+#define PIPEBTRN_0 USB200.PIPEBTRN
+#define PIPECTRE_0 USB200.PIPECTRE
+#define PIPECTRN_0 USB200.PIPECTRN
+#define PIPEDTRE_0 USB200.PIPEDTRE
+#define PIPEDTRN_0 USB200.PIPEDTRN
+#define PIPEETRE_0 USB200.PIPEETRE
+#define PIPEETRN_0 USB200.PIPEETRN
+#define PIPEFTRE_0 USB200.PIPEFTRE
+#define PIPEFTRN_0 USB200.PIPEFTRN
+#define PIPE9TRE_0 USB200.PIPE9TRE
+#define PIPE9TRN_0 USB200.PIPE9TRN
+#define PIPEATRE_0 USB200.PIPEATRE
+#define PIPEATRN_0 USB200.PIPEATRN
+#define DEVADD0_0 USB200.DEVADD0
+#define DEVADD1_0 USB200.DEVADD1
+#define DEVADD2_0 USB200.DEVADD2
+#define DEVADD3_0 USB200.DEVADD3
+#define DEVADD4_0 USB200.DEVADD4
+#define DEVADD5_0 USB200.DEVADD5
+#define DEVADD6_0 USB200.DEVADD6
+#define DEVADD7_0 USB200.DEVADD7
+#define DEVADD8_0 USB200.DEVADD8
+#define DEVADD9_0 USB200.DEVADD9
+#define DEVADDA_0 USB200.DEVADDA
+#define SUSPMODE_0 USB200.SUSPMODE
+#define D0FIFOB0_0 USB200.D0FIFOB0
+#define D0FIFOB1_0 USB200.D0FIFOB1
+#define D0FIFOB2_0 USB200.D0FIFOB2
+#define D0FIFOB3_0 USB200.D0FIFOB3
+#define D0FIFOB4_0 USB200.D0FIFOB4
+#define D0FIFOB5_0 USB200.D0FIFOB5
+#define D0FIFOB6_0 USB200.D0FIFOB6
+#define D0FIFOB7_0 USB200.D0FIFOB7
+#define D1FIFOB0_0 USB200.D1FIFOB0
+#define D1FIFOB1_0 USB200.D1FIFOB1
+#define D1FIFOB2_0 USB200.D1FIFOB2
+#define D1FIFOB3_0 USB200.D1FIFOB3
+#define D1FIFOB4_0 USB200.D1FIFOB4
+#define D1FIFOB5_0 USB200.D1FIFOB5
+#define D1FIFOB6_0 USB200.D1FIFOB6
+#define D1FIFOB7_0 USB200.D1FIFOB7
+#define SYSCFG0_1 USB201.SYSCFG0
+#define BUSWAIT_1 USB201.BUSWAIT
+#define SYSSTS0_1 USB201.SYSSTS0
+#define DVSTCTR0_1 USB201.DVSTCTR0
+#define TESTMODE_1 USB201.TESTMODE
+#define D0FBCFG_1 USB201.D0FBCFG
+#define D1FBCFG_1 USB201.D1FBCFG
+#define CFIFO_1 USB201.CFIFO.UINT32
+#define CFIFO_1L USB201.CFIFO.UINT16[L]
+#define CFIFO_1H USB201.CFIFO.UINT16[H]
+#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
+#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
+#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
+#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
+#define D0FIFO_1 USB201.D0FIFO.UINT32
+#define D0FIFO_1L USB201.D0FIFO.UINT16[L]
+#define D0FIFO_1H USB201.D0FIFO.UINT16[H]
+#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
+#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
+#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
+#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
+#define D1FIFO_1 USB201.D1FIFO.UINT32
+#define D1FIFO_1L USB201.D1FIFO.UINT16[L]
+#define D1FIFO_1H USB201.D1FIFO.UINT16[H]
+#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
+#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
+#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
+#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
+#define CFIFOSEL_1 USB201.CFIFOSEL
+#define CFIFOCTR_1 USB201.CFIFOCTR
+#define D0FIFOSEL_1 USB201.D0FIFOSEL
+#define D0FIFOCTR_1 USB201.D0FIFOCTR
+#define D1FIFOSEL_1 USB201.D1FIFOSEL
+#define D1FIFOCTR_1 USB201.D1FIFOCTR
+#define INTENB0_1 USB201.INTENB0
+#define INTENB1_1 USB201.INTENB1
+#define BRDYENB_1 USB201.BRDYENB
+#define NRDYENB_1 USB201.NRDYENB
+#define BEMPENB_1 USB201.BEMPENB
+#define SOFCFG_1 USB201.SOFCFG
+#define INTSTS0_1 USB201.INTSTS0
+#define INTSTS1_1 USB201.INTSTS1
+#define BRDYSTS_1 USB201.BRDYSTS
+#define NRDYSTS_1 USB201.NRDYSTS
+#define BEMPSTS_1 USB201.BEMPSTS
+#define FRMNUM_1 USB201.FRMNUM
+#define UFRMNUM_1 USB201.UFRMNUM
+#define USBADDR_1 USB201.USBADDR
+#define USBREQ_1 USB201.USBREQ
+#define USBVAL_1 USB201.USBVAL
+#define USBINDX_1 USB201.USBINDX
+#define USBLENG_1 USB201.USBLENG
+#define DCPCFG_1 USB201.DCPCFG
+#define DCPMAXP_1 USB201.DCPMAXP
+#define DCPCTR_1 USB201.DCPCTR
+#define PIPESEL_1 USB201.PIPESEL
+#define PIPECFG_1 USB201.PIPECFG
+#define PIPEBUF_1 USB201.PIPEBUF
+#define PIPEMAXP_1 USB201.PIPEMAXP
+#define PIPEPERI_1 USB201.PIPEPERI
+#define PIPE1CTR_1 USB201.PIPE1CTR
+#define PIPE2CTR_1 USB201.PIPE2CTR
+#define PIPE3CTR_1 USB201.PIPE3CTR
+#define PIPE4CTR_1 USB201.PIPE4CTR
+#define PIPE5CTR_1 USB201.PIPE5CTR
+#define PIPE6CTR_1 USB201.PIPE6CTR
+#define PIPE7CTR_1 USB201.PIPE7CTR
+#define PIPE8CTR_1 USB201.PIPE8CTR
+#define PIPE9CTR_1 USB201.PIPE9CTR
+#define PIPEACTR_1 USB201.PIPEACTR
+#define PIPEBCTR_1 USB201.PIPEBCTR
+#define PIPECCTR_1 USB201.PIPECCTR
+#define PIPEDCTR_1 USB201.PIPEDCTR
+#define PIPEECTR_1 USB201.PIPEECTR
+#define PIPEFCTR_1 USB201.PIPEFCTR
+#define PIPE1TRE_1 USB201.PIPE1TRE
+#define PIPE1TRN_1 USB201.PIPE1TRN
+#define PIPE2TRE_1 USB201.PIPE2TRE
+#define PIPE2TRN_1 USB201.PIPE2TRN
+#define PIPE3TRE_1 USB201.PIPE3TRE
+#define PIPE3TRN_1 USB201.PIPE3TRN
+#define PIPE4TRE_1 USB201.PIPE4TRE
+#define PIPE4TRN_1 USB201.PIPE4TRN
+#define PIPE5TRE_1 USB201.PIPE5TRE
+#define PIPE5TRN_1 USB201.PIPE5TRN
+#define PIPEBTRE_1 USB201.PIPEBTRE
+#define PIPEBTRN_1 USB201.PIPEBTRN
+#define PIPECTRE_1 USB201.PIPECTRE
+#define PIPECTRN_1 USB201.PIPECTRN
+#define PIPEDTRE_1 USB201.PIPEDTRE
+#define PIPEDTRN_1 USB201.PIPEDTRN
+#define PIPEETRE_1 USB201.PIPEETRE
+#define PIPEETRN_1 USB201.PIPEETRN
+#define PIPEFTRE_1 USB201.PIPEFTRE
+#define PIPEFTRN_1 USB201.PIPEFTRN
+#define PIPE9TRE_1 USB201.PIPE9TRE
+#define PIPE9TRN_1 USB201.PIPE9TRN
+#define PIPEATRE_1 USB201.PIPEATRE
+#define PIPEATRN_1 USB201.PIPEATRN
+#define DEVADD0_1 USB201.DEVADD0
+#define DEVADD1_1 USB201.DEVADD1
+#define DEVADD2_1 USB201.DEVADD2
+#define DEVADD3_1 USB201.DEVADD3
+#define DEVADD4_1 USB201.DEVADD4
+#define DEVADD5_1 USB201.DEVADD5
+#define DEVADD6_1 USB201.DEVADD6
+#define DEVADD7_1 USB201.DEVADD7
+#define DEVADD8_1 USB201.DEVADD8
+#define DEVADD9_1 USB201.DEVADD9
+#define DEVADDA_1 USB201.DEVADDA
+#define SUSPMODE_1 USB201.SUSPMODE
+#define D0FIFOB0_1 USB201.D0FIFOB0
+#define D0FIFOB1_1 USB201.D0FIFOB1
+#define D0FIFOB2_1 USB201.D0FIFOB2
+#define D0FIFOB3_1 USB201.D0FIFOB3
+#define D0FIFOB4_1 USB201.D0FIFOB4
+#define D0FIFOB5_1 USB201.D0FIFOB5
+#define D0FIFOB6_1 USB201.D0FIFOB6
+#define D0FIFOB7_1 USB201.D0FIFOB7
+#define D1FIFOB0_1 USB201.D1FIFOB0
+#define D1FIFOB1_1 USB201.D1FIFOB1
+#define D1FIFOB2_1 USB201.D1FIFOB2
+#define D1FIFOB3_1 USB201.D1FIFOB3
+#define D1FIFOB4_1 USB201.D1FIFOB4
+#define D1FIFOB5_1 USB201.D1FIFOB5
+#define D1FIFOB6_1 USB201.D1FIFOB6
+#define D1FIFOB7_1 USB201.D1FIFOB7
+/* <-SEC M1.10.1 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h
new file mode 100644
index 000000000..d20922524
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h
@@ -0,0 +1,1596 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : vdc5_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef VDC5_IODEFINE_H
+#define VDC5_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_vdc5
+{ /* VDC5 */
+ volatile uint32_t INP_UPDATE; /* INP_UPDATE */
+ volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
+ volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
+ volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
+ volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
+ volatile uint8_t dummy1[108]; /* */
+ volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
+#define VDC5_IMGCNT_NR_CNT0_COUNT 2
+ volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
+ volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
+ volatile uint8_t dummy2[20]; /* */
+ volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
+ volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
+ volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
+ volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
+ volatile uint8_t dummy3[4]; /* */
+ volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
+ volatile uint8_t dummy4[60]; /* */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
+#define VDC5_SC0_SCL0_FRC1_COUNT 7
+ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
+ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
+ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
+ volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
+ volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
+ volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
+ volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
+ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
+ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
+#define VDC5_SC0_SCL0_DS1_COUNT 7
+ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
+ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
+ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
+ volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
+ volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
+ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
+ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
+#define VDC5_SC0_SCL0_US1_COUNT 8
+ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
+ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
+ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
+ volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
+ volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
+ volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
+ volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
+ volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
+ volatile uint8_t dummy6[4]; /* */
+ volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
+ volatile uint8_t dummy7[16]; /* */
+ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
+ volatile uint8_t dummy8[4]; /* */
+#define VDC5_SC0_SCL1_WR1_COUNT 4
+ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
+ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
+ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
+ volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
+ volatile uint8_t dummy9[4]; /* */
+ volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
+ volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
+ volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
+ volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
+ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
+ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
+ volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC0_SCL1_PBUF0_COUNT 4
+ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
+ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
+ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
+ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
+ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
+ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+ volatile uint8_t dummy10[44]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
+ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
+#define VDC5_GR0_FLM1_COUNT 6
+ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
+ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
+ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
+ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
+ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
+ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
+#define VDC5_GR0_AB1_COUNT 3
+ volatile uint32_t GR0_AB1; /* GR0_AB1 */
+ volatile uint32_t GR0_AB2; /* GR0_AB2 */
+ volatile uint32_t GR0_AB3; /* GR0_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint8_t dummy11[12]; /* */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR0_AB7; /* GR0_AB7 */
+ volatile uint32_t GR0_AB8; /* GR0_AB8 */
+ volatile uint32_t GR0_AB9; /* GR0_AB9 */
+ volatile uint32_t GR0_AB10; /* GR0_AB10 */
+ volatile uint32_t GR0_AB11; /* GR0_AB11 */
+ volatile uint32_t GR0_BASE; /* GR0_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR0_CLUT; /* GR0_CLUT */
+ volatile uint8_t dummy12[44]; /* */
+/* start of struct st_vdc5_from_adj0_update */
+ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
+ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
+#define VDC5_ADJ0_ENH_TIM1_COUNT 3
+ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
+ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
+ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
+#define VDC5_ADJ0_ENH_SHP1_COUNT 6
+ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
+ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
+ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
+ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
+ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
+ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
+#define VDC5_ADJ0_ENH_LTI1_COUNT 2
+ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
+ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
+ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
+ volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+ volatile uint8_t dummy13[48]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
+ volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
+#define VDC5_GR2_FLM1_COUNT 6
+ volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
+ volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
+ volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
+ volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
+ volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
+ volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
+#define VDC5_GR2_AB1_COUNT 3
+ volatile uint32_t GR2_AB1; /* GR2_AB1 */
+ volatile uint32_t GR2_AB2; /* GR2_AB2 */
+ volatile uint32_t GR2_AB3; /* GR2_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR2_AB4; /* GR2_AB4 */
+ volatile uint32_t GR2_AB5; /* GR2_AB5 */
+ volatile uint32_t GR2_AB6; /* GR2_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR2_AB7; /* GR2_AB7 */
+ volatile uint32_t GR2_AB8; /* GR2_AB8 */
+ volatile uint32_t GR2_AB9; /* GR2_AB9 */
+ volatile uint32_t GR2_AB10; /* GR2_AB10 */
+ volatile uint32_t GR2_AB11; /* GR2_AB11 */
+ volatile uint32_t GR2_BASE; /* GR2_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR2_CLUT; /* GR2_CLUT */
+ volatile uint32_t GR2_MON; /* GR2_MON */
+ volatile uint8_t dummy14[40]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
+ volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
+#define VDC5_GR3_FLM1_COUNT 6
+ volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
+ volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
+ volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
+ volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
+ volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
+ volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
+#define VDC5_GR3_AB1_COUNT 3
+ volatile uint32_t GR3_AB1; /* GR3_AB1 */
+ volatile uint32_t GR3_AB2; /* GR3_AB2 */
+ volatile uint32_t GR3_AB3; /* GR3_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR3_AB4; /* GR3_AB4 */
+ volatile uint32_t GR3_AB5; /* GR3_AB5 */
+ volatile uint32_t GR3_AB6; /* GR3_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR3_AB7; /* GR3_AB7 */
+ volatile uint32_t GR3_AB8; /* GR3_AB8 */
+ volatile uint32_t GR3_AB9; /* GR3_AB9 */
+ volatile uint32_t GR3_AB10; /* GR3_AB10 */
+ volatile uint32_t GR3_AB11; /* GR3_AB11 */
+ volatile uint32_t GR3_BASE; /* GR3_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
+ volatile uint32_t GR3_MON; /* GR3_MON */
+ volatile uint8_t dummy15[40]; /* */
+ volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
+ volatile uint32_t GAM_SW; /* GAM_SW */
+#define VDC5_GAM_G_LUT1_COUNT 16
+ volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
+ volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
+ volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
+ volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
+ volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
+ volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
+ volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
+ volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
+ volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
+ volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
+ volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
+ volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
+ volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
+ volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
+ volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
+ volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
+#define VDC5_GAM_G_AREA1_COUNT 8
+ volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
+ volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
+ volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
+ volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
+ volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
+ volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
+ volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
+ volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
+ volatile uint8_t dummy16[24]; /* */
+ volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
+ volatile uint8_t dummy17[4]; /* */
+#define VDC5_GAM_B_LUT1_COUNT 16
+ volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
+ volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
+ volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
+ volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
+ volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
+ volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
+ volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
+ volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
+ volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
+ volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
+ volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
+ volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
+ volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
+ volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
+ volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
+ volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
+#define VDC5_GAM_B_AREA1_COUNT 8
+ volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
+ volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
+ volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
+ volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
+ volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
+ volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
+ volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
+ volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
+ volatile uint8_t dummy18[24]; /* */
+ volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
+ volatile uint8_t dummy19[4]; /* */
+#define VDC5_GAM_R_LUT1_COUNT 16
+ volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
+ volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
+ volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
+ volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
+ volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
+ volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
+ volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
+ volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
+ volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
+ volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
+ volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
+ volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
+ volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
+ volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
+ volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
+ volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
+#define VDC5_GAM_R_AREA1_COUNT 8
+ volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
+ volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
+ volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
+ volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
+ volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
+ volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
+ volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
+ volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
+ volatile uint8_t dummy20[24]; /* */
+ volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
+ volatile uint32_t TCON_TIM; /* TCON_TIM */
+#define VDC5_TCON_TIM_STVA1_COUNT 2
+ volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
+ volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
+#define VDC5_TCON_TIM_STVB1_COUNT 2
+ volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
+ volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
+#define VDC5_TCON_TIM_STH1_COUNT 2
+ volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
+ volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
+#define VDC5_TCON_TIM_STB1_COUNT 2
+ volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
+ volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
+#define VDC5_TCON_TIM_CPV1_COUNT 2
+ volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
+ volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
+#define VDC5_TCON_TIM_POLA1_COUNT 2
+ volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
+ volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
+#define VDC5_TCON_TIM_POLB1_COUNT 2
+ volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
+ volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
+ volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
+ volatile uint8_t dummy21[60]; /* */
+ volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
+ volatile uint32_t OUT_SET; /* OUT_SET */
+#define VDC5_OUT_BRIGHT1_COUNT 2
+ volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
+ volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
+ volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
+ volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
+ volatile uint8_t dummy22[12]; /* */
+ volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
+ volatile uint8_t dummy23[88]; /* */
+#define VDC5_SYSCNT_INT1_COUNT 6
+ volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
+ volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
+ volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
+ volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
+ volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
+ volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
+ volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
+ volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
+ volatile uint8_t dummy24[356]; /* */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
+#define VDC5_SC1_SCL0_FRC1_COUNT 7
+ volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
+ volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
+ volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
+ volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
+ volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
+ volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
+ volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
+ volatile uint8_t dummy25[4]; /* */
+ volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
+ volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
+ volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
+ volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
+ volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
+ volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
+ volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
+ volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
+ volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
+ volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
+#define VDC5_SC1_SC1_SCL0_US1_COUNT 8
+ volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
+ volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
+ volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
+ volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
+ volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
+ volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
+ volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
+ volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
+ volatile uint8_t dummy26[4]; /* */
+ volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
+ volatile uint8_t dummy27[16]; /* */
+ volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
+ volatile uint8_t dummy28[4]; /* */
+#define VDC5_SC1_SCL1_WR1_COUNT 4
+ volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
+ volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
+ volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
+ volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
+ volatile uint8_t dummy29[4]; /* */
+ volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
+ volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
+ volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
+ volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
+ volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
+ volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
+ volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC1_SCL1_PBUF0_COUNT 4
+ volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
+ volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
+ volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
+ volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
+ volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
+ volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+ volatile uint8_t dummy30[44]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
+ volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
+#define VDC5_GR1_FLM1_COUNT 6
+ volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
+ volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
+ volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
+ volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
+ volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
+ volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
+#define VDC5_GR1_AB1_COUNT 3
+ volatile uint32_t GR1_AB1; /* GR1_AB1 */
+ volatile uint32_t GR1_AB2; /* GR1_AB2 */
+ volatile uint32_t GR1_AB3; /* GR1_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR1_AB4; /* GR1_AB4 */
+ volatile uint32_t GR1_AB5; /* GR1_AB5 */
+ volatile uint32_t GR1_AB6; /* GR1_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR1_AB7; /* GR1_AB7 */
+ volatile uint32_t GR1_AB8; /* GR1_AB8 */
+ volatile uint32_t GR1_AB9; /* GR1_AB9 */
+ volatile uint32_t GR1_AB10; /* GR1_AB10 */
+ volatile uint32_t GR1_AB11; /* GR1_AB11 */
+ volatile uint32_t GR1_BASE; /* GR1_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR1_CLUT; /* GR1_CLUT */
+ volatile uint32_t GR1_MON; /* GR1_MON */
+ volatile uint8_t dummy31[40]; /* */
+/* start of struct st_vdc5_from_adj0_update */
+ volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
+ volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
+#define VDC5_ADJ1_ENH_TIM1_COUNT 3
+ volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
+ volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
+ volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
+#define VDC5_ADJ1_ENH_SHP1_COUNT 6
+ volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
+ volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
+ volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
+ volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
+ volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
+ volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
+#define VDC5_ADJ1_ENH_LTI1_COUNT 2
+ volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
+ volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
+ volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
+ volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+ volatile uint8_t dummy32[48]; /* */
+ volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
+ volatile uint8_t dummy33[28]; /* */
+#define VDC5_GR_VIN_AB1_COUNT 7
+ volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
+ volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
+ volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
+ volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
+ volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
+ volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
+ volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
+ volatile uint8_t dummy34[16]; /* */
+ volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
+ volatile uint8_t dummy35[4]; /* */
+ volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
+ volatile uint8_t dummy36[40]; /* */
+ volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
+#define VDC5_OIR_SCL0_FRC1_COUNT 7
+ volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
+ volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
+ volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
+ volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
+ volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
+ volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
+ volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
+ volatile uint8_t dummy37[12]; /* */
+#define VDC5_OIR_SCL0_DS1_COUNT 3
+ volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
+ volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
+ volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
+ volatile uint8_t dummy38[12]; /* */
+ volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
+ volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
+ volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
+ volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
+ volatile uint8_t dummy39[16]; /* */
+ volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
+ volatile uint8_t dummy40[4]; /* */
+ volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
+ volatile uint8_t dummy41[16]; /* */
+ volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
+ volatile uint8_t dummy42[4]; /* */
+#define VDC5_OIR_SCL1_WR1_COUNT 4
+ volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
+ volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
+ volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
+ volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
+ volatile uint8_t dummy43[4]; /* */
+ volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
+ volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
+ volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
+ volatile uint8_t dummy44[88]; /* */
+ volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
+ volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
+#define VDC5_GR_OIR_FLM1_COUNT 6
+ volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
+ volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
+ volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
+ volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
+ volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
+ volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
+#define VDC5_GR_OIR_AB1_COUNT 3
+ volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
+ volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
+ volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
+ volatile uint8_t dummy45[12]; /* */
+ volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
+ volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
+ volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
+ volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
+ volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
+ volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
+ volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
+ volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
+};
+
+
+struct st_vdc5_from_gr0_update
+{
+ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
+ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
+ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
+ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
+ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
+ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
+ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
+ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
+ volatile uint32_t GR0_AB1; /* GR0_AB1 */
+ volatile uint32_t GR0_AB2; /* GR0_AB2 */
+ volatile uint32_t GR0_AB3; /* GR0_AB3 */
+};
+
+
+struct st_vdc5_from_gr0_ab7
+{
+ volatile uint32_t GR0_AB7; /* GR0_AB7 */
+ volatile uint32_t GR0_AB8; /* GR0_AB8 */
+ volatile uint32_t GR0_AB9; /* GR0_AB9 */
+ volatile uint32_t GR0_AB10; /* GR0_AB10 */
+ volatile uint32_t GR0_AB11; /* GR0_AB11 */
+ volatile uint32_t GR0_BASE; /* GR0_BASE */
+};
+
+
+struct st_vdc5_from_adj0_update
+{
+ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
+ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
+ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
+ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
+ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
+ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
+ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
+ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
+ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
+ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
+ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
+ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
+ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
+ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
+ volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
+};
+
+
+struct st_vdc5_from_sc0_scl0_update
+{
+ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
+ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
+ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
+ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
+ volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
+ volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
+ volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
+ volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
+ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
+ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
+ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
+ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
+ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
+ volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
+ volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
+ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
+ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
+ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
+ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
+ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
+ volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
+ volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
+ volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
+ volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
+ volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
+ volatile uint8_t dummy6[4]; /* */
+ volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
+ volatile uint8_t dummy7[16]; /* */
+ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
+ volatile uint8_t dummy8[4]; /* */
+ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
+ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
+ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
+ volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
+ volatile uint8_t dummy9[4]; /* */
+ volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
+ volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
+ volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
+ volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
+ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
+ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
+};
+
+
+struct st_vdc5_from_sc0_scl1_pbuf0
+{
+ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
+ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
+ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
+ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
+ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
+ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
+};
+
+
+#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
+#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channnel array defines of VDC5 */
+
+/* Channnel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT 2
+#define VDC5_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &VDC50, &VDC51 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2
+#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+ &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+ &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+ &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+ &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+ &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2
+#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+ &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+ &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channnel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE VDC50.INP_UPDATE
+#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
+#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
+#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
+#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
+#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
+#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
+#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
+#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
+#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
+#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
+#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
+#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
+#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
+#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
+#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
+#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
+#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
+#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
+#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
+#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
+#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
+#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
+#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
+#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
+#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
+#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
+#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
+#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
+#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
+#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
+#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
+#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
+#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
+#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
+#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
+#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
+#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
+#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
+#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
+#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
+#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
+#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
+#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
+#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
+#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
+#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
+#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
+#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
+#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
+#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
+#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
+#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
+#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
+#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
+#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
+#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
+#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
+#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
+#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
+#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
+#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
+#define VDC50GR0_UPDATE VDC50.GR0_UPDATE
+#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
+#define VDC50GR0_FLM1 VDC50.GR0_FLM1
+#define VDC50GR0_FLM2 VDC50.GR0_FLM2
+#define VDC50GR0_FLM3 VDC50.GR0_FLM3
+#define VDC50GR0_FLM4 VDC50.GR0_FLM4
+#define VDC50GR0_FLM5 VDC50.GR0_FLM5
+#define VDC50GR0_FLM6 VDC50.GR0_FLM6
+#define VDC50GR0_AB1 VDC50.GR0_AB1
+#define VDC50GR0_AB2 VDC50.GR0_AB2
+#define VDC50GR0_AB3 VDC50.GR0_AB3
+#define VDC50GR0_AB7 VDC50.GR0_AB7
+#define VDC50GR0_AB8 VDC50.GR0_AB8
+#define VDC50GR0_AB9 VDC50.GR0_AB9
+#define VDC50GR0_AB10 VDC50.GR0_AB10
+#define VDC50GR0_AB11 VDC50.GR0_AB11
+#define VDC50GR0_BASE VDC50.GR0_BASE
+#define VDC50GR0_CLUT VDC50.GR0_CLUT
+#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
+#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
+#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
+#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
+#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
+#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
+#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
+#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
+#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
+#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
+#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
+#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
+#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
+#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
+#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
+#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
+#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
+#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
+#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
+#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
+#define VDC50GR2_UPDATE VDC50.GR2_UPDATE
+#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
+#define VDC50GR2_FLM1 VDC50.GR2_FLM1
+#define VDC50GR2_FLM2 VDC50.GR2_FLM2
+#define VDC50GR2_FLM3 VDC50.GR2_FLM3
+#define VDC50GR2_FLM4 VDC50.GR2_FLM4
+#define VDC50GR2_FLM5 VDC50.GR2_FLM5
+#define VDC50GR2_FLM6 VDC50.GR2_FLM6
+#define VDC50GR2_AB1 VDC50.GR2_AB1
+#define VDC50GR2_AB2 VDC50.GR2_AB2
+#define VDC50GR2_AB3 VDC50.GR2_AB3
+#define VDC50GR2_AB4 VDC50.GR2_AB4
+#define VDC50GR2_AB5 VDC50.GR2_AB5
+#define VDC50GR2_AB6 VDC50.GR2_AB6
+#define VDC50GR2_AB7 VDC50.GR2_AB7
+#define VDC50GR2_AB8 VDC50.GR2_AB8
+#define VDC50GR2_AB9 VDC50.GR2_AB9
+#define VDC50GR2_AB10 VDC50.GR2_AB10
+#define VDC50GR2_AB11 VDC50.GR2_AB11
+#define VDC50GR2_BASE VDC50.GR2_BASE
+#define VDC50GR2_CLUT VDC50.GR2_CLUT
+#define VDC50GR2_MON VDC50.GR2_MON
+#define VDC50GR3_UPDATE VDC50.GR3_UPDATE
+#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
+#define VDC50GR3_FLM1 VDC50.GR3_FLM1
+#define VDC50GR3_FLM2 VDC50.GR3_FLM2
+#define VDC50GR3_FLM3 VDC50.GR3_FLM3
+#define VDC50GR3_FLM4 VDC50.GR3_FLM4
+#define VDC50GR3_FLM5 VDC50.GR3_FLM5
+#define VDC50GR3_FLM6 VDC50.GR3_FLM6
+#define VDC50GR3_AB1 VDC50.GR3_AB1
+#define VDC50GR3_AB2 VDC50.GR3_AB2
+#define VDC50GR3_AB3 VDC50.GR3_AB3
+#define VDC50GR3_AB4 VDC50.GR3_AB4
+#define VDC50GR3_AB5 VDC50.GR3_AB5
+#define VDC50GR3_AB6 VDC50.GR3_AB6
+#define VDC50GR3_AB7 VDC50.GR3_AB7
+#define VDC50GR3_AB8 VDC50.GR3_AB8
+#define VDC50GR3_AB9 VDC50.GR3_AB9
+#define VDC50GR3_AB10 VDC50.GR3_AB10
+#define VDC50GR3_AB11 VDC50.GR3_AB11
+#define VDC50GR3_BASE VDC50.GR3_BASE
+#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
+#define VDC50GR3_MON VDC50.GR3_MON
+#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
+#define VDC50GAM_SW VDC50.GAM_SW
+#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
+#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
+#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
+#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
+#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
+#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
+#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
+#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
+#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
+#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
+#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
+#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
+#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
+#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
+#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
+#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
+#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
+#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
+#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
+#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
+#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
+#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
+#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
+#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
+#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
+#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
+#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
+#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
+#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
+#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
+#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
+#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
+#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
+#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
+#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
+#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
+#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
+#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
+#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
+#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
+#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
+#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
+#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
+#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
+#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
+#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
+#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
+#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
+#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
+#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
+#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
+#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
+#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
+#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
+#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
+#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
+#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
+#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
+#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
+#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
+#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
+#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
+#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
+#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
+#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
+#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
+#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
+#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
+#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
+#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
+#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
+#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
+#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
+#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
+#define VDC50TCON_UPDATE VDC50.TCON_UPDATE
+#define VDC50TCON_TIM VDC50.TCON_TIM
+#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
+#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
+#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
+#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
+#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
+#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
+#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
+#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
+#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
+#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
+#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
+#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
+#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
+#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
+#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
+#define VDC50OUT_UPDATE VDC50.OUT_UPDATE
+#define VDC50OUT_SET VDC50.OUT_SET
+#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
+#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
+#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
+#define VDC50OUT_PDTHA VDC50.OUT_PDTHA
+#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
+#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
+#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
+#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
+#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
+#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
+#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
+#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
+#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
+#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
+#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
+#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
+#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
+#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
+#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
+#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
+#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
+#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
+#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
+#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
+#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
+#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
+#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
+#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
+#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
+#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
+#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
+#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
+#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
+#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
+#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
+#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
+#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
+#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
+#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
+#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
+#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
+#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
+#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
+#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
+#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
+#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
+#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
+#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
+#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
+#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
+#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
+#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
+#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
+#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
+#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
+#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
+#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
+#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
+#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
+#define VDC50GR1_UPDATE VDC50.GR1_UPDATE
+#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
+#define VDC50GR1_FLM1 VDC50.GR1_FLM1
+#define VDC50GR1_FLM2 VDC50.GR1_FLM2
+#define VDC50GR1_FLM3 VDC50.GR1_FLM3
+#define VDC50GR1_FLM4 VDC50.GR1_FLM4
+#define VDC50GR1_FLM5 VDC50.GR1_FLM5
+#define VDC50GR1_FLM6 VDC50.GR1_FLM6
+#define VDC50GR1_AB1 VDC50.GR1_AB1
+#define VDC50GR1_AB2 VDC50.GR1_AB2
+#define VDC50GR1_AB3 VDC50.GR1_AB3
+#define VDC50GR1_AB4 VDC50.GR1_AB4
+#define VDC50GR1_AB5 VDC50.GR1_AB5
+#define VDC50GR1_AB6 VDC50.GR1_AB6
+#define VDC50GR1_AB7 VDC50.GR1_AB7
+#define VDC50GR1_AB8 VDC50.GR1_AB8
+#define VDC50GR1_AB9 VDC50.GR1_AB9
+#define VDC50GR1_AB10 VDC50.GR1_AB10
+#define VDC50GR1_AB11 VDC50.GR1_AB11
+#define VDC50GR1_BASE VDC50.GR1_BASE
+#define VDC50GR1_CLUT VDC50.GR1_CLUT
+#define VDC50GR1_MON VDC50.GR1_MON
+#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
+#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
+#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
+#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
+#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
+#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
+#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
+#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
+#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
+#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
+#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
+#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
+#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
+#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
+#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
+#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
+#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
+#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
+#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
+#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
+#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
+#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
+#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
+#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
+#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
+#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
+#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
+#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
+#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
+#define VDC50GR_VIN_MON VDC50.GR_VIN_MON
+#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
+#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
+#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
+#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
+#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
+#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
+#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
+#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
+#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
+#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
+#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
+#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
+#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
+#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
+#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
+#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
+#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
+#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
+#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
+#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
+#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
+#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
+#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
+#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
+#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
+#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
+#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
+#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
+#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
+#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
+#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
+#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
+#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
+#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
+#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
+#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
+#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
+#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
+#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
+#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
+#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
+#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
+#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
+#define VDC50GR_OIR_MON VDC50.GR_OIR_MON
+#define VDC51INP_UPDATE VDC51.INP_UPDATE
+#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
+#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
+#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
+#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
+#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
+#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
+#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
+#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
+#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
+#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
+#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
+#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
+#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
+#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
+#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
+#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
+#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
+#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
+#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
+#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
+#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
+#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
+#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
+#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
+#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
+#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
+#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
+#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
+#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
+#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
+#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
+#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
+#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
+#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
+#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
+#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
+#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
+#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
+#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
+#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
+#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
+#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
+#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
+#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
+#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
+#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
+#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
+#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
+#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
+#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
+#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
+#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
+#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
+#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
+#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
+#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
+#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
+#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
+#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
+#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
+#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
+#define VDC51GR0_UPDATE VDC51.GR0_UPDATE
+#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
+#define VDC51GR0_FLM1 VDC51.GR0_FLM1
+#define VDC51GR0_FLM2 VDC51.GR0_FLM2
+#define VDC51GR0_FLM3 VDC51.GR0_FLM3
+#define VDC51GR0_FLM4 VDC51.GR0_FLM4
+#define VDC51GR0_FLM5 VDC51.GR0_FLM5
+#define VDC51GR0_FLM6 VDC51.GR0_FLM6
+#define VDC51GR0_AB1 VDC51.GR0_AB1
+#define VDC51GR0_AB2 VDC51.GR0_AB2
+#define VDC51GR0_AB3 VDC51.GR0_AB3
+#define VDC51GR0_AB7 VDC51.GR0_AB7
+#define VDC51GR0_AB8 VDC51.GR0_AB8
+#define VDC51GR0_AB9 VDC51.GR0_AB9
+#define VDC51GR0_AB10 VDC51.GR0_AB10
+#define VDC51GR0_AB11 VDC51.GR0_AB11
+#define VDC51GR0_BASE VDC51.GR0_BASE
+#define VDC51GR0_CLUT VDC51.GR0_CLUT
+#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
+#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
+#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
+#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
+#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
+#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
+#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
+#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
+#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
+#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
+#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
+#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
+#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
+#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
+#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
+#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
+#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
+#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
+#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
+#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
+#define VDC51GR2_UPDATE VDC51.GR2_UPDATE
+#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
+#define VDC51GR2_FLM1 VDC51.GR2_FLM1
+#define VDC51GR2_FLM2 VDC51.GR2_FLM2
+#define VDC51GR2_FLM3 VDC51.GR2_FLM3
+#define VDC51GR2_FLM4 VDC51.GR2_FLM4
+#define VDC51GR2_FLM5 VDC51.GR2_FLM5
+#define VDC51GR2_FLM6 VDC51.GR2_FLM6
+#define VDC51GR2_AB1 VDC51.GR2_AB1
+#define VDC51GR2_AB2 VDC51.GR2_AB2
+#define VDC51GR2_AB3 VDC51.GR2_AB3
+#define VDC51GR2_AB4 VDC51.GR2_AB4
+#define VDC51GR2_AB5 VDC51.GR2_AB5
+#define VDC51GR2_AB6 VDC51.GR2_AB6
+#define VDC51GR2_AB7 VDC51.GR2_AB7
+#define VDC51GR2_AB8 VDC51.GR2_AB8
+#define VDC51GR2_AB9 VDC51.GR2_AB9
+#define VDC51GR2_AB10 VDC51.GR2_AB10
+#define VDC51GR2_AB11 VDC51.GR2_AB11
+#define VDC51GR2_BASE VDC51.GR2_BASE
+#define VDC51GR2_CLUT VDC51.GR2_CLUT
+#define VDC51GR2_MON VDC51.GR2_MON
+#define VDC51GR3_UPDATE VDC51.GR3_UPDATE
+#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
+#define VDC51GR3_FLM1 VDC51.GR3_FLM1
+#define VDC51GR3_FLM2 VDC51.GR3_FLM2
+#define VDC51GR3_FLM3 VDC51.GR3_FLM3
+#define VDC51GR3_FLM4 VDC51.GR3_FLM4
+#define VDC51GR3_FLM5 VDC51.GR3_FLM5
+#define VDC51GR3_FLM6 VDC51.GR3_FLM6
+#define VDC51GR3_AB1 VDC51.GR3_AB1
+#define VDC51GR3_AB2 VDC51.GR3_AB2
+#define VDC51GR3_AB3 VDC51.GR3_AB3
+#define VDC51GR3_AB4 VDC51.GR3_AB4
+#define VDC51GR3_AB5 VDC51.GR3_AB5
+#define VDC51GR3_AB6 VDC51.GR3_AB6
+#define VDC51GR3_AB7 VDC51.GR3_AB7
+#define VDC51GR3_AB8 VDC51.GR3_AB8
+#define VDC51GR3_AB9 VDC51.GR3_AB9
+#define VDC51GR3_AB10 VDC51.GR3_AB10
+#define VDC51GR3_AB11 VDC51.GR3_AB11
+#define VDC51GR3_BASE VDC51.GR3_BASE
+#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
+#define VDC51GR3_MON VDC51.GR3_MON
+#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
+#define VDC51GAM_SW VDC51.GAM_SW
+#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
+#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
+#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
+#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
+#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
+#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
+#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
+#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
+#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
+#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
+#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
+#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
+#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
+#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
+#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
+#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
+#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
+#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
+#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
+#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
+#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
+#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
+#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
+#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
+#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
+#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
+#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
+#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
+#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
+#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
+#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
+#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
+#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
+#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
+#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
+#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
+#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
+#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
+#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
+#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
+#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
+#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
+#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
+#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
+#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
+#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
+#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
+#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
+#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
+#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
+#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
+#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
+#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
+#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
+#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
+#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
+#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
+#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
+#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
+#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
+#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
+#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
+#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
+#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
+#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
+#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
+#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
+#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
+#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
+#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
+#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
+#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
+#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
+#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
+#define VDC51TCON_UPDATE VDC51.TCON_UPDATE
+#define VDC51TCON_TIM VDC51.TCON_TIM
+#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
+#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
+#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
+#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
+#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
+#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
+#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
+#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
+#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
+#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
+#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
+#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
+#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
+#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
+#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
+#define VDC51OUT_UPDATE VDC51.OUT_UPDATE
+#define VDC51OUT_SET VDC51.OUT_SET
+#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
+#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
+#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
+#define VDC51OUT_PDTHA VDC51.OUT_PDTHA
+#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
+#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
+#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
+#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
+#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
+#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
+#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
+#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
+#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
+#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
+#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
+#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
+#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
+#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
+#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
+#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
+#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
+#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
+#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
+#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
+#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
+#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
+#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
+#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
+#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
+#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
+#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
+#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
+#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
+#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
+#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
+#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
+#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
+#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
+#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
+#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
+#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
+#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
+#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
+#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
+#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
+#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
+#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
+#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
+#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
+#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
+#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
+#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
+#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
+#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
+#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
+#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
+#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
+#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
+#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
+#define VDC51GR1_UPDATE VDC51.GR1_UPDATE
+#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
+#define VDC51GR1_FLM1 VDC51.GR1_FLM1
+#define VDC51GR1_FLM2 VDC51.GR1_FLM2
+#define VDC51GR1_FLM3 VDC51.GR1_FLM3
+#define VDC51GR1_FLM4 VDC51.GR1_FLM4
+#define VDC51GR1_FLM5 VDC51.GR1_FLM5
+#define VDC51GR1_FLM6 VDC51.GR1_FLM6
+#define VDC51GR1_AB1 VDC51.GR1_AB1
+#define VDC51GR1_AB2 VDC51.GR1_AB2
+#define VDC51GR1_AB3 VDC51.GR1_AB3
+#define VDC51GR1_AB4 VDC51.GR1_AB4
+#define VDC51GR1_AB5 VDC51.GR1_AB5
+#define VDC51GR1_AB6 VDC51.GR1_AB6
+#define VDC51GR1_AB7 VDC51.GR1_AB7
+#define VDC51GR1_AB8 VDC51.GR1_AB8
+#define VDC51GR1_AB9 VDC51.GR1_AB9
+#define VDC51GR1_AB10 VDC51.GR1_AB10
+#define VDC51GR1_AB11 VDC51.GR1_AB11
+#define VDC51GR1_BASE VDC51.GR1_BASE
+#define VDC51GR1_CLUT VDC51.GR1_CLUT
+#define VDC51GR1_MON VDC51.GR1_MON
+#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
+#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
+#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
+#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
+#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
+#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
+#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
+#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
+#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
+#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
+#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
+#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
+#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
+#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
+#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
+#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
+#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
+#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
+#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
+#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
+#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
+#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
+#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
+#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
+#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
+#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
+#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
+#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
+#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
+#define VDC51GR_VIN_MON VDC51.GR_VIN_MON
+#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
+#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
+#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
+#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
+#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
+#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
+#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
+#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
+#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
+#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
+#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
+#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
+#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
+#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
+#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
+#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
+#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
+#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
+#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
+#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
+#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
+#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
+#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
+#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
+#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
+#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
+#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
+#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
+#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
+#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
+#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
+#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
+#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
+#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
+#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
+#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
+#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
+#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
+#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
+#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
+#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
+#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
+#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
+#define VDC51GR_OIR_MON VDC51.GR_OIR_MON
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h
new file mode 100644
index 000000000..0ee2a5321
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : wdt_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef WDT_IODEFINE_H
+#define WDT_IODEFINE_H
+
+struct st_wdt
+{ /* WDT */
+ volatile uint16_t WTCSR; /* WTCSR */
+ volatile uint16_t WTCNT; /* WTCNT */
+ volatile uint16_t WRCSR; /* WRCSR */
+};
+
+
+#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */
+
+
+#define WDTWTCSR WDT.WTCSR
+#define WDTWTCNT WDT.WTCNT
+#define WDTWRCSR WDT.WRCSR
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h
new file mode 100644
index 000000000..0d40bbc74
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h
@@ -0,0 +1,11 @@
+#ifndef __REG32_T
+#define __REG32_T
+
+union reg32_t {
+ volatile uint32_t UINT32;
+ volatile uint16_t UINT16[2];
+ volatile uint8_t UINT8[4];
+};
+
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/rza_io_regrw.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/rza_io_regrw.h
new file mode 100644
index 000000000..5f0fec64d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/rza_io_regrw.h
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rza_io_regrw.h
+* $Rev: 1135 $
+* $Date:: 2014-08-08 10:11:30 +0900#$
+* Description : Low level register read/write header
+*******************************************************************************/
+#ifndef RZA_IO_REGRW_H
+#define RZA_IO_REGRW_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+/* ==== includes each bit mask header ==== */
+#include "cpg_iobitmask.h"
+#include "intc_iobitmask.h"
+#include "bsc_iobitmask.h"
+#include "dmac_iobitmask.h"
+#include "mtu2_iobitmask.h"
+#include "ostm_iobitmask.h"
+#include "scif_iobitmask.h"
+#include "rspi_iobitmask.h"
+#include "riic_iobitmask.h"
+#include "usb_iobitmask.h"
+#include "gpio_iobitmask.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask);
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
+uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask);
+uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
+uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RZA_IO_REGRW_H */
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
new file mode 100644
index 000000000..59e3da598
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c
@@ -0,0 +1,826 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file mbed_sf_boot.c
+* $Rev: $
+* $Date:: $
+* @brief RZ_A1 serial flash boot loader
+******************************************************************************/
+#if defined (__CC_ARM)
+#pragma arm section rodata = "BOOT_LOADER"
+const char boot_loader[] __attribute__((used)) =
+
+#else
+const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) =
+
+#endif
+{
+ 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+ 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+ 0x00,0x30,0x00,0x18,0x74,0x30,0x00,0x18,0x78,0x30,0x00,0x18,0x7C,0x30,0x00,0x18,
+ 0x80,0x30,0x00,0x18,0x84,0x30,0x00,0x18,0x88,0x30,0x00,0x18,0x8C,0x30,0x00,0x18,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,
+ 0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,
+ 0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,
+ 0x10,0x80,0xBD,0xE8,0x97,0x28,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20,
+ 0x70,0x40,0x2D,0xE9,0x02,0x29,0xA0,0xE3,0xC8,0x40,0x9F,0xE5,0x0F,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x4C,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0x06,0x00,0x00,0x1A,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0x33,0x00,0x00,0xEB,0x08,0x00,0x44,0xE2,0xB8,0x00,0xD0,0xE1,0x01,0x34,0xA0,0xE3,
+ 0x94,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0x32,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,
+ 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x36,0x00,0x00,0xEB,
+ 0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x00,0x00,0xA0,0xE3,0x4C,0x10,0x9F,0xE5,
+ 0x04,0x00,0x81,0xE5,0x00,0x20,0xA0,0xE1,0x44,0x40,0x9F,0xE5,0x00,0x10,0xA0,0xE1,
+ 0x03,0x30,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x1C,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3,
+ 0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x17,0x00,0x00,0xEB,
+ 0x05,0x00,0xA0,0xE1,0x01,0x3C,0xA0,0xE3,0x70,0x40,0xBD,0xE8,0x08,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x11,0x00,0x00,0xEA,0x08,0x18,0xFF,0xFC,0x0C,0xA0,0xEF,0x3F,
+ 0x00,0xA0,0xEF,0x3F,0x08,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9,0x00,0x40,0xD0,0xE5,
+ 0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0xC0,0xE5,
+ 0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1,0x11,0x12,0xA0,0xE1,
+ 0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1,0x10,0x80,0xBD,0xE8,
+ 0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,
+ 0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8,0x00,0x00,0xD0,0xE5,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xB0,0x00,0xD0,0xE1,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x90,0xE5,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x10,0xFF,0x2F,0xE1,0x10,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x7D,0x03,0x00,0xEB,
+ 0x2C,0x10,0x9F,0xE5,0x00,0x00,0xA0,0xE3,0x7B,0x03,0x00,0xEB,0x20,0x20,0x9F,0xE5,
+ 0x00,0x10,0xA0,0xE3,0x01,0x00,0xA0,0xE1,0x51,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0x00,0x00,0x00,0x0A,0xFE,0xFF,0xFF,0xEA,0x10,0x40,0xBD,0xE8,0x04,0x00,0x9F,0xE5,
+ 0xEE,0xFF,0xFF,0xEA,0x94,0x2A,0x02,0x20,0x00,0x40,0x00,0x18,0xF0,0x41,0x2D,0xE9,
+ 0x00,0x40,0xA0,0xE1,0x03,0x70,0xA0,0xE1,0x02,0x50,0xA0,0xE1,0x18,0x60,0x9D,0xE5,
+ 0x01,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE1,0xD9,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0xF0,0x81,0xBD,0x18,0x00,0x00,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0F,0x00,0x56,0xE3,
+ 0x54,0x16,0x9F,0xE5,0x18,0x30,0x81,0xE2,0x00,0x00,0x81,0xE5,0x08,0x00,0x81,0xE5,
+ 0x14,0x20,0x81,0xE5,0xD8,0x20,0xA0,0x13,0x41,0x00,0x83,0xE8,0xDC,0x20,0xA0,0x03,
+ 0x20,0x00,0x81,0xE5,0x01,0x00,0x55,0xE3,0x24,0x00,0x81,0xE5,0x28,0x00,0x81,0xE5,
+ 0x2C,0x00,0x81,0xE5,0x30,0x00,0x81,0xE5,0x46,0x20,0xC1,0xE5,0xA4,0x20,0xA0,0x01,
+ 0x48,0x20,0x81,0x05,0x48,0x40,0x81,0x15,0x34,0x00,0x81,0xE5,0x38,0x00,0x81,0xE5,
+ 0x3C,0x00,0x81,0xE5,0x40,0x00,0x81,0xE5,0x08,0x00,0xA0,0xE1,0xF8,0x15,0x9F,0xE5,
+ 0x91,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x07,0x20,0xA0,0xE1,
+ 0x05,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x9E,0x01,0x00,0xEA,
+ 0xFF,0x5F,0x2D,0xE9,0x00,0xB0,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x01,0x60,0xA0,0xE1,
+ 0x0C,0x00,0x9D,0xE5,0x40,0x80,0x9D,0xE5,0x3C,0x90,0x9D,0xE5,0x38,0xA0,0x9D,0xE5,
+ 0xAB,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,0x7A,0x00,0x00,0x1A,0x00,0x50,0xA0,0xE3,
+ 0xA4,0x45,0x9F,0xE5,0x01,0x00,0xA0,0xE3,0x00,0x00,0x59,0xE3,0x14,0x10,0x84,0xE2,
+ 0x00,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x21,0x01,0x81,0xE8,0x28,0x10,0x84,0xE2,
+ 0x20,0x50,0x84,0xE5,0x24,0x50,0x84,0xE5,0x21,0x00,0x81,0xE8,0x30,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0x22,0x00,0x00,0x0A,0x0F,0x00,0x58,0xE3,0x34,0x00,0xA0,0x03,0x32,0x00,0xA0,0x13,
+ 0x01,0x00,0x5A,0xE3,0x50,0x15,0x9F,0xE5,0x46,0x00,0xC4,0xE5,0xAB,0x00,0xA0,0x01,
+ 0x48,0x00,0x84,0x05,0x48,0xB0,0x84,0x15,0x0C,0x00,0x9D,0xE5,0x62,0x08,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x5B,0x00,0x00,0x1A,0x14,0x50,0x84,0xE5,0x10,0x90,0x84,0xE5,
+ 0x01,0x30,0xA0,0xE3,0x18,0x50,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x1C,0x50,0x84,0xE5,
+ 0x0F,0x00,0xA0,0xE3,0x20,0x50,0x84,0xE5,0x08,0x10,0xA0,0xE3,0x30,0x30,0x84,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x2C,0x50,0x84,0xE5,0x0C,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,
+ 0x20,0x00,0x00,0x0A,0x01,0x00,0x17,0xE3,0x23,0x00,0x00,0x0A,0x00,0x00,0x57,0xE3,
+ 0x01,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x42,0x00,0x00,0xDA,0x2C,0x00,0x00,0xEA,
+ 0x0F,0x00,0x58,0xE3,0x02,0x00,0xA0,0x13,0x12,0x00,0xA0,0x03,0xDB,0xFF,0xFF,0xEA,
+ 0x07,0x00,0x17,0xE3,0x09,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,0x0C,0x00,0x00,0x0A,
+ 0x01,0x00,0x17,0xE3,0x00,0x00,0xE0,0x13,0x3A,0x00,0x00,0x1A,0x00,0x00,0x57,0xE3,
+ 0x02,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x1F,0x00,0x00,0xCA,0x31,0x00,0x00,0xEA,
+ 0x00,0x00,0x57,0xE3,0x08,0x80,0xA0,0xE3,0x24,0x00,0x84,0xE5,0x1E,0x00,0x00,0xCA,
+ 0x2C,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,
+ 0x17,0x00,0x00,0xCA,0x27,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,
+ 0x24,0x00,0x84,0xE5,0x12,0x00,0x00,0xCA,0x22,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,
+ 0x02,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,0x0B,0x00,0x00,0xCA,0x1D,0x00,0x00,0xEA,
+ 0x01,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x02,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,
+ 0x04,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x08,0x00,0x58,0xE3,0x0A,0x00,0x00,0x1A,
+ 0x05,0x00,0x00,0xEA,0x00,0x00,0xD6,0xE5,0x06,0x00,0x00,0xEA,0xB0,0x00,0xD6,0xE1,
+ 0x04,0x00,0x00,0xEA,0x00,0x00,0x96,0xE5,0x02,0x00,0x00,0xEA,0x00,0x10,0x96,0xE5,
+ 0x5C,0x10,0x84,0xE5,0x04,0x00,0x96,0xE5,0x58,0x00,0x84,0xE5,0x08,0x70,0x47,0xE0,
+ 0x00,0x00,0x57,0xE3,0xF0,0x13,0x9F,0xE5,0x28,0x50,0x84,0xD5,0x08,0x60,0x86,0xE0,
+ 0x0C,0x00,0x9D,0xE5,0x0C,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0x05,0x00,0x00,0x1A,
+ 0x00,0x00,0x57,0xE3,0xE1,0xFF,0xFF,0xCA,0x0C,0x00,0x9D,0xE5,0x09,0x20,0xA0,0xE1,
+ 0x0A,0x10,0xA0,0xE1,0x18,0x01,0x00,0xEB,0x10,0xD0,0x8D,0xE2,0xF0,0x9F,0xBD,0xE8,
+ 0xF0,0x47,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0xAC,0x43,0x9F,0xE5,0x00,0x70,0xA0,0xE3,
+ 0x24,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x20,0x90,0x9D,0xE5,0x02,0x60,0xA0,0xE1,
+ 0x1C,0x20,0x84,0xE2,0x03,0xA0,0xA0,0xE1,0x00,0x70,0x84,0xE5,0x0F,0x00,0x51,0xE3,
+ 0x08,0x70,0x84,0xE5,0x14,0x80,0x84,0xE5,0x18,0x70,0x84,0xE5,0x82,0x00,0x82,0xE8,
+ 0x24,0x20,0x84,0xE2,0x6C,0x10,0xA0,0x03,0x6B,0x10,0xA0,0x13,0x80,0x01,0x82,0xE8,
+ 0x01,0x00,0x59,0xE3,0x2C,0x70,0x84,0xE5,0xA0,0x00,0xA0,0x01,0x30,0x70,0x84,0xE5,
+ 0x46,0x10,0xC4,0xE5,0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x44,0x70,0xC4,0xE5,
+ 0x45,0x10,0xC4,0xE5,0x38,0x70,0x84,0xE5,0x3C,0x70,0x84,0xE5,0x38,0x13,0x9F,0xE5,
+ 0x40,0x70,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,0xDE,0x07,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x02,0x30,0xA0,0xE3,0x10,0xC0,0x84,0xE2,
+ 0x01,0x00,0x59,0xE3,0x0F,0x00,0xA0,0xE3,0x08,0x10,0xA0,0xE3,0x88,0x00,0x8C,0xE8,
+ 0x0C,0x20,0xA0,0xE3,0x18,0x70,0x84,0xE5,0x1C,0x70,0x84,0xE5,0x20,0x70,0x84,0xE5,
+ 0x2C,0x80,0x84,0xE5,0x30,0x70,0x84,0xE5,0x34,0x70,0x84,0xE5,0x04,0x00,0x00,0x0A,
+ 0x04,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,
+ 0x06,0x00,0x00,0xEA,0x08,0x00,0x56,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+ 0x1A,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x87,0xBD,0x18,
+ 0x24,0x10,0x84,0xE5,0x0A,0x00,0xA0,0xE1,0x28,0x70,0x84,0xE5,0xA8,0x12,0x9F,0xE5,
+ 0xBD,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x01,0x00,0x56,0xE3,
+ 0x50,0x00,0xD4,0x05,0x00,0x00,0xC5,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,
+ 0xB0,0x05,0xD4,0x01,0xB0,0x00,0xC5,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+ 0x50,0x00,0x94,0x05,0x00,0x00,0x85,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x56,0xE3,
+ 0x04,0x00,0x00,0x0A,0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,
+ 0x24,0x20,0x84,0xE5,0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x85,0xE5,
+ 0x50,0x00,0x94,0xE5,0x04,0x00,0x85,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,
+ 0xF0,0x5F,0x2D,0xE9,0x01,0x60,0xA0,0xE1,0x2C,0x42,0x9F,0xE5,0x00,0x50,0xA0,0xE3,
+ 0x2C,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x28,0xA0,0x9D,0xE5,0x02,0x70,0xA0,0xE1,
+ 0x1C,0x20,0x84,0xE2,0x0C,0x90,0xA0,0xE3,0x00,0x50,0x84,0xE5,0x0F,0x00,0x51,0xE3,
+ 0x08,0x50,0x84,0xE5,0x03,0xB0,0xA0,0xE1,0x14,0x80,0x84,0xE5,0x18,0x50,0x84,0xE5,
+ 0x22,0x00,0x82,0xE8,0x24,0x20,0x84,0xE2,0x0B,0x10,0xA0,0x13,0x20,0x01,0x82,0xE8,
+ 0x2C,0x50,0x84,0xE5,0x30,0x50,0x84,0xE5,0x46,0x90,0xC4,0x05,0x46,0x10,0xC4,0x15,
+ 0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x44,0x50,0xC4,0xE5,
+ 0xA0,0x00,0xA0,0x01,0x45,0x10,0xC4,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,
+ 0xB4,0x11,0x9F,0xE5,0x40,0x50,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,
+ 0x7D,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x0F,0x00,0xA0,0xE3,
+ 0x01,0x00,0x5A,0xE3,0x08,0x10,0xA0,0xE3,0x10,0x50,0x84,0xE5,0x14,0x50,0x84,0xE5,
+ 0x18,0x50,0x84,0xE5,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x2C,0x80,0x84,0xE5,
+ 0x30,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x04,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,
+ 0x1F,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0x1F,0x00,0x00,0x0A,0x06,0x00,0x00,0xEA,
+ 0x08,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A,
+ 0x02,0x00,0x57,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x9F,0xBD,0x18,0x24,0x10,0x84,0xE5,
+ 0x0B,0x00,0xA0,0xE1,0x28,0x50,0x84,0xE5,0x2C,0x11,0x9F,0xE5,0x5E,0x07,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x01,0x00,0x57,0xE3,0x50,0x00,0xD4,0x05,
+ 0x00,0x00,0xC6,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0xB0,0x05,0xD4,0x01,
+ 0xB0,0x00,0xC6,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x50,0x00,0x94,0x05,
+ 0x00,0x00,0x86,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x57,0xE3,0x04,0x00,0x00,0x0A,
+ 0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,0x24,0x90,0x84,0xE5,
+ 0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x86,0xE5,0x50,0x00,0x94,0xE5,
+ 0x04,0x00,0x86,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x9F,0xBD,0xE8,0xFC,0x5F,0x2D,0xE9,
+ 0x00,0x80,0xA0,0xE1,0x30,0x00,0x8D,0xE2,0x03,0xB0,0xA0,0xE1,0x38,0x90,0x9D,0xE5,
+ 0x02,0x50,0xA0,0xE1,0x40,0x04,0x90,0xE8,0x01,0x70,0xA0,0xE1,0x01,0x00,0x56,0xE3,
+ 0x00,0x00,0xA0,0xE3,0x05,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3,0x0D,0x00,0x00,0x0A,
+ 0x01,0x00,0x15,0xE3,0x01,0x40,0xA0,0x13,0x08,0x00,0x00,0x0A,0x0A,0x00,0x00,0xEA,
+ 0x07,0x00,0x15,0xE3,0x08,0x40,0xA0,0x03,0x07,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3,
+ 0x04,0x00,0x00,0x0A,0x01,0x00,0x15,0xE3,0x00,0x00,0xE0,0x13,0x11,0x00,0x00,0x1A,
+ 0x02,0x40,0xA0,0xE3,0x00,0x00,0x00,0xEA,0x04,0x40,0xA0,0xE3,0x00,0x00,0x55,0xE3,
+ 0x0C,0x00,0x00,0xDA,0x00,0x00,0x5A,0xE3,0x40,0x02,0x8D,0xE8,0x0B,0x30,0xA0,0xE1,
+ 0x04,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0x06,0x00,0x00,0x0A,
+ 0x1A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x04,0x80,0x88,0x00,0x04,0x70,0x87,0x00,
+ 0x04,0x50,0x45,0x00,0xF0,0xFF,0xFF,0x0A,0xFC,0x9F,0xBD,0xE8,0x73,0xFF,0xFF,0xEB,
+ 0xF7,0xFF,0xFF,0xEA,0x14,0x07,0x00,0xEA,0xB1,0x00,0x00,0xEA,0xA4,0x2A,0x02,0x20,
+ 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x64,0x45,0x9F,0xE5,0x03,0x60,0xB0,0xE1,
+ 0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,0x08,0x10,0xA0,0xE3,
+ 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8,
+ 0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x05,0x10,0xA0,0xE3,0x20,0x50,0x84,0xE5,
+ 0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1,
+ 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x00,0x56,0xE3,
+ 0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11,0x21,0x14,0xA0,0x11,
+ 0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8,0xFE,0x40,0x2D,0xE9,
+ 0x02,0x50,0xA0,0xE1,0x01,0x40,0xA0,0xE1,0x00,0x60,0xA0,0xE1,0x04,0x30,0xA0,0xE1,
+ 0x06,0x20,0xA0,0xE1,0x08,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x50,0x8D,0xE5,
+ 0xCE,0xFF,0xFF,0xEB,0x01,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05,0x08,0x20,0xDD,0x05,
+ 0x02,0x10,0x81,0x01,0x03,0x00,0x00,0x0A,0x00,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05,
+ 0x00,0x00,0xE0,0x13,0x01,0x00,0x00,0x1A,0x01,0x00,0x11,0xE3,0xEE,0xFF,0xFF,0x1A,
+ 0xFE,0x80,0xBD,0xE8,0x78,0x14,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+ 0x00,0x20,0x81,0xE5,0x14,0x30,0x81,0xE5,0x06,0x30,0xA0,0xE3,0x18,0x20,0x81,0xE5,
+ 0x1C,0x20,0x81,0xE5,0x20,0x20,0x81,0xE5,0x24,0x20,0x81,0xE5,0x28,0x20,0x81,0xE5,
+ 0x2C,0x20,0x81,0xE5,0x30,0x20,0x81,0xE5,0x46,0x30,0xC1,0xE5,0x34,0x20,0x81,0xE5,
+ 0x38,0x20,0x81,0xE5,0x3C,0x20,0x81,0xE5,0x40,0x20,0x81,0xE5,0xAC,0xFF,0xFF,0xEA,
+ 0xF0,0x41,0x2D,0xE9,0x80,0x00,0x10,0xE3,0x03,0x60,0xA0,0xE1,0x02,0x70,0xA0,0xE1,
+ 0x18,0x80,0x9D,0xE5,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x0A,
+ 0x80,0x40,0xC4,0xE3,0x06,0x20,0xA0,0xE1,0x08,0x30,0xA0,0xE1,0x07,0x10,0xA0,0xE1,
+ 0x04,0x00,0xA0,0xE1,0x7F,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x07,0x00,0xA0,0xE1,0xDA,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x00,0x10,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0C,0x30,0xA0,0xE3,0xD0,0x03,0x9F,0xE5,
+ 0x1C,0xC0,0x80,0xE2,0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5,
+ 0x18,0x10,0x80,0xE5,0x0A,0x00,0x8C,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5,
+ 0x2C,0x10,0x80,0xE5,0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5,
+ 0x4D,0x50,0xC0,0xE5,0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,
+ 0x38,0x10,0x80,0xE5,0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2,
+ 0x07,0x00,0xA0,0xE1,0x7E,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x08,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,
+ 0xA1,0xFF,0xFF,0xEA,0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x50,0x43,0x9F,0xE5,
+ 0x03,0x60,0xB0,0xE1,0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,
+ 0x08,0x10,0xA0,0xE3,0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,
+ 0x21,0x00,0x83,0xE8,0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x35,0x10,0xA0,0xE3,
+ 0x20,0x50,0x84,0xE5,0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5,
+ 0x02,0x00,0xA0,0xE1,0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,
+ 0x5C,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,
+ 0x40,0x50,0x84,0xE5,0x5A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x00,0x00,0x56,0xE3,0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11,
+ 0x21,0x14,0xA0,0x11,0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8,
+ 0x38,0x40,0x2D,0xE9,0x10,0x40,0x9D,0xE5,0x00,0x40,0x8D,0xE5,0x57,0x00,0x00,0xEB,
+ 0x38,0x80,0xBD,0xE8,0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x14,0xD0,0x4D,0xE2,
+ 0x00,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x00,0x30,0x8D,0xE5,
+ 0x02,0x30,0xA0,0xE1,0x01,0x20,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,
+ 0x42,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x1C,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,
+ 0x07,0x20,0xA0,0xE1,0x10,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,
+ 0xBF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x14,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,
+ 0x08,0x00,0xDD,0xE5,0x07,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x01,0x10,0xC0,0xE3,
+ 0x04,0x00,0xDD,0xE5,0x81,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,
+ 0x01,0x00,0x55,0xE3,0x04,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x00,0x40,0x8D,0xE5,0x1C,0x00,0x80,0x13,0x1C,0x00,0xC0,0x03,0x04,0x00,0xCD,0xE5,
+ 0x08,0x00,0xDD,0xE5,0x01,0x10,0x80,0xE3,0x04,0x00,0xDD,0xE5,0x73,0xFF,0xFF,0xEB,
+ 0x14,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0x03,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE1,
+ 0x57,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x10,0xA0,0xE3,
+ 0x01,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,0xC4,0x01,0x9F,0xE5,0x1C,0x80,0x80,0xE2,
+ 0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5,0x18,0x10,0x80,0xE5,
+ 0x0A,0x00,0x88,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5,0x2C,0x10,0x80,0xE5,
+ 0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5,0x4D,0x10,0xC0,0xE5,
+ 0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,0x38,0x10,0x80,0xE5,
+ 0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2,0x07,0x00,0xA0,0xE1,
+ 0xFB,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x05,0x20,0xA0,0xE1,
+ 0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x1E,0xFF,0xFF,0xEA,
+ 0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x1C,0xD0,0x4D,0xE2,0x02,0x50,0xA0,0xE1,
+ 0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x00,0x20,0xA0,0xE1,0x00,0x30,0x8D,0xE5,
+ 0x01,0x30,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0xEB,0xFE,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x1F,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x10,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x68,0xFF,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x17,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x18,0x10,0x8D,0xE2,0x14,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x13,0x00,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x0F,0x00,0x00,0x1A,0x02,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05,
+ 0x02,0x00,0xC0,0x03,0x04,0x00,0x00,0x0A,0x03,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05,
+ 0x02,0x00,0x80,0x03,0x00,0x00,0xE0,0x13,0x06,0x00,0x00,0x1A,0x3F,0x10,0x00,0xE2,
+ 0x08,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x04,0x10,0xCD,0xE5,0x07,0x20,0xA0,0xE1,
+ 0x00,0x40,0x8D,0xE5,0x19,0xFF,0xFF,0xEB,0x1C,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,
+ 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x84,0x40,0x9F,0xE5,0x03,0x80,0xA0,0xE1,
+ 0x00,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x60,0xA0,0xE1,0x08,0x10,0xA0,0xE3,
+ 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8,
+ 0x24,0x30,0x84,0xE2,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x22,0x00,0x83,0xE8,
+ 0x16,0x10,0xA0,0xE3,0x2C,0x00,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1,
+ 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0xA7,0xFE,0xFF,0xEB,0x50,0x10,0xD4,0xE5,0x00,0x00,0x58,0xE3,0x00,0x10,0xC7,0xE5,
+ 0xB0,0x15,0xD4,0x11,0x00,0x50,0xC6,0x05,0x21,0x14,0xA0,0x11,0x00,0x10,0xC6,0x15,
+ 0xF0,0x81,0xBD,0xE8,0xA4,0x2A,0x02,0x20,0x89,0x05,0x00,0xEA,0x9D,0x05,0x00,0xEA,
+ 0x73,0x05,0x00,0xEA,0xF8,0x40,0x2D,0xE9,0x02,0x40,0xA0,0xE1,0x18,0x20,0x8D,0xE2,
+ 0x03,0xC0,0xA0,0xE1,0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x28,0x00,0x92,0xE8,
+ 0x0C,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x2E,0x04,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0x0B,0x00,0x00,0x1A,0x00,0x00,0x54,0xE3,0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,
+ 0x02,0x00,0x54,0xE3,0x03,0x20,0xA0,0x03,0x00,0x00,0xE0,0x13,0x04,0x00,0x00,0x1A,
+ 0x04,0x30,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0x00,0x50,0x8D,0xE5,
+ 0x32,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+ 0x02,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,
+ 0x00,0x00,0x51,0xE3,0x00,0x10,0xA0,0x03,0x01,0x10,0xA0,0x13,0x0B,0x20,0xD4,0xE5,
+ 0xE9,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,0x70,0x80,0xBD,0x18,0x04,0x10,0xA0,0xE1,
+ 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0x9D,0x04,0x00,0xEA,0x01,0x20,0xD1,0xE5,
+ 0x02,0x00,0x52,0xE3,0x0E,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x12,0x00,0x00,0x8A,
+ 0x06,0x00,0xD1,0xE5,0x0F,0x00,0x50,0xE3,0x07,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,
+ 0x0D,0x00,0x00,0x8A,0x08,0x00,0xD1,0xE5,0x07,0x00,0x50,0xE3,0x09,0x00,0xD1,0x95,
+ 0x01,0x00,0x50,0x93,0x08,0x00,0x00,0x8A,0x0A,0x00,0xD1,0xE5,0x02,0x00,0x50,0xE3,
+ 0x0B,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x03,0x00,0x00,0x8A,0x0D,0x00,0xD1,0xE5,
+ 0x03,0x00,0x50,0xE3,0x00,0x00,0xA0,0x93,0x1E,0xFF,0x2F,0x91,0x00,0x00,0xE0,0xE3,
+ 0x1E,0xFF,0x2F,0xE1,0xF8,0x40,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0x02,0x40,0xA0,0xE1,
+ 0x00,0x60,0xA0,0xE1,0x02,0x10,0xA0,0xE1,0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x1B,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0B,0x00,0xD4,0xE5,0x00,0x00,0x8D,0xE5,
+ 0x06,0x00,0xA0,0xE1,0x0D,0x30,0xD4,0xE5,0x0C,0x20,0xD4,0xE5,0xE5,0x03,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x12,0x00,0x00,0x1A,0x0B,0x30,0xD4,0xE5,0x00,0x00,0x53,0xE3,
+ 0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,0x02,0x00,0x53,0xE3,0x03,0x20,0xA0,0x03,
+ 0x00,0x00,0xE0,0x13,0x0A,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0F,0x00,0xD4,0xE5,
+ 0x00,0x00,0x8D,0xE5,0x06,0x00,0xA0,0xE1,0xE8,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x03,0x00,0x00,0x1A,0x04,0x20,0xA0,0xE1,0x05,0x10,0xA0,0xE1,0x06,0x00,0xA0,0xE1,
+ 0xB0,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x52,0x04,0x00,0xEA,0x70,0x40,0x2D,0xE9,
+ 0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x7F,0x06,0x00,0xEB,0x04,0x10,0xA0,0xE1,
+ 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0xB7,0xFF,0xFF,0xEA,0xF7,0x4F,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x92,0x03,0x00,0x8A,
+ 0x00,0x00,0x50,0xE3,0xE5,0x00,0x00,0x0A,0x01,0x3A,0xA0,0xE3,0x3C,0x5E,0x9F,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x38,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x62,0x85,0xE1,
+ 0x06,0x00,0xA0,0xE1,0x32,0xFC,0xFF,0xEB,0x3D,0x7C,0x45,0xE2,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x82,0x87,0xE0,
+ 0x08,0x00,0xA0,0xE1,0x26,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x02,0x93,0x26,0xE0,0x09,0x00,0xA0,0xE1,0x20,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0x1B,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0xA3,0x27,0xE0,0x0A,0x00,0xA0,0xE1,0x15,0xFC,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xB4,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,
+ 0x0F,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0x03,0x88,0xE0,0x0A,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x05,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x00,0xFC,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0xFB,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xF6,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF1,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xEC,0xFB,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0xE7,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xE2,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xDD,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xD8,0xFB,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0xC3,0x01,0x8B,0xE0,
+ 0xD3,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xCE,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xC9,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xC4,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xBF,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xBA,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xB5,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB0,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xAB,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xA6,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xA1,0xFB,0xFF,0xEB,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x39,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x03,0x87,0xE0,0x9C,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x97,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x92,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x8D,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x88,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x83,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x7E,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x79,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x74,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0x6F,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0x6A,0xFB,0xFF,0xEB,0x0F,0x20,0xA0,0xE3,0x02,0x39,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x02,0x04,0x2A,0xE0,0x65,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x60,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x5B,0xFB,0xFF,0xEB,0x02,0x00,0x54,0xE3,0x3B,0x02,0x00,0x0A,0xA9,0x02,0x00,0xEA,
+ 0xAC,0x5A,0x9F,0xE5,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x52,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x63,0x85,0xE1,0x06,0x00,0xA0,0xE1,0x4C,0xFB,0xFF,0xEB,
+ 0x3D,0x7C,0x45,0xE2,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x46,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x83,0x87,0xE0,0x08,0x00,0xA0,0xE1,0x40,0xFB,0xFF,0xEB,
+ 0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x93,0x86,0xE0,
+ 0x09,0x00,0xA0,0xE1,0x3A,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x35,0xFB,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0xA4,0x88,0xE1,0x0A,0x00,0xA0,0xE1,
+ 0x2F,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0xB3,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,0x29,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,
+ 0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x04,0x8B,0xE0,0x24,0xFB,0xFF,0xEB,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x1F,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x1A,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x15,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x10,0xFB,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x0B,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x06,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x01,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xFC,0xFA,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0xF7,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0xF2,0xFA,0xFF,0xEB,0x03,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x04,0x88,0xE0,0xED,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xE8,0xFA,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xE3,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0xDE,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xD9,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xD4,0xFA,0xFF,0xEB,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xCF,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xCA,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xC5,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xC0,0xFA,0xFF,0xEB,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0xBB,0xFA,0xFF,0xEB,0x04,0x20,0xA0,0xE3,0x10,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x02,0x04,0x8B,0xE0,0xB6,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB1,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xAC,0xFA,0xFF,0xEB,
+ 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0xA7,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xA2,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x9D,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+ 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x98,0xFA,0xFF,0xEB,
+ 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x93,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0x8E,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x89,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+ 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x84,0xFA,0xFF,0xEB,
+ 0x05,0x20,0xA0,0xE3,0x20,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x04,0x8A,0xE0,
+ 0x7F,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x7A,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x75,0xFA,0xFF,0xEB,0x02,0x00,0x54,0xE3,
+ 0xC4,0x01,0x00,0x1A,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x6E,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x69,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x64,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x5F,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x5A,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x55,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x50,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x4B,0xFA,0xFF,0xEB,0x06,0x20,0xA0,0xE3,0x40,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x02,0x44,0x88,0xE0,0x04,0x00,0xA0,0xE1,0x45,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x40,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x3B,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x36,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x31,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFA,0xFF,0xEB,
+ 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x27,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x22,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x1D,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x18,0xFA,0xFF,0xEB,
+ 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x13,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x0E,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x09,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x04,0xFA,0xFF,0xEB,
+ 0x08,0x00,0x9D,0xE5,0x01,0x00,0x50,0xE3,0x52,0x01,0x00,0x1A,0x1C,0x40,0x45,0xE2,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0xFB,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x43,0x52,0x84,0xE1,0x05,0x00,0xA0,0xE1,0xF5,0xF9,0xFF,0xEB,0x3D,0x6C,0x44,0xE2,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xEF,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x43,0x72,0x86,0xE0,0x07,0x00,0xA0,0xE1,0xE9,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,
+ 0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x83,0x25,0xE0,0x08,0x00,0xA0,0xE1,
+ 0xE3,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0xDE,0xF9,0xFF,0xEB,0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x94,0x87,0xE1,0x09,0x00,0xA0,0xE1,0xD8,0xF9,0xFF,0xEB,
+ 0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xA4,0x89,0xE0,
+ 0x0A,0x00,0xA0,0xE1,0xD2,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0xB3,0x87,0xE0,0x0B,0x00,0xA0,0xE1,0xCC,0xF9,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xC7,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xC2,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xBD,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xB8,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xB3,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xAE,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xA9,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xA4,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x9F,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0x9A,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x95,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x90,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x8B,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x86,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x81,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x7C,0xF9,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x77,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x72,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x6D,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x68,0xF9,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0x63,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0x5E,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x59,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x54,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0x4F,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x4A,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x45,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x40,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x3B,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x36,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x31,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x2C,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x27,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x22,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6D,0x00,0x00,0xEA,0x01,0x3B,0xA0,0xE3,
+ 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x18,0xF9,0xFF,0xEB,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0x13,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x0E,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x09,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,
+ 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x04,0xF9,0xFF,0xEB,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xFF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xFA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xF5,0xF8,0xFF,0xEB,0x24,0x41,0x9F,0xE5,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0xEF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xEA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xE5,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xE0,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xDB,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xD6,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xD1,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xCC,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xC7,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xC2,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xBD,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xB8,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0xB3,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0xAE,0xF8,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0xFE,0x8F,0xBD,0xE8,
+ 0x20,0x70,0xFE,0xFC,0x24,0x70,0xFE,0xFC,0x20,0x3A,0xFE,0xFC,0xF0,0x41,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x02,0x70,0xA0,0xE1,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,
+ 0x15,0x00,0x00,0x8A,0x54,0x6B,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x01,0x96,0xE7,0x48,0x00,0x80,0xE2,0xB3,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,
+ 0x0D,0x00,0x00,0x1A,0x04,0x01,0x96,0xE7,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0xAD,0xF8,0xFF,0xEB,0x05,0x00,0x50,0xE1,0x14,0x00,0x00,0x0A,0x01,0x00,0x55,0xE3,
+ 0x07,0x00,0x00,0x1A,0x05,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,
+ 0x49,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0xAA,0x00,0x00,0xE0,0xE3,
+ 0xF0,0x81,0xBD,0xE8,0x04,0x01,0x96,0xE7,0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+ 0x05,0x10,0xA0,0xE1,0x8D,0xF8,0xFF,0xEB,0x04,0x01,0x96,0xE7,0x02,0x3C,0xA0,0xE3,
+ 0x09,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0x87,0xF8,0xFF,0xEB,
+ 0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,0xF0,0x47,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+ 0x03,0x70,0xA0,0xE1,0x02,0x80,0xA0,0xE1,0x20,0x60,0x9D,0xE5,0x01,0x90,0xA0,0xE1,
+ 0x00,0x40,0xA0,0xE1,0x71,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,
+ 0x2D,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x6C,0x00,0x00,0xBA,0x01,0x20,0xA0,0xE3,
+ 0x88,0x5A,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,
+ 0x81,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x64,0x00,0x00,0x1A,0x04,0x01,0x95,0xE7,
+ 0x03,0x35,0xA0,0xE3,0x16,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x6B,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x03,0x36,0xA0,0xE3,0x14,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+ 0x66,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x37,0xA0,0xE3,0x12,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE3,0x61,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x38,0xA0,0xE3,
+ 0x10,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x5C,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x57,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x03,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+ 0x52,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE3,0x4D,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x34,0xA0,0xE3,
+ 0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x3E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x39,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x34,0xF8,0xFF,0xEB,0x06,0x20,0xA0,0xE1,
+ 0x09,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,0x7F,0xFF,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x07,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,
+ 0x2A,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x07,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,0x24,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x00,0x20,0xA0,0xE3,0x07,0x30,0xA0,0xE3,0x02,0x10,0xA0,0xE1,0x04,0x00,0x80,0xE2,
+ 0x1E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x08,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,0x18,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x07,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,
+ 0x12,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x48,0x00,0x80,0xE2,0x1C,0xF8,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,
+ 0x00,0x00,0xE0,0xE3,0xF0,0x87,0xBD,0xE8,0x04,0x11,0x95,0xE7,0x08,0x05,0x0A,0xE3,
+ 0x50,0x00,0x81,0xE5,0x04,0x11,0x95,0xE7,0xC4,0x08,0x9F,0xE5,0x68,0x00,0x81,0xE5,
+ 0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0xA8,0x58,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x48,0x00,0x80,0xE2,0x08,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x01,0x60,0xA0,0xE1,
+ 0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE3,0x6C,0x58,0x9F,0xE5,
+ 0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,0xFA,0xF7,0xFF,0xEB,
+ 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0x70,0x80,0xBD,0xE8,
+ 0x04,0x01,0x95,0xE7,0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0xE2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x0F,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0xDC,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,
+ 0xD6,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE1,0x0C,0x00,0x80,0xE2,0xD0,0xF7,0xFF,0xEB,0x00,0x10,0xD6,0xE5,
+ 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x00,0x80,0xE2,
+ 0xCA,0xF7,0xFF,0xEB,0x01,0x10,0xD6,0xE5,0x03,0x31,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x1E,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xC4,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xBE,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0xFF,0x30,0xA0,0xE3,
+ 0x02,0x10,0xA0,0xE1,0x10,0x00,0x80,0xE2,0xB8,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x32,0xA0,0xE3,0x1C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xB2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xAC,0xF7,0xFF,0xEB,0x0E,0x10,0xD6,0xE5,
+ 0x03,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x18,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xA6,0xF7,0xFF,0xEB,0x0F,0x10,0xD6,0xE5,0x0F,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x08,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xA0,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0xFF,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x14,0x00,0x80,0xE2,
+ 0x9A,0xF7,0xFF,0xEB,0x02,0x10,0xD6,0xE5,0xFF,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x18,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x94,0xF7,0xFF,0xEB,0x03,0x10,0xD6,0xE5,
+ 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+ 0x8E,0xF7,0xFF,0xEB,0x04,0x10,0xD6,0xE5,0xFF,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x08,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x88,0xF7,0xFF,0xEB,0x05,0x10,0xD6,0xE5,
+ 0xFF,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+ 0x82,0xF7,0xFF,0xEB,0x07,0x10,0xD6,0xE5,0x03,0x36,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x14,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x7C,0xF7,0xFF,0xEB,0x06,0x10,0xD6,0xE5,
+ 0xF0,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x04,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0x76,0xF7,0xFF,0xEB,0x0B,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x10,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x70,0xF7,0xFF,0xEB,0x09,0x10,0xD6,0xE5,
+ 0x02,0x39,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x0F,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0x6A,0xF7,0xFF,0xEB,0x0A,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x10,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,0x64,0xF7,0xFF,0xEB,0x08,0x10,0xD6,0xE5,
+ 0x07,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,
+ 0x5E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,0x58,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,
+ 0x52,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+ 0x02,0x10,0xA0,0xE1,0x5C,0x00,0x80,0xE2,0x4C,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x00,0x40,0xA0,0xE1,
+ 0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,0x01,0x34,0xA0,0xE3,0x18,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0xB4,0x55,0x9F,0xE5,0x04,0x01,0x95,0xE7,0x0C,0x00,0x80,0xE2,
+ 0x3E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x48,0x00,0x80,0xE2,0x48,0xF7,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,0x7C,0x55,0x9F,0xE5,
+ 0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x3E,0xF7,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,0xE0,0xFF,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,0x02,0x31,0xA0,0xE3,
+ 0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x23,0xF7,0xFF,0xEB,
+ 0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0x28,0x55,0x9F,0xE5,0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x29,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,
+ 0xCB,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,
+ 0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x0E,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x19,0x00,0x00,0x8A,
+ 0x02,0x21,0xA0,0xE3,0xC4,0x64,0x9F,0xE5,0x1F,0x10,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+ 0x11,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0x0A,0xF7,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,0x05,0x01,0x96,0xE7,0x02,0x31,0xA0,0xE3,
+ 0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0xF4,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0xFE,0xF6,0xFF,0xEB,
+ 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0xF0,0x81,0xBD,0xE8,
+ 0x05,0x01,0x96,0xE7,0x01,0x39,0xA0,0xE3,0x14,0x10,0x94,0xE5,0x0E,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0xE5,0xF6,0xFF,0xEB,0x14,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,
+ 0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x46,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+ 0x24,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,0xDC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x03,0x31,0xA0,0xE3,0x00,0x10,0x94,0xE5,0x1E,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0xD6,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3A,0xA0,0xE3,0x18,0x10,0x94,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xD0,0xF6,0xFF,0xEB,0x18,0x00,0x94,0xE5,
+ 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x47,0x10,0xD4,0xE5,
+ 0xFF,0x30,0xA0,0xE3,0x24,0x00,0x80,0xE2,0x00,0x20,0xA0,0xE3,0xC7,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x03,0x32,0xA0,0xE3,0x04,0x10,0x94,0xE5,0x1C,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0xC1,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x0F,0x3C,0xA0,0xE3,
+ 0x1C,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xBB,0xF6,0xFF,0xEB,
+ 0x1C,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x48,0x10,0x94,0xE5,0x00,0x30,0xE0,0xE3,0x00,0x20,0xA0,0xE3,0x28,0x00,0x80,0xE2,
+ 0xB2,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x03,0x34,0xA0,0xE3,0x08,0x10,0x94,0xE5,
+ 0x18,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xAC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0xF0,0x30,0xA0,0xE3,0x20,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0xA6,0xF6,0xFF,0xEB,0x20,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x1D,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0x4C,0x10,0xD4,0xE5,0xFF,0x34,0xA0,0xE3,0x2C,0x00,0x80,0xE2,
+ 0x18,0x20,0xA0,0xE3,0x9D,0xF6,0xFF,0xEB,0x4D,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+ 0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x97,0xF6,0xFF,0xEB,
+ 0x4E,0x10,0xD4,0xE5,0xFF,0x3C,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x08,0x20,0xA0,0xE3,
+ 0x2C,0x00,0x80,0xE2,0x91,0xF6,0xFF,0xEB,0x4F,0x10,0xD4,0xE5,0xFF,0x30,0xA0,0xE3,
+ 0x05,0x01,0x96,0xE7,0x00,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x8B,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x03,0x36,0xA0,0xE3,0x0C,0x10,0x94,0xE5,0x14,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0x85,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x02,0x39,0xA0,0xE3,
+ 0x34,0x10,0x94,0xE5,0x0F,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0x7F,0xF6,0xFF,0xEB,
+ 0x34,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x44,0x10,0xD4,0xE5,0x03,0x38,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,
+ 0x76,0xF6,0xFF,0xEB,0x45,0x10,0xD4,0xE5,0x07,0x30,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+ 0x00,0x20,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x70,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x0F,0x30,0xA0,0xE3,0x24,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0x6A,0xF6,0xFF,0xEB,0x24,0x00,0x94,0xE5,0x58,0x72,0x9F,0xE5,0x00,0x00,0x50,0xE3,
+ 0x2C,0x00,0x00,0x0A,0x08,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+ 0x0C,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x14,0x00,0x00,0x0A,0x1F,0x00,0x00,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6A,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x58,0x00,0xD4,0x05,0x05,0x11,0x96,0x07,0x40,0x00,0xC1,0x05,
+ 0x06,0x00,0x00,0x1A,0x15,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x60,0xF6,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x53,0x00,0x00,0x1A,
+ 0x05,0x11,0x96,0xE7,0xB8,0x05,0xD4,0xE1,0xB0,0x04,0xC1,0xE1,0x0B,0x00,0x00,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x56,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x49,0x00,0x00,0x0A,0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,
+ 0x40,0x00,0x81,0xE5,0x05,0x01,0x96,0xE7,0x5C,0x10,0x94,0xE5,0x44,0x10,0x80,0xE5,
+ 0x03,0x38,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x10,0x94,0xE5,
+ 0x30,0x00,0x80,0xE2,0x39,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+ 0x28,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x33,0xF6,0xFF,0xEB,
+ 0x10,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x24,0x00,0x94,0x15,0x00,0x00,0x50,0x13,
+ 0x04,0x00,0x00,0x0A,0x2C,0x00,0x94,0xE5,0x01,0x00,0x50,0xE3,0x30,0x00,0x94,0x05,
+ 0x01,0x00,0x50,0x03,0x3B,0xFF,0xFF,0x0A,0x05,0x01,0x96,0xE7,0x2C,0x10,0x94,0xE5,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x23,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x02,0x30,0xA0,0xE3,0x30,0x10,0x94,0xE5,0x01,0x20,0xA0,0xE3,
+ 0x20,0x00,0x80,0xE2,0x1D,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+ 0x38,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x17,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x10,0x30,0xA0,0xE3,0x3C,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,
+ 0x64,0x00,0x80,0xE2,0x11,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,
+ 0x40,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x0B,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE1,
+ 0x20,0x00,0x80,0xE2,0x05,0xF6,0xFF,0xEB,0x05,0x00,0xA0,0xE1,0xAD,0xF9,0xFF,0xEB,
+ 0x24,0x00,0x94,0xE5,0x08,0x00,0x50,0xE3,0x08,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+ 0x11,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x16,0x00,0x00,0x0A,0x21,0x00,0x00,0xEA,
+ 0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,0x40,0x00,0x81,0xE5,0xB7,0xFF,0xFF,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x02,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x05,0x01,0x96,0x07,0x38,0x00,0xD0,0x05,0x19,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0xB8,0x03,0xD0,0xE1,0x16,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF7,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x0E,0x00,0x00,0x1A,0xF5,0xFF,0xFF,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xF0,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x07,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0x05,0x01,0x96,0xE7,
+ 0x3C,0x00,0x90,0xE5,0x54,0x00,0x84,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,
+ 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0xF9,0xFF,0xFF,0xEA,
+ 0x8C,0x2A,0x02,0x20,0x63,0x63,0x00,0xA5,0x00,0xA0,0xEF,0x3F,0xF0,0x40,0x2D,0xE9,
+ 0xEB,0xC0,0xA0,0xE3,0x00,0xC0,0xC1,0xE5,0x08,0x70,0xA0,0xE3,0x06,0x70,0xC1,0xE5,
+ 0x03,0x60,0xA0,0xE3,0x08,0x60,0xC1,0xE5,0x55,0x50,0xA0,0xE3,0x02,0x50,0xC1,0xE5,
+ 0x01,0x40,0xA0,0xE3,0x09,0x40,0xC1,0xE5,0x02,0x30,0xA0,0xE3,0x0E,0x30,0xC1,0xE5,
+ 0x00,0x20,0xA0,0xE3,0x07,0x30,0xC1,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x30,0xC1,0xE5,
+ 0x07,0x00,0xA0,0xE3,0x01,0x20,0xC1,0xE5,0x03,0x20,0xC1,0xE5,0x04,0x20,0xC1,0xE5,
+ 0x05,0x20,0xC1,0xE5,0x0A,0x20,0xC1,0xE5,0x0C,0x40,0xC1,0x05,0x0C,0x30,0xC1,0x15,
+ 0x0D,0x20,0xC1,0xE5,0x0F,0x00,0xC1,0xE5,0xF0,0x80,0xBD,0xE8,0x00,0xA0,0xEF,0x3F,
+ 0x00,0xB0,0xEF,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x5C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5,
+ 0x50,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+ 0x44,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+ 0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3,
+ 0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x26,0x00,0x00,0xEB,0x1C,0xD0,0x9F,0xE5,
+ 0x14,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB,0x0F,0x00,0x00,0xEB,
+ 0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x14,0x00,0xFE,0xFC,
+ 0x00,0x00,0x03,0x20,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+ 0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+ 0x04,0xF0,0x1F,0xE5,0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20,
+ 0x04,0xF0,0x1F,0xE5,0x04,0x02,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,
+ 0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,
+ 0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,
+ 0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,0x10,0x80,0xBD,0xE8,0xAF,0x01,0x00,0x00,
+ 0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,
+ 0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
+#if defined (__CC_ARM)
+#pragma arm section
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
new file mode 100644
index 000000000..16c0cc0c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file mmu_Renesas_RZ_A1.c
+ * @brief MMU Startup File for
+ * mmu_Renesas_RZ_A1 Device Series
+ * @version V1.01
+ * @date 2 Aug 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
+//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+#include <stdint.h>
+#include "MBRZA1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$ZI_DATA$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void create_translation_table(void)
+{
+ mmu_region_attributes_Type region;
+
+ /*
+ * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ section_normal_nc(Sect_Normal_NC, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Create 4GB of faulting entries
+ __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ // R7S72100 memory map.
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
+
+ //Define Image
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#if defined( __CC_ARM )
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
+#else
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c
new file mode 100644
index 000000000..6a09dcf06
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c
@@ -0,0 +1,229 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file nvic_wrapper.c
+* $Rev: $
+* $Date:: $
+* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "wdt_iodefine.h"
+#include "nvic_wrapper.h"
+#include "gic.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */
+#define WDT_WTCNT_WRITE (0x5A00)
+#define WDT_WTCSR_WRITE (0xA500)
+#define WDT_WRCSR_WOVF_WRITE (0xA500)
+#define WDT_WRCSR_RSTE_WRITE (0x5A00)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+
+/* ########################## NVIC functions #################################### */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ GIC_SetBinaryPoint(PriorityGroup);
+}
+
+
+uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return GIC_GetBinaryPoint(0);
+}
+
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GIC_EnableIRQ(IRQn);
+}
+
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GIC_DisableIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ uint32_t pending;
+
+ pending = GIC_GetIRQStatus(IRQn);
+ pending = (pending & 0x00000001);
+
+ return pending;
+}
+
+
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ GIC_SetPendingIRQ(IRQn);
+}
+
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ GIC_ClearPendingIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ uint32_t active;
+
+ active = GIC_GetIRQStatus(IRQn);
+ active = ((active >> 1) & 0x00000001);
+
+ return active;
+}
+
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ GIC_SetPriority(IRQn, (priority << 3));
+}
+
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+ uint32_t priority_field;
+
+ priority_field = GIC_GetPriority(IRQn);
+ priority_field = (priority_field >> 3);
+ return priority_field;
+}
+
+
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+void NVIC_SystemReset(void)
+{
+ uint16_t reg;
+ uint8_t dummy_read;
+ /* Use Watch Dog Timer to system reset */
+
+ /* Set WT/IT bit of WTCSR to 1 = Watch Dog */
+ /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
+ reg = (WDT_WTCSR_WRITE | 0x0058);
+ WDTWTCSR = reg;
+
+ /* Clear Count reg */
+ reg = (WDT_WTCNT_WRITE | 0x0000);
+ WDTWTCNT = reg;
+
+ /* Clear WOVF flag */
+ dummy_read = WDTWRCSR;
+ reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
+ WDTWRCSR = reg;
+ /* Enable Internal Reset */
+ reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
+ WDTWRCSR = reg;
+
+ /* Watch Dog start */
+ reg = (WDT_WTCSR_WRITE | 0x0078);
+ WDTWTCSR = reg;
+
+ while(1); /* wait Internal Reset */
+}
+
+/* ################################## SysTick function ############################################ */
+uint32_t SysTick_Config(uint32_t ticks)
+{
+ /* Not support this function */
+ /* Use mbed Ticker */
+ return (1); /* impossible */
+}
+
+
+/* ##################################### Debug In/Output function ########################################### */
+uint32_t ITM_SendChar (uint32_t ch)
+{
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (ch);
+}
+
+
+int32_t ITM_ReceiveChar (void) {
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (-1); /* no character available */
+}
+
+
+int32_t ITM_CheckChar (void) {
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (0); /* no character available */
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h
new file mode 100644
index 000000000..fcdf554bb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file nvic_wrapper.h
+* $Rev: $
+* $Date:: $
+* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+#ifndef NVIC_WRAPPER_H
+#define NVIC_WRAPPER_H
+
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* NVIC functions */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t NVIC_GetPriorityGrouping(void);
+void NVIC_EnableIRQ(IRQn_Type IRQn);
+void NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetActive(IRQn_Type IRQn);
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+void NVIC_SystemReset(void);
+/* SysTick function */
+uint32_t SysTick_Config(uint32_t ticks);
+/* Debug In/Output function */
+uint32_t ITM_SendChar (uint32_t ch);
+int32_t ITM_ReceiveChar (void);
+int32_t ITM_CheckChar (void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NVIC_WRAPPER_H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c
new file mode 100644
index 000000000..9e67970b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c
@@ -0,0 +1,128 @@
+/**************************************************************************//**
+ * @file pl310.c
+ * @brief Implementation of pl310 functions
+ * @version
+ * @date 11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+#include "MBRZA1H.h"
+
+//Cache Sync operation
+void PL310_Sync(void)
+{
+ PL310->CACHE_SYNC = 0x0;
+}
+
+//return Cache controller cache ID
+int PL310_GetID (void)
+{
+ return PL310->CACHE_ID;
+}
+
+//return Cache controller cache Type
+int PL310_GetType (void)
+{
+ return PL310->CACHE_TYPE;
+}
+
+//Invalidate all cache by way
+void PL310_InvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (PL310->AUX_CNT & (1<<16))
+ assoc = 16;
+ else
+ assoc = 8;
+
+ PL310->INV_WAY = (1 << assoc) - 1;
+ while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+ PL310_Sync();
+}
+
+//Clean and Invalidate all cache by way
+void PL310_CleanInvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (PL310->AUX_CNT & (1<<16))
+ assoc = 16;
+ else
+ assoc = 8;
+
+ PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
+ while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate
+
+ PL310_Sync();
+}
+
+//Enable Cache
+void PL310_Enable(void)
+{
+ PL310->CONTROL = 0;
+ PL310->INTERRUPT_CLEAR = 0x000001FFuL;
+ PL310->DEBUG_CONTROL = 0;
+ PL310->DATA_LOCK_0_WAY = 0;
+ PL310->CACHE_SYNC = 0;
+
+ PL310->CONTROL = 0x01;
+ PL310_Sync();
+}
+//Disable Cache
+void PL310_Disable(void)
+{
+ PL310->CONTROL = 0x00;
+ PL310_Sync();
+}
+
+//Invalidate cache by physical address
+void PL310_InvPa (void *pa)
+{
+ PL310->INV_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+//Clean cache by physical address
+void PL310_CleanPa (void *pa)
+{
+ PL310->CLEAN_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+//Clean and invalidate cache by physical address
+void PL310_CleanInvPa (void *pa)
+{
+ PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h
new file mode 100644
index 000000000..0960a4d1f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file pl310.h
+ * @brief Implementation of pl310 functions
+ * @version
+ * @date 11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#ifndef __PL310
+#define __PL310
+
+typedef struct
+{
+ __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
+ __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
+ uint32_t RESERVED0[0x3e];
+ __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
+ __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
+ uint32_t RESERVED1[0x3e];
+ __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
+ __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
+ __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
+ uint32_t RESERVED2[0x2];
+ __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
+ __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
+ __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
+ __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
+ uint32_t RESERVED3[0x143];
+ __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
+ uint32_t RESERVED4[0xf];
+ __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
+ uint32_t RESERVED6[2];
+ __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
+ uint32_t RESERVED5[0xc];
+ __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
+ uint32_t RESERVED7[1];
+ __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
+ __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
+ uint32_t RESERVED8[0xc];
+ __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
+ uint32_t RESERVED9[1];
+ __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
+ __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
+ uint32_t RESERVED10[0x40];
+ __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
+ __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
+ __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
+ __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
+ __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
+ __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
+ __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
+ __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
+ __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
+ __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
+ __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
+ __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
+ __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
+ __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
+ __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
+ __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
+ uint32_t RESERVED11[0x4];
+ __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
+ __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
+ uint32_t RESERVED12[0xaa];
+ __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
+ __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
+ uint32_t RESERVED13[0xce];
+ __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
+
+} PL310_TypeDef;
+
+#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
+
+extern int PL310_GetID (void);
+extern int PL310_GetType (void);
+extern void PL310_InvAllByWay (void);
+extern void PL310_CleanInvAllByWay(void);
+extern void PL310_Enable(void);
+extern void PL310_Disable(void);
+extern void PL310_InvPa (void *);
+extern void PL310_CleanPa (void *);
+extern void PL310_CleanInvPa (void *);
+
+#endif
+
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h
new file mode 100644
index 000000000..188c22218
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : r_typedefs.h
+* $Rev: 788 $
+* $Date:: 2014-04-07 18:57:13 +0900#$
+* Description : basic type definition
+******************************************************************************/
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#if defined(__ARM_NEON__)
+
+#include <arm_neon.h>
+
+#else /* __ARM_NEON__ */
+
+typedef float float32_t;
+typedef double float64_t;
+
+#endif /* __ARM_NEON__ */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef char char_t;
+typedef int bool_t;
+typedef int int_t;
+typedef long double float128_t;
+typedef signed long long_t;
+typedef unsigned long ulong_t;
+
+#endif /* R_TYPEDEFS_H */
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c
new file mode 100644
index 000000000..f919fa8c8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c
@@ -0,0 +1,200 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rza_io_regrw.c
+* $Rev: 1121 $
+* $Date:: 2014-08-06 17:09:53 +0900#$
+* Description : Low level register read/write
+*******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_IO_REGRW"
+#pragma arm section rodata = "CONST_IO_REGRW"
+#pragma arm section rwdata = "DATA_IO_REGRW"
+#pragma arm section zidata = "BSS_IO_REGRW"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_8
+* Description : IO register 8-bit write
+* Arguments : volatile uint8_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint8_t write_value : Write value for the IO register
+* : uint8_t shift : The number of left shifts to the
+* : : target bit
+* : uint8_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask)
+{
+ uint8_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_16
+* Description : IO register 16-bit write
+* Arguments : volatile uint16_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint16_t write_value : Write value for the IO register
+* : uint16_t shift : The number of left shifts to the
+* : : target bit
+* : uint16_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask)
+{
+ uint16_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_32
+* Description : IO register 32-bit write
+* Arguments : volatile uint32_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint32_t write_value : Write value for the IO register
+* : uint32_t shift : The number of left shifts to the
+* : : target bit
+* : uint32_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
+{
+ uint32_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_8
+* Description : IO register 8-bit read
+* Arguments : volatile uint8_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint8_t shift : The number of right shifts to the
+* : : target bit
+* : uint8_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint8_t : Value of the obtained target bit
+******************************************************************************/
+uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask)
+{
+ uint8_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_16
+* Description : IO register 16-bit read
+* Arguments : volatile uint16_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint16_t shift : The number of right shifts to the
+* : : target bit
+* : uint16_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint16_t : Value of the obtained target bit
+******************************************************************************/
+uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask)
+{
+ uint16_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_32
+* Description : IO register 32-bit read
+* Arguments : volatile uint32_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint32_t shift : The number of right shifts to the
+* : : target bit
+* : uint32_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint32_t : Value of the obtained target bit
+******************************************************************************/
+uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
+{
+ uint32_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+
+/* End of File */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
new file mode 100644
index 000000000..3a37c602c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
@@ -0,0 +1,384 @@
+/**************************************************************************//**
+ * @file system_MBRZA1H.c
+ * @brief CMSIS Device System Source File for
+ * ARMCA9 Device Series
+ * @version V1.00
+ * @date 19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "MBRZA1H.h"
+#include "RZ_A1_Init.h"
+
+
+#if defined(__ARMCC_VERSION)
+extern void $Super$$main(void);
+__asm void FPUEnable(void);
+#else
+void FPUEnable(void);
+
+#endif
+
+uint32_t IRQNestLevel;
+
+
+#if defined(__ARMCC_VERSION)
+/**
+ * Initialize the cache.
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
+ */
+#pragma push
+#pragma arm
+
+void InitMemorySubsystem(void) {
+
+ /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+ * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+ * You are not required to invalidate the main TLB, even though it is recommended for safety
+ * reasons. This ensures compatibility with future revisions of the processor. */
+
+ unsigned int l2_id;
+
+ /* Invalidate undefined data */
+ __ca9u_inv_tlb_all();
+ __v7_inv_icache_all();
+ __v7_inv_dcache_all();
+ __v7_inv_btac();
+
+ /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+ * invalidate in order to flush the valid data to the next level cache.
+ */
+ __enable_mmu();
+
+ /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+ __enable_caches();
+ __enable_btac();
+
+ /* If present, you may also need to Invalidate and Enable L2 cache here */
+ l2_id = PL310_GetID();
+ if (l2_id)
+ {
+ PL310_InvAllByWay();
+ PL310_Enable();
+ }
+}
+#pragma pop
+
+#elif defined(__GNUC__)
+
+void InitMemorySubsystem(void) {
+
+ /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+ * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+ * You are not required to invalidate the main TLB, even though it is recommended for safety
+ * reasons. This ensures compatibility with future revisions of the processor. */
+
+ unsigned int l2_id;
+
+ /* Invalidate undefined data */
+ __ca9u_inv_tlb_all();
+ __v7_inv_icache_all();
+ __v7_inv_dcache_all();
+ __v7_inv_btac();
+
+ /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+ * invalidate in order to flush the valid data to the next level cache.
+ */
+ __enable_mmu();
+
+ /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+ __enable_caches();
+ __enable_btac();
+
+ /* If present, you may also need to Invalidate and Enable L2 cache here */
+ l2_id = PL310_GetID();
+ if (l2_id)
+ {
+ PL310_InvAllByWay();
+ PL310_Enable();
+ }
+}
+#else
+
+#endif
+
+
+IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+uint32_t IRQCount = sizeof IRQTable / 4;
+
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = handler;
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = 0;
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ IRQNestLevel = 0;
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section maybe overwritten afterwards. */
+ RZ_A1_InitClock();
+ RZ_A1_InitBus();
+
+ //Configure GIC ICDICFR GIC_SetICDICFR()
+ GIC_Enable();
+ __enable_irq();
+
+}
+
+
+//Fault Status Register (IFSR/DFSR) definitions
+#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
+#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
+#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
+#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
+#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
+#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
+#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
+#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
+#define FSR_DEBUG_EVENT 0x02 //internal
+#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
+#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
+#define FSR_LOCKDOWN 0x14 //internal
+#define FSR_COPROCESSOR_ABORT 0x1a //internal
+#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
+#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
+#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
+
+void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
+ uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in DFAR is invalid for some fault statuses.
+ case FSR_ALIGNMENT_FAULT:
+ case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISION_FAULT_FIRST:
+ case FSR_PERMISION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT:
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
+ case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
+ default:
+ while(1);
+ }
+}
+
+void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
+ uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in IFAR is invalid for some fault statuses.
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISION_FAULT_FIRST:
+ case FSR_PERMISION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT: //IFAR invalid
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ default:
+ while(1);
+ }
+}
+
+//returns amount to decrement lr by
+//this will be 0 when we have emulated the instruction and simply want to execute the next instruction
+//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
+uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
+ const unsigned int THUMB = 2;
+ const unsigned int ARM = 4;
+ //Lazy VFP/NEON initialisation and switching
+ if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
+ (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
+ if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
+ FPUEnable();
+ return state;
+ }
+ }
+
+ //Add code here for other Undef cases
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION)
+#pragma push
+#pragma arm
+//Critical section, called from undef handler, so systick is disabled
+__asm void FPUEnable(void) {
+ ARM
+
+ //Permit access to VFP registers by modifying CPACR
+ MRC p15,0,R1,c1,c0,2
+ ORR R1,R1,#0x00F00000
+ MCR p15,0,R1,c1,c0,2
+
+ //Enable VFP
+ VMRS R1,FPEXC
+ ORR R1,R1,#0x40000000
+ VMSR FPEXC,R1
+
+ //Initialise VFP registers to 0
+ MOV R2,#0
+ VMOV D0, R2,R2
+ VMOV D1, R2,R2
+ VMOV D2, R2,R2
+ VMOV D3, R2,R2
+ VMOV D4, R2,R2
+ VMOV D5, R2,R2
+ VMOV D6, R2,R2
+ VMOV D7, R2,R2
+ VMOV D8, R2,R2
+ VMOV D9, R2,R2
+ VMOV D10,R2,R2
+ VMOV D11,R2,R2
+ VMOV D12,R2,R2
+ VMOV D13,R2,R2
+ VMOV D14,R2,R2
+ VMOV D15,R2,R2
+
+ //Initialise FPSCR to a known state
+ VMRS R2,FPSCR
+ LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R2,R2,R3
+ VMSR FPSCR,R2
+
+ BX LR
+}
+#pragma pop
+
+#elif defined(__GNUC__)
+void FPUEnable(void)
+{
+ __asm__ __volatile__ (
+ ".align 2 \n\t"
+ ".arm \n\t"
+ "mrc p15,0,r1,c1,c0,2 \n\t"
+ "orr r1,r1,#0x00f00000 \n\t"
+ "mcr p15,0,r1,c1,c0,2 \n\t"
+ "vmrs r1,fpexc \n\t"
+ "orr r1,r1,#0x40000000 \n\t"
+ "vmsr fpexc,r1 \n\t"
+ "mov r2,#0 \n\t"
+ "vmov d0, r2,r2 \n\t"
+ "vmov d1, r2,r2 \n\t"
+ "vmov d2, r2,r2 \n\t"
+ "vmov d3, r2,r2 \n\t"
+ "vmov d4, r2,r2 \n\t"
+ "vmov d5, r2,r2 \n\t"
+ "vmov d6, r2,r2 \n\t"
+ "vmov d7, r2,r2 \n\t"
+ "vmov d8, r2,r2 \n\t"
+ "vmov d9, r2,r2 \n\t"
+ "vmov d10,r2,r2 \n\t"
+ "vmov d11,r2,r2 \n\t"
+ "vmov d12,r2,r2 \n\t"
+ "vmov d13,r2,r2 \n\t"
+ "vmov d14,r2,r2 \n\t"
+ "vmov d15,r2,r2 \n\t"
+ "vmrs r2,fpscr \n\t"
+ "ldr r3,=0x00086060 \n\t"
+ "and r2,r2,r3 \n\t"
+ "vmsr fpscr,r2 \n\t"
+ "bx lr \n\t"
+ );
+}
+#else
+#endif
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h
new file mode 100644
index 000000000..832e58bb9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file system_MBRZA1H.h
+ * @brief CMSIS Device System Header File for
+ * ARMCA9 Device Series
+ * @version V1.00
+ * @date 11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __SYSTEM_MBRZA1H
+#define __SYSTEM_MBRZA1H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void(*IRQHandler)();
+uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the Systd short int16_t;emCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_MBRZA1H */
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
new file mode 100644
index 000000000..2b50515c1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
@@ -0,0 +1,846 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv="Content-Type" content="text/html; charset=windows-1252"><link rel="File-List" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/filelist.xml"><link rel="Edit-Time-Data" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/editdata.mso"><title>Release Notes for STM32F0xx HAL Drivers</title><link rel="themeData" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/themedata.thmx"><link rel="colorSchemeMapping" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/colorschememapping.xml"><style>
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+/* Font Definitions */
+@font-face
+{font-family:"Cambria Math";
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+mso-font-pitch:variable;
+mso-font-signature:1627400839 -2147483648 8 0 66047 0;}
+@font-face
+{font-family:Verdana;
+panose-1:2 11 6 4 3 5 4 4 2 4;
+mso-font-charset:0;
+mso-generic-font-family:swiss;
+mso-font-pitch:variable;
+mso-font-signature:536871559 0 0 0 415 0;}
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+h1
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 1 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:1;
+font-size:24.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+h2
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 2 Char";
+mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:"Arial","sans-serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;
+font-style:italic;}
+h3
+{mso-style-unhide:no;
+mso-style-qformat:yes;
+mso-style-link:"Heading 3 Char";
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+mso-outline-level:3;
+font-size:13.5pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:minor-fareast;
+font-weight:bold;}
+a:link, span.MsoHyperlink
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{mso-style-unhide:no;
+color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-style-unhide:no;
+mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman","serif";
+mso-fareast-font-family:"Times New Roman";}
+p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
+{mso-style-unhide:no;
+mso-style-link:"Balloon Text Char";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-fareast-font-family:"Times New Roman";}
+span.Heading1Char
+{mso-style-name:"Heading 1 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 1";
+mso-ansi-font-size:14.0pt;
+mso-bidi-font-size:14.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#365F91;
+mso-themecolor:accent1;
+mso-themeshade:191;
+font-weight:bold;}
+span.Heading2Char
+{mso-style-name:"Heading 2 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 2";
+mso-ansi-font-size:13.0pt;
+mso-bidi-font-size:13.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.Heading3Char
+{mso-style-name:"Heading 3 Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Heading 3";
+mso-ansi-font-size:12.0pt;
+mso-bidi-font-size:12.0pt;
+font-family:"Cambria","serif";
+mso-ascii-font-family:Cambria;
+mso-ascii-theme-font:major-latin;
+mso-fareast-font-family:"Times New Roman";
+mso-fareast-theme-font:major-fareast;
+mso-hansi-font-family:Cambria;
+mso-hansi-theme-font:major-latin;
+mso-bidi-font-family:"Times New Roman";
+mso-bidi-theme-font:major-bidi;
+color:#4F81BD;
+mso-themecolor:accent1;
+font-weight:bold;}
+span.BalloonTextChar
+{mso-style-name:"Balloon Text Char";
+mso-style-unhide:no;
+mso-style-locked:yes;
+mso-style-link:"Balloon Text";
+mso-ansi-font-size:8.0pt;
+mso-bidi-font-size:8.0pt;
+font-family:"Tahoma","sans-serif";
+mso-ascii-font-family:Tahoma;
+mso-hansi-font-family:Tahoma;
+mso-bidi-font-family:Tahoma;}
+.MsoChpDefault
+{mso-style-type:export-only;
+mso-default-props:yes;
+font-size:10.0pt;
+mso-ansi-font-size:10.0pt;
+mso-bidi-font-size:10.0pt;}
+@page WordSection1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.WordSection1
+{page:WordSection1;}
+/* List Definitions */
+@list l0
+{mso-list-id:62067358;
+mso-list-template-ids:-174943062;}
+@list l0:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l0:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l0:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1
+{mso-list-id:128015942;
+mso-list-template-ids:-90681214;}
+@list l1:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l1:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2
+{mso-list-id:216556000;
+mso-list-template-ids:925924412;}
+@list l2:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l2:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l2:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3
+{mso-list-id:562446694;
+mso-list-template-ids:913898366;}
+@list l3:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l3:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
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+@list l3:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l3:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4
+{mso-list-id:797802132;
+mso-list-template-ids:-1971191336;}
+@list l4:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l4:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5
+{mso-list-id:907304066;
+mso-list-template-ids:1969781532;}
+@list l5:level1
+{mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l5:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6
+{mso-list-id:1050613616;
+mso-list-template-ids:-1009886748;}
+@list l6:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l6:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l6:level5
+{mso-level-tab-stop:2.5in;
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+@list l6:level6
+{mso-level-tab-stop:3.0in;
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+@list l6:level7
+{mso-level-tab-stop:3.5in;
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+@list l6:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
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+@list l6:level9
+{mso-level-tab-stop:4.5in;
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+@list l7
+{mso-list-id:1234970193;
+mso-list-template-ids:2055904002;}
+@list l7:level1
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;
+mso-ansi-font-size:10.0pt;
+font-family:Symbol;}
+@list l7:level2
+{mso-level-number-format:bullet;
+mso-level-text:\F0B7;
+mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
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+font-family:Symbol;}
+@list l7:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
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+@list l7:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l7:level9
+{mso-level-tab-stop:4.5in;
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+text-indent:-.25in;}
+@list l8
+{mso-list-id:1846092290;
+mso-list-template-ids:-768590846;}
+@list l8:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l8:level9
+{mso-level-tab-stop:4.5in;
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+text-indent:-.25in;}
+@list l9
+{mso-list-id:1894656566;
+mso-list-template-ids:1199983812;}
+@list l9:level1
+{mso-level-start-at:2;
+mso-level-tab-stop:.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level2
+{mso-level-tab-stop:1.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level3
+{mso-level-tab-stop:1.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level4
+{mso-level-tab-stop:2.0in;
+mso-level-number-position:left;
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+@list l9:level5
+{mso-level-tab-stop:2.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level6
+{mso-level-tab-stop:3.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level7
+{mso-level-tab-stop:3.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level8
+{mso-level-tab-stop:4.0in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+@list l9:level9
+{mso-level-tab-stop:4.5in;
+mso-level-number-position:left;
+text-indent:-.25in;}
+ol
+{margin-bottom:0in;}
+ul
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+<body style="" link="blue" vlink="blue">
+<div class="WordSection1">
+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0in;" valign="top">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
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+<td style="padding: 0in 5.4pt;" valign="top">
+<p class="MsoNormal"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release
+Notes for STM32F0xx HAL Drivers</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
+2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img id="_x0000_i1026" src="../../_htmresc/st_logo.png" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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+<td style="padding: 0in;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
+/ 11-December-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span>&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HandleTypeDef.ErrorCode must be typed uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update HAL drivers to ensure compliancy w/ C++</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Case mismatch between #include typo and effective file name generating compiler errors under Linux</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct various issues for documentation generation (group name, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">doxygen tags, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">etc..)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing support of I2C_PAx_FMP of F04xx devices<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL ADC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Improve HAL ADC comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct issue observed with ADC start simultaneous commands</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove&nbsp;macro __HAL_ADC_OFR_CHANNEL()&nbsp;since&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OFRx register</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> is not available on F0 devices.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL&nbsp;CAN&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as __IO uint32 instead of <span style="font-weight: bold;">enum HAL_CAN_ErrorTypeDef</span> to fix C++ compilation issue<span style="font-weight: bold;"><br></span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CEC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change<span style="font-weight: bold;"> ErrorCode </span>field declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t &nbsp;to</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> __IO uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct CEC state:&nbsp;Ready to Receive state lost upon Transmission end</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL&nbsp;COMP&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">State&nbsp;</span>field is now declared as&nbsp;uint32_t instead of <span style="font-weight: bold;">enum&nbsp;HAL_COMP_StateTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CRC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong @ref in CRCLength field description for documentation generation&nbsp;</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DAC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_DAC_Stop_DMA() code clean up</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Use of internal macro MODIFY_REG() to update CR register<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DMA channel remap register renamed for compatibility with other STM32 devices.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL FLASH&nbsp;</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum&nbsp;FLASH_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change HAL_FLASH_GetError() type declaration from&nbsp;FLASH_ErrorTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Clean the error context to FLASH_ERROR_NONE before starting new Flash operation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Put all the clear flags in the FLASH_SetSerrorCode()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Stop&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the programming procedure in case of error detected </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">in HAL_FLASH_Program()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Check error before doing new procedure in&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_FLASH_IRQhandler() </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct Typo in 'How to use this driver' section &amp; update comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add assert on GPIO PIN in HAL_GPIO_DeInit()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add assert </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">on GPIO AF instance to protect HAL_GPIO_Init() </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">from impossible AF configuration</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Reset </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Interrupt mode registers&nbsp;only in HAL_GPIO_DeInit()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span></span><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_I2C_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_I2S_ErrorTypeDef</span> to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_I2S_GetError</span>() type declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_I2S_ErrorTypeDef </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() &amp; __HAL_I2S_CLEAR_UDRFLAG to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">fix&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_IRDA_ErrorTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing doxygen tags for IRDA_HandleTypeDef fields description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new API&nbsp;to manage&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SLEEPONEXIT and SEVONPEND bits of SCR register:</span></li></ul></ul><ul style="margin-left: 80px;"><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_DisableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_EnableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_EnableSEVOnPend()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_PWR_DisableSEVOnPend()</span></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Removed useless regulator parameter setting for F0 family&nbsp;in core of HAL_PWR_EnterSLEEPMode()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Move __HAL_RCC_USART2_CONFIG() &amp;&nbsp;__HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f0xx_hal_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">rcc_ex.h since this feature is not supported on all F0 devices </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_RCCEx_CRSWaitSynchronization</span>() type declaration from </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RCC_CRSStatusTypeDef</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RTC&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Enhance @note describing the use of HAL RTC APIs&nbsp;</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD</span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SMARTCARD_ErrorTypeDef</span> to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS</span></span><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode &amp; PreviousState </span>fields are now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SMBUS_ErrorTypeDef</span> &amp; <span style="font-weight: bold;">HAL_SMBUS_StateTypeDef </span>to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-weight: bold;">HAL_SMBUS_GetState</span>() type declaration from&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_SMBUS_StateTypeDef<span style="font-weight: bold;"> </span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> to uint32_t </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SPI&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_SPI_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">fix&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add DMA circular mode support on SPI HAL driver.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Internal
+fucntion renaming:&nbsp;HAL_SPI_DMATransmitCplt(),
+HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() &amp;
+HAL_SPI_DMAError() renamed respectively into </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMATransmitCplt(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMAReceiveCplt(),&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMATransmitReceiveCplt() &amp;&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">SPI_DMAError().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t driver alignment for compatibility with other STM32 devices<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new API <span style="font-weight: bold;">HAL_SPI_GetError</span>(), which was missing on STM32F0xx family<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART/USART&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">ErrorCode </span>field is now declared as&nbsp;uint32 instead of <span style="font-weight: bold;">enum HAL_U(S)ART_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add missing API&nbsp;HAL_StatusTypeDef <span style="font-weight: bold;">HAL_LIN_SendBreak</span>()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct wrong USART_IT_CM value</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">correct issue with Lin mode data length</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new value for&nbsp;Stop bit definition: UART_STOPBITS_1_5<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USB&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span><span style="font-weight: bold;"></span>.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correct _HAL_PCD_CLEAR_FLAG() macros definition <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL WWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new&nbsp;macro to manage WWDG IT &amp; correction:</span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_WWDG_DISABLE_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_WWDG_GET_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">__HAL_WWDG_GET_IT_SOURCE()</span><br></span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
+/ 03-October-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span>&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">general improvement of Doxygen Tags for CHM UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add support of new devices </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">STM32F091xC</span>,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">STM32F098xx</span> in </span><span style="font-size: 10pt; font-family: Verdana;">STM32F0xx HAL drivers</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">minor corrections for Pdf/Chm UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Correction for MISRA&nbsp;</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">[F098xx] Remove PVD IT line wrapper</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">FLAG&amp;IT assert macros to be removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bad macro name in stm32F0xx_hal.c/.h files</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">uint32_t Alignement&nbsp;in HAL driver</span></li></ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL </span>update&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">(for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx)</span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new define for HAL IRDA Enveloppe source Selection</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_GET_PENDING_IT()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_SYSCFG_IRDA_ENV_SELECTION()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_SYSCFG_GET_IRDA_ENV_SELECTION()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL COMP&nbsp;</span></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missing assert param IS_COMP_TRIGGERMODE</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL Cortex&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">remove Macro not supported by cortex-M0 in stm32f0xx.h</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA&nbsp;</span></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DMAx channels </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">remap bit field definition</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macros: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_GET_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">A</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">dd new macro: </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bit definition name error for&nbsp;HAL_DMA1_CH2 remap on STM32F091xC</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">HAL_DMA_PollForTransfer updated</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL GPIO&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">BSRR regsiter should not be split in BSRRH/BSRRL</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">rework GPIO_GET_SOURCE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines for AF functions selection</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Supp ClockSource in Init</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Use WRITE_REG instead of SET_BIT</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Calibri;">PVD feature need falling/rising Event modes</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update defines name&nbsp;PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING&nbsp;to PWR_<span style="font-weight: bold;">PVD</span>_MODE_<span style="font-weight: bold;">NORMAL/</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">MODE_IT_RISING/PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">MODE_IT_FALLING/PWR_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">PVD</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_MODE_IT_RISING_FALLING</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING<span style="font-weight: bold;"><br></span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update macro IS_PWR_PVD_MODE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change macro name: __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_ENABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_DISABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_GENERATE_SWIT(), __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_GET_FLAG(),&nbsp; __HAL</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_PVD_EXTI_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
+new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(),
+__HAL_PWR_PVD_EXTI_DISABLE_EVENT(),
+__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(),
+__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC&nbsp;</span></span><ul><li><span style="font-family: Calibri;">Defect correction:</span><span style="font-family: Calibri;"></span></li><ul><li><span style="font-family: Calibri;">HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">New structure RCC_PeriphCLKInitTypeDef</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
+defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1,
+RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC,
+RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro IS_RCC_PERIPHCLK()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
+defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1,
+RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE,
+CC_USART3CLKSOURCE_HSI</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro IS_RCC_USART3CLKSOURCE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro __HAL_RCC_GET_USART3_SOURCE()</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add macro __HAL_RCC_USART3_CONFIG()<br></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add clock enable macros for new UART: __USART5_CLK_ENABLE,&nbsp; __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add clock disable macros for new UART: __USART5_CLK_DISABLE,&nbsp; __USART6_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">, __USART7_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">, __USART8_CLK_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DISABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET, __USART7_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET, __USART8_</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">RELEASE</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">_RESET</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;</span></li></ul></ul></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change&nbsp;SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS&nbsp;</span>&nbsp;</span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">change&nbsp;SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SPI&nbsp;</span></span></p></li><ul style="font-family: Lucida Sans;" class="MsoChpDefault"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Missed/Unused assert param to be added/removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Trigger interrupt should be activated when working with a slave mode</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">missing assert in HAL_TIMEx_ConfigBreakDeadTime</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">URS_ENABLE/ URS_DISABLE macros</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART/USART&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change UART TX-IT implementation to remove WaitOnFlag in ISR</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F091xC/</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32F098xx:</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USB&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Bad IN/OUT EndPoint parameter array size</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL WWDG&nbsp;</span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">improvements from other families</span></p></li></ul></ul><div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Defect Correction<br><br></span></u></b>
+
+<table class="MsoNormalTable" style="width: 652.45pt; border-collapse: collapse;" border="0" cellpadding="0" cellspacing="0" width="870">
+ <tbody><tr style="height: 15pt;">
+
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
+ <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
+ <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
+ <p class="MsoNormal"><span style="color: black;">PWR<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
+ <p class="MsoNormal"><span style="color: black;">PVD feature need falling/rising Event modes<o:p></o:p></span></p>
+ </td>
+ </tr>
+ <tr style="height: 15pt;">
+
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
+ <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
+ <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
+ <p class="MsoNormal"><span style="color: black;">COMP<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
+ <p class="MsoNormal"><span style="color: black;">Missing assert param IS_COMP_TRIGGERMODE&nbsp;<o:p></o:p></span></p>
+ </td>
+ </tr>
+
+ <tr style="height: 15pt;">
+
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
+ <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
+ <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
+ <p class="MsoNormal"><span style="color: black;">RCC<o:p></o:p></span></p>
+ </td>
+ <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
+ <p class="MsoNormal"><span style="color: black;">HAL_RCC_OscConfig: HSERDY has to be checked also in by
+ pass mode<o:p></o:p></span></p>
+ </td>
+ </tr>
+</tbody></table>
+<br></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
+/ 18-June-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL generic</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"=" </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">instead of ready-modify-write operation "|=" or "&amp;="</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix
+on Timeout management, Timeout value set to 0 passed to API
+automatically exits the function after checking the flag without any
+wait.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
+new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL CEC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span>&nbsp;</li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL COMP</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add <span style="font-style: italic;">NonInvertingInput</span> field in the <span style="font-style: italic;">COMP_InitTypeDef</span> structure.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new defines <span style="font-style: italic;">COMP_NONINVERTINGINPUT_IO1</span> and <span style="font-style: italic;">COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED</span><br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL DMA</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in&nbsp;<span style="font-style: italic;">HAL_DMA_PollForTransfer()</span> to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE </span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2C</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add
+management of NACK event in Master transmitter mode and Slave
+transmitter/receiver modes (only in polling mode), in that case the
+current transfer is stopped.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL I2S</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">I2S clock source change: new define <span style="font-style: italic;">I2S_CLOCK_SYSCLK</span>, remove<span style="font-style: italic;"> I2S_CLOCK_PLL</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Improvement done in I2S transfer/receive processes <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new enum typedef <span style="font-style: italic;">IRDA_ClockSourceTypeDef</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro <span style="font-style: italic;">__HAL_IRDA_GETCLOCKSOURCE</span></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable IRDA_IT_TXE instead of IRDA_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+ <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></p>
+ </li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+ <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT</span></span></p>
+ </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL PWR</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span> to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL RCC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add USB peripheral and clocking macros for STM32F078xx device.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix HSI Calibration issue when selected as SYSCLK </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL SMBUS</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TIM</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix macro __HAL_TIM_PRESCALER</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL TSC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Fix define&nbsp;<span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
+
+
+
+
+
+
+
+<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL UART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_LIN_Init()</span> parameter BreakDetectLength to uint32_t</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable UART_IT_TXE instead of UART_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-weight: bold;">HAL USART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change <span style="font-style: italic;">USART_InitTypeDef</span> fields to uint32_t type</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Rename __USART_ENABLE and __USART_DISABLE macros to respectively </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">__HAL_USART_ENABLE and __HAL_USART_DISABLE</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable USART_IT_TXE instead of USART_IT_TC.</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Process no more locked during the transmission in interrupt mode.</span></li><li><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Change in <span style="font-style: italic;">HAL_USART_TransmitReceive_DMA()</span> to manage DMA half transfer mode</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
+/ 20-May-2014<o:p></o:p></span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official
+release of STM32F0xx HAL drivers for </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F030x4/x6, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F030x8,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F031x4/x6</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">, &nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F051x4/x6/x8</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F071x8/xB,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F042x4/x6,
+</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F072x8/xB, &nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F038xx,
+</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> STM32F048xx</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F058xx and STM32F078xx
+</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">devices.</span></li></ul><br><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+<div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistribution
+and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+</font>
+<ol>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the
+documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li>
+<li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the
+name of STMicroelectronics nor the names of its contributors may be
+used to endorse or promote products derived </span><br>
+</font> </li>
+</ol>
+<font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
+from this software without specific prior written permission.</span><br>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS
+SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES,
+INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR
+PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+THE POSSIBILITY OF SUCH DAMAGE.</span></font> </div>
+<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span>
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+<tr><td style="padding: 0in;" valign="top"></td></tr></tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html> \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld
new file mode 100644
index 000000000..3480bf3aa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld
@@ -0,0 +1,155 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.s
new file mode 100644
index 000000000..d39ff65ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.s
@@ -0,0 +1,299 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f051x8.s
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bl exit
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detect */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_CRS_IRQHandler /* RCC and CRS */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word TSC_IRQHandler /* TSC */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
+ .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
+ .word 0 /* Reserved */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word 0 /* Reserved */
+ .word CEC_CAN_IRQHandler /* CEC and CAN */
+ .word 0 /* Reserved */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_CRS_IRQHandler
+ .thumb_set RCC_CRS_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_5_IRQHandler
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+ .weak ADC1_COMP_IRQHandler
+ .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak CEC_CAN_IRQHandler
+ .thumb_set CEC_CAN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h
new file mode 100644
index 000000000..be4a7706f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c
new file mode 100644
index 000000000..3a0d329f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h
new file mode 100644
index 000000000..ce6b91f7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F030R8
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 29 vectors = 116 bytes from 0x40 to 0xB3
+// Total: 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+#define NVIC_NUM_VECTORS 45
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h
new file mode 100644
index 000000000..3b3687105
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h
@@ -0,0 +1,3815 @@
+/**
+ ******************************************************************************
+ * @file stm32f051x8.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
+ * Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f051x8
+ * @{
+ */
+
+#ifndef __STM32F051x8_H
+#define __STM32F051x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F051x4/STM32F051x6/STM32F051x8 device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F051x4/STM32F051x6/STM32F051x8 specific Interrupt Numbers **************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC global Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 28, /*!< USART2 global Interrupt */
+ CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief HDMI-CEC
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+}COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+}COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+}DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+}TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP_BASE)
+#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/*********************** Bit definition for COMP_CSR register ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+/* COMPx bits definition */
+#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< CEC Clock source selection */
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
+
+#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
+
+/*!< USART2 Clock source selection */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ***************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ***************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ***************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ***************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ***************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/****************************** COMP Instances *********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
+
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+/****************************** GPIO Lock Instances ****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : LIN mode ********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : wakeup from stop mode ********************/
+#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_VDDIO2_IRQn PVD_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F051x8_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h
new file mode 100644
index 000000000..8dee1e541
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h
@@ -0,0 +1,228 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ #define STM32F051x8 /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.1.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c
new file mode 100644
index 000000000..164d05f19
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c
@@ -0,0 +1,435 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
+#else
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = 0; // not used
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+
+/* Used for the different timeouts in the HAL */
+void SysTick_Handler(void)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h
new file mode 100644
index 000000000..00f7ba2ef
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.s
new file mode 100644
index 000000000..c82949c83
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.s
@@ -0,0 +1,216 @@
+; STM32F030x8 devices vector table for MDK ARM_MICRO toolchain
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8)
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct
new file mode 100644
index 000000000..dbf0cb563
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F030R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+
+ LR_IROM1 0x08000000 0x10000 { ; load region size_region
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/startup_stm32f030x8.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/startup_stm32f030x8.s
new file mode 100644
index 000000000..8d3a08bac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/startup_stm32f030x8.s
@@ -0,0 +1,189 @@
+; STM32F030x8 devices vector table for MDK ARM_STD toolchain
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx.sct
new file mode 100644
index 000000000..dbf0cb563
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F030R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
+
+ LR_IROM1 0x08000000 0x10000 { ; load region size_region
+ ER_IROM1 0x08000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/STM32F030X8.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/STM32F030X8.ld
new file mode 100644
index 000000000..76dae312c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/STM32F030X8.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 8k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s
new file mode 100644
index 000000000..1bba55d45
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.s
@@ -0,0 +1,287 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f030x8.s
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief STM32F030x8 devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word 0 /* Reserved */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word 0 /* Reserved */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word 0 /* Reserved */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word 0 /* Reserved */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_5_IRQHandler
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/startup_stm32f030x8.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/startup_stm32f030x8.s
new file mode 100644
index 000000000..8c13b3d33
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/startup_stm32f030x8.s
@@ -0,0 +1,291 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f030x8.s
+;* Author : MCD Application Team
+;* Version : V2.1.0
+;* Date : 03-Oct-2014
+;* Description : STM32F030x8 devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address,
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD 0 ; Reserved
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+ B EXTI0_1_IRQHandler
+
+ PUBWEAK EXTI2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+ B EXTI2_3_IRQHandler
+
+ PUBWEAK EXTI4_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+ B EXTI4_15_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+ B DMA1_Channel2_3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_IRQHandler
+ B DMA1_Channel4_5_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+ B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf
new file mode 100644
index 000000000..ba742ac29
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf
@@ -0,0 +1,31 @@
+/* [ROM = 64kb = 0x10000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0800FFFF;
+
+/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 45 vectors = 180 bytes (0xB4) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200000B7; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200000B8;
+define symbol __region_RAM_end__ = 0x20001FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0x800;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis.h
new file mode 100644
index 000000000..be4a7706f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.c
new file mode 100644
index 000000000..8b706e8d5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.h
new file mode 100644
index 000000000..ce6b91f7f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F030R8
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 29 vectors = 116 bytes from 0x40 to 0xB3
+// Total: 45 vectors = 180 bytes (0xB4) to be reserved in RAM
+#define NVIC_NUM_VECTORS 45
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h
new file mode 100644
index 000000000..8cab6e21c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h
@@ -0,0 +1,3214 @@
+/**
+ ******************************************************************************
+ * @file stm32f030x8.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f030x8
+ * @{
+ */
+
+#ifndef __STM32F030x8_H
+#define __STM32F030x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F030x8 device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F030x8 specific Interrupt Numbers **************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC global Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt */
+ USART2_IRQn = 28 /*!< USART2 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< USART2 Clock source selection */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+
+/* Aliases for __IRQHandler */
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F030x8_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h
new file mode 100644
index 000000000..61a90d66d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+#define STM32F030x8 /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
new file mode 100644
index 000000000..5b7227f3c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
@@ -0,0 +1,456 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+ #warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = 0; // not used
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+
+/* Used for the different timeouts in the HAL */
+void SysTick_Handler(void)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h
new file mode 100644
index 000000000..7647daf2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s
new file mode 100644
index 000000000..0814fae07
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.s
@@ -0,0 +1,239 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD 0 ; Reserved
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct
new file mode 100644
index 000000000..d6531bd02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F070RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s
new file mode 100644
index 000000000..29a68407e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.s
@@ -0,0 +1,212 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD 0 ; Reserved
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_IRQHandler
+ADC1_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct
new file mode 100644
index 000000000..d6531bd02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F070RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld
new file mode 100644
index 000000000..137d80971
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 16k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s
new file mode 100644
index 000000000..288a5bda8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.s
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f070xb.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word 0 /* Reserved */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word 0 /* Reserved */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word 0 /* Reserved */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_4_IRQHandler /* USART3 and USART4 */
+ .word 0 /* Reserved */
+ .word USB_IRQHandler /* USB */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_5_IRQHandler
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_4_IRQHandler
+ .thumb_set USART3_4_IRQHandler,Default_Handler
+
+ .weak USB_IRQHandler
+ .thumb_set USB_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s
new file mode 100644
index 000000000..7fcd91c9e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.s
@@ -0,0 +1,305 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f070xb.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 05-December-2014
+;* Description : STM32F070xB devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address,
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD 0 ; Reserved
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD 0 ; Reserved
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
+ DCD ADC1_IRQHandler ; ADC1
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD 0 ; Reserved
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 and USART4
+ DCD 0 ; Reserved
+ DCD USB_IRQHandler ; USB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+ B EXTI0_1_IRQHandler
+
+ PUBWEAK EXTI2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+ B EXTI2_3_IRQHandler
+
+ PUBWEAK EXTI4_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+ B EXTI4_15_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+ B DMA1_Channel2_3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_IRQHandler
+ B DMA1_Channel4_5_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+ B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_4_IRQHandler
+ B USART3_4_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf
new file mode 100644
index 000000000..2a2b853d4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf
@@ -0,0 +1,31 @@
+/* [ROM = 128kb = 0x20000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0801FFFF;
+
+/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200000C0;
+define symbol __region_RAM_end__ = 0x20003FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x1000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h
new file mode 100644
index 000000000..be4a7706f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c
new file mode 100644
index 000000000..1253c2d50
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (NVIC_vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ NVIC_vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h
new file mode 100644
index 000000000..027dd9f78
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
+// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+#define NVIC_NUM_VECTORS 48
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c
new file mode 100644
index 000000000..d2b52d2b4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c
@@ -0,0 +1,167 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+void set_compare(uint16_t count);
+
+extern volatile uint32_t SlaveCounter;
+extern volatile uint32_t oc_int_part;
+extern volatile uint16_t oc_rem_part;
+
+// Used to increment the slave counter
+void timer_update_irq_handler(void)
+{
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Clear Update interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
+ SlaveCounter++;
+ }
+}
+
+// Used for mbed timeout (channel 1) and HAL tick (channel 2)
+void timer_oc_irq_handler(void)
+{
+ uint16_t cval = TIM_MST->CNT;
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ if (oc_rem_part > 0) {
+ set_compare(oc_rem_part); // Finish the remaining time left
+ oc_rem_part = 0;
+ } else {
+ if (oc_int_part > 0) {
+ set_compare(0xFFFF);
+ oc_rem_part = cval; // To finish the counter loop the next time
+ oc_int_part--;
+ } else {
+ us_ticker_irq_handler();
+ }
+ }
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 1 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_Base_Init(&TimMasterHandle);
+
+ // Configure output compare channel 1 for mbed timeout (enabled later when used)
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Configure output compare channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+
+ // Configure interrupts
+ // Update interrupt used for 32-bit counter
+ // Output compare channel 1 interrupt for mbed timeout
+ // Output compare channel 2 interrupt for HAL tick
+ NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_UP_IRQ);
+ NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_OC_IRQ);
+
+ // Enable interrupts
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
+
+ // Enable timer
+ HAL_TIM_Base_Start(&TimMasterHandle);
+
+#if 1 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.h
new file mode 100644
index 000000000..3100089c2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.h
@@ -0,0 +1,61 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM1
+#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
+#define TIM_MST_OC_IRQ TIM1_CC_IRQn
+#define TIM_MST_RCC __TIM1_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM1_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h
new file mode 100644
index 000000000..5313b9d71
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h
@@ -0,0 +1,3420 @@
+/**
+ ******************************************************************************
+ * @file stm32f070xb.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f070xb
+ * @{
+ */
+
+#ifndef __STM32F070xB_H
+#define __STM32F070xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F070xB device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F070xB specific Interrupt Numbers **************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC Global Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 global Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt */
+ USART2_IRQn = 28, /*!< USART2 global Interrupt */
+ USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
+ USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t RESERVED1;/*!< Reserved, Address offset: 0x20 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+}USB_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP2 register *********************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP3 register *********************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
+#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
+#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
+#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
+#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< USB Clock source selection */
+#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
+
+#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< Keep for compatibility */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
+#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< Keep for compatibility */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< Keep for compatibility */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Keep for compatibility */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
+
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+/****************************** GPIO Lock Instances ****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define USART3_8_IRQn USART3_4_IRQn
+#define USART3_6_IRQn USART3_4_IRQn
+
+/* Aliases for __IRQHandler */
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
+#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
+#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define USART3_8_IRQHandler USART3_4_IRQHandler
+#define USART3_6_IRQHandler USART3_4_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F070xB_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h
new file mode 100644
index 000000000..7c60f8808
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+#define STM32F070xB /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
new file mode 100644
index 000000000..fe0f8d4ba
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
@@ -0,0 +1,467 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+extern int NVIC_vtor_remap;
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+ #warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = 0; // not used
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h
new file mode 100644
index 000000000..7647daf2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.s
new file mode 100644
index 000000000..23b894eaa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.s
@@ -0,0 +1,247 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f072xb.s
+;* Author : MCD Application Team
+;* Version : V2.0.0
+;* Date : 20-May-2014
+;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TS
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_VDDIO2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_CRS_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+ EXPORT ADC1_COMP_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT CEC_CAN_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+CEC_CAN_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/stm32f072rb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/stm32f072rb.sct
new file mode 100644
index 000000000..e0e5a5f5a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/stm32f072rb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F072RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/startup_stm32f072xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/startup_stm32f072xb.s
new file mode 100644
index 000000000..33050eb33
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/startup_stm32f072xb.s
@@ -0,0 +1,220 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f072xb.s
+;* Author : MCD Application Team
+;* Version : V2.0.0
+;* Date : 20-May-2014
+;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp EQU 0x20004000 ; Top of RAM (16KB)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TS
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 & USART4
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+ DCD USB_IRQHandler ; USB
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_VDDIO2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_CRS_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+ EXPORT ADC1_COMP_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_4_IRQHandler [WEAK]
+ EXPORT CEC_CAN_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_4_IRQHandler
+CEC_CAN_IRQHandler
+USB_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f072rb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f072rb.sct
new file mode 100644
index 000000000..e0e5a5f5a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f072rb.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F072RB: 128KB FLASH (0x20000) + 16KB RAM (0x4000)
+
+ LR_IROM1 0x08000000 0x20000 { ; load region size_region
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x4000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/STM32F072XB.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/STM32F072XB.ld
new file mode 100644
index 000000000..137d80971
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/STM32F072XB.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 16k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s
new file mode 100644
index 000000000..15f7d9e03
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.s
@@ -0,0 +1,315 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f072xb.s
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief STM32F072x8/STM32F072xB devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ //bl __libc_init_array
+/* Call the application's entry point.*/
+ //bl main
+/**
+ * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+ * and when existing hardware_init_hook() and software_init_hook() before
+ * starting main(). software_init_hook() is available and has to be called due
+ * to initializsation when using rtos.
+*/
+ bl _start
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_CRS_IRQHandler /* RCC and CRS */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word TSC_IRQHandler /* TSC */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
+ .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
+ .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_4_IRQHandler /* USART3 and USART4 */
+ .word CEC_CAN_IRQHandler /* CEC and CAN */
+ .word USB_IRQHandler /* USB */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_VDDIO2_IRQHandler
+ .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_CRS_IRQHandler
+ .thumb_set RCC_CRS_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_3_IRQHandler
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_5_6_7_IRQHandler
+ .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
+
+ .weak ADC1_COMP_IRQHandler
+ .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_4_IRQHandler
+ .thumb_set USART3_4_IRQHandler,Default_Handler
+
+ .weak CEC_CAN_IRQHandler
+ .thumb_set CEC_CAN_IRQHandler,Default_Handler
+
+ .weak USB_IRQHandler
+ .thumb_set USB_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/startup_stm32f072xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/startup_stm32f072xb.s
new file mode 100644
index 000000000..82a403f68
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/startup_stm32f072xb.s
@@ -0,0 +1,325 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f072xb.s
+;* Author : MCD Application Team
+;* Version : V2.1.0
+;* Date : 03-Oct-2014
+;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address,
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TSC
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
+ DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4 to Channel 7
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_4_IRQHandler ; USART3 and USART4
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+ DCD USB_IRQHandler ; USB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_VDDIO2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_VDDIO2_IRQHandler
+ B PVD_VDDIO2_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_CRS_IRQHandler
+ B RCC_CRS_IRQHandler
+
+ PUBWEAK EXTI0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+ B EXTI0_1_IRQHandler
+
+ PUBWEAK EXTI2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+ B EXTI2_3_IRQHandler
+
+ PUBWEAK EXTI4_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+ B EXTI4_15_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+ B DMA1_Channel2_3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_6_7_IRQHandler
+ B DMA1_Channel4_5_6_7_IRQHandler
+
+ PUBWEAK ADC1_COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_COMP_IRQHandler
+ B ADC1_COMP_IRQHandler
+
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+ B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_4_IRQHandler
+ B USART3_4_IRQHandler
+
+ PUBWEAK CEC_CAN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_CAN_IRQHandler
+ B CEC_CAN_IRQHandler
+
+ PUBWEAK USB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+ B USB_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf
new file mode 100644
index 000000000..585592331
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf
@@ -0,0 +1,30 @@
+/* [ROM = 128kb = 0x20000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0801FFFF;
+
+/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200000C0;
+define symbol __region_RAM_end__ = 0x20003FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x1000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h
new file mode 100644
index 000000000..be4a7706f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c
new file mode 100644
index 000000000..1253c2d50
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (NVIC_vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ NVIC_vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.h
new file mode 100644
index 000000000..5b41f231d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F072RB
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
+// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+#define NVIC_NUM_VECTORS 48
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.c
new file mode 100644
index 000000000..a295911ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.c
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h
new file mode 100644
index 000000000..2ba180005
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC __TIM2_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h
new file mode 100644
index 000000000..baba8b4d6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h
@@ -0,0 +1,5576 @@
+/**
+ ******************************************************************************
+ * @file stm32f072xb.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f072xb
+ * @{
+ */
+
+#ifndef __STM32F072xB_H
+#define __STM32F072xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
+ CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+ USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+}CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+}CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+}CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+}CAN_TypeDef;
+
+/**
+ * @brief HDMI-CEC
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+}COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+}COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+}CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+}DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+}TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+}USB_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP_BASE)
+#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/*********************** Bit definition for COMP_CSR register ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+/* COMPx bits definition */
+#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
+
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
+
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
+
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP2 register *********************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP3 register *********************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
+#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
+#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
+#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
+#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
+#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< CEC Clock source selection */
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
+
+#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
+
+/*!< USB Clock source selection */
+#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
+
+#define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
+#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
+
+/*!< USART2 Clock source selection */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
+#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
+#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register ****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ***************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ***************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ***************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ***************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ***************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
+#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
+#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
+#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
+#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
+#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
+#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
+#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
+
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances *********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
+
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/****************** UART Instances : LIN mode ********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : wakeup from stop mode ********************/
+#define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_IRQn PVD_VDDIO2_IRQn
+#define VDDIO2_IRQn PVD_VDDIO2_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_IRQHandler PVD_VDDIO2_IRQHandler
+#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F072xB_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h
new file mode 100644
index 000000000..76a9ab906
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+#define STM32F072xB /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c
new file mode 100644
index 000000000..b203ab80e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c
@@ -0,0 +1,467 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+extern int NVIC_vtor_remap;
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+ #warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSI48 oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h
new file mode 100644
index 000000000..7647daf2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.s
new file mode 100644
index 000000000..d338b6ae5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.s
@@ -0,0 +1,244 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f091xc.s
+;* Author : MCD Application Team
+;* Version : V2.1.0
+;* Date : 03-Oct-2014
+;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20008000 ; Top of RAM (32KB)
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TS
+ DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
+ DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_VDDIO2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_CRS_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT DMA1_Ch1_IRQHandler [WEAK]
+ EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
+ EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
+ EXPORT ADC1_COMP_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_8_IRQHandler [WEAK]
+ EXPORT CEC_CAN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Ch1_IRQHandler
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_8_IRQHandler
+CEC_CAN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/stm32f091rc.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/stm32f091rc.sct
new file mode 100644
index 000000000..c0680f17a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/stm32f091rc.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F091RC: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+ LR_IROM1 0x08000000 0x40000 { ; load region size_region
+ ER_IROM1 0x08000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x8000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/startup_stm32f091rc.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/startup_stm32f091rc.s
new file mode 100644
index 000000000..d6f00552e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/startup_stm32f091rc.s
@@ -0,0 +1,217 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f091xc.s
+;* Author : MCD Application Team
+;* Version : V2.1.0
+;* Date : 03-Oct-2014
+;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp EQU 0x20008000 ; Top of RAM (32KB)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TS
+ DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
+ DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_VDDIO2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_CRS_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT DMA1_Ch1_IRQHandler [WEAK]
+ EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
+ EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
+ EXPORT ADC1_COMP_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_8_IRQHandler [WEAK]
+ EXPORT CEC_CAN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_VDDIO2_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Ch1_IRQHandler
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ADC1_COMP_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_8_IRQHandler
+CEC_CAN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/stm32f091rc.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/stm32f091rc.sct
new file mode 100644
index 000000000..c0680f17a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/stm32f091rc.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F091RC: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+ LR_IROM1 0x08000000 0x40000 { ; load region size_region
+ ER_IROM1 0x08000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x8000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/STM32F091XC.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/STM32F091XC.ld
new file mode 100644
index 000000000..d598aac01
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/STM32F091XC.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
+ RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 32k - 0x0C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.s
new file mode 100644
index 000000000..a4f13199b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.s
@@ -0,0 +1,311 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f091xc.s
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 03-Oct-2014
+ * @brief STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M0 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2]
+ adds r2, r2, #4
+
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ //bl __libc_init_array
+/* Call the application's entry point.*/
+ //bl main
+/**
+ * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+ * and when existing hardware_init_hook() and software_init_hook() before
+ * starting main(). software_init_hook() is available and has to be called due
+ * to initializsation when using rtos.
+*/
+ bl _start
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word 0
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
+ .word RTC_IRQHandler /* RTC through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_CRS_IRQHandler /* RCC and CRS */
+ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
+ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
+ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
+ .word TSC_IRQHandler /* TSC */
+ .word DMA1_Ch1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler /* DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 */
+ .word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler /* DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 */
+ .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word I2C1_IRQHandler /* I2C1 */
+ .word I2C2_IRQHandler /* I2C2 */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_8_IRQHandler /* USART3, USART4, USART5, USART6, USART7, USART8 */
+ .word CEC_CAN_IRQHandler /* CEC and CAN */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_VDDIO2_IRQHandler
+ .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_CRS_IRQHandler
+ .thumb_set RCC_CRS_IRQHandler,Default_Handler
+
+ .weak EXTI0_1_IRQHandler
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+ .weak EXTI2_3_IRQHandler
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+ .weak EXTI4_15_IRQHandler
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak DMA1_Ch1_IRQHandler
+ .thumb_set DMA1_Ch1_IRQHandler,Default_Handler
+
+ .weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+ .thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler
+
+ .weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ .thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler
+
+ .weak ADC1_COMP_IRQHandler
+ .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler,Default_Handler
+
+ .weak I2C2_IRQHandler
+ .thumb_set I2C2_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_8_IRQHandler
+ .thumb_set USART3_8_IRQHandler,Default_Handler
+
+ .weak CEC_CAN_IRQHandler
+ .thumb_set CEC_CAN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/startup_stm32f091xc.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/startup_stm32f091xc.s
new file mode 100644
index 000000000..682f12bc3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/startup_stm32f091xc.s
@@ -0,0 +1,319 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f091xc.s
+;* Author : MCD Application Team
+;* Version : V2.1.0
+;* Date : 03-Oct-2014
+;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address,
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M0 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
+ DCD RTC_IRQHandler ; RTC through EXTI Line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_CRS_IRQHandler ; RCC and CRS
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
+ DCD TSC_IRQHandler ; TS
+ DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
+ DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
+ DCD TIM7_IRQHandler ; TIM7
+ DCD TIM14_IRQHandler ; TIM14
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD I2C1_IRQHandler ; I2C1
+ DCD I2C2_IRQHandler ; I2C2
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
+ DCD CEC_CAN_IRQHandler ; CEC and CAN
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_VDDIO2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_VDDIO2_IRQHandler
+ B PVD_VDDIO2_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_CRS_IRQHandler
+ B RCC_CRS_IRQHandler
+
+ PUBWEAK EXTI0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+ B EXTI0_1_IRQHandler
+
+ PUBWEAK EXTI2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+ B EXTI2_3_IRQHandler
+
+ PUBWEAK EXTI4_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+ B EXTI4_15_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK DMA1_Ch1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Ch1_IRQHandler
+ B DMA1_Ch1_IRQHandler
+
+ PUBWEAK DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+ B DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+
+ PUBWEAK DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+ B DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+
+ PUBWEAK ADC1_COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_COMP_IRQHandler
+ B ADC1_COMP_IRQHandler
+
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+ B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK I2C1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+ B I2C1_IRQHandler
+
+ PUBWEAK I2C2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+ B I2C2_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_8_IRQHandler
+ B USART3_8_IRQHandler
+
+ PUBWEAK CEC_CAN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_CAN_IRQHandler
+ B CEC_CAN_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf
new file mode 100644
index 000000000..f7a77ff5d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf
@@ -0,0 +1,31 @@
+/* [ROM = 256kb = 0x40000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0803FFFF;
+
+/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x200000C0;
+define symbol __region_RAM_end__ = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x1000;
+define symbol __size_heap__ = 0x2000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h
new file mode 100644
index 000000000..be4a7706f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c
new file mode 100644
index 000000000..1253c2d50
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (NVIC_vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ NVIC_vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h
new file mode 100644
index 000000000..4cc9ad676
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F091RC
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
+// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+#define NVIC_NUM_VECTORS 48
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.c
new file mode 100644
index 000000000..a295911ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.c
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h
new file mode 100644
index 000000000..2ba180005
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC __TIM2_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h
new file mode 100644
index 000000000..79a4f7d6d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h
@@ -0,0 +1,5710 @@
+/**
+ ******************************************************************************
+ * @file stm32f091xc.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f091xc
+ * @{
+ */
+
+#ifndef __STM32F091xC_H
+#define __STM32F091xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F091xC device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F091xC specific Interrupt Numbers **************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
+ DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */
+ DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */
+ CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+}CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+}CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+}CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+}CAN_TypeDef;
+
+/**
+ * @brief HDMI-CEC
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+}COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+}COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+}CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+}DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+ uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */
+ __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+ __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
+ __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ uint32_t RESERVED1[25]; /*!< Reserved + COMP, 0x1C */
+ __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
+
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+}TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
+#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
+#define USART5_BASE (APBPERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
+#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define USART6_BASE (APBPERIPH_BASE + 0x00011400)
+#define USART7_BASE (APBPERIPH_BASE + 0x00011800)
+#define USART8_BASE (APBPERIPH_BASE + 0x00011C00)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define USART5 ((USART_TypeDef *) USART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP_BASE)
+#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define USART7 ((USART_TypeDef *) USART7_BASE)
+#define USART8 ((USART_TypeDef *) USART8_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
+
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/*********************** Bit definition for COMP_CSR register ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+/* COMPx bits definition */
+#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
+
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
+
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
+
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA1_CSELR register ********************/
+#define DMA1_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */
+#define DMA1_CSELR_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/
+#define DMA1_CSELR_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */
+#define DMA1_CSELR_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_SPI1_RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */
+#define DMA1_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */
+#define DMA1_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */
+#define DMA1_CSELR_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */
+#define DMA1_CSELR_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */
+#define DMA1_CSELR_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define DMA1_CSELR_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */
+
+/****************** Bit definition for DMA2_CSELR register ********************/
+#define DMA2_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */
+#define DMA2_CSELR_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */
+#define DMA2_CSELR_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */
+#define DMA2_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */
+#define DMA2_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */
+#define DMA2_CSELR_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define DMA2_CSELR_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP1 register *********************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP2 register *********************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OB_WRP3 register *********************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
+#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
+#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
+#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
+#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration: obsolete setting for STM32F091xC */
+/*#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000)*/ /*!< ADCPRE bit (ADC prescaler) */
+
+/*#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)*/ /*!< PCLK divided by 2 */
+/*#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)*/ /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_USART8RST ((uint32_t)0x00000080) /*!< USART8 clock reset */
+#define RCC_APB2RSTR_USART7RST ((uint32_t)0x00000040) /*!< USART7 clock reset */
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) /*!< USART6 clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
+#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
+#define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART 5 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_USART8EN ((uint32_t)0x00000080) /*!< USART8 clock enable */
+#define RCC_APB2ENR_USART7EN ((uint32_t)0x00000040) /*!< USART7 clock enable */
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) /*!< USART6 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
+#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
+#define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/*!< CEC Clock source selection */
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
+
+#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
+
+/*!< USART2 Clock source selection */
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+/*!< USART3 Clock source selection */
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
+#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
+#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register ****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ***************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ***************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ***************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ***************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ***************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_0 ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
+#define SYSCFG_CFGR1_IRDA_ENV_SEL_1 ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
+#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/***************** Bit definition for SYSCFG_xxx ISR Wrapper register ****************/
+#define SYSCFG_ITLINE0_SR_EWDG ((uint32_t)0x00000001) /*!< EWDG interrupt */
+#define SYSCFG_ITLINE1_SR_PVDOUT ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
+#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
+#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
+#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
+#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */
+#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
+#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */
+#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */
+#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */
+#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */
+#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
+#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
+#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
+#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
+#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
+#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
+#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */
+#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
+#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
+#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
+#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
+#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
+#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
+#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
+#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */
+#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
+#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
+#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
+#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
+#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
+#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
+#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
+#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
+#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
+#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */
+#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
+#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
+#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
+#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
+#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
+#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */
+#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances *********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
+
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == USART7) || \
+ ((INSTANCE) == USART8))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == USART7) || \
+ ((INSTANCE) == USART8))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == USART7) || \
+ ((INSTANCE) == USART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == USART7) || \
+ ((INSTANCE) == USART8))
+
+/****************** UART Instances : LIN mode ********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : wakeup from stop mode ********************/
+#define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == USART7) || \
+ ((INSTANCE) == USART8))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F3xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_IRQn PVD_VDDIO2_IRQn
+#define VDDIO2_IRQn PVD_VDDIO2_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel1_IRQn DMA1_Ch1_IRQn
+#define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define USART3_4_IRQn USART3_8_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_IRQHandler PVD_VDDIO2_IRQHandler
+#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler
+#define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define USART3_4_IRQHandler USART3_8_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F091xC_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h
new file mode 100644
index 000000000..ab84cc6b0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+#define STM32F091xC /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c
new file mode 100644
index 000000000..b203ab80e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c
@@ -0,0 +1,467 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+extern int NVIC_vtor_remap;
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+ #warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select HSI48 oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h
new file mode 100644
index 000000000..7647daf2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 05-December-2014
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c
new file mode 100644
index 000000000..aba3a02eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c
@@ -0,0 +1,430 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs categories:
+ (+) HAL Initialization and de-initialization functions
+ (+) HAL Control functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL module driver
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private Constants
+ * @{
+ */
+/**
+ * @brief STM32F0xx HAL Driver version number V1.2.0
+ */
+#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F0xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\
+ |(__STM32F0xx_HAL_VERSION_SUB1 << 16)\
+ |(__STM32F0xx_HAL_VERSION_SUB2 << 8 )\
+ |(__STM32F0xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+static __IO uint32_t uwTick;
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the source of time base also when timeout
+ is needed and the backup domain when enabled.
+ (+) de-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __Weak
+ to make override possible in case of other implementations in user file.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function configures the Flash prefetch,
+ * Configures time base source, NVIC and Low level hardware
+ * @note This function is called at the beginning of program after reset and before
+ * the clock configuration
+ * @note The time base configuration is based on HSI clock when exiting from Reset.
+ * Once done, time base tick start incrementing.
+ * In the default implementation,Systick is used as source of time base.
+ * The tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the source
+ * of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __APB1_FORCE_RESET();
+ __APB1_RELEASE_RESET();
+
+ __APB2_FORCE_RESET();
+ __APB2_RELEASE_RESET();
+
+ __AHB_FORCE_RESET();
+ __AHB_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick++;
+}
+
+/**
+ * @brief Povides a tick value in millisecond.
+ * @note The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note ThiS function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+ uint32_t tickstart = 0;
+ tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
+ {
+ }
+}
+
+/**
+ * @brief This method returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F0xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h
new file mode 100644
index 000000000..8417f6416
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h
@@ -0,0 +1,697 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_H
+#define __STM32F0xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_conf.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @defgroup HAL_DMA_remapping HAL DMA remapping
+ * Elements values convention: 0xYYYYYYYY
+ * - YYYYYYYY : Position in the SYSCFG register CFGR1
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
+ 0: No remap (ADC DMA requests mapped on DMA channel 1
+ 1: Remap (ADC DMA requests mapped on DMA channel 2 */
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
+ 0: No remap (USART1_TX DMA request mapped on DMA channel 2
+ 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
+ 0: No remap (USART1_RX DMA request mapped on DMA channel 3
+ 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
+#define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
+ 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
+ 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
+#define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
+ 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
+ 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
+#define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
+ 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
+ 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
+#define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
+ 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
+ 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
+#define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
+ 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
+#define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
+ 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
+#define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
+ 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
+#define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
+ 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
+#define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
+ 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
+#define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
+ 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
+#define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
+ 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
+#endif
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
+#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
+ ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
+ ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
+ ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
+ ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \
+ ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \
+ ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \
+ ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \
+ ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \
+ ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \
+ ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \
+ ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \
+ ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \
+ ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6))
+#else
+#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
+ ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
+ ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
+ ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
+ ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2))
+#endif
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
+/** @defgroup HAL_Pin_remapping HAL Pin remapping
+ * @{
+ */
+#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
+ 0: No remap (pin pair PA9/10 mapped on the pins)
+ 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
+
+#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
+ * @note Applicable on STM32F09x
+ * @{
+ */
+#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
+
+#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
+/**
+ * @}
+ */
+#endif /* STM32F091xC || STM32F098xx */
+
+
+/** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_I2C_FMP_PB6)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PB6 pin operates in standard mode
+ 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_PB7)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PB7 pin operates in standard mode
+ 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_PB8)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PB8 pin operates in standard mode
+ 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_PB9)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PB9 pin operates in standard mode
+ 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation
+ 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
+ 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
+#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation
+ 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
+ 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
+#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PA9 pin operates in standard mode
+ 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
+
+#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
+ 0: PA10 pin operates in standard mode
+ 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */
+#endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
+#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
+#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030x6)
+#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
+#else
+#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
+ ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
+#endif
+
+/**
+ * @}
+ */
+
+#if defined(STM32F091xC) || defined (STM32F098xx)
+/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
+ * @brief ISR Wrapper
+ * @note applicable on STM32F09x
+ * @{
+ */
+#define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) /*!< Internal define for macro handling */
+
+#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
+#if defined(STM32F091xC)
+#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
+#endif
+#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
+#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
+#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
+#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
+#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
+#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
+#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
+#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
+#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
+#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
+#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
+#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
+#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
+#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
+#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
+#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
+#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
+#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
+#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
+#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
+#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
+#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
+#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
+#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
+#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
+#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
+#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
+#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
+#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
+#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
+#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
+#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
+#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
+#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
+#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
+#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
+#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
+#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
+#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
+#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
+#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
+#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
+#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
+#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
+#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
+#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
+#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
+#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
+#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
+#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
+#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
+#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
+#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
+#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
+#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
+#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
+#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
+#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
+#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
+#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
+#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
+#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
+#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
+#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
+#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
+#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
+#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
+#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
+/**
+ * @}
+ */
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
+ * @brief Freeze/Unfreeze Peripherals in Debug mode
+ * @{
+ */
+
+#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
+#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
+#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
+
+/**
+ * @}
+ */
+
+/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_MEM_MODE)
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
+#endif /* SYSCFG_CFGR1_MEM_MODE */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0)
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
+ }while(0)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
+ }while(0)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @defgroup HAL_DMA_remap HAL DMA remap
+ * @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
+ * @{
+ */
+#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 |= (__DMA_REMAP__); \
+ }while(0)
+#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
+/** @defgroup HAL_Pin_remap HAL Pin remap
+ * @brief Pin remapping enable/disable macros
+ * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
+ * @{
+ */
+#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
+ SYSCFG->CFGR1 |= (__PIN_REMAP__); \
+ }while(0)
+#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
+ SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
+
+/** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap
+ * @brief Fast mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
+ * @{
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
+ SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
+ }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
+ SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
+ }while(0)
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+ * @{
+ */
+/** @brief SYSCFG Break Lockup lock
+ * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+
+#if defined(SYSCFG_CFGR2_PVD_LOCK)
+/** @defgroup PVD_Lock_Enable PVD Lock
+ * @{
+ */
+/** @brief SYSCFG Break PVD lock
+ * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_PVD_LOCK */
+
+#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
+ * @{
+ */
+/** @brief SYSCFG Break SRAM PARITY lock
+ * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+
+#if defined(SYSCFG_CFGR2_SRAM_PEF)
+/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
+ * @brief Parity check on RAM disable macro
+ * @note Disabling the parity check on RAM locks the configuration bit.
+ * To re-enable the parity check on RAM perform a system reset.
+ * @{
+ */
+#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_SRAM_PEF */
+
+
+#if defined(STM32F091xC) || defined (STM32F098xx)
+/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
+ * @brief ISR wrapper check
+ * @note This feature is applicable on STM32F09x
+ * @note Allow to determine interrupt source per line.
+ * @{
+ */
+#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF))
+/**
+ * @}
+ */
+#endif /* (STM32F091xC) || defined (STM32F098xx)*/
+
+#if defined(STM32F091xC) || defined (STM32F098xx)
+/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
+ * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
+ * @note This feature is applicable on STM32F09x
+ * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
+ * @{
+ */
+#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
+ SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
+ SYSCFG->CFGR1 |= (__SOURCE__); \
+ }while(0)
+
+#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
+/**
+ * @}
+ */
+#endif /* (STM32F091xC) || defined (STM32F098xx)*/
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c
new file mode 100644
index 000000000..b6f04aee8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c
@@ -0,0 +1,1865 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_adc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular group,
+ * using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Analog Watchdog configuration
+ * ++ Channels configuration on regular group
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC specific features #####
+ ==============================================================================
+ [..]
+ (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
+
+ (#) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (#) Single and continuous conversion modes.
+
+ (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
+
+ (#) Data alignment with in-built data coherency.
+
+ (#) Programmable sampling time.
+
+ (#) ADC conversion group Regular.
+
+ (#) External trigger (timer or EXTI) with configurable polarity.
+
+ (#) DMA request generation for transfer of conversions data of regular group.
+
+ (#) ADC calibration
+
+ (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+
+ (#) ADC input range: from Vref minus (connected to Vssa) to Vref plus (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
+ at RCC top level: clock source and clock prescaler.
+ (++)Two possible clock sources: synchronous clock derived from APB clock
+ or asynchronous clock derived from ADC dedicated HSI RC oscillator
+ 14MHz.
+ (++)Example:
+ __ADC1_CLK_ENABLE(); (mandatory)
+
+ HI14 enable or let under control of ADC: (optional)
+
+ RCC_OscInitTypeDef RCC_OscInitStructure;
+ RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
+ RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
+ RCC_OscInitStructure.PLL... (optional if used for system clock)
+ HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ Parameter "HSI14State" must be set either:
+ - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
+ the HSI14 oscillator enable/disable (if not used to supply the main
+ system clock): feature used if ADC mode LowPowerAutoPowerOff is
+ enabled.
+ - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
+ always enabled: can be used to supply the main system clock.
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
+
+ (#) Configure the ADC parameters (conversion resolution, data alignment,
+ continuous mode, ...) using the HAL_ADC_Init() function.
+
+ (#) Activate the ADC peripheral using one of the start functions:
+ HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
+
+ *** Channels configuration to regular group ***
+ ================================================
+ [..]
+ (+) To configure the ADC regular group features, use
+ HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
+ (+) To activate the continuous mode, use the HAL_ADC_Init() function.
+ (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+
+ *** DMA for regular configuration ***
+ =============================================================
+ [..]
+ (+) To enable the DMA mode for regular group, use the
+ HAL_ADC_Start_DMA() function.
+ (+) To enable the generation of DMA requests continuously at the end of
+ the last DMA transfer, use the HAL_ADC_Init() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC HAL module driver
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+ /* Fixed timeout values for ADC calibration, enable settling time, disable */
+ /* settling time. */
+ /* Values defined to be higher than worst cases: low clock frequency, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 2)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+ /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */
+ /* have the minimum number of CPU cycles to fulfill this delay. */
+ #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t) 480)
+
+ /* Delay for ADC stabilization time. */
+ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+ /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */
+ /* have the minimum number of CPU cycles to fulfill this delay. */
+ #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)48)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on both possible clock sources: APB clock of HSI clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ uint32_t tmpCFGR1 = 0;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level depending on both possible clock sources: */
+ /* APB clock or HSI clock. */
+ /* Refer to header of this file for more details on clock enabling procedure*/
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ /* - ADC voltage regulator enable */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ /* and if there is no conversion on going on regular group (ADC can be */
+ /* enabled anyway, in case of call of this function to update a parameter */
+ /* on the fly). */
+ if ((hadc->State != HAL_ADC_STATE_ERROR) &&
+ (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
+ {
+ /* Initialize the ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY;
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - ADC clock mode */
+ /* - ADC clock prescaler */
+ if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ /* Reset configuration of ADC configuration register CFGR2: */
+ /* - ADC clock mode: CKMODE */
+ hadc->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);
+
+ /* Configuration of ADC clock mode: clock source AHB or HSI with */
+ /* selectable prescaler */
+ hadc->Instance->CFGR2 |= hadc->Init.ClockPrescaler;
+ }
+
+ /* Configuration of ADC: */
+ /* - discontinuous mode */
+ /* - LowPowerAutoWait mode */
+ /* - LowPowerAutoPowerOff mode */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - data alignment */
+ /* - resolution */
+ /* - scan direction */
+ /* - DMA continuous request */
+ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF |
+ ADC_CFGR1_AUTDLY |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC_CFGR1_ALIGN |
+ ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR |
+ ADC_CFGR1_DMACFG );
+
+ tmpCFGR1 |= (__HAL_ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
+ __HAL_ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) |
+ __HAL_ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) |
+ __HAL_ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ hadc->Init.Resolution |
+ __HAL_ADC_CFGR1_SCANDIR(hadc->Init.ScanConvMode) |
+ __HAL_ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Enable discontinuous mode of regular group */
+ tmpCFGR1 |= ADC_CFGR1_DISCEN;
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* @Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
+ hadc->Init.ExternalTrigConvEdge );
+ }
+
+ /* Update ADC configuration register with previous settings */
+ hadc->Instance->CFGR1 |= tmpCFGR1;
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core IP clocking. */
+ /* Check through register CFGR1 (excluding analog watchdog configuration: */
+ /* set into separate dedicated function). */
+ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL))
+ == tmpCFGR1)
+ {
+ /* Set ADC error code to none */
+ __HAL_ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize the ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ tmpHALStatus = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmpHALStatus = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY;
+
+ /* Stop potential conversion on going, on regular group */
+ tmpHALStatus = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Disable the ADC peripheral */
+ tmpHALStatus = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY ) );
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN );
+
+ /* Reset register CFGR2 */
+ /* @Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR &= ~ADC_SMPR_SMP;
+
+ /* Reset register TR1 */
+ hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
+
+ /* Reset register CHSELR */
+ hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 |
+ ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 |
+ ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 |
+ ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 |
+ ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register CCR */
+ ADC->CCR &= ~( ADC_CCR_VBATEN |
+ ADC_CCR_TSEN |
+ ADC_CCR_VREFEN );
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
+ /* */
+ /* __ADC1_FORCE_RESET() */
+ /* __ADC1_RELEASE_RESET() */
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ __HAL_ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+ {
+ tmpHALStatus = ADC_Enable(hadc);
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* State machine update: Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+
+ /* Set ADC error code to none */
+ __HAL_ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ hadc->Instance->CR |= ADC_CR_ADSTART;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ else
+ {
+ tmpHALStatus = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular group */
+ tmpHALStatus = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmpHALStatus = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_EOC;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence */
+ if (hadc->Init.EOCSelection == EOC_SEQ_CONV)
+ {
+ tmp_Flag_EOC = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of each conversion */
+ else /* EOC_SINGLE_CONV */
+ {
+ tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Clear end of conversion flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (hadc->Init.LowPowerAutoWait == DISABLE)
+ {
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for conversion event.
+ * @param hadc: ADC handle
+ * @param EventType: the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg AWD_EVENT: ADC Analog watchdog event
+ * @arg OVR_EVENT: ADC Overrun event
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart=0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ switch(EventType)
+ {
+ /* Analog watchdog (level out of window) event */
+ case AWD_EVENT:
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_AWD;
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ break;
+
+ /* Overrun event */
+ default: /* Case OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == OVR_DATA_PRESERVED)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to overrun */
+ hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+ }
+
+ /* Clear ADC Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ break;
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+ {
+ tmpHALStatus = ADC_Enable(hadc);
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* State machine update: Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+
+ /* Set ADC error code to none */
+ __HAL_ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ /* Enable ADC overrun interrupt */
+ switch(hadc->Init.EOCSelection)
+ {
+ case EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
+ break;
+ /* case EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+ break;
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ hadc->Instance->CR |= ADC_CR_ADSTART;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ else
+ {
+ tmpHALStatus = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+
+/**
+ * @brief Stop ADC conversion of regular group, disable interruption of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular group */
+ tmpHALStatus = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmpHALStatus = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+ {
+ tmpHALStatus = ADC_Enable(hadc);
+ }
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* State machine update: Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+
+ /* Set ADC error code to none */
+ __HAL_ADC_CLEAR_ERRORCODE(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ hadc->Instance->CR |= ADC_CR_ADSTART;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ else
+ {
+ tmpHALStatus = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular group */
+ tmpHALStatus = ADC_ConversionStop(hadc);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmpHALStatus != HAL_ERROR)
+ {
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmpHALStatus != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmpHALStatus == HAL_OK)
+ {
+ tmpHALStatus = ADC_Disable(hadc);
+ }
+ else
+ {
+ ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmpHALStatus == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading DR register automatically clears EOC (end of conversion of
+ * regular group) flag.
+ * Additionally, this functions clears EOS (end of sequence of
+ * regular group) flag, in case of the end of the sequence is reached.
+ * @param hadc: ADC handle
+ * @retval Converted value
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* @Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Clear regular group end of sequence flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Half conversion callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+/**
+ * @brief Handles ADC interrupt request.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+
+ /* Disable interruption if no further conversion upcoming by regular */
+ /* external trigger or by continuous mode, */
+ /* and if scan sequence if completed. */
+ if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* @Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* @Note: into callback, to determine if conversion has been triggered */
+ /* from EOC or EOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+
+ /* Clear regular group conversion flag */
+ /* @Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */
+ /* flags clear induces the release of the preserved data. */
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+ }
+
+ /* ========== Check Analog watchdog flags ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_AWD;
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear ADC Analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+
+ }
+
+
+ /* ========== Check Overrun flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) ||
+ HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
+ {
+ /* Change ADC state to error state */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to overrun */
+ hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+ }
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+}
+
+
+/**
+ * @brief Conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog callback in non blocking mode.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non blocking mode
+ * (ADC conversion with interruption or transfer by DMA)
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * VrefInt/Vbat/TempSensor.
+ * Sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values, parameters TS_vrefint,
+ * TS_vbat, TS_temp (values rough order: 5us to 17us).
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel sampling time */
+ /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Configure channel: depending on rank setting, add it or remove it from */
+ /* ADC conversion sequencer. */
+ if (sConfig->Rank != ADC_RANK_NONE)
+ {
+ /* Regular sequence configuration */
+ /* Set the channel selection register from the selected channel */
+ hadc->Instance->CHSELR |= __HAL_ADC_CHSELR_CHANNEL(sConfig->Channel);
+
+ /* Channel sampling time configuration */
+ /* Modify sampling time if needed (not needed in case of reoccurrence */
+ /* for several channels programmed consecutively into the sequencer) */
+ if (sConfig->SamplingTime != __HAL_ADC_GET_SAMPLINGTIME(hadc))
+ {
+ /* Channel sampling time configuration */
+ /* Clear the old sample time */
+ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR |= (sConfig->SamplingTime);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* @Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+
+ /* If Channel_16 is selected, enable Temp. sensor measurement path. */
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ ADC->CCR |= ADC_CCR_TSEN;
+
+ /* Delay for temperature sensor stabilization time */
+ while(wait_loop_index < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
+ {
+ wait_loop_index++;
+ }
+ }
+ /* If Channel_17 is selected, enable VBAT measurement path. */
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ ADC->CCR |= ADC_CCR_VBATEN;
+ }
+ /* If Channel_18 is selected, enable VREFINT measurement path. */
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ ADC->CCR |= ADC_CCR_VREFEN;
+ }
+
+ }
+ else
+ {
+ /* Regular sequence configuration */
+ /* Reset the channel selection register from the selected channel */
+ hadc->Instance->CHSELR &= ~__HAL_ADC_CHSELR_CHANNEL(sConfig->Channel);
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* internal measurement paths disable: If internal channel selected, */
+ /* disable dedicated internal buffers and path. */
+
+ /* If Channel_16 is selected, disable Temp. sensor measurement path. */
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ ADC->CCR &= ~ADC_CCR_TSEN;
+ }
+ /* If Channel_17 is selected, disable VBAT measurement path. */
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ ADC->CCR &= ~ADC_CCR_VBATEN;
+ }
+ /* If Channel_18 is selected, disable VREFINT measurement path. */
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ ADC->CCR &= ~ADC_CCR_VREFEN;
+ }
+ }
+
+ }
+
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmpHALStatus = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+
+/**
+ * @brief Configures the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+
+ uint32_t tmpAWDHighThresholdShifted;
+ uint32_t tmpAWDLowThresholdShifted;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+ /* Verify if threshold is within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+ if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
+ ADC_CFGR1_AWDEN |
+ ADC_CFGR1_AWDCH );
+
+ hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
+ __HAL_ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) );
+
+ /* Shift the offset in function of the selected ADC resolution: Thresholds*/
+ /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ /* Set the high and low thresholds */
+ hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
+ hadc->Instance->TR |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ /* Clear the ADC Analog watchdog flag (in case of left enabled by */
+ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+ /* or HAL_ADC_PollForEvent(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD);
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ }
+ /* If a conversion is on going on regular group, no update could be done */
+ /* on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmpHALStatus = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the ADC state
+ * @param hadc: ADC handle
+ * @retval HAL state
+ */
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code
+ * @param hadc: ADC handle
+ * @retval ADC Error Code
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time. */
+ /* Delay fixed to worst case: maximum CPU frequency */
+ while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES)
+ {
+ wait_loop_index++;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively enabled */
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Verification if ADC is not already disabled: */
+ /* @Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if (__HAL_ADC_IS_ENABLED(hadc) != RESET )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Stop ADC conversion.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped to disable the ADC.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification if ADC is not already stopped on regular group to bypass */
+ /* this function if not needed. */
+ if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
+ {
+
+ /* Stop potential conversion on going on regular group */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
+ {
+ /* Stop conversions on regular group */
+ hadc->Instance->CR |= ADC_CR_ADSTP;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h
new file mode 100644
index 000000000..ee6dd66a4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h
@@ -0,0 +1,951 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_ADC_H
+#define __STM32F0xx_HAL_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of ADC initialization and regular group
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
+ * - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler.
+ This parameter can be a value of @ref ADC_ClockPrescaler
+ Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
+ Note: This parameter can be modified only if the ADC is disabled */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular group.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+ If only 1 channel is set: Conversion is performed in single mode.
+ If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
+ This parameter can be a value of @ref ADC_Scan_mode */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADC_EOCSelection. */
+ uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
+ conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
+ This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
+ and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
+ uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+ This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
+ This parameter can be set to ENABLE or DISABLE.
+ Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE
+ Note: Number of discontinuous ranks increment is fixed to one-by-one. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADC_External_trigger_source_Regular */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
+ This parameter has an effect on regular group only, including in DMA mode.
+ This parameter can be a value of @ref ADC_Overrun */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled or enabled without conversion on going on regular group.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
+ On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ This parameter can be a value of @ref ADC_rank */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
+ This parameter can be a value of @ref ADC_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief HAL ADC state machine: ADC States structure definition
+ */
+typedef enum
+{
+ HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
+ HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
+ HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
+ HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
+ HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
+ HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
+ HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
+ HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
+ HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
+ HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
+ HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
+ HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
+}HAL_ADC_StateTypeDef;
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
+ * @{
+ */
+#define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */
+
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Resolution ADC Resolution
+ * @{
+ */
+#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
+ ((RESOLUTION) == ADC_RESOLUTION10b) || \
+ ((RESOLUTION) == ADC_RESOLUTION8b) || \
+ ((RESOLUTION) == ADC_RESOLUTION6b) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Data_align ADC Data_align
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC Scan mode
+ * @{
+ */
+/* Note: Scan mode values must be compatible with other STM32 devices having */
+/* a configurable sequencer. */
+/* Scan direction setting values are defined by taking in account */
+/* already defined values for other STM32 devices: */
+/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
+/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
+/* Scan direction forward is considered as default setting equivalent */
+/* to scan enable. */
+/* Scan direction backward is considered as additional setting. */
+/* In case of migration from another STM32 device, the user will be */
+/* warned of change of setting choices with assert check. */
+#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+ ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
+ * @{
+ */
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
+
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
+ * @{
+ */
+
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC EOCSelection
+ * @{
+ */
+#define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+#define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == EOC_SEQ_CONV) || \
+ ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Overrun ADC Overrun
+ * @{
+ */
+#define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000)
+#define OVR_DATA_PRESERVED ((uint32_t)0x00000001)
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \
+ ((OVR) == OVR_DATA_OVERWRITTEN) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels ADC channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+/* Note: Channels are used by bitfields for setting of channel selection */
+/* (register ADC_CHSELR) and used by number for setting of analog watchdog */
+/* channel (bits AWDCH in register ADC_CFGR1). */
+/* Channels are defined with decimal numbers and converted them to bitfields */
+/* when needed. */
+#define ADC_CHANNEL_0 ((uint32_t) 0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t) 0x00000001)
+#define ADC_CHANNEL_2 ((uint32_t) 0x00000002)
+#define ADC_CHANNEL_3 ((uint32_t) 0x00000003)
+#define ADC_CHANNEL_4 ((uint32_t) 0x00000004)
+#define ADC_CHANNEL_5 ((uint32_t) 0x00000005)
+#define ADC_CHANNEL_6 ((uint32_t) 0x00000006)
+#define ADC_CHANNEL_7 ((uint32_t) 0x00000007)
+#define ADC_CHANNEL_8 ((uint32_t) 0x00000008)
+#define ADC_CHANNEL_9 ((uint32_t) 0x00000009)
+#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A)
+#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B)
+#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C)
+#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D)
+#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E)
+#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F)
+#define ADC_CHANNEL_16 ((uint32_t) 0x00000010)
+#define ADC_CHANNEL_17 ((uint32_t) 0x00000011)
+#define ADC_CHANNEL_18 ((uint32_t) 0x00000012)
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_rank ADC rank
+ * @{
+ */
+#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((WATCHDOG) == ADC_RANK_NONE) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times ADC sampling times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
+
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */
+#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
+ ((EVENT) == OVR_EVENT) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+
+#define ADC_FLAG_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY )
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_range_verification ADC range verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank_verification ADC regular rank verification
+ * @{
+ */
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */
+/* performed automatically by hardware and flag ADC_FLAG_RDY is not */
+/* set. */
+#define __HAL_ADC_IS_ENABLED(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \
+ ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+
+/**
+ * @brief Check if no conversion on going on regular group
+ * @param __HANDLE__: ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Returns resolution bits in CFGR1 register: RES[1:0].
+ * Returned value is among parameters to @ref ADC_Resolution.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+
+/**
+ * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
+ * Returned value is among parameters to @ref ADC_Resolution.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * @retval State ofinterruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \
+ )? SET : RESET \
+ )
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+
+/**
+ * @brief Configure the channel number into channel selection register
+ * @param _CHANNEL_: ADC Channel
+ * @retval None
+ */
+/* This function converts ADC channels from numbers (see defgroup ADC_channels)
+ to bitfields, to get the equivalence of CMSIS channels:
+ ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0)
+ ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1)
+ ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2)
+ ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3)
+ ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4)
+ ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5)
+ ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6)
+ ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7)
+ ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8)
+ ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9)
+ ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10)
+ ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11)
+ ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12)
+ ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13)
+ ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14)
+ ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15)
+ ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16)
+ ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17)
+ ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18)
+*/
+#define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Set the Analog Watchdog 1 channel.
+ * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26)
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for regular group
+ * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
+
+/**
+ * @brief Enable the ADC auto off mode.
+ * @param _AUTOOFF_: Auto off bit enable or disable.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15)
+
+/**
+ * @brief Enable the ADC auto delay mode.
+ * @param _AUTOWAIT_: Auto delay bit enable or disable.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
+
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_: Overrun mode.
+ * @retval Overun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
+/* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */
+/* default case to be compliant with other STM32 devices. */
+#define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR1_OVRMOD) : (0x00000000) \
+ )
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_: Scan conversion mode.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_) \
+ ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
+ )? (ADC_CFGR1_SCANDIR) : (0x00000000) \
+ )
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
+
+/**
+ * @brief Configure the analog watchdog high threshold into register TR.
+ * @param _Threshold_: Threshold value
+ * @retval None
+ */
+#define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
+
+/**
+ * @brief Enable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+ */
+#define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_ADCAL | ADC_CR_ADSTP | \
+ ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
+ ) == RESET \
+ ) ? SET : RESET)
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
+ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+ } while(0)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+ */
+#define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
+ ) ? SET : RESET)
+
+/**
+ * @brief Shift the AWD threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__: ADC handle
+ * @param _Threshold_: Value to be shifted
+ * @retval None
+ */
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f0xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
+
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c
new file mode 100644
index 000000000..99f6a0f72
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c
@@ -0,0 +1,265 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Calibration (ADC automatic self-calibration)
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC specific features #####
+ ==============================================================================
+ [..]
+ (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
+
+ (#) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (#) Single and continuous conversion modes.
+
+ (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
+
+ (#) Data alignment with in-built data coherency.
+
+ (#) Programmable sampling time.
+
+ (#) ADC conversion group Regular.
+
+ (#) External trigger (timer or EXTI) with configurable polarity.
+
+ (#) DMA request generation for transfer of conversions data of regular group.
+
+ (#) ADC calibration
+
+ (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+
+ (#) ADC input range: from Vref minud (connected to Vssa) to Vref plus(connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Enable the ADC interface
+ As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
+ at RCC top level: clock source and clock prescaler.
+ Two possible clock sources: synchronous clock derived from APB clock
+ or asynchronous clock derived from ADC dedicated HSI RC oscillator
+ 14MHz.
+ Example:
+ __ADC1_CLK_ENABLE(); (mandatory)
+
+ HI14 enable or let under control of ADC: (optional)
+
+ RCC_OscInitTypeDef RCC_OscInitStructure;
+ RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
+ RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
+ RCC_OscInitStructure.PLL... (optional if used for system clock)
+ HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ Parameter "HSI14State" must be set either:
+ - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
+ the HSI14 oscillator enable/disable (if not used to supply the main
+ system clock): feature used if ADC mode LowPowerAutoPowerOff is
+ enabled.
+ - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
+ always enabled: can be used to supply the main system clock.
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
+
+ (#) Configure the ADC parameters (conversion resolution, data alignment,
+ continuous mode, ...) using the HAL_ADC_Init() function.
+
+ (#) Activate the ADC peripheral using one of the start functions:
+ HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
+
+ *** Regular channels group configuration ***
+ ============================================
+ [..]
+ (+) To configure the ADC regular channels group features, use
+ HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
+ (+) To activate the continuous mode, use the HAL_ADC_Init() function.
+ (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+
+ *** DMA for Regular channels group features configuration ***
+ =============================================================
+ [..]
+ (+) To enable the DMA mode for regular channels group, use the
+ HAL_ADC_Start_DMA() function.
+ (+) To enable the generation of DMA requests continuously at the end of
+ the last DMA transfer, use the HAL_ADC_Init() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx Extended HAL Module Driver
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC calibration, enable settling time, disable */
+ /* settling time. */
+ /* Values defined to be higher than worst cases: low clock frequency, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4. */
+ /* Unit: ms */
+ #define ADC_DISABLE_TIMEOUT 2
+ #define ADC_CALIBRATION_TIMEOUT 2
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Perform the ADC calibration.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @note Calibration factor can be read after calibration, using function
+ * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ uint32_t tickstart=0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+ if (__HAL_ADC_IS_ENABLED(hadc) == RESET )
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+
+ /* Start ADC calibration */
+ hadc->Instance->CR |= ADC_CR_ADCAL;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmpHALStatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h
new file mode 100644
index 000000000..7e5801059
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h
@@ -0,0 +1,98 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of ADC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_ADC_EX_H
+#define __STM32F0xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c
new file mode 100644
index 000000000..263c2f730
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c
@@ -0,0 +1,1400 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_can.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using __CAN_CLK_ENABLE();
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init();
+
+ (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN HAL Module Driver
+ * @brief CAN driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define HAL_CAN_DEFAULT_TIMEOUT 10
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
+ uint32_t tickstart = 0;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+ /* Get tickstart */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+ ((uint32_t)hcan->Init.SJW) | \
+ ((uint32_t)hcan->Init.BS1) | \
+ ((uint32_t)hcan->Init.BS2) | \
+ ((uint32_t)hcan->Init.Prescaler - 1);
+
+ /* Request leave initialisation */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ status = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(status == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+
+ /* Initialisation mode for the filter */
+ hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+ /* Filter Deactivation */
+ hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ hcan->Instance->FS1R |= filternbrbitpos;
+ /* 32-bit identifier or First 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
+ }
+
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ hcan->Instance->FA1R |= filternbrbitpos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = 0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = 1;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmitmailbox = 2;
+ }
+
+ if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[0]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[4]));
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = 0;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = 1;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmitmailbox = 2;
+ }
+
+ if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[0]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[4]));
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Enable Error warning Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Enable Error passive Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Enable Bus-off Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Enable Last error code Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+
+ /* Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO number.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO number.
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable Error warning Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Enable Error passive Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Enable Bus-off Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Enable Last error code Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ }
+
+ /* Check End of reception flag for FIFO0 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ /* Check End of reception flag for FIFO1 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Check Error Warning Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-Off Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ /* No need for clear of Bus-Off Flag as read-only */
+ }
+
+ /* Check Last error code Flag */
+ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions CAN Private Functions
+ * @brief CAN Frame message Rx/Tx functions
+ *
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable Error warning Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Disable Error passive Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Disable Bus-off Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Disable Last error code Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Disable Error warning Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Disable Error passive Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Disable Bus-off Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Disable Last error code Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Disable CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h
new file mode 100644
index 000000000..6aec5253f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h
@@ -0,0 +1,810 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_can.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CAN_H
+#define __STM32F0xx_HAL_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN CAN HAL Module Driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code
+ This parameter can be a value of @ref CAN_Error */
+
+}CAN_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error CAN Error
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */
+#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */
+#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */
+#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */
+#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN operating mode
+ * @{
+ */
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width
+ * @{
+ */
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler CAN clock prescaler
+ * @{
+ */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number CAN filter number
+ * @{
+ */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN filter mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN filter scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN CAN Start bank filter for slave CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx CAN Tx
+ * @{
+ */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN identifier type
+ * @{
+ */
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN remote transmission request
+ * @{
+ */
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants CAN transmit constants
+ * @{
+ */
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts CAN interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Timeouts CAN Timeouts
+* @{
+*/
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes CAN Mailboxes
+* @{
+*/
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__: CAN handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disables the DBG Freeze for CAN.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c
new file mode 100644
index 000000000..fc05c3582
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c
@@ -0,0 +1,1119 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_cec.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief CEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization function
+ * + IO operation function
+ * + Peripheral Control function
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follows:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (++) Enable the CEC interface clock.
+ (++) CEC pins configuration:
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ -@@- The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F042x6) || defined(STM32F048xx) ||\
+ defined(STM32F051x8) || defined(STM32F058xx) ||\
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
+ defined(STM32F091xC) || defined (STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CEC CEC HAL Module Driver
+ * @brief HAL CEC module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
+ | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
+ | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization/de-initialization function
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tmpreg = 0x0;
+
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+
+
+ if(hcec->State == HAL_CEC_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ tmpreg = hcec->Init.SignalFreeTime;
+ tmpreg |= hcec->Init.Tolerance;
+ tmpreg |= hcec->Init.BRERxStop;
+ tmpreg |= hcec->Init.BREErrorBitGen;
+ tmpreg |= hcec->Init.LBPEErrorBitGen;
+ tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
+ tmpreg |= hcec->Init.SignalFreeTimeOption;
+ tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
+ tmpreg |= hcec->Init.ListenMode;
+
+ /* Write to CEC Control Register */
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->State = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->State = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 IO operation function
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non Blocking mode: The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode API s are :
+ (+) HAL_CEC_Transmit()
+ (+) HAL_CEC_Receive()
+
+ (#) Non-Blocking mode API s with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_Receive_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in blocking mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint8_t temp = 0;
+ uint32_t tempisr = 0;
+ uint32_t tickstart = 0;
+
+ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if((pData == NULL ) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+
+ hcec->TxXferCount = Size;
+
+ /* case no data to be sent, sender is only pinging the system */
+ if (Size == 0)
+ {
+ /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ while (hcec->TxXferCount > 0)
+ {
+ hcec->TxXferCount--;
+
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_TXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check whether error occured while waiting for TXBR to be set:
+ * has Tx underrun occurred ?
+ * has Tx error occurred ?
+ * has Tx Missing Acknowledge error occurred ?
+ * has Arbitration Loss error occurred ? */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+ /* TXBR to clear BEFORE writing TXDR register */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ if (hcec->TxXferCount == 0)
+ {
+ /* if last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ hcec->Instance->TXDR = *pData++;
+
+ /* error check after TX byte write up */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* end while (while (hcec->TxXferCount > 0)) */
+
+
+ /* if no error up to this point, check that transmission is
+ * complete, that is wait until TXEOM is reset */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Final error check once all bytes have been transmitted */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @param Timeout: Timeout duration.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0;
+
+ if (hcec->State == HAL_CEC_STATE_READY)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if (pData == NULL )
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hcec->RxXferSize = 0;
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+
+ /* Rx loop until CEC_ISR_RXEND is set */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))
+ {
+ tickstart = HAL_GetTick();
+ /* Wait for next byte to be received */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ /* any error so far ?
+ * has Rx Missing Acknowledge occurred ?
+ * has Rx Long Bit Period error occurred ?
+ * has Rx Short Bit Period error occurred ?
+ * has Rx Bit Rising error occurred ?
+ * has Rx Overrun error occurred ? */
+ temp = (uint32_t) (hcec->Instance->ISR);
+ if ((temp & (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = temp;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
+
+
+ /* read received data */
+ *pData++ = hcec->Instance->RXDR;
+ temp = (uint32_t) (hcec->Instance->ISR);
+ /* end of message ? */
+ if ((temp & CEC_ISR_RXEND) != 0)
+ {
+ assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND);
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+
+ /* clear Rx-Byte Received flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR);
+ /* increment payload byte counter */
+ hcec->RxXferSize++;
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
+
+ /* if the instructions below are executed, it means RXEND was set when RXBR was
+ * set for the first time:
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
+ * loop has not been executed and this means a single byte has been sent */
+ *pData++ = hcec->Instance->RXDR;
+ /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
+ hcec->RxXferSize = 0;
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ uint8_t temp = 0;
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ if((pData == NULL ) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following two CEC Transmission interrupts as
+ * well as the following CEC Transmission Errors interrupts:
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* in case of no payload (Size = 0), sender is only pinging the system;
+ * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ return HAL_OK;
+ }
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * Note that the received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
+{
+ if(hcec->State == HAL_CEC_STATE_READY)
+ {
+ if(pData == NULL )
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->RxXferSize = 0;
+ hcec->pRxBuffPtr = pData;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ /* the IP is moving to a ready to receive state */
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following CEC Reception Error Interrupts:
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the following two CEC Reception interrupts:
+ * Rx Byte Received IT
+ * End of Reception IT */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RXBRIE|CEC_IER_RXENDIE);
+
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec: CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+ /* save interrupts register for further error or interrupts handling purposes */
+ hcec->ErrorCode = hcec->Instance->ISR;
+ /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXACKEIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC transmit error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXERRIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXERR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX underrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXUDRIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXUDR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX arbitration error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_ARBLSTIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_ARBLST);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX overrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXOVRIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXOVR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX bit rising error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_BREIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_BRE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX short bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_SBPEIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_SBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX long bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_LBPEIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_LBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXACKEIE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
+ {
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXBRIE) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+ /* CEC RX end received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXENDIE) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+
+ /* CEC TX byte request interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXBRIE) != RESET))
+ {
+ /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+ /* CEC TX end interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXENDIE) != RESET))
+ {
+ /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+}
+
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CEC state
+ * @param hcec: CEC handle
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ return hcec->State;
+}
+
+/**
+* @brief Return the CEC error code
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+* @retval CEC Error Code
+*/
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
+{
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND);
+
+ /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */
+ if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IER_RXBRIE|CEC_IER_RXENDIE) ) != RESET)
+ {
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+ }
+ else
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tempisr;
+
+ /* Three different conditions are tested to carry out the RX IT processing:
+ * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
+ * the reception of the first byte is starting
+ * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
+ * and a new byte is being received
+ * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
+ * but has been interrupted by a new message reception or discarded due to
+ * arbitration loss: the reception of the first or higher priority message
+ * (the arbitration winner) is starting */
+ if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_TX))
+ {
+ /* reception is starting */
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ tempisr = (uint32_t) (hcec->Instance->ISR);
+ if ((tempisr & CEC_ISR_RXBR) != 0)
+ {
+ /* read received byte */
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
+ /* if last byte has been received */
+ if ((tempisr & CEC_ISR_RXEND) != 0)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR|CEC_ISR_RXEND);
+ /* RX interrupts are not disabled at this point.
+ * Indeed, to disable the IT, the IP must be disabled first
+ * which resets the TXSOM flag. In case of arbitration loss,
+ * this leads to a transmission abort.
+ * Therefore, RX interruptions disabling if so required,
+ * is done in HAL_CEC_RxCpltCallback */
+
+ /* IP state is moved to READY.
+ * If the IP must remain in standby mode to listen
+ * any new message, it is up to HAL_CEC_RxCpltCallback
+ * to move it again to HAL_CEC_STATE_STANDBY_RX */
+ hcec->State = HAL_CEC_STATE_READY;
+
+ HAL_CEC_RxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXBR);
+
+ hcec->RxXferSize++;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */
+ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
+ /* defined(STM32F091xC) || defined (STM32F098xx) */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h
new file mode 100644
index 000000000..4c52b0877
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h
@@ -0,0 +1,598 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_cec.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CEC_H
+#define __STM32F0xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F042x6) || defined(STM32F048xx) ||\
+ defined(STM32F051x8) || defined(STM32F058xx) ||\
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
+ defined(STM32F091xC) || defined(STM32F098xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC CEC HAL Module Driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief HAL Error structures definition
+ */
+typedef enum
+{
+ HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
+ HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */
+ HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */
+ HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */
+ HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */
+ HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */
+ HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */
+ HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */
+ HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */
+ HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+}
+HAL_CEC_ErrorTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /* CEC registers base address */
+
+ CEC_InitTypeDef Init; /* CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /* CEC Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
+
+ __IO uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
+ in case error is reported */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ HAL_CEC_StateTypeDef State; /* CEC communication state */
+
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
+#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
+#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \
+ ((RXTOL) == CEC_EXTENDED_TOLERANCE))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
+#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((BRERXSTOP) == CEC_RX_STOP_ON_BRE))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
+#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
+#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
+#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \
+ ((SFTOP) == CEC_SFT_START_ON_TX_RX_END))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
+#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \
+ ((MODE) == CEC_FULL_LISTENING_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle state
+ * @param __HANDLE__: CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_ISR_RXBR : Rx-Byte Received
+ * @arg CEC_ISR_RXEND : End of Reception
+ * @arg CEC_ISR_RXOVR : Rx Overrun
+ * @arg CEC_ISR_BRE : Rx Bit Rising Error
+ * @arg CEC_ISR_SBPE : Rx Short Bit Period Error
+ * @arg CEC_ISR_LBPE : Rx Long Bit Period Error
+ * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
+ * @arg CEC_ISR_ARBLST : Arbitration lost
+ * @arg CEC_ISR_TXBR : Tx-Byte Request
+ * @arg CEC_ISR_TXEND : End of Transmission
+ * @arg CEC_ISR_TXUDR : Tx-buffer Underrun
+ * @arg CEC_ISR_TXERR : Tx Error
+ * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+
+/** @brief Clears the interrupt or status flag when raised (write at 1)
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_ISR_RXBR : Rx-Byte Received
+ * @arg CEC_ISR_RXEND : End of Reception
+ * @arg CEC_ISR_RXOVR : Rx Overrun
+ * @arg CEC_ISR_BRE : Rx Bit Rising Error
+ * @arg CEC_ISR_SBPE : Rx Short Bit Period Error
+ * @arg CEC_ISR_LBPE : Rx Long Bit Period Error
+ * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
+ * @arg CEC_ISR_ARBLST : Arbitration lost
+ * @arg CEC_ISR_TXBR : Tx-Byte Request
+ * @arg CEC_ISR_TXEND : End of Transmission
+ * @arg CEC_ISR_TXUDR : Tx-buffer Underrun
+ * @arg CEC_ISR_TXERR : Tx Error
+ * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__))
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
+ * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
+ * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
+ * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
+ * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
+ * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
+ * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
+ * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
+ * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
+ * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
+ * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
+ * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
+ * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
+ * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
+ * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
+ * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
+ * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
+ * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
+ * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
+ * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
+ * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
+ * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
+ * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
+ * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
+ * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
+ * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
+ * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
+ * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
+ * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
+ * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
+ * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
+ * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
+ * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
+ * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
+ * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
+ * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
+ * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+/** @addtogroup CEC_Exported_Functions_Group1 Initialization/de-initialization function
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2 IO operation function
+ * @brief CEC Transmit/Receive functions
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F042x6) || defined(STM32F048xx) || */
+ /* defined(STM32F051x8) || defined(STM32F058xx) || */
+ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
+ /* defined(STM32F091xC) || defined(STM32F098xx) */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c
new file mode 100644
index 000000000..88e46e777
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c
@@ -0,0 +1,695 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_comp.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief COMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the COMP peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+================================================================================
+ ##### COMP Peripheral features #####
+================================================================================
+
+ [..]
+ The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
+ (#) The non inverting input and inverting input can be set to GPIO pins
+ as shown in table1. COMP Inputs below.
+
+ (#) The COMP output is available using HAL_COMP_GetOutputLevel()
+ and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
+
+ (#) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3)
+ Refer to table 3. COMP Outputs redirection to embedded timers below.
+
+ (#) The comparators COMP1 and COMP2 can be combined in window mode.
+
+ (#) The comparators have interrupt capability with wake-up
+ from Sleep and Stop modes (through the EXTI controller):
+ (++) COMP1 is internally connected to EXTI Line 21
+ (++) COMP2 is internally connected to EXTI Line 22
+ From the corresponding IRQ handler, the right interrupt source can be retrieved with the
+ macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are:
+ (++) COMP_EXTI_LINE_COMP1_EVENT
+ (++) COMP_EXTI_LINE_COMP2_EVENT
+
+
+[..] Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
+ +--------------------------------------------------+
+ | | | COMP1 | COMP2 |
+ |-----------------|----------------|---------------|
+ | | 1/4 VREFINT | OK | OK |
+ | | 1/2 VREFINT | OK | OK |
+ | | 3/4 VREFINT | OK | OK |
+ | Inverting Input | VREFINT | OK | OK |
+ | | DAC1 OUT (PA4) | OK | OK |
+ | | DAC2 OUT (PA5) | OK | OK |
+ | | IO1 | PA0 | PA2 |
+ |-----------------|----------------|-------|-------|
+ | Non Inverting | | PA1 | PA3 |
+ | Input | | | |
+ +--------------------------------------------------+
+
+ [..] Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
+ +---------------+
+ | COMP1 | COMP2 |
+ |-------|-------|
+ | PA0 | PA2 |
+ | PA6 | PA7 |
+ | PA11 | PA12 |
+ +---------------+
+
+ [..] Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
+ +---------------------------------+
+ | COMP1 | COMP2 |
+ |----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN |
+ | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR |
+ | | |
+ | TIM1 IC1 | TIM1 IC1 |
+ | | |
+ | TIM2 IC4 | TIM2 IC4 |
+ | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR |
+ | | |
+ | TIM3 IC1 | TIM3 IC1 |
+ | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR |
+ +---------------------------------+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ This driver provides functions to configure and program the Comparators of STM32F05x, STM32F07x and STM32F09x devices.
+
+ To use the comparator, perform the following steps:
+
+ (#) Fill in the HAL_COMP_MspInit() to
+ (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
+ (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
+ output to the GPIO pin
+ (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
+ selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+ interrupt vector using HAL_NVIC_EnableIRQ() function.
+
+ (#) Configure the comparator using HAL_COMP_Init() function:
+ (++) Select the inverting input
+ (++) Select the non inverting input
+ (++) Select the output polarity
+ (++) Select the output redirection
+ (++) Select the hysteresis level
+ (++) Select the power mode
+ (++) Select the event/interrupt mode
+
+ (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode
+
+ (#) Read the comparator output level with HAL_COMP_GetOutputLevel()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined (STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup COMP COMP HAL Module Driver
+ * @brief COMP HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+ * @{
+ */
+/* CSR register reset value */
+#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+/* CSR register masks */
+#define COMP_CSR_RESET_PARAMETERS_MASK ((uint32_t)0x00003FFF)
+#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0x00003FFE)
+/* CSR COMPx non inverting input mask */
+#define COMP_CSR_COMPxNONINSEL_MASK ((uint16_t)COMP_CSR_COMP1SW1)
+/* CSR COMP2 shift */
+#define COMP_CSR_COMP1_SHIFT 0U
+#define COMP_CSR_COMP2_SHIFT 16U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions to initialize and de-initialize comparators
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the COMP according to the specified
+ * parameters in the COMP_InitTypeDef and create the associated handle.
+ * @note If the selected comparator is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
+ assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
+ assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
+ assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+ assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+ assert_param(IS_COMP_MODE(hcomp->Init.Mode));
+
+ if(hcomp->Init.NonInvertingInput == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)
+ {
+ assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance));
+ }
+
+ if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
+ {
+ assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
+ }
+
+ if(hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ /* Init SYSCFG and the low level hardware to access comparators */
+ __SYSCFG_CLK_ENABLE();
+
+ HAL_COMP_MspInit(hcomp);
+ }
+
+ /* Set COMP parameters */
+ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
+ /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
+ /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
+ /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
+ /* Set COMPxMODE bits according to hcomp->Init.Mode value */
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ MODIFY_REG(COMP->CSR,
+ (uint32_t)(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
+ COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
+ COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift,
+ (hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ hcomp->Init.Output | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Hysteresis | \
+ hcomp->Init.Mode) << regshift);
+
+ if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
+ {
+ COMP->CSR |= COMP_CSR_WNDWEN;
+ }
+
+ /* Initialize the COMP state*/
+ if(hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitializes the COMP peripheral
+ * @note Deinitialization can't be performed if the COMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set COMP_CSR register to reset value for the corresponding COMP instance */
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_RESET_PARAMETERS_MASK << regshift,
+ COMP_CSR_RESET_VALUE << regshift);
+
+ /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+ HAL_COMP_MspDeInit(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initializes the COMP MSP.
+ * @param hcomp: COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_COMP_MspInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes COMP MSP.
+ * @param hcomp: COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_COMP_MspDeInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the COMP data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the comparator
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Enable the selected comparator */
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_BUSY)
+ {
+ /* Disable the selected comparator */
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);
+
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enables the interrupt and starts the comparator
+ * @param hcomp: COMP handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0;
+
+ /* Check the parameter */
+ assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+
+ status = HAL_COMP_Start(hcomp);
+ if(status == HAL_OK)
+ {
+ /* Check the Exti Line output configuration */
+ extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
+ /* Configure the rising edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
+ {
+ __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline);
+ }
+ else
+ {
+ __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline);
+ }
+ /* Configure the falling edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
+ {
+ __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline);
+ }
+ else
+ {
+ __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline);
+ }
+ /* Enable Exti interrupt mode */
+ __HAL_COMP_EXTI_ENABLE_IT(extiline);
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the interrupt and Stop the comparator
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the Exti Line interrupt mode */
+ __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance));
+
+ status = HAL_COMP_Stop(hcomp);
+
+ return status;
+}
+
+/**
+ * @brief Comparator IRQ Handler
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Check COMP Exti flag */
+ if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET)
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
+
+ /* COMP trigger user callback */
+ HAL_COMP_TriggerCallback(hcomp);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the COMP data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected comparator configuration.
+ * @param hcomp: COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set lock flag */
+ hcomp->State |= COMP_STATE_BIT_LOCK;
+
+ /* Set the lock bit corresponding to selected comparator */
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the output level (high or low) of the selected comparator.
+ * The output level depends on the selected polarity.
+ * If the polarity is not inverted:
+ * - Comparator output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * If the polarity is inverted:
+ * - Comparator output is high when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is low when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @param hcomp: COMP handle
+ * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
+ *
+ */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t level=0;
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT;
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->Instance == COMP2)
+ {
+ regshift = COMP_CSR_COMP2_SHIFT;
+ }
+ level = READ_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxOUT << regshift);
+
+ if(level != 0)
+ {
+ return(COMP_OUTPUTLEVEL_HIGH);
+ }
+ return(COMP_OUTPUTLEVEL_LOW);
+}
+
+/**
+ * @brief Comparator callback.
+ * @param hcomp: COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_TriggerCallback should be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the COMP state
+ * @param hcomp : COMP handle
+ * @retval HAL state
+ */
+uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the COMP handle allocation */
+ if(hcomp == NULL)
+ {
+ return HAL_COMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ return hcomp->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || defined (STM32F098xx) */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h
new file mode 100644
index 000000000..82cf797ad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h
@@ -0,0 +1,479 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_comp.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of COMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_COMP_H
+#define __STM32F0xx_HAL_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup COMP COMP HAL Module Driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
+ This parameter can be a value of @ref COMP_InvertingInput */
+
+ uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
+ This parameter can be a value of @ref COMP_NonInvertingInput */
+
+ uint32_t Output; /*!< Selects the output redirection of the comparator.
+ This parameter can be a value of @ref COMP_Output */
+
+ uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
+ This parameter can be a value of @ref COMP_OutputPolarity */
+
+ uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
+ This parameter can be a value of @ref COMP_Hysteresis */
+
+ uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator
+ to adjust the speed/consumption.
+ This parameter can be a value of @ref COMP_Mode */
+
+ uint32_t WindowMode; /*!< Selects the window mode of the comparator 1 & 2.
+ This parameter can be a value of @ref COMP_WindowMode */
+
+ uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
+ This parameter can be a value of @ref COMP_TriggerMode */
+
+}COMP_InitTypeDef;
+
+/**
+ * @brief COMP Handle Structure definition
+ */
+typedef struct
+{
+ COMP_TypeDef *Instance; /*!< Register base address */
+ COMP_InitTypeDef Init; /*!< COMP required parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO uint32_t State; /*!< COMP communication state
+ This parameter can be a value of @ref COMP_State */
+}COMP_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_State COMP State
+ * @{
+ */
+#define HAL_COMP_STATE_RESET ((uint32_t)0x00000000) /*!< COMP not yet initialized or disabled */
+#define HAL_COMP_STATE_READY ((uint32_t)0x00000001) /*!< COMP initialized and ready for use */
+#define HAL_COMP_STATE_READY_LOCKED ((uint32_t)0x00000011) /*!< COMP initialized but the configuration is locked */
+#define HAL_COMP_STATE_BUSY ((uint32_t)0x00000002) /*!< COMP is running */
+#define HAL_COMP_STATE_BUSY_LOCKED ((uint32_t)0x00000012) /*!< COMP is running and the configuration is locked */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputPolarity COMP OutputPolarity
+ * @{
+ */
+#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
+ ((POL) == COMP_OUTPUTPOL_INVERTED))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Hysteresis COMP Hysteresis
+ * @{
+ */
+#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH COMP_CSR_COMP1HYST /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Mode COMP Mode
+ * @{
+ */
+/* Please refer to the electrical characteristics in the device datasheet for
+ the power consumption values */
+#define COMP_MODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */
+#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
+#define COMP_MODE_LOWPOWER COMP_CSR_COMP1MODE_1 /*!< Low power mode */
+#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_InvertingInput COMP InvertingInput
+ * @{
+ */
+
+#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMP1INSEL_1|COMP_CSR_COMP1INSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC_OUT1 (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1SWITCHCLOSED (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1SW1) /*!< DAC_OUT1 (PA4) connected to comparator inverting input
+ and close switch (PA0 for COMP1 only) */
+#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_0) /*!< DAC_OUT2 (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_1) /*!< IO (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_NonInvertingInput COMP NonInvertingInput
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2)
+ connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Output COMP Output
+ * @{
+ */
+
+/* Output Redirection common for COMP1 and COMP2 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM1OCREFCLR (COMP_CSR_COMP1OUTSEL_1|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM2OCREFCLR (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel COMP OutputLevel
+ * @{
+ */
+/* When output polarity is not inverted, comparator output is low when
+ the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
+/* When output polarity is not inverted, comparator output is high when
+ the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMP1OUT
+/**
+ * @}
+ */
+
+/** @defgroup COMP_TriggerMode COMP TriggerMode
+ * @{
+ */
+#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \
+ ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
+ ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \
+ ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_WindowMode COMP WindowMode
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2
+ is connected to the non inverting input of comparator 1 (PA1) */
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent
+ * Elements values convention: XXXX0000
+ * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register
+ * @{
+ */
+#define COMP_EXTI_LINE_COMP1_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Lock COMP Lock
+ * @{
+ */
+#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
+#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK
+
+#define COMP_STATE_BIT_LOCK ((uint32_t)0x10)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset COMP handle state
+ * @param __HANDLE__: COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __FLAG__: specifies the COMP Exti sources to be checked.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval The state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (EXTI->PR & (__FLAG__))
+
+/**
+ * @brief Clear the COMP Exti flags.
+ * @param __FLAG__: specifies the COMP Exti sources to be cleared.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+
+/**
+ * @brief Enable the COMP Exti Line.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the COMP Exti Line.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+ * @brief Enable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (EXTI->RTSR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (EXTI->RTSR &= ~(__EXTILINE__))
+
+/**
+ * @brief Enable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (EXTI->FTSR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMP_ExtiLineEvent
+ * @retval None.
+ */
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (EXTI->FTSR &= ~(__EXTILINE__))
+
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMP_ExtiLineEvent
+ */
+#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1_EVENT : \
+ COMP_EXTI_LINE_COMP2_EVENT)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions COMP Exported Functions
+ * @{
+ */
+/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Exported_Functions_Group2 I/O operation functions
+ * @brief Data transfers functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+
+/* Callback in Interrupt mode */
+void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h
new file mode 100644
index 000000000..c39e929da
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CONF_H
+#define __STM32F0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ######################### Oscillator Values adaptation ################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator for ADC (HSI14) value.
+ */
+#if !defined (HSI14_VALUE)
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* HSI14_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator for USB (HSI48) value.
+ */
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
+ /* Warning: Must be set to higher priority for HAL_Delay() */
+ /* and HAL_GetTick() usage under interrupt context */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 0
+#define DATA_CACHE_ENABLE 0
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/*#define USE_FULL_ASSERT 1*/
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f0xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c
new file mode 100644
index 000000000..26af9a410
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_cortex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M0 exceptions are managed by CMSIS functions.
+ (#) Enable and Configure the priority of the selected IRQ Channels.
+ The priority can be 0..3.
+
+ -@- Lower priority values gives higher priority.
+ -@- Priority Order:
+ (#@) Lowest priority.
+ (#@) Lowest hardware priority (IRQn position).
+
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x03).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f0xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX HAL module driver
+ * @brief CORTEX CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 3.
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: The subpriority level for the IRQ channel.
+ * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
+ * no subpriority supported in Cortex M0 based products.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ NVIC_SetPriority(IRQn,PreemptPriority);
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval None
+ */
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
+{
+ /* Get priority for Cortex-M system or device specific interrupts */
+ return NVIC_GetPriority(IRQn);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h
new file mode 100644
index 000000000..28f2be05d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h
@@ -0,0 +1,166 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CORTEX_H
+#define __STM32F0xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX CORTEX HAL module driver
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Priority CORTEX Priority
+ * @{
+ */
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macro CORTEX Exported Macro
+ * @{
+ */
+
+/** @brief Configures the SysTick clock source.
+ * @param __CLKSRC__: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
+ do { \
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
+ { \
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
+ } \
+ else \
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *******************************/
+void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ * @{
+ */
+
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c
new file mode 100644
index 000000000..ba5e364b1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c
@@ -0,0 +1,506 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_crc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (#) Initialize CRC calculator
+ (++)specify generating polynomial (IP default or non-default one)
+ (++)specify initialization value (IP default or non-default one)
+ (++)specify input data format
+ (++)specify input or output data inversion mode if any
+ (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC HAL module driver
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP
+ (+) DeInitialize CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and creates the associated handle.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Extended initialization: if programmable polynomial feature is
+ applicable to device, set default or non-default generating
+ polynomial according to hcrc->Init parameters.
+ If feature is non-applicable to device in use, HAL_CRCEx_Init straight
+ away reports HAL_OK. */
+ if (HAL_CRCEx_Init(hcrc) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRC peripheral.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if(hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using combination of the previous CRC value and the new one.
+
+ or
+
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRC state.
+ * @param hcrc: CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the IP */
+ for(i = 0; i < (BufferLength/4); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength%4) != 0)
+ {
+ if (BufferLength%4 == 1)
+ {
+ *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
+ }
+ if (BufferLength%4 == 2)
+ {
+ *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1];
+ }
+ if (BufferLength%4 == 3)
+ {
+ *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1];
+ *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the IP */
+ for(i = 0; i < (BufferLength/2); i++)
+ {
+ hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1];
+ }
+ if ((BufferLength%2) != 0)
+ {
+ *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h
new file mode 100644
index 000000000..7b13f5830
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h
@@ -0,0 +1,327 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CRC_H
+#define __STM32F0xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC CRC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+}HAL_CRC_StateTypeDef;
+
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+ e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRCEx_Polynomial_Sizes and indicates CRC length.
+ Value can be either one of
+ CRC_POLYLENGTH_32B (32-bit CRC)
+ CRC_POLYLENGTH_16B (16-bit CRC)
+ CRC_POLYLENGTH_8B (8-bit CRC)
+ CRC_POLYLENGTH_7B (7-bit CRC) */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
+ CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
+}CRC_InitTypeDef;
+
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
+ CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
+ CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+ must occur if InputBufferFormat is not one of the three values listed above */
+}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
+#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
+#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
+#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state
+ * @param __HANDLE__: CRC handle.
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+ * @param __HANDLE__ : CRC handle
+ * @param __INIT__ : 32-bit initial value
+ * @retval None.
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+ * @}
+ */
+
+
+/* Include CRC HAL Extension module */
+#include "stm32f0xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants CRC Exported Constants
+ * @brief aliases for inter STM32 series compatibility
+ * @{
+ */
+/** @defgroup CRC_Aliases Aliases for inter STM32 series compatibility
+ * @{
+ */
+/* Aliases for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c
new file mode 100644
index 000000000..807fe8ad8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c
@@ -0,0 +1,275 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CRC peripheral:
+ * + Extended initialization functions
+ *
+ @verbatim
+================================================================================
+ ##### Product specific features #####
+================================================================================
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Extended initialization
+ (+) Set or not user-defined generating
+ polynomial other than default one
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx CRCEx Extended HAL Module Driver
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC generating polynomial: if programmable polynomial
+ feature is applicable to device, set default or non-default generating
+ polynomial according to hcrc->Init.DefaultPolynomialUse parameter.
+ If feature is non-applicable to device in use, HAL_CRCEx_Init straight
+ away reports HAL_OK.
+ (+) Set the generating polynomial
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Extended initialization to set generating polynomial
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
+{
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx)
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize IP with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC IP with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc: CRC handle
+ * @param InputReverseMode: Input Data inversion mode
+ * This parameter can be one of the following values:
+ * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc: CRC handle
+ * @param OutputReverseMode: Output Data inversion mode
+ * This parameter can be one of the following values:
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value)
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx)
+/**
+ * @brief Initializes the CRC polynomial if different from default one.
+ * @param hcrc: CRC handle
+ * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
+ * This parameter is written in normal representation, e.g.
+ * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength: CRC polynomial length
+ * This parameter can be one of the following values:
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while (((Pol & (1U << msb)) == 0) && (msb-- > 0))
+ {}
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ break;
+ }
+
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h
new file mode 100644
index 000000000..9a49b6e41
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h
@@ -0,0 +1,202 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of CRC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CRC_EX_H
+#define __STM32F0xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx CRCEx Extended HAL Module Driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants
+ * @{
+ */
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
+#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
+#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
+#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
+#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Polynomial_Sizes Polynomial sizes to configure the IP
+ * @{
+ */
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
+#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
+#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
+#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+#else
+#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
+#define IS_CRC_POL_LENGTH(LENGTH) ((LENGTH) == CRC_POLYLENGTH_32B)
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define HAL_CRC_LENGTH_32B 32
+#define HAL_CRC_LENGTH_16B 16
+#define HAL_CRC_LENGTH_8B 8
+#define HAL_CRC_LENGTH_7B 7
+#else
+#define HAL_CRC_LENGTH_32B 32
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__ : CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__ : CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__ : CRC handle
+ * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
+ * @retval None.
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @}
+ */
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c
new file mode 100644
index 000000000..38f94f0e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c
@@ -0,0 +1,693 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dac.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ STM32F0 devices integrates no, one or two 12-bit Digital Analog Converters.
+ STM32F05x devices have one converter (channel1)
+ STM32F07x & STM32F09x devices have two converters (i.e. channel1 & channel2)
+
+ When 2 converters are present (i.e. channel1 & channel2) they
+ can be used independently or simultaneously (dual mode):
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ The used pin (GPIOx_Pin9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM3, TIM6, and TIM15
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
+
+ (#) Software using DAC_Trigger_Software
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels can be used to generate
+ (#) Noise wave
+ (#) Triangle wave
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondence ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ DAC_OUTx = VREF+ * DOR / 4095
+ with DOR is the Data Output Register
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ e.g. To set DAC_OUT1 to 0.7V, use
+ Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ HAL_DAC_Start_DMA()
+ [..]
+ DMA1 requests are mapped as following:
+ (#) DAC channel1 : mapped on DMA1 channel3 which must be
+ already configured
+ (#) DAC channel2 : mapped on DMA1 channel4 which must be
+ already configured
+
+ -@- For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extension Features Driver description
+ STM32F0 devices with one channel (one converting capability) does not
+ support Dual mode and specific signal (Triangle and noise) generation.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transfered at each end of conversion
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined (STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC DAC HAL module driver
+ * @brief DAC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripharal */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ }
+ else /* Channel2 is used for */
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Alignment: Specifies the data alignment.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)hdac->Instance;
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
+ }
+ else
+ {
+ tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
+ }
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC state
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC state */
+ return hdac->State;
+}
+
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @brief Handles DAC interrupt request
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h
new file mode 100644
index 000000000..5a0704556
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h
@@ -0,0 +1,354 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_DAC_H
+#define __STM32F0xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+}DAC_ChannelConfTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement DAC data alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data DAC data
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition DAC IT definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the FLAG.
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the FLAG.
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+
+/* Include DAC HAL Extension module */
+#include "stm32f0xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__STM32F0xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c
new file mode 100644
index 000000000..8a4a993fc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c
@@ -0,0 +1,1083 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of DAC extension peripheral:
+ * + Extended features functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DACEx DACEx Extended HAL module driver
+ * @brief DACEx driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx Private Functions
+ * @{
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+#endif /* STM32F051x8 STM32F058xx */
+ /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+ /* Disable wave generation */
+ DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ // tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+ /* Disable wave generation */
+ // DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#endif /* STM32F051x8 STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+/* DAC 1 has 2 channels 1 & 2 */
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Returns the DAC channel data output register value */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+ else
+ {
+ return hdac->Instance->DOR2;
+ }
+}
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+
+/* DAC 1 has 1 channels */
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Returns the DAC channel data output register value */
+ return hdac->Instance->DOR1;
+}
+
+
+
+#endif /* STM32F051x8 STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ uint32_t tmp1 = 0, tmp2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+ /* Check if software trigger enabled */
+ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ }
+ }
+ else
+ {
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
+ /* Check if software trigger enabled */
+ if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+ {
+ /* Enable the selected DAC software conversion*/
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN1;
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN2;
+
+ /* Case of use of channel 2 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA channel */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ uint32_t tmp1 = 0, tmp2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+ /* Check if software trigger enabled */
+ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN1;
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the DMA channel */
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#endif /* STM32F051x8 STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+/* DAC channel 2 is available on top of DAC channel 1 */
+
+/**
+ * @brief Handles DAC interrupt request
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+ /* Check Overrun flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ else
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
+}
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
+
+/**
+ * @brief Handles DAC interrupt request
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+ /* Check Overrun flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+}
+
+#endif /* STM32F051x8 STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0;
+
+ tmp |= hdac->Instance->DOR1;
+
+ /* DAC channel 2 is present in DAC 1 */
+ tmp |= hdac->Instance->DOR2 << 16;
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0;
+
+ tmp |= hdac->Instance->DOR1;
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+#endif /* STM32F051x8 STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude: Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_TRIANGLE | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_NOISE | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)hdac->Instance;
+ tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+/**
+ * @}
+ */
+#endif /* STM32F051x8 STM32F058xx */
+ /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @brief Extended features functions
+ * @{
+ */
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel2.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
new file mode 100644
index 000000000..b38d32f37
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
@@ -0,0 +1,297 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of DAC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_DAC_EX_H
+#define __STM32F0xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+ * @{
+ */
+/** @defgroup DACEx_wave_generation DACEx wave generation
+ * @{
+ */
+#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
+ ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+ ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_wave_generationbis DACEx wave generation bis
+ * @{
+ */
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+ * @{
+ */
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+ * @{
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Extension features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+#endif /* */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#endif /*__STM32F0xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
new file mode 100644
index 000000000..62bb2973b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_DEF
+#define __STM32F0xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F0xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
new file mode 100644
index 000000000..64123ec36
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
@@ -0,0 +1,703 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dma.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0;
+
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+ /* Enable the Half transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+ /* Enable the transfer Error interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ *
+ * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
+ * effectively disabled is added. If a Channel is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Channel will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tickstart = 0x00;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA Channel is effectively disabled */
+ while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0x00;
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ {
+ if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ {
+ /* Clear the transfer error flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers of half buffer are complete) */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Transfer Error Interrupt management ***************************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
new file mode 100644
index 000000000..07bed3c23
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
@@ -0,0 +1,459 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_DMA_H
+#define __STM32F0xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Configuration enumeration values definition
+ */
+typedef enum
+{
+ DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
+ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
+
+} DMA_ControlTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
+ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_buffer_size DMA Data buffer size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32f0xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+/** @addtogroup DMA_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ * @brief I/O operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup DMA_Exported_Functions_Group3
+ * @brief Peripheral State functions
+ * @{
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
new file mode 100644
index 000000000..fd85710b2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
@@ -0,0 +1,783 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of DMA HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_DMA_EX_H
+#define __STM32F0xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+ * @{
+ */
+#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#if !defined(STM32F030xC)
+#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#endif /* !defined(STM32F030xC) */
+
+/****************** DMA1 remap bit field definition********************/
+/* DMA1 - Channel 1 */
+#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
+#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
+#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
+#endif /* !defined(STM32F030xC) */
+
+/* DMA1 - Channel 2 */
+#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
+#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
+#endif /* !defined(STM32F030xC) */
+
+/* DMA1 - Channel 3 */
+#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
+#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
+#endif /* !defined(STM32F030xC) */
+
+/* DMA1 - Channel 4 */
+#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
+#endif /* !defined(STM32F030xC) */
+
+/* DMA1 - Channel 5 */
+#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
+#if !defined(STM32F030xC)
+#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
+#endif /* !defined(STM32F030xC) */
+
+#if !defined(STM32F030xC)
+/* DMA1 - Channel 6 */
+#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
+/* DMA1 - Channel 7 */
+#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
+
+/****************** DMA2 remap bit field definition********************/
+/* DMA2 - Channel 1 */
+#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
+/* DMA2 - Channel 2 */
+#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
+/* DMA2 - Channel 3 */
+#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
+#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
+#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
+/* DMA2 - Channel 4 */
+#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
+#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
+#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
+/* DMA2 - Channel 5 */
+#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
+#endif /* !defined(STM32F030xC) */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
+ ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
+
+#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
+ ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
+ ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
+ ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
+ ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA2_CH5_ADC) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
+ ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030xC)
+#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
+ ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
+ ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
+ ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
+#endif /* STM32F030xC */
+
+/**
+ * @}
+ */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+#elif defined(STM32F091xC) || defined(STM32F098xx)
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+ (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+ (DMA1->IFCR = (__FLAG__)))
+
+#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_5 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_5 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+#endif
+
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define __HAL_DMA1_REMAP(__REQUEST__) \
+ do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
+ DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
+ DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
+ }while(0)
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define __HAL_DMA2_REMAP(__REQUEST__) \
+ do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
+ DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
+ DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
+ }while(0)
+#endif /* STM32F091xC || STM32F098xx */
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_DMA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
new file mode 100644
index 000000000..64232f81b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
@@ -0,0 +1,722 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_flash.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) Option Bytes programming
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F0xx devices. These functions are split in 3 groups:
+
+ (#) FLASH Memory I/O Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface
+ (++) Erase function: Erase page, erase all pages
+ (++) Program functions: half word, word and doubleword
+
+ (#) Option Bytes Programming functions: this group includes all needed
+ functions to manage the Option Bytes:
+ (++) Lock and Unlock the Option Bytes
+ (++) Erase Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Program the data Option Bytes
+ (++) Launch the Option Bytes loader
+
+ (#) Interrupts and flags management functions : this group
+ includes all needed functions to:
+ (++) Handle FLASH interrupts
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status
+
+ [..] In addition to these function, this driver includes a set of macros allowing
+ to handle the following operations:
+
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH HAL module driver
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Defines FLASH Private Define
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+/* Erase operations */
+void FLASH_PageErase(uint32_t PageAddress);
+
+/* Program operations */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+static void FLASH_SetErrorCode(void);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 I/O operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations (write/erase).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0;
+ uint8_t nbiterations = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1;
+ }
+ else if(TypeProgram == TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4;
+ }
+
+ for (index = 0; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /*Program halfword (16-bit) at a specified address.*/
+ pFlash.DataRemaining = 1;
+ }
+ else if(TypeProgram == TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /*Program word (32-bit : 2*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 2;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /*Program double word (64-bit : 4*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 4;
+ }
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(pFlash.Address);
+
+ /* Reset address and stop the procedure ongoing*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
+
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+ /*MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which has been erased
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET)
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_FKEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_FKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET)
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Set the bit to force the option byte reloading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+ /* Wait for last operation to be completed */
+ return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode: The returned value can be:
+ * @arg FLASH_ERROR_PG: FLASH Programming error flag
+ * @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress: FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout: maximum flash operationtimeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+ {
+ pFlash.ErrorCode |= FLASH_ERROR_WRP;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ pFlash.ErrorCode |= FLASH_ERROR_PG;
+ }
+
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
new file mode 100644
index 000000000..29b37cecc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
@@ -0,0 +1,515 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_FLASH_H
+#define __STM32F0xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASH_Type_Erase */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a value of @ref FLASHEx_Address */
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between 1 and (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASH_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASH_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASH_OB_Read_Protection */
+
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
+ This parameter can be a combination of @ref FLASH_OB_Watchdog, @ref FLASH_OB_nRST_STOP,
+ @ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring and
+ @ref FLASH_OB_RAM_Parity_Check_Enable */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed
+ This parameter can be a value of @ref FLASH_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter can have any value */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGEERASE = 1,
+ FLASH_PROC_MASSERASE = 2,
+ FLASH_PROC_PROGRAMHALFWORD = 3,
+ FLASH_PROC_PROGRAMWORD = 4,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
+
+ __IO uint32_t ErrorCode; /*!< FLASH error code
+ This parameter can be a value of @ref FLASH_Error */
+
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error FLASH Error
+ * @{
+ */
+#define FLASH_ERROR_NONE ((uint32_t)0x00000000)
+#define FLASH_ERROR_PG ((uint32_t)0x00000001)
+#define FLASH_ERROR_WRP ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
+#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
+
+#define IS_TYPEERASE(VALUE) (((VALUE) == TYPEERASE_PAGES) || \
+ ((VALUE) == TYPEERASE_MASSERASE))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
+#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
+#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
+
+#define IS_TYPEPROGRAM(VALUE) (((VALUE) == TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == TYPEPROGRAM_WORD) || \
+ ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_WRP_State FLASH WRP State
+ * @{
+ */
+#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
+#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == WRPSTATE_DISABLE) || \
+ ((VALUE) == WRPSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
+
+#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Data_Address FLASH OB Data Address
+ * @{
+ */
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Read_Protection FLASH OB Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_Watchdog FLASH OB Watchdog
+ * @{
+ */
+#define OB_WDG_SW ((uint8_t)0x01) /*!< Software WDG selected */
+#define OB_WDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
+#define IS_OB_WDG_SOURCE(SOURCE) (((SOURCE) == OB_WDG_SW) || ((SOURCE) == OB_WDG_HW))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_nRST_STOP FLASH OB nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_nRST_STDBY FLASH OB nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_BOOT1 FLASH OB BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_VDDA_Analog_Monitoring FLASH OB VDDA Analog Monitoring
+ * @{
+ */
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_RAM_Parity_Check_Enable FLASH OB RAM Parity Check Enable
+ * @{
+ */
+#define OB_RAM_PARITY_CHECK_SET ((uint8_t)0x00) /*!< RAM parity check enable set */
+#define OB_RAM_PARITY_CHECK_RESET ((uint8_t)0x40) /*!< RAM parity check enable reset */
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_RAM_PARITY_CHECK_SET) || ((PARITY) == OB_RAM_PARITY_CHECK_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+ * @{
+ */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Timeout_definition FLASH Timeout definition
+ * @brief FLASH Timeout definition
+ * @{
+ */
+#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @brief macros to control FLASH features
+ * @{
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__: FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ * @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupt
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extension module */
+#include "stm32f0xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @brief Data transfers functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @brief management functions
+ * @{
+ */
+
+/* FLASH Memory Programming functions *****************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+
+/* Option Bytes Programming functions *****************************************/
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c
new file mode 100644
index 000000000..e24ea27d5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c
@@ -0,0 +1,854 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + Extended Initialization/de-initialization functions
+ * + Extended I/O operation functions
+ * + Extended Peripheral Control functions
+ * + Extended Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash peripheral extended features #####
+ ==============================================================================
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F0xxx devices. It includes
+
+ (+) Set/Reset the write protection
+ (+) Program the user Option Bytes
+ (+) Get the Read protection Level
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx FLASHEx Extended HAL module driver
+ * @brief FLASH Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables FLASHEx Private Variables
+ * @{
+ */
+
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+
+/* Erase operations */
+extern void FLASH_PageErase(uint32_t PageAddress);
+static void FLASH_MassErase(void);
+
+/* Option bytes control */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+static uint32_t FLASH_OB_GetWRP(void);
+static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetUser(void);
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Extern_Functions FLASHEx Extern Functions
+ * @{
+ */
+/* Private functions ---------------------------------------------------------*/
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions
+ * @brief Extended I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError: pointer to variable that
+ * contains the configuration information on faulty page in case of error
+ * (0xFFFFFFFF means that all the pages have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t address = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if (status == HAL_OK)
+ {
+ if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase by page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+ if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ FLASH_MassErase();
+ }
+ else
+ {
+ /* Erase by page to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.DataRemaining = pEraseInit->NbPages;
+ pFlash.Address = pEraseInit->PageAddress;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_PageErase(pEraseInit->PageAddress);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+{
+ uint8_t rdptmp = OB_RDP_LEVEL_0;
+ HAL_StatusTypeDef status = HAL_ERROR;
+ FLASH_OBProgramInitTypeDef optionsbytes;
+
+ /* Get the actual read protection Option Byte value */
+ HAL_FLASHEx_OBGetConfig(&optionsbytes);
+ if(optionsbytes.RDPLevel != RESET)
+ {
+ rdptmp = OB_RDP_LEVEL_1;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Restore the last read protection Option Byte value */
+ optionsbytes.OptionType = OPTIONBYTE_RDP;
+ optionsbytes.RDPLevel = rdptmp;
+ status = HAL_FLASHEx_OBProgram(&optionsbytes);
+ }
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ *
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Write protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == WRPSTATE_ENABLE)
+ {
+ /* Enable of Write protection on the selected page */
+ status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
+ }
+ else
+ {
+ /* Disable of Write protection on the selected page */
+ status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
+ }
+ }
+
+ /* Read protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ }
+
+ /* USER configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig);
+ }
+
+ /* DATA configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+ {
+ status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
+
+ /*Get WRP*/
+ pOBInit->WRPPage = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+
+/**
+ * @brief Mass erase of FLASH memory
+ * @retval None
+ */
+static void FLASH_MassErase(void)
+{
+
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Proceed to erase all sectors */
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Enable the write protection of the desired pages
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage: specifies the page(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ WriteProtectPage = (uint32_t)(~WriteProtectPage);
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24);
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#if defined(STM32F091xC) || defined(STM32F098xx)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
+ STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC*/
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired pages
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage: specifies the page(s) to be write unprotected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || STM32F070x6 || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24);
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#if defined(STM32F091xC) || defined(STM32F098xx)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* STM32F091xC || STM32F098xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
+ STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param ReadProtectLevel: specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ *
+ * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ *
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WDG_SOURCE((UserConfig&OB_WDG_SW)));
+ assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
+ assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
+ assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
+ assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
+ assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_RAM_PARITY_CHECK_RESET)));
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+ assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
+ assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+ OB->USER = UserConfig;
+#else
+ OB->USER = (UserConfig | 0x88);
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = FLASH_ERROR_NONE;
+
+ /* Enables the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(READ_REG(FLASH->WRPR));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
+ * - RESET, when OB_RDP_Level_0 is set
+ */
+static FlagStatus FLASH_OB_GetRDP(void)
+{
+ FlagStatus readstatus = RESET;
+
+ if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT1) != RESET)
+ {
+ readstatus = SET;
+ }
+
+ return readstatus;
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)(READ_REG(FLASH->OBR) >> 8);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
new file mode 100644
index 000000000..69d52579c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of FLASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_FLASH_EX_H
+#define __STM32F0xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+/** @defgroup FLASHEx_Address FLASHEx Address
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) || defined(STM32F070x6)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF))
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB*/
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
+#define FLASH_PAGE_SIZE 0x400
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define FLASH_PAGE_SIZE 0x800
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Nb_Pages FLASHEx Nb Pages
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF)
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF)
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
+#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO57 ((uint32_t)0x00002000) /* Write protection of page 52 to 57 */
+#define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
+#define OB_WRP_ALLPAGES ((uint32_t)0x000000FF) /*!< Write protection of all pages */
+#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#define OB_WRP_PAGES62TO63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#define OB_WRP_PAGES48TO63MASK ((uint32_t)0xFF000000)
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+/**
+ * @}
+ */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx OB BOOT SEL
+ * @{
+ */
+#define OB_BOOT_SEL_RESET ((uint8_t)0x00) /*!< BOOT_SEL Reset */
+#define OB_BOOT_SEL_SET ((uint8_t)0x80) /*!< BOOT_SEL Set */
+#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_BOOT0 FLASHEx OB BOOT0
+ * @{
+ */
+#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */
+#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */
+#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
+/**
+ * @}
+ */
+#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions
+ * @brief Extended I/O operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
new file mode 100644
index 000000000..cca2d3b5a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
@@ -0,0 +1,561 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_gpio.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ configured by software in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral s alternate function (AF) connected
+ to an IO pin at a time. In this way, there can be no conflict between peripherals
+ sharing the same IO pin.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 28 edge detectors
+ (depending on products 16 lines are connected to GPIO) for generating event/interrupt
+ requests (each input line can be independently configured to select the type
+ (interrupt or event) and the corresponding trigger event (rising or falling or both).
+ Each line can also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure,
+ the speed is configurable: Low, Medium and High.
+ (++) If alternate mode is selected, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
+ recommended to use it to unconfigure pin which was used as an external interrupt
+ or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
+ registers.
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO HAL module driver
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Define GPIO Private Define
+ * @{
+ */
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER ((uint32_t)16)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exporte functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+ * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t temp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ while ((GPIO_Init->Pin) >> position)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1 << position);
+
+ if(iocurrent)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
+
+ /* In case of Output or Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ temp |= (GPIO_Init->Speed << (position * 2));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ GPIOx->PUPDR = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable SYSCFG Clock */
+ __SYSCFG_CLK_ENABLE();
+
+ temp = SYSCFG->EXTICR[position >> 2];
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+ SYSCFG->EXTICR[position >> 2] = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR = temp;
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+ * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t tmp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while (GPIO_Pin >> position)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ {
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+ * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+ }
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+ * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
+ }
+}
+
+/**
+ * @brief Toggles the specified GPIO pin
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+ * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ * @param GPIO_Pin: specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief Locks GPIO Pins configuration registers.
+* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+* @note The configuration of the locked GPIO pins can no longer be modified
+* until the next reset.
+* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+* @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
+* @note GPIOE is only available on STM32F07xx and STM32F09xx
+* @param GPIO_Pin: specifies the port bit to be locked.
+* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+* @retval None
+*/
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief This function handles EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callbacks.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
new file mode 100644
index 000000000..9fcbe451b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_gpio.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_GPIO_H
+#define __STM32F0xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pin_actions GPIO pin actions
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_pins GPIO pins
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode GPIO mode
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed GPIO speed
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
+#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
+#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_HIGH))
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f0xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
new file mode 100644
index 000000000..b737e4e5f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
@@ -0,0 +1,810 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_GPIO_EX_H
+#define __STM32F0xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+ * @{
+ */
+
+#if defined (STM32F030x6)
+/*------------------------- STM32F030x6---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F030x6 */
+
+/*---------------------------------- STM32F030x8 -------------------------------------------*/
+#if defined (STM32F030x8)
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F030x8 */
+
+#if defined (STM32F031x6) || defined (STM32F038xx)
+/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_SWDAT ((uint8_t)0x00) /*!< AF0: SWDAT Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F031x6 || STM32F038xx */
+
+#if defined (STM32F051x8) || defined (STM32F058xx)
+/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+/* AF 7 */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32F051x8/STM32F058xx */
+
+#if defined (STM32F071xB)
+/*--------------------------- STM32F071xB ---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: AEVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART3 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: TSC Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+/* AF 7 */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32F071xB */
+
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART3 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+#define GPIO_AF0_USART8 ((uint8_t)0x00) /*!< AF0: USART8 Alternate Function mapping */
+#define GPIO_AF0_CAN ((uint8_t)0x00) /*!< AF0: CAN Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */
+#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< AF1: USART4 Alternate Function mapping */
+#define GPIO_AF1_USART5 ((uint8_t)0x01) /*!< AF1: USART5 Alternate Function mapping */
+#define GPIO_AF1_USART6 ((uint8_t)0x01) /*!< AF1: USART6 Alternate Function mapping */
+#define GPIO_AF1_USART7 ((uint8_t)0x01) /*!< AF1: USART7 Alternate Function mapping */
+#define GPIO_AF1_USART8 ((uint8_t)0x01) /*!< AF1: USART8 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: TSC Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USART5 ((uint8_t)0x02) /*!< AF2: USART5 Alternate Function mapping */
+#define GPIO_AF2_USART6 ((uint8_t)0x02) /*!< AF2: USART6 Alternate Function mapping */
+#define GPIO_AF2_USART7 ((uint8_t)0x02) /*!< AF2: USART7 Alternate Function mapping */
+#define GPIO_AF2_USART8 ((uint8_t)0x02) /*!< AF2: USART8 Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */
+#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART5 ((uint8_t)0x04) /*!< AF4: USART5 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_USART6 ((uint8_t)0x05) /*!< AF5: USART6 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+/* AF 7 */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030xC)
+/*--------------------------- STM32F030xC ----------------------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USART5 ((uint8_t)0x02) /*!< AF2: USART5 Alternate Function mapping */
+#define GPIO_AF2_USART6 ((uint8_t)0x02) /*!< AF2: USART6 Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART5 ((uint8_t)0x04) /*!< AF4: USART5 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_USART6 ((uint8_t)0x05) /*!< AF5: USART6 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F030xC */
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+#define GPIO_AF0_CAN ((uint8_t)0x00) /*!< AF0: CAN Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */
+#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+/* AF 7 */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32F072xB || STM32F078xx */
+
+#if defined (STM32F070xB)
+/*---------------------------------- STM32F070xB ---------------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART4 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F070xB */
+
+#if defined (STM32F042x6) || defined (STM32F048xx)
+/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */
+#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */
+#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_I2C1 ((uint8_t)0x05) /*!< AF5: I2C1 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_USB ((uint8_t)0x05) /*!< AF5: USB Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined (STM32F070x6)
+/*--------------------------------------- STM32F070x6 ----------------------------------------*/
+/* AF 0 */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */
+#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */
+
+/* AF 1 */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */
+#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */
+
+/* AF 2 */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */
+#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */
+
+/* AF 3 */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
+
+/* AF 4 */
+#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */
+
+/* AF 5 */
+#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */
+#define GPIO_AF5_I2C1 ((uint8_t)0x05) /*!< AF5: I2C1 Alternate Function mapping */
+#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */
+#define GPIO_AF5_USB ((uint8_t)0x05) /*!< AF5: USB Alternate Function mapping */
+
+/* AF 6 */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06)
+
+#endif /* STM32F070x6 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
+* @{
+ */
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)
+#endif
+
+#if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F070xB) || defined (STM32F030xC) || \
+ defined (STM32F051x8) || defined (STM32F058xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U : 5U)
+#endif
+
+#if defined (STM32F031x6) || defined (STM32F038xx) || \
+ defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U : 5U)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
new file mode 100644
index 000000000..0b386ad15
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
@@ -0,0 +1,4101 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2c.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
+ (++) Enable the I2Cx interface clock
+ (++) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (++) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (++) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init() API:
+ (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three modes of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C HAL module driver
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
+#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
+#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
+
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and create the associated handle.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if(hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ if(hi2c->Init.OwnAddress1 != 0)
+ {
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2C peripheral.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C MSP Init.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C MSP DeInit
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*pData++);
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to RXDR */
+ (*pData++) =hi2c->Instance->RXDR;
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from TXDR */
+ hi2c->Instance->TXDR = (*pData++);
+ Size--;
+ }while(Size > 0);
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+ Size--;
+ }
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = Size;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* If 10bits addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is set Receiver mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->TXDR = (*pData++);
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+
+ /* Decrement the Size counter */
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param Trials: Number of trials
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t I2C_Trials = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR2 = __HAL_I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (I2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+ }while(I2C_Trials < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* I2C in mode Transmitter ---------------------------------------------------*/
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
+ {
+ I2C_SlaveTransmit_ISR(hi2c);
+ }
+ }
+
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
+ {
+ I2C_MasterTransmit_ISR(hi2c);
+ }
+ }
+
+ /* I2C in mode Receiver ----------------------------------------------------*/
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
+ {
+ I2C_SlaveReceive_ISR(hi2c);
+ }
+ }
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
+ {
+ I2C_MasterReceive_ISR(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the I2C state.
+ * @param hi2c : I2C handle
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->State;
+}
+
+/**
+* @brief Return the I2C error code
+* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Handle Interrupt Flags Master Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ {
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ {
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hi2c->XferCount > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = hi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ {
+ if(hi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ {
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Master Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ {
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ {
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hi2c->XferCount > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = hi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ {
+ if(hi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ {
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
+{
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hi2c->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+ /* Check first if STOPF is set */
+ /* to prevent a Write Data in TX buffer */
+ /* which is stuck in TXDR until next */
+ /* communication with Master */
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ if(hi2c->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Mememory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal Use case, a AF is generated by master */
+ /* to inform slave the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOPF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Write process complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Read process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ HAL_I2C_ErrorCallback(hi2c);
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag: specifies the I2C flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a STOPF is detected */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */
+ if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
+ {
+ /* No need to generate the STOP condition if AUTOEND mode is enabled */
+ /* Generate the STOP condition only in case of SOFTEND mode is enabled */
+ if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ }
+
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hi2c: I2C handle.
+ * @param DevAddress: specifies the slave address to be programmed.
+ * @param Size: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_RELOAD_MODE: Enable Reload mode .
+ * @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
+ * @arg I2C_SOFTEND_MODE: Enable Software end mode.
+ * @param Request: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
+ * @arg I2C_GENERATE_START_READ: Generate Restart for read request.
+ * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
+ * @retval None
+ */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hi2c->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hi2c->Instance->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
new file mode 100644
index 000000000..80fbdfcb8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
@@ -0,0 +1,562 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2c.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_I2C_H
+#define __STM32F0xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref I2C_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
+ HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
+ HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
+ HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
+ HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief I2C handle Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code
+ This parameter can be a value of @ref I2C_Error */
+
+}I2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_Error I2C Error
+ * @brief I2C Error
+ * @{
+ */
+
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+ * @{
+ */
+
+#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address2_masks I2C own address2 masks
+ * @{
+ */
+
+#define I2C_OA2_NOMASK ((uint8_t)0x00)
+#define I2C_OA2_MASK01 ((uint8_t)0x01)
+#define I2C_OA2_MASK02 ((uint8_t)0x02)
+#define I2C_OA2_MASK03 ((uint8_t)0x03)
+#define I2C_OA2_MASK04 ((uint8_t)0x04)
+#define I2C_OA2_MASK05 ((uint8_t)0x05)
+#define I2C_OA2_MASK06 ((uint8_t)0x06)
+#define I2C_OA2_MASK07 ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
+ ((CALL) == I2C_GENERALCALL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
+ * @{
+ */
+
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
+#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
+ * @{
+ */
+
+#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
+#define I2C_GENERATE_STOP I2C_CR2_STOP
+#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE I2C_CR2_START
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_AF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+#define I2C_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: I2C handle.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enables or disables the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_ERRI: Errors interrupt enable
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable
+ * @arg I2C_IT_NACKI: NACK received interrupt enable
+ * @arg I2C_IT_ADDRI: Address match interrupt enable
+ * @arg I2C_IT_RXI: RX interrupt enable
+ * @arg I2C_IT_TXI: TX interrupt enable
+ *
+ * @retval None
+ */
+
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_ERRI: Errors interrupt enable
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable
+ * @arg I2C_IT_NACKI: NACK received interrupt enable
+ * @arg I2C_IT_ADDRI: Address match interrupt enable
+ * @arg I2C_IT_RXI: RX interrupt enable
+ * @arg I2C_IT_TXI: TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_TXE: Transmit data register empty
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status
+ * @arg I2C_FLAG_RXNE: Receive data register not empty
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)
+ * @arg I2C_FLAG_TCR: Transfer complete reload
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus alert
+ * @arg I2C_FLAG_BUSY: Bus busy
+ * @arg I2C_FLAG_DIR: Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+/**
+ * @}
+ */
+
+/* Include I2C HAL Extended module */
+#include "stm32f0xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
new file mode 100644
index 000000000..6026fff2c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief I2C Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C extension peripheral:
+ * + Extension features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral extension features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32F0XX
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config()
+ (#) Configure the enabling or disabling of I2C Wake Up Mode using the functions :
+ (++) HAL_I2CEx_EnableWakeUp()
+ (++) HAL_I2CEx_DisableWakeUp()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx Extended HAL module driver
+ * @brief I2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2CEx Exported Functions
+ * @{
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures I2C Analog noise filter.
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter : new state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures I2C Digital noise filter.
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->CR1;
+
+ /* Reset I2Cx DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DFN);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8;
+
+ /* Store the new register value */
+ hi2c->Instance->CR1 = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/**
+ * @brief Enables I2C wakeup from stop mode.
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables I2C wakeup from stop mode.
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
new file mode 100644
index 000000000..1452a42e5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
@@ -0,0 +1,132 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of I2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_I2C_EX_H
+#define __STM32F0xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx I2CEx Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Digital_Filter I2CEx Digital Filter
+ * @{
+ */
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
+#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
new file mode 100644
index 000000000..c1a03a8b2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
@@ -0,0 +1,1389 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2s.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follow:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx Channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Channel.
+ (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2S I2S HAL module driver
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0, i2sclk = 0;
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+
+ if(hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get I2S source Clock frequency ****************************************/
+ i2sclk = HAL_RCC_GetSysClockFreq();
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->pTxBuffPtr = pData;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Wait until TXE flag is set, to confirm the end of the transcation */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->pRxBuffPtr = pData;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Transmit data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set the I2S Tx DMA Half transfert complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfert complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Channel */
+ HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
+ {
+ /* Enable Tx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+
+ /* Set the I2S Rx DMA Half transfert complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfert complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Channel */
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
+ {
+ /* Enable Rx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
+
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmatx);
+ __HAL_DMA_DISABLE(hi2s->hdmarx);
+
+ /* Abort the I2S DMA tx channel */
+ if(hi2s->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA rx channel */
+ if(hi2s->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t i2ssr = hi2s->Instance->SR;
+
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
+ ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ return;
+ }
+
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ return;
+ }
+
+ /* I2S Overrun error interrupt occured ---------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured --------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable Rx DMA Request */
+ hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0;
+ hi2s->RxXferCount = 0;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxCpltCallback(hi2s);
+ }
+}
+
+/**
+* @brief Receive an amount of data in non-blocking mode with Interrupt
+* @param hi2s: I2S handle
+ * @retval None
+*/
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
+}
+
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag: Flag checked
+ * @param State: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(State == RESET)
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
+ /* defined(STM32F051x8) || defined(STM32F058xx) || */
+ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
+ /* defined(STM32F042x6) || defined(STM32F048xx) || */
+ /* defined(STM32F091xC) || defined(STM32F098xx) */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
new file mode 100644
index 000000000..38e7841ee
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
@@ -0,0 +1,453 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_i2s.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_I2S_H
+#define __STM32F0xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_PAUSE = 0x06, /*!< I2S pause state: used in case of DMA */
+ HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
+
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
+
+}I2S_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX)|| \
+ ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition I2S Flag definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: I2S handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
+ /* defined(STM32F051x8) || defined(STM32F058xx) || */
+ /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||*/
+ /* defined(STM32F042x6) || defined(STM32F048xx) || */
+ /* defined(STM32F091xC) || defined(STM32F098xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
new file mode 100644
index 000000000..3bb9b4447
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
@@ -0,0 +1,1363 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_irda.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization function
+ * + IO operation function
+ * + Peripheral Control function
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure.
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) IRDA pins configuration:
+ (+++) Enable the clock for the IRDA GPIOs.
+ (+++) Configure these IRDA pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA HAL module driver
+ * @brief HAL IRDA module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define TEACK_REACK_TIMEOUT 1000
+#define IRDA_TXDMA_TIMEOUTVALUE 22000
+#define IRDA_TIMEOUT_VALUE 22000
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
+ the possible IRDA frame formats are as listed in the following table:
+ +---------------------------------------------------------------+
+ | M bit | PCE bit | IRDA frame |
+ |-----------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | IRDA frame |
+ |-----------------------|---------------------------------------|
+ | 10 | 0 | | SB | 7-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_IRDA_Init() function follows IRDA configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and creates the associated handle .
+ * @param hirda: IRDA handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ if(hirda->State == HAL_IRDA_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
+ hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* TEACK and/or REACK to check before moving hirda->State to Ready */
+ return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+ * @brief DeInitializes the IRDA peripheral
+ * @param hirda: IRDA handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->State = HAL_IRDA_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief IRDA MSP Init
+ * @param hirda: IRDA handle
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA MSP DeInit
+ * @param hirda: IRDA handle
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, these API s return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API s are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode API s with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+ (++) IRDA_Transmit_IT()
+ (++) IRDA_Receive_IT()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0)
+ {
+ hirda->TxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ __HAL_IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* Check data remaining to be received */
+ while(hirda->RxXferCount > 0)
+ {
+ hirda->RxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pData +=2;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ __HAL_IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Enable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Data Register not empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the IRDA transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode
+ * @param hirda: IRDA handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles IRDA interrupt request.
+ * @param hirda: IRDA handle
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA frame error interrupt occured --------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA noise error interrupt occured --------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA Over-Run interrupt occured -----------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+ }
+
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ }
+
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ }
+
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA IRDA Tx transfer completed callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hirda->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+}
+
+/**
+ * @brief DMA IRDA Rx Transfer completed callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hirda->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0;
+ hirda->State= HAL_IRDA_STATE_READY;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ HAL_IRDA_ErrorCallback(hirda);
+}
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hirda: irda handle
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hirda: irda handle
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA error callback
+ * @param hirda: IRDA handle
+ * @retval None
+ */
+ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Receive an amount of data in non blocking mode.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT()
+ * @param hirda: IRDA handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+
+ if(hirda->TxXferCount == 0)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ hirda->pTxBuffPtr += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+ hirda->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non blocking mode.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda: IRDA handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = hirda->Mask;
+
+ if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ hirda->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--hirda->RxXferCount == 0)
+ {
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief IRDA control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the IRDA.
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
+ (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the IRDA state
+ * @param hirda: irda handle
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->State;
+}
+
+/**
+* @brief Return the IRDA error code
+* @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA.
+* @retval IRDA Error Code
+*/
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the IRDA peripheral
+ * @param hirda: irda handle
+ * @retval None
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg = 0x00000000;
+ IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ __HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State
+ * @param hirda: IRDA handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->State= HAL_IRDA_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout.
+ * @param hirda: IRDA handle
+ * @param Flag: specifies the IRDA flag to check.
+ * @param Status: the flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
new file mode 100644
index 000000000..1dd71b509
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
@@ -0,0 +1,631 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_irda.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file contains all the functions prototypes for the IRDA
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_IRDA_H
+#define __STM32F0xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDAEx_Word_Length */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+ to achieve low-power frequency.
+ @note Prescaler value 0 is forbidden */
+
+ uint16_t PowerMode; /*!< Specifies the IRDA power mode.
+ This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State structures definition
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief IRDA clock sources definition
+ */
+typedef enum
+{
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART RX RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code
+ This parameter can be a value of @ref IRDA_Error */
+
+}IRDA_HandleTypeDef;
+
+/**
+ * @brief IRDA Configuration enumeration values definition
+ */
+typedef enum
+{
+ IRDA_BAUDRATE = 0x00,
+ IRDA_PARITY = 0x01,
+ IRDA_WORDLENGTH = 0x02,
+ IRDA_MODE = 0x03,
+ IRDA_PRESCALER = 0x04,
+ IRDA_POWERMODE = 0x05
+}IRDA_ControlTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants
+ * @{
+ */
+
+/** @defgroup IRDA_Error IRDA Error
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE ((uint16_t)0x0000)
+#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & ((uint16_t)(~((uint16_t)(IRDA_MODE_TX_RX))))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000)
+#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP)
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+/**
+ * @}
+ */
+
+ /** @defgroup IRDA_State IRDA State
+ * @{
+ */
+#define IRDA_STATE_DISABLE ((uint16_t)0x0000)
+#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE)
+#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \
+ ((STATE) == IRDA_STATE_ENABLE))
+/**
+ * @}
+ */
+
+ /** @defgroup IRDA_Mode IRDA Mode
+ * @{
+ */
+#define IRDA_MODE_DISABLE ((uint16_t)0x0000)
+#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN)
+#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \
+ ((STATE) == IRDA_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000)
+#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT)
+#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \
+ ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+ * @{
+ */
+#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000)
+#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT)
+#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \
+ ((DMATX) == IRDA_DMA_TX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+ * @{
+ */
+#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000)
+#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR)
+#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \
+ ((DMARX) == IRDA_DMA_RX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
+#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
+#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
+#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
+#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
+#define IRDA_FLAG_TC ((uint32_t)0x00000040)
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
+#define IRDA_FLAG_NE ((uint32_t)0x00000004)
+#define IRDA_FLAG_FE ((uint32_t)0x00000002)
+#define IRDA_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define IRDA_IT_PE ((uint16_t)0x0028)
+#define IRDA_IT_TXE ((uint16_t)0x0727)
+#define IRDA_IT_TC ((uint16_t)0x0626)
+#define IRDA_IT_RXNE ((uint16_t)0x0525)
+#define IRDA_IT_IDLE ((uint16_t)0x0424)
+
+
+
+/** Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ */
+#define IRDA_IT_ERR ((uint16_t)0x0060)
+
+/** Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ */
+#define IRDA_IT_ORE ((uint16_t)0x0300)
+#define IRDA_IT_NE ((uint16_t)0x0200)
+#define IRDA_IT_FE ((uint16_t)0x0100)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+ * @{
+ */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
+ ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask
+ * @{
+ */
+#define IRDA_IT_MASK ((uint16_t)0x001F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state
+ * @param __HANDLE__: IRDA handle.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief Checks whether the specified IRDA flag is set or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_REACK: Receive enable ackowledge flag
+ * @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg IRDA_FLAG_BUSY: Busy flag
+ * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
+ * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enables the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief Disables the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief Checks whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_ORE: OverRun Error interrupt
+ * @arg IRDA_IT_NE: Noise Error interrupt
+ * @arg IRDA_IT_FE: Framing Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+
+/** @brief Checks whether the specified IRDA interrupt source is enabled.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_ORE: OverRun Error interrupt
+ * @arg IRDA_IT_NE: Noise Error interrupt
+ * @arg IRDA_IT_FE: Framing Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+
+/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
+ * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
+ * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
+ * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief Set a specific IRDA request flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+
+
+/** @brief Enable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
+ * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0
+ * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32f0xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
new file mode 100644
index 000000000..56cffaafe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
@@ -0,0 +1,415 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_irda_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of IRDA HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_IRDA_EX_H
+#define __STM32F0xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDAEx IRDAEx Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDAEx_Word_Length IRDA Word Length
+ * @{
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#else
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)*/
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Exported_Macros IRDAEx Exported Macros
+ * @{
+ */
+
+/** @brief Reports the IRDA clock source.
+ * @param __HANDLE__: specifies the IRDA Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+ */
+
+#if defined(STM32F031x6) || defined(STM32F038xx)
+#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } while(0)
+#elif defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F051x8) || defined (STM32F058xx)
+#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F091xC) || defined(STM32F098xx)
+#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART7) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART8) \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+
+#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
+
+
+/** @brief Computes the mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @param __HANDLE__: specifies the IRDA Handle
+ * @retval none
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined(STM32F098xx) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
new file mode 100644
index 000000000..d8ade7223
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
@@ -0,0 +1,415 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Configuration functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### IWDG Specific features #####
+ ===============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+ (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
+ thus stays active even if the main clock fails.
+ (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled
+ (LSI cannot be disabled too), and the counter starts counting down from
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)
+ a system reset is generated.
+ (+) The IWDG counter should be refreshed at regular intervals, otherwise the
+ watchdog generates an MCU reset when the counter reaches 0.
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+ (+) Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F0x
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM16 CH1 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+ For more information, please refer to the STM32F0x Reference manual.
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) if Window option is disabled
+ (++) Use IWDG using HAL_IWDG_Init() function to :
+ (+++) Enable write access to IWDG_PR, IWDG_RLR.
+ (+++) Configure the IWDG prescaler, counter reload value.
+ This reload value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (++) Use IWDG using HAL_IWDG_Start() function to :
+ (+++) Reload IWDG counter with value defined in the IWDG_RLR register.
+ (+++) Start the IWDG, when the IWDG is used in software mode (no need
+ to enable the LSI, it will be enabled by hardware).
+ (++) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+ (#) if Window option is enabled:
+ (++) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
+ (++) Use IWDG using HAL_IWDG_Init() function to :
+ (+++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ (+++) Configure the IWDG prescaler, reload value and window value.
+ (++) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver.
+
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
+ (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
+ (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
+ (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG HAL module driver
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+
+#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters
+ in the IWDG_InitTypeDef and create the associated handle
+ (+) Manage Window option
+ (+) Initialize the IWDG MSP
+ (+) DeInitialize IWDG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IWDG according to the specified
+ * parameters in the IWDG_InitTypeDef and creates the associated handle.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the IWDG handle allocation */
+ if(hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+ /* Check pending flag, if previous update not done, return error */
+ if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hiwdg->State == HAL_IWDG_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_IWDG_MspInit(hiwdg);
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
+ /* by writing 0x5555 in KR */
+ __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
+ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
+ MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
+
+ /* check if window option is enabled */
+ if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while((uint32_t)(hiwdg->Instance->SR) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write to IWDG WINR the IWDG_Window value to compare with */
+ MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window);
+
+ }
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the IWDG MSP.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval None
+ */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the IWDG.
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Reload IWDG counter with value defined in the RLR register */
+ if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
+ {
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Enable the IWDG peripheral */
+ __HAL_IWDG_START(hiwdg);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until PVU, RVU, WVU flag are RESET */
+ while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
+ {
+ if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Refreshes the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+ {
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until RVU flag is RESET */
+ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the IWDG state.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL state
+ */
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
+{
+ return hiwdg->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
new file mode 100644
index 000000000..0607b4122
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
@@ -0,0 +1,311 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_IWDG_H
+#define __STM32F0xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+
+}HAL_IWDG_StateTypeDef;
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+
+}IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
+ * @brief IWDG registers bit mask
+ * @{
+ */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
+#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
+#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
+#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
+
+#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
+ ((__KR__) == KR_KEY_ENABLE))|| \
+ ((__KR__) == KR_KEY_EWA)) || \
+ ((__KR__) == KR_KEY_DWA))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition IWDG Flag definition
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
+#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
+
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Reload_Value IWDG Reload Value
+ * @{
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_CounterWindow_Value IWDG CounterWindow Value
+ * @{
+ */
+#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF)
+/**
+ * @}
+ */
+/** @defgroup IWDG_Window_option IWDG Window option
+ * @{
+ */
+#define IWDG_WINDOW_DISABLE 0xFFF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @brief Reset IWDG handle state
+ * @param __HANDLE__: IWDG handle.
+ * @retval None
+ */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
+/**
+ * @brief Enables the IWDG peripheral.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
+
+/**
+ * @brief Gets the selected IWDG's flag status.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @arg IWDG_FLAG_WVU: Watchdog counter window value flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
new file mode 100644
index 000000000..ecec1e265
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
@@ -0,0 +1,1360 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pcd.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __USB_CLK_ENABLE);
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD HAL module driver
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCD_Private_Define PCD Private Define
+ * @{
+ */
+#define BTABLE_ADDRESS (0x000)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and create the associated handle.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t i = 0;
+
+ uint32_t wInterrupt_Mask = 0;
+
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+ hpcd->State = PCD_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+
+ /* Init endpoints structures */
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1;
+ hpcd->IN_ep[i].num = i;
+ /* Control until ep is actvated */
+ hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0;
+ hpcd->IN_ep[i].xfer_buff = 0;
+ hpcd->IN_ep[i].xfer_len = 0;
+ }
+
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0;
+ hpcd->OUT_ep[i].xfer_buff = 0;
+ hpcd->OUT_ep[i].xfer_len = 0;
+ }
+
+ /* Init Device */
+ /*CNTR_FRES = 1*/
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /*CNTR_FRES = 0*/
+ hpcd->Instance->CNTR = 0;
+
+ /*Clear pending interrupts*/
+ hpcd->Instance->ISTR = 0;
+
+ /*Set Btable Adress*/
+ hpcd->Instance->BTABLE = BTABLE_ADDRESS;
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ hpcd->USB_Address = 0;
+ hpcd->State= PCD_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = PCD_BUSY;
+
+ /* Stop Device */
+ HAL_PCD_Stop(hpcd);
+
+ /* DeInit the low level hardware */
+ HAL_PCD_MspDeInit(hpcd);
+
+ hpcd->State = PCD_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start The USB OTG Device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+ /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+ hpcd->Instance->BCDR |= USB_BCDR_DPPU;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop The USB OTG Device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* disable all interrupts and force USB reset */
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /* clear interrupt status register */
+ hpcd->Instance->ISTR = 0;
+
+ /* switch-off device */
+ hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+/**
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t count=0;
+ uint8_t EPindex;
+ __IO uint16_t wIstr;
+ __IO uint16_t wEPVal = 0;
+
+ /* stay in loop while pending interrupts */
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, 0);
+
+
+ if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ {
+ hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0;
+ }
+
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0)
+ {
+ /* Get SETUP Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ /* SETUP bit kept frozen while CTR_RX = 1*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+ HAL_PCD_SetupStageCallback(hpcd);
+ }
+
+ else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ /* Get Control Data OUT Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ ep->xfer_buff+=ep->xfer_count;
+ }
+
+ /* Process Control Data OUT Packet*/
+ HAL_PCD_DataOutStageCallback(hpcd, 0);
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
+ }
+ }
+ else
+ {
+
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+ if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
+ ep = &hpcd->OUT_ep[EPindex];
+
+ /* OUT double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
+ }
+ /*multi-packet on the NON control OUT endpoint*/
+ ep->xfer_count+=count;
+ ep->xfer_buff+=count;
+
+ if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ {
+ /* RX COMPLETE */
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+
+ } /* if((wEPVal & EP_CTR_RX) */
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0)
+ {
+ ep = &hpcd->IN_ep[EPindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
+
+ /* IN double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
+ }
+ /*multi-packet on the NON control IN endpoint*/
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff+=ep->xfer_count;
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0)
+ {
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t wInterrupt_Mask = 0;
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+ {
+ /* servicing of the endpoint correct transfer interrupt */
+ /* clear of the CTR flag into the sub */
+ PCD_EP_ISR_Handler(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+ HAL_PCD_ResetCallback(hpcd);
+ HAL_PCD_SetAddress(hpcd, 0);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+ {
+
+ hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+ {
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+ /* Force low-power mode in the macrocell */
+ hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+ hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+ HAL_PCD_SOFCallback(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+ {
+ /* clear ESOF flag in ISTR */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+ }
+}
+
+/**
+ * @brief Data out stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd: ppp handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callbacks
+ * @param hpcd: ppp handle
+ * @retval None
+ */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+ hpcd->Instance->BCDR |= USB_BCDR_DPPU;
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Disable DP Pull-Down bit*/
+ hpcd->Instance->BCDR &= ~(USB_BCDR_DPPU);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address
+ * @param hpcd: PCD handle
+ * @param address: new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+
+ if(address == 0)
+ {
+ /* set device address and enable function */
+ hpcd->Instance->DADDR = USB_DADDR_EF;
+ }
+ else /* USB Address will be applied later */
+ {
+ hpcd->USB_Address = address;
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param ep_mps: endpoint max packert size
+ * @param ep_type: endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+
+ __HAL_LOCK(hpcd);
+
+/* initialize Endpoint */
+ switch (ep->type)
+ {
+ case PCD_EP_TYPE_CTRL:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
+ break;
+ case PCD_EP_TYPE_BULK:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
+ break;
+ case PCD_EP_TYPE_INTR:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
+ break;
+ case PCD_EP_TYPE_ISOC:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
+ break;
+ }
+
+ PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0)
+ {
+ if (ep->is_in)
+ {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ /* Configure NAK status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /*Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ /*Set the endpoint Receive buffer counter*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure VALID status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ /*Set the endpoint as double buffered*/
+ PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
+ /*Set buffer address for double buffered mode*/
+ PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+
+ if (ep->is_in==0)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return ret;
+}
+
+
+/**
+ * @brief Deactivate an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->doublebuffer == 0)
+ {
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ if (ep->is_in==0)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the reception buffer
+ * @param len: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 0;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0;
+ }
+
+ /* configure and validate Rx endpoint */
+ if (ep->doublebuffer == 0)
+ {
+ /*Set RX buffer count*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
+ }
+ else
+ {
+ /*Set the Double buffer counter*/
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+ }
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval Data Size
+ */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the transmission buffer
+ * @param len: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t pmabuffer = 0;
+
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 1;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ /*Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
+ PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
+ }
+ else
+ {
+ /*Set the Double buffer counter*/
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+ /*Write the data to the USB endpoint*/
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
+ {
+ pmabuffer = ep->pmaaddr1;
+ }
+ else
+ {
+ pmabuffer = ep->pmaaddr0;
+ }
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
+ }
+
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ __HAL_LOCK(hpcd);
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 1;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ if (ep->num == 0)
+ {
+ /* This macro sets STALL status for RX & TX*/
+ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
+ }
+ else
+ {
+ if (ep->is_in)
+ {
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL);
+ }
+ else
+ {
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
+ }
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 0;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR |= USB_CNTR_RESUME;
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf = pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ }
+}
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD state
+ * @param hpcd : PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
new file mode 100644
index 000000000..47fc4318a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
@@ -0,0 +1,783 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pcd.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_PCD_H
+#define __STM32F0xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structures definition
+ */
+typedef enum
+{
+ PCD_READY = 0x00,
+ PCD_ERROR = 0x01,
+ PCD_BUSY = 0x02,
+ PCD_TIMEOUT = 0x03
+} PCD_StateTypeDef;
+
+typedef enum
+{
+ /* double buffered endpoint direction */
+ PCD_EP_DBUF_OUT,
+ PCD_EP_DBUF_IN,
+ PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/* endpoint buffer number */
+typedef enum
+{
+ PCD_EP_NOBUF,
+ PCD_EP_BUF0,
+ PCD_EP_BUF1
+}PCD_EP_BUF_NUM;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Core_Speed */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref PCD_EP0_MPS */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_Core_PHY */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t low_power_enable; /*!< Enable or disable Low Power mode
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+
+}PCD_InitTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref PCD_EP_Type */
+
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}PCD_EPTypeDef;
+
+typedef USB_TypeDef PCD_TypeDef;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+#include "stm32f0xx_hal_pcd_ex.h"
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Core_Speed PCD Core Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0 /* Not Supported */
+#define PCD_SPEED_FULL 2
+/**
+ * @}
+ */
+
+ /** @defgroup PCD_Core_PHY PCD Core PHY
+ * @{
+ */
+#define PCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+ * @{
+ */
+#define DEP0CTL_MPS_64 0
+#define DEP0CTL_MPS_32 1
+#define DEP0CTL_MPS_16 2
+#define DEP0CTL_MPS_8 3
+
+#define PCD_EP0MPS_64 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP_Type PCD EP Type
+ * @{
+ */
+#define PCD_EP_TYPE_CTRL 0
+#define PCD_EP_TYPE_ISOC 1
+#define PCD_EP_TYPE_BULK 2
+#define PCD_EP_TYPE_INTR 3
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP_Type PCD_ENDP_Type
+ * @{
+ */
+
+#define PCD_ENDP0 ((uint8_t)0)
+#define PCD_ENDP1 ((uint8_t)1)
+#define PCD_ENDP2 ((uint8_t)2)
+#define PCD_ENDP3 ((uint8_t)3)
+#define PCD_ENDP4 ((uint8_t)4)
+#define PCD_ENDP5 ((uint8_t)5)
+#define PCD_ENDP6 ((uint8_t)6)
+#define PCD_ENDP7 ((uint8_t)7)
+
+/* Endpoint Kind */
+#define PCD_SNG_BUF 0
+#define PCD_DBL_BUF 1
+
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP
+#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP)
+#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+
+/**
+ * @}
+ */
+
+/* Internal macros -----------------------------------------------------------*/
+
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
+
+
+
+/**
+ * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wType: Endpoint Type.
+ * @retval None
+ */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+
+/**
+ * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Type
+ */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: Direction
+ * @retval None
+ */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+ if ((bDir) == PCD_EP_DBUF_OUT)\
+ { /* OUT double buffered endpoint */\
+ PCD_TX_DTOG((USBx), (bEpNum));\
+ }\
+ else if ((bDir) == PCD_EP_DBUF_IN)\
+ { /* IN double buffered endpoint */\
+ PCD_RX_DTOG((USBx), (bEpNum));\
+ }\
+}
+
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval EP_DBUF_OUT, EP_DBUF_IN,
+ * EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+ if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+ return(PCD_EP_DBUF_OUT);\
+ else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+ return(PCD_EP_DBUF_IN);\
+ else\
+ return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+ * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wState))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wState))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_TX_STATUS */
+
+/**
+ * @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & (wState))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wState))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_RX_STATUS */
+
+/**
+ * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wStaterx: new state.
+ * @param wStatetx: new state.
+ * @retval None
+ */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
+ } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+ * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval status
+ */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+ * @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+ * @brief checks stall condition in an endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval TRUE = endpoint in stall condition.
+ */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_RX_STALL)
+
+/**
+ * @brief set & clear EP_KIND bit.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+
+/**
+ * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+
+/**
+ * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+
+/**
+ * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+ PCD_RX_DTOG((USBx), (bEpNum))
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+ PCD_TX_DTOG((USBx), (bEpNum))
+
+/**
+ * @brief Sets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bAddr: Address.
+ * @retval None
+ */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400)))
+
+/**
+ * @brief sets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wAddr: address to be set (must be word aligned).
+ * @retval None
+ */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+
+/**
+ * @brief Gets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval address of the buffer.
+ */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Sets counter of rx buffer with no. of blocks.
+ * @param dwReg: Register
+ * @param wCount: Counter.
+ * @param wNBlocks: no. of Blocks.
+ * @retval None
+ */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 5;\
+ if(((wCount) & 0x1f) == 0)\
+ (wNBlocks)--;\
+ *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\
+ }/* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 1;\
+ if(((wCount) & 0x1) != 0)\
+ (wNBlocks)++;\
+ *pdwReg = (uint16_t)((wNBlocks) << 10);\
+ }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
+ uint16_t wNBlocks;\
+ if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\
+ else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\
+ }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+ }
+/**
+ * @brief sets counter for the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wCount: Counter value.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ }
+
+/**
+ * @brief gets counter of the tx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Counter value
+ */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+
+/**
+ * @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @retval Counter value
+ */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+
+/**
+ * @brief Sets addresses in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+ } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount: Counter value
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ /* IN endpoint */ \
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ /* IN endpoint */\
+ *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ } /* PCD_SET_EP_DBUF_CNT */
+
+/**
+ * @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PCD_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+ /* Non Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
new file mode 100644
index 000000000..b25c170de
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
@@ -0,0 +1,153 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Configuration of the PMA for EP
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx Extended HAL module driver
+ * @brief PCDEx PCDEx Extended HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group2 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral extended features methods #####
+ ===============================================================================
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure PMA for EP
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param ep_kind: endpoint Kind
+ * @arg USB_SNG_BUF: Single Buffer used
+ * @arg USB_DBL_BUF: Double Buffer used
+ * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
+ * this parameter is 16-bit value providing the address
+ * in PMA allocated to endpoint.
+ * In case of double buffer endpoint this parameter
+ * is a 32-bit value providing the endpoint buffer 0 address
+ * in the LSB part of 32-bit value and endpoint buffer 1 address
+ * in the MSB part of 32-bit value.
+ * @retval : status
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress)
+
+{
+ PCD_EPTypeDef *ep;
+
+ /* initialize ep structure*/
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ /* Here we check if the endpoint is single or double Buffer*/
+ if (ep_kind == PCD_SNG_BUF)
+ {
+ /*Single Buffer*/
+ ep->doublebuffer = 0;
+ /*Configure te PMA*/
+ ep->pmaadress = (uint16_t)pmaadress;
+ }
+ else /*USB_DBL_BUF*/
+ {
+ /*Double Buffer Endpoint*/
+ ep->doublebuffer = 1;
+ /*Configure the PMA*/
+ ep->pmaaddr0 = pmaadress & 0xFFFF;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
new file mode 100644
index 000000000..167070957
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of PCD HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_PCD_EX_H
+#define __STM32L0xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Internal macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PCDEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PCDEx_Exported_Functions_Group2
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
new file mode 100644
index 000000000..a65152763
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
@@ -0,0 +1,470 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pwr.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization function
+ * + Peripheral Control function
+ *
+ @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR HAL module Driver
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __PWR_FORCE_RESET();
+ __PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enables access to the backup domain (RTC registers, RTC
+ * backup data registers).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ PWR->CR |= (uint32_t)PWR_CR_DBP;
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ PWR->CR &= ~((uint32_t)PWR_CR_DBP);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
+ forced in input pull down configuration and is active on rising edges.
+ (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
+ (++)WakeUp Pin 1 on PA.00.
+ (++)WakeUp Pin 2 on PC.13.
+ (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
+ (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
+ (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
+ (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
+ (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
+ (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The devices feature 3 low-power modes:
+ (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
+ (+) Stop mode: all clocks are stopped, regulator running, regulator
+ in low power mode
+ (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
+ functions with
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ (+) Exit:
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+
+ *** Stop mode ***
+ =================
+ [..]
+ In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents
+ are preserved.
+ The voltage regulator can be configured either in normal or low-power mode.
+ To minimize the consumption.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
+ function with:
+ (++) Main regulator ON.
+ (++) Low Power regulator ON.
+ (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
+ (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
+ (+) Exit:
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+ (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
+ when programmed in wakeup mode (the peripheral must be
+ programmed in wakeup mode and the corresponding interrupt vector
+ must be enabled in the NVIC)
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode allows to achieve the lowest power consumption. It is based
+ on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
+ The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
+ the HSE oscillator are also switched off. SRAM and register contents are lost
+ except for the RTC registers, RTC backup registers and Standby circuitry.
+ The voltage regulator is OFF.
+
+ (+) Entry:
+ (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..]
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event,
+ without depending on an external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ is necessary to configure the RTC to detect the tamper or time stamp event using the
+ HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
+
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
+
+ (+) Comparator auto-wakeup (AWU) from the Stop mode
+
+ (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
+ (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
+ to be sensitive to to the selected edges (falling, rising or falling
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+ (+++) Configure the comparator to generate the event.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ * This parameter can be value of :
+ * @ref PWREx_WakeUp_Pins
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
+}
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * This parameter can be values of :
+ * @ref PWREx_WakeUp_Pins
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
+}
+
+/**
+ * @brief Enters Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param Regulator: Specifies the regulator state in SLEEP mode.
+ * On STM32F0 devices, this parameter is a dummy value and it is ignored
+ * as regulator can't be modified in this mode. Parameter is kept for platform
+ * compatibility.
+ * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ * When WFI entry is used, tick interrupt have to be disabled if not desired as
+ * the interrupt wake up source.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
+ * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
+
+ /* Set LPDS bit according to Regulator value */
+ tmpreg |= Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available)
+ * - RTC alternate function pins if configured for tamper, time-stamp, RTC
+ * Alarm out, or RTC clock calibration out.
+ * - WKUP pins if enabled.
+ * STM32F0x8 devices, the Stop mode is available, but it is
+ * aningless to distinguish between voltage regulator in Low power
+ * mode and voltage regulator in Run mode because the regulator
+ * not used and the core is supplied directly from an external source.
+ * Consequently, the Standby mode is not available on those devices.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select STANDBY mode */
+ PWR->CR |= (uint32_t)PWR_CR_PDDS;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
new file mode 100644
index 000000000..572532364
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
@@ -0,0 +1,207 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pwr.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_PWR_H
+#define __STM32F0xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR PWR HAL module Driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A),
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * Warning: this Flag is not available on STM32F030x8 products
+ * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
+ * voltage VREFINT is ready.
+ * Warning: this Flag is not available on STM32F030x8 products
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
+
+
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extension module */
+#include "stm32f0xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
new file mode 100644
index 000000000..55dd4a383
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx Extended HAL module driver
+ * @brief PWREx HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000)
+#define PVD_MODE_EVT ((uint32_t)0x00020000)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral extended control functions #####
+ ===============================================================================
+
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ HAL_PWR_PVDConfig(), HAL_PWR_EnablePVD() functions.
+ (+) The PVD is stopped in Standby mode.
+ -@- PVD is not available on STM32F030x4/x6/x8
+
+ *** VDDIO2 Monitor Configuration ***
+ ====================================
+ [..]
+ (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it
+ to VREFInt Voltage
+ (+) This monitor is internally connected to the EXTI line31
+ and can generate an interrupt if enabled. This is done through
+ HAL_PWR_EnableVddio2Monitor() function.
+ -@- VDDIO2 is available on STM32F07x/09x/04x
+
+@endverbatim
+ * @{
+ */
+
+#if defined (STM32F031x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F091xC) || \
+ defined (STM32F042x6) || defined (STM32F072xB)
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER();
+ }
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ PWR->CR |= (uint32_t)PWR_CR_PVDE;
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ PWR->CR &= ~((uint32_t)PWR_CR_PVDE);
+}
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ /* Check PWR exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F091xC) || */
+ /* defined (STM32F042x6) || defined (STM32F072xB) */
+
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+/**
+ * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection.
+ * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint,
+ an interrupt is generated Irq line 1.
+ NVIS has to be enable by user.
+ * @retval None
+ */
+void HAL_PWR_EnableVddio2Monitor(void)
+{
+ __HAL_PWR_VDDIO2_EXTI_ENABLE_IT();
+ __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER();
+}
+
+/**
+ * @brief Disable the Vddio2 Monitor.
+ * @retval None
+ */
+void HAL_PWR_DisableVddio2Monitor(void)
+{
+ __HAL_PWR_VDDIO2_EXTI_DISABLE_IT();
+ __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER();
+
+}
+
+/**
+ * @brief This function handles the PWR Vddio2 monitor interrupt request.
+ * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_Vddio2Monitor_IRQHandler(void)
+{
+ /* Check PWR exti flag */
+ if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR Vddio2 monitor interrupt user callback */
+ HAL_PWR_Vddio2MonitorCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR Vddio2 Monitor interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_Vddio2MonitorCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_Vddio2MonitorCallback could be implemented in the user file
+ */
+}
+
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
new file mode 100644
index 000000000..43e482263
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of PWR HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_PWR_EX_H
+#define __STM32F0xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+ * @{
+ */
+
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ This parameter can be a value of @ref PWREx_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWREx_PVD_Mode */
+}PWR_PVDTypeDef;
+
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+
+
+/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
+ * @{
+ */
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
+#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
+#define PWR_WAKEUP_PIN3 ((uint32_t)0x02)
+#define PWR_WAKEUP_PIN4 ((uint32_t)0x03)
+#define PWR_WAKEUP_PIN5 ((uint32_t)0x04)
+#define PWR_WAKEUP_PIN6 ((uint32_t)0x05)
+#define PWR_WAKEUP_PIN7 ((uint32_t)0x06)
+#define PWR_WAKEUP_PIN8 ((uint32_t)0x07)
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3) || \
+ ((PIN) == PWR_WAKEUP_PIN4) || \
+ ((PIN) == PWR_WAKEUP_PIN5) || \
+ ((PIN) == PWR_WAKEUP_PIN6) || \
+ ((PIN) == PWR_WAKEUP_PIN7) || \
+ ((PIN) == PWR_WAKEUP_PIN8))
+#else
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
+#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN2))
+#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || */
+ /* defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_EXTI_Line PWREx EXTI Line
+ * @{
+ */
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+
+#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)0x80000000) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
+
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
+/**
+ * @}
+ */
+
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVD_Mode PWREx PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
+
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+/**
+ * @}
+ */
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+
+/** @defgroup PWREx_Flag PWREx Flag
+ * @{
+ */
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
+#else
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
+ * @{
+ */
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief PVD EXTI line configuration: clear falling edge and rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \
+ EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+
+
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+/**
+ * @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
+
+/**
+ * @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
+
+/**
+ * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
+ EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2)
+
+/**
+ * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
+
+/**
+ * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
+ * @retval EXTI VDDIO2 Monitor Line Status.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
+
+/**
+ * @brief Clear the VDDIO2 Monitor EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
+
+
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+void HAL_PWR_Vddio2Monitor_IRQHandler(void);
+void HAL_PWR_Vddio2MonitorCallback(void);
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) */
+
+/* Peripheral Control functions **********************************************/
+#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || \
+ defined (STM32F091xC)
+void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
+ /* defined (STM32F071xB) || defined (STM32F072xB) || */
+ /* defined (STM32F091xC) */
+
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+void HAL_PWR_EnableVddio2Monitor(void);
+void HAL_PWR_DisableVddio2Monitor(void);
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
new file mode 100644
index 000000000..34315ac04
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
@@ -0,0 +1,628 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rcc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
+ and all peripherals are off except internal SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registeres.
+ (+) This delay depends on the peripheral mapping.
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ after the clock enable bit is set on the hardware register
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ after the clock enable bit is set on the hardware register
+
+ [..]
+ Possible Workarounds:
+ (#) Enable the peripheral clock sometimes before the peripheral read/write
+ register is required.
+ (#) For AHB peripheral, insert two dummy read to the peripheral register.
+ (#) For APB peripheral, insert a dummy read to the peripheral register.
+
+@endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC HAL module driver
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Define RCC Private Define
+ * @{
+ */
+#define RCC_CFGR_HPRE_BITNUMBER 4
+#define RCC_CFGR_PPRE_BITNUMBER 8
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+#define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
+#define MCO_GPIO_PORT GPIOA
+#define MCO_PIN GPIO_PIN_8
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization function #####
+ ===============================================================================
+ [..]
+ This section provide functions allowing to configure the internal/external oscillators
+ (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK,
+ AHB and APB1).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+ The HSI clock can be used also to clock the USART and I2C peripherals.
+
+ (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
+ the ADC peripheral.
+
+ (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 48 MHz)
+ (++) The second output is used to generate the clock for the USB FS (48 MHz)
+ (++) The third output may be used to generate the clock for the TIM, I2C and USART
+ peripherals (up to 48 MHz)
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clockis automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
+ clock (divided by 2) output on pin (such as PA8 pin).
+
+ [..] System, AHB and APB busses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (++) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (++) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (++) The ADC clock which is derived from PLL output.
+ (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (++) IWDG clock which is always the LSI clock.
+
+ (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ +-----------------------------------------------+
+
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
+
+ /* Reset HSEON, CSSON, PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+ /* Reset CFGR3 register */
+ CLEAR_REG(RCC->CFGR3);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
+ /* handle the possible oscillators present in STM32F0xx devices */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency: FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
+ /* handle the possible oscillators present in STM32F0xx devices */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function
+ * @brief RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the clock source to output on MCO pin(such as PA8).
+ * @note MCO pin (such as PA8) should be configured in alternate function mode.
+ * @param RCC_MCOx: specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
+ * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
+ * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
+ * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
+ * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices)
+ * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
+ * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
+ * @param RCC_MCODiv: specifies the MCOx prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO_NODIV: no division applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ /* RCC_MCO */
+ assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
+
+ /* MCO Clock Enable */
+ __MCO_CLK_ENABLE();
+
+ /* Configue the MCO pin in alternate function mode */
+ gpio.Pin = MCO_PIN;
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ gpio.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
+
+ /* Configure the MCO clock source */
+ __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
+ * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
+ * PLL factor .
+ * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
+ * (default values 8 MHz and 48MHz).
+ * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @retval SYSCLK frequency
+ */
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
+ /* handle the possible oscillators present in STM32F0xx devices */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ *
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
+ RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
+
+ /* Get the HSI14 configuration -----------------------------------------------*/
+ if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
+ {
+ RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber);
+
+ /* Get the HSI48 configuration if any-----------------------------------------*/
+ RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * contains the current clock configuration.
+ * @param pFLatency: Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CCSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval none
+ */
+__weak void HAL_RCC_CCSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CCSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
new file mode 100644
index 000000000..7b9785c51
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
@@ -0,0 +1,1255 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_RCC_H
+#define __STM32F0xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
+
+}RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The Oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t HSI14State; /*!< The new state of the HSI14.
+ This parameter can be a value of @ref RCC_HSI14_Config */
+
+ uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
+ This parameter can be a value of @ref RCCEx_HSI48_Config */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+}RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
+/* --- CIR Register ---*/
+#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
+/* --- BDCR Register ---*/
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
+/* --- CSR Register ---*/
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
+/* --- CR2 Register ---*/
+#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
+
+/* CSR register byte 1 (Bits[15:8]) base address */
+#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
+
+/* BDCR register byte 0 (Bits[7:0] base address */
+#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_CFGR_PLLMUL_BITNUMBER 18
+#define RCC_CFGR2_PREDIV_BITNUMBER 0
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+/* LSE state change timeout */
+#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+
+/* Disable Backup domain write protection state change timeout */
+#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
+#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config RCC HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config RCC_LSE_Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config RCC HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint8_t)0x00)
+#define RCC_HSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI14_Config RCC HSI14 Config
+ * @{
+ */
+#define RCC_HSI14_OFF ((uint32_t)0x00)
+#define RCC_HSI14_ON RCC_CR2_HSI14ON
+#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
+
+#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
+
+#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config RCC LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint8_t)0x00)
+#define RCC_LSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config RCC PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint8_t)0x00)
+#define RCC_PLL_OFF ((uint8_t)0x01)
+#define RCC_PLL_ON ((uint8_t)0x02)
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
+ * @{
+ */
+#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
+ ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
+ ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
+ ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
+ ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
+ ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
+ ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
+ ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
+ * @{
+ */
+#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
+#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
+#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
+#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
+#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
+#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
+#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
+#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
+#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
+
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
+ ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
+ ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
+ ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
+ ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
+ ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
+ ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
+ ((MUL) == RCC_PLL_MUL16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
+
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
+
+#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
+ ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
+ ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
+ ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
+ ((DIV) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
+
+#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
+ ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
+ ((DIV) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
+ ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
+ * @{
+ */
+#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
+
+#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Index RCC MCOx Index
+ * @{
+ */
+#define RCC_MCO ((uint32_t)0x00000000)
+
+#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
+ * @{
+ */
+#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt RCC Interrupt
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_HSI14 ((uint8_t)0x20)
+#define RCC_IT_CSS ((uint8_t)0x80)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag RCC Flag
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XX : Register index
+ * - 00: CR register
+ * - 01: CR2 register
+ * - 10: BDCR register
+ * - 11: CSR register
+ * @{
+ */
+#define CR_REG_INDEX 0
+#define CR2_REG_INDEX 1
+#define BDCR_REG_INDEX 2
+#define CSR_REG_INDEX 3
+
+/* Flags in the CR register */
+#define RCC_CR_HSIRDY_BitNumber 1
+#define RCC_CR_HSERDY_BitNumber 17
+#define RCC_CR_PLLRDY_BitNumber 25
+
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
+
+/* Flags in the CR2 register */
+#define RCC_CR2_HSI14RDY_BitNumber 1
+
+#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
+
+/* Flags in the BDCR register */
+#define RCC_BDCR_LSERDY_BitNumber 1
+
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
+
+/* Flags in the CSR register */
+#define RCC_CSR_LSIRDY_BitNumber 1
+#define RCC_CSR_V18PWRRSTF_BitNumber 23
+#define RCC_CSR_RMVF_BitNumber 24
+#define RCC_CSR_OBLRSTF_BitNumber 25
+#define RCC_CSR_PINRSTF_BitNumber 26
+#define RCC_CSR_PORRSTF_BitNumber 27
+#define RCC_CSR_SFTRSTF_BitNumber 28
+#define RCC_CSR_IWDGRSTF_BitNumber 29
+#define RCC_CSR_WWDGRSTF_BitNumber 30
+#define RCC_CSR_LPWRRSTF_BitNumber 31
+
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
+#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
+#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Calibration_values RCC Calibration values
+ * @{
+ */
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Timeout
+ * @{
+ */
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
+#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
+#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
+#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
+#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
+#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
+#define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
+#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
+
+#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
+#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
+#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
+#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
+#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
+#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+
+#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
+#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
+#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
+#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
+#define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
+#define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
+#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
+
+#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
+#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
+#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
+#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
+#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
+
+#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
+#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
+#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
+#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
+
+#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__: specifies the calibration trimming value
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define RCC_CR_HSITRIM_BitNumber 3
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
+ * @{
+ */
+
+/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSEPredivValue__: specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
+ * @{
+ */
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
+ * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI14 can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI14.
+ * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
+ * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
+ * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
+ * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
+#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
+
+/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
+ */
+#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
+#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
+
+/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI14 RC.
+ * @param __HSI14CalibrationValue__: specifies the calibration trimming value
+ * (default is RCC_HSI14CALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define RCC_CR2_HSI14TRIM_BitNumber 3
+#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
+ MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the USART1 clock (USART1CLK).
+ * @param __USART1CLKSource__: specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
+
+/** @brief Macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
+ * @param __I2C1CLKSource__: specifies the I2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
+
+/** @brief Macro to get the I2C1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+/** @brief Macros to enable or disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief Macro to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * a Power On Reset (POR).
+ * @param __RTCCLKSource__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
+ *
+ * @note If the LSE is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
+ * the RTC cannot be used in STOP and STANDBY modes.
+ * @note The system must always be configured so as to get a PCLK frequency greater than or
+ * equal to the RTCCLK frequency for a proper operation of the RTC.
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
+ * @{
+ */
+
+/** @brief Macro to force or release the Backup domain reset.
+ * @note These macros reset the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
+ * @{
+ */
+
+/** @brief Macro to enable or disable the PLL.
+ * @note After enabling the PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL can not be disabled if it is used as system clock source
+ * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
+ } while(0)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source RCC Get Clock source
+ * @{
+ */
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock.
+ * The returned value can be one of the following value:
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
+
+/** @brief Macro to get the oscillator used as PLL clock source.
+ * @retval The oscillator used as PLL clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
+ * the selected interrupts.).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
+ * @arg RCC_IT_LSERDY: LSE ready interrupt enable
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
+ * @arg RCC_IT_HSERDY: HSE ready interrupt enable
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
+ * the selected interrupts.).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
+ * @arg RCC_IT_LSERDY: LSE ready interrupt enable
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
+ * @arg RCC_IT_HSERDY: HSE ready interrupt enable
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __IT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
+ * @arg RCC_IT_LSERDY: LSE ready interrupt clear
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
+ * @arg RCC_IT_HSERDY: HSE ready interrupt clear
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
+ * @arg RCC_IT_CSS: Clock Security System interrupt clear
+ */
+#define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __IT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
+ * @arg RCC_IT_LSERDY: LSE ready interrupt flag
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
+ * @arg RCC_IT_HSERDY: HSE ready interrupt flag
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
+ * @arg RCC_IT_CSS: Clock Security System interrupt flag
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
+ * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_OBLRST: Option Byte Load reset
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
+ (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
+ (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
+ RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extension module */
+#include "stm32f0xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ***************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions *********************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CCSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
new file mode 100644
index 000000000..00a4cc123
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
@@ -0,0 +1,1407 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended RCC HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Clock Source configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ For CRS, RCC Extention HAL driver can be used as follows:
+
+ (#) In System clock config, HSI48 need to be enabled
+
+ (#] Enable CRS clock in IP MSP init which will use CRS functions
+
+ (#) Call CRS functions like this
+ (##) Prepare synchronization configuration necessary for HSI48 calibration
+ (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+ and also HSI48 oscillator smooth trimming.
+ (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
+ directly reload value with target and sychronization frequencies values
+ (##) Call function HAL_RCCEx_CRSConfig which
+ (+++) Reset CRS registers to their default values.
+ (+++) Configure CRS registers with synchronization configuration
+ (+++) Enable automatic calibration and frequency error counter feature
+
+ (##) A polling function is provided to wait for complete Synchronization
+ (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+ (+++) According to CRS status, user can decide to adjust again the calibration or continue
+ application if synchronization is OK
+
+ (#) User can retrieve information related to synchronization in calling function
+ HAL_RCCEx_CRSGetSynchronizationInfo()
+
+ (#) Regarding synchronization status and synchronization information, user can try a new calibration
+ in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+ Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
+ it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+ incremented), while when it is detected during the upcounting phase it means that the actual frequency
+ is higher (and that the TRIM value should be decremented).
+
+ (#) To use IT mode, user needs to handle it in calling different macros available to do it
+ (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
+ (++) Call function HAL_RCCEx_CRSConfig()
+ (++) Enable RCC_IRQn (thnaks to NVIC functions)
+ (++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT)
+ (++) Implement CRS status management in RCC_CRS_IRQHandler
+
+ (#) To force a SYNC EVENT, user can use function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be
+ called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx Extended HAL module driver
+ * @brief RCC Extension HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Define RCCEx Private Define
+ * @{
+ */
+#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/* Bit position in register */
+#define CRS_CFGR_FELIM_BITNUMBER 16
+#define CRS_CR_TRIM_BITNUMBER 8
+#define CRS_ISR_FECAP_BITNUMBER 16
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Variables RCCEx Private Variables
+ * @{
+ */
+const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 16};
+const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
+ 9,10, 11, 12, 13, 14, 15, 16};
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) ||
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG((uint8_t)RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) ||
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+ {
+ /* When the HSI is used as system clock it is not allowed to be disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock */
+ __PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if(RCC_OscInitStruct->LSEState == RCC_LSE_ON)
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*----------------------------- HSI14 Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
+
+ /* Check the HSI14 State */
+ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
+ {
+ /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_DISABLE();
+
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI14_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ }
+ else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
+ {
+ /* Enable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_ENABLE();
+
+ /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ }
+ else
+ {
+ /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_DISABLE();
+
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI14_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ /*----------------------------- HSI48 Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+ /* When the HSI48 is used as system clock it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, predivider and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PREDIV,
+ RCC_OscInitStruct->PLL.PLLMUL);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency: FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+ /* Increasing the CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ /* HSI48 is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ /* Check the HSI48 ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+ else
+ {
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /* Decreasing the CPU frequency */
+ else
+ {
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ /* HSI48 is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ /* Check the HSI48 ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+ else
+ {
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
+ * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
+ * PLL factor .
+ * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
+ * (default values 8 MHz and 48MHz).
+ * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0;
+ uint32_t sysclockfreq = 0;
+
+ tmpreg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ sysclockfreq = HSE_VALUE;
+ break;
+
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
+ pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
+ prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
+ if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
+ {
+ /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
+ pllclk = (HSI48_VALUE/prediv) * pllmul;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE/prediv) * pllmul;
+#else
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (HSI_VALUE >> 1) * pllmul;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ sysclockfreq = pllclk;
+ break;
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
+ sysclockfreq = HSI48_VALUE;
+ break;
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default:
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks
+ * (USART, RTC, I2C, CEC and USB).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC configuration -------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Clock*/
+ __PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selction is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg;
+ }
+
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+
+ /*------------------------------- USART1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ /*----------------------------- USART2 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ }
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+ /*----------------------------- USART3 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ }
+#endif /* STM32F091xC || STM32F098xx */
+
+ /*------------------------------ I2C1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ }
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
+ /*------------------------------ USB Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
+
+ /* Configure the USB clock source */
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ /*------------------------------ CEC clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals clocks
+ * (USART, RTC, I2C, CEC and USB).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ /* Common part first */
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
+ /* Get the RTC configuration --------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+ /* Get the USART1 configuration --------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+ /* Get the I2C1 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
+ /* Get the USART2 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3;
+ /* Get the USART3 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+ /* Get the USB clock source ---------------------------------------------*/
+ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
+ /* Get the CEC clock source ------------------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+}
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+/**
+ * @brief Start automatic synchronization using polling mode
+ * @param pInit Pointer on RCC_CRSInitTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+ assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+ assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+ assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+ assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+ assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+
+ /* CONFIGURATION */
+
+ /* Before configuration, reset CRS registers to their default values*/
+ __CRS_FORCE_RESET();
+ __CRS_RELEASE_RESET();
+
+ /* Configure Synchronization input */
+ /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
+ CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
+
+ /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
+ CRS->CFGR |= pInit->Prescaler;
+
+ /* Set the SYNCSRC[1:0] bits according to Source value */
+ CRS->CFGR |= pInit->Source;
+
+ /* Set the SYNCSPOL bits according to Polarity value */
+ CRS->CFGR |= pInit->Polarity;
+
+ /* Configure Frequency Error Measurement */
+ /* Clear RELOAD[15:0] & FELIM[7:0] bits*/
+ CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
+
+ /* Set the RELOAD[15:0] bits according to ReloadValue value */
+ CRS->CFGR |= pInit->ReloadValue;
+
+ /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+ CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
+
+ /* Adjust HSI48 oscillator smooth trimming */
+ /* Clear TRIM[5:0] bits */
+ CRS->CR &= ~CRS_CR_TRIM;
+
+ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+ CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
+
+
+ /* START AUTOMATIC SYNCHRONIZATION*/
+
+ /* Enable Automatic trimming */
+ __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
+
+ /* Enable Frequency error counter */
+ __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
+
+}
+
+/**
+ * @brief Generate the software synchronization event
+ * @retval None
+ */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+ CRS->CR |= CRS_CR_SWSYNC;
+}
+
+
+/**
+ * @brief Function to return synchronization info
+ * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+ * @retval None
+ */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+ /* Check the parameter */
+ assert_param(pSynchroInfo != NULL);
+
+ /* Get the reload value */
+ pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
+
+ /* Get HSI48 oscillator smooth trimming */
+ pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
+
+ /* Get Frequency error capture */
+ pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
+
+ /* Get FFrequency error direction */
+ pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
+
+
+}
+
+/**
+* @brief This function handles CRS Synchronization Timeout.
+* @param Timeout: Duration of the timeout
+* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
+* frequency.
+* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+* This parameter can be a combination of the following values:
+* @arg RCC_CRS_TIMEOUT
+* @arg RCC_CRS_SYNCOK
+* @arg RCC_CRS_SYNCWARM
+* @arg RCC_CRS_SYNCERR
+* @arg RCC_CRS_SYNCMISS
+* @arg RCC_CRS_TRIMOV
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+ uint32_t crsstatus = RCC_CRS_NONE;
+ uint32_t tickstart = 0;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check that if one of CRS flags have been set */
+ while(RCC_CRS_NONE == crsstatus)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ crsstatus = RCC_CRS_TIMEOUT;
+ }
+ }
+ /* Check CRS SYNCOK flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+ {
+ /* CRS SYNC event OK */
+ crsstatus |= RCC_CRS_SYNCOK;
+
+ /* Clear CRS SYNC event OK bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+ }
+
+ /* Check CRS SYNCWARN flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+ {
+ /* CRS SYNC warning */
+ crsstatus |= RCC_CRS_SYNCWARM;
+
+ /* Clear CRS SYNCWARN bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+ }
+
+ /* Check CRS TRIM overflow flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+ {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_TRIMOV;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+ }
+
+ /* Check CRS Error flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+ {
+ /* CRS SYNC Error */
+ crsstatus |= RCC_CRS_SYNCERR;
+
+ /* Clear CRS Error bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+ }
+
+ /* Check CRS SYNC Missed flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+ {
+ /* CRS SYNC Missed */
+ crsstatus |= RCC_CRS_SYNCMISS;
+
+ /* Clear CRS SYNC Missed bit */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+ }
+
+ /* Check CRS Expected SYNC flag */
+ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+ {
+ /* frequency error counter reached a zero value */
+ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+ }
+ }
+
+ return crsstatus;
+}
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
new file mode 100644
index 000000000..c070dcb62
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
@@ -0,0 +1,1680 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_RCC_EX_H
+#define __STM32F0xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F030xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F071xB */
+
+#if defined(STM32F072xB) || defined(STM32F078xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F072xB || STM32F078xx */
+
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/**
+ * @brief RCC_CRS Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
+ This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
+
+ uint32_t Source; /*!< Specifies the SYNC signal source.
+ This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
+
+ uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
+ This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+ uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+ It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
+ This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
+ This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+ This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+ * @brief RCC_CRS Synchronization structure definition
+ */
+typedef struct
+{
+ uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
+ This parameter must be a number between 0 and 0xFFFF*/
+
+ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+ This parameter must be a number between 0 and 0x3F */
+
+ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+ value latched in the time of the last SYNC event.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+ frequency error counter latched in the time of the last SYNC event.
+ It shows whether the actual frequency is below or above the target.
+ This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+#endif /* STM32F042x6 || STM32F048xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define RCC_CRS_NONE ((uint32_t)0x00000000)
+#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
+#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
+#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
+#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
+#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
+#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
+
+#endif /* STM32F042x6 || STM32F048xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F030xC)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F071xB */
+
+#if defined(STM32F072xB) || defined(STM32F078xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F072xB || STM32F078xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
+ * @{
+ */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
+
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI48))
+
+#define RCC_IT_HSI48 ((uint8_t)0x40)
+
+/* Flags in the CR2 register */
+#define RCC_CR2_HSI48RDY_BitNumber 16
+
+#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+
+/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
+ * @{
+ */
+#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
+#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
+ ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
+ * @{
+ */
+#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
+ * @{
+ */
+#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
+#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
+#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
+ * @{
+ */
+#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
+#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
+#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+#endif /* STM32F091xC || STM32F098xx */
+
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
+#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
+
+#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+#define RCC_HSI48_ON ((uint8_t)0x01)
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+/**
+ * @}
+ */
+#else
+/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
+ * @{
+ */
+
+#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#else
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
+#endif
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
+ * @{
+ */
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
+ * @{
+ */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define RCC_MCO_NODIV ((uint32_t)0x00000000)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
+#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
+#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
+#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
+#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
+#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
+#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
+#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
+ ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
+ ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
+ ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+ * @{
+ */
+#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
+#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
+
+#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+ * @{
+ */
+#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+
+#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+ * @{
+ */
+#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+
+#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+ * @{
+ */
+#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
+ to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+
+#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+ * @{
+ */
+#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
+
+#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+ * @{
+ */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+ The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+ corresponds to a higher output frequency */
+
+#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+ * @{
+ */
+#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+
+#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+ * @{
+ */
+#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
+#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
+#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
+#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
+#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+ * @{
+ */
+#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
+#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
+#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
+#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
+#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
+#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
+
+#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
+
+#endif /* STM32F030x6 || STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || STM32F070xB || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
+
+#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
+
+#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
+
+#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if defined(STM32F030x8) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+
+#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+
+#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+
+#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+
+#endif /* STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+
+#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
+
+#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
+#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
+#define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
+
+#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+
+#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
+
+#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
+#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
+
+#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
+
+#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
+
+#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
+#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
+
+#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
+#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
+ * @brief Forces or releases peripheral reset.
+ * @{
+ */
+
+/** @brief Force or release AHB peripheral reset.
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
+
+#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
+
+#endif /* STM32F030x6 || STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+
+#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+
+#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#if defined(STM32F030x8) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+
+#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+
+#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+
+#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+
+#endif /* STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
+
+#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+
+#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+
+#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
+
+#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
+
+#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
+
+#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+
+#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
+#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
+
+#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
+#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
+ * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
+ * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI48 can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI14.
+ * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
+ * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
+ * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
+ * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
+ * clock cycles.
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
+#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
+
+/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_HSI48_ON: HSI48 enabled
+ * @arg RCC_HSI48_OFF: HSI48 disabled
+ */
+#define __HAL_RCC_GET_HSI48_STATE() \
+ (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
+
+#else
+
+/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_HSI_OFF: HSI48 disabled
+ */
+#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F070x6) || defined(STM32F070xB)
+
+/** @brief Macro to configure the USB clock (USBCLK).
+ * @param __USBCLKSource__: specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
+ * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
+
+/** @brief Macro to get the USB clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
+ * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F072xB || STM32F078xx || */
+ /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @brief Macro to configure the CEC clock.
+ * @param __CECCLKSource__: specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
+
+/** @brief Macro to get the HDMI CEC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || defined(STM32F098xx) */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSource__: specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
+ * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
+ * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
+ * @param __MCODiv__: specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO_DIV1: MCO clock source is divided by 1
+ * @arg RCC_MCO_DIV2: MCO clock source is divided by 2
+ * @arg RCC_MCO_DIV4: MCO clock source is divided by 4
+ * @arg RCC_MCO_DIV8: MCO clock source is divided by 8
+ * @arg RCC_MCO_DIV16: MCO clock source is divided by 16
+ * @arg RCC_MCO_DIV32: MCO clock source is divided by 32
+ * @arg RCC_MCO_DIV64: MCO clock source is divided by 64
+ * @arg RCC_MCO_DIV128: MCO clock source is divided by 128
+ */
+#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
+#else
+
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSource__: specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
+ * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
+ * @param __MCODiv__: specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO_NODIV: No division applied on MCO clock source
+ */
+#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ * @param __USART2CLKSource__: specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ * @param __USART3CLKSource__: specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
+
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
+
+#endif /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
+ * @{
+ */
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified CRS interrupts.
+ * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_CRS_IT_SYNCOK
+ * @arg RCC_CRS_IT_SYNCWARN
+ * @arg RCC_CRS_IT_ERR
+ * @arg RCC_CRS_IT_ESYNC
+ * @retval None
+ */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified CRS interrupts.
+ * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_CRS_IT_SYNCOK
+ * @arg RCC_CRS_IT_SYNCWARN
+ * @arg RCC_CRS_IT_ERR
+ * @arg RCC_CRS_IT_ESYNC
+ * @retval None
+ */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
+
+/** @brief Check the CRS's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the CRS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_CRS_IT_SYNCOK
+ * @arg RCC_CRS_IT_SYNCWARN
+ * @arg RCC_CRS_IT_ERR
+ * @arg RCC_CRS_IT_ESYNC
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
+
+/** @brief Clear the CRS's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_CRS_IT_SYNCOK
+ * @arg RCC_CRS_IT_SYNCWARN
+ * @arg RCC_CRS_IT_ERR
+ * @arg RCC_CRS_IT_ESYNC
+ * @arg RCC_CRS_IT_TRIMOVF
+ * @arg RCC_CRS_IT_SYNCERR
+ * @arg RCC_CRS_IT_SYNCMISS
+ */
+/* CRS IT Error Mask */
+#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
+ (CRS->ICR |= (__INTERRUPT__)))
+
+/**
+ * @brief Checks whether the specified CRS flag is set or not.
+ * @param _FLAG_: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_CRS_FLAG_SYNCOK
+ * @arg RCC_CRS_FLAG_SYNCWARN
+ * @arg RCC_CRS_FLAG_ERR
+ * @arg RCC_CRS_FLAG_ESYNC
+ * @arg RCC_CRS_FLAG_TRIMOVF
+ * @arg RCC_CRS_FLAG_SYNCERR
+ * @arg RCC_CRS_FLAG_SYNCMISS
+ * @retval The new state of _FLAG_ (TRUE or FALSE).
+ */
+#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
+
+/**
+ * @brief Clears the CRS specified FLAG.
+ * @param _FLAG_: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg RCC_CRS_FLAG_SYNCOK
+ * @arg RCC_CRS_FLAG_SYNCWARN
+ * @arg RCC_CRS_FLAG_ERR
+ * @arg RCC_CRS_FLAG_ESYNC
+ * @arg RCC_CRS_FLAG_TRIMOVF
+ * @arg RCC_CRS_FLAG_SYNCERR
+ * @arg RCC_CRS_FLAG_SYNCMISS
+ * @retval None
+ */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
+ (CRS->ICR |= (__FLAG__)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+ * @{
+ */
+/**
+ * @brief Enables the oscillator clock for frequency error counter.
+ * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
+
+/**
+ * @brief Disables the oscillator clock for frequency error counter.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
+
+/**
+ * @brief Enables the automatic hardware adjustement of TRIM bits.
+ * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
+ * @retval None
+ */
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+ * of the synchronization source after prescaling. It is then decreased by one in order to
+ * reach the expected synchronization on the zero value. The formula is the following:
+ * RELOAD = (fTARGET / fSYNC) -1
+ * @param _FTARGET_ Target frequency (value in Hz)
+ * @param _FSYNC_ Synchronization signal frequency (value in Hz)
+ * @retval None
+ */
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
new file mode 100644
index 000000000..2783c28b5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
@@ -0,0 +1,1385 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rtc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization
+ * + RTC Time and Date functions
+ * + RTC Alarm functions
+ * + Backup Data Registers configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RTC Operating Condition #####
+ ===============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC to operate even when the main digital supply (VDD)
+ is turned off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os (when available)
+
+ [..] When the backup domain is supplied by VDD (analog switch connected
+ to VDD), the following pins are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_OUT pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected
+ to VBAT because VDD is not present), the following pins are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_OUT pin
+
+ ##### Backup Domain Reset #####
+ ===============================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR
+ register to their reset values.
+ A backup domain reset is generated when one of the following events
+ occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
+
+ ##### Backup Domain Access #####
+ ===================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted write
+ accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (#) Enable the Power Controller (PWR) APB1 interface clock using the
+ __PWR_CLK_ENABLE() function.
+ (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+ (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+
+ ##### How to use this driver #####
+ ===================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ ##### RTC and low power modes #####
+ ===================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarm (Alarm A),
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC HAL module driver
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wake-up from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RTC peripheral
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ /* Check the RTC peripheral state */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief DeInitializes the RTC peripheral
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This function doesn't reset the RTC Backup Data registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Reset TR, DR and CR registers */
+ hrtc->Instance->TR = (uint32_t)0x00000000;
+ hrtc->Instance->DR = (uint32_t)0x00002101;
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= (uint32_t)0x00000000;
+ hrtc->Instance->PRER = (uint32_t)0x007F00FF;
+ hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
+ hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
+ hrtc->Instance->CALR = (uint32_t)0x00000000;
+ hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
+
+ /* Reset ISR register and exit initialization mode */
+ hrtc->Instance->ISR = (uint32_t)0x00000000;
+
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = 0x00000000;
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RTC MSP.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the RTC MSP.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provide functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets RTC current time.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << 16));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
+ ((uint32_t)(sTime->Minutes) << 8) | \
+ ((uint32_t)sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << 16));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TR register */
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Clear the bits to be configured */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets RTC current time.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get subseconds values from the correspondent registers*/
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+
+ /* Check the input parameters format */
+ if(Format == FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets RTC current date.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate: Pointer to date structure
+ * @param Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if(Format == FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << 13));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ datetmpreg = RTC_Bcd2ToByte(sDate->Month);
+ assert_param(IS_RTC_MONTH(datetmpreg));
+ datetmpreg = RTC_Bcd2ToByte(sDate->Date);
+ assert_param(IS_RTC_DATE(datetmpreg));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
+ (((uint32_t)sDate->Month) << 8) | \
+ ((uint32_t)sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DR register */
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY ;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets RTC current date.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate: Pointer to Date structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN : Binary data format
+ * @arg FORMAT_BCD : BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if(Format == FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Sets the specified RTC Alarm.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_ALARM(sAlarm->Alarm));
+ assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+
+ /* Configure the Alarm A Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the specified RTC Alarm with Interrupt
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_ALARM(sAlarm->Alarm));
+ assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ /* Configure the Alarm A Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
+
+ EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactive the specified RTC Alarm
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC Alarm value and masks.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Date structure
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_ALARM(Alarm));
+
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+
+ if(Format == FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Alarm interrupt request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+ {
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmA Polling request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wake-up from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Clear RSF flag */
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Returns the RTC state.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status:
+ * - HAL_OK : RTC is in Init mode
+ * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Check if the Initialization mode is set */
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value: Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0;
+
+ while(Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Converts from 2 digit BCD to Binary.
+ * @param Value: BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
new file mode 100644
index 000000000..277112e5f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
@@ -0,0 +1,785 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rtc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_RTC_H
+#define __STM32F0xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC RTC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief Time Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Mask_Definition RTC Mask Definition
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+
+#define RTC_TIMEOUT_VALUE 1000
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions RTC Time Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
+ * @{
+ */
+#define FORMAT_BIN ((uint32_t)0x000000000)
+#define FORMAT_BCD ((uint32_t)0x000000001)
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+
+#define IS_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value
+ * @{
+ */
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000)
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCA; \
+ (__HANDLE__)->Instance->WPR = 0x53; \
+ } while(0)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFF; \
+ } while(0)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRAWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+
+/**
+ * @brief Enable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/* alias define maintained for legacy */
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+/**
+ * @brief Disable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/* alias define maintained for legacy */
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+
+/**
+ * @brief Clear the RTC Exti flags.
+ * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+
+/* alias define maintained for legacy */
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extension module */
+#include "stm32f0xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @{
+ */
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @{
+ */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
new file mode 100644
index 000000000..4566192ad
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
@@ -0,0 +1,1577 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extension peripheral:
+ * + RTC TimeStamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
+ * + Extension Control functions
+ * + Extension RTC features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** RTC Wake-up configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wake-up timer in interrupt mode
+ using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ function.
+ (@) Not available on F030x6/x8/xC and F070x6/xB
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
+ mode using HAL_RTCEx_SetTamper_IT() function.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+ (@) Not available on F030x6/x8/xC and F070x6/xB
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTCEx RTCEx Extended HAL module driver
+ * @brief RTCEx Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg|= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets TimeStamp with Interrupt.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable IT timestamp */
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates TimeStamp.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmpreg = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC TimeStamp value.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTimeStamp: Pointer to Time structure
+ * @param sTimeStampDate: Pointer to Date structure
+ * @param Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if(Format == FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper: Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TAMPER(sTamper->Tamper));
+ assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets Tamper with interrupt.
+ * @note By calling this API we force the tamper interrupt for all tampers.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper: Pointer to RTC Tamper.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TAMPER(sTamper->Tamper));
+ assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Configure the tamper trigger */
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates Tamper.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Tamper: Selected tamper pin.
+ * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ assert_param(IS_TAMPER(Tamper));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the selected Tamper pin */
+ hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles TimeStamp interrupt request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+ {
+ /* TIMESTAMP callback */
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+
+ /* Clear the TIMESTAMP interrupt pending bit */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ }
+ }
+
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ }
+ }
+
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ }
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper3EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+ }
+ }
+#endif
+
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+ __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 2 callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ */
+}
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Tamper 3 callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ */
+}
+#endif
+
+/**
+ * @brief This function handles TimeStamp polling request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ {
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+ {
+ /* Clear the TIMESTAMP Overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Tamper1 Polling.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Tamper2 Polling.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+/**
+ * @brief This function handles Tamper3 Polling.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
+ * @brief RTC Wake-up functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets wake up timer.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* Configure the Wake-up Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets wake up timer with interrupt
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the Wake-up Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+ EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates wake up timer counter.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets wake up timer counter.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval Counter value
+ */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the counter value */
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+ * @brief This function handles Wake Up Timer interrupt request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+ {
+ /* Get the status of the Interrupt */
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
+ {
+ /* WAKEUPTIMER callback */
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Wake Up Timer callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles Wake Up Timer Polling.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the WAKEUPTIMER Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+
+/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
+ * @brief Extension Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
+ * specify the register.
+ * @param Data: Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
+ * specify the register.
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/**
+ * @brief Sets the Smooth calibration parameters.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmouthCalibMinusPulsesValue must be equal to 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS: Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibOutput : Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear flags before config */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the RTC reference clock detection.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the Bypass Shadow feature.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the Bypass Shadow feature.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
new file mode 100644
index 000000000..9bc612815
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
@@ -0,0 +1,708 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of RTC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_RTC_EX_H
+#define __STM32F0xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
+#endif
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#else
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA))
+#endif
+/**
+ * @}
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
+/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
+ * @{
+ */
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+/**
+ * @}
+ */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
+#endif
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \
+ ((TAMPER) == RTC_TAMPER_2) || \
+ ((TAMPER) == RTC_TAMPER_3))
+#else
+#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \
+ ((TAMPER) == RTC_TAMPER_2))
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+
+#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active level. */
+
+#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+
+#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definition
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+/**
+ * @}
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+
+#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definition
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definition
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+#endif
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* RTC Wake-up functions ******************************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Extension Control functions ************************************************/
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Extension RTC features functions *******************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
new file mode 100644
index 000000000..27cd92a6b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
@@ -0,0 +1,1431 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit ()API:
+ (++) Enable the USARTx interface clock.
+ (++) SMARTCARD pins configuration:
+ (+++) Enable the clock for the SMARTCARD GPIOs.
+ (+++) Configure these SMARTCARD pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD associated USART registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customed HAL_SMARTCARD_MspInit() API.
+
+ -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD HAL module driver
+ * @brief HAL SMARTCARD module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define TEACK_REACK_TIMEOUT 1000
+#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000
+#define SMARTCARD_TIMEOUT_VALUE 22000
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in Smartcard mode.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) For the Smartcard mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled,
+ Frame Length is fixed to 8 bits plus parity:
+ the USART frame format is given in the following table:
+ +---------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |---------------------|-----------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ or
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+
+ [..]
+ The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_InitTypeDef and creates the associated handle .
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SmartCard */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+ }
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN);
+ hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* set the USART in SMARTCARD mode */
+ hsmartcard->Instance->CR3 |= USART_CR3_SCEN;
+
+ /* Enable the Peripheral */
+ __HAL_SMARTCARD_ENABLE(hsmartcard);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->State to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+
+/**
+ * @brief DeInitializes the SMARTCARD peripheral
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ hsmartcard->Instance->CR1 = 0x0;
+ hsmartcard->Instance->CR2 = 0x0;
+ hsmartcard->Instance->CR3 = 0x0;
+ hsmartcard->Instance->RTOR = 0x0;
+ hsmartcard->Instance->GTPR = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->State = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMARTCARD MSP Init
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD MSP DeInit
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API s return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API s are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode API s with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+ while(hsmartcard->TxXferCount > 0)
+ {
+ hsmartcard->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Check if a non-blocking receive Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(hsmartcard->RxXferCount > 0)
+ {
+ hsmartcard->RxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ }
+
+ /* Check if a non-blocking transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Data Register not empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ hsmartcard->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode
+ * @param hsmartcard: SMARTCARD handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a transmit rocess is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ hsmartcard->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief SMARTCARD interrupt requests handling.
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD frame error interrupt occured --------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD noise error interrupt occured --------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD Over-Run interrupt occured -----------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occured -----------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsmartcard);
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD error callbacks
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SMARTCARD peripheral
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during
+ communication.
+
+ (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral
+ (+) SMARTCARD_AdvFeatureConfig() API optionally configures the SMARTCARD advanced features
+ (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the SMARTCARD state
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->State;
+}
+
+/**
+* @brief Return the SMARTCARD error code
+* @param hsmartcard : pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD.
+* @retval SMARTCARD Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @brief This function handles SMARTCARD Communication Timeout.
+ * @param hsmartcard: SMARTCARD handle
+ * @param Flag: specifies the SMARTCARD flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode
+ * @param hsmartcard: SMARTCARD handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ if(hsmartcard->TxXferCount == 0)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsmartcard: SMARTCARD handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0)
+ {
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg = 0x00000000;
+ SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONEBIT_SAMPLING(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+ /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLED))
+ {
+ tmpreg |= USART_CR1_RE;
+ }
+ tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Stop bits are forced to 1.5 (STOP = 11) */
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+ MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLED)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ __HAL_SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD state*/
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced feautures
+ * @param hsmartcard: SMARTCARD handle
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
new file mode 100644
index 000000000..b5d5746f0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
@@ -0,0 +1,818 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_SMARTCARD_H
+#define __STM32F0xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
+ Only 1.5 stop bits are authorized in SmartCard mode. */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note The parity is enabled by default (PCE is forced to 1).
+ Since the WordLength is forced to 8 bits + parity, M is
+ forced to 1 and the parity bit is the 9th bit. */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */
+
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */
+
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFF */
+
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief SMARTCARD advanced features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD clock sources
+ */
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code
+ This parameter can be a value of @ref SMARTCARD_Error */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Error SMARTCARD Error
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020) /*!< Receiver TimeOut error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
+#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000)
+#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL)
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000)
+#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA)
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLED ((uint16_t)0x0000)
+#define SMARTCARD_LASTBIT_ENABLED ((uint16_t)USART_CR2_LBCL)
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLED) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+ * @{
+ */
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint16_t)0x0000)
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint16_t)USART_CR3_ONEBIT)
+#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \
+ ((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED))
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLED ((uint16_t)0x0000)
+#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
+ ((NACK) == SMARTCARD_NACK_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+ * @{
+ */
+#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000)
+#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN)
+#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \
+ ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
+#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
+#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
+#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
+#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
+#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
+#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
+#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define SMARTCARD_IT_PE ((uint16_t)0x0028)
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
+#define SMARTCARD_IT_TC ((uint16_t)0x0626)
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
+
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
+#define SMARTCARD_IT_NE ((uint16_t)0x0200)
+#define SMARTCARD_IT_FE ((uint16_t)0x0100)
+
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+ * @{
+ */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+ * @{
+ */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+ * @{
+ */
+#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+ * @{
+ */
+#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK ((uint16_t)0x001F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle state
+ * @param __HANDLE__: SMARTCARD handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_REACK: Receive enable ackowledge flag
+ * @arg SMARTCARD_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg SMARTCARD_FLAG_BUSY: Busy flag
+ * @arg SMARTCARD_FLAG_EOBF: End of block flag
+ * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enables the specified SmartCard interrupt.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disables the specified SmartCard interrupt.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT__: specifies the SMARTCARD interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
+ * @arg SMARTCARD_IT_NE: Noise Error interrupt
+ * @arg SMARTCARD_IT_FE: Framing Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
+ * @arg SMARTCARD_IT_NE: Noise Error interrupt
+ * @arg SMARTCARD_IT_FE: Framing Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
+ * @arg USART_CLEAR_EOBF: End Of Block Clear Flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific SMARTCARD request flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the
+ * maximum clock on F0 (i.e. 48 MHz) divided by the oversampling used
+ * on the SMARTCARD (i.e. 16)
+ * @param __BAUDRATE__: Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+
+/** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__: block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
+
+/** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout
+ * value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__: receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
+
+/** @brief Check the SMARTCARD autoretry counter value. The maximum number of
+ * retransmissions is 0x7.
+ * @param __COUNT__: number of retransmissions
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
+
+/**
+ * @}
+ */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32f0xx_hal_smartcard_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
new file mode 100644
index 000000000..80fe71380
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
@@ -0,0 +1,197 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief SMARTCARD HAL module driver.
+ *
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization function
+ * + Peripheral Control function
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARD Extended HAL module driver
+ * @brief SMARTCARD Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the SMARTCARD block length in RTOR register
+ * @param hsmartcard: SMARTCARD handle
+ * @param BlockLength: SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register
+ * @param hsmartcard: SMARTCARD handle
+ * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+ * @brief Enable the SMARTCARD receiver timeout feature
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the SMARTCARD receiver timeout feature
+ * @param hsmartcard: SMARTCARD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
new file mode 100644
index 000000000..cc053004d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
@@ -0,0 +1,330 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smartcard_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_SMARTCARD_EX_H
+#define __STM32F0xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Extended_Exported_Macros SMARTCARDEx Exported Macros
+ * @{
+ */
+
+/** @brief Reports the SMARTCARD clock source.
+ * @param __HANDLE__: specifies the SMARTCARD Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F031x6) || defined(STM32F038xx)
+#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } while(0)
+#elif defined (STM32F030x8) || \
+ defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F051x8) || defined (STM32F058xx)
+#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F091xC) || defined(STM32F098xx)
+#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART7) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART8) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Peripheral State and Error functions ***************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
new file mode 100644
index 000000000..a3499df66
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
@@ -0,0 +1,1939 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smbus.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief SMBUS HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principales of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver :
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback
+ (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback
+ (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback
+ (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback
+ (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback
+ (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
+ to check the Error Code using function HAL_SMBUS_GetError()
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS HAL module driver
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
+#define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
+#define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
+#define MAX_NBYTE_SIZE 255
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macros SMBUS Private Macros
+ * @{
+ */
+#define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
+#define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and create the associated handle.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if(hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure SMBUSx: Frequency range */
+ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure SMBUSx: Bus Timeout */
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+ hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+ /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ if(hsmbus->Init.OwnAddress1 != 0)
+ {
+ if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
+ else /* SMBUS_ADDRESSINGMODE_10BIT */
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+ /* Configure SMBUSx: Addressing Master mode */
+ if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+ {
+ hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+ /* Configure SMBUSx: Generalcall and NoStretch mode */
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
+ if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED)
+ && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+ {
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+ }
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SMBUS peripheral.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if(hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMBUS MSP Init.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS MSP DeInit
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) No-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_DisableListen_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process commnunication with Interrupt
+ * @note : This abort can be called only if state is ready
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress: Target device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+ if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ {
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief This function enable the Address listen mode
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function disable the Address listen mode
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function enable the SMBUS alert mode.
+ * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief This function disable the SMBUS alert mode.
+ * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress: Target device address
+ * @param Trials: Number of trials
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t SMBUS_Trials = 0;
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (SMBUS_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+ }while(SMBUS_Trials < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles SMBUS event interrupt request.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t tmpisrvalue = 0;
+
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus);
+
+ /* SMBUS in mode Transmitter ---------------------------------------------------*/
+ if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Receiver ----------------------------------------------------*/
+ if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
+ if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+ && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ {
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ }
+}
+
+/**
+ * @brief This function handles SMBUS error interrupt request.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the the HAL state in case of ALERT error */
+ if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection: Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode: Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callbacks.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SMBUS state.
+ * @param hsmbus : SMBUS handle
+ * @retval HAL state
+ */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->State;
+}
+
+/**
+* @brief Return the SMBUS error code
+* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+* @retval SMBUS Error Code
+*/
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_SMBUS_RESET_CR2(hsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* REenable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ __HAL_SMBUS_RESET_CR2(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ {
+ if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ {
+ DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
+ {
+ /* Call TxCpltCallback if no stop mode is set */
+ if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ {
+ if(hsmbus->XferCount == 0)
+ {
+ /* Specific use case for Quick command */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback if no stop mode is set */
+ else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint8_t TransferDirection = 0;
+ uint16_t SlaveAddrCode = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that SMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hsmbus->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus);
+ SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus);
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call Slave Addr callback */
+ HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+ }
+ else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ {
+ if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+
+ if(hsmbus->XferCount == 1)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+ SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else if(hsmbus->XferCount == 0)
+ {
+ /* Last Byte is received, disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+ }
+ }
+ else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ {
+ if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Datas have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if(hsmbus->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
+ if(hsmbus->XferCount == 0)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+ }
+ }
+
+ /* Check if STOPF is set */
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable RX and TX Interrupts */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ __HAL_SMBUS_RESET_CR2(hsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ hsmbus->XferOptions = 0;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+ HAL_SMBUS_SlaveListenCpltCallback(hsmbus);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of SMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the disabling of Interrupts
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+ if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+ if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+ if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+/**
+ * @brief This function handles SMBUS Communication Timeout.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param Flag: specifies the SMBUS flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State= HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State= HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hsmbus: SMBUS handle.
+ * @param DevAddress: specifies the slave address to be programmed.
+ * @param Size: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode: new state of the SMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg SMBUS_NO_MODE: No specific mode enabled.
+ * @arg SMBUS_RELOAD_MODE: Enable Reload mode.
+ * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
+ * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
+ * @param Request: new state of the SMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
+ * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
+ * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
+ * @retval None
+ */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hsmbus->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hsmbus->Instance->CR2 = tmpreg;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
new file mode 100644
index 000000000..35fe420e3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
@@ -0,0 +1,617 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_smbus.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of SMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_SMBUS_H
+#define __STM32F0xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMBUS Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a a value of @ref SMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref SMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+} SMBUS_InitTypeDef;
+
+/**
+ * @brief SMBUS handle Structure definition
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state
+ This parameter can be a value of @ref SMBUS_State */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO uint32_t State; /*!< SMBUS communication state
+ This parameter can be a value of @ref SMBUS_State */
+
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code
+ This parameter can be a value of @ref SMBUS_Error */
+
+}SMBUS_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUS_Error SMBUS Error
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_State SMBUS State
+ * @{
+ */
+
+#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
+ /* Aliases for inter STM32 series compatibility */
+#define HAL_SMBUS_STATE_LISTEN HAL_SMBUS_STATE_SLAVE_LISTEN
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+ * @{
+ */
+#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
+#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+ * @{
+ */
+#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+ * @{
+ */
+
+#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
+#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+ * @{
+ */
+
+#define SMBUS_OA2_NOMASK ((uint8_t)0x00)
+#define SMBUS_OA2_MASK01 ((uint8_t)0x01)
+#define SMBUS_OA2_MASK02 ((uint8_t)0x02)
+#define SMBUS_OA2_MASK03 ((uint8_t)0x03)
+#define SMBUS_OA2_MASK04 ((uint8_t)0x04)
+#define SMBUS_OA2_MASK05 ((uint8_t)0x05)
+#define SMBUS_OA2_MASK06 ((uint8_t)0x06)
+#define SMBUS_OA2_MASK07 ((uint8_t)0x07)
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
+ ((MASK) == SMBUS_OA2_MASK01) || \
+ ((MASK) == SMBUS_OA2_MASK02) || \
+ ((MASK) == SMBUS_OA2_MASK03) || \
+ ((MASK) == SMBUS_OA2_MASK04) || \
+ ((MASK) == SMBUS_OA2_MASK05) || \
+ ((MASK) == SMBUS_OA2_MASK06) || \
+ ((MASK) == SMBUS_OA2_MASK07))
+/**
+ * @}
+ */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+ * @{
+ */
+#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
+#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+ * @{
+ */
+#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
+#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+ * @{
+ */
+#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
+#define SMBUS_PEC_ENABLED I2C_CR1_PECEN
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
+ ((PEC) == SMBUS_PEC_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+ * @{
+ */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
+#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
+#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
+#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
+
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+ * @{
+ */
+
+#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
+#define SMBUS_GENERATE_STOP I2C_CR2_STOP
+#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+ * @{
+ */
+
+#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
+#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+ * @brief SMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SMBUS_IT_ERRI I2C_CR1_ERRIE
+#define SMBUS_IT_TCI I2C_CR1_TCIE
+#define SMBUS_IT_STOPI I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI I2C_CR1_RXIE
+#define SMBUS_IT_TXI I2C_CR1_TXIE
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define SMBUS_FLAG_TXE I2C_ISR_TXE
+#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
+#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
+#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
+#define SMBUS_FLAG_AF I2C_ISR_NACKF
+#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
+#define SMBUS_FLAG_TC I2C_ISR_TC
+#define SMBUS_FLAG_TCR I2C_ISR_TCR
+#define SMBUS_FLAG_BERR I2C_ISR_BERR
+#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
+#define SMBUS_FLAG_OVR I2C_ISR_OVR
+#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
+#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
+#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
+#define SMBUS_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMBUS handle state
+ * @param __HANDLE__: SMBUS handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief Enable or disable the specified SMBUS interrupts.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_IT_ERRI: Errors interrupt enable
+ * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
+ * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
+ * @arg SMBUS_IT_NACKI: NACK received interrupt enable
+ * @arg SMBUS_IT_ADDRI: Address match interrupt enable
+ * @arg SMBUS_IT_RXI: RX interrupt enable
+ * @arg SMBUS_IT_TXI: TX interrupt enable
+ *
+ * @retval None
+ */
+
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
+ * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_IT_ERRI: Errors interrupt enable
+ * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
+ * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
+ * @arg SMBUS_IT_NACKI: NACK received interrupt enable
+ * @arg SMBUS_IT_ADDRI: Address match interrupt enable
+ * @arg SMBUS_IT_RXI: RX interrupt enable
+ * @arg SMBUS_IT_TXI: TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SMBUS flag is set or not.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_FLAG_TXE: Transmit data register empty
+ * @arg SMBUS_FLAG_TXIS: Transmit interrupt status
+ * @arg SMBUS_FLAG_RXNE: Receive data register not empty
+ * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
+ * @arg SMBUS_FLAG_AF: NACK received flag
+ * @arg SMBUS_FLAG_STOPF: STOP detection flag
+ * @arg SMBUS_FLAG_TC: Transfer complete (master mode)
+ * @arg SMBUS_FLAG_TCR: Transfer complete reload
+ * @arg SMBUS_FLAG_BERR: Bus error
+ * @arg SMBUS_FLAG_ARLO: Arbitration lost
+ * @arg SMBUS_FLAG_OVR: Overrun/Underrun
+ * @arg SMBUS_FLAG_PECERR: PEC error in reception
+ * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg SMBUS_FLAG_ALERT: SMBus alert
+ * @arg SMBUS_FLAG_BUSY: Bus busy
+ * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
+ * @arg SMBUS_FLAG_AF: NACK received flag
+ * @arg SMBUS_FLAG_STOPF: STOP detection flag
+ * @arg SMBUS_FLAG_BERR: Bus error
+ * @arg SMBUS_FLAG_ARLO: Arbitration lost
+ * @arg SMBUS_FLAG_OVR: Overrun/Underrun
+ * @arg SMBUS_FLAG_PECERR: PEC error in reception
+ * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg SMBUS_FLAG_ALERT: SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+
+#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
+#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+
+/* Aliases for new API and to insure inter STM32 series compatibility */
+#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT
+
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/* Aliases for new API and to insure inter STM32 series compatibility */
+#define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback
+#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback
+
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
new file mode 100644
index 000000000..6633ea8aa
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
@@ -0,0 +1,2722 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_spi.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SPI peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_SPI_MspInit(&hspi) API.
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits:
+ +-----------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |--------------------|--------------------|--------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |=========================================================================================|
+ | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
+ | R |----------------|----------|---------|----------|---------|----------|---------|
+ | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA |
+ |=========|================|==========|=========|==========|=========|==========|=========|
+ | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
+ | |----------------|----------|---------|----------|---------|----------|---------|
+ | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 |
+ |=========|================|==========|=========|==========|=========|==========|=========|
+ | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
+ | |----------------|----------|---------|----------|---------|----------|---------|
+ | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 |
+ +-----------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI HAL module driver
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 50
+#define SPI_FIFO_SIZE 4
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the SPIx peripheral:
+
+ (+) User must Implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and create the associated handle.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t frxth;
+
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Align by default the rs fifo threshold on the data size */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_HF;
+ }
+ else
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_QF;
+ }
+
+ /* CRC calculation is valid only for 16Bit and 8 Bit */
+ if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+ {
+ /* CRC must be disabled */
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ }
+
+ /* Align the CRC Length on the data size */
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Lengtht aligned on the data size : value set by default */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit, CRC calculation state, CRC Length */
+ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
+
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCL;
+ }
+
+ /* Configure : NSS management */
+ /* Configure : Rx Fifo Threshold */
+ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
+ hspi->Init.DataSize ) | frxth;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Configure : CRC Polynomial */
+ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State= HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SPI peripheral
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* check flag before the SPI disable */
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
+ SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SPI MSP Init
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief SPI MSP DeInit
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 I/O operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_TransmitReceive() in full duplex mode
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
+ (++) HAL_SPI_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
+ (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_SPI_TxCpltCallback()
+ (++) HAL_SPI_RxCpltCallback()
+ (++) HAL_SPI_ErrorCallback()
+ (++) HAL_SPI_TxRxCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ while (hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ {
+ if(hspi->TxXferCount > 1)
+ {
+ /* write on the data register in packaing mode */
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ else
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ }
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ __IO uint16_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this case we call the transmitReceive process */
+ /* Process Locked */
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+
+ /* Set the Rx Fido thresold */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthresold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Configure communication direction 1Line and enabled SPI if needed */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ /* Transfert loop */
+ while(hspi->RxXferCount > 0)
+ {
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ {
+ /* read the received data */
+ (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout manamgement */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Transfert loop */
+ while(hspi->RxXferCount > 0)
+ {
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout mamangement */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+ /* Handle the CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* freeze the CRC before the latest data */
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+
+ /* Read the latest data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Flag Error*/
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer to be
+ * @param Size : amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+__IO uint16_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+ assert_param(pTxData != NULL);
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the Rx Fido threshold */
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ {
+ /* set fiforxthreshold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthreshold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+ {
+ /* Check TXE flag */
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ }
+ }
+
+ /* Check RXNE flag */
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+ {
+ /* check TXE flag */
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ {
+ if(hspi->TxXferCount > 1)
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ }
+
+ /* Wait until RXNE flag is reset */
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ {
+ if(hspi->RxXferCount > 1)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2;
+ if(hspi->RxXferCount <= 1)
+ {
+ /* set fiforxthresold before to switch on 8 bit data size */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ else
+ {
+ (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+
+ /* Read CRC from DR to close CRC calculation process */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+ errorcode = HAL_ERROR;
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in no-blocking mode with Interrupt
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* prepore the transfer */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+ hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL;
+
+ /* Set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this we call the transmitReceive process */
+ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
+ }
+
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2;
+ }
+ }
+ else
+ {
+ hspi->CRCSize = 0;
+ }
+
+ hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL;
+ /* check the data size to adapt Rx threshold and the set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ /* set fiforxthresold according the reception data lenght: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer to be
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->CRCSize = 0;
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2;
+ }
+ }
+
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatement */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* check if packing mode is enabled and if there is more than 2 data to receive */
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+ {
+ /* set fiforxthresold according the reception data lenght: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in no-blocking mode with DMA
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfert complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ /* packing mode is enabled only if the DMA setting is HALWORD */
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Check the even/odd of the data size + crc if enabled */
+ if((hspi->TxXferCount & 0x1) == 0)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1);
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ }
+ }
+
+ /* Enable the Tx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with DMA
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this case we call the transmitReceive process */
+ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ __HAL_SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* packing mode management is enabled by the DMA settings */
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthresold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfert complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Enable the Rx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData : pointer to transmission data buffer
+ * @param pRxData : pointer to reception data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) ||
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* check if the transmit Receive function is not called by a receive master */
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Reset CRC Calculation + increase the rxsize */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* the packing mode management is enabled by the DMA settings according the spi data size */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthreshold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ if((hspi->TxXferSize & 0x1) == 0x0)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ }
+ }
+
+ if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* set fiforxthresold according the reception data lenght: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if((hspi->RxXferCount & 0x1) == 0x0 )
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+ }
+ }
+ }
+
+ /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
+ reception request (RXNE) */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Enable the Rx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable the Tx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPI interrupt request.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None.
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Tramitter ---------------------------------------------------*/
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Erreur Treatment ---------------------------------------------------*/
+ if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ {
+ /* SPI Overrun error interrupt occured -------------------------------------*/
+ if((itflag & SPI_FLAG_OVR) != RESET)
+ {
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occured -------------------------------------*/
+ if((itflag & SPI_FLAG_MODF) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occured ----------------------------------------*/
+ if((itflag & SPI_FLAG_FRE) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+}
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0;
+ while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if(count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ };
+ return HAL_OK;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief SPI error callbacks
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI state
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI Error Code
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions SPI Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO uint16_t tmpreg;
+
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Check the end of the transaction */
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO int16_t tmpreg;
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Erreur on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Half transmit receive process complete callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None.
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief Rx Handler for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in packing mode */
+ if(hspi->RxXferCount > 1)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2;
+ if(hspi->RxXferCount == 1)
+ {
+ /* set fiforxthresold according the reception data lenght: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+ }
+
+ /* check end of the reception */
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx Handler for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ UNUSED(tmpreg);
+ hspi->CRCSize--;
+
+ /* check end of the reception */
+ if(hspi->CRCSize == 0)
+ {
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Tx Handler for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in packing Bit mode */
+ if(hspi->TxXferCount >= 2)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ /* check the end of the transmission */
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ __IO uint16_t tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+
+/**
+ * @brief Tx Handler for Transmit and Receive in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Manage the CRC receive in Interrupt context
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
+ UNUSED(tmpreg);
+ hspi->CRCSize--;
+
+ if(hspi->CRCSize == 0)
+ {
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Manage the recieve in Interrupt context
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Manage the CRC 16bit recieve in Interrupt context
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg;
+
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+
+/**
+ * @brief Manage the 16Bit recieve in Interrupt context
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8Bit transmit in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* Enable CRC Transmission */
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16Bit transmit in Interrupt mode
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ /* Enable CRC Transmission */
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief This function handles SPI Communication Timeout.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag : SPI flag to check
+ * @param State : flag state to check
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while((hspi->Instance->SR & Flag) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPI Communication Timeout.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo : Fifo to check
+ * @param State : Fifo state to check
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
+{
+ __IO uint8_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+
+ while((hspi->Instance->SR & Fifo) != State)
+ {
+ if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ UNUSED(tmpreg);
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ __HAL_SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles the check of the RX transaction complete.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout : Timeout duration
+ * @retval None.
+ */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+{
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles the close of the RXTX transaction.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief This function handles the close of the RX transaction.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief This function handles the close of the TX transaction.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None.
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
new file mode 100644
index 000000000..b9ecd1716
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
@@ -0,0 +1,677 @@
+ /**
+ ******************************************************************************
+ * @file stm32f0xx_hal_spi.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_SPI_H
+#define __STM32F0xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ CRC Length is only used with Data8 and Data16, not other data size
+ This parameter must 0 or 1 or 2*/
+
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and
+ it takes effect only if the SPI interface is configured as Motorola SPI
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+ CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
+}HAL_SPI_StateTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code
+ This parameter can be a value of @ref SPI_Error */
+
+}SPI_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error SPI Error
+ * @{
+ */
+ #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+ #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
+ #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
+ #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
+ #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
+ #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+ #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+ #define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /*!< Unknow Error error */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode SPI mode
+ * @{
+ */
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction
+ * @{
+ */
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size SPI Data size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS pulse management
+ * @{
+ */
+#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLED SPI_CR2_FRF
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
+ ((MODE) == SPI_TIMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC length
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit
+ */
+#define SPI_CRC_LENGTH_DATASIZE 0
+#define SPI_CRC_LENGTH_8BIT 1
+#define SPI_CRC_LENGTH_16BIT 2
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+ * RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2(16-bits).
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+ * @brief SPI Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Flag_definition SPI Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXX : Flag register Index
+ * - YYYY : Flag mask
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
+ * @{
+ */
+#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
+#define SPI_FTLVL_FULL ((uint32_t)0x1800)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
+ * @{
+ */
+#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state
+ * @param __HANDLE__: SPI handle.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enables or disables the specified SPI interrupts.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SPI flag is set or not.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__ : specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the SPI CRCERR pending flag.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief Clears the SPI MODF pending flag.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = (__HANDLE__)->Instance->SR;\
+ UNUSED(tmpreg); \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\
+ }while(0)
+
+/** @brief Clears the SPI OVR pending flag.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clears the SPI FRE pending flag.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0)
+/** @brief Enables the SPI.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+
+/** @brief Disables the SPI.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+
+/** @brief Sets the SPI transmit-only mode.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief Sets the SPI receive-only mode.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief Resets the CRC calculation of the SPI.
+ * @param __HANDLE__ : specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
new file mode 100644
index 000000000..a6284fd92
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
@@ -0,0 +1,5305 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tim.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM HAL module driver
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions TIM_Private_Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM OC handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM OPWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The destination Buffer address.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM OnePulse handle
+ * @param OnePulseMode : Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim : TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @param htim : TIM Encoder Interface handle
+ * @param sConfig : TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+
+ /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim : TIM Encoder handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param pData1 : The destination Buffer address for IC1.
+ * @param pData2 : The destination Buffer address for IC2.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim : TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM Output Compare handle
+ * @param sConfig : TIM Output Compare configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim : TIM IC handle
+ * @param sConfig : TIM Input Capture configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM handle
+ * @param sConfig : TIM PWM configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim : TIM One Pulse handle
+ * @param sConfig : TIM One Pulse configuration structure
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if(OutputChannel != InputChannel)
+ {
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Ouput compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ default:
+ break;
+ }
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim : TIM handle
+ * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR1
+ * @arg TIM_DMABase_CR2
+ * @arg TIM_DMABase_SMCR
+ * @arg TIM_DMABase_DIER
+ * @arg TIM_DMABase_SR
+ * @arg TIM_DMABase_EGR
+ * @arg TIM_DMABase_CCMR1
+ * @arg TIM_DMABase_CCMR2
+ * @arg TIM_DMABase_CCER
+ * @arg TIM_DMABase_CNT
+ * @arg TIM_DMABase_PSC
+ * @arg TIM_DMABase_ARR
+ * @arg TIM_DMABase_RCR
+ * @arg TIM_DMABase_CCR1
+ * @arg TIM_DMABase_CCR2
+ * @arg TIM_DMABase_CCR3
+ * @arg TIM_DMABase_CCR4
+ * @arg TIM_DMABase_BDTR
+ * @arg TIM_DMABase_DCR
+ * @param BurstRequestSrc : TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer : The Buffer address.
+ * @param BurstLength : DMA Burst length. This parameter can be one value
+ * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim : TIM handle
+ * @param BurstRequestSrc : TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim : TIM handle
+ * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR1
+ * @arg TIM_DMABase_CR2
+ * @arg TIM_DMABase_SMCR
+ * @arg TIM_DMABase_DIER
+ * @arg TIM_DMABase_SR
+ * @arg TIM_DMABase_EGR
+ * @arg TIM_DMABase_CCMR1
+ * @arg TIM_DMABase_CCMR2
+ * @arg TIM_DMABase_CCER
+ * @arg TIM_DMABase_CNT
+ * @arg TIM_DMABase_PSC
+ * @arg TIM_DMABase_ARR
+ * @arg TIM_DMABase_RCR
+ * @arg TIM_DMABase_CCR1
+ * @arg TIM_DMABase_CCR2
+ * @arg TIM_DMABase_CCR3
+ * @arg TIM_DMABase_CCR4
+ * @arg TIM_DMABase_BDTR
+ * @arg TIM_DMABase_DCR
+ * @param BurstRequestSrc : TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer : The Buffer address.
+ * @param BurstLength : DMA Burst length. This parameter can be one value
+ * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim : TIM handle
+ * @param BurstRequestSrc : TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim : TIM handle
+ * @param EventSource : specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim : TIM handle
+ * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit */
+ tmpsmcr &= ~TIM_SMCR_OCCS;
+
+ /* Clear the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set TIMx_SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim : TIM handle
+ * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ /* Reset the SMS and TS Bits */
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR0:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim : TIM handle.
+ * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim : TIM handle.
+ * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim : TIM handle.
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+
+}
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim : TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim : TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim : TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim : TIM Ouput Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim : TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim : TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim : TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim : TIM Encoder handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx : TIM periheral
+ * @param Structure : TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Time Ouput Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @arg TIM_ICPolarity_BothEdge
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource : The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0 : Internal Trigger 0
+ * @arg TIM_TS_ITR1 : Internal Trigger 1
+ * @arg TIM_TS_ITR2 : Internal Trigger 2
+ * @arg TIM_TS_ITR3 : Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
+ * @arg TIM_TS_ETRF : External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
+ * @param ExtTRGFilter : External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr = 0;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1 : TIM Channel 1
+ * @arg TIM_Channel_2 : TIM Channel 2
+ * @arg TIM_Channel_3 : TIM Channel 3
+ * @arg TIM_Channel_4 : TIM Channel 4
+ * @param ChannelState : specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h
new file mode 100644
index 000000000..405d26d60
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h
@@ -0,0 +1,1645 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tim.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_TIM_H
+#define __STM32F0xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a value of @ref TIM_Clock_Filter */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a value of @ref TIM_ClearInput_Filter */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a value of @ref TIM_Trigger_Filter */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref TIM_DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+/**
+ * @}
+ */
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_COMMUTATION TIM Commutation
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+
+/**
+ * @}
+ */
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EventSource_Update TIM_EGR_UG
+#define TIM_EventSource_CC1 TIM_EGR_CC1G
+#define TIM_EventSource_CC2 TIM_EGR_CC2G
+#define TIM_EventSource_CC3 TIM_EGR_CC3G
+#define TIM_EventSource_CC4 TIM_EGR_CC4G
+#define TIM_EventSource_COM TIM_EGR_COMG
+#define TIM_EventSource_Trigger TIM_EGR_TG
+#define TIM_EventSource_Break TIM_EGR_BG
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+
+#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_TRIGGER) || \
+ ((FLAG) == TIM_FLAG_BREAK) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+/**
+ * @}
+ */
+/** @defgroup TIM_Clock_Filter TIM Clock Filter
+ * @{
+ */
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
+ * @{
+ */
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level TIM Lock Configuration
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+/**
+ * @}
+ */
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+/**
+ * @}
+ */
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave Mode
+ * @{
+ */
+
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
+#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+ * @{
+ */
+
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
+#define TIM_TS_ETRF ((uint32_t)0x0070)
+#define TIM_TS_NONE ((uint32_t)0xFFFF)
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
+ * @{
+ */
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+ * @{
+ */
+#define TIM_DMABase_CR1 (0x00000000)
+#define TIM_DMABase_CR2 (0x00000001)
+#define TIM_DMABase_SMCR (0x00000002)
+#define TIM_DMABase_DIER (0x00000003)
+#define TIM_DMABase_SR (0x00000004)
+#define TIM_DMABase_EGR (0x00000005)
+#define TIM_DMABase_CCMR1 (0x00000006)
+#define TIM_DMABase_CCMR2 (0x00000007)
+#define TIM_DMABase_CCER (0x00000008)
+#define TIM_DMABase_CNT (0x00000009)
+#define TIM_DMABase_PSC (0x0000000A)
+#define TIM_DMABase_ARR (0x0000000B)
+#define TIM_DMABase_RCR (0x0000000C)
+#define TIM_DMABase_CCR1 (0x0000000D)
+#define TIM_DMABase_CCR2 (0x0000000E)
+#define TIM_DMABase_CCR3 (0x0000000F)
+#define TIM_DMABase_CCR4 (0x00000010)
+#define TIM_DMABase_BDTR (0x00000011)
+#define TIM_DMABase_DCR (0x00000012)
+#define TIM_DMABase_OR (0x00000013)
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer (0x00000000)
+#define TIM_DMABurstLength_2Transfers (0x00000100)
+#define TIM_DMABurstLength_3Transfers (0x00000200)
+#define TIM_DMABurstLength_4Transfers (0x00000300)
+#define TIM_DMABurstLength_5Transfers (0x00000400)
+#define TIM_DMABurstLength_6Transfers (0x00000500)
+#define TIM_DMABurstLength_7Transfers (0x00000600)
+#define TIM_DMABurstLength_8Transfers (0x00000700)
+#define TIM_DMABurstLength_9Transfers (0x00000800)
+#define TIM_DMABurstLength_10Transfers (0x00000900)
+#define TIM_DMABurstLength_11Transfers (0x00000A00)
+#define TIM_DMABurstLength_12Transfers (0x00000B00)
+#define TIM_DMABurstLength_13Transfers (0x00000C00)
+#define TIM_DMABurstLength_14Transfers (0x00000D00)
+#define TIM_DMABurstLength_15Transfers (0x00000E00)
+#define TIM_DMABurstLength_16Transfers (0x00000F00)
+#define TIM_DMABurstLength_17Transfers (0x00001000)
+#define TIM_DMABurstLength_18Transfers (0x00001100)
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __COUNTER__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetCounter(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetAutoreload(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CKD__: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1
+ * @arg TIM_CLOCKDIVISION_DIV2
+ * @arg TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetClockDivision(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
+ __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * (+) Counter overflow/underflow
+ * (+) Setting the UG bit
+ * (+) Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @}
+ */
+
+/* Include TIM HAL Extension module */
+#include "stm32f0xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ * @{
+ */
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ * @{
+ */
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @brief TIM Callbacks functions
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+
+/* Private Functions --------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c
new file mode 100644
index 000000000..e8d8543f6
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c
@@ -0,0 +1,1835 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal bread and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Timer remapping capabilities configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx Extended HAL module driver
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
+ * @param htim : TIM Encoder Interface handle
+ * @param sConfig : TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim : TIM Hall Sensor handle
+ * @param pData : The destination Buffer address.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Enable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim : TIM OC handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+{
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * output.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation Interrupt Request */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim : TIM handle.
+ * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the MMS Bits */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+ /* Set or Reset the MSM Bit */
+ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim : TIM handle
+ * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
+ sBreakDeadTimeConfig->OffStateIDLEMode |
+ sBreakDeadTimeConfig->LockLevel |
+ sBreakDeadTimeConfig->DeadTime |
+ sBreakDeadTimeConfig->BreakState |
+ sBreakDeadTimeConfig->BreakPolarity |
+ sBreakDeadTimeConfig->AutomaticOutput;
+
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM14 Remapping input capabilities.
+ * @param htim : TIM handle.
+ * @param Remap : specifies the TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
+ * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
+ * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
+ * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extension Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extension TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIMEx_CommutationCallback(htim);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
+ * @brief Extension Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface state
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp = 0;
+
+ tmp = TIM_CCER_CC1NE << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h
new file mode 100644
index 000000000..f7f974df5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h
@@ -0,0 +1,293 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_TIM_EX_H
+#define __STM32F0xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIMEx Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIMEx Remap
+ * @{
+ */
+
+#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
+#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
+#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
+#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\
+ ((TIM_REMAP) == TIM_TIM14_RTC) ||\
+ ((TIM_REMAP) == TIM_TIM14_HSE) ||\
+ ((TIM_REMAP) == TIM_TIM14_MCO))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Filter TIM Clock Filter
+ * @{
+ */
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extended Callbacks functions
+ * @{
+ */
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
+ * @brief Extended Peripheral State functions
+ * @{
+ */
+/* Extension Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F0xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c
new file mode 100644
index 000000000..589d6de1b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c
@@ -0,0 +1,791 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tsc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Touch Sensing Controller (TSC) peripheral:
+ * + Initialization and DeInitialization
+ * + Channel IOs, Shield IOs and Sampling IOs configuration
+ * + Start and Stop an acquisition
+ * + Read acquisition result
+ * + Interrupts and flags management
+ *
+ @verbatim
+================================================================================
+ ##### TSC specific features #####
+================================================================================
+ [..]
+ (#) Proven and robust surface charge transfer acquisition principle
+
+ (#) Supports up to 3 capacitive sensing channels per group
+
+ (#) Capacitive sensing channels can be acquired in parallel offering a very good
+ response time
+
+ (#) Spread spectrum feature to improve system robustness in noisy environments
+
+ (#) Full hardware management of the charge transfer acquisition sequence
+
+ (#) Programmable charge transfer frequency
+
+ (#) Programmable sampling capacitor I/O pin
+
+ (#) Programmable channel I/O pin
+
+ (#) Programmable max count value to avoid long acquisition when a channel is faulty
+
+ (#) Dedicated end of acquisition and max count error flags with interrupt capability
+
+ (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+ components
+
+ (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro.
+
+ (#) GPIO pins configuration
+ (++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro.
+ (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+ and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+ using HAL_GPIO_Init() function.
+ (++) Configure the alternate function on all the TSC pins using HAL_xxxx() function.
+
+ (#) Interrupts configuration
+ (++) Configure the NVIC (if the interrupt model is used) using HAL_xxx() function.
+
+ (#) TSC configuration
+ (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+ *** Acquisition sequence ***
+ ===================================
+ [..]
+ (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+ (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+ of the sampling capacitor and electrodes design.
+ (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+ (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+ If the synchronized mode is selected, the acquisition will start as soon as the signal
+ is received on the synchro pin.
+ (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+ HAL_TSC_GetState() function or using WFI instruction for example.
+ (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+ (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+#ifdef HAL_TSC_MODULE_ENABLED
+
+#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
+ defined(STM32F042x6) || defined(STM32F072xB) || \
+ defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TSC TSC HAL module driver
+ * @brief TSC HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t TSC_extract_groups(uint32_t iomask);
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Functions TSC Exported Functions
+ * @{
+ */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the TSC.
+ (+) De-initialize the TSC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TSC peripheral according to the specified parameters
+ * in the TSC_InitTypeDef structure.
+ * @param htsc: TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+ assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+ assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+ assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+ assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+ assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+ assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+ assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+ assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+ assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_TSC_MspInit(htsc);
+
+ /*--------------------------------------------------------------------------*/
+ /* Set TSC parameters */
+
+ /* Enable TSC */
+ htsc->Instance->CR = TSC_CR_TSCE;
+
+ /* Set all functions */
+ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+ htsc->Init.CTPulseLowLength |
+ (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
+ htsc->Init.SpreadSpectrumPrescaler |
+ htsc->Init.PulseGeneratorPrescaler |
+ htsc->Init.MaxCountValue |
+ htsc->Init.IODefaultMode |
+ htsc->Init.SynchroPinPolarity |
+ htsc->Init.AcquisitionMode);
+
+ /* Spread spectrum */
+ if (htsc->Init.SpreadSpectrum == ENABLE)
+ {
+ htsc->Instance->CR |= TSC_CR_SSE;
+ }
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+
+ /* Set the groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+
+ /* Clear interrupts */
+ htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+ /*--------------------------------------------------------------------------*/
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the TSC peripheral registers to their default reset values.
+ * @param htsc: TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_TSC_MspDeInit(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TSC MSP.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the TSC MSP.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start acquisition in polling mode.
+ (+) Start acquisition in interrupt mode.
+ (+) Stop conversion in polling mode.
+ (+) Stop conversion in interrupt mode.
+ (+) Get group acquisition status.
+ (+) Get group acquisition value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the acquisition.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Clear interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Stop discharging the IOs */
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the interrupt and starts the acquisition
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Enable end of acquisition interrupt */
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+ /* Enable max count error interrupt (optional) */
+ if (htsc->Init.MaxCountInterrupt == ENABLE)
+ {
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+ }
+ else
+ {
+ __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+ }
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Stop discharging the IOs */
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the acquisition previously launched in polling mode
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the acquisition previously launched in interrupt mode
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the acquisition status for a group
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index: Index of the group
+ * @retval Group status
+ */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_GROUP_INDEX(gx_index));
+
+ /* Return the group status */
+ return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+ * @brief Gets the acquisition measure for a group
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index: Index of the group
+ * @retval Acquisition measure
+ */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_GROUP_INDEX(gx_index));
+
+ /* Return the group acquisition counter */
+ return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure TSC IOs
+ (+) Discharge TSC IOs
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures TSC IOs
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param config: pointer to the configuration structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = config->SamplingIOs;
+
+ /* Set groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Discharge TSC IOs
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param choice: enable or disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (choice == ENABLE)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return the group acquisition counter */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group4 State functions
+ * @brief State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get TSC state.
+ (+) Poll for acquisition completed.
+ (+) Handles TSC interrupt request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TSC state
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ if (htsc->State == HAL_TSC_STATE_BUSY)
+ {
+ /* Check end of acquisition flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Check max count error flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ }
+ }
+ }
+
+ /* Return TSC state */
+ return htsc->State;
+}
+
+/**
+ * @brief Start acquisition and wait until completion
+ * @note There is no need of a timeout parameter as the max count error is already
+ * managed by the TSC peripheral.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Check end of acquisition */
+ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+ {
+ /* The timeout (max count error) is managed by the TSC peripheral itself. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles TSC interrupt request
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Check if the end of acquisition occured */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Clear EOA flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+ }
+
+ /* Check if max count error occured */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Clear MCE flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ /* Conversion completed callback */
+ HAL_TSC_ErrorCallback(htsc);
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ /* Conversion completed callback */
+ HAL_TSC_ConvCpltCallback(htsc);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+
+/**
+ * @brief Acquisition completed callback in non blocking mode
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback in non blocking mode
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Private_Functions TSC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Utility function used to set the acquired groups mask
+ * @param iomask: Channels IOs mask
+ * @retval Acquired groups mask
+ */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+ uint32_t groups = 0;
+ uint32_t idx;
+
+ for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
+ {
+ if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
+ {
+ groups |= ((uint32_t)1 << idx);
+ }
+ }
+
+ return groups;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
+ /* defined(STM32F042x6) || defined(STM32F072xB) || */
+ /* defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
+
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h
new file mode 100644
index 000000000..da76cf0eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h
@@ -0,0 +1,724 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_tsc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief This file contains all the functions prototypes for the TSC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_TSC_H
+#define __STM32F0xx_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
+ defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Types TSC Exported Types
+ * @{
+ */
+/**
+ * @brief TSC state structure definition
+ */
+typedef enum
+{
+ HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/**
+ * @brief TSC group status structure definition
+ */
+typedef enum
+{
+ TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/**
+ * @brief TSC init structure definition
+ */
+typedef struct
+{
+ uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
+ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
+ uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
+ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
+ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
+ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
+ uint32_t MaxCountValue; /*!< Max count value */
+ uint32_t IODefaultMode; /*!< IO default mode */
+ uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
+ uint32_t AcquisitionMode; /*!< Acquisition mode */
+ uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/**
+ * @brief TSC IOs configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/**
+ * @brief TSC handle Structure definition
+ */
+typedef struct
+{
+ TSC_TypeDef *Instance; /*!< Register base address */
+ TSC_InitTypeDef Init; /*!< Initialization parameters */
+ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
+ HAL_LockTypeDef Lock; /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+ * @{
+ */
+
+/** @defgroup TSC_CTPH_Cycles TSC Charge Transfer Pulse High
+ * @{
+ */
+#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
+#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
+#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
+#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
+#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
+#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
+#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
+#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
+#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
+#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
+#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
+#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
+#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
+#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
+#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
+#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+ ((VAL) == TSC_CTPH_2CYCLES) || \
+ ((VAL) == TSC_CTPH_3CYCLES) || \
+ ((VAL) == TSC_CTPH_4CYCLES) || \
+ ((VAL) == TSC_CTPH_5CYCLES) || \
+ ((VAL) == TSC_CTPH_6CYCLES) || \
+ ((VAL) == TSC_CTPH_7CYCLES) || \
+ ((VAL) == TSC_CTPH_8CYCLES) || \
+ ((VAL) == TSC_CTPH_9CYCLES) || \
+ ((VAL) == TSC_CTPH_10CYCLES) || \
+ ((VAL) == TSC_CTPH_11CYCLES) || \
+ ((VAL) == TSC_CTPH_12CYCLES) || \
+ ((VAL) == TSC_CTPH_13CYCLES) || \
+ ((VAL) == TSC_CTPH_14CYCLES) || \
+ ((VAL) == TSC_CTPH_15CYCLES) || \
+ ((VAL) == TSC_CTPH_16CYCLES))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_CTPL_Cycles TSC Charge Transfer Pulse Low
+ * @{
+ */
+#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
+#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
+#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
+#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
+#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
+#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
+#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
+#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
+#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
+#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
+#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
+#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
+#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
+#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
+#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
+#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+ ((VAL) == TSC_CTPL_2CYCLES) || \
+ ((VAL) == TSC_CTPL_3CYCLES) || \
+ ((VAL) == TSC_CTPL_4CYCLES) || \
+ ((VAL) == TSC_CTPL_5CYCLES) || \
+ ((VAL) == TSC_CTPL_6CYCLES) || \
+ ((VAL) == TSC_CTPL_7CYCLES) || \
+ ((VAL) == TSC_CTPL_8CYCLES) || \
+ ((VAL) == TSC_CTPL_9CYCLES) || \
+ ((VAL) == TSC_CTPL_10CYCLES) || \
+ ((VAL) == TSC_CTPL_11CYCLES) || \
+ ((VAL) == TSC_CTPL_12CYCLES) || \
+ ((VAL) == TSC_CTPL_13CYCLES) || \
+ ((VAL) == TSC_CTPL_14CYCLES) || \
+ ((VAL) == TSC_CTPL_15CYCLES) || \
+ ((VAL) == TSC_CTPL_16CYCLES))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_SS_Prescaler_definition TSC Spread spectrum prescaler definition
+ * @{
+ */
+#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
+#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_PG_Prescaler_definition TSC Pulse Generator prescaler definition
+ * @{
+ */
+#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
+#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
+#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
+#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
+#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
+#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
+#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+ ((VAL) == TSC_PG_PRESC_DIV2) || \
+ ((VAL) == TSC_PG_PRESC_DIV4) || \
+ ((VAL) == TSC_PG_PRESC_DIV8) || \
+ ((VAL) == TSC_PG_PRESC_DIV16) || \
+ ((VAL) == TSC_PG_PRESC_DIV32) || \
+ ((VAL) == TSC_PG_PRESC_DIV64) || \
+ ((VAL) == TSC_PG_PRESC_DIV128))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_MCV_definition TSC Max Count Value definition
+ * @{
+ */
+#define TSC_MCV_255 ((uint32_t)(0 << 5))
+#define TSC_MCV_511 ((uint32_t)(1 << 5))
+#define TSC_MCV_1023 ((uint32_t)(2 << 5))
+#define TSC_MCV_2047 ((uint32_t)(3 << 5))
+#define TSC_MCV_4095 ((uint32_t)(4 << 5))
+#define TSC_MCV_8191 ((uint32_t)(5 << 5))
+#define TSC_MCV_16383 ((uint32_t)(6 << 5))
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+ ((VAL) == TSC_MCV_511) || \
+ ((VAL) == TSC_MCV_1023) || \
+ ((VAL) == TSC_MCV_2047) || \
+ ((VAL) == TSC_MCV_4095) || \
+ ((VAL) == TSC_MCV_8191) || \
+ ((VAL) == TSC_MCV_16383))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_default_mode_definition TSC I/O default mode definition
+ * @{
+ */
+#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
+#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity
+ * @{
+ */
+#define TSC_SYNC_POL_FALL ((uint32_t)0)
+#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL)
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Acquisition_mode TSC Acquisition mode
+ * @{
+ */
+#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_mode_definition TSC I/O mode definition
+ * @{
+ */
+#define TSC_IOMODE_UNUSED ((uint32_t)0)
+#define TSC_IOMODE_CHANNEL ((uint32_t)1)
+#define TSC_IOMODE_SHIELD ((uint32_t)2)
+#define TSC_IOMODE_SAMPLING ((uint32_t)3)
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+ ((VAL) == TSC_IOMODE_CHANNEL) || \
+ ((VAL) == TSC_IOMODE_SHIELD) || \
+ ((VAL) == TSC_IOMODE_SAMPLING))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_interrupts_definition TSC interrupts definition
+ * @{
+ */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_flags_definition TSC Flags Definition
+ * @{
+ */
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_groups_definition TSC groups definition
+ * @{
+ */
+#define TSC_NB_OF_GROUPS (8)
+
+#define TSC_GROUP1 ((uint32_t)0x00000001)
+#define TSC_GROUP2 ((uint32_t)0x00000002)
+#define TSC_GROUP3 ((uint32_t)0x00000004)
+#define TSC_GROUP4 ((uint32_t)0x00000008)
+#define TSC_GROUP5 ((uint32_t)0x00000010)
+#define TSC_GROUP6 ((uint32_t)0x00000020)
+#define TSC_GROUP7 ((uint32_t)0x00000040)
+#define TSC_GROUP8 ((uint32_t)0x00000080)
+#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
+
+#define TSC_GROUP1_IDX ((uint32_t)0)
+#define TSC_GROUP2_IDX ((uint32_t)1)
+#define TSC_GROUP3_IDX ((uint32_t)2)
+#define TSC_GROUP4_IDX ((uint32_t)3)
+#define TSC_GROUP5_IDX ((uint32_t)4)
+#define TSC_GROUP6_IDX ((uint32_t)5)
+#define TSC_GROUP7_IDX ((uint32_t)6)
+#define TSC_GROUP8_IDX ((uint32_t)7)
+#define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
+#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
+#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
+#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
+#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
+
+#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
+#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
+#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
+#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
+#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
+
+#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
+#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
+#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
+#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
+#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
+
+#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
+#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
+#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
+#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
+#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
+
+#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
+#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
+#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
+#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
+#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
+
+#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
+#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
+#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
+#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
+#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
+
+#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
+#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
+#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
+#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
+#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
+
+#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
+#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
+#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
+#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
+#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
+
+#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros -----------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros TSC Private Macros
+ * @{
+ */
+/** @defgroup TSC_Spread_Spectrum TSC Spread Spectrum
+ * @{
+ */
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
+
+/** @brief Reset TSC handle state
+ * @param __HANDLE__: TSC handle.
+ * @retval None
+ */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+ * @brief Enable the TSC peripheral.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+ * @brief Disable the TSC peripheral.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+ * @brief Start acquisition
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+ * @brief Stop acquisition
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+ * @brief Set IO default mode to output push-pull low
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+ * @brief Set IO default mode to input floating
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+ * @brief Set synchronization polarity to falling edge
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+ * @brief Set synchronization polarity to rising edge and high level
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+ * @brief Enable TSC interrupt.
+ * @param __HANDLE__: TSC handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable TSC interrupt.
+ * @param __HANDLE__: TSC handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check if the specified TSC interrupt source is enabled or disabled.
+ * @param __HANDLE__: TSC Handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Get the selected TSC's flag status.
+ * @param __HANDLE__: TSC handle
+ * @param __FLAG__: TSC flag
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TSC's pending flag.
+ * @param __HANDLE__: TSC handle
+ * @param __FLAG__: TSC flag
+ * @retval None
+ */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable schmitt trigger hysteresis on a group of IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable schmitt trigger hysteresis on a group of IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Open analog switch on a group of IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Close analog switch on a group of IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Enable a group of IOs in channel mode
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of channel IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable a group of IOs in sampling mode
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of sampling IOs
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable acquisition groups
+ * @param __HANDLE__: TSC handle
+ * @param __GX_MASK__: Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+ * @brief Disable acquisition groups
+ * @param __HANDLE__: TSC handle
+ * @param __GX_MASK__: Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status
+ * @param __HANDLE__: TSC Handle
+ * @param __GX_INDEX__: Group index
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions TSC Exported Functions
+ * @{
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group4 State functions
+ * @brief State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
+ /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || */
+ /* defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F0xx_TSC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c
new file mode 100644
index 000000000..4300a4ca3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c
@@ -0,0 +1,1811 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_uart.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit ()API:
+ (##) Enable the USARTx interface clock.
+ (##) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
+ also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customed HAL_UART_MspInit() API.
+
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+ *** UART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in UART HAL driver.
+
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+
+ [..]
+ (@) You can refer to the UART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART HAL module driver
+ * @brief HAL UART module driver
+ * @{
+ */
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define HAL_UART_TXDMA_TIMEOUTVALUE 22000
+#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible UART frame formats are as listed in the following table:
+ |-----------|-----------|---------------------------------------|
+ | M1M0 bits | PCE bit | UART frame |
+ |-----------------------|---------------------------------------|
+ | 00 | 0 | | SB | 8-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 00 | 1 | | SB | 7-bit data | PB | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 01 | 0 | | SB | 9-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 01 | 1 | | SB | 8-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ | 10 | 0 | | SB | 7-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
+ API follow respectively the UART asynchronous, UART Half duplex and multiprocessor
+ configuration procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initializes the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ huart->Instance->CR3 |= USART_CR3_HDSEL;
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initializes the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long)
+ * @param WakeUpMethod: specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief DeInitializes the UART peripheral
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0;
+ huart->Instance->CR2 = 0x0;
+ huart->Instance->CR3 = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State = HAL_UART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief UART MSP Init
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART MSP DeInit
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_UART_Transmit()
+ (++) HAL_UART_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_UART_Transmit_IT()
+ (++) HAL_UART_Receive_IT()
+ (++) HAL_UART_IRQHandler()
+ (++) UART_Transmit_IT()
+ (++) UART_Receive_IT()
+
+ (#) Non Blocking mode APIs with DMA are :
+ (++) HAL_UART_Transmit_DMA()
+ (++) HAL_UART_Receive_DMA()
+ (++) HAL_UART_DMAPause()
+ (++) HAL_UART_DMAResume()
+ (++) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
+ (++) HAL_UART_TxHalfCpltCallback()
+ (++) HAL_UART_TxCpltCallback()
+ (++) HAL_UART_RxHalfCpltCallback()
+ (++) HAL_UART_RxCpltCallback()
+ (++) HAL_UART_ErrorCallback()
+
+ [..]
+ (@) In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ while(huart->TxXferCount > 0)
+ {
+ huart->TxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData += 2;
+ }
+ else
+ {
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Check if a non-blocking receive Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ __HAL_UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* as long as data have to be received */
+ while(huart->RxXferCount > 0)
+ {
+ huart->RxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ pData +=2;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* Check if a non-blocking transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Transmit Data Register Empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ __HAL_UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Enable the UART Parity Error Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Data Register not empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the UART transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode
+ * @param huart: uart handle
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param huart: UART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Disable the UART DMA Tx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Disable the UART DMA Rx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Disable the UART DMA Tx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ /* Disable the UART DMA Rx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param huart: UART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Enable the UART DMA Rx request */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Enable the UART DMA Rx request before the DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+ /* Enable the UART DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+
+ /* If the UART peripheral is still not enabled, enable it */
+ if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
+ {
+ /* Enable UART peripheral */
+ __HAL_UART_ENABLE(huart);
+ }
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param huart: UART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Disable the UART Tx/Rx DMA requests */
+ huart->Instance->CR3 &= ~USART_CR3_DMAT;
+ huart->Instance->CR3 &= ~USART_CR3_DMAR;
+
+ /* Abort the UART DMA tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ /* Abort the UART DMA rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ /* Disable UART peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param huart: UART handle
+ * @retval None
+ */
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param huart: uart handle
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param huart: UART handle
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART error callbacks
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_UART_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UART_DisableStopMode() API disables the above functionality
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
+ * @param huart: UART handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ huart->Instance->CR1 |= USART_CR1_MME;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
+ * as it may not have been in mute mode at this very moment).
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ huart->Instance->CR1 &= ~(USART_CR1_MME);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enables the UART transmitter and disables the UART receiver.
+ * @param huart: UART handle
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->State = HAL_UART_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the UART receiver and disables the UART transmitter.
+ * @param huart: UART handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->State = HAL_UART_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+
+/**
+ * @brief return the UART state
+ * @param huart: uart handle
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ return huart->State;
+}
+
+/**
+* @brief Return the UART error code
+* @param huart : pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+* @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT()
+ * @param huart: UART handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+
+ if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ {
+
+ if(huart->TxXferCount == 0)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ huart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+
+ huart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart: UART handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = huart->Mask;
+
+ if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ {
+
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ huart->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--huart->RxXferCount == 0)
+ {
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Check the UART Idle State
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->State= HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles UART Communication Timeout.
+ * @param huart: UART handle
+ * @param Flag: specifies the UART flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA UART transmit process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ /* Wait for UART TC Flag */
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ huart->State = HAL_UART_STATE_TIMEOUT;
+ HAL_UART_ErrorCallback(huart);
+ }
+ else
+ {
+ /* No Timeout */
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ HAL_UART_TxCpltCallback(huart);
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication error callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0;
+ huart->TxXferCount = 0;
+ huart->State= HAL_UART_STATE_READY;
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief Configure the UART peripheral
+ * @param huart: uart handle
+ * @retval None
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00000000;
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_ONEBIT_SAMPLING(huart->Init.OneBitSampling));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ __HAL_UART_GETCLOCKSOURCE(huart, clocksource);
+
+ /* Check the Over Sampling to set Baud Rate Register */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(__DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(__DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t) ((usartdiv & (uint16_t)0x000F) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ }
+
+ return ret;
+
+}
+
+/**
+ * @brief Configure the UART peripheral advanced feautures
+ * @param huart: uart handle
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h
new file mode 100644
index 000000000..29bf8761b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h
@@ -0,0 +1,934 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_uart.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_UART_H
+#define __STM32F0xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ - If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices),
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+}UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
+ Advanced Features may be initialized at the same time .
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref UART_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref UART_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref UART_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref UART_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
+ This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART clock sources definition
+ */
+typedef enum
+{
+ UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+}UART_ClockSourceTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_UART_StateTypeDef State; /*!< UART communication state */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code
+ This parameter can be a value of @ref UART_Error */
+
+}UART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported constants
+ * @{
+ */
+
+/** @defgroup UART_Error UART Error
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_1 ((uint32_t)0x0000)
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2) || \
+ ((STOPBITS) == UART_STOPBITS_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE ((uint32_t)0x0000)
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x0000)
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+ /** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x0000)
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 ((uint32_t)0x0000)
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000)
+#define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT)
+#define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \
+ ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED))
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
+#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_One_Bit UART One Bit sampling
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000)
+#define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT)
+#define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \
+ ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
+#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \
+ ((DMATX) == UART_DMA_TX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE ((uint32_t)0x0000)
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
+#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \
+ ((DMARX) == UART_DMA_RX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
+#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
+ ((HDSEL) == UART_HALF_DUPLEX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
+#define IS_UART_ADDRESSLENGTH_DETECT(ADDRESS) (((ADDRESS) == UART_ADDRESS_DETECT_4B) || \
+ ((ADDRESS) == UART_ADDRESS_DETECT_7B))
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT UART IT
+ * Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * @{
+ */
+#define UART_IT_ERR ((uint16_t)0x0060)
+
+/** Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ */
+#define UART_IT_ORE ((uint16_t)0x0300)
+#define UART_IT_NE ((uint16_t)0x0200)
+#define UART_IT_FE ((uint16_t)0x0100)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
+#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
+#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
+#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
+#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
+#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
+#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
+#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \
+ ((POLARITY) == UART_DE_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK ((uint32_t)0x001F)
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle state
+ * @param __HANDLE__: UART handle.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief Checks whether the specified UART flag is set or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral (datasheet: up to four USART/UARTs)
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_REACK: Receive enable ackowledge flag
+ * @arg UART_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg UART_FLAG_WUF: Wake up from stop mode flag (not available on F030xx devices)
+ * @arg UART_FLAG_RWU: Receiver wake up flag (not available on F030xx devices)
+ * @arg UART_FLAG_SBKF: Send Break flag
+ * @arg UART_FLAG_CMF: Character match flag
+ * @arg UART_FLAG_BUSY: Busy flag
+ * @arg UART_FLAG_ABRF: Auto Baud rate detection flag
+ * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
+ * @arg UART_FLAG_EOBF: End of block flag (not available on F030xx devices)
+ * @arg UART_FLAG_RTOF: Receiver timeout flag
+ * @arg UART_FLAG_CTS: CTS Change flag
+ * @arg UART_FLAG_LBD: LIN Break detection flag (not available on F030xx devices)
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enables the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief Disables the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Checks whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __IT__: specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_ORE: OverRun Error interrupt
+ * @arg UART_IT_NE: Noise Error interrupt
+ * @arg UART_IT_FE: Framing Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Checks whether the specified UART interrupt source is enabled.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __IT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_ORE: OverRun Error interrupt
+ * @arg UART_IT_NE: Noise Error interrupt
+ * @arg UART_IT_FE: Framing Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+
+/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg UART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg UART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg UART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag (not available on F030xx devices)
+ * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
+ * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices)
+ * @arg UART_CLEAR_CMF: Character Match Clear Flag
+ * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag (not available on F030xx devices)
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
+ * UART peripheral. (datasheet: up to four USART/UARTs)
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg UART_SENDBREAK_REQUEST: Send Break Request
+ * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
+ * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices)
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
+ * @param _PCLK_: UART clock
+ * @param _BAUD_: Baud rate set by the user
+ * @retval Division result
+ */
+#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_)))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
+ * @param _PCLK_: UART clock
+ * @param _BAUD_: Baud rate set by the user
+ * @retval Division result
+ */
+#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))
+
+/** @brief Check UART Baud rate
+ * @param BAUDRATE: Baudrate specified by the user
+ * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
+
+/** @brief Check UART assertion time
+ * @param TIME: 5-bit value assertion time
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+
+/** @brief Check UART deassertion time
+ * @param TIME: 5-bit value deassertion time
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/* Include UART HAL Extension module */
+#include "stm32f0xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c
new file mode 100644
index 000000000..0a0121e98
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c
@@ -0,0 +1,708 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Extended UART HAL module driver.
+ *
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The Extended UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx Extended HAL module driver
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length (Fixed to 8-bits only for LIN mode)
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible UART frame formats are as listed in the following table:
+ |-----------|-----------|---------------------------------------|
+ | M1M0 bits | PCE bit | UART frame |
+ |-----------------------|---------------------------------------|
+ | 00 | 0 | | SB | 8-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 00 | 1 | | SB | 7-bit data | PB | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 01 | 0 | | SB | 9-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 01 | 1 | | SB | 8-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ | 10 | 0 | | SB | 7-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_LIN_Init() and HAL_RS485Ex_Init() APIs follows respectively the LIN and
+ the UART RS485 mode configuration procedures (details for the procedures are
+ available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Initializes the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: uart handle
+ * @param UART_DEPolarity: select the driver enable polarity
+ * This parameter can be one of the following values:
+ * @arg UART_DE_POLARITY_HIGH: DE signal is active high
+ * @arg UART_DE_POLARITY_LOW: DE signal is active low
+ * @param UART_DEAssertionTime: Driver Enable assertion time
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param UART_DEDeassertionTime: Driver Enable deassertion time
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime)
+{
+ uint32_t temp = 0x0;
+
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(UART_DEPolarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(UART_DEAssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(UART_DEDeassertionTime));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ huart->Instance->CR3 |= USART_CR3_DEM;
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, UART_DEPolarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (UART_DEAssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (UART_DEDeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Initializes the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: uart handle
+ * @param BreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+
+ /* in LIN mode, data length is limited to 8-bit only */
+ if(huart->Init.WordLength!= UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ huart->Instance->CR2 |= USART_CR2_LINEN;
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
+ * @brief Extended UART Interrupt handling function
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to manage the UART interrupts
+ and to handle Wake up interrupt call-back.
+
+ (#) Non-Blocking mode API with Interrupt is :
+ (++) HAL_UART_IRQHandler()
+
+ (#) Callback provided in No_Blocking mode:
+ (++) HAL_UART_WakeupCallback()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief This function handles UART interrupt request.
+ * @param huart: uart handle
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART frame error interrupt occured --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART noise error interrupt occured --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART Over-Run interrupt occured -----------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ HAL_UART_ErrorCallback(huart);
+ }
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ HAL_UART_WakeupCallback(huart);
+ }
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
+ {
+ UART_Transmit_IT(huart);
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+}
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief UART wakeup from Stop mode callback
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_WakeupCallback can be implemented in the user file
+ */
+}
+#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides extended functions allowing to control the UART.
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
+ (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
+ long as UART clock is HSI or LSE
+ (+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+
+@endverbatim
+ * @{
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection
+ * @param huart: uart handle,
+ * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUP_ON_ADDRESS
+ * @arg UART_WAKEUP_ON_STARTBIT
+ * @arg UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ /* Check parameters */
+ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UART_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->State= HAL_UART_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Enable UART Stop Mode
+ * The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Set the USART UESM bit */
+ huart->Instance->CR1 |= USART_CR1_UESM;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode
+ * @param huart: uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear USART UESM bit */
+ huart->Instance->CR1 &= ~(USART_CR1_UESM);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection.
+ * This API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long):
+ * - 6-bit address detection in 7-bit data mode
+ * - 7-bit address detection in 8-bit data mode
+ * - 8-bit address detection in 9-bit data mode
+ * @param huart: UART handle
+ * @param AddressLength: this parameter can be one of the following values:
+ * @arg UART_ADDRESS_DETECT_4B: 4-bit long address
+ * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Transmits break characters.
+ * @param huart: UART handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart: uart handle
+ * @param WakeUpSelection: UART wake up from stop mode parameters
+ * @retval HAL status
+ */
+static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ /* Check parmeters */
+ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h
new file mode 100644
index 000000000..7a941621b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h
@@ -0,0 +1,770 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of UART HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_UART_EX_H
+#define __STM32F0xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UART_WakeUp_Address_Length */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max) */
+} UART_WakeUpTypeDef;
+/**
+ * @}
+ */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \
+ ((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#else
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode
+ * @{
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+#else
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE ((uint32_t)0x00000000)
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
+#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \
+ ((LIN) == UART_LIN_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+/**
+ * @}
+ */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/** @defgroup UART_Flags UARTEx Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_REACK ((uint32_t)0x00400000)
+#define UART_FLAG_TEACK ((uint32_t)0x00200000)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_FLAG_WUF ((uint32_t)0x00100000)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#define UART_FLAG_RWU ((uint32_t)0x00080000)
+#define UART_FLAG_SBKF ((uint32_t)0x00040000
+#define UART_FLAG_CMF ((uint32_t)0x00020000)
+#define UART_FLAG_BUSY ((uint32_t)0x00010000)
+#define UART_FLAG_ABRF ((uint32_t)0x00008000)
+#define UART_FLAG_ABRE ((uint32_t)0x00004000)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#define UART_FLAG_EOBF ((uint32_t)0x00001000)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#define UART_FLAG_RTOF ((uint32_t)0x00000800)
+#define UART_FLAG_CTS ((uint32_t)0x00000400)
+#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_FLAG_LBDF ((uint32_t)0x00000100)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#define UART_FLAG_TXE ((uint32_t)0x00000080)
+#define UART_FLAG_TC ((uint32_t)0x00000040)
+#define UART_FLAG_RXNE ((uint32_t)0x00000020)
+#define UART_FLAG_IDLE ((uint32_t)0x00000010)
+#define UART_FLAG_ORE ((uint32_t)0x00000008)
+#define UART_FLAG_NE ((uint32_t)0x00000004)
+#define UART_FLAG_FE ((uint32_t)0x00000002)
+#define UART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition
+ * Elements values convention: 0000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * @{
+ */
+#define UART_IT_PE ((uint16_t)0x0028)
+#define UART_IT_TXE ((uint16_t)0x0727)
+#define UART_IT_TC ((uint16_t)0x0626)
+#define UART_IT_RXNE ((uint16_t)0x0525)
+#define UART_IT_IDLE ((uint16_t)0x0424)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_IT_LBD ((uint16_t)0x0846)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#define UART_IT_CTS ((uint16_t)0x096A)
+#define UART_IT_CM ((uint16_t)0x112E)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_IT_WUF ((uint16_t)0x1476)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_IT_CLEAR_Flags UARTEx Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UARTEx Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
+ ((PARAM) == UART_SENDBREAK_REQUEST) || \
+ ((PARAM) == UART_MUTE_MODE_REQUEST) || \
+ ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((PARAM) == UART_TXDATA_FLUSH_REQUEST))
+#else
+#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
+ ((PARAM) == UART_SENDBREAK_REQUEST) || \
+ ((PARAM) == UART_MUTE_MODE_REQUEST) || \
+ ((PARAM) == UART_RXDATA_FLUSH_REQUEST))
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+/**
+ * @}
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000)
+#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)
+#define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000)
+#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
+#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
+#define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \
+ ((WAKE) == UART_WAKEUP_ON_STARTBIT) || \
+ ((WAKE) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+/**
+ * @}
+ */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
+ * @{
+ */
+
+/** @brief Reports the UART clock source.
+ * @param __HANDLE__: specifies the UART Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } while(0)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || \
+ defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F051x8) || defined (STM32F058xx)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F070xB)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F091xC) || defined (STM32F098xx)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART7) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART8) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F030xC)
+#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+
+#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
+
+
+/** @brief Computes the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__: specifies the UART Handle
+ * @retval none
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @brief Extended Initialization and Configuration Functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @brief Extended UART Interrupt handling function
+ * @{
+ */
+
+/* IO operation functions ***************************************************/
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6) && !defined(STM32F030xC)
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+/**
+ * @}
+ */
+/* Peripheral State functions ************************************************/
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c
new file mode 100644
index 000000000..a5fb466f4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c
@@ -0,0 +1,1831 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_usart.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure.
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit ()API:
+ (##) Enable the USARTx interface clock.
+ (##) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the husart Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_USART_MspInit(&husart) API.
+
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
+ *** USART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+
+ [..]
+ (@) You can refer to the USART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART HAL module driver
+ * @brief HAL USART Synchronous module driver
+ * @{
+ */
+#ifdef HAL_USART_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define DUMMY_DATA ((uint16_t) 0xFFFF)
+#define TEACK_REACK_TIMEOUT ((uint32_t) 1000)
+#define USART_TXDMA_TIMEOUTVALUE 22000
+#define USART_TIMEOUT_VALUE 22000
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE))
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
+ the possible USART frame formats are as listed in the following table:
+ +---------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |-----------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 10 | 0 | | SB | 7-bit data | STB | |
+ |-----------|-----------|---------------------------------------|
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |
+ +---------------------------------------------------------------+
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and create the associated handle .
+ * @param husart: usart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if(husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_USART_MspInit(husart);
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* Set the Usart Communication parameters */
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripharal */
+ __HAL_USART_ENABLE(husart);
+
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
+ return (USART_CheckIdleState(husart));
+}
+
+/**
+ * @brief DeInitializes the USART peripheral
+ * @param husart: usart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ husart->Instance->CR1 = 0x0;
+ husart->Instance->CR2 = 0x0;
+ husart->Instance->CR3 = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USART MSP Init
+ * @param husart: usart handle
+ * @retval None
+ */
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART MSP DeInit
+ * @param husart: usart handle
+ * @retval None
+ */
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..]
+ The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit()in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex Send an amount of data in blocking mode
+ * @param husart: USART handle
+ * @param pTxData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Check the remaining data to be sent */
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pTxData += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * To receive synchronous data, dummy data are simultaneously transmitted
+ * @param husart: USART handle
+ * @param pRxData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ __HAL_USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* as long as data have to be received */
+ while(husart->RxXferCount > 0)
+ {
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF);
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode
+ * @param husart: USART handle
+ * @param pTxData: pointer to TX data buffer
+ * @param pRxData: pointer to RX data buffer
+ * @param Size: amount of data to be sent (same amount to be received)
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ __HAL_USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* Check the remain data to be sent */
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & uhMask);
+ pTxData += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ }
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode
+ * @param husart: USART handle
+ * @param pTxData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+ are not managed by the USART Transmit Process to avoid the overrun interrupt
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the usart mode should be
+ configured only for transmit "USART_MODE_TX" */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * To receive synchronous data, dummy data are simultaneously transmitted
+ * @param husart: usart handle
+ * @param pRxData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ __HAL_USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+
+ /* Send dummy byte in order to generate the clock for the Slave to send the next data */
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF);
+ }
+ else
+ {
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode
+ * @param husart: USART handle
+ * @param pTxData: pointer to TX data buffer
+ * @param pRxData: pointer to RX data buffer
+ * @param Size: amount of data to be sent (same amount to be received)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ __HAL_USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode
+ * @param husart: USART handle
+ * @param pTxData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Receive an amount of data in non-blocking mode
+ * @param husart: USART handle
+ * @param pRxData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position)
+ * @retval HAL status
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
+ * @param husart: usart handle
+ * @param pTxData: pointer to TX data buffer
+ * @param pRxData: pointer to RX data buffer
+ * @param Size: amount of data to be received/sent
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param husart: USART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the USART DMA Tx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Disable the USART DMA Rx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ /* Disable the USART DMA Tx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ /* Disable the USART DMA Rx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param husart: USART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Enable the USART DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Enable the USART DMA Rx request */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ /* Enable the USART DMA Rx request before the DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+ /* Enable the USART DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+
+ /* If the USART peripheral is still not enabled, enable it */
+ if ((husart->Instance->CR1 & USART_CR1_UE) == 0)
+ {
+ /* Enable USART peripheral */
+ __HAL_USART_ENABLE(husart);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param husart: USART handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ /* Disable the USART Tx/Rx DMA requests */
+ husart->Instance->CR3 &= ~USART_CR3_DMAT;
+ husart->Instance->CR3 &= ~USART_CR3_DMAR;
+
+ /* Abort the USART DMA tx Channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ /* Abort the USART DMA rx Channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* Disable USART peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles USART interrupt request.
+ * @param husart: USART handle
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+
+ /* USART parity error interrupt occured ------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_IT_PE);
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART frame error interrupt occured -------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_IT_FE);
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART noise error interrupt occured -------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_IT_NE);
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART Over-Run interrupt occured ----------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_IT_ORE);
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ HAL_USART_ErrorCallback(husart);
+ }
+
+ /* USART in mode Receiver --------------------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* USART in mode Transmitter -----------------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ USART_Transmit_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ }
+
+}
+
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param husart: usart handle
+ * @retval None
+ */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param husart: USART handle
+ * @retval None
+ */
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param husart: USART handle
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks
+ * @param husart: usart handle
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process
+ * @param husart: usart handle
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callbacks
+ * @param husart: usart handle
+ * @retval None
+ */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief USART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the USART.
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral.
+ (+) USART_SetConfig() API is used to set the USART communication parameters.
+ (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the USART state
+ * @param husart: USART handle
+ * @retval HAL state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @brief USART Private functions
+ * @{
+ */
+
+/**
+ * @brief Configure the USART peripheral
+ * @param husart: USART handle
+ * @retval None
+ */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg = 0x0;
+ USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
+ * set CPOL bit according to husart->Init.CLKPolarity value
+ * set CPHA bit according to husart->Init.CLKPhase value
+ * set LBCL bit according to husart->Init.CLKLastBit value
+ * set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLED);
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+ tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* no CR3 register configuration */
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ __HAL_USART_GETCLOCKSOURCE(husart, clocksource);
+ switch (clocksource)
+ {
+ case USART_CLOCKSOURCE_PCLK1:
+ husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ husart->Instance->BRR = (uint16_t)(HSI_VALUE / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ husart->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ husart->Instance->BRR = (uint16_t)(LSE_VALUE / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the USART Idle State
+ * @param husart: USART handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+ /* Initialize the USART ErrorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ husart->State= HAL_USART_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ husart->State= HAL_USART_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the USART state*/
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles USART Communication Timeout.
+ * @param husart: USART handle
+ * @param Flag: specifies the USART flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DMA USART transmit process complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->TxXferCount = 0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Wait for USART TC Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Timeout Occured */
+ husart->State = HAL_USART_STATE_TIMEOUT;
+ HAL_USART_ErrorCallback(husart);
+ }
+ else
+ {
+ /* No Timeout */
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+ husart->State= HAL_USART_STATE_READY;
+ }
+ }
+ /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ else
+ {
+ husart->State= HAL_USART_STATE_BUSY_RX;
+ HAL_USART_TxCpltCallback(husart);
+}
+}
+
+
+/**
+ * @brief DMA USART transmit process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->RxXferCount = 0;
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_RxCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process half complete callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->RxXferCount = 0;
+ husart->TxXferCount = 0;
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT()
+ * @param husart: USART handle
+ * @retval HAL status
+ * @note The USART errors are not managed to avoid the overrun error.
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+
+ if(husart->TxXferCount == 0)
+ {
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+
+ husart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT()
+ * @param husart: USART handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
+
+ if(--husart->RxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_RxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT()
+ * @param husart: USART handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+
+ if(husart->TxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+ }
+ husart->TxXferCount--;
+
+ /* Check the latest data transmitted */
+ if(husart->TxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ }
+ }
+ }
+
+ if(husart->RxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ husart->RxXferCount--;
+ }
+ }
+
+ /* Check the latest data received */
+ if(husart->RxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxRxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h
new file mode 100644
index 000000000..cabbd3026
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h
@@ -0,0 +1,595 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_usart.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_USART_H
+#define __STM32F0xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USARTEx_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief USART clock sources definitions
+ */
+typedef enum
+{
+ USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+}USART_ClockSourceTypeDef;
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< USART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code
+ This parameter can be a value of @ref USART_Error */
+
+}USART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported constants
+ * @{
+ */
+
+/** @defgroup USART_Error USART Error
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_1 ((uint32_t)0x0000)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE ((uint32_t)0x0000)
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLED ((uint32_t)0x0000)
+#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
+ ((CLOCK) == USART_CLOCK_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW ((uint32_t)0x0000)
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE ((uint32_t)0x0000)
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE ((uint32_t)0x0000)
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define USART_FLAG_REACK ((uint32_t)0x00400000)
+#define USART_FLAG_TEACK ((uint32_t)0x00200000)
+#define USART_FLAG_BUSY ((uint32_t)0x00010000)
+#define USART_FLAG_CTS ((uint32_t)0x00000400)
+#define USART_FLAG_CTSIF ((uint32_t)0x00000200)
+#define USART_FLAG_LBDF ((uint32_t)0x00000100)
+#define USART_FLAG_TXE ((uint32_t)0x00000080)
+#define USART_FLAG_TC ((uint32_t)0x00000040)
+#define USART_FLAG_RXNE ((uint32_t)0x00000020)
+#define USART_FLAG_IDLE ((uint32_t)0x00000010)
+#define USART_FLAG_ORE ((uint32_t)0x00000008)
+#define USART_FLAG_NE ((uint32_t)0x00000004)
+#define USART_FLAG_FE ((uint32_t)0x00000002)
+#define USART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_ERR ((uint16_t)0x0060)
+
+#define USART_IT_ORE ((uint16_t)0x0300)
+#define USART_IT_NE ((uint16_t)0x0200)
+#define USART_IT_FE ((uint16_t)0x0100)
+/**
+ * @}
+ */
+
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
+ * @{
+ */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Request_Parameters USART Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IS_USART_REQUEST_PARAMETER(PARAM) (((PARAM) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((PARAM) == USART_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interruption_Mask USART interruptions flag mask
+ * @{
+ */
+#define USART_IT_MASK ((uint16_t)0x001F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+
+/** @brief Reset USART handle state
+ * @param __HANDLE__: USART handle.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Checks whether the specified USART flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_REACK: Receive enable ackowledge flag
+ * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg USART_FLAG_BUSY: Busy flag
+ * @arg USART_FLAG_CTS: CTS Change flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enables the specified USART interrupt.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __INTERRUPT__: specifies the USART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief Disables the specified USART interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __INTERRUPT__: specifies the USART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Checks whether the specified USART interrupt source is enabled.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
+ (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific USART request flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+
+/** @brief Check USART Baud rate
+ * @param BAUDRATE: Baudrate specified by the user
+ * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
+/**
+ * @}
+ */
+
+/* Include USART HAL Extension module */
+#include "stm32f0xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h
new file mode 100644
index 000000000..9f244f929
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h
@@ -0,0 +1,503 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_usart_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of USART HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_USART_EX_H
+#define __STM32F0xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USARTEx USARTEx Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+ * @{
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \
+ ((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+#else
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
+ * @{
+ */
+
+/** @brief Reports the USART clock source.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } while(0)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || \
+ defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F051x8) || defined (STM32F058xx)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined (STM32F070xB)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F091xC) || defined (STM32F098xx)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART7) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART8) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F030xC)
+#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
+
+
+/** @brief Reports the USART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__: specifies the USART Handle
+ * @retval none
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions ****************************/
+/* I/O operation functions ***************************************************/
+/* Peripheral Control functions **********************************************/
+/* Peripheral State functions ************************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c
new file mode 100644
index 000000000..946ecad9f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c
@@ -0,0 +1,449 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### WWDG specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the Counter (T[6;0] downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls over from 0x40 to 0x3F).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+ (+) WWDG clock (Hz) = PCLK / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock
+ where T[5;0] are the lowest 6 bits of Counter.
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (mS) = 1000 * (Counter-Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter-0x40) / WWDG clock
+
+ (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
+ (+) Set the WWDG prescaler, refresh window and counter value
+ using HAL_WWDG_Init() function.
+ (+) Start the WWDG using HAL_WWDG_Start() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
+ generated when the counter reaches 0x40, and then start the WWDG using
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
+ add his own code by customization of function pointer HAL_WWDG_WakeupCallback
+ Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the refresh window value already programmed.
+
+ *** WWDG HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup WWDG WWDG HAL module driver
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef and create the associated handle
+ (+) DeInitialize the WWDG peripheral
+ (+) Initialize the WWDG MSP
+ (+) DeInitialize the WWDG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the WWDG according to the specified
+ * parameters in the WWDG_InitTypeDef and creates the associated handle.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+
+ if(hwwdg->State == HAL_WWDG_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+ }
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Set WWDG Prescaler and Window */
+ MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Set WWDG Counter */
+ MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the WWDG peripheral.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_WWDG_MspDeInit(hwwdg);
+
+ /* Reset WWDG Control register */
+ hwwdg->Instance->CR = (uint32_t)0x0000007F;
+
+ /* Reset WWDG Configuration register */
+ hwwdg->Instance->CFR = (uint32_t)0x0000007F;
+
+ /* Reset WWDG Status register */
+ hwwdg->Instance->SR = 0;
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the WWDG MSP.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the WWDG MSP.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_WWDG_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the WWDG.
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the WWDG.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Enable the peripheral */
+ __HAL_WWDG_ENABLE(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the WWDG with interrupt enabled.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Enable the Early Wakeup Interrupt */
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
+
+ /* Enable the peripheral */
+ __HAL_WWDG_ENABLE(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Refreshes the WWDG.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @param Counter: value of counter to put in WWDG counter
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Wheck if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Early Wakeup callback */
+ HAL_WWDG_WakeupCallback(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+ }
+ }
+}
+
+/**
+ * @brief Early Wakeup WWDG callback.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_WWDG_WakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the WWDG state.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL state
+ */
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
+{
+ return hwwdg->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h
new file mode 100644
index 000000000..155f5448d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h
@@ -0,0 +1,334 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 11-December-2014
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_WWDG_H
+#define __STM32F0xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
+ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
+ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
+ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
+}HAL_WWDG_StateTypeDef;
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number lower than Max_Data = 0x80 */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+} WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< WWDG locking object */
+
+ __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
+
+} WWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Window WWDG Window
+ * @{
+ */
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Counter WWDG Counter
+ * @{
+ */
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+
+/** @brief Reset WWDG handle state
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
+
+/**
+ * @brief Enables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
+
+/**
+ * @brief Disables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
+
+/**
+ * @brief Gets the selected WWDG's it status.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Clear the WWDG's interrupt pending bits
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Gets the selected WWDG's flag status.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the WWDG's pending flags.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __HANDLE__: WWDG Handle.
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/Release_Notes_stm32f1xx_hal.html b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/Release_Notes_stm32f1xx_hal.html
new file mode 100644
index 000000000..c3219be4c
--- /dev/null
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+ <meta content="MCD Application Team" name="author"></head>
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+
+<div class="WordSection1">
+
+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
+
+<div align="center">
+
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+ <tbody><tr style="">
+ <td style="padding: 0in;" valign="top">
+ <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+ <tbody><tr style="">
+ <td style="padding: 0in 5.4pt;" valign="top">
+ <p class="MsoNormal"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+ </td>
+ </tr>
+ <tr style="">
+ <td style="padding: 1.5pt;">
+ <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for STM32F1xx HAL Drivers</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
+ 2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+ <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img style="border: 0px solid ; width: 112px; height: 83px;" alt="" id="_x0000_i1026" src="../../_htmresc/st_logo.png"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+ </td>
+ </tr>
+ </tbody></table>
+ <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
+ <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+ <tbody><tr style="">
+ <td style="padding: 0in;" valign="top">
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 15-December-2014</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First Official release of <span style="font-weight: bold;">STM32F1xx HAL
+Drivers</span> for all STM32F1</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">devices</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">This
+release is in line with <span style="font-weight: bold;">STM32Cube
+Firmware specification Rev1.0</span> document&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+ <div style="text-align: justify;">
+ <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+ </font>
+ <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+ </font>
+ </li></ol>
+ <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+ <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+ <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+
+ </div>
+<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></div>
+<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span>
+ <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+ <hr align="center" size="2" width="100%">
+ </span></div>
+ <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+ complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
+ Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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+
+</div></body></html> \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld
new file mode 100644
index 000000000..cc4103d43
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld
@@ -0,0 +1,156 @@
+/* Linker script for STM32F407 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+ RAM (rwx) : ORIGIN = 0x200001D0, LENGTH = 8K - 0x1D0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s
new file mode 100644
index 000000000..c1bf0b23a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.s
@@ -0,0 +1,423 @@
+/**
+ *************** (C) COPYRIGHT 2014 STMicroelectronics ************************
+ * @file startup_stm32f100xb.s
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief STM32F100xB Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+/* bl __libc_init_array */
+/* Call the application's entry point.*/
+/* bl main */
+ bl _start
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10xB Value Line devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h
new file mode 100644
index 000000000..8bd1a4d1c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c
new file mode 100644
index 000000000..2da63fc9a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h
new file mode 100644
index 000000000..1410b207e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
+// MCU Peripherals: 100 vectors (= 400 bytes from 0x40 to 0x1CC)
+// Total: 464 bytes to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS (16 + 100)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c
new file mode 100644
index 000000000..9e42da7a4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+void set_compare(uint16_t count);
+
+extern volatile uint32_t SlaveCounter;
+extern volatile uint32_t oc_int_part;
+extern volatile uint16_t oc_rem_part;
+
+void timer_irq_handler(void) {
+ uint16_t cval = TIM_MST->CNT;
+
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Clear Update interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
+ SlaveCounter++;
+ }
+
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ if (oc_rem_part > 0) {
+ set_compare(oc_rem_part); // Finish the remaining time left
+ oc_rem_part = 0;
+ } else {
+ if (oc_int_part > 0) {
+ set_compare(0xFFFF);
+ oc_rem_part = cval; // To finish the counter loop the next time
+ oc_int_part--;
+ } else {
+ us_ticker_irq_handler();
+ }
+ }
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_Base_Init(&TimMasterHandle);
+
+ // Configure output compare channel 1 for mbed timeout (enabled later when used)
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Configure output compare channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+
+ // Configure interrupts
+ // Update interrupt used for 32-bit counter
+ // Output compare channel 1 interrupt for mbed timeout
+ // Output compare channel 2 interrupt for HAL tick
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Enable interrupts
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
+
+ // Enable timer
+ HAL_TIM_Base_Start(&TimMasterHandle);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h
new file mode 100644
index 000000000..09c66b92c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM4
+#define TIM_MST_IRQ TIM4_IRQn
+#define TIM_MST_RCC __TIM4_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM4_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h
new file mode 100644
index 000000000..41a76df4d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h
@@ -0,0 +1,4073 @@
+/**
+ ******************************************************************************
+ * @file stm32f100xb.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f100xb
+ * @{
+ */
+
+#ifndef __STM32F100xB_H
+#define __STM32F100xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+ __IO uint32_t SR;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
+
+#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+
+
+
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
+
+
+
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
+
+#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+
+
+
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
+
+
+
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
+
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+
+ #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */
+ #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
+#define CEC_CFGR_IE ((uint32_t)0x00000002) /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM ((uint32_t)0x00000004) /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM ((uint32_t)0x00000008) /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA ((uint32_t)0x0000000F) /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define CEC_OAR_OA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define CEC_OAR_OA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define CEC_OAR_OA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES ((uint32_t)0x00003FFF) /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE ((uint32_t)0x00000001) /*!< Bit Timing Error */
+#define CEC_ESR_BPE ((uint32_t)0x00000002) /*!< Bit Period Error */
+#define CEC_ESR_RBTFE ((uint32_t)0x00000004) /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE ((uint32_t)0x00000008) /*!< Start Bit Error */
+#define CEC_ESR_ACKE ((uint32_t)0x00000010) /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE ((uint32_t)0x00000020) /*!< Line Error */
+#define CEC_ESR_TBTFE ((uint32_t)0x00000040) /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM ((uint32_t)0x00000001) /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM ((uint32_t)0x00000002) /*!< Tx End Of Message */
+#define CEC_CSR_TERR ((uint32_t)0x00000004) /*!< Tx Error */
+#define CEC_CSR_TBTRF ((uint32_t)0x00000008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM ((uint32_t)0x00000010) /*!< Rx Start Of Message */
+#define CEC_CSR_REOM ((uint32_t)0x00000020) /*!< Rx End Of Message */
+#define CEC_CSR_RERR ((uint32_t)0x00000040) /*!< Rx Error */
+#define CEC_CSR_RBTF ((uint32_t)0x00000080) /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD ((uint32_t)0x000000FF) /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD ((uint32_t)0x000000FF) /*!< Rx Data register */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
+#define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
+#define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */
+#define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+
+
+
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+
+#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
+
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+
+
+
+#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+
+
+
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+
+
+
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
+
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+
+
+
+#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+
+
+
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F100xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h
new file mode 100644
index 000000000..7609aa728
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F1xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+ !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+#define STM32F100xB /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V4.0.0
+ */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+ #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+ #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+ #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+ #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+ #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+ #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+ #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+ #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+ #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+ #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+ #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+ #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+ #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+ #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c
new file mode 100644
index 000000000..abbe81c0f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c
@@ -0,0 +1,603 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f1xx.c
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+ * the product used), refer to "HSE_VALUE".
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 8 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 24 | 24
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f1xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+ uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F105xC */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depending on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F100xB or STM32F100xE */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F105xC */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f1xx_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmpreg;
+ /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+ (void)(tmpreg);
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x444B4B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001091;
+ FSMC_Bank1->BTCR[5] = 0x00110212;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h
new file mode 100644
index 000000000..e344021f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f103xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f103xb.s
new file mode 100644
index 000000000..09a1908eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f103xb.s
@@ -0,0 +1,300 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f103xb.s
+;* Author : MCD Application Team
+;* Version : V4.0.0
+;* Date : 16-December-2014
+;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* COPYRIGHT(c) 2014 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20005000 ; Top of RAM
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct
new file mode 100644
index 000000000..857bd6211
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x20000 { ; load region size_region (128K)
+
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
+ RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/startup_stm32f103xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/startup_stm32f103xb.s
new file mode 100644
index 000000000..fd8ae113f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/startup_stm32f103xb.s
@@ -0,0 +1,273 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f103xb.s
+;* Author : MCD Application Team
+;* Version : V4.0.0
+;* Date : 16-December-2014
+;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* COPYRIGHT(c) 2014 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp EQU 0x20005000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f103xb.sct b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f103xb.sct
new file mode 100644
index 000000000..857bd6211
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f103xb.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LR_IROM1 0x08000000 0x20000 { ; load region size_region (128K)
+
+ ER_IROM1 0x08000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
+ RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.cpp b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..bb665909b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld
new file mode 100644
index 000000000..e3b9e14dd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld
@@ -0,0 +1,154 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x200000EC, LENGTH = 20K - 0xEC
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.s
new file mode 100644
index 000000000..dfd7da400
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.s
@@ -0,0 +1,379 @@
+/**
+ *************** (C) COPYRIGHT 2014 STMicroelectronics ************************
+ * @file startup_stm32f103xb.s
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief STM32F103xB Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/startup_stm32f103xb.s b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/startup_stm32f103xb.s
new file mode 100644
index 000000000..67807932d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/startup_stm32f103xb.s
@@ -0,0 +1,410 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name : startup_stm32f103xb.s
+;* Author : MCD Application Team
+;* Version : V4.0.0
+;* Date : 16-December-2014
+;* Description : STM32F103xB Performance Line Devices vector table for
+;* EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f103xb.icf b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f103xb.icf
new file mode 100644
index 000000000..21cb93bac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f103xb.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x200000EB;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000EC;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0xA00;
+define symbol __ICFEDIT_size_heap__ = 0x1400;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block HEAP, block CSTACK }; \ No newline at end of file
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis.h
new file mode 100644
index 000000000..8bd1a4d1c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.c
new file mode 100644
index 000000000..2da63fc9a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.h
new file mode 100644
index 000000000..3711fee67
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.h
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F)
+// MCU Peripherals: 43 vectors (= 172 bytes from 0x40 to 0xEB)
+// Total: 236 bytes to be reserved in RAM (see scatter file)
+#define NVIC_NUM_VECTORS (16 + 43)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.c
new file mode 100644
index 000000000..9e42da7a4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.c
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+void set_compare(uint16_t count);
+
+extern volatile uint32_t SlaveCounter;
+extern volatile uint32_t oc_int_part;
+extern volatile uint16_t oc_rem_part;
+
+void timer_irq_handler(void) {
+ uint16_t cval = TIM_MST->CNT;
+
+ TimMasterHandle.Instance = TIM_MST;
+
+ // Clear Update interrupt flag
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
+ SlaveCounter++;
+ }
+
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+ if (oc_rem_part > 0) {
+ set_compare(oc_rem_part); // Finish the remaining time left
+ oc_rem_part = 0;
+ } else {
+ if (oc_int_part > 0) {
+ set_compare(0xFFFF);
+ oc_rem_part = cval; // To finish the counter loop the next time
+ oc_int_part--;
+ } else {
+ us_ticker_irq_handler();
+ }
+ }
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
+ __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ HAL_TIM_Base_Init(&TimMasterHandle);
+
+ // Configure output compare channel 1 for mbed timeout (enabled later when used)
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Configure output compare channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+
+ // Configure interrupts
+ // Update interrupt used for 32-bit counter
+ // Output compare channel 1 interrupt for mbed timeout
+ // Output compare channel 2 interrupt for HAL tick
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Enable interrupts
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
+
+ // Enable timer
+ HAL_TIM_Base_Start(&TimMasterHandle);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.h
new file mode 100644
index 000000000..09c66b92c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.h
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f1xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM4
+#define TIM_MST_IRQ TIM4_IRQn
+#define TIM_MST_RCC __TIM4_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM4_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f103xb.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f103xb.h
new file mode 100644
index 000000000..2c7c0783a
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f103xb.h
@@ -0,0 +1,5906 @@
+/**
+ ******************************************************************************
+ * @file stm32f103xb.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103xb
+ * @{
+ */
+
+#ifndef __STM32F103xB_H
+#define __STM32F103xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+
+#define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint32_t)0x00000001) /*!< Force USB Reset */
+#define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!< Low-power mode */
+#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!< Force suspend */
+#define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint32_t)0x00000010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint32_t)0x00000200) /*!< Start Of Frame */
+#define USB_ISTR_RESET ((uint32_t)0x00000400) /*!< USB RESET request */
+#define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!< Wake up */
+#define USB_ISTR_ERR ((uint32_t)0x00002000) /*!< Error */
+#define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint32_t)0x00008000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint32_t)0x000007FF) /*!< Frame Number */
+#define USB_FNR_LSOF ((uint32_t)0x00001800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint32_t)0x00002000) /*!< Locked */
+#define USB_FNR_RXDM ((uint32_t)0x00004000) /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint32_t)0x00008000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
+
+#define USB_DADDR_EF ((uint32_t)0x00000080) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!< Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!< CAN software master reset */
+#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!< Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!< Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!< Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!< Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!< Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!< Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
+#define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
+#define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */
+#define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+
+
+
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+
+
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+
+
+
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f1xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f1xx.h
new file mode 100644
index 000000000..24ed93993
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f1xx.h
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F1xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+ !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+ /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+#define STM32F103xB /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V4.0.0
+ */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+ #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+ #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+ #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+ #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+ #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+ #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+ #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+ #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+ #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+ #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+ #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+ #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+ #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+ #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c
new file mode 100644
index 000000000..196ddfff5
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c
@@ -0,0 +1,605 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f1xx.c
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+ * the product used), refer to "HSE_VALUE".
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 8 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 36 | 32
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 72 | 64
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | NO | NO
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f1xx.h"
+#include "hal_tick.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+ uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F105xC */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depending on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F100xB or STM32F100xE */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F105xC */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f1xx_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmpreg;
+ /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+ (void)(tmpreg);
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x444B4B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001091;
+ FSMC_Bank1->BTCR[5] = 0x00110212;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.h
new file mode 100644
index 000000000..e344021f3
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.h
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 16-December-2014
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h
new file mode 100644
index 000000000..3b041ea33
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h
@@ -0,0 +1,2165 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100)
+#define ETH_MMCRIR ((uint32_t)0x00000104)
+#define ETH_MMCTIR ((uint32_t)0x00000108)
+#define ETH_MMCRIMR ((uint32_t)0x0000010C)
+#define ETH_MMCTIMR ((uint32_t)0x00000110)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
+#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+
+#endif
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.c
new file mode 100644
index 000000000..b7cc4edf0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.c
@@ -0,0 +1,526 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+
+/**
+ * @brief STM32F1xx HAL Driver version number V1.0.0
+ */
+#define __STM32F1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
+ |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
+ |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
+ |(__STM32F1xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+
+static __IO uint32_t uwTick;
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the source of time base also when timeout
+ is needed and the backup domain when enabled.
+ (+) de-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __Weak
+ to make override possible in case of other implementations in user file.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function configures the Flash prefetch,
+ * Configures time base source, NVIC and Low level hardware
+ * Note: This function is called at the beginning of program after reset and before
+ * the clock configuration
+ * Note: The time base configuration is based on MSI clock when exiting from Reset.
+ * Once done, time base tick start incrementing.
+ * In the default implementation,Systick is used as source of time base.
+ * the tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0)
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+ /* Prefetch buffer is not available on value line devices */
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the source
+ * of time base.
+ * Note: This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
+#endif
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * Note: This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * Note: In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * Note: In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * Note: This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick++;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * Note: This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * Note: In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * Note: ThiS function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+ uint32_t tickstart = 0;
+ tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * Note: In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * Note: This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * Note: In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * Note: This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F1xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> POSITION_VAL(DBGMCU_IDCODE_REV_ID));
+}
+
+/**
+ * @brief Returns the device identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ * If the system tick timer interrupt is enabled during the Stop mode
+ * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ * the system from Stop mode.
+ * Workaround: To debug the Stop mode, disable the system tick timer
+ * interrupt.
+ * Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ * If the system tick timer interrupt is enabled during the Stop mode
+ * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ * the system from Stop mode.
+ * Workaround: To debug the Stop mode, disable the system tick timer
+ * interrupt.
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h
new file mode 100644
index 000000000..feb9809cf
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h
@@ -0,0 +1,328 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_H
+#define __STM32F1xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_conf.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
+ * @brief Freeze/Unfreeze Peripherals in Debug mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @{
+ */
+
+/* Peripherals on APB1 */
+/**
+ * @brief TIM2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+
+/**
+ * @brief TIM3 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+
+#if defined (DBGMCU_CR_DBG_TIM4_STOP)
+/**
+ * @brief TIM4 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM5_STOP)
+/**
+ * @brief TIM5 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM6_STOP)
+/**
+ * @brief TIM6 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM7_STOP)
+/**
+ * @brief TIM7 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM12_STOP)
+/**
+ * @brief TIM12 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM13_STOP)
+/**
+ * @brief TIM13 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM14_STOP)
+/**
+ * @brief TIM14 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#endif
+
+/**
+ * @brief WWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+
+/**
+ * @brief IWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+
+/**
+ * @brief I2C1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+
+#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+/**
+ * @brief I2C2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN1_STOP)
+/**
+ * @brief CAN1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN2_STOP)
+/**
+ * @brief CAN2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#endif
+
+/* Peripherals on APB2 */
+#if defined (DBGMCU_CR_DBG_TIM1_STOP)
+/**
+ * @brief TIM1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM8_STOP)
+/**
+ * @brief TIM8 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM9_STOP)
+/**
+ * @brief TIM9 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM10_STOP)
+/**
+ * @brief TIM10 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM11_STOP)
+/**
+ * @brief TIM11 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#endif
+
+
+#if defined (DBGMCU_CR_DBG_TIM15_STOP)
+/**
+ * @brief TIM15 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM16_STOP)
+/**
+ * @brief TIM16 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM17_STOP)
+/**
+ * @brief TIM17 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c
new file mode 100644
index 000000000..e347d3e91
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c
@@ -0,0 +1,1924 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_adc.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Channels configuration on injected group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32f1xx_hal_adc_ex.c".
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit resolution
+
+ (+) Interrupt generation at the end of regular conversion, end of injected
+ conversion, and in case of analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for automatic conversion of channel 0 to channel 'n'.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Channel-wise programmable sampling time.
+
+ (+) ADC conversion Regular or Injected groups.
+
+ (+) External trigger (timer or EXTI) with configurable polarity for both
+ regular and injected groups.
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Multimode Dual mode (available on devices with 2 ADCs or more).
+
+ (+) Configurable DMA data storage in Multimode Dual mode (available on devices
+ with 2 DCs or more).
+
+ (+) Configurable delay between conversions in Dual interleaved mode (available
+ on devices with 2 DCs or more).
+
+ (+) ADC calibration
+
+ (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+ Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
+ to device datasheet).
+ Therefore, ADC clock prescaler must be configured in
+ function of ADC clock source frequency to remain
+ below this maximum frequency.
+ (++) One clock setting is mandatory:
+ ADC clock (core and conversion clock).
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
+ (+++) __ADC1_CLK_ENABLE();
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==========================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...,
+ of regular group)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters
+ using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ (++) For devices with several ADCs: ADC multimode conversion
+ with transfer by DMA:
+ (+++) Activate the ADC peripheral (slave) and start conversions
+ using function HAL_ADC_Start()
+ (+++) Activate the ADC peripheral (master) and start conversions
+ using function HAL_ADCEx_MultiModeStart_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral (master)
+ using function HAL_ADCEx_MultiModeStop_DMA()
+ (+++) Stop conversion and disable the ADC peripheral (slave)
+ using function HAL_ADC_Stop_IT()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+ (+@) HAL_ADCEx_InjectedConvCpltCallback()
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+ /* Timeout values for ADC enable and disable settling time. */
+ /* Values defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+
+ /* Delay for ADC stabilization time. */
+ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ((uint32_t) 1)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (clock source APB2).
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_cr1 = 0;
+ uint32_t tmp_cr2 = 0;
+ uint32_t tmp_sqr1 = 0;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock enabling */
+ /* procedure. */
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hadc-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+ }
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ /* Note: In case of ADC already enabled, precaution to not launch an */
+ /* unwanted conversion while modifying register CR2 by writing 1 to */
+ /* bit ADON. */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Initialize the ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY;
+
+ /* Set ADC parameters */
+
+ /* Configuration of ADC: */
+ /* - data alignment */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity (always set to 1, because needed for all */
+ /* triggers: external trigger of SW start) */
+ /* - continuous conversion mode */
+ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
+ /* HAL_ADC_Start_xxx functions because if set in this function, */
+ /* a conversion on injected group would start a conversion also on */
+ /* regular group after ADC enabling. */
+ tmp_cr2 |= (hadc->Init.DataAlign |
+ ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
+ ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
+
+ /* Configuration of ADC: */
+ /* - scan mode */
+ /* - discontinuous mode disable/enable */
+ /* - discontinuous mode number of conversions */
+ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ /* Set the number of channels to be converted in discontinuous mode */
+ tmp_cr1 |= (ADC_CR1_DISCEN |
+ ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
+ }
+
+ /* Update ADC configuration register CR1 with previous settings */
+ MODIFY_REG(hadc->Instance->CR1,
+ ADC_CR1_SCAN |
+ ADC_CR1_DISCEN |
+ ADC_CR1_DISCNUM ,
+ tmp_cr1 );
+
+ /* Update ADC configuration register CR2 with previous settings */
+ MODIFY_REG(hadc->Instance->CR2,
+ ADC_CR2_ALIGN |
+ ADC_CR2_EXTSEL |
+ ADC_CR2_EXTTRIG |
+ ADC_CR2_CONT ,
+ tmp_cr2 );
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion" */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
+ }
+
+ MODIFY_REG(hadc->Instance->SQR1,
+ ADC_SQR1_L ,
+ tmp_sqr1 );
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core IP clocking. */
+ /* Check through register CR2 (excluding bits set in other functions: */
+ /* execution control bits (ADON, JSWSTART, SWSTART), injected group bits */
+ /* (JEXTTRIG and JEXTSEL), channel internal measurement path bit (TSVREFE)*/
+ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON |
+ ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
+ ADC_CR2_TSVREFE ))
+ == tmp_cr2)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize the ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * If needed, the example code can be copied and uncommented into
+ * function HAL_ADC_MspDeInit().
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY;
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* ========== Reset ADC registers ========== */
+
+
+
+
+ /* Reset register SR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
+ ADC_FLAG_JSTRT | ADC_FLAG_STRT));
+
+ /* Reset register CR1 */
+ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
+ ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
+ ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
+ ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
+
+ /* Reset register CR2 */
+ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
+ ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
+ ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
+ ADC_CR2_ADON ));
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
+ ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
+ ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
+ ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
+ ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
+ ADC_SMPR2_SMP0 ));
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
+ ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
+ ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
+ /* */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* State machine update: Check if an injected conversion is ongoing */
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): if ADC is */
+ /* slave, ADC is enabled only (conversion is not started). If ADC is */
+ /* master, ADC is enabled and conversion is started. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Variables for polling in case of scan mode enabled and polling for each */
+ /* conversion. */
+ __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* - If single conversion for regular group (Scan mode disabled or enabled */
+ /* with NbrOfConversion =1), flag EOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for regular group, flag EOC is set only a the */
+ /* end of the sequence. To poll for each conversion, the maximum */
+ /* conversion time is calculated from ADC conversion time (selected */
+ /* sampling time + conversion time of 12.5 ADC clock cycles) and */
+ /* APB2/ADC clock prescalers (depending on settings, conversion time */
+ /* range can be from 28 to 32256 CPU cycles). */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
+ HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Poll with maximum conversion time */
+ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
+ /* and ADC maximum conversion cycles on all channels. */
+ /* - Wait for the expected ADC clock cycles delay */
+ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
+ / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
+ * ADC_CONVCYCLES_MAX_RANGE(hadc) );
+
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Update ADC state machine */
+ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
+ {
+ /* Check if a conversion is ready on injected group */
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for conversion event.
+ * @param hadc: ADC handle
+ * @param EventType: the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get start tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Analog watchdog (level out of window) event */
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_AWD;
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* State machine update: Check if an injected conversion is ongoing */
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): if ADC is */
+ /* slave, ADC is enabled only (conversion is not started). If ADC is */
+ /* master, ADC is enabled and conversion is started. */
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * Each of these interruptions has its dedicated callback function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStart function.
+ * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
+ * on devices) have DMA capability.
+ * ADC2 converted data can be transferred in dual ADC mode using DMA
+ * of ADC1 (ADC master in multimode).
+ * In case of using ADC1 with DMA on a device featuring 2 ADC
+ * instances: ADC1 conversion register DR contains ADC1 conversion
+ * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
+ * conversion result (ADC1 register DR bits 16 to 27). Therefore, to
+ * have DMA transferring the conversion results of ADC1 only, DMA must
+ * be configured to transfer size: half word.
+ * @param hadc: ADC handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
+
+ /* Verification if multimode is disabled (for devices with several ADC) */
+ /* If multimode is enabled, dedicated function multimode conversion */
+ /* start DMA must be used. */
+ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* State machine update: Check if an injected conversion is ongoing */
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC DMA mode */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStop function.
+ * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
+ * on devices) have DMA capability.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Disable ADC DMA mode */
+ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading DR register automatically clears EOC (end of conversion of
+ * regular group) flag.
+ * @param hadc: ADC handle
+ * @retval Converted value
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handles ADC interrupt request
+ * @param hadc: ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Update ADC state machine */
+ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
+ {
+ /* Check if a conversion is ready on injected group */
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+ }
+ }
+
+ /* Disable interruption if no further conversion upcoming regular */
+ /* external trigger or by continuous mode */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+ }
+ }
+
+ /* ========== Check End of Conversion flag for injected group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Update ADC state machine */
+ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
+ {
+
+ if(hadc->State == HAL_ADC_STATE_EOC_REG)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ;
+ }
+ }
+ }
+
+ /* Disable interruption if no further conversion upcoming injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above). */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ }
+
+ /* Conversion complete callback */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+ }
+ }
+
+ /* ========== Check Analog watchdog flags ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_AWD;
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear the ADCx's Analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
+ }
+ }
+
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog callback in non blocking mode.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non blocking mode
+ * (ADC conversion with interruption or transfer by DMA)
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Regular sequence configuration */
+ /* For Rank 1 to 6 */
+ if (sConfig->Rank < 7)
+ {
+ MODIFY_REG(hadc->Instance->SQR3 ,
+ ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
+ ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 7 to 12 */
+ else if (sConfig->Rank < 13)
+ {
+ MODIFY_REG(hadc->Instance->SQR2 ,
+ ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
+ ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ MODIFY_REG(hadc->Instance->SQR1 ,
+ ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
+ ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
+ }
+
+
+ /* Channel sampling time configuration */
+ /* For channels 10 to 17 */
+ if (sConfig->Channel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+ }
+ else /* For channels 0 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfig->Channel == ADC_CHANNEL_VREFINT) )
+ {
+ /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
+ /* measurement channels (VrefInt/TempSensor). If these channels are */
+ /* intended to be set on other ADC instances, an error is reported. */
+ if (hadc->Instance == ADC1)
+ {
+ if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configures the analog watchdog.
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
+
+ if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Analog watchdog configuration */
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: regular and/or injected groups, */
+ /* one or all channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ MODIFY_REG(hadc->Instance->CR1 ,
+ ADC_CR1_AWDSGL |
+ ADC_CR1_JAWDEN |
+ ADC_CR1_AWDEN |
+ ADC_CR1_AWDCH ,
+ AnalogWDGConfig->WatchdogMode |
+ AnalogWDGConfig->Channel );
+
+ /* Set the high threshold */
+ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
+
+ /* Set the low threshold */
+ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the ADC state
+ * @param hadc: ADC handle
+ * @retval HAL state
+ */
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+ /* Return ADC state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code
+ * @param hadc: ADC handle
+ * @retval ADC Error Code
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively enabled */
+ while(ADC_IS_ENABLE(hadc) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop ADC conversion and disable the selected ADC
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped to disable the ADC.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Verification if ADC is not already disabled */
+ if (ADC_IS_ENABLE(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively disabled */
+ while(ADC_IS_ENABLE(hadc) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to ADC IP internal error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Update ADC state machine */
+ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
+ {
+ /* Check if a conversion is ready on injected group */
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_REG;
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Half conversion callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Set ADC error code to DMA error */
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.h
new file mode 100644
index 000000000..a1b9e5d84
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.h
@@ -0,0 +1,946 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_H
+#define __STM32F1xx_HAL_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of ADC and regular group initialization
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADC_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADC_Scan_mode
+ Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
+ or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
+ the last conversion of the sequence. All previous conversions would be overwritten by the last one.
+ Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADC_External_trigger_source_Regular */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+ Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+ Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
+ It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
+ Refer to errata sheet of these devices for more details. */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
+ This parameter can be a value of @ref ADC_regular_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration analog watchdog definition
+ * @note The setting of these parameters with function is conditioned to ADC state.
+ * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+ This parameter can be a value of @ref ADC_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief HAL ADC state machine: ADC States structure definition
+ */
+typedef enum
+{
+ HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
+ HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
+ HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
+ HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
+ HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
+ HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
+ HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
+ HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
+ HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
+ HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F1xx devices (kept for compatibility with other devices featuring several AWD) */
+ HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F1xx devices (kept for compatibility with other devices featuring several AWD) */
+}HAL_ADC_StateTypeDef;
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Data_align ADC data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC scan mode
+ * @{
+ */
+/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
+/* compatibility with other STM32 devices having a sequencer with */
+/* additional options. */
+#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels ADC channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
+#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
+#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
+#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
+#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
+#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
+#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
+#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
+#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times ADC sampling times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank ADC rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
+#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
+#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
+#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
+#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
+#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
+#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
+#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
+#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
+#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
+#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
+#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
+#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
+#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
+#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
+#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC conversion group
+ * @{
+ */
+#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
+#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
+
+#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
+#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
+#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
+#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
+#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/** @defgroup ADC_conversion_cycles ADC conversion cycles
+ * @{
+ */
+/* ADC conversion cycles (unit: ADC clock cycles) */
+/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
+/* resolution 12 bits) */
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
+ * @{
+ */
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
+ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
+ ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
+ ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
+ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
+ ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
+ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
+ ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
+ ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
+ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
+ ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
+ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
+ ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
+ ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
+ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
+ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+/**
+ * @}
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/**
+ * @brief Enable the ADC peripheral
+ * @note ADC enable requires a delay for ADC stabilization time
+ * (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
+ * SW start on regular group.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__)))
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set ADC number of conversions into regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length
+ * @retval None
+ */
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
+ (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13)))
+
+/**
+ * @brief Set the injected sequence length.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
+ (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL))
+
+/**
+ * @brief Set the selected injected channel rank
+ * Note: on STM32F1 devices, channel rank position in JSQR register
+ * is depending on total number of ranks selected into
+ * injected sequencer (ranks sequence starting from 4-JL)
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
+ ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
+ ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
+ (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_: Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
+/* is equivalent to ADC_SCAN_ENABLE. */
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
+ (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
+ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
+ )
+
+/**
+ * @brief Get the maximum ADC conversion cycles on all channels.
+ * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
+ * Approximation of sampling time within 4 ranges, returns the highest value:
+ * below 7.5 cycles {1.5 cycle; 7.5 cycles},
+ * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
+ * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
+ * equal to 239.5 cycles
+ * Unit: ADC clock cycles
+ * @param __HANDLE__: ADC handle
+ * @retval ADC conversion cycles on all channels
+ */
+#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
+ \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
+ : \
+ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
+ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
+ )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_16) || \
+ ((CHANNEL) == ADC_CHANNEL_17) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
+
+#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_10) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_11) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_12) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_13) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_14) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_15) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_16) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
+ ((CONVERSION) == ADC_INJECTED_GROUP) || \
+ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
+
+
+/** @defgroup ADC_range_verification ADC range verification
+ * For a unique ADC resolution: 12 bits
+ * @{
+ */
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f1xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
+
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Internal HAL driver functions **********************************************/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
+void ADC_StabilizationTime(uint32_t DelayUs);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.c
new file mode 100644
index 000000000..6608a6aef
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.c
@@ -0,0 +1,1300 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of injected
+ * group, using 2 possible modes: polling, interruption.
+ * ++ Multimode feature (available on devices with 2 ADCs or more)
+ * ++ Calibration (ADC automatic self-calibration)
+ * + Control functions
+ * ++ Channels configuration on injected group
+ * Other functions (generic functions) are available in file
+ * "stm32f1xx_hal_adc.c".
+ *
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32f1xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+ /* Delay for ADC calibration: */
+ /* Hardware prerequisite before starting a calibration: the ADC must have */
+ /* been in power-on state for at least two ADC clock cycles. */
+ /* Unit: ADC clock cycles */
+ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
+
+ /* Timeout value for ADC calibration */
+ /* Value defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
+ * @brief Extended Extended Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of injected group.
+ (+) Stop conversion of injected group.
+ (+) Poll for conversion complete on injected group.
+ (+) Get result of injected channel conversion.
+ (+) Start conversion of injected group and enable interruptions.
+ (+) Stop conversion of injected group and disable interruptions.
+
+ (+) Start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * During calibration process, ADC is enabled. ADC is let enabled at
+ * the completion of this function.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Calibration prerequisite: */
+ /* - ADC must be disabled for at least two ADC clock cycles in disable */
+ /* mode before ADC enable */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Hardware prerequisite: delay before starting the calibration. */
+ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
+ /* - Wait for the expected ADC clock cycles delay */
+ wait_loop_index = ((SystemCoreClock
+ / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
+ * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
+
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+
+ /* 2. Enable the ADC peripheral */
+ ADC_Enable(hadc);
+
+
+ /* 3. Resets ADC calibration registers */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration reset completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+
+ /* 4. Start ADC calibration */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of injected group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Check if a regular conversion is ongoing */
+ if(hadc->State == HAL_ADC_STATE_BUSY_REG)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable conversion of injected group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ /* Case of multimode enabled (for devices with several ADCs): if ADC is */
+ /* slave, ADC is enabled only (conversion is not started). If ADC is */
+ /* master, ADC is enabled and conversion is started. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
+ {
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
+ (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Variables for polling in case of scan mode enabled and polling for each */
+ /* conversion. */
+ __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* For injected group, flag JEOC is set only at the end of the sequence, */
+ /* not for each conversion within the sequence. */
+ /* - If single conversion for injected group (scan mode disabled or */
+ /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for injected group (scan mode enabled and */
+ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
+ /* sequence. */
+ /* To poll for each conversion, the maximum conversion time is computed */
+ /* from ADC conversion time (selected sampling time + conversion time of */
+ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
+ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
+ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Poll with maximum conversion time */
+ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
+ /* and ADC maximum conversion cycles on all channels. */
+ /* - Wait for the expected ADC clock cycles delay */
+ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
+ / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
+ * ADC_CONVCYCLES_MAX_RANGE(hadc) );
+
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ hadc->State = HAL_ADC_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+ /* Clear injected group conversion flag (and regular conversion flag raised */
+ /* simultaneously) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
+
+ /* Update state machine on conversion status if not in error state */
+ if(hadc->State != HAL_ADC_STATE_ERROR)
+ {
+ /* Update ADC state machine */
+ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
+ {
+
+ if(hadc->State == HAL_ADC_STATE_EOC_REG)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_EOC_INJ;
+ }
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of injected group with interruption.
+ * - JEOC (end of conversion of injected group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Check if a regular conversion is ongoing */
+ if(hadc->State == HAL_ADC_STATE_BUSY_REG)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Start conversion of injected group if software start has been selected */
+ /* and if automatic injected conversion is disabled. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
+ {
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
+ (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * Each of these interruptions has its dedicated callback function.
+ * @note: On STM32F1 devices, ADC slave regular group must be configured
+ * with conversion trigger ADC_SOFTWARE_START.
+ * @note: ADC slave can be enabled preliminarily using single-mode
+ * HAL_ADC_Start() function.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ /* On STM32F1 devices, ADC slave regular group must be configured with */
+ /* conversion trigger ADC_SOFTWARE_START. */
+ /* Note: External trigger of ADC slave must be enabled, it is already done */
+ /* into function "HAL_ADC_Init()". */
+ if ((tmphadcSlave.Instance == NULL) ||
+ (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) )
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ }
+
+ /* Start conversion all ADCs of multimode are effectively enabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* State machine update (ADC master): Check if an injected conversion is */
+ /* ongoing. */
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
+ }
+ else
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_BUSY_REG;
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC DMA mode of ADC master */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Start conversion of regular group if software start has been selected. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note Multimode is kept enabled after this function. To disable multimode
+ * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC master peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable ADC slave peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable ADC DMA mode */
+ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
+
+ /* Reset configuration of ADC DMA continuous request for dual mode */
+ CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Change ADC state (ADC master) */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @param hadc: ADC handle
+ * @param InjectedRank: the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval None
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Clear injected group conversion flag to have similar behaviour as */
+ /* regular group: reading data register also clears end of conversion flag. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Get ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/**
+ * @brief Returns the last ADC Master&Slave regular conversions results data
+ * in the selected multi mode.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval The converted data value.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tmpDR = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */
+ /* only if ADC1 DMA mode is enabled. */
+ tmpDR = hadc->Instance->DR;
+
+ if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
+ {
+ tmpDR |= (ADC2->DR << 16);
+ }
+
+ /* Return ADC converted value */
+ return tmpDR;
+}
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Injected conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on injected group
+ (+) Configure multimode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the ADC injected group and the selected channel to be
+ * linked to the injected group.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * this function must be called when ADC is not under conversion.
+ * @param hadc: ADC handle
+ * @param sConfigInjected: Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* - if scan mode is disabled, injected channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, injected channels sequence length is set to */
+ /* parameter "InjectedNbrOfConversion". */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Clear the old SQx bits for all injected ranks */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 ,
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ ADC_INJECTED_RANK_1,
+ 0x01) );
+ }
+ /* If another injected rank than rank1 was intended to be set, and could */
+ /* not due to ScanConvMode disabled, error is reported. */
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Since injected channels rank conv. order depends on total number of */
+ /* injected conversions, selected rank must be below or equal to total */
+ /* number of injected conversions to be updated. */
+ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
+ {
+ /* Clear the old SQx bits for the selected rank */
+ /* Set the SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) );
+ }
+ else
+ {
+ /* Clear the old SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ 0x00000000 );
+ }
+ }
+
+ /* Configuration of injected group */
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - external trigger to start conversion */
+ /* Parameters update not conditioned to ADC state: */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+ /* Note: In case of ADC already enabled, caution to not launch an unwanted */
+ /* conversion while modifying register CR2 by writing 1 to bit ADON. */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ MODIFY_REG(hadc->Instance->CR2 ,
+ ADC_CR2_JEXTSEL |
+ ADC_CR2_ADON ,
+ ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
+ }
+
+
+ /* Configuration of injected group */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+
+ /* Automatic injected conversion can be enabled if injected group */
+ /* external triggers are disabled. */
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Injected discontinuous can be enabled only if auto-injected mode is */
+ /* disabled. */
+ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+ {
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* InjectedChannel sampling time configuration */
+ /* For channels 10 to 17 */
+ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+ else /* For channels 0 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+
+ /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+ }
+
+
+ /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
+ switch(sConfigInjected->InjectedRank)
+ {
+ case 1:
+ /* Set injected channel 1 offset */
+ MODIFY_REG(hadc->Instance->JOFR1,
+ ADC_JOFR1_JOFFSET1,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 2:
+ /* Set injected channel 2 offset */
+ MODIFY_REG(hadc->Instance->JOFR2,
+ ADC_JOFR2_JOFFSET2,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 3:
+ /* Set injected channel 3 offset */
+ MODIFY_REG(hadc->Instance->JOFR3,
+ ADC_JOFR3_JOFFSET3,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 4:
+ default:
+ MODIFY_REG(hadc->Instance->JOFR4,
+ ADC_JOFR4_JOFFSET4,
+ sConfigInjected->InjectedOffset);
+ break;
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
+ {
+ /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
+ /* measurement channels (VrefInt/TempSensor). If these channels are */
+ /* intended to be set on other ADC instances, an error is reported. */
+ if (hadc->Instance == ADC1)
+ {
+ if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
+ * the ADCs (both ADCs of the common group).
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To change back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc: ADC handle
+ * @param multimode: Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MODE(multimode->Mode));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - ADC master and ADC slave DMA configuration */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* To optimize code, all multimode settings can be set when both ADCs of */
+ /* the common group are in state: disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ (ADC_IS_ENABLE(&tmphadcSlave) == RESET) &&
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) )
+ {
+ MODIFY_REG(hadc->Instance->CR1,
+ ADC_CR1_DUALMOD ,
+ multimode->Mode );
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ hadc->State = HAL_ADC_STATE_ERROR;
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.h
new file mode 100644
index 000000000..2ca34cf6b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.h
@@ -0,0 +1,703 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of ADC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_EX_H
+#define __STM32F1xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
+ * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+ Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+ Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
+ It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
+ Refer to errata sheet of these devices for more details. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
+ * State of ADCs of the common group must be: disabled.
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADCEx_Common_mode
+ Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
+ Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
+ Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
+ Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
+ The equivalences are:
+ - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
+ - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
+
+
+}ADC_MultiModeTypeDef;
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target, sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/*!< External triggers of regular group for ADC3 only */
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of regular group for all ADC instances */
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
+
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+/* To use it on ADC or ADC2, a rempap of trigger must be done from */
+/* EXTI line 11 to TIM8_TRGO with macro: */
+/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
+/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
+
+/* Note for internal constant value management: If TIM8_TRGO is available, */
+/* its definition is set to value for ADC1&ADC2 by default and changed to */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target, sorted by trigger name: */
+
+/*!< External triggers of injected group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/*!< External triggers of injected group for ADC3 only */
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of injected group for all ADC instances */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
+
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+/* To use it on ADC or ADC2, a rempap of trigger must be done from */
+/* EXTI line 11 to TIM8_TRGO with macro: */
+/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
+/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
+
+/* Note for internal constant value management: If TIM8_CC4 is available, */
+/* its definition is set to value for ADC1&ADC2 by default and changed to */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
+/**
+ * @}
+ */
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode */
+#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode only */
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode only */
+#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode only (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode only (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode only */
+/**
+ * @}
+ */
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
+/* instance is availble on the selected device). */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t) 0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/* External triggers of regular group for ADC3 */
+#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
+#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
+/* instance is availble on the selected device). */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/* External triggers of injected group for ADC3 */
+#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t) 0x00000000)
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
+#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ * for regular group according to ADC into common group ADC1&ADC2 or
+ * ADC3 (some triggers with same source have different value to
+ * be programmed into ADC EXTSEL bits of CR2 register).
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
+ * @retval External trigger to be programmed into EXTSEL bits of CR2 register
+ */
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
+ (( (((__HANDLE__)->Instance) == ADC3) \
+ )? \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
+ )? \
+ (ADC3_EXTERNALTRIG_T8_TRGO) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ ) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ )
+#else
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
+ (__EXT_TRIG_CONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ * for injected group according to ADC into common group ADC1&ADC2 or
+ * ADC3 (some triggers with same source have different value to
+ * be programmed into ADC JEXTSEL bits of CR2 register).
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
+ * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
+ */
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (( (((__HANDLE__)->Instance) == ADC3) \
+ )? \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
+ )? \
+ (ADC3_EXTERNALTRIGINJEC_T8_CC4) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ ) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ )
+#else
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (__EXT_TRIG_INJECTCONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+
+/**
+ * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
+ */
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ (ADC1->CR1 & ADC_CR1_DUALMOD) \
+ : \
+ (RESET) \
+ )
+#else
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
+ (RESET)
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
+ : \
+ (!RESET) \
+ )
+#else
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/**
+ * @brief Set handle of the other ADC sharing the common multimode settings
+ * @param __HANDLE__: ADC handle
+ * @param __HANDLE_OTHER_ADC__: other ADC handle
+ * @retval None
+ */
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
+
+/**
+ * @brief Set handle of the ADC slave associated to the ADC master
+ * On STM32F1 devices, ADC slave is always ADC2 (this can be different
+ * on other STM32 devices)
+ * @param __HANDLE_MASTER__: ADC master handle
+ * @param __HANDLE_SLAVE__: ADC slave handle
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ((__HANDLE_SLAVE__)->Instance = ADC2)
+
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_2) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_3) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_4) )
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
+
+/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) \
+ (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif
+#if defined (STM32F101xE) || defined (STM32F101xG)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ \
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif
+#if defined (STM32F101xE) || defined (STM32F101xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ \
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ \
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERLFAST) || \
+ ((MODE) == ADC_DUALMODE_INTERLSLOW) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) )
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+
+
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.c
new file mode 100644
index 000000000..7b9e62a0e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.c
@@ -0,0 +1,1416 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_can.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (++) Connect and configure the involved CAN pins using the
+ following function HAL_GPIO_Init();
+
+ (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10
+
+#define CAN_TI0R_STID_BIT_POSITION ((uint32_t)21) /* Position of LSB bits STID in register CAN_TI0R */
+#define CAN_TI0R_EXID_BIT_POSITION ((uint32_t) 3) /* Position of LSB bits EXID in register CAN_TI0R */
+#define CAN_TDL0R_DATA0_BIT_POSITION ((uint32_t) 0) /* Position of LSB bits DATA0 in register CAN_TDL0R */
+#define CAN_TDL0R_DATA1_BIT_POSITION ((uint32_t) 8) /* Position of LSB bits DATA1 in register CAN_TDL0R */
+#define CAN_TDL0R_DATA2_BIT_POSITION ((uint32_t)16) /* Position of LSB bits DATA2 in register CAN_TDL0R */
+#define CAN_TDL0R_DATA3_BIT_POSITION ((uint32_t)24) /* Position of LSB bits DATA3 in register CAN_TDL0R */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
+ uint32_t tickstart = 0;
+ uint32_t tmp_mcr = 0;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan-> Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_ABOM);
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_AWUM);
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_NART);
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_RFLM);
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ SET_BIT(tmp_mcr, CAN_MCR_TXFP);
+ }
+
+ /* Update register MCR */
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_TTCM |
+ CAN_MCR_ABOM |
+ CAN_MCR_AWUM |
+ CAN_MCR_NART |
+ CAN_MCR_RFLM |
+ CAN_MCR_TXFP,
+ tmp_mcr);
+
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SJW |
+ hcan->Init.BS1 |
+ hcan->Init.BS2 |
+ (hcan->Init.Prescaler - 1) ));
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ {
+ status = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(status == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+
+ /* Initialisation mode for the filter */
+ /* Select the start slave bank */
+ MODIFY_REG(hcan->Instance->FMR ,
+ CAN_FMR_CAN2SB ,
+ CAN_FMR_FINIT |
+ (uint32_t)(sFilterConfig->BankNumber << 8) );
+
+ /* Filter Deactivation */
+ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
+ /* 32-bit identifier or First 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = 0;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = 1;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
+ {
+ transmitmailbox = 2;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ }
+
+ if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = 0;
+ }
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = 1;
+ }
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
+ {
+ transmitmailbox = 2;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ }
+
+ if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO Number value
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_INRQ ,
+ CAN_MCR_SLEEP );
+
+ /* Sleep mode status */
+ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ }
+
+ /* Check End of reception flag for FIFO0 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ /* Check End of reception flag for FIFO1 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Check Error Warning Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-Off Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ /* No need for clear of Bus-Off Flag as read-only */
+ }
+
+ /* Check Last error code Flag */
+ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Disable CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
+ /* STM32F103xG) || STM32F105xC || STM32F107xC */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.h
new file mode 100644
index 000000000..b6beb5613
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.h
@@ -0,0 +1,825 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_can.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __stm32f1xx_CAN_H
+#define __stm32f1xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint32_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be a value of @ref CAN_receive_FIFO_number_constants */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code */
+
+}CAN_HandleTypeDef;
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+
+
+#define HAL_CAN_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_CAN_ERROR_EWG ((uint32_t)0x01) /*!< EWG error */
+#define HAL_CAN_ERROR_EPV ((uint32_t)0x02) /*!< EPV error */
+#define HAL_CAN_ERROR_BOF ((uint32_t)0x04) /*!< BOF error */
+#define HAL_CAN_ERROR_STF ((uint32_t)0x08) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR ((uint32_t)0x10) /*!< Form error */
+#define HAL_CAN_ERROR_ACK ((uint32_t)0x20) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR ((uint32_t)0x40) /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD ((uint32_t)0x80) /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC ((uint32_t)0x100) /*!< LEC transfer error */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_InitStatus CAN initialization Status
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants CAN Transmit Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
+#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
+#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
+#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+
+/* CAN intermediate shift values used for CAN flags */
+#define TSR_REGISTER_INDEX ((uint32_t)0x5)
+#define RF0R_REGISTER_INDEX ((uint32_t)0x2)
+#define RF1R_REGISTER_INDEX ((uint32_t)0x4)
+#define MSR_REGISTER_INDEX ((uint32_t)0x1)
+#define ESR_REGISTER_INDEX ((uint32_t)0x3)
+
+/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
+/* Transmit Flags */
+#define CAN_TSR_RQCP0_BIT_POSITION ((uint32_t)0x00000000)
+#define CAN_TSR_RQCP1_BIT_POSITION ((uint32_t)0x00000008)
+#define CAN_TSR_RQCP2_BIT_POSITION ((uint32_t)0x00000010)
+#define CAN_TSR_TXOK0_BIT_POSITION ((uint32_t)0x00000001)
+#define CAN_TSR_TXOK1_BIT_POSITION ((uint32_t)0x00000009)
+#define CAN_TSR_TXOK2_BIT_POSITION ((uint32_t)0x00000011)
+#define CAN_TSR_TME0_BIT_POSITION ((uint32_t)0x0000001A)
+#define CAN_TSR_TME1_BIT_POSITION ((uint32_t)0x0000001B)
+#define CAN_TSR_TME2_BIT_POSITION ((uint32_t)0x0000001C)
+
+/* Receive Flags */
+#define CAN_RF0R_FF0_BIT_POSITION ((uint32_t)0x00000003)
+#define CAN_RF0R_FOV0_BIT_POSITION ((uint32_t)0x00000004)
+
+#define CAN_RF1R_FF1_BIT_POSITION ((uint32_t)0x00000003)
+#define CAN_RF1R_FOV1_BIT_POSITION ((uint32_t)0x00000004)
+
+/* Operating Mode Flags */
+#define CAN_MSR_WKU_BIT_POSITION ((uint32_t)0x00000003)
+#define CAN_MSR_SLAK_BIT_POSITION ((uint32_t)0x00000001)
+#define CAN_MSR_SLAKI_BIT_POSITION ((uint32_t)0x00000004)
+
+/* Error Flags */
+#define CAN_ESR_EWG_BIT_POSITION ((uint32_t)0x00000000)
+#define CAN_ESR_EPV_BIT_POSITION ((uint32_t)0x00000001)
+#define CAN_ESR_BOF_BIT_POSITION ((uint32_t)0x00000002)
+
+/* Mask used by macro to get/clear CAN flags*/
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macro CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
+ * @arg CAN_IT_FF0 : FIFO 0 full interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
+ * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
+ * @arg CAN_IT_FF1 : FIFO 1 full interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
+ * @arg CAN_IT_WKU : Wake-up interrupt
+ * @arg CAN_IT_SLK : Sleep acknowledge interrupt
+ * @arg CAN_IT_EWG : Error warning interrupt
+ * @arg CAN_IT_EPV : Error passive interrupt
+ * @arg CAN_IT_BOF : Bus-off interrupt
+ * @arg CAN_IT_LEC : Last error code interrupt
+ * @arg CAN_IT_ERR : Error Interrupt
+ * @retval None.
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
+ * @arg CAN_IT_FF0 : FIFO 0 full interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
+ * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
+ * @arg CAN_IT_FF1 : FIFO 1 full interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
+ * @arg CAN_IT_WKU : Wake-up interrupt
+ * @arg CAN_IT_SLK : Sleep acknowledge interrupt
+ * @arg CAN_IT_EWG : Error warning interrupt
+ * @arg CAN_IT_EPV : Error passive interrupt
+ * @arg CAN_IT_BOF : Bus-off interrupt
+ * @arg CAN_IT_LEC : Last error code interrupt
+ * @arg CAN_IT_ERR : Error Interrupt
+ * @retval None.
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
+ * @arg CAN_IT_FF0 : FIFO 0 full interrupt
+ * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
+ * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
+ * @arg CAN_IT_FF1 : FIFO 1 full interrupt
+ * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
+ * @arg CAN_IT_WKU : Wake-up interrupt
+ * @arg CAN_IT_SLK : Sleep acknowledge interrupt
+ * @arg CAN_IT_EWG : Error warning interrupt
+ * @arg CAN_IT_EPV : Error passive interrupt
+ * @arg CAN_IT_BOF : Bus-off interrupt
+ * @arg CAN_IT_LEC : Last error code interrupt
+ * @arg CAN_IT_ERR : Error Interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None.
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval None.
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disables the DBG Freeze for CAN.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/* Include CAN HAL Extension module */
+#include "stm32f1xx_hal_can_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @brief I/O operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
+ /* STM32F103xG) || STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __stm32f1xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can_ex.h
new file mode 100644
index 000000000..55a53d657
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can_ex.h
@@ -0,0 +1,147 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_can_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of CAN HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CAN_EX_H
+#define __STM32F1xx_HAL_CAN_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CANEx CANEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+/* CAN filter banks differences over STM32F1 devices: */
+/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
+/* - Other STM32F10x devices: 14 filter banks */
+
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+#else
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
+#endif /* STM32F105xC || STM32F107xC */
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
+
+}CAN_FilterConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
+ * @{
+ */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#else
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
+ /* STM32F103xG) || STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CAN_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.c
new file mode 100644
index 000000000..eda05bfed
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.c
@@ -0,0 +1,1034 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cec.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief CEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CEC HAL driver can be used as follows:
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (##) Enable the CEC interface clock.
+ (##) Enable the clock for the CEC GPIOs.
+ (##) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (##) Configure the CEC interrupt priority.
+ (##) Enable the NVIC CEC IRQ handle.
+ (##) The CEC interrupt is activated/deactivated by the HAL driver
+
+ (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+ (#) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_CEC_MspInit() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+#define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM )
+#define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF)
+#define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF)
+#define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
+#define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) TimingErrorFree
+ (++) PeriodErrorFree
+ (++) InitiatorAddress
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+
+ if(hcec->State == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec-> Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Write to CEC Control Register */
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree|hcec->Init.PeriodErrorFree);
+
+ /* Write to CEC Own Address Register */
+ MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.InitiatorAddress);
+
+ /* Configure the prescaler to generate the required 50 microseconds time base.*/
+ MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50*(HAL_RCC_GetPCLK1Freq()/1000000)-1);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->State = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec: CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Set peripheral to reset state */
+ hcec->Instance->CFGR = 0x0;
+ hcec->Instance->OAR = 0x0;
+ hcec->Instance->PRES = 0x0;
+ hcec->Instance->CFGR = 0x0;
+ hcec->Instance->ESR = 0x0;
+ hcec->Instance->CSR = 0x0;
+ hcec->Instance->TXD = 0x0;
+ hcec->Instance->RXD = 0x0;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->State = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) No-Blocking mode: The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the Transmit or Receive process.
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+ (#) Blocking mode API's are :
+ (##) HAL_CEC_Transmit()
+ (##) HAL_CEC_Receive()
+ (#) Non-Blocking mode API's with Interrupt are :
+ (##) HAL_CEC_Transmit_IT()
+ (##) HAL_CEC_Receive_IT()
+ (##) HAL_CEC_IRQHandler()
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (##) HAL_CEC_TxCpltCallback()
+ (##) HAL_CEC_RxCpltCallback()
+ (##) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in blocking mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint8_t temp = 0;
+ uint32_t tickstart = 0;
+
+ /* If the IP is ready */
+ if((hcec->State == HAL_CEC_STATE_READY)
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ /* Basic check on pData pointer */
+ if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size)))
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ /* Enter the transmit mode */
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* Send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXD = temp;
+
+ /* In case no data to be sent, sender is only pinging the system */
+ if (Size != 0)
+ {
+ /* Set TX Start of Message (TXSOM) bit */
+ hcec->Instance->CSR = CEC_FLAG_TSOM;
+ }
+ else
+ {
+ /* Send a ping command */
+ hcec->Instance->CSR = CEC_FLAG_TEOM|CEC_FLAG_TSOM;
+ }
+
+ /* Polling TBTRF bit with timeout handling*/
+ while (hcec->TxXferCount > 0)
+ {
+ /* Decreasing of the number of remaining data to receive */
+ hcec->TxXferCount--;
+
+ /* Timeout handling */
+ tickstart = HAL_GetTick();
+
+ /* Waiting for the next data transmission */
+ while(HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF))
+ {
+ /* Timeout handling */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if an error occured */
+ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
+ {
+ /* Copy ESR for error handling purposes */
+ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
+
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+
+ /* Write the next data to TX buffer */
+ hcec->Instance->TXD = *pData++;
+
+ /* If this is the last byte of the ongoing transmission */
+ if (hcec->TxXferCount == 0)
+ {
+ /* Acknowledge byte request and signal end of message */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
+ }
+ else
+ {
+ /* Acknowledge byte request by writing 0x00 */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+ }
+ }
+
+ /* Timeout handling */
+ tickstart = HAL_GetTick();
+
+ /* Wait for message transmission completion (TBTRF is set) */
+ while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF))
+ {
+ /* Timeout handling */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check of error during transmission of the last byte */
+ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
+ {
+ /* Copy ESR for error handling purposes */
+ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
+
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check of error after the last byte transmission */
+ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
+ {
+ /* Copy ESR for error handling purposes */
+ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
+
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+
+ /* Acknowledge successful completion by writing 0x00 */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in blocking mode.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @param Timeout: Timeout duration.
+ * @note The received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
+{
+ uint32_t temp = 0;
+ uint32_t tickstart = 0;
+
+ if(hcec->State == HAL_CEC_STATE_READY)
+ {
+ if(pData == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* When a ping is received, RxXferSize is 0*/
+ /* When a message is received, RxXferSize contains the number of received bytes */
+ hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE;
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Continue the reception until the End Of Message is received (CEC_FLAG_REOM) */
+ do
+ {
+ /* Timeout handling */
+ tickstart = HAL_GetTick();
+
+ /* Wait for next byte to be received */
+ while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_RBTF))
+ {
+ /* Timeout handling */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if an error occured during the reception */
+ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
+ {
+ /* Copy ESR for error handling purposes */
+ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
+
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+
+ /* Keep the value of CSR register as the register is cleared during reception process */
+ temp = hcec->Instance->CSR;
+
+ /* Read received data */
+ *pData++ = hcec->Instance->RXD;
+
+ /* Acknowledge received byte by writing 0x00 */
+ CLEAR_BIT(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK);
+
+ /* Increment the number of received data */
+ if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE)
+ {
+ hcec->RxXferSize = 0;
+ }
+ else
+ {
+ hcec->RxXferSize++;
+ }
+
+ }while (HAL_IS_BIT_CLR(temp, CEC_FLAG_REOM));
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ if(IS_CEC_MSGSIZE(hcec->RxXferSize))
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ uint8_t temp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hcec->State;
+ if(((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_RX))
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+
+ /* Basic check on pData pointer */
+ if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size)))
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+
+ /* Check if a receive process is ongoing or not */
+ if(hcec->State == HAL_CEC_STATE_BUSY_RX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX_RX;
+
+ /* Interrupt are not enabled here because they are already enabled in the Reception process */
+ }
+ else
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+
+ /* Enable the CEC interrupt */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
+ }
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXD = temp;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* case no data to be sent, sender is only pinging the system */
+ if (Size != 0)
+ {
+ /* Set TX Start of Message (TXSOM) bit */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM);
+ }
+ else
+ {
+ /* Send a ping command */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @note The received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
+{
+ uint32_t tmp_state = 0;
+ tmp_state = hcec->State;
+ if((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_TX))
+ {
+ if(pData == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* When a ping is received, RxXferSize is 0 */
+ /* When a message is received, RxXferSize contains the number of received bytes */
+ hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE;
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->pRxBuffPtr = pData;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Check if a transmit process is ongoing or not */
+ if(hcec->State == HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+
+ /* Enable CEC interrupt */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec: CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec: CEC handle
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+ /* Save error status register for further error handling purposes */
+ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
+
+ /* Transmit error */
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET))
+ {
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
+
+ /* Check if a receive process is ongoing or not */
+ if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
+ {
+ /* Interrupts are not disabled due to reception still ongoing */
+
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+ }
+
+ /* Receive error */
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET))
+ {
+ /* Acknowledgement of the error */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
+
+ /* Check if a transmit process is ongoing or not */
+ if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
+ {
+ /* Interrupts are not disabled due to reception still ongoing */
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+ }
+
+ if ((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0)
+ {
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+ /* Transmit byte request or block transfer finished */
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET))
+ {
+ CEC_Transmit_IT(hcec);
+ }
+
+ /* Receive byte or block transfer finished */
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET))
+ {
+ CEC_Receive_IT(hcec);
+ }
+}
+
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC error callbacks
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to get the error code of a failed transmission or reception.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CEC state
+ * @param hcec: CEC handle
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ return hcec->State;
+}
+
+/**
+* @brief Return the CEC error code
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+* @retval CEC Error Code
+*/
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Private_Functions
+ * @{
+ */
+
+ /**
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hcec->State;
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ if(((tmp_state == HAL_CEC_STATE_BUSY_TX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX))
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Acknowledge successful completion by writing 0x00 */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+
+ /* Check if a receive process is ongoing or not */
+ if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
+ {
+ /* Interrupts are not disabled due to reception still ongoing */
+
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Reduce the number of bytes to transfer by one */
+ hcec->TxXferCount--;
+
+ /* Write data to TX buffer*/
+ hcec->Instance->TXD = *hcec->pTxBuffPtr++;
+
+ /* If this is the last byte of the ongoing transmission */
+ if (hcec->TxXferCount == 0)
+ {
+ /* Acknowledge byte request and signal end of message */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
+ }
+ else
+ {
+ /* Acknowledge byte request by writing 0x00 */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+ }
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
+{
+ static uint32_t temp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hcec->State;
+ if((tmp_state == HAL_CEC_STATE_BUSY_RX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX))
+ {
+ temp = hcec->Instance->CSR;
+
+ /* Store received data */
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXD;
+
+ /* Acknowledge received byte by writing 0x00 */
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00);
+
+ /* Increment the number of received data */
+ if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE)
+ {
+ hcec->RxXferSize = 0;
+ }
+ else
+ {
+ hcec->RxXferSize++;
+ }
+
+ /* If the End Of Message is reached */
+ if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
+ {
+ if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
+ {
+ /* Interrupts are not disabled due to transmission still ongoing */
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+
+ HAL_CEC_RxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.h
new file mode 100644
index 000000000..85fbd81e0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.h
@@ -0,0 +1,411 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cec.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CEC_H
+#define __STM32F1xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+/** @addtogroup CEC_Private_Constants
+ * @{
+ */
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
+ ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
+ ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
+ This parameter can be a value of @ref CEC_BitTimingErrorMode */
+ uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
+ This parameter can be a value of @ref CEC_BitPeriodErrorMode */
+ uint8_t InitiatorAddress; /*!< Initiator address (source logical address, sent in each header)
+ This parameter can be a value <= 0xF */
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_CEC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_CEC_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief HAL Error structures definition
+ */
+typedef enum
+{
+ HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
+ HAL_CEC_ERROR_BTE = CEC_ESR_BTE, /*!< Bit Timing Error */
+ HAL_CEC_ERROR_BPE = CEC_ESR_BPE, /*!< Bit Period Error */
+ HAL_CEC_ERROR_RBTFE = CEC_ESR_RBTFE, /*!< Rx Block Transfer Finished Error */
+ HAL_CEC_ERROR_SBE = CEC_ESR_SBE, /*!< Start Bit Error */
+ HAL_CEC_ERROR_ACKE = CEC_ESR_ACKE, /*!< Block Acknowledge Error */
+ HAL_CEC_ERROR_LINE = CEC_ESR_LINE, /*!< Line Error */
+ HAL_CEC_ERROR_TBTFE = CEC_ESR_TBTFE, /*!< Tx Block Transfer Finished Error */
+}HAL_CEC_ErrorTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
+
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ESR register in case error is reported */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_CEC_StateTypeDef State; /*!< CEC communication state */
+
+}CEC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
+ * @{
+ */
+#define CEC_BIT_TIMING_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
+ * @{
+ */
+#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
+/**
+ * @}
+ */
+/** @defgroup CEC_Interrupts_Definitions Interrupts definition
+ * @{
+ */
+#define CEC_IT_IE CEC_CFGR_IE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions Flags definition
+ * @{
+ */
+#define CEC_FLAG_TSOM CEC_CSR_TSOM
+#define CEC_FLAG_TEOM CEC_CSR_TEOM
+#define CEC_FLAG_TERR CEC_CSR_TERR
+#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
+#define CEC_FLAG_RSOM CEC_CSR_RSOM
+#define CEC_FLAG_REOM CEC_CSR_REOM
+#define CEC_FLAG_RERR CEC_CSR_RERR
+#define CEC_FLAG_RBTF CEC_CSR_RBTF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle state
+ * @param __HANDLE__: CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * @arg CEC_FLAG_TERR: Tx Error
+ * @arg CEC_FLAG_TBTF: Tx Block Transfer Finished
+ * @arg CEC_FLAG_RERR: Rx Error
+ * @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
+ * @retval ITStatus
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CSR,(__INTERRUPT__))
+
+/** @brief Clears the CEC's pending flags.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg CEC_CSR_TERR: Tx Error
+ * @arg CEC_CSR_TBTF: Tx Block Transfer Finished
+ * @arg CEC_CSR_RERR: Rx Error
+ * @arg CEC_CSR_RBTF: Rx Block Transfer Finished
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ do { \
+ uint32_t tmp = 0x0; \
+ tmp = (__HANDLE__)->Instance->CSR & 0x2; \
+ (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFC) | tmp);\
+ } while(0)
+
+/** @brief Enables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: The CEC interrupt to enable.
+ * This parameter can be:
+ * @arg CEC_IT_IE : Interrupt Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief Disables the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: The CEC interrupt to enable.
+ * This parameter can be:
+ * @arg CEC_IT_IE : Interrupt Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: The CEC interrupt to enable.
+ * This parameter can be:
+ * @arg CEC_IT_IE : Interrupt Enable
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief Enables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
+
+/** @brief Disables the CEC device
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
+
+/** @brief Set Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
+
+/** @brief Set Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
+
+/** @brief Get Transmission Start flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
+
+/** @brief Get Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
+
+/** @brief Clear OAR register
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
+
+/** @brief Set OAR register
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __ADDRESS__: Own Address value.
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief CEC control functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h
new file mode 100644
index 000000000..7543c3cb1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h
@@ -0,0 +1,367 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f1xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CONF_H
+#define __STM32F1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#if defined(USE_STM3210C_EVAL)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#else
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/*#define USE_FULL_ASSERT 1*/
+
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f1xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c
new file mode 100644
index 000000000..3e32b268f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c
@@ -0,0 +1,448 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cortex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief CORTEX HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using Cortex HAL driver ***
+ ===========================================================
+ [..]
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M3 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+ ==========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ==========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ==========================================================================================================================
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using Cortex HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for 1 msec interrupts.
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f1xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provide the Cortex HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.h
new file mode 100644
index 000000000..f8db956cb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.h
@@ -0,0 +1,222 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CORTEX_H
+#define __STM32F1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+ * @{
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source
+ * @{
+ */
+
+/** @brief Configures the SysTick clock source.
+ * @param __CLKSRC__: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
+ do { \
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
+ { \
+ SET_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); \
+ } \
+ else \
+ CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); \
+ } while(0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
+ * @{
+ */
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.c
new file mode 100644
index 000000000..e71cf4243
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.c
@@ -0,0 +1,341 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_crc.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRC HAL driver can be used as follows:
+
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+
+ (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
+ a 32-bit data buffer using combination of the previous CRC value
+ and the new one.
+
+ (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
+ a new 32-bit data buffer. This function resets the CRC computation
+ unit before starting the computation to avoid getting wrong CRC values.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP
+ (+) DeInitialize CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and creates the associated handle.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRC peripheral.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CRC MSP.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Compute the 32-bit CRC value of 32-bit data buffer,
+ using combination of the previous CRC value and the new one.
+ (+) Compute the 32-bit CRC value of 32-bit data buffer,
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Computes the 32-bit CRC of 32-bit data buffer using combination
+ * of the previous CRC value and the new one.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed (defined in word, 4 bytes)
+ * @retval 32-bit CRC
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Enter Data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of 32-bit data buffer independently
+ * of the previous CRC value.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @param pBuffer: Pointer to the buffer containing the data to be computed
+ * @param BufferLength: Length of the buffer to be computed (defined in word, 4 bytes)
+ * @retval 32-bit CRC
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Enter Data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRC state.
+ * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
+ * the configuration information for CRC
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.h
new file mode 100644
index 000000000..9afa6174b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.h
@@ -0,0 +1,195 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CRC_H
+#define __STM32F1xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+
+}HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< CRC locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+}CRC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Resets CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @param __VALUE__: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group3
+ ** @{
+ */
+
+/* Peripheral State functions **************************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.c
new file mode 100644
index 000000000..c1e8b57f1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.c
@@ -0,0 +1,929 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dac.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ The device integrates two 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_PIN_9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
+ For STM32F10x connectivity line devices and STM32F100x devices: TIM3
+ For STM32F10x high-density and XL-density devices: TIM8
+ For STM32F100x high-density value line devices: TIM15 as
+ replacement of TIM5.
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
+
+ (#) Software using DAC_TRIGGER_SOFTWARE
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** DAC connect feature ***
+ ===============================
+ [..]
+ Each DAC channel can be connected internally.
+ To connect, use
+ sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
+
+ *** GPIO configurations guidelines ***
+ =====================
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
+ (ex channel1 on PA5 is configured in Analog and disabled).
+ Channel1 may disturb channel2 as coupling effect.
+ Note that there is no coupling on channel2 as soon as channel2 is turned on.
+ Coupling on adjacent channel could be avoided as follows:
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels can be used to generate
+ (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
+ (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondance ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ [..]
+ DAC_OUTx = VREF+ * DOR / 4095
+ (+) with DOR is the Data Output Register
+ [..]
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ [..]
+ e.g. To set DAC_OUT1 to 0.7V, use
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ HAL_DAC_Start_DMA()
+ [..]
+ DMA requests are mapped as following:
+ (#) DAC channel1 :
+ For STM32F100x low-density, medium-density, high-density with DAC
+ DMA remap:
+ mapped on DMA1 channel3 which must be
+ already configured
+ For STM32F100x high-density without DAC DMA remap and other
+ STM32F1 devices:
+ mapped on DMA2 channel3 which must be
+ already configured
+ (#) DAC channel2 :
+ For STM32F100x low-density, medium-density, high-density with DAC
+ DMA remap:
+ mapped on DMA1 channel4 which must be
+ already configured
+ For STM32F100x high-density without DAC DMA remap and other
+ STM32F1 devices:
+ mapped on DMA2 channel4 which must be
+ already configured
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
+ (+) For STM32F100x devices with specific feature: DMA underrun.
+ In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+ HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdac-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Check if software trigger enabled */
+ if(HAL_IS_BIT_SET(hdac->Instance->CR, (DAC_CR_TEN1 | DAC_CR_TSEL1)))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+ }
+ else
+ {
+ /* Check if software trigger enabled */
+ if(HAL_IS_BIT_SET(hdac->Instance->CR, (DAC_CR_TEN2 | DAC_CR_TSEL2)))
+ {
+ /* Enable the selected DAC software conversion*/
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function enables the interruption of DMA
+ * underrun.
+ * (refer to redefinition of this function in DAC extended file)
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Case of use of channel 2 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA channel */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function disables the interruption of DMA
+ * underrun.
+ * (refer to redefinition of this function in DAC extended file)
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripharal */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ }
+ else /* Channel2 is used for */
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if (status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Returns the DAC channel data output register value */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+ else
+ {
+ return hdac->Instance->DOR2;
+ }
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Configure for the selected DAC channel: buffer output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
+
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ /* Calculate CR register value depending on DAC_Channel */
+ MODIFY_REG(hdac->Instance->CR,
+ ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
+ tmpreg1 << Channel);
+
+ /* Disable wave generation */
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param Alignment: Specifies the data alignment.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)hdac->Instance;
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+ }
+ else
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+ }
+
+ /* Set the DAC channel selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC state
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC state */
+ return hdac->State;
+}
+
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.h
new file mode 100644
index 000000000..bddc4e157
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.h
@@ -0,0 +1,324 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DAC_H
+#define __STM32F1xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DACEx_trigger_selection
+ Note: For STM32F100x high-density value line devices, additional trigger sources are available. */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+}DAC_ChannelConfTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+ * @{
+ */
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement DAC data alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/**
+ * @}
+ */
+
+
+/* Include DAC HAL Extension module */
+#include "stm32f1xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__STM32F1xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.c
new file mode 100644
index 000000000..71e292fdd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.c
@@ -0,0 +1,659 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of DAC extension peripheral:
+ * + Extended features functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DACEx DACEx
+ * @brief DACEx driver module
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0;
+
+ tmp |= hdac->Instance->DOR1;
+
+ tmp |= hdac->Instance->DOR2 << 16;
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude: Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_TRIANGLE | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * DAC_CHANNEL_1 / DAC_CHANNEL_2
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_NOISE | Amplitude) << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)hdac->Instance;
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+ */
+}
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function uses the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel2.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function uses the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+#endif /* STM32F100xB) || defined (STM32F100xE) */
+
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function enables the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Case of use of channel 2 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA channel */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F100xB) || defined (STM32F100xE) */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function disables the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripharal */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+ }
+ else /* Channel2 is used for */
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if(status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+#endif /* STM32F100xB) || defined (STM32F100xE) */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief Handles DAC interrupt request
+ * Note: For STM32F100x devices with specific feature: DMA underrun.
+ * On these devices, this function uses the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1 */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ }
+
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ {
+ /* Check underrun flag of DAC channel 2 */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
+ }
+}
+#endif /* STM32F100xB || STM32F100xE */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Private_Functions DACEx Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.h
new file mode 100644
index 000000000..50da774bd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.h
@@ -0,0 +1,398 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of DAC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DAC_EX_H
+#define __STM32F1xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+ * @{
+ */
+
+/** @defgroup DACEx_wave_generation DACEx wave generation
+ * @{
+ */
+#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_wave_generation DACEx wave generation
+ * @{
+ */
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_trigger_selection DAC trigger selection
+ * @{
+ */
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+/* For STM32F10x high-density and XL-density devices: TIM8 */
+#define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
+/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
+
+/* Availability of trigger from TIM5 and TIM15: */
+/* - For STM32F10x value line devices STM32F100xB: */
+/* trigger from TIM15 is available, TIM5 not available. */
+/* - For STM32F10x value line devices STM32F100xE: */
+/* trigger from TIM15 and TIM5 are both available, */
+/* selection depends on remap (with TIM5 as default configuration). */
+/* - Other STM32F1 devices: */
+/* trigger from TIM5 is available, TIM15 not available. */
+#if defined (STM32F100xB)
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#else
+
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+
+#if defined (STM32F100xE)
+/*!< DAC trigger availability depending on STM32F1 devices:
+ For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
+ as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
+ Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
+ Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
+ For more details please refer to the AFIO section. */
+#define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
+#endif /* STM32F100xE */
+
+#endif /* STM32F100xB */
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/** @defgroup DAC_flags_definition DAC flags definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition DAC IT definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+/**
+ * @}
+ */
+#endif /* STM32F100xB || STM32F100xE */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
+ * @{
+ */
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the FLASH flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+
+/**
+ * @}
+ */
+#endif /* STM32F100xB || STM32F100xE */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+ * @{
+ */
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
+#if defined (STM32F100xB)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F100xB */
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+ ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @{
+ */
+/* Extension features functions ***********************************************/
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+#endif /* STM32F100xB) || defined (STM32F100xE) */
+
+/**
+ * @}
+ */
+
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
+ * @{
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F1xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_def.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_def.h
new file mode 100644
index 000000000..183a794e4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_def.h
@@ -0,0 +1,216 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DEF
+#define __STM32F1xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+#include "stm32_hal_legacy.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c
new file mode 100644
index 000000000..d6ac9c4dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c
@@ -0,0 +1,709 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0;
+
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ if(hdma->State == HAL_DMA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma-> Lock = HAL_UNLOCKED;
+ }
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+ /* Enable the Half transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+ /* Enable the transfer Error interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ *
+ * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
+ * effectively disabled is added. If a Channel is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Channel will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tickstart = 0x00;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA Channel is effectively disabled */
+ while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0x00;
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ {
+ if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ {
+ /* Clear the transfer error flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers of half buffer are complete) */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Transfer Error Interrupt management ***************************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h
new file mode 100644
index 000000000..7760ad730
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h
@@ -0,0 +1,458 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_H
+#define __STM32F1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Configuration enumeration values definition
+ */
+typedef enum
+{
+ DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
+ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
+
+} DMA_ControlTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
+ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Codes DMA Error Codes
+ * @{
+ */
+ #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+ #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
+ #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_buffer_size DMA Data buffer size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32f1xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma_ex.h
new file mode 100644
index 000000000..eb1bbf6fb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma_ex.h
@@ -0,0 +1,257 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of DMA HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_EX_H
+#define __STM32F1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+
+#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
+ defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
+ * @{
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+ (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+ (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else
+
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
+ /* STM32F103xG || STM32F105xC || STM32F107xC */
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c
new file mode 100644
index 000000000..4add72df2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c
@@ -0,0 +1,2000 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_eth.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief ETH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Ethernet (ETH) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:
+ ETH_HandleTypeDef heth;
+
+ (#)Fill parameters of Init structure in heth handle
+
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
+
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+ (##) Enable the Ethernet interface clock using
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure Ethernet pin-out
+ (##) Configure Ethernet NVIC interrupt (IT mode)
+
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process
+
+ (#)Enable MAC and DMA transmission and reception:
+ (##) HAL_ETH_Start();
+
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
+ the frame to MAC TX FIFO:
+ (##) HAL_ETH_TransmitFrame();
+
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received
+ frame parameters
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
+
+ (#) Get a received frame when an ETH RX interrupt occurs:
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
+
+ (#) Communicate with external PHY device:
+ (##) Read a specific register from the PHY
+ HAL_ETH_ReadPHYRegister();
+ (##) Write data to a specific RHY register:
+ HAL_ETH_WritePHYRegister();
+
+ (#) Configure the Ethernet MAC after ETH peripheral initialization
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
+
+ (#) Configure the Ethernet DMA after ETH peripheral initialization
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
+
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported
+ in this driver
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+#if defined (STM32F107xC)
+
+/** @defgroup ETH ETH
+ * @brief ETH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Constants ETH Private Constants
+ * @{
+ */
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
+ * @{
+ */
+
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the Ethernet peripheral
+ (+) De-initialize the Ethernet peripheral
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the Ethernet MAC and DMA according to default
+ * parameters.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+ uint32_t tmpreg = 0, phyreg = 0;
+ uint32_t hclk = 60000000;
+ uint32_t tickstart = 0;
+ uint32_t err = ETH_SUCCESS;
+
+ /* Check the ETH peripheral state */
+ if(heth == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
+
+ if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ heth-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspInit(heth);
+ }
+
+ /* Select MII or RMII Mode*/
+ AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
+ AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface;
+
+ /* Ethernet Software reset */
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+ /* After reset all the registers holds their respective reset values */
+ (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
+
+ /* Wait for software reset */
+ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+ {
+ }
+
+ /*-------------------------------- MAC Initialization ----------------------*/
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = (heth->Instance)->MACMIIAR;
+ /* Clear CSR Clock Range CR[2:0] bits */
+ tmpreg &= ETH_MACMIIAR_CR_MASK;
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ /* Set CR bits depending on hclk value */
+ if((hclk >= 20000000)&&(hclk < 35000000))
+ {
+ /* CSR Clock Range between 20-35 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
+ }
+ else if((hclk >= 35000000)&&(hclk < 60000000))
+ {
+ /* CSR Clock Range between 35-60 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
+ }
+ else
+ {
+ /* CSR Clock Range between 60-72 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
+ }
+
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+
+ /*-------------------- PHY initialization and configuration ----------------*/
+ /* Put the PHY in reset mode */
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Delay to assure PHY reset */
+ HAL_Delay(PHY_RESET_DELAY);
+
+ if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* We wait for linked status */
+ do
+ {
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+ } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
+
+
+ /* Enable Auto-Negotiation */
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the auto-negotiation will be completed */
+ do
+ {
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
+
+ /* Read the result of the auto-negotiation */
+ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
+ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
+ {
+ /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
+ }
+ else
+ {
+ /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
+ (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
+ }
+ /* Configure the MAC with the speed fixed by the auto-negotiation process */
+ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
+ {
+ /* Set Ethernet speed to 10M following the auto-negotiation */
+ (heth->Init).Speed = ETH_SPEED_10M;
+ }
+ else
+ {
+ /* Set Ethernet speed to 100M following the auto-negotiation */
+ (heth->Init).Speed = ETH_SPEED_100M;
+ }
+ }
+ else /* AutoNegotiation Disable */
+ {
+ /* Check parameters */
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+
+ /* Set MAC Speed and Duplex Mode */
+ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
+ (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
+ {
+ /* In case of write timeout */
+ err = ETH_ERROR;
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set the ETH peripheral state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return HAL_ERROR */
+ return HAL_ERROR;
+ }
+
+ /* Delay to assure PHY configuration */
+ HAL_Delay(PHY_CONFIG_DELAY);
+ }
+
+ /* Config MAC and DMA */
+ ETH_MACDMAConfig(heth, err);
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the ETH peripheral.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspDeInit(heth);
+
+ /* Set ETH HAL state to Disabled */
+ heth->State= HAL_ETH_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA Tx descriptors in chain mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param DMATxDescTab: Pointer to the first Tx desc list
+ * @param TxBuff: Pointer to the first TxBuffer list
+ * @param TxBuffCount: Number of the used Tx desc in the list
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADescTypeDef *dmatxdesc;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+ heth->TxDesc = DMATxDescTab;
+
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0; i < TxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ dmatxdesc = DMATxDescTab + i;
+
+ /* Set Second Address Chained bit */
+ dmatxdesc->Status = ETH_DMATXDESC_TCH;
+
+ /* Set Buffer1 address pointer */
+ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
+
+ if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+ {
+ /* Set the DMA Tx descriptors checksum insertion */
+ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
+ }
+
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ if(i < (TxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+ }
+ }
+
+ /* Set Transmit Descriptor List Address Register */
+ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in chain mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param DMARxDescTab: Pointer to the first Rx desc list
+ * @param RxBuff: Pointer to the first RxBuffer list
+ * @param RxBuffCount: Number of the used Rx desc in the list
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADescTypeDef *DMARxDesc;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
+ heth->RxDesc = DMARxDescTab;
+
+ /* Fill each DMARxDesc descriptor with the right values */
+ for(i=0; i < RxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ DMARxDesc = DMARxDescTab+i;
+
+ /* Set Own bit of the Rx descriptor Status */
+ DMARxDesc->Status = ETH_DMARXDESC_OWN;
+
+ /* Set Buffer1 size and Second Address Chained bit */
+ DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
+
+ /* Set Buffer1 address pointer */
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
+
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+ {
+ /* Enable Ethernet DMA Rx Descriptor interrupt */
+ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
+ }
+
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ if(i < (RxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+ }
+ }
+
+ /* Set Receive Descriptor List Address Register */
+ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
+
+ /* Set ETH HAL State to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the ETH MSP.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes ETH MSP.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a frame
+ HAL_ETH_TransmitFrame();
+ (+) Receive a frame
+ HAL_ETH_GetReceivedFrame();
+ HAL_ETH_GetReceivedFrame_IT();
+ (+) Read from an External PHY register
+ HAL_ETH_ReadPHYRegister();
+ (+) Write to an External PHY register
+ HAL_ETH_WritePHYRegister();
+
+ @endverbatim
+
+ * @{
+ */
+
+/**
+ * @brief Sends an Ethernet frame.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param FrameLength: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
+{
+ uint32_t bufcount = 0, size = 0, i = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ if (FrameLength == 0)
+ {
+ /* Set ETH HAL state to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_ERROR;
+ }
+
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+ {
+ /* OWN bit set */
+ heth->State = HAL_ETH_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_ERROR;
+ }
+
+ /* Get the number of needed Tx buffers for the current frame */
+ if (FrameLength > ETH_TX_BUF_SIZE)
+ {
+ bufcount = FrameLength/ETH_TX_BUF_SIZE;
+ if (FrameLength % ETH_TX_BUF_SIZE)
+ {
+ bufcount++;
+ }
+ }
+ else
+ {
+ bufcount = 1;
+ }
+ if (bufcount == 1)
+ {
+ /* Set LAST and FIRST segment */
+ heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
+ /* Set frame size */
+ heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+ /* Point to next descriptor */
+ heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+ }
+ else
+ {
+ for (i=0; i< bufcount; i++)
+ {
+ /* Clear FIRST and LAST segment bits */
+ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
+
+ if (i == 0)
+ {
+ /* Setting the first segment bit */
+ heth->TxDesc->Status |= ETH_DMATXDESC_FS;
+ }
+
+ /* Program size */
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
+
+ if (i == (bufcount-1))
+ {
+ /* Setting the last segment bit */
+ heth->TxDesc->Status |= ETH_DMATXDESC_LS;
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
+ }
+
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+ /* point to next descriptor */
+ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+ }
+ }
+
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+ {
+ /* Clear TBUS ETHERNET DMA flag */
+ (heth->Instance)->DMASR = ETH_DMASR_TBUS;
+ /* Resume DMA transmission*/
+ (heth->Instance)->DMATPDR = 0;
+ }
+
+ /* Set ETH HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Checks for received frames.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
+{
+ uint32_t framelength = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Check the ETH state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Check if segment is not owned by DMA */
+ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
+ {
+ /* Check if last segment */
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
+ {
+ /* increment segment count */
+ (heth->RxFrameInfos).SegCount++;
+
+ /* Check if last segment is first segment: one segment contains the frame */
+ if ((heth->RxFrameInfos).SegCount == 1)
+ {
+ (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
+ }
+
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+ heth->RxFrameInfos.length = framelength;
+
+ /* Get the address of the buffer start address */
+ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+ /* point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ /* Check if first segment */
+ else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
+ {
+ (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
+ (heth->RxFrameInfos).LSRxDesc = NULL;
+ (heth->RxFrameInfos).SegCount = 1;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Check if intermediate segment */
+ else
+ {
+ (heth->RxFrameInfos).SegCount++;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ }
+
+ /* Set ETH HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Gets the Received frame in interrupt mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
+{
+ uint32_t descriptorscancounter = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set ETH HAL State to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Scan descriptors owned by CPU */
+ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
+ {
+ /* Just for security */
+ descriptorscancounter++;
+
+ /* Check if first segment in frame */
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
+ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
+ {
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+ heth->RxFrameInfos.SegCount = 1;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Check if intermediate segment */
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
+ else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
+ {
+ /* Increment segment count */
+ (heth->RxFrameInfos.SegCount)++;
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
+ }
+ /* Should be last segment */
+ else
+ {
+ /* Last segment */
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+
+ /* Increment segment count */
+ (heth->RxFrameInfos.SegCount)++;
+
+ /* Check if last segment is first segment: one segment contains the frame */
+ if ((heth->RxFrameInfos.SegCount) == 1)
+ {
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+ }
+
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+
+ /* Get the address of the buffer start address */
+ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+
+ /* Point to next descriptor */
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ }
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief This function handles ETH interrupt request.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+ /* Frame received */
+ if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
+ {
+ /* Receive complete callback */
+ HAL_ETH_RxCpltCallback(heth);
+
+ /* Clear the Eth DMA Rx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ }
+ /* Frame transmitted */
+ else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
+ {
+ /* Transfer complete callback */
+ HAL_ETH_TxCpltCallback(heth);
+
+ /* Clear the Eth DMA Tx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+ }
+
+ /* Clear the interrupt flags */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
+
+ /* ETH DMA Error */
+ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
+ {
+ /* Ethernet Error callback */
+ HAL_ETH_ErrorCallback(heth);
+
+ /* Clear the interrupt flags */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
+
+ /* Set HAL State to Ready */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Ethernet transfer error callbacks
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Reads a PHY register
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * PHY_BCR: Transceiver Basic Control Register,
+ * PHY_BSR: Transceiver Basic Status Register.
+ * More PHY register could be read depending on the used PHY
+ * @param RegValue: PHY register value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
+{
+ uint32_t tmpreg = 0;
+ uint32_t tickstart = 0;
+
+ /* Check parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+
+ /* Check the ETH peripheral state */
+ if(heth->State == HAL_ETH_STATE_BUSY_RD)
+ {
+ return HAL_BUSY;
+ }
+ /* Set ETH HAL State to BUSY_RD */
+ heth->State = HAL_ETH_STATE_BUSY_RD;
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = heth->Instance->MACMIIAR;
+
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+
+ /* Prepare the MII address register value */
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+
+ /* Write the result value into the MII Address register */
+ heth->Instance->MACMIIAR = tmpreg;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check for the Busy flag */
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg = heth->Instance->MACMIIAR;
+ }
+
+ /* Get MACMIIDR value */
+ *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
+
+ /* Set ETH HAL State to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes to a PHY register.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * PHY_BCR: Transceiver Control Register.
+ * More PHY register could be written depending on the used PHY
+ * @param RegValue: the value to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
+{
+ uint32_t tmpreg = 0;
+ uint32_t tickstart = 0;
+
+ /* Check parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+
+ /* Check the ETH peripheral state */
+ if(heth->State == HAL_ETH_STATE_BUSY_WR)
+ {
+ return HAL_BUSY;
+ }
+ /* Set ETH HAL State to BUSY_WR */
+ heth->State = HAL_ETH_STATE_BUSY_WR;
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = heth->Instance->MACMIIAR;
+
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+
+ /* Prepare the MII register address value */
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+
+ /* Give the value to the MII data register */
+ heth->Instance->MACMIIDR = (uint16_t)RegValue;
+
+ /* Write the result value into the MII Address register */
+ heth->Instance->MACMIIAR = tmpreg;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check for the Busy flag */
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
+ {
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ return HAL_TIMEOUT;
+ }
+
+ tmpreg = heth->Instance->MACMIIAR;
+ }
+
+ /* Set ETH HAL State to READY */
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable MAC and DMA transmission and reception.
+ HAL_ETH_Start();
+ (+) Disable MAC and DMA transmission and reception.
+ HAL_ETH_Stop();
+ (+) Set the MAC configuration in runtime mode
+ HAL_ETH_ConfigMAC();
+ (+) Set the DMA configuration in runtime mode
+ HAL_ETH_ConfigDMA();
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Enables Ethernet MAC and DMA reception/transmission
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Enable transmit state machine of the MAC for transmission on the MII */
+ ETH_MACTransmissionEnable(heth);
+
+ /* Enable receive state machine of the MAC for reception from the MII */
+ ETH_MACReceptionEnable(heth);
+
+ /* Flush Transmit FIFO */
+ ETH_FlushTransmitFIFO(heth);
+
+ /* Start DMA transmission */
+ ETH_DMATransmissionEnable(heth);
+
+ /* Start DMA reception */
+ ETH_DMAReceptionEnable(heth);
+
+ /* Set the ETH state to READY*/
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop Ethernet MAC and DMA reception/transmission
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State = HAL_ETH_STATE_BUSY;
+
+ /* Stop DMA transmission */
+ ETH_DMATransmissionDisable(heth);
+
+ /* Stop DMA reception */
+ ETH_DMAReceptionDisable(heth);
+
+ /* Disable receive state machine of the MAC for reception from the MII */
+ ETH_MACReceptionDisable(heth);
+
+ /* Flush Transmit FIFO */
+ ETH_FlushTransmitFIFO(heth);
+
+ /* Disable transmit state machine of the MAC for transmission on the MII */
+ ETH_MACTransmissionDisable(heth);
+
+ /* Set the ETH state*/
+ heth->State = HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set ETH MAC Configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param macconf: MAC Configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
+{
+ uint32_t tmpreg = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State= HAL_ETH_STATE_BUSY;
+
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+
+ if (macconf != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
+ assert_param(IS_ETH_JABBER(macconf->Jabber));
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
+
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg = (heth->Instance)->MACCR;
+ /* Clear WD, PCE, PS, TE and RE bits */
+ tmpreg &= ETH_MACCR_CLEAR_MASK;
+
+ tmpreg |= (uint32_t)(macconf->Watchdog |
+ macconf->Jabber |
+ macconf->InterFrameGap |
+ macconf->CarrierSense |
+ (heth->Init).Speed |
+ macconf->ReceiveOwn |
+ macconf->LoopbackMode |
+ (heth->Init).DuplexMode |
+ macconf->ChecksumOffload |
+ macconf->RetryTransmission |
+ macconf->AutomaticPadCRCStrip |
+ macconf->BackOffLimit |
+ macconf->DeferralCheck);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+ /* Write to ETHERNET MACFFR */
+ (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
+ macconf->SourceAddrFilter |
+ macconf->PassControlFrames |
+ macconf->BroadcastFramesReception |
+ macconf->DestinationAddrFilter |
+ macconf->PromiscuousMode |
+ macconf->MulticastFramesFilter |
+ macconf->UnicastFramesFilter);
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACFFR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFFR = tmpreg;
+
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+ /* Write to ETHERNET MACHTHR */
+ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
+
+ /* Write to ETHERNET MACHTLR */
+ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+
+ /* Get the ETHERNET MACFCR value */
+ tmpreg = (heth->Instance)->MACFCR;
+ /* Clear xx bits */
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;
+
+ tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
+ macconf->ZeroQuantaPause |
+ macconf->PauseLowThreshold |
+ macconf->UnicastPauseFrameDetect |
+ macconf->ReceiveFlowControl |
+ macconf->TransmitFlowControl);
+
+ /* Write to ETHERNET MACFCR */
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACFCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFCR = tmpreg;
+
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+ (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
+ macconf->VLANTagIdentifier);
+
+ /* Wait until the write operation will be taken into account :
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACVLANTR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACVLANTR = tmpreg;
+ }
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */
+ {
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg = (heth->Instance)->MACCR;
+
+ /* Clear FES and DM bits */
+ tmpreg &= ~((uint32_t)0x00004800);
+
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+ }
+
+ /* Set the ETH state to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets ETH DMA Configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param dmaconf: DMA Configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
+{
+ uint32_t tmpreg = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(heth);
+
+ /* Set the ETH peripheral state to BUSY */
+ heth->State= HAL_ETH_STATE_BUSY;
+
+ /* Check parameters */
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
+
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+ /* Get the ETHERNET DMAOMR value */
+ tmpreg = (heth->Instance)->DMAOMR;
+ /* Clear xx bits */
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+
+ tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ dmaconf->ReceiveStoreForward |
+ dmaconf->FlushReceivedFrame |
+ dmaconf->TransmitStoreForward |
+ dmaconf->TransmitThresholdControl |
+ dmaconf->ForwardErrorFrames |
+ dmaconf->ForwardUndersizedGoodFrames |
+ dmaconf->ReceiveThresholdControl |
+ dmaconf->SecondFrameOperate);
+
+ /* Write to ETHERNET DMAOMR */
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->DMAOMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg;
+
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+ (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
+ dmaconf->FixedBurst |
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+ dmaconf->TxDMABurstLength |
+ (dmaconf->DescriptorSkipLength << 2) |
+ dmaconf->DMAArbitration |
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->DMABMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMABMR = tmpreg;
+
+ /* Set the ETH state to Ready */
+ heth->State= HAL_ETH_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+ (+) Get the ETH handle state:
+ HAL_ETH_GetState();
+
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ETH HAL state
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL state
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+{
+ /* Return ETH state */
+ return heth->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures Ethernet MAC and DMA with default parameters.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param err: Ethernet Init error
+ * @retval HAL status
+ */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
+{
+ ETH_MACInitTypeDef macinit;
+ ETH_DMAInitTypeDef dmainit;
+ uint32_t tmpreg = 0;
+
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */
+ {
+ /* Set Ethernet duplex mode to Full-duplex */
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
+
+ /* Set Ethernet speed to 100M */
+ (heth->Init).Speed = ETH_SPEED_100M;
+ }
+
+ /* Ethernet MAC default initialization **************************************/
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;
+ macinit.Jabber = ETH_JABBER_ENABLE;
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+ {
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
+ }
+ else
+ {
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+ }
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
+ macinit.HashTableHigh = 0x0;
+ macinit.HashTableLow = 0x0;
+ macinit.PauseTime = 0x0;
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
+ macinit.VLANTagIdentifier = 0x0;
+
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg = (heth->Instance)->MACCR;
+ /* Clear WD, PCE, PS, TE and RE bits */
+ tmpreg &= ETH_MACCR_CLEAR_MASK;
+ /* Set the WD bit according to ETH Watchdog value */
+ /* Set the JD: bit according to ETH Jabber value */
+ /* Set the IFG bit according to ETH InterFrameGap value */
+ /* Set the DCRS bit according to ETH CarrierSense value */
+ /* Set the FES bit according to ETH Speed value */
+ /* Set the DO bit according to ETH ReceiveOwn value */
+ /* Set the LM bit according to ETH LoopbackMode value */
+ /* Set the DM bit according to ETH Mode value */
+ /* Set the IPCO bit according to ETH ChecksumOffload value */
+ /* Set the DR bit according to ETH RetryTransmission value */
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
+ /* Set the BL bit according to ETH BackOffLimit value */
+ /* Set the DC bit according to ETH DeferralCheck value */
+ tmpreg |= (uint32_t)(macinit.Watchdog |
+ macinit.Jabber |
+ macinit.InterFrameGap |
+ macinit.CarrierSense |
+ (heth->Init).Speed |
+ macinit.ReceiveOwn |
+ macinit.LoopbackMode |
+ (heth->Init).DuplexMode |
+ macinit.ChecksumOffload |
+ macinit.RetryTransmission |
+ macinit.AutomaticPadCRCStrip |
+ macinit.BackOffLimit |
+ macinit.DeferralCheck);
+
+ /* Write to ETHERNET MACCR */
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+ /* Set the RA bit according to ETH ReceiveAll value */
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
+ /* Set the PCF bit according to ETH PassControlFrames value */
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */
+ /* Set the PR bit according to ETH PromiscuousMode value */
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
+ /* Write to ETHERNET MACFFR */
+ (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
+ macinit.SourceAddrFilter |
+ macinit.PassControlFrames |
+ macinit.BroadcastFramesReception |
+ macinit.DestinationAddrFilter |
+ macinit.PromiscuousMode |
+ macinit.MulticastFramesFilter |
+ macinit.UnicastFramesFilter);
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACFFR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFFR = tmpreg;
+
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
+ /* Write to ETHERNET MACHTHR */
+ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
+
+ /* Write to ETHERNET MACHTLR */
+ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/
+
+ /* Get the ETHERNET MACFCR value */
+ tmpreg = (heth->Instance)->MACFCR;
+ /* Clear xx bits */
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;
+
+ /* Set the PT bit according to ETH PauseTime value */
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
+ /* Set the PLT bit according to ETH PauseLowThreshold value */
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */
+ /* Set the TFE bit according to ETH TransmitFlowControl value */
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
+ macinit.ZeroQuantaPause |
+ macinit.PauseLowThreshold |
+ macinit.UnicastPauseFrameDetect |
+ macinit.ReceiveFlowControl |
+ macinit.TransmitFlowControl);
+
+ /* Write to ETHERNET MACFCR */
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACFCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACFCR = tmpreg;
+
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
+ /* Set the ETV bit according to ETH VLANTagComparison value */
+ /* Set the VL bit according to ETH VLANTagIdentifier value */
+ (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
+ macinit.VLANTagIdentifier);
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACVLANTR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACVLANTR = tmpreg;
+
+ /* Ethernet DMA default initialization ************************************/
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+ dmainit.DescriptorSkipLength = 0x0;
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
+
+ /* Get the ETHERNET DMAOMR value */
+ tmpreg = (heth->Instance)->DMAOMR;
+ /* Clear xx bits */
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */
+ /* Set the TSF bit according to ETH TransmitStoreForward value */
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */
+ /* Set the OSF bit according to ETH SecondFrameOperate value */
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ dmainit.ReceiveStoreForward |
+ dmainit.FlushReceivedFrame |
+ dmainit.TransmitStoreForward |
+ dmainit.TransmitThresholdControl |
+ dmainit.ForwardErrorFrames |
+ dmainit.ForwardUndersizedGoodFrames |
+ dmainit.ReceiveThresholdControl |
+ dmainit.SecondFrameOperate);
+
+ /* Write to ETHERNET DMAOMR */
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->DMAOMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg;
+
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */
+ /* Set the FB bit according to ETH FixedBurst value */
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */
+ /* Set the PR and DA bits according to ETH DMAArbitration value */
+ (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
+ dmainit.FixedBurst |
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+ dmainit.TxDMABurstLength |
+ (dmainit.DescriptorSkipLength << 2) |
+ dmainit.DMAArbitration |
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->DMABMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMABMR = tmpreg;
+
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+ {
+ /* Enable the Ethernet Rx Interrupt */
+ __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
+ }
+
+ /* Initialize MAC address in ethernet MAC */
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
+}
+
+/**
+ * @brief Configures the selected MAC address.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param MacAddr: The MAC address to configure
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address0: MAC Address0
+ * @arg ETH_MAC_Address1: MAC Address1
+ * @arg ETH_MAC_Address2: MAC Address2
+ * @arg ETH_MAC_Address3: MAC Address3
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)
+ * @retval HAL status
+ */
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+ /* Calculate the selected MAC address high register */
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ /* Load the selected MAC address high register */
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+ /* Calculate the selected MAC address low register */
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+
+ /* Load the selected MAC address low register */
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+}
+
+/**
+ * @brief Enables the MAC transmission.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Enable the MAC transmission */
+ (heth->Instance)->MACCR |= ETH_MACCR_TE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+ * @brief Disables the MAC transmission.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Disable the MAC transmission */
+ (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+ * @brief Enables the MAC reception.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Enable the MAC reception */
+ (heth->Instance)->MACCR |= ETH_MACCR_RE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+ * @brief Disables the MAC reception.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Disable the MAC reception */
+ (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->MACCR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+ * @brief Enables the DMA transmission.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
+{
+ /* Enable the DMA transmission */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
+}
+
+/**
+ * @brief Disables the DMA transmission.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
+{
+ /* Disable the DMA transmission */
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
+}
+
+/**
+ * @brief Enables the DMA reception.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
+{
+ /* Enable the DMA reception */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
+}
+
+/**
+ * @brief Disables the DMA reception.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
+{
+ /* Disable the DMA reception */
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
+}
+
+/**
+ * @brief Clears the ETHERNET transmit FIFO.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Set the Flush Transmit FIFO bit */
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
+
+ /* Wait until the write operation will be taken into account:
+ at least four TX_CLK/RX_CLK clock cycles */
+ tmpreg = (heth->Instance)->DMAOMR;
+ HAL_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ETH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+#endif /* STM32F107xC */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.h
new file mode 100644
index 000000000..67f7a2b4f
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.h
@@ -0,0 +1,2135 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_eth.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ETH_H
+#define __STM32F1xx_HAL_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+#if defined (STM32F107xC)
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/** @addtogroup ETH_Private_Macros
+ * @{
+ */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Constants
+ * @{
+ */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS ((uint32_t)0)
+#define ETH_ERROR ((uint32_t)1)
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+ /**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_ETH_StateTypeDef;
+
+/**
+ * @brief ETH Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
+ This parameter can be a value of @ref ETH_Rx_Mode */
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
+ This parameter can be a value of @ref ETH_Checksum_Mode */
+
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /**
+ * @brief ETH MAC Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Watchdog */
+
+ uint32_t Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode.
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a collision occurs (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address).
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering.
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+} ETH_DMAInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Descriptors data structure definition
+ */
+
+typedef struct
+{
+ __IO uint32_t Status; /*!< Status */
+
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+
+} ETH_DMADescTypeDef;
+
+
+/**
+ * @brief Received Frame Informations structure definition
+ */
+typedef struct
+{
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
+
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
+
+ uint32_t SegCount; /*!< Segment count */
+
+ uint32_t length; /*!< Frame length */
+
+ uint32_t buffer; /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+
+typedef struct
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ uint32_t LinkStatus; /*!< Ethernet link status */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
+
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
+
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
+
+ HAL_LockTypeDef Lock; /*!< ETH Lock */
+
+} ETH_HandleTypeDef;
+
+ /**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
+
+/** @defgroup ETH_Buffers_setting ETH Buffers setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
+#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
+
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
+
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
+
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
+
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
+
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_TX_BUF_SIZE
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+ /**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+ * @{
+ */
+
+/*
+ DMA Tx Desciptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/**
+ * @}
+ */
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+ * @{
+ */
+
+/*
+ DMA Rx Descriptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/**
+ * @}
+ */
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Speed ETH Speed
+ * @{
+ */
+#define ETH_SPEED_10M ((uint32_t)0x00000000)
+#define ETH_SPEED_100M ((uint32_t)0x00004000)
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+ * @{
+ */
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface ETH Media Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog ETH Watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber ETH Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own ETH Receive Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All ETH Receive All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
+ * @{
+ */
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
+ * @{
+ */
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
+ * @{
+ */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
+ * @{
+ */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
+ * @{
+ */
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
+ * @{
+ */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
+ * @{
+ */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+ * @{
+ */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
+ * @{
+ */
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
+ * @{
+ */
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
+ * @{
+ */
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
+ * @{
+ */
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags ETH PMT Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags ETH MAC Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags ETH DMA Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
+ * @{
+ */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
+ * @{
+ */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow ETH DMA overflow
+ * @{
+ */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
+
+/**
+ * @}
+ */
+
+ /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ * @{
+ */
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__: specifies the ETH handle.
+ * @retval None
+ */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag of TDES0 to check .
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag of RDES0 to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+ * @brief Disables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param __HANDLE__: ETH Handle
+ * @retval The Transmit descriptor collision counter value.
+ */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param __HANDLE__: ETH Handle
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+ * @brief Enables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+ * @brief Disables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The state of ETHERNET MAC flag.
+ */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * enabled @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+ * @brief Set the DMA Receive status watchdog timer register value
+ * @param __HANDLE__: ETH Handle
+ * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @retval None
+ */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/**
+ * @brief Enables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Enables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Disables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+ * @brief Disables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Disables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param __HANDLE__: ETH Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+ * @brief Enables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+ * @brief Disables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+ * @brief Enables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+ * @brief Disables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+ * @brief Enables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+ * @brief Disables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Enables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enable event on ETH External event line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disable event on ETH External event line
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Get flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Clear flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+
+/**
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+
+/**
+ * @}
+ */
+
+/* IO operation functions ****************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+/* Communication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+ /* Callback in non blocking modes (Interrupt) */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F107xC */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ETH_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.c
new file mode 100644
index 000000000..95c4abde1
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.c
@@ -0,0 +1,661 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) Option Bytes programming
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F1xx devices. These functions are split in 3 groups:
+
+ (#) FLASH Memory I/O Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface
+ (++) Erase function: Erase page, erase all pages
+ (++) Program functions: half word, word and doubleword
+
+ (#) Option Bytes Programming functions: this group includes all needed
+ functions to manage the Option Bytes:
+ (++) Lock and Unlock the Option Bytes
+ (++) Erase Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Program the data Option Bytes
+ (++) Launch the Option Bytes loader
+
+ (#) Interrupts and flags management functions : this group
+ includes all needed functions to:
+ (++) Handle FLASH interrupts
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status
+
+ [..] In addition to these function, this driver includes a set of macros allowing
+ to handle the following operations:
+
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the half cycle access
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations (write/erase).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+__weak HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0;
+ uint8_t nbiterations = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4;
+ }
+
+ for (index = 0; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+__weak HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /*Program halfword (16-bit) at a specified address.*/
+ pFlash.DataRemaining = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /*Program word (32-bit : 2*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 2;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /*Program double word (64-bit : 4*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 4;
+ }
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+__weak void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(pFlash.Address);
+
+ /* Reset address and stop the procedure ongoing*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
+
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /* Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which has been erased
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+__weak HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+__weak HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @note This function will reset automatically the MCU.
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Initiates a system reset request to launch the option byte loading */
+ HAL_NVIC_SystemReset();
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode: The returned value can be:
+ * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error flag
+ * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg HAL_FLASH_ERROR_OPTV: Option byte error
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout: maximum flash operationtimeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || \
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.h
new file mode 100644
index 000000000..9320b7d81
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.h
@@ -0,0 +1,261 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_H
+#define __STM32F1xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGEERASE = 1,
+ FLASH_PROC_MASSERASE = 2,
+ FLASH_PROC_PROGRAMHALFWORD = 3,
+ FLASH_PROC_PROGRAMWORD = 4,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
+
+ __IO uint32_t DataRemaining; /* Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+ __IO uint32_t Address; /* Internal variable to save address selected for program or erase */
+
+ __IO uint64_t Data; /* Internal variable to save data to be programmed */
+
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+
+ __IO uint32_t ErrorCode; /* FLASH error code */
+
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00)
+#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01)
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02)
+#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_Type_Program Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @brief macros to control FLASH features
+ * @{
+ */
+
+/**
+ * @brief Enable the FLASH half cycle access.
+ * @note halfcycle access can only be used with a low-frequency clock of less than
+ 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+ * @brief Disable the FLASH half cycle access.
+ * @note halfcycle access can only be used with a low-frequency clock of less than
+ 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f1xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t PageAddress);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+void FLASH_SetErrorCode(void);
+void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.c
new file mode 100644
index 000000000..f7a21c5ab
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.c
@@ -0,0 +1,1650 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Extended FLASH HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + Extended Initialization/de-initialization functions
+ * + Extended I/O operation functions
+ * + Extended Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash peripheral extended features #####
+ ==============================================================================
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F1xxx devices. It includes
+
+ (++) Set/Reset the write protection
+ (++) Program the user Option Bytes
+ (++) Get the Read protection Level
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @addtogroup FLASH
+ * @{
+ */
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+/* Erase operations */
+static void FLASH_MassErase(uint32_t Banks);
+
+/* Option bytes control */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+static uint32_t FLASH_OB_GetWRP(void);
+static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetUser(void);
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+/* State operations */
+static HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
+#endif
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError: pointer to variable that
+ * contains the configuration information on faulty page in case of error
+ * (0xFFFFFFFF means that all the pages have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t address = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if (pEraseInit->Banks == FLASH_BANK_BOTH)
+ {
+ /* Mass Erase requested for Bank1 and Bank2 */
+ /* Wait for last operation to be completed */
+ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_BOTH);
+
+ /* Wait for last operation to be completed */
+ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
+ {
+ status = HAL_OK;
+ }
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+ }
+ }
+ else if (pEraseInit->Banks == FLASH_BANK_2)
+ {
+ /* Mass Erase requested for Bank2 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_2);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+ }
+ }
+ else
+#endif /* STM32F101xG || STM32F103xG */
+ {
+ /* Mass Erase requested for Bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_1);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ }
+ }
+ else
+ {
+ /* Page Erase is requested */
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ /* Page Erase requested on address located on bank2 */
+ if(pEraseInit->PageAddress > FLASH_BANK1_END)
+ {
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase by page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+ else
+#endif /* STM32F101xG || STM32F103xG */
+ {
+ /* Page Erase requested on address located on bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(pEraseInit->Banks);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ else
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase by page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2));
+#endif
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ FLASH_MassErase(pEraseInit->Banks);
+ }
+ else
+ {
+ /* Erase by page to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.DataRemaining = pEraseInit->NbPages;
+ pFlash.Address = pEraseInit->PageAddress;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_PageErase(pEraseInit->PageAddress);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+{
+ uint8_t rdptmp = OB_RDP_LEVEL_0;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Get the actual read protection Option Byte value */
+ if(FLASH_OB_GetRDP() != RESET)
+ {
+ rdptmp = OB_RDP_LEVEL_1;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Restore the last read protection Option Byte value */
+ status = FLASH_OB_RDP_LevelConfig(rdptmp);
+ }
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ *
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Write protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ {
+ /* Enable of Write protection on the selected page */
+ status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
+ }
+ else
+ {
+ /* Disable of Write protection on the selected page */
+ status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
+ }
+ }
+
+ /* Read protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ }
+
+ /* USER configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig);
+ }
+
+ /* DATA configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+ {
+ status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
+
+ /*Get WRP*/
+ pOBInit->WRPPage = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Full erase of FLASH memory Bank
+ * @param Banks: Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+ *
+ * @retval HAL Status
+ */
+static void FLASH_MassErase(uint32_t Banks)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ /* bank1 & bank2 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR2, FLASH_CR2_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else if(Banks == FLASH_BANK_2)
+ {
+ /*Only bank2 will be erased*/
+ SET_BIT(FLASH->CR2, FLASH_CR2_MER);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else
+ {
+#endif /* STM32F101xG || STM32F103xG */
+ /*Only bank1 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ }
+#endif /* STM32F101xG || STM32F103xG */
+}
+
+/**
+ * @brief Enable the write protection of the desired pages
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage: specifies the page(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) || \
+ defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+ uint16_t WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB || */
+ /* STM32F100xE || STM32F101xE || STM32F103xE || */
+ /* STM32F101xG || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ WriteProtectPage = (uint32_t)(~WriteProtectPage);
+
+ /* Low Density and Medium Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || \
+ defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 || */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* High Density, XL Density and Connectivity line devices*/
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) || \
+ defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB || */
+ /* STM32F100xE || STM32F101xE || STM32F103xE || */
+ /* STM32F101xG || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired pages
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage: specifies the page(s) to be write unprotected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) || \
+ defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+ uint16_t WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB || */
+ /* STM32F100xE || STM32F101xE || STM32F103xE || */
+ /* STM32F101xG || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Low Density and Medium Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || \
+ defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 || */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* High Density, XL Density and Connectivity line devices*/
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) || \
+ defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB ||*/
+ /* STM32F100xE || STM32F101xE || STM32F103xE ||*/
+ /* STM32F101xG || STM32F103xG ||*/
+ /* STM32F105xC || STM32F107xC */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param ReadProtectLevel: specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ *
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param UserConfig: The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
+ * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
+ * And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
+ assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
+ assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
+#endif /* STM32F101xG || STM32F103xG */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ OB->USER = (UserConfig | 0xF0);
+#else
+ OB->USER = (UserConfig | 0xF8);
+#endif /* STM32F101xG || STM32F103xG */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enables the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(READ_REG(FLASH->WRPR));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * - SET, when OB_RDP_LEVEL_1 is set
+ * - RESET, when OB_RDP_LEVEL_0 is set
+ */
+static FlagStatus FLASH_OB_GetRDP(void)
+{
+ FlagStatus readstatus = RESET;
+
+ if (HAL_IS_BIT_SET(FLASH->OBR, FLASH_OBR_RDPRT))
+ {
+ readstatus = SET;
+ }
+ else
+ {
+ readstatus = RESET;
+ }
+ return readstatus;
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
+ * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
+ * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> 2);
+}
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+/**
+ * @brief Wait for a FLASH BANK2 operation to complete.
+ * @param Timeout: maximum flash operationtimeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+static HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
+{
+ /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is an error flag set */
+ return HAL_OK;
+
+}
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
+ {
+ /* Authorize the FLASH BANK1 Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+
+ if (HAL_IS_BIT_SET(FLASH->CR2, FLASH_CR2_LOCK))
+ {
+ /* Authorize the FLASH BANK2 Registers access */
+ WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH BANK1 Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
+ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0;
+ uint8_t nbiterations = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ if(Address <= FLASH_BANK1_END)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4;
+ }
+
+ for (index = 0; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+
+ if(Address <= FLASH_BANK1_END)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+ }
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ if(Address <= FLASH_BANK1_END)
+ {
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1));
+ }else
+ {
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2));
+ }
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /*Program halfword (16-bit) at a specified address.*/
+ pFlash.DataRemaining = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /*Program word (32-bit : 2*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 2;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /*Program double word (64-bit : 4*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 4;
+ }
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
+ (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
+ {
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(pFlash.Address);
+
+ /* Reset address and stop the procedure ongoing*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
+
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+ /* Stop Mass Erase procedure if no pending mass erase on other bank */
+ if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
+ {
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
+
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
+ {
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, PER and MER Bits for both bank */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+ CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts for both banks */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F101xG || STM32F103xG */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval None
+ */
+void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if(Address <= FLASH_BANK1_END)
+ {
+#endif /* STM32F101xG || STM32F103xG */
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ }
+ else
+ {
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR2, FLASH_CR2_PG);
+ }
+#endif /* STM32F101xG || STM32F103xG */
+
+ /* Write data in the address */
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+void FLASH_SetErrorCode(void)
+{
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+#endif /* STM32F101xG || STM32F103xG */
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ }
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+#endif /* STM32F101xG || STM32F103xG */
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+ }
+
+ /* Clear FLASH error pending bits */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2);
+#else
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+#endif /* STM32F101xG || STM32F103xG */
+}
+
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress: FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ if(PageAddress > FLASH_BANK1_END)
+ {
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR2, FLASH_CR2_PER);
+ WRITE_REG(FLASH->AR2, PageAddress);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else
+#endif /* STM32F101xG || STM32F103xG */
+ {
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.h
new file mode 100644
index 000000000..bcbee85dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.h
@@ -0,0 +1,889 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_EX_H
+#define __STM32F1xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0)
+#define OBR_REG_INDEX ((uint32_t)1)
+#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))))
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)))
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF))
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity Line */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
+#endif /* STM32F105xC || STM32F107xC */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#else
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFF)))
+
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
+ ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
+ ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF)))))
+
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \
+ ((ADDRESS) <= 0x0805FFFF) : ((ADDRESS) <= 0x0803FFFF))))
+
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \
+ ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFF)))
+
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity Line */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
+ ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
+
+#else
+
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+ ((__LATENCY__) == FLASH_LATENCY_1) || \
+ ((__LATENCY__) == FLASH_LATENCY_2))
+#endif
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
+ (x = 1 or 2 depending on devices)*/
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
+#else
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY */
+#endif /* STM32F101xG || STM32F103xG */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed
+ This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Constants FLASH Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size Page Size
+ * @{
+ */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || \
+ defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define FLASH_PAGE_SIZE ((uint32_t)0x400)
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define FLASH_PAGE_SIZE ((uint32_t)0x800)
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency_Values Latency Values
+ * @{
+ */
+#define FLASH_LATENCY_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+/* Only Latency0 supported on value lines */
+#else
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Banks Banks
+ * @{
+ */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+
+#else
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+#endif /* STM32F101xG || STM32F103xG */
+
+/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
+#define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
+ * @{
+ */
+/* STM32 Low and Medium density devices */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || \
+ defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 Medium-density devices */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55 ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67 ((uint32_t)0x00010000) /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71 ((uint32_t)0x00020000) /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75 ((uint32_t)0x00040000) /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79 ((uint32_t)0x00080000) /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83 ((uint32_t)0x00100000) /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87 ((uint32_t)0x00200000) /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91 ((uint32_t)0x00400000) /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95 ((uint32_t)0x00800000) /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99 ((uint32_t)0x01000000) /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103 ((uint32_t)0x02000000) /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107 ((uint32_t)0x04000000) /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111 ((uint32_t)0x08000000) /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115 ((uint32_t)0x10000000) /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119 ((uint32_t)0x20000000) /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123 ((uint32_t)0x40000000) /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127 ((uint32_t)0x80000000) /*!< Write protection of page 124 to 127 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+
+/* STM32 High-density, XL-density and Connectivity line devices */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || \
+ defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000)
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000)
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000)
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Flag_definition Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
+ #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
+ #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
+ #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
+
+ #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
+ #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
+ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
+ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
+
+ #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */
+ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */
+ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */
+ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */
+
+#else
+
+ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+ #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+ #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
+ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+
+#endif
+ #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8 | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+ #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
+
+ #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
+
+ #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16) /*!< End of FLASH Operation Interrupt source Bank2 */
+ #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16) /*!< Error Interrupt source Bank2 */
+
+#else
+
+ #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+ #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
+
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
+ * @{
+ */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+/* Macros not available */
+#else
+/** @defgroup FLASH_Latency Latency configuration
+ * @brief macros to set the FLASH latency
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__: FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2: FLASH Two Latency cycle
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+/** @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2: FLASH Two Latency cycle
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Prefetch Prefetch activation or deactivation
+ * @brief macros to set the FLASH Prefetch
+ * @{
+ */
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+#endif
+
+/** @defgroup FLASH_Interrupt Interrupt
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP_BANK1: End of FLASH Operation Interrupt on bank1
+ * @arg FLASH_IT_ERR_BANK1: Error Interrupt on bank1
+ * @arg FLASH_IT_EOP_BANK2: End of FLASH Operation Interrupt on bank2
+ * @arg FLASH_IT_ERR_BANK2: Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
+ /* Enable Bank1 IT */ \
+ SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ /* Enable Bank2 IT */ \
+ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
+ } while(0)
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP_BANK1: End of FLASH Operation Interrupt on bank1
+ * @arg FLASH_IT_ERR_BANK1: Error Interrupt on bank1
+ * @arg FLASH_IT_EOP_BANK2: End of FLASH Operation Interrupt on bank2
+ * @arg FLASH_IT_ERR_BANK2: Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
+ /* Disable Bank1 IT */ \
+ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ /* Disable Bank2 IT */ \
+ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
+ } while(0)
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP_BANK1 : FLASH End of Operation flag on bank1
+ * @arg FLASH_FLAG_WRPERR_BANK1: FLASH Write protected error flag on bank1
+ * @arg FLASH_FLAG_PGERR_BANK1 : FLASH Programming error flag on bank1
+ * @arg FLASH_FLAG_BSY_BANK1 : FLASH Busy flag on bank1
+ * @arg FLASH_FLAG_EOP_BANK2 : FLASH End of Operation flag on bank2
+ * @arg FLASH_FLAG_WRPERR_BANK2: FLASH Write protected error flag on bank2
+ * @arg FLASH_FLAG_PGERR_BANK2 : FLASH Programming error flag on bank2
+ * @arg FLASH_FLAG_BSY_BANK2 : FLASH Busy flag on bank2
+ * @arg FLASH_FLAG_OPTVERR : Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+ (FLASH->OBR & FLASH_OBR_OPTERR) : \
+ ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
+ (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
+ (FLASH->SR2 & ((__FLAG__) >> 16))))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP_BANK1 : FLASH End of Operation flag on bank1
+ * @arg FLASH_FLAG_WRPERR_BANK1: FLASH Write protected error flag on bank1
+ * @arg FLASH_FLAG_PGERR_BANK1 : FLASH Programming error flag on bank1
+ * @arg FLASH_FLAG_BSY_BANK1 : FLASH Busy flag on bank1
+ * @arg FLASH_FLAG_EOP_BANK2 : FLASH End of Operation flag on bank2
+ * @arg FLASH_FLAG_WRPERR_BANK2: FLASH Write protected error flag on bank2
+ * @arg FLASH_FLAG_PGERR_BANK2 : FLASH Programming error flag on bank2
+ * @arg FLASH_FLAG_BSY_BANK2 : FLASH Busy flag on bank2
+ * @arg FLASH_FLAG_OPTVERR : Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
+ /* Clear FLASH_FLAG_OPTVERR flag */ \
+ if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+ { \
+ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+ } \
+ else { \
+ /* Clear Flag in Bank1 */ \
+ if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
+ { \
+ FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
+ } \
+ /* Clear Flag in Bank2 */ \
+ if (((__FLAG__) >> 16) != RESET) \
+ { \
+ FLASH->SR2 = ((__FLAG__) >> 16); \
+ } \
+ } \
+ } while(0)
+#else
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @arg FLASH_FLAG_OPTVERR : Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+ (FLASH->OBR & FLASH_OBR_OPTERR) : \
+ (FLASH->SR & (__FLAG__)))
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
+ * @arg FLASH_FLAG_OPTVERR : Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
+ /* Clear FLASH_FLAG_OPTVERR flag */ \
+ if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+ { \
+ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+ } \
+ else { \
+ /* Clear Flag in Bank1 */ \
+ FLASH->SR = (__FLAG__); \
+ } \
+ } while(0)
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c
new file mode 100644
index 000000000..f56bd6814
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c
@@ -0,0 +1,596 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 20 edge detectors in connectivity
+ line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
+ Each input line can be independently configured to select the type (event or interrupt) and
+ the corresponding trigger event (rising or falling or both). Each line can also masked
+ independently. A pending register maintains the status line of the interrupt requests
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO APB2 clock using the following function : __HAL_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_NUMBER ((uint32_t)16)
+
+/* Definitions for bit manipulation of CRL and CRH register */
+#define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */
+#define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */
+#define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */
+#define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */
+#define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */
+#define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */
+#define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */
+#define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and deinitialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position;
+ uint32_t ioposition = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t temp = 0x00;
+ uint32_t config = 0x00;
+ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+ uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ for (position = 0; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+ if (iocurrent == ioposition)
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+
+ /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
+ switch (GPIO_Init->Mode)
+ {
+ /* If we are configuring the pin in OUTPUT push-pull mode */
+ case GPIO_MODE_OUTPUT_PP:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
+ break;
+
+ /* If we are configuring the pin in OUTPUT open-drain mode */
+ case GPIO_MODE_OUTPUT_OD:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
+ break;
+
+ /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
+ case GPIO_MODE_AF_PP:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
+ break;
+
+ /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
+ case GPIO_MODE_AF_OD:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
+ break;
+
+ /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
+ case GPIO_MODE_INPUT:
+ case GPIO_MODE_IT_RISING:
+ case GPIO_MODE_IT_FALLING:
+ case GPIO_MODE_IT_RISING_FALLING:
+ case GPIO_MODE_EVT_RISING:
+ case GPIO_MODE_EVT_FALLING:
+ case GPIO_MODE_EVT_RISING_FALLING:
+ /* Check the GPIO pull parameter */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ if(GPIO_Init->Pull == GPIO_NOPULL)
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
+ }
+ else if(GPIO_Init->Pull == GPIO_PULLUP)
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+ /* Set the corresponding ODR bit */
+ GPIOx->BSRR = ioposition;
+ }
+ else /* GPIO_PULLDOWN */
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+ /* Reset the corresponding ODR bit */
+ GPIOx->BRR = ioposition;
+ }
+ break;
+
+ /* If we are configuring the pin in INPUT analog mode */
+ case GPIO_MODE_ANALOG:
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
+ break;
+
+ /* Parameters are checked with assert_param */
+ default:
+ break;
+ }
+
+ /* Check if the current bit belongs to first half or last half of the pin count number
+ in order to address CRH or CRL register*/
+ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+
+ /* Apply the new configuration of the pin to the register */
+ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable AFIO Clock */
+ __HAL_RCC_AFIO_CLK_ENABLE();
+ temp = AFIO->EXTICR[position >> 2];
+ CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ AFIO->EXTICR[position >> 2] = temp;
+
+
+ /* Configure the interrupt mask */
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ SET_BIT(EXTI->IMR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->IMR, iocurrent);
+ }
+
+ /* Configure the event mask */
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ SET_BIT(EXTI->EMR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->EMR, iocurrent);
+ }
+
+ /* Enable or disable the rising trigger */
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ SET_BIT(EXTI->RTSR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->RTSR, iocurrent);
+ }
+
+ /* Enable or disable the falling trigger */
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ SET_BIT(EXTI->FTSR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->FTSR, iocurrent);
+ }
+ }
+ }
+ }
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t tmp = 0x00;
+ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+ uint32_t registeroffset = 0;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Check if the current bit belongs to first half or last half of the pin count number
+ in order to address CRH or CRL register */
+ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+
+ /* CRL/CRH default value is floating input(0x04) shifted to correct position */
+ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
+
+ /* ODR default value is 0 */
+ CLEAR_BIT(GPIOx->ODR, iocurrent);
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = AFIO->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ {
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
+
+ /* Clear EXTI line configuration */
+ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the GPIOs.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_BIT_RESET: to clear the port pin
+ * @arg GPIO_BIT_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+ }
+}
+
+/**
+ * @brief Toggles the specified GPIO pin
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief Locks GPIO Pins configuration registers.
+* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
+* has been applied on a port bit, it is no longer possible to modify the value of the port bit until
+* the next reset.
+* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+* @param GPIO_Pin: specifies the port bit to be locked.
+* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+* @retval None
+*/
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ SET_BIT(tmp, GPIO_Pin);
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief This function handles EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.h
new file mode 100644
index 000000000..b5e045301
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.h
@@ -0,0 +1,324 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_H
+#define __STM32F1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_speed_define GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
+#define GPIO_SPEED_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
+#define GPIO_SPEED_HIGH (GPIO_CRL_MODE0) /*!< High speed */
+
+/**
+ * @}
+ */
+
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || \
+ ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_HIGH))
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/* IO operation functions *******************************************************/
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.c
new file mode 100644
index 000000000..295c5541d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.c
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief GPIO Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral extension features #####
+ ==============================================================================
+ [..] GPIO module on STM32F1 family, manage also the AFIO register:
+ (+) Possibility to use the EVENTOUT Cortex feature
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to use EVENTOUT Cortex feature
+ (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+ (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+ (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+ (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+ (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
+ * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
+ * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
+ * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
+ * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
+ * @retval None
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
+{
+ /* Verify the parameters */
+ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
+ assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
+
+ /* Apply the new configuration */
+ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource));
+}
+
+/**
+ * @brief Enables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_EnableEventout(void)
+{
+ SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @brief Disables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_DisableEventout(void)
+{
+ CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h
new file mode 100644
index 000000000..036114ae8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h
@@ -0,0 +1,887 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_EX_H
+#define __STM32F1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
+ * @brief This section propose definition to use the Cortex EVENTOUT signal.
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
+#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
+#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
+#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
+#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
+#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
+#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
+#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
+#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
+#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
+#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_E))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @note ENABLE: Remap (TX/PB6, RX/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @note DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @note DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @note DISABLE: TIM5_CH4 is connected to PA3
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_MII() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
+#endif
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+#endif
+
+#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note ENABLE: PTP_PPS is output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note DISABLE: PTP_PPS not output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @note ENABLE: Remap (TIM10_CH1 on PF6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @note DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @note ENABLE: Remap (TIM11_CH1 on PF7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @note DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @note ENABLE: Remap (TIM16_CH1 on PA6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @note DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @note ENABLE: Remap (TIM17_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @note DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @note ENABLE: Remap (CEC on PB10).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @note DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
+ * @{
+ */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :3U)
+#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :4U)
+#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :6U)
+#endif
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIOEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
+void HAL_GPIOEx_EnableEventout(void);
+void HAL_GPIOEx_DisableEventout(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.c
new file mode 100644
index 000000000..2031a3bb8
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.c
@@ -0,0 +1,1173 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_hcd.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief HCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Declare a HCD_HandleTypeDef handle structure, for example:
+ HCD_HandleTypeDef hhcd;
+
+ (#)Fill parameters of Init structure in HCD handle
+
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+ (##) Enable the HCD/USB Low Level interface clock using the following macro
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure HCD pin-out
+ (##) Configure HCD NVIC interrupt
+
+ (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+ (##) hhcd.pData = phost;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_HCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+
+#ifdef HAL_HCD_MODULE_ENABLED
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @defgroup HCD HCD
+ * @brief HCD HAL module driver
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function ----------------------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the host driver
+ * @param hhcd: HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{
+ /* Check the HCD handle allocation */
+ if(hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+ if(hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhcd-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_HCD_MspInit(hhcd);
+ }
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+ /* Disable the Interrupts */
+ __HAL_HCD_DISABLE(hhcd);
+
+ /*Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE);
+
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+
+ hhcd->State= HAL_HCD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize a host channel
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param epnum: Endpoint number.
+ * This parameter can be a value from 1 to 15
+ * @param dev_address : Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed: Current device speed.
+ * This parameter can be one of these values:
+ * HCD_SPEED_FULL: Full speed mode,
+ * HCD_SPEED_LOW: Low speed mode
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type,
+ * EP_TYPE_ISOC: Isochronous type,
+ * EP_TYPE_BULK: Bulk type,
+ * EP_TYPE_INTR: Interrupt type
+ * @param mps: Max Packet Size.
+ * This parameter can be a value from 0 to32K
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(hhcd);
+
+ hhcd->hc[ch_num].dev_addr = dev_address;
+ hhcd->hc[ch_num].max_packet = mps;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].ep_type = ep_type;
+ hhcd->hc[ch_num].ep_num = epnum & 0x7F;
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+ hhcd->hc[ch_num].speed = speed;
+
+ status = USB_HC_Init(hhcd->Instance,
+ ch_num,
+ epnum,
+ dev_address,
+ speed,
+ ep_type,
+ mps);
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief Halt a host channel
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num)
+{
+ __HAL_LOCK(hhcd);
+ USB_HC_Halt(hhcd->Instance, ch_num);
+ __HAL_UNLOCK(hhcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the host driver
+ * @param hhcd: HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* Check the HCD handle allocation */
+ if(hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_HCD_MspDeInit(hhcd);
+
+ __HAL_HCD_DISABLE(hhcd);
+
+ hhcd->State = HAL_HCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the HCD MSP.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes HCD MSP.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
+ * @brief HCD IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the USB Host Data
+ Transfer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Submit a new URB for processing
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param direction: Channel number.
+ * This parameter can be one of these values:
+ * 0 : Output / 1 : Input
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type/
+ * EP_TYPE_ISOC: Isochronous type/
+ * EP_TYPE_BULK: Bulk type/
+ * EP_TYPE_INTR: Interrupt type/
+ * @param token: Endpoint Type.
+ * This parameter can be one of these values:
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1
+ * @param pbuff: pointer to URB data
+ * @param length: Length of URB data
+ * @param do_ping: activate do ping protocol (for high speed only).
+ * This parameter can be one of these values:
+ * 0 : do ping inactive / 1 : do ping active
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t direction ,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping)
+{
+ hhcd->hc[ch_num].ep_is_in = direction;
+ hhcd->hc[ch_num].ep_type = ep_type;
+
+ if(token == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+
+ /* Manage Data Toggle */
+ switch(ep_type)
+ {
+ case EP_TYPE_CTRL:
+ if((token == 1) && (direction == 0)) /*send data */
+ {
+ if ( length == 0 )
+ { /* For Status OUT stage, Length==0, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1;
+ }
+
+ /* Set the Data Toggle bit as per the Flag */
+ if ( hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ }
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
+ {
+ hhcd->hc[ch_num].do_ping = do_ping;
+ }
+ }
+ break;
+
+ case EP_TYPE_BULK:
+ if(direction == 0)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if ( hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ }
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
+ {
+ hhcd->hc[ch_num].do_ping = do_ping;
+ }
+ }
+ else
+ {
+ if( hhcd->hc[ch_num].toggle_in == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ break;
+
+ case EP_TYPE_INTR:
+ if(direction == 0)
+ {
+ /* Set the Data Toggle bit as per the Flag */
+ if ( hhcd->hc[ch_num].toggle_out == 0)
+ { /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ { /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ }
+ }
+ else
+ {
+ if( hhcd->hc[ch_num].toggle_in == 0)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
+ break;
+
+ case EP_TYPE_ISOC:
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ break;
+ }
+
+ hhcd->hc[ch_num].xfer_buff = pbuff;
+ hhcd->hc[ch_num].xfer_len = length;
+ hhcd->hc[ch_num].urb_state = URB_IDLE;
+ hhcd->hc[ch_num].xfer_count = 0 ;
+ hhcd->hc[ch_num].ch_num = ch_num;
+ hhcd->hc[ch_num].state = HC_IDLE;
+
+ return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]));
+}
+
+/**
+ * @brief This function handles HCD interrupt request.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+
+ uint32_t index = 0 , interrupt = 0;
+
+ /* ensure that we are in device mode */
+ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+ {
+ /* avoid spurious interrupt */
+ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ {
+ return;
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+ }
+
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ /* Handle Host Disconnect Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+ {
+
+ /* Cleanup HPRT */
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ /* Handle Host Port Interrupts */
+ HAL_HCD_Disconnect_Callback(hhcd);
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+ }
+
+ /* Handle Host Port Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+ {
+ HCD_Port_IRQHandler (hhcd);
+ }
+
+ /* Handle Host SOF Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+ {
+ HAL_HCD_SOF_Callback(hhcd);
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Host channel Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+ {
+ interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+ for (index = 0; index < hhcd->Init.Host_channels ; index++)
+ {
+ if (interrupt & (1 << index))
+ {
+ if ((USBx_HC(index)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
+ {
+ HCD_HC_IN_IRQHandler (hhcd, index);
+ }
+ else
+ {
+ HCD_HC_OUT_IRQHandler (hhcd, index);
+ }
+ }
+ }
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+ }
+
+ /* Handle Rx Queue Level Interrupts */
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ HCD_RXQLVL_IRQHandler (hhcd);
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
+ }
+}
+
+/**
+ * @brief SOF callback.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_SOF_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connexion Event callback.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Connect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disonnexion Event callback.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Notify URB state change callback.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param urb_state:
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
+ * @retval None
+ */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the HCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the host driver
+ * @param hhcd: HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ __HAL_HCD_ENABLE(hhcd);
+ USB_DriveVbus(hhcd->Instance, 1);
+ __HAL_UNLOCK(hhcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the host driver
+ * @param hhcd: HCD handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{
+ __HAL_LOCK(hhcd);
+ USB_StopHost(hhcd->Instance);
+ __HAL_UNLOCK(hhcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the host port
+ * @param hhcd: HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HCD state
+ * @param hhcd: HCD handle
+ * @retval HAL state
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+ return hhcd->State;
+}
+
+/**
+ * @brief Return URB state for a channel
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval URB state.
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
+ */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+ * @brief Return the last host transfer size
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval last transfer size in byte
+ */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].xfer_count;
+}
+
+/**
+ * @brief Return the Host Channel state
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval Host channel state
+ * This parameter can be one of the these values:
+ * HC_IDLE/
+ * HC_XFRC/
+ * HC_HALTED/
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR/
+ */
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ return hhcd->hc[chnum].state;
+}
+
+/**
+ * @brief Return the current Host frame number
+ * @param hhcd: HCD handle
+ * @retval Current Host frame number
+ */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+ * @brief Return the Host enumeration speed
+ * @param hhcd: HCD handle
+ * @retval Enumeration speed
+ */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+ return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup HCD_Private_Functions
+ * @{
+ */
+/**
+ * @brief This function handles Host Channel IN interrupt requests.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval none
+ */
+static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ hhcd->hc[chnum].state = HC_STALL;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ hhcd->hc[chnum].state = HC_DATATGLERR;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ }
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ {
+ hhcd->hc[chnum].state = HC_XFRC;
+ hhcd->hc[chnum].ErrCnt = 0;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+
+ }
+ else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+ hhcd->hc[chnum].toggle_in ^= 1;
+
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ {
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
+ if(hhcd->hc[chnum].state == HC_XFRC)
+ {
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ }
+ else if (hhcd->hc[chnum].state == HC_STALL)
+ {
+ hhcd->hc[chnum].urb_state = URB_STALL;
+ }
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+ (hhcd->hc[chnum].state == HC_DATATGLERR))
+ {
+ if(hhcd->hc[chnum].ErrCnt++ > 3)
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ /* re-activate the channel */
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ hhcd->hc[chnum].ErrCnt++;
+ hhcd->hc[chnum].state = HC_XACTERR;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ {
+ if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+ else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ /* re-activate the channel */
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+
+ }
+ hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ }
+}
+
+/**
+ * @brief This function handles Host Channel OUT interrupt requests.
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval none
+ */
+static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+ if( hhcd->hc[chnum].do_ping == 1)
+ {
+ hhcd->hc[chnum].state = HC_NYET;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[chnum].state = HC_NYET;
+ hhcd->hc[chnum].ErrCnt= 0;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+ hhcd->hc[chnum].state = HC_XFRC;
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ {
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_STALL;
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_XACTERR;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ hhcd->hc[chnum].state = HC_DATATGLERR;
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ {
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
+ if(hhcd->hc[chnum].state == HC_XFRC)
+ {
+ hhcd->hc[chnum].urb_state = URB_DONE;
+ if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+ {
+ hhcd->hc[chnum].toggle_out ^= 1;
+ }
+ }
+ else if (hhcd->hc[chnum].state == HC_NAK)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+ else if (hhcd->hc[chnum].state == HC_NYET)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[chnum].do_ping = 0;
+ }
+ else if (hhcd->hc[chnum].state == HC_STALL)
+ {
+ hhcd->hc[chnum].urb_state = URB_STALL;
+ }
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+ (hhcd->hc[chnum].state == HC_DATATGLERR))
+ {
+ if(hhcd->hc[chnum].ErrCnt++ > 3)
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ /* re-activate the channel */
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
+
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+}
+
+/**
+ * @brief This function handles Rx Queue Level interrupt requests.
+ * @param hhcd: HCD handle
+ * @retval none
+ */
+static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint8_t channelnum =0;
+ uint32_t pktsts;
+ uint32_t pktcnt;
+ uint32_t temp = 0;
+
+ temp = hhcd->Instance->GRXSTSP;
+ channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+
+ switch (pktsts)
+ {
+ case GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
+ {
+ USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
+
+ /*manage multiple Xfer */
+ hhcd->hc[channelnum].xfer_buff += pktcnt;
+ hhcd->hc[channelnum].xfer_count += pktcnt;
+
+ if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+ {
+ /* re-activate the channel when more packets are expected */
+ USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ hhcd->hc[channelnum].toggle_in ^= 1;
+ }
+ }
+ break;
+
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ break;
+
+ case GRXSTS_PKTSTS_IN_XFER_COMP:
+ case GRXSTS_PKTSTS_CH_HALTED:
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief This function handles Host Port interrupt requests.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ __IO uint32_t hprt0 = 0, hprt0_dup = 0;
+
+ /* Handle Host Port Interrupts */
+ hprt0 = USBx_HPRT0;
+ hprt0_dup = USBx_HPRT0;
+
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ /* Check whether Port Connect Detected */
+ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+ {
+ if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+ HAL_HCD_Connect_Callback(hhcd);
+ }
+ hprt0_dup |= USB_OTG_HPRT_PCDET;
+ }
+
+ /* Check whether Port Enable Changed */
+ if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+
+ if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+ {
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+ {
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+ }
+ else
+ {
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ }
+ HAL_HCD_Connect_Callback(hhcd);
+ }
+ else
+ {
+ /* Cleanup HPRT */
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+ }
+ }
+
+ /* Check For an over current */
+ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+ {
+ hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+ }
+
+ /* Clear Port Interrupts */
+ USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.h
new file mode 100644
index 000000000..b811be1eb
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.h
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_hcd.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of HCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_HCD_H
+#define __STM32F1xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_usb.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief HCD Status structure definition
+ */
+typedef enum
+{
+ HAL_HCD_STATE_RESET = 0x00,
+ HAL_HCD_STATE_READY = 0x01,
+ HAL_HCD_STATE_ERROR = 0x02,
+ HAL_HCD_STATE_BUSY = 0x03,
+ HAL_HCD_STATE_TIMEOUT = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
+
+/**
+ * @brief HCD Handle Structure definition
+ */
+typedef struct
+{
+ HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_InitTypeDef Init; /*!< HCD required parameters */
+ HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */
+ void *pData; /*!< Pointer Stack Handler */
+} HCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+ * @{
+ */
+/** @defgroup HCD_Speed HCD Speed
+ * @{
+ */
+#define HCD_SPEED_LOW 2
+#define HCD_SPEED_FULL 3
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num);
+
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t pipe,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+/**
+ * @}
+ */
+/* Peripheral Control functions **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+/* Peripheral State functions ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+ * @{
+ */
+/** @defgroup HCD_Instance_definition HCD Instance definition
+ * @{
+ */
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.c
new file mode 100644
index 000000000..73e573327
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.c
@@ -0,0 +1,3829 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_i2c.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) The I2C interrupts should have the highest priority in the application in order
+ to make them uninterruptible.
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) The I2C interrupts should have the highest priority in the application in order
+ to make them uninterruptible.
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+
+ *** I2C Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
+ (@) See ErrataSheet to know full silicon limitation list of your product.
+
+ (#) Workarounds Implemented inside I2C HAL Driver
+ (##) Wrong data read into data register (Polling and Interrupt mode)
+ (##) Start cannot be generated after a misplaced Stop
+ (##) Some software events must be managed before the current byte is being transferred:
+ Workaround: Use DMA in general, except when the Master is receiving a single byte.
+ For Interupt mode, I2C should have the highest priority in the application.
+ (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
+ Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
+ supported by the slave.
+ (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
+ Workaround: If the slave device allows it, use the clock stretching mechanism
+ by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */
+#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
+
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+
+static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Communication Speed
+ (++) Duty cycle
+ (++) Addressing mode
+ (++) Own Address 1
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and create the associated handle.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t freqrange = 0;
+ uint32_t pclk1 = 0;
+
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
+ assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if(hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_I2C_MspInit(hi2c);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get PCLK1 frequency */
+ pclk1 = HAL_RCC_GetPCLK1Freq();
+
+ /* Calculate frequency range */
+ freqrange = I2C_FREQ_RANGE(pclk1);
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->CR2 = freqrange;
+
+ /*---------------------------- I2Cx TRISE Configuration --------------------*/
+ /* Configure I2Cx: Rise Time */
+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+
+ /*---------------------------- I2Cx CCR Configuration ----------------------*/
+ /* Configure I2Cx: Speed */
+ hi2c->Instance->CCR = I2C_Configure_Speed(hi2c, pclk1);
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Configure I2Cx: Own Address1 and addressing mode */
+ hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2C peripheral.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->State = HAL_I2C_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2C MSP Init.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C MSP DeInit
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ while(Size > 0)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+ }
+ }
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
+ software sequence must complete before the current byte end of transfer */
+ __disable_irq();
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Re-enable IRQs */
+ __enable_irq();
+ }
+ else if(Size == 2)
+ {
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
+ software sequence must complete before the current byte end of transfer */
+ __disable_irq();
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Re-enable IRQs */
+ __enable_irq();
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(Size > 0)
+ {
+ if(Size <= 3)
+ {
+ /* One byte */
+ if(Size == 1)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ /* Two bytes */
+ else if(Size == 2)
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
+ software sequence must complete before the current byte end of transfer */
+ __disable_irq();
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Re-enable IRQs */
+ __enable_irq();
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ /* 3 Last bytes */
+ else
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
+ software sequence must complete before the current byte end of transfer */
+ __disable_irq();
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Re-enable IRQs */
+ __enable_irq();
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ }
+ else
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ }
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* If 10bit addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+ }
+ }
+
+ /* Wait until AF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ {
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ }
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(hi2c->XferCount == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if(hi2c->XferCount == 2)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+ /* Send Slave Address */
+ if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
+ else
+ {
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ }
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If 7bit addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*pData++);
+ Size--;
+ }
+ }
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if(Size == 2)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while(Size > 0)
+ {
+ if(Size <= 3)
+ {
+ /* One byte */
+ if(Size== 1)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ /* Two bytes */
+ else if(Size == 2)
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ /* 3 Last bytes */
+ else
+ {
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ }
+ else
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*pData++) = hi2c->Instance->DR;
+ Size--;
+ }
+ }
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(hi2c->XferCount == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if(hi2c->XferCount == 2)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfert complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
+ else
+ {
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ }
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param Trials: Number of trials
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR or AF flag are set */
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ tmp3 = hi2c->State;
+ while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hi2c->State = HAL_I2C_STATE_TIMEOUT;
+ }
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ tmp3 = hi2c->State;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if the ADDR flag has been set */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear ADDR Flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear AF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }while(I2C_Trials++ < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0;
+ /* Master mode selected */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET)
+ {
+ /* I2C in mode Transmitter -----------------------------------------------*/
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+ tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+ tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ {
+ I2C_MasterTransmit_TXE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if((tmp3 == SET) && (tmp4 == SET))
+ {
+ I2C_MasterTransmit_BTF(hi2c);
+ }
+ }
+ /* I2C in mode Receiver --------------------------------------------------*/
+ else
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+ tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+ tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+ /* RXNE set and BTF reset -----------------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ {
+ I2C_MasterReceive_RXNE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if((tmp3 == SET) && (tmp4 == SET))
+ {
+ I2C_MasterReceive_BTF(hi2c);
+ }
+ }
+ }
+ /* Slave mode selected */
+ else
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
+ tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
+ /* ADDR set --------------------------------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET))
+ {
+ I2C_Slave_ADDR(hi2c);
+ }
+ /* STOPF set --------------------------------------------------------------*/
+ else if((tmp3 == SET) && (tmp2 == SET))
+ {
+ I2C_Slave_STOPF(hi2c);
+ }
+ /* I2C in mode Transmitter -----------------------------------------------*/
+ else if(tmp4 == SET)
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+ tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+ tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ {
+ I2C_SlaveTransmit_TXE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if((tmp3 == SET) && (tmp4 == SET))
+ {
+ I2C_SlaveTransmit_BTF(hi2c);
+ }
+ }
+ /* I2C in mode Receiver --------------------------------------------------*/
+ else
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+ tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+ tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+ /* RXNE set and BTF reset ----------------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ {
+ I2C_SlaveReceive_RXNE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if((tmp3 == SET) && (tmp4 == SET))
+ {
+ I2C_SlaveReceive_BTF(hi2c);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+ /* I2C Bus error interrupt occurred ----------------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+ /* Workaround: Start cannot be generated after a misplaced Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
+ }
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+ /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+ /* I2C Acknowledge failure error interrupt occurred ------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET))
+ {
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL);
+ tmp2 = hi2c->XferCount;
+ tmp3 = hi2c->State;
+ if((tmp1 == RESET) && (tmp2 == 0) && (tmp3 == HAL_I2C_STATE_BUSY_TX))
+ {
+ I2C_Slave_AF(hi2c);
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
+ tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+ /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
+ if((tmp1 == SET) && (tmp2 == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Disable Pos bit in I2C CR1 when error occured in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callbacks.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the I2C state.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->State;
+}
+
+/**
+ * @brief Return the I2C error code
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Handle TXE flag for Master Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+
+ if(hi2c->XferCount == 0)
+ {
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Master Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t tmp = 0;
+
+ tmp = hi2c->XferCount;
+ if(tmp > 3)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ else if((tmp == 2) || (tmp == 3))
+ {
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+ }
+ else
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount == 3)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ else if(hi2c->XferCount == 2)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Disable EVT and ERR interrupt */
+ /* Workaround - Wong data read into data register */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ else
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TXE flag for Slave Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave Transmit Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Slave Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave Receive Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->XferCount != 0)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD flag for Slave
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
+{
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle STOPF flag for Slave Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
+{
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear STOPF flag */
+ __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Acknowledge Failed for Slave Mode
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
+{
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+{
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+ }
+ else
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+ /* Wait until ADD10 flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+ }
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+{
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+ }
+ else
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+ /* Wait until ADD10 flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Restart */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
+ }
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address
+ * @param MemAddress: Internal memory address
+ * @param MemAddSize: Size of internal memory address
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TXE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Generate Restart */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until BTF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until AF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Disable Last DMA */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Clear STOPF flag */
+ __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Write process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until BTF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Read process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Disable Last DMA */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable DMA Request */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ hi2c->XferCount = 0;
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Configuration Speed function
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param I2CClkSrcFreq: PCLK frequency from RCC.
+ * @retval CCR Speed: Speed to set in I2C CCR Register
+ */
+static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq)
+{
+ uint32_t tmp1 = 0;
+
+ /* Clock Standard Mode */
+ if(hi2c->Init.ClockSpeed <= I2C_STANDARD_MODE_MAX_CLK)
+ {
+ /* Calculate Value to be set in CCR register */
+ tmp1 = (I2CClkSrcFreq/(hi2c->Init.ClockSpeed << 1));
+
+ /* The minimum allowed value set in CCR register is 0x04 for Standard Mode */
+ if( (tmp1 & I2C_CCR_CCR) < 4 )
+ {
+ return 4;
+ }
+ else
+ {
+ return tmp1;
+ }
+ }
+ else
+ {
+ /* Clock Fast Mode */
+ tmp1 = I2C_CCR_FS;
+
+ /* Duty Cylce tLow/tHigh = 2 */
+ if(hi2c->Init.DutyCycle == I2C_DUTYCYCLE_2)
+ {
+ tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 3)) | I2C_DUTYCYCLE_2;
+ }
+ else /* Duty Cylce tLow/tHigh = 16/9 */
+ {
+ tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 25)) | I2C_DUTYCYCLE_16_9;
+ }
+
+ /* The minimum allowed value set in CCR register is 0x01 for Fast Mode */
+ if( (tmp1 & I2C_CCR_CCR) < 1 )
+ {
+ return 1;
+ }
+ else
+ {
+ return tmp1;
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ HAL_I2C_ErrorCallback(hi2c);
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag: specifies the I2C flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for Master addressing phase.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag: specifies the I2C flag to check.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear AF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.h
new file mode 100644
index 000000000..16e8b1e0c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.h
@@ -0,0 +1,582 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_i2c.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_I2C_H
+#define __STM32F1xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
+ HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief I2C handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO uint32_t ErrorCode; /* I2C Error code */
+
+}I2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_Error_Codes I2C Error Codes
+ * @{
+ */
+
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x01) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x02) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x04) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x08) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C Duty Cycle
+ * @{
+ */
+#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @brief I2C Interrupt definition
+ * - 0001XXXX : Flag control mask for SR1 Register
+ * - 0010XXXX : Flag control mask for SR2 Register
+ * @{
+ */
+#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
+#define I2C_FLAG_PECERR ((uint32_t)0x00011000)
+#define I2C_FLAG_OVR ((uint32_t)0x00010800)
+#define I2C_FLAG_AF ((uint32_t)0x00010400)
+#define I2C_FLAG_ARLO ((uint32_t)0x00010200)
+#define I2C_FLAG_BERR ((uint32_t)0x00010100)
+#define I2C_FLAG_TXE ((uint32_t)0x00010080)
+#define I2C_FLAG_RXNE ((uint32_t)0x00010040)
+#define I2C_FLAG_STOPF ((uint32_t)0x00010010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
+#define I2C_FLAG_BTF ((uint32_t)0x00010004)
+#define I2C_FLAG_ADDR ((uint32_t)0x00010002)
+#define I2C_FLAG_SB ((uint32_t)0x00010001)
+#define I2C_FLAG_DUALF ((uint32_t)0x00100080)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
+#define I2C_FLAG_TRA ((uint32_t)0x00100004)
+#define I2C_FLAG_BUSY ((uint32_t)0x00100002)
+#define I2C_FLAG_MSL ((uint32_t)0x00100001)
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enable the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
+
+/** @brief Disable the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
+
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag
+ * @arg I2C_FLAG_RXNE: Data register not empty flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg I2C_FLAG_SB: Start bit flag
+ * @arg I2C_FLAG_DUALF: Dual flag
+ * @arg I2C_FLAG_SMBHOST: SMBus host header
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ * @arg I2C_FLAG_GENCALL: General call header flag
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HANDLE__)->Instance->SR1 = (((__HANDLE__)->Instance->SR1) & (~((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief Clears the I2C ADDR pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+}while(0)
+
+/** @brief Clears the I2C STOPF pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+}while(0)
+
+/** @brief Enable the specified I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions *************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_STANDARD_MODE_MAX_CLK ((uint32_t)100000) /* Standard Clock Up to 100kHz */
+#define I2C_FAST_MODE_MAX_CLK ((uint32_t)400000) /* Fast Clock up to 400kHz */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_FAST_MODE_MAX_CLK))
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+
+#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= I2C_STANDARD_MODE_MAX_CLK) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+/**
+ * @}
+ */
+
+/* Private Fonctions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f1xx_hal_i2c.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c
new file mode 100644
index 000000000..a23967cfe
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c
@@ -0,0 +1,1435 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_i2s.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follow:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx Channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Channel.
+ (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
+ For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
+ in order to achieve the maximum accuracy.
+ -@- Make sure that either:
+ (+@) External clock source is configured after setting correctly
+ the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+
+ *** I2C Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ (@) Only the 16-bit mode with no data extension can be used when the I2S
+ is in Master and used the PCM long synchronization mode.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0, i2sclk = 0;
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+
+ if(hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+ {
+ i2sodd = (uint32_t)0;
+ i2sdiv = (uint32_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ if(hi2s->Instance == SPI2)
+ {
+ /* Get the source clock value: based on SPI2 Instance */
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
+ }
+ else if(hi2s->Instance == SPI3)
+ {
+ /* Get the source clock value: based on SPI3 Instance */
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
+ }
+ else
+ {
+ /* Get the source clock value: based on System Clock value */
+ i2sclk = HAL_RCC_GetSysClockFreq();
+ }
+ if(i2sclk == 0)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
+ hi2s->Init.Standard | hi2s->Init.DataFormat |\
+ hi2s->Init.CPOL));
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->pTxBuffPtr = pData;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Wait until TXE flag is set, to confirm the end of the transcation */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->pRxBuffPtr = pData;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0)
+ {
+ /* Wait until RXNE flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ return HAL_ERROR;
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Transmit data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set the I2S Tx DMA Half transfert complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfert complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Channel */
+ HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+
+ /* Set the I2S Rx DMA Half transfert complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfert complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Channel */
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA Channel tx */
+ if(hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA Channel rx */
+ if(hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmarx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t i2ssr = hi2s->Instance->SR;
+
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
+ ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ return;
+ }
+
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ return;
+ }
+
+ /* I2S interrupt error -------------------------------------------------*/
+ if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
+ {
+ /* I2S Overrun error interrupt occured ---------------------------------*/
+ if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+
+ /* I2S Underrun error interrupt occured --------------------------------*/
+ if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call the Error Callback */
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0;
+ hi2s->RxXferCount = 0;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
+}
+
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag: Flag checked
+ * @param Status: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.h
new file mode 100644
index 000000000..e81d8ede7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.h
@@ -0,0 +1,475 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_i2s.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_I2S_H
+#define __STM32F1xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /* I2S registers base address */
+
+ I2S_InitTypeDef Init; /* I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /* I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+
+ __IO uint32_t ErrorCode; /* I2S Error code */
+
+}I2S_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_Error_Codes I2S Error Codes
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */
+#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000)
+#define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
+ SPI_I2SCFGR_I2SCFG_1))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000)
+#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
+ SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
+ SPI_I2SCFGR_I2SSTD_1 |\
+ SPI_I2SCFGR_PCMSYNC))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition I2S Flag definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Enable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief Disable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
+ tmpreg = (__HANDLE__)->Instance->SR;\
+ UNUSED(tmpreg); \
+ }while(0)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/* Private Fonctions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f1xx_hal_i2s.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.c
new file mode 100644
index 000000000..8ed510c45
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.c
@@ -0,0 +1,1548 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_irda.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA SIR ENDEC block (IrDA):
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure.
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) IRDA pins configuration:
+ (+++) Enable the clock for the IRDA GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
+
+ (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
+ and Mode(Receiver/Transmitter) in the hirda Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief HAL IRDA module driver
+ * @{
+ */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF
+#define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF
+
+#define IRDA_DR_MASK_U8_7DATABITS (uint8_t)0x7F
+#define IRDA_DR_MASK_U8_8DATABITS (uint8_t)0xFF
+
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in IrDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible IRDA frame formats are as listed in the following table:
+ (+++) +-------------------------------------------------------------+
+ (+++) | M bit | PCE bit | IRDA frame |
+ (+++) |---------------------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +-------------------------------------------------------------+
+ (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
+ not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
+ specification specifies a minimum of 10 ms delay between transmission and
+ reception (IrDA is a half duplex protocol).
+ (++) Mode: Receiver/transmitter modes
+ (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
+
+ [..]
+ The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures
+ are available in reference manuals (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and create the associated handle.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the IRDA instance parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+ /* Check the IRDA mode parameter in the IRDA handle */
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
+
+ if(hirda->State == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the IRDA peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA communication parameters */
+ IRDA_SetConfig(hirda);
+
+ /* In IrDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+ /* Enable the IRDA peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* Set the prescaler */
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /* Configure the IrDA mode */
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
+
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
+
+ /* Initialize the IRDA state*/
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the IRDA peripheral
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->State = HAL_IRDA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief IRDA MSP Init.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA MSP DeInit.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0)
+ {
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS));
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ pData +=2;
+ }
+ else
+ {
+ pData +=1;
+ }
+ }
+ else
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS));
+ }
+ hirda->TxXferCount--;
+ }
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(hirda->RxXferCount > 0)
+ {
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData ;
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
+ pData +=2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
+ pData +=1;
+ }
+ }
+ else
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
+ }
+ }
+ hirda->RxXferCount--;
+ }
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non-blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non-blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Data Register not empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
+
+ /* Enable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non-blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfert complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the IRDA transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfert complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Disable the IRDA DMA Tx & Rx requests */
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Tx & Rx request */
+ SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+ */
+
+ /* Disable the IRDA Tx/Rx DMA requests */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ /* Abort the IRDA DMA rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ hirda->State = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles IRDA interrupt request.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmp_flag = 0, tmp_it_source = 0;
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
+ tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
+ /* IRDA parity error interrupt occurred -----------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_IRDA_CLEAR_PEFLAG(hirda);
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
+ tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
+ /* IRDA frame error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_IRDA_CLEAR_FEFLAG(hirda);
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
+ /* IRDA noise error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_IRDA_CLEAR_NEFLAG(hirda);
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
+ /* IRDA Over-Run interrupt occurred ---------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* Disable PE and ERR interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
+ tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
+ /* IRDA in mode Receiver --------------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
+ tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
+ /* IRDA in mode Transmitter -----------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ }
+
+ tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
+ tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callbacks.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA error callbacks.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral.
+ (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the IRDA state.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->State;
+}
+
+/**
+ * @brief Return the IRDA error code
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @brief IRDA Private functions
+ * @{
+ */
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief This function handles IRDA Communication Timeout.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag: specifies the IRDA flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT()
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_BUSY_TX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS));
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ hirda->pTxBuffPtr += 2;
+ }
+ else
+ {
+ hirda->pTxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS));
+ }
+
+ if(--hirda->TxXferCount == 0)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hirda->State;
+ if((tmp_state == HAL_IRDA_STATE_BUSY_RX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+ if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr;
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
+ hirda->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
+ hirda->pRxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
+ }
+ }
+
+ if(--hirda->RxXferCount == 0)
+ {
+
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_MODE(hirda->Init.Mode));
+
+ /*------- IRDA-associated USART registers setting : CR2 Configuration ------*/
+ /* Clear STOP[13:12] bits */
+ CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
+
+ /*------- IRDA-associated USART registers setting : CR1 Configuration ------*/
+ /* Configure the USART Word Length, Parity and mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ MODIFY_REG(hirda->Instance->CR1,
+ ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
+ (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
+
+ /*------- IRDA-associated USART registers setting : CR3 Configuration ------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /*------- IRDA-associated USART registers setting : BRR Configuration ------*/
+ if(hirda->Instance == USART1)
+ {
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+ }
+ else
+ {
+ hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.h
new file mode 100644
index 000000000..38019764c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.h
@@ -0,0 +1,555 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_irda.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of IRDA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_IRDA_H
+#define __STM32F1xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDA_Word_Length */
+
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed
+ in the IrDA low-power Baud Register, for defining pulse width on which
+ burst acceptance/rejection will be decided. This value is used as divisor
+ of system clock to achieve required pulse width. */
+
+ uint32_t IrDAMode; /*!< Specifies the IrDA mode
+ This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State structures definition
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
+
+}IRDA_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants
+ * @{
+ */
+
+/** @defgroup IRDA_Error_Codes IRDA Error Codes
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Word_Length IRDA Word Length
+ * @{
+ */
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
+#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
+#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
+#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask (16 bits) in the Y register
+ * - Y : Interrupt source register (4 bits)
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
+ *
+ * @{
+ */
+
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief Flush the IRDA DR register
+ * @param __HANDLE__: specifies the USART Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Check whether the specified IRDA flag is set or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_FLAG_TC: Transmission Complete flag.
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ }while(0) \
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+
+/** @brief Disable the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_ERR: Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:((((__IT__) >> 28) == IRDA_CR2_REG_INDEX)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+
+/** @brief Enable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+
+/** @brief Disable UART/USART associated to IRDA Handle
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+
+#define IRDA_CR1_REG_INDEX 1
+#define IRDA_CR2_REG_INDEX 2
+#define IRDA_CR3_REG_INDEX 3
+
+#define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
+#define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100)
+#define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
+#define IRDA_BRR(__PCLK__, __BAUD__) ((IRDA_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(IRDA_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
+
+/** Ensure that IRDA Baud rate is less or equal to maximum value
+ * __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+ * The maximum Baud Rate is 115200bps
+ * Returns : True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+
+#define IS_IRDA_MODE(MODE) ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \
+ ((MODE) != (uint32_t)0x00000000))
+
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+
+/** IRDA interruptions flag mask
+ *
+ */
+#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.c
new file mode 100644
index 000000000..409548de0
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.c
@@ -0,0 +1,358 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and Configuration functions
+ * + IO operation functions
+ * + Peripheral State functions
+ @verbatim
+================================================================================
+ ##### IWDG specific features #####
+================================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+ (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
+ thus stays active even if the main clock fails.
+ (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled
+ (LSI cannot be disabled too), and the counter starts counting down from
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)
+ a system reset is generated.
+ (+) The IWDG counter should be refreshed at regular intervals, otherwise the
+ watchdog generates an MCU reset when the counter reaches 0.
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ (+) Min-max timeout value at 40KHz (LSI): 0.1us / 26.2s .
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM5 CH4 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+ For more information, please refer to the STM32F1xx Reference manual.
+ Note: LSI Calibration is only available on: High density, XL-density and Connectivity line devices.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable write access to IWDG_PR, IWDG_RLR.
+ (++) Configure the IWDG prescaler, counter reload value.
+ This reload value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (+) Use IWDG using HAL_IWDG_Start() function to :
+ (++) Reload IWDG counter with value defined in the IWDG_RLR register.
+ (++) Start the IWDG, when the IWDG is used in software mode (no need
+ to enable the LSI, it will be enabled by hardware).
+ (+) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver.
+
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
+ (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+#define IWDG_DEFAULT_TIMEOUT (uint32_t)1000
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters
+ in the IWDG_InitTypeDef and create the associated handle
+ (+) Initialize the IWDG MSP
+ (+) DeInitialize IWDG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IWDG according to the specified
+ * parameters in the IWDG_InitTypeDef and creates the associated handle.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Check the IWDG handle allocation */
+ if(hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+
+ /* Check pending flag, if previous update not done, return error */
+ if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hiwdg->State == HAL_IWDG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hiwdg-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_IWDG_MspInit(hiwdg);
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Enable write access to IWDG_PR and IWDG_RLR registers */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
+ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
+ MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the IWDG MSP.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval None
+ */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the IWDG.
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Process Locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Start the IWDG peripheral */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Reload IWDG counter with value defined in the RLR register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Refreshes the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until RVU flag is RESET */
+ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the IWDG state.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL state
+ */
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
+{
+ return hiwdg->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.h
new file mode 100644
index 000000000..88616823b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.h
@@ -0,0 +1,299 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_IWDG_H
+#define __STM32F1xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+
+}HAL_IWDG_StateTypeDef;
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+}IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+
+}IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
+ * @brief IWDG registers bit mask
+ * @{
+ */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition IWDG Flag definition
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @brief Reset IWDG handle state
+ * @param __HANDLE__: IWDG handle.
+ * @retval None
+ */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
+/**
+ * @brief Enables the IWDG peripheral.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+
+
+/**
+ * @brief Gets the selected IWDG's flag status.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+
+/**
+ * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c
new file mode 100644
index 000000000..43b916dac
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c
@@ -0,0 +1,1173 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_nand.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief NAND HAL module driver.
+ * This file provides a generic firmware to drive NAND memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
+ with NAND devices. This driver is used as follows:
+
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+ with control and timing parameters for both common and attribute spaces.
+
+ (+) Read NAND flash memory maker and device IDs using the function
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NAND flash memory by read/write operations using the functions
+ HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+ to read/write page(s)/spare area(s). These functions use specific device
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
+ structure. The read/write address information is contained by the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+ The erase block address information is contained in the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+ (+) You can monitor the NAND device HAL state by calling the function
+ HAL_NAND_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+ If a NAND flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup NAND_Private_Functions NAND Private Functions
+ * @{
+ */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NAND memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform NAND memory Initialization sequence
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ComSpace_Timing: pointer to Common space timing structure
+ * @param AttSpace_Timing: pointer to Attribute space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+ /* Check the NAND handle state */
+ if(hnand == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnand-> Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspInit(hnand);
+ }
+
+ /* Initialize NAND control Interface */
+ FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+ /* Initialize NAND common space timing Interface */
+ FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+ /* Initialize NAND attribute space timing Interface */
+ FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+ /* Enable the NAND device */
+ __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NAND memory De-Initialization sequence
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspDeInit(hnand);
+
+ /* Configure the NAND registers with their reset values */
+ FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+ /* Reset the NAND controller state */
+ hnand->State = HAL_NAND_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND MSP Init
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NAND MSP DeInit
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles NAND device interrupt request.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+ /* Check NAND interrupt Rising edge flag */
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Rising edge pending bit */
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check NAND interrupt Level flag */
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Level pending bit */
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
+ }
+
+ /* Check NAND interrupt Falling edge flag */
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Falling edge pending bit */
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check NAND interrupt FIFO empty flag */
+ if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt FIFO empty pending bit */
+ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
+ }
+
+}
+
+/**
+ * @brief NAND interrupt feature callback
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NAND
+ memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the NAND memory electronic signature
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pNAND_ID: NAND ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+ __IO uint32_t data = 0;
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+
+ /* Read the electronic signature from NAND flash */
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
+ pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
+ pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
+ pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory reset
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send NAND reset command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to destination read buffer
+ * @param NumPageToRead : number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0;
+ uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
+
+ /* Get the address offset */
+ addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numpagesread++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to source buffer to write
+ * @param NumPageToWrite : number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+
+ /* Get the address offset */
+ addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numpageswritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer: pointer to source buffer to write
+ * @param NumSpareAreaToRead: Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+
+ /* Get the address offset */
+ addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Get Data into Buffer */
+ for ( ;index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ num_spare_area_read++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to source buffer to write
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+
+ /* Get the address offset */
+ addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ num_spare_area_written++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory Block erase
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t deviceaddress = 0;
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Erase block command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory read status
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval NAND status
+ */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+ uint32_t data = 0;
+ uint32_t deviceaddress = 0;
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Send Read status operation command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+ /* Read status register data */
+ data = *(__IO uint8_t *)deviceaddress;
+
+ /* Return the status */
+ if((data & NAND_ERROR) == NAND_ERROR)
+ {
+ return NAND_ERROR;
+ }
+ else if((data & NAND_READY) == NAND_READY)
+ {
+ return NAND_READY;
+ }
+
+ return NAND_BUSY;
+}
+
+/**
+ * @brief Increment the NAND memory address
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ /* Increment page address */
+ pAddress->Page++;
+
+ /* Check NAND address is valid */
+ if(pAddress->Page == hnand->Info.BlockSize)
+ {
+ pAddress->Page = 0;
+ pAddress->Block++;
+
+ if(pAddress->Block == hnand->Info.ZoneSize)
+ {
+ pAddress->Block = 0;
+ pAddress->Zone++;
+
+ if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Enable ECC feature */
+ FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FSMC_NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Disable ECC feature */
+ FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ECCval: pointer to ECC value
+ * @param Timeout: maximum timeout to wait
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Get NAND ECC value */
+ status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NAND controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NAND state
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL state
+ */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+ return hnand->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Increment the NAND memory address.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param Address: address to be incremented.
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ Address->Page++;
+
+ if(Address->Page == hnand->Info.BlockSize)
+ {
+ Address->Page = 0;
+ Address->Block++;
+
+ if(Address->Block == hnand->Info.ZoneSize)
+ {
+ Address->Block = 0;
+ Address->Zone++;
+
+ if(Address->Zone == hnand->Info.BlockNbr)
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.h
new file mode 100644
index 000000000..b6db1c778
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.h
@@ -0,0 +1,304 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_nand.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_NAND_H
+#define __STM32F1xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_fsmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+/** @addtogroup NAND
+ * @{
+ */
+
+/** @addtogroup NAND_Private_Constants
+ * @{
+ */
+
+#define NAND_DEVICE1 FSMC_BANK2
+#define NAND_DEVICE2 FSMC_BANK3
+#define NAND_WRITE_TIMEOUT ((uint32_t)1000)
+
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
+#define NAND_BUSY ((uint32_t)0x00000000)
+#define NAND_ERROR ((uint32_t)0x00000001)
+#define NAND_READY ((uint32_t)0x00000040)
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define __ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define __ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define __ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define __ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Zone; /*!< NAND memory Zone address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of blocks */
+
+ uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
+}NAND_InfoTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FSMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
+}NAND_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c
new file mode 100644
index 000000000..1d071708c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c
@@ -0,0 +1,1050 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_nor.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief NOR HAL module driver.
+ * This file provides a generic firmware to drive NOR memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NOR flash memories. It uses the FSMC layer functions to interface
+ with NOR devices. This driver is used as follows:
+
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+ with control and timing parameters for both normal and extended mode.
+
+ (+) Read NOR flash memory manufacturer code and device IDs using the function
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NOR flash memory by read/write data unit operations using the functions
+ HAL_NOR_Read(), HAL_NOR_Program().
+
+ (+) Perform NOR flash erase block/chip operations using the functions
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+ structure declared by the function caller.
+
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+ (+) You can monitor the NOR device HAL state by calling the function
+ HAL_NOR_GetState()
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+ If a NOR flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** NOR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in NOR HAL driver.
+
+ (+) __NOR_WRITE : NOR memory write data to specified address
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
+
+/** @defgroup NOR NOR
+ * @brief NOR driver modules
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Variables NOR Private Variables
+ * @{
+ */
+
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the NOR memory Initialization sequence
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timing: pointer to NOR control timing structure
+ * @param ExtTiming: pointer to NOR extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the NOR handle parameter */
+ if(hnor == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnor->State == HAL_NOR_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnor-> Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_NOR_MspInit(hnor);
+ }
+
+ /* Initialize NOR control Interface */
+ FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+ /* Initialize NOR timing Interface */
+ FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+ /* Initialize NOR extended mode timing Interface */
+ FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+ /* Initialize NOR Memory Data Width*/
+ if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;
+ }
+ else
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NOR memory De-Initialization sequence
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_NOR_MspDeInit(hnor);
+
+ /* Configure the NOR registers with their reset values */
+ FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NOR MSP Init
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP DeInit
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP Wait fro Ready/Busy signal
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timeout: Maximum timeout value
+ * @retval None
+ */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspWait could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read NOR flash IDs
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_ID : pointer to NOR ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read ID command */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the NOR memory to Read mode.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ __NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read data from NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress: pointer to Device address
+ * @param pData : pointer to read data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read the data */
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program data to NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress: Device address
+ * @param pData : pointer to the data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send program data command */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+ /* Write the data */
+ __NOR_WRITE(pAddress, *pData);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a block of data from the FSMC NOR memory.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress: NOR memory internal address to read from.
+ * @param pData: pointer to the buffer that receives the data read from the
+ * NOR memory.
+ * @param uwBufferSize : number of Half word to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read buffer */
+ while( uwBufferSize > 0)
+ {
+ *pData++ = *(__IO uint16_t *)uwAddress;
+ uwAddress += 2;
+ uwBufferSize--;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a half-word buffer to the FSMC NOR memory. This function
+ * must be used only with S29GL128P NOR memory.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress: NOR memory internal address from which the data
+ * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
+ * 64 bytes boundary for example).
+ * @param pData: pointer to source data buffer.
+ * @param uwBufferSize: number of Half words to write.
+ * @note The maximum buffer size allowed is NOR memory dependent
+ * (can be 64 Bytes max for example).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Initialize variables */
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1);
+ lastloadedaddress = (uint32_t)(uwAddress);
+
+ /* Issue unlock command sequence */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+
+ /* Write Buffer Load Command */
+ __NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ __NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
+
+ /* Load Data into NOR Buffer */
+ while(p_currentaddress <= p_endaddress)
+ {
+ /* Store last loaded address & data value (for polling) */
+ lastloadedaddress = (uint32_t)p_currentaddress;
+
+ __NOR_WRITE(p_currentaddress, *pData++);
+
+ p_currentaddress++;
+ }
+
+ __NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the specified block of the NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param BlockAddress : Block to erase address
+ * @param Address: Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send block erase command sequence */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ __NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the entire NOR chip.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address : Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send NOR chip erase command sequence */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read NOR flash CFI IDs
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_CFI : pointer to NOR CFI IDs structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FSMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read CFI query command */
+ __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+ /* read the NOR CFI information */
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group3 Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NOR interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically NOR write operation.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Enable write operation */
+ FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NOR write operation.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the SRAM controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Disable write operation */
+ FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group4 State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NOR controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NOR controller state
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval NOR controller state
+ */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+ return hnor->State;
+}
+
+/**
+ * @brief Returns the NOR operation status.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address: Device address
+ * @param Timeout: NOR progamming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
+ */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+ uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
+ uint32_t tickstart = 0;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ HAL_NOR_MspWait(hnor, Timeout);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
+ }
+ }
+
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.h
new file mode 100644
index 000000000..f09d033f2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.h
@@ -0,0 +1,306 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_nor.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_NOR_H
+#define __STM32F1xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_fsmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
+/** @addtogroup NOR
+ * @{
+ */
+
+/** @addtogroup NOR_Private_Constants
+ * @{
+ */
+
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x10)
+#define CFI2_ADDRESS ((uint16_t)0x11)
+#define CFI3_ADDRESS ((uint16_t)0x12)
+#define CFI4_ADDRESS ((uint16_t)0x13)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x0)
+#define NOR_MEMORY_16B ((uint8_t)0x1)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 FSMC_BANK1_1
+#define NOR_MEMORY_ADRESS2 FSMC_BANK1_2
+#define NOR_MEMORY_ADRESS3 FSMC_BANK1_3
+#define NOR_MEMORY_ADRESS4 FSMC_BANK1_4
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS: NOR base address
+ * @param __NOR_MEMORY_WIDTH_: NOR memory width
+ * @param __ADDRESS__: NOR memory address
+ * @retval NOR shifted address value
+ */
+#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__: NOR memory address
+ * @param __DATA__: Data to write
+ * @retval None
+ */
+#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FSMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FSMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FSMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup NOR_Exported_macro NOR Exported Macros
+ * @{
+ */
+
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: NOR handle
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3
+ * @{
+ */
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4
+ * @{
+ */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.c
new file mode 100644
index 000000000..c482fde4e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.c
@@ -0,0 +1,742 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pccard.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief PCCARD HAL module driver.
+ * This file provides a generic firmware to drive PCCARD memories mounted
+ * as external device.
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control PCCARD/compact flash memories. It uses the FSMC/FSMC layer functions
+ to interface with PCCARD devices. This driver is used for:
+
+ (+) PCCARD/compact flash memory configuration sequence using the function
+ HAL_PCCARD_Init() with control and timing parameters for both common and
+ attribute spaces.
+
+ (+) Read PCCARD/compact flash memory maker and device IDs using the function
+ HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
+ structure declared by the function caller.
+
+ (+) Access PCCARD/compact flash memory by read/write operations using the functions
+ HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
+
+ (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
+
+ (+) Perform PCCARD/compact flash erase sector operation using the function
+ HAL_PCCARD_Erase_Sector().
+
+ (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
+
+ (+) You can monitor the PCCARD/compact flash device HAL state by calling the function
+ HAL_PCCARD_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
+ operations. If a PCCARD/compact flash device contains different operations
+ and/or implementations, it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+
+#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
+
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the PCCARD memory Initialization sequence
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param ComSpaceTiming: Common space timing structure
+ * @param AttSpaceTiming: Attribute space timing structure
+ * @param IOSpaceTiming: IO space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+{
+ /* Check the PCCARD controller state */
+ if(hpccard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpccard-> Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspInit(hpccard);
+ }
+
+ /* Initialize the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD control Interface */
+ FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+
+ /* Init PCCARD common space timing Interface */
+ FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+
+ /* Init PCCARD attribute space timing Interface */
+ FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+
+ /* Init PCCARD IO space timing Interface */
+ FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+
+ /* Enable the PCCARD device */
+ __FSMC_PCCARD_ENABLE(hpccard->Instance);
+
+ /* Update the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Perform the PCCARD memory De-initialization sequence
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspDeInit(hpccard);
+
+ /* Configure the PCCARD registers with their reset values */
+ FSMC_PCCARD_DeInit(hpccard->Instance);
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief PCCARD MSP Init
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PCCARD MSP DeInit
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Input Output and memory functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read Compact Flash's ID.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID: Compact flash ID structure.
+ * @param pStatus: pointer to compact flash status
+ * @retval HAL status
+ *
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize the CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Send the Identify Command */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
+
+ /* Read CF IDs and timeout treatment */
+ do
+ {
+ /* Read the CF status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+ else
+ {
+ /* Read CF ID bytes */
+ for(index = 0; index < 16; index++)
+ {
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
+ }
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read sector from PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to destination read buffer
+ * @param SectorAddress: Sector address to read
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
+
+ do
+ {
+ /* wait till the Status = 0x80 */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status == 0x80) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ timeout = 0xFFFF;
+
+ do
+ {
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Read bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Write sector to PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to source write buffer
+ * @param SectorAddress: Sector address to write
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Write bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ }
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Erase sector from PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress: Sector address to erase
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = 0x400;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
+
+ /* wait till the CF is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
+ {
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Provide an SW reset and Read and verify the:
+ - CF Configuration Option Register at address 0x98000200 --> 0x80
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
+ - Socket and Copy Register at address 0x98000206 --> 0x00
+ */
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles PCCARD device interrupt request.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+*/
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Check PCCARD interrupt Rising edge flag */
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Rising edge pending bit */
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check PCCARD interrupt Level flag */
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Level pending bit */
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
+ }
+
+ /* Check PCCARD interrupt Falling edge flag */
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Falling edge pending bit */
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check PCCARD interrupt FIFO empty flag */
+ if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt FIFO empty pending bit */
+ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
+ }
+
+}
+
+/**
+ * @brief PCCARD interrupt feature callback
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### PCCARD Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the PCCARD controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the PCCARD controller state
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
+ */
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
+{
+ return hpccard->State;
+}
+
+/**
+ * @brief Get the compact flash memory status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval New status of the CF operation. This parameter can be:
+ * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
+ * a Timeout error
+ * - CompactFlash_READY: when memory is ready for the next operation
+ *
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status_cf == PCCARD_BUSY) && timeout)
+ {
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Return the operation status */
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @brief Reads the Compact Flash memory status using the Read status command
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval The status of the Compact Flash memory. This parameter can be:
+ * - CompactFlash_BUSY: when memory is busy
+ * - CompactFlash_READY: when memory is ready for the next operation
+ * - CompactFlash_ERROR: when the previous operation gererates error
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint8_t data = 0, status_cf = PCCARD_BUSY;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ /* Read status operation */
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+ else if((data & PCCARD_READY) == PCCARD_READY)
+ {
+ status_cf = PCCARD_READY;
+ }
+
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.h
new file mode 100644
index 000000000..20a1b904e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.h
@@ -0,0 +1,249 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pccard.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PCCARD_H
+#define __STM32F1xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_fsmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+/** @addtogroup PCCARD
+ * @{
+ */
+
+/** @addtogroup PCCARD_Private_Constants
+ * @{
+ */
+
+#define PCCARD_DEVICE_ADDRESS FSMC_BANK4
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */
+
+/* Compact Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+
+/* Compact Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
+#define PCCARD_BUSY ((uint8_t)0x80)
+#define PCCARD_PROGR ((uint8_t)0x01)
+#define PCCARD_READY ((uint8_t)0x40)
+
+#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+
+/* Compact Flash redefinition */
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define CF_ERROR HAL_PCCARD_STATUS_ERROR
+#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define CF_StatusTypedef HAL_PCCARD_StatusTypeDef
+
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL PCCARD State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
+
+/**
+ * @brief FSMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__: specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.c
new file mode 100644
index 000000000..feda8f46e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.c
@@ -0,0 +1,1410 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pcd.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using the following macro
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available
+ on STM32F102xx and STM32F103xx devices
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available
+ on STM32F105xx and STM32F107xx devices
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+#if defined (USB_OTG_FS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#endif /* USB */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and create the associated handle.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t index = 0;
+
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+
+ /*Init the Core (common init.) */
+ USB_CoreInit(hpcd->Instance, hpcd->Init);
+
+ /* Force Device Mode*/
+ USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
+
+ /* Init endpoints structures */
+ for (index = 0; index < 15 ; index++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[index].is_in = 1;
+ hpcd->IN_ep[index].num = index;
+ hpcd->IN_ep[index].tx_fifo_num = index;
+ /* Control until ep is actvated */
+ hpcd->IN_ep[index].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[index].maxpacket = 0;
+ hpcd->IN_ep[index].xfer_buff = 0;
+ hpcd->IN_ep[index].xfer_len = 0;
+ }
+
+ for (index = 0; index < 15 ; index++)
+ {
+ hpcd->OUT_ep[index].is_in = 0;
+ hpcd->OUT_ep[index].num = index;
+ hpcd->IN_ep[index].tx_fifo_num = index;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[index].maxpacket = 0;
+ hpcd->OUT_ep[index].xfer_buff = 0;
+ hpcd->OUT_ep[index].xfer_len = 0;
+ }
+
+ /* Init Device */
+ USB_DevInit(hpcd->Instance, hpcd->Init);
+
+ hpcd->USB_Address = 0;
+ hpcd->State= HAL_PCD_STATE_READY;
+
+ USB_DevDisconnect (hpcd->Instance);
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ HAL_PCD_Stop(hpcd);
+
+ /* DeInit the low level hardware */
+ HAL_PCD_MspDeInit(hpcd);
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start The USB Device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ HAL_PCDEx_SetConnectionState (hpcd, 1);
+ USB_DevConnect (hpcd->Instance);
+ __HAL_PCD_ENABLE(hpcd);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop The USB Device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ __HAL_PCD_DISABLE(hpcd);
+ USB_StopDevice(hpcd->Instance);
+ USB_DevDisconnect (hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+#if defined (USB_OTG_FS)
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0;
+ uint32_t fifoemptymsk = 0, temp = 0;
+ USB_OTG_EPTypeDef *ep = NULL;
+
+ /* ensure that we are in device mode */
+ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+ {
+ /* avoid spurious interrupt */
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ {
+ return;
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ {
+ /* incorrect mode, acknowledge the interrupt */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ {
+ epnum = 0;
+
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+ while ( ep_intr )
+ {
+ if (ep_intr & 0x1)
+ {
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
+
+ if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+
+ HAL_PCD_DataOutStageCallback(hpcd, epnum);
+ }
+
+ if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+ {
+ /* Inform the upper layer that a setup packet is available */
+ HAL_PCD_SetupStageCallback(hpcd);
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+ }
+
+ if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1;
+ }
+ }
+
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ {
+ /* Read in the device interrupt bits */
+ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+ epnum = 0;
+
+ while ( ep_intr )
+ {
+ if (ep_intr & 0x1) /* In ITR */
+ {
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+
+ if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+ {
+ fifoemptymsk = 0x1 << epnum;
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+ HAL_PCD_DataInStageCallback(hpcd, epnum);
+ }
+ if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+ }
+ if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+ }
+ if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+ }
+ if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+ {
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+ }
+ if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+ {
+ PCD_WriteEmptyTxFifo(hpcd , epnum);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1;
+ }
+ }
+
+ /* Handle Resume Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ {
+ /* Clear the Remote Wake-up signalling */
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+ }
+
+ /* Handle Suspend Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ {
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+ }
+
+ /* Handle Reset Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ {
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+ USB_FlushTxFifo(hpcd->Instance , 0 );
+
+ for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
+ {
+ USBx_INEP(index)->DIEPINT = 0xFF;
+ USBx_OUTEP(index)->DOEPINT = 0xFF;
+ }
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;
+ USBx_DEVICE->DAINTMSK |= 0x10001;
+
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+
+ /* Set Default Address to 0 */
+ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+ /* setup EP0 to receive SETUP packets */
+ USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+ }
+
+ /* Handle Enumeration done Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ {
+ USB_ActivateSetup(hpcd->Instance);
+ hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+
+ hpcd->Init.speed = USB_OTG_SPEED_FULL;
+ hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
+ hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);
+
+ HAL_PCD_ResetCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+ }
+
+ /* Handle RxQLevel Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ temp = USBx->GRXSTSP;
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+ if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ {
+ if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
+ {
+ USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ }
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ {
+ USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
+ /* Handle SOF Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ {
+ HAL_PCD_SOFCallback(hpcd);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+ }
+
+ /* Handle Incomplete ISO IN Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ {
+ HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+ }
+
+ /* Handle Incomplete ISO OUT Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ {
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+ }
+
+ /* Handle Connection event Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ {
+ HAL_PCD_ConnectCallback(hpcd);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+ }
+
+ /* Handle Disconnection event Interrupt */
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ {
+ temp = hpcd->Instance->GOTGINT;
+
+ if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ {
+ HAL_PCD_DisconnectCallback(hpcd);
+ }
+ hpcd->Instance->GOTGINT |= temp;
+ }
+ }
+}
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t wInterrupt_Mask = 0;
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+ {
+ /* servicing of the endpoint correct transfer interrupt */
+ /* clear of the CTR flag into the sub */
+ PCD_EP_ISR_Handler(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+ HAL_PCD_ResetCallback(hpcd);
+ HAL_PCD_SetAddress(hpcd, 0);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+ }
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+ {
+ hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE);
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+ {
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+ /* Force low-power mode in the macrocell */
+ hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+ hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+ HAL_PCD_SOFCallback(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+ {
+ /* clear ESOF flag in ISTR */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+ }
+}
+#endif /* USB */
+
+/**
+ * @brief Data out stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ HAL_PCDEx_SetConnectionState (hpcd, 1);
+ USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+ HAL_PCDEx_SetConnectionState (hpcd, 0);
+ USB_DevDisconnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address
+ * @param hpcd: PCD handle
+ * @param address: new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+ hpcd->USB_Address = address;
+ USB_SetDevAddress(hpcd->Instance, address);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param ep_mps: endpoint max packet size
+ * @param ep_type: endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep = NULL;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+
+ __HAL_LOCK(hpcd);
+ USB_ActivateEndpoint(hpcd->Instance , ep);
+ __HAL_UNLOCK(hpcd);
+ return ret;
+}
+
+/**
+ * @brief Deactivate an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+
+ __HAL_LOCK(hpcd);
+ USB_DeactivateEndpoint(hpcd->Instance , ep);
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the reception buffer
+ * @param len: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 0;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x7F) == 0 )
+ {
+ USB_EP0StartXfer(hpcd->Instance , ep);
+ }
+ else
+ {
+ USB_EPStartXfer(hpcd->Instance , ep);
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval Data Size
+ */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the transmission buffer
+ * @param len: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 1;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x7F) == 0 )
+ {
+ USB_EP0StartXfer(hpcd->Instance , ep);
+ }
+ else
+ {
+ USB_EPStartXfer(hpcd->Instance , ep);
+ }
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 1;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ __HAL_LOCK(hpcd);
+ USB_EPSetStall(hpcd->Instance , ep);
+ if((ep_addr & 0x7F) == 0)
+ {
+ USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 0;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ __HAL_LOCK(hpcd);
+ USB_EPClearStall(hpcd->Instance , ep);
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+ }
+ else
+ {
+ USB_FlushRxFifo(hpcd->Instance);
+ }
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ return(USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ return(USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD state
+ * @param hpcd: PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private_Functions
+ * @{
+ */
+#if defined (USB_OTG_FS)
+/**
+ * @brief DCD_WriteEmptyTxFifo
+ * check FIFO for the next packet to be loaded
+ * @param hpcd: PCD handle
+ * @param epnum : endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ USB_OTG_EPTypeDef *ep = NULL;
+ int32_t len = 0;
+ uint32_t len32b = 0;
+ uint32_t fifoemptymsk = 0;
+
+ ep = &hpcd->IN_ep[epnum];
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+
+ len32b = (len + 3) / 4;
+
+ while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
+ ep->xfer_count < ep->xfer_len &&
+ ep->xfer_len != 0)
+ {
+ /* Write the FIFO */
+ len = ep->xfer_len - ep->xfer_count;
+
+ if (len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+ len32b = (len + 3) / 4;
+
+ USB_WritePacket(USBx, ep->xfer_buff, epnum, len);
+
+ ep->xfer_buff += len;
+ ep->xfer_count += len;
+ }
+
+ if(len <= 0)
+ {
+ fifoemptymsk = 0x1 << epnum;
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+ }
+
+ return HAL_OK;
+}
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+ PCD_EPTypeDef *ep = NULL;
+ uint16_t count = 0;
+ uint8_t epindex = 0;
+ __IO uint16_t wIstr = 0;
+ __IO uint16_t wEPVal = 0;
+
+ /* stay in loop while pending interrupts */
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+ {
+ /* extract highest priority endpoint number */
+ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (epindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, 0);
+
+
+ if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ {
+ hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0;
+ }
+
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0)
+ {
+ /* Get SETUP Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ /* SETUP bit kept frozen while CTR_RX = 1*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+ HAL_PCD_SetupStageCallback(hpcd);
+ }
+
+ else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ /* Get Control Data OUT Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_count != 0)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ ep->xfer_buff+=ep->xfer_count;
+ }
+
+ /* Process Control Data OUT Packet*/
+ HAL_PCD_DataOutStageCallback(hpcd, 0);
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
+ }
+ }
+ else
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+ if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+ ep = &hpcd->OUT_ep[epindex];
+
+ /* OUT double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
+ }
+ /*multi-packet on the NON control OUT endpoint*/
+ ep->xfer_count+=count;
+ ep->xfer_buff+=count;
+
+ if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ {
+ /* RX COMPLETE */
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+
+ } /* if((wEPVal & EP_CTR_RX) */
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0)
+ {
+ ep = &hpcd->IN_ep[epindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+
+ /* IN double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
+ }
+ /*multi-packet on the NON control IN endpoint*/
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff+=ep->xfer_count;
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0)
+ {
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+#endif /* USB */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F102x6 || STM32F102xB || */
+ /* STM32F103x6 || STM32F103xB || */
+ /* STM32F103xE || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.h
new file mode 100644
index 000000000..9c27289b7
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.h
@@ -0,0 +1,825 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pcd.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PCD_H
+#define __STM32F1xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_usb.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum
+{
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+#if defined (USB)
+/**
+ * @brief PCD double buffered endpoint direction
+ */
+typedef enum
+{
+ PCD_EP_DBUF_OUT,
+ PCD_EP_DBUF_IN,
+ PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/**
+ * @brief PCD endpoint buffer number
+ */
+typedef enum
+{
+ PCD_EP_NOBUF,
+ PCD_EP_BUF0,
+ PCD_EP_BUF1
+}PCD_EP_BUF_NUM;
+#endif /* USB */
+
+#if defined (USB_OTG_FS)
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+typedef USB_TypeDef PCD_TypeDef;
+typedef USB_CfgTypeDef PCD_InitTypeDef;
+typedef USB_EPTypeDef PCD_EPTypeDef;
+#endif /* USB */
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f1xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed PCD Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0 /* Not Supported */
+#define PCD_SPEED_HIGH_IN_FULL 1 /* Not Supported */
+#define PCD_SPEED_FULL 2
+/**
+ * @}
+ */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+ * @{
+ */
+#define PCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#if defined (USB_OTG_FS)
+
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+ ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_WAKEUP_EXTI_LINE
+#endif /* USB */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+#if defined (USB_OTG_FS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */
+#endif /* USB */
+/**
+ * @}
+ */
+
+#if defined (USB)
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+ * @{
+ */
+#define PCD_EP0MPS_64 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP PCD ENDP
+ * @{
+ */
+#define PCD_ENDP0 ((uint8_t)0)
+#define PCD_ENDP1 ((uint8_t)1)
+#define PCD_ENDP2 ((uint8_t)2)
+#define PCD_ENDP3 ((uint8_t)3)
+#define PCD_ENDP4 ((uint8_t)4)
+#define PCD_ENDP5 ((uint8_t)5)
+#define PCD_ENDP6 ((uint8_t)6)
+#define PCD_ENDP7 ((uint8_t)7)
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+ * @{
+ */
+#define PCD_SNG_BUF 0
+#define PCD_DBL_BUF 1
+/**
+ * @}
+ */
+#endif /* USB */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+#if defined (USB)
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
+
+/* ENDPOINT transfer */
+#define USB_EP0StartXfer USB_EPStartXfer
+
+/**
+ * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wType: Endpoint Type.
+ * @retval None
+ */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+
+/**
+ * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Type
+ */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: Direction
+ * @retval None
+ */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+ if ((bDir) == PCD_EP_DBUF_OUT)\
+ { /* OUT double buffered endpoint */\
+ PCD_TX_DTOG((USBx), (bEpNum));\
+ }\
+ else if ((bDir) == PCD_EP_DBUF_IN)\
+ { /* IN double buffered endpoint */\
+ PCD_RX_DTOG((USBx), (bEpNum));\
+ }\
+}
+
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval EP_DBUF_OUT, EP_DBUF_IN,
+ * EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+ if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+ return(PCD_EP_DBUF_OUT);\
+ else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+ return(PCD_EP_DBUF_IN);\
+ else\
+ return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+ * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wState))!= 0)\
+ { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wState))!= 0) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
+ } /* PCD_SET_EP_TX_STATUS */
+
+/**
+ * @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & (wState))!= 0) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wState))!= 0) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_RX_STATUS */
+
+/**
+ * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wStaterx: new state.
+ * @param wStatetx: new state.
+ * @retval None
+ */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
+ } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+ * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval status
+ */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+ * @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+ * @brief checks stall condition in an endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval TRUE = endpoint in stall condition.
+ */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_RX_STALL)
+
+/**
+ * @brief set & clear EP_KIND bit.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+
+/**
+ * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+
+/**
+ * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+
+/**
+ * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+ { \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ }
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+ { \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ }
+
+/**
+ * @brief Sets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bAddr: Address.
+ * @retval None
+ */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400)))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+ }
+
+/**
+ * @brief sets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wAddr: address to be set (must be word aligned).
+ * @retval None
+ */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+
+/**
+ * @brief Gets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval address of the buffer.
+ */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Sets counter of rx buffer with no. of blocks.
+ * @param dwReg: Register
+ * @param wCount: Counter.
+ * @param wNBlocks: no. of Blocks.
+ * @retval None
+ */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 5;\
+ if(((wCount) & 0x1f) == 0)\
+ { \
+ (wNBlocks)--;\
+ } \
+ *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
+ }/* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 1;\
+ if(((wCount) & 0x1) != 0)\
+ { \
+ (wNBlocks)++;\
+ } \
+ *pdwReg = (uint16_t)((wNBlocks) << 10);\
+ }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
+ uint16_t wNBlocks;\
+ if((wCount) > 62) \
+ { \
+ PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \
+ } \
+ }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+ }
+
+/**
+ * @brief sets counter for the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wCount: Counter value.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+
+
+/**
+ * @brief gets counter of the tx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Counter value
+ */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+
+/**
+ * @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @retval Counter value
+ */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+
+/**
+ * @brief Sets addresses in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+ } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount: Counter value
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ /* IN endpoint */ \
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ {/* OUT endpoint */ \
+ PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \
+ } \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ {/* IN endpoint */ \
+ *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } \
+ } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ } /* PCD_SET_EP_DBUF_CNT */
+
+/**
+ * @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+#endif /* USB */
+
+/** @defgroup PCD_Instance_definition PCD Instance definition
+ * @{
+ */
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F102x6 || STM32F102xB || */
+ /* STM32F103x6 || STM32F103xB || */
+ /* STM32F103xE || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.c
new file mode 100644
index 000000000..fd9cb749c
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.c
@@ -0,0 +1,249 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Extended PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Extended features functions: Update FIFO configuration,
+ * PMA configuration for EPs
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update FIFO (USB_OTG_FS)
+ (+) Update PMA configuration (USB)
+
+@endverbatim
+ * @{
+ */
+
+#if defined (USB_OTG_FS)
+/**
+ * @brief Set Tx FIFO
+ * @param hpcd: PCD handle
+ * @param fifo: The number of Tx fifo
+ * @param size: Fifo size
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+ uint8_t index = 0;
+ uint32_t Tx_Offset = 0;
+
+ /* TXn min size = 16 words. (n : Transmit FIFO index)
+ When a TxFIFO is not used, the Configuration should be as follows:
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txm can use the space allocated for Txn.
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
+ --> Txn should be configured with the minimum space of 16 words
+ The FIFO is used optimally when used TxFIFOs are allocated in the top
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+ Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+ if(fifo == 0)
+ {
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+ }
+ else
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+ for (index = 0; index < (fifo - 1); index++)
+ {
+ Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16);
+ }
+
+ /* Multiply Tx_Size by 2 to get higher performance */
+ hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
+
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Rx FIFO
+ * @param hpcd: PCD handle
+ * @param size: Size of Rx fifo
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+ hpcd->Instance->GRXFSIZ = size;
+ return HAL_OK;
+}
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+/**
+ * @brief Configure PMA for EP
+ * @param hpcd : Device instance
+ * @param ep_addr: endpoint address
+ * @param ep_kind: endpoint Kind
+ * USB_SNG_BUF: Single Buffer used
+ * USB_DBL_BUF: Double Buffer used
+ * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
+ * this parameter is 16-bit value providing the address
+ * in PMA allocated to endpoint.
+ * In case of double buffer endpoint this parameter
+ * is a 32-bit value providing the endpoint buffer 0 address
+ * in the LSB part of 32-bit value and endpoint buffer 1 address
+ * in the MSB part of 32-bit value.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress)
+
+{
+ PCD_EPTypeDef *ep = NULL;
+
+ /* initialize ep structure*/
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ /* Here we check if the endpoint is single or double Buffer*/
+ if (ep_kind == PCD_SNG_BUF)
+ {
+ /*Single Buffer*/
+ ep->doublebuffer = 0;
+ /*Configure te PMA*/
+ ep->pmaadress = (uint16_t)pmaadress;
+ }
+ else /*USB_DBL_BUF*/
+ {
+ /*Double Buffer Endpoint*/
+ ep->doublebuffer = 1;
+ /*Configure the PMA*/
+ ep->pmaaddr0 = pmaadress & 0xFFFF;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
+ }
+
+ return HAL_OK;
+}
+#endif /* USB */
+/**
+ * @}
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions
+ * @brief Manage device connection state
+ * @{
+ */
+/**
+ * @brief Software Device Connection,
+ * this function is not required by USB OTG FS peripheral, it is used
+ * only by USB Device FS peripheral.
+ * @param hpcd: PCD handle
+ * @param state: connection state (0 : disconnected / 1: connected)
+ * @retval None
+ */
+__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCDEx_SetConnectionState could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F102x6 || STM32F102xB || */
+ /* STM32F103x6 || STM32F103xB || */
+ /* STM32F103xE || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.h
new file mode 100644
index 000000000..8c3cc87e4
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.h
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of Extended PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PCD_EX_H
+#define __STM32F1xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+#if defined (USB_OTG_FS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* USB_OTG_FS */
+
+#if defined (USB)
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress);
+#endif /* USB */
+/**
+ * @}
+ */
+
+/** @addtogroup PCDEx_Exported_Functions_Group2 Peripheral State functions
+ * @{
+ */
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F102x6 || STM32F102xB || */
+ /* STM32F103x6 || STM32F103xB || */
+ /* STM32F103xE || STM32F103xG || */
+ /* STM32F105xC || STM32F107xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.c
new file mode 100644
index 000000000..fd1ae1d7b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.c
@@ -0,0 +1,636 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pwr.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief PWR HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000)
+#define PVD_MODE_EVT ((uint32_t)0x00020000)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET 0x00
+#define PWR_CSR_OFFSET 0x04
+#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+ * @{
+ */
+/* --- CR Register ---*/
+/* Alias word address of LPSDSR bit */
+#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS)
+#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
+
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
+#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
+#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+ * @{
+ */
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP1 bit */
+#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PWR_Private_Functions PWR Private Functions
+ * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
+ * @{
+ */
+static void PWR_OverloadWfe(void);
+
+/* Private functions ---------------------------------------------------------*/
+__NOINLINE
+static void PWR_OverloadWfe(void)
+{
+ __asm volatile( "wfe" );
+ __asm volatile( "nop" );
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enables access to the backup domain (RTC registers, RTC
+ * backup data registers ).
+ * @note If the HSE divided by 128 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ /* Enable access to RTC and backup registers */
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers).
+ * @note If the HSE divided by 128 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ /* Disable access to RTC and backup registers */
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PVD_EXTI_ENABLE_IT() macro.
+ (+) The PVD is stopped in Standby mode.
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
+ forced in input pull-down configuration and is active on rising edges.
+ (+) There is one WakeUp pin:
+ WakeUp Pin 1 on PA.00.
+
+ [..]
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The device features 3 low-power modes:
+ (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
+ NVIC, SysTick, etc. are kept running
+ (+) Stop mode: All clocks are stopped
+ (+) Standby mode: 1.8V domain powered off
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
+ functions with
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ (+) Exit:
+ (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+ (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
+ (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
+ (+++) Any EXTI Line (Internal or External) configured in Event mode
+
+ *** Stop mode ***
+ =================
+ [..]
+ The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
+ clock gating. The voltage regulator can be configured either in normal or low-power mode.
+ In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
+ oscillators are disabled. SRAM and register contents are preserved.
+ In Stop mode, all I/O pins keep the same state as in Run mode.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
+ function with:
+ (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
+ (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+ (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+ (+) Exit:
+ (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
+ (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode allows to achieve the lowest power consumption. It is based on the
+ Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
+ consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
+ switched off. SRAM and register contents are lost except for registers in the Backup domain
+ and Standby circuitry
+
+ (+) Entry:
+ (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
+ NRSTpin, IWDG Reset
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..]
+
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
+ without depending on an external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+ *** PWR Workarounds linked to Silicon Limitation ***
+ ====================================================
+ [..]
+ Below the list of all silicon limitations known on STM32F1xx prouct.
+
+ (#)Workarounds Implemented inside PWR HAL Driver
+ (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ /* Enable the power voltage detector */
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ /* Disable the power voltage detector */
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ /* Enable the EWUPx pin */
+ *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ /* Check the parameter */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ /* Disable the EWUPx pin */
+ *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enters Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
+ * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ * When WFI entry is used, tick interrupt have to be disabled if not desired as
+ * the interrupt wake up source.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ /* No check on Regulator because parameter not used in SLEEP mode */
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters Stop mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by using an interrupt or a wakeup event,
+ * HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in Stop mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
+ CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
+
+ /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ PWR_OverloadWfe(); /* WFE redefine locally */
+ PWR_OverloadWfe(); /* WFE redefine locally */
+ }
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enters Standby mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available)
+ * - TAMPER pin if configured for tamper or calibration out.
+ * - WKUP pin (PA0) if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select Standby mode */
+ SET_BIT(PWR->CR, PWR_CR_PDDS);
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Enables CORTEX M3 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disables CORTEX M3 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ /* Check PWR exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.h
new file mode 100644
index 000000000..33b97af05
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.h
@@ -0,0 +1,406 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_pwr.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PWR_H
+#define __STM32F1xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+ This parameter can be a value of @ref PWR_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+
+/**
+ * @}
+ */
+
+
+/* Internal constants --------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
+
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+ * @brief PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+/* #define HAL_PWR_ConfigPVD 12*/
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+
+
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c
new file mode 100644
index 000000000..1e199ce02
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c
@@ -0,0 +1,1085 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
+ and all peripherals are off except internal SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals whose clocks are not
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+* @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provide functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+
+ (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clockis automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
+ HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
+
+ [..] System, AHB and APB busses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
+ divided by 128.
+ (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
+ to work correctly. This clock is derived of the main PLL through PLL Multiplier.
+ (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
+ (+@) IWDG clock which is always the LSI clock.
+
+ (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
+ For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ |---------------|-------------------------------|
+ |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ +-----------------------------------------------+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS and MCO1 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+__weak void HAL_RCC_DeInit(void)
+{
+ /* Switch SYSCLK to HSI */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+
+ /* Reset HSEON, CSSON, & PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Set HSITRIM bits to the reset value */
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
+ should be added.*/
+ HAL_Delay(1);
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv1 factor --------------------------------*/
+ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
+ if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
+
+ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+ }
+
+ /* Configure the main PLL clock source and multiplication factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLMUL);
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency: FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
+ * @arg FLASH_LATENCY_2: FLASH 2 Latency cycle
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ * @retval None
+ */
+__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ }
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx: specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
+ * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected as MCO source
+ * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO source
+ * @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected as MCO source (only for connectivity line devices)
+ * @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO source (only for connectivity line devices)
+ * @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected as MCO source (only for connectivity line devices)
+ * @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected as MCO source (only for connectivity line devices)
+ * @param RCC_MCODiv: specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: no division applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* MCO Clock Enable */
+ MCO1_CLK_ENABLE();
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Pin = MCO1_PIN;
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
+
+ /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, RCC_MCOSource);
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz).
+ * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[2] = { 1, 2};
+
+ uint32_t tmpreg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+
+ tmpreg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+}
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
+}
+
+/**
+ * @brief Configures the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency: Pointer on the Flash Latency.
+ * @retval None
+ */
+__weak void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+ /* For VALUE lines devices, only LATENCY_0 can be set*/
+ *pFLatency = (uint32_t)FLASH_LATENCY_0;
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h
new file mode 100644
index 000000000..5c8ee91dc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h
@@ -0,0 +1,1263 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RCC_H
+#define __STM32F1xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
+
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
+#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
+/* Alias word address of HSEON bit */
+#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
+#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
+/* Alias word address of CSSON bit */
+#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
+/* Alias word address of PLLON bit */
+#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
+
+/* --- BDCR Register ---*/
+/* Alias word address of LSEON bit */
+#define LSEON_BITNUMBER POSITION_VAL(RCC_BDCR_LSEON)
+#define BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
+
+/* Alias word address of LSEON bit */
+#define LSEBYP_BITNUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
+#define BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
+
+/* Alias word address of RTCEN bit */
+#define RTCEN_BITNUMBER POSITION_VAL(RCC_BDCR_RTCEN)
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BITNUMBER POSITION_VAL(RCC_BDCR_BDRST)
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define BDCR_REG_INDEX ((uint8_t)2)
+#define CSR_REG_INDEX ((uint8_t)3)
+
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+/**
+ * @}
+ */
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+
+#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+
+#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+
+/**
+ * @}
+ */
+
+/** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
+#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
+#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 (RCC_CFGR_HPRE_DIV1) /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 (RCC_CFGR_HPRE_DIV2) /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_DIV4) /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_DIV8) /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_DIV16) /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_DIV64) /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_DIV128) /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_DIV256) /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_DIV512) /*!< SYSCLK divided by 512 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 (RCC_CFGR_PPRE1_DIV1) /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 (RCC_CFGR_PPRE1_DIV2) /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_DIV4) /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_DIV8) /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE1_DIV16) /*!< HCLK divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_LSE (RCC_BDCR_RTCSEL_LSE) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI (RCC_BDCR_RTCSEL_LSI) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV128 (RCC_BDCR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XX : Register index
+ * - 01: CR register
+ * - 10: BDCR register
+ * - 11: CSR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_BKP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+
+#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
+#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
+#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+
+#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+
+#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ if((__STATE__) == RCC_HSE_ON) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
+ */
+#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
+ do{ \
+ if ((__LSE_STATE__) == RCC_LSE_OFF) \
+ { \
+ *(__IO uint32_t *) BDCR_LSEON_BB = DISABLE; \
+ *(__IO uint32_t *) BDCR_LSEBYP_BB = DISABLE; \
+ } \
+ else if ((__LSE_STATE__) == RCC_LSE_ON) \
+ { \
+ *(__IO uint32_t *) BDCR_LSEBYP_BB = DISABLE; \
+ *(__IO uint32_t *) BDCR_LSEON_BB = ENABLE; \
+ } \
+ else \
+ { \
+ *(__IO uint32_t *) BDCR_LSEON_BB = DISABLE; \
+ *(__IO uint32_t *) BDCR_LSEBYP_BB = ENABLE; \
+ } \
+ }while(0)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+
+/** @brief Macros to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+/** @brief macros to configure the main PLL clock source and multiplication factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
+ * @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
+ * @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
+ * @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
+ * @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
+ * @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
+ * @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
+ * @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
+ * @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
+ * @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
+ * @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
+ * @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
+ * @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
+ * @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
+ * @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
+ * @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
+
+/**
+ * @}
+ */
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macro to configures the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+ * a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+
+/** @brief macros to get the RTC clock source.
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
+
+/** @brief Macros to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+
+/** @brief Macros to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macros to force the Backup domain reset.
+ * @note This function resets the entire Backup domain.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+ * the selected interrupts.).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
+ * @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
+ * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
+ * @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
+ * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
+ * @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
+ * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
+ * @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+ * @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
+ * @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
+ * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extension module */
+#include "stm32f1xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c
new file mode 100644
index 000000000..ee3c51bfc
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c
@@ -0,0 +1,1946 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Extended RCC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extension HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+#define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/* Alias word address of PLL2ON bit */
+#define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
+#define CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
+
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS and MCO1 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Switch SYSCLK to HSI */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+
+ /* Reset HSEON, CSSON, & PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Set HSITRIM bits to the reset value */
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
+
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
+ should be added.*/
+ HAL_Delay(1);
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*-------------------------------- PLL2 Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
+ if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
+ {
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
+ assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLLI2S is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
+
+ /* Configure the main PLL2 multiplication factors. */
+ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
+
+ /* Enable the main PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Set PREDIV1 source to HSE */
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv1 factor and source --------------------------------*/
+ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
+ if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
+ {
+ /* Check the parameter */
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
+ assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
+
+ /* Set PREDIV1 source */
+ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
+
+ /* Set PREDIV1 Value */
+ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+ }
+
+ /* Configure the main PLL clock source and multiplication factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLMUL);
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC STM32F107xC */
+
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/**
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency: FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+ /* Increasing the CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /* Decreasing the CPU frequency */
+ else
+ {
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration -------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ }
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz).
+ * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+
+ uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+ uint32_t prediv2 = 0, pll2mul = 0;
+
+ tmp_reg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmp_reg & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+
+ if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+ if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+ {
+ /* PLL2 selected as Prediv1 source */
+ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
+ }
+ else
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+
+ /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+ /* In this case need to divide pllclk by 2 */
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ {
+ pllclk = pllclk / 2;
+ }
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the Prediv1 source --------------------------------------------------*/
+ RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
+
+ /* Get the PLL2 configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
+ }
+ RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
+ RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC*/
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/**
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz).
+ * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+ uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+
+ tmp_reg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmp_reg & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F100xB || STM32F100xE*/
+
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
+ defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/**
+ * @brief Configures the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency: Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+/**
+ * @}
+ */
+
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(RTC clock).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) are set to their reset values.
+ *
+ * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
+ * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
+ * manually disable it.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0, tmp_reg = 0;
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t pllactive = 0;
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*------------------------------- RTC/LCD Configuration ------------------------*/
+ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+ {
+ /* Enable Power Controller clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ tmp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if((tmp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmp_reg;
+ }
+
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+ if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE))
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+
+ /*------------------------------ ADC clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
+
+ /* Configure the ADC clock source */
+ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+ }
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /*------------------------------ I2S2 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
+
+ /* Configure the I2S2 clock source */
+ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
+ }
+
+ /*------------------------------ I2S3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
+
+ /* Configure the I2S3 clock source */
+ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
+ }
+
+ /*------------------------------ PLL I2S Configuration ----------------------*/
+ /* Check that PLLI2S need to be enabled */
+ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Update flag to indicate that PLL I2S should be active */
+ pllactive = 1;
+ }
+
+ /* Check if PLL I2S need to be enabled */
+ if (pllactive == 1)
+ {
+ /* Enable PLL I2S only if not active */
+ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLL2 is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
+
+ /* Configure the main PLLI2S multiplication factors. */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
+
+ /* Enable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
+ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+ /*------------------------------ USB clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
+
+ /* Configure the USB clock source */
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the PeriphClkInit according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t srcclk = 0;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
+
+ /* Get the RTC configuration -----------------------------------------------*/
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+ /* Source clock is LSE or LSI*/
+ PeriphClkInit->RTCClockSelection = srcclk;
+
+ /* Get the ADC clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
+ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Get the I2S2 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+ PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
+
+ /* Get the I2S3 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+ PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+ /* Get the I2S2 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+ PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
+
+ /* Get the I2S3 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+ PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+ /* Get the USB clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+}
+
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
+ * @arg RCC_PERIPHCLK_ADC: ADC peripheral clock
+ * @arg RCC_PERIPHCLK_I2S2: I2S2 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
+ * @arg RCC_PERIPHCLK_I2S3: I2S3 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
+ * @arg RCC_PERIPHCLK_USB: USB peripheral clock (STM32F102xx, STM32F103xx, STM32F105xC & STM32F107xC)
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[2] = { 1, 2};
+#endif
+#endif
+ uint32_t tmp_reg = 0, frequency = 0;
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Get RCC configuration ------------------------------------------------------*/
+ tmp_reg = RCC->CFGR;
+
+ /* Check if PLL is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+#else
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+ {
+ /* PLL2 selected as Prediv1 source */
+ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
+ }
+ else
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+
+ /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+ /* In this case need to divide pllclk by 2 */
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ {
+ pllclk = pllclk / 2;
+ }
+#else
+ if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+#endif /* STM32F105xC || STM32F107xC */
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+
+ /* Calcul of the USB frequency*/
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
+ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV2)
+ {
+ /* Prescaler of 2 selected for USB */
+ frequency = pllclk;
+ }
+ else
+ {
+ /* Prescaler of 3 selected for USB */
+ frequency = (2 * pllclk) / 3;
+ }
+#else
+ /* USBCLK = PLLCLK / USB prescaler */
+ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV1)
+ {
+ /* No prescaler selected for USB */
+ frequency = pllclk;
+ }
+ else
+ {
+ /* Prescaler of 1.5 selected for USB */
+ frequency = (pllclk * 2) / 3;
+ }
+#endif
+ }
+ break;
+ }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+ case RCC_PERIPHCLK_I2S2:
+ {
+#if defined (STM32F103xE) || defined (STM32F103xG)
+ /* SYSCLK used as source clock for I2S2 */
+ frequency = HAL_RCC_GetSysClockFreq();
+#else
+ if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
+ {
+ /* SYSCLK used as source clock for I2S2 */
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else
+ {
+ /* Check if PLLI2S is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+ }
+ }
+#endif /* STM32F103xE || STM32F103xG */
+ break;
+ }
+ case RCC_PERIPHCLK_I2S3:
+ {
+#if defined (STM32F103xE) || defined (STM32F103xG)
+ /* SYSCLK used as source clock for I2S3 */
+ frequency = HAL_RCC_GetSysClockFreq();
+#else
+ if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
+ {
+ /* SYSCLK used as source clock for I2S3 */
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else
+ {
+ /* Check if PLLI2S is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+ }
+ }
+#endif /* STM32F103xE || STM32F103xG */
+ break;
+ }
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get RCC BDCR configuration ------------------------------------------------------*/
+ tmp_reg = RCC->BDCR;
+
+ /* Check if LSE is ready if RTC clock selection is LSE */
+ if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(tmp_reg, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready if RTC clock selection is LSI */
+ else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ frequency = HSE_VALUE / 128;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_ADC:
+ {
+ frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
+ break;
+ }
+ default:
+ {
+ break;
+ }
+ }
+ return(frequency);
+}
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
+ * @brief PLLI2S Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended PLLI2S Management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PLLI2S
+ activation or deactivation
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S
+ * @param PLLI2SInit: pointer to an RCC_PLLI2SInitTypeDef structure that
+ * contains the configuration information for the PLLI2S
+ * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
+{
+ uint32_t tickstart = 0;
+
+ /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
+ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLL2 is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
+
+
+ /* Configure the main PLLI2S multiplication factors. */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
+
+ /* Enable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLI2S
+ * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable PLL I2S as not requested by I2S2 or I2S3*/
+ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Disable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
+ * @brief PLL2 Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended PLL2 Management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PLL2
+ activation or deactivation
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2
+ * @param PLL2Init: pointer to an RCC_PLL2InitTypeDef structure that
+ * contains the configuration information for the PLL2
+ * @note The PLL2 configuration not modified if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
+{
+ uint32_t tickstart = 0;
+
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLLI2S is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
+
+ /* Configure the main PLL2 multiplication factors. */
+ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
+
+ /* Enable the main PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLL2
+ * @note PLL2 is not disabled if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
+{
+ uint32_t tickstart = 0;
+
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h
new file mode 100644
index 000000000..a629d894d
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h
@@ -0,0 +1,1895 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RCC_EX_H
+#define __STM32F1xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
+#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
+
+/** @defgroup RCCEx_PLL_Timeout PLL I2S Timeout
+ * @{
+ */
+#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#define CR_REG_INDEX ((uint8_t)1)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
+
+#else
+#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL6_5))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
+
+#else
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
+
+#endif /* STM32F105xC || STM32F107xC*/
+
+#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
+ ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
+
+#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
+
+#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV2) || ((__USBCLK__) == RCC_USBPLLCLK_DIV3))
+
+#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
+ ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
+ ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
+ ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
+ ((__MUL__) == RCC_PLLI2S_MUL20))
+
+#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
+
+#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
+ ((__PLL__) == RCC_PLL2_ON))
+
+#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
+ ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
+ ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
+ ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
+ ((__MUL__) == RCC_PLL2_MUL20))
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+#elif defined(STM32F103xE) || defined(STM32F103xG)
+
+#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
+
+#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+
+#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+#else
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+
+#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV1) || ((__USBCLK__) == RCC_USBPLLCLK_DIV1_5))
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/**
+ * @brief RCC PLL2 configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLL2State; /*!< The new state of the PLL2.
+ This parameter can be a value of @ref RCCEx_PLL2_Config */
+
+ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
+ This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
+ This parameter can be a value of @ref RCCEx_Prediv2_Factor */
+
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_PLL2InitTypeDef;
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t Prediv1Source; /*!< The Prediv1 source value.
+ This parameter can be a value of @ref RCCEx_Prediv1_Source */
+#endif /* STM32F105xC || STM32F107xC */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref __HAL_RCC_HSE_CONFIG */
+
+ uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
+ This parameter can be a value of @ref RCCEx_Prediv1_Factor */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref __HAL_RCC_LSE_CONFIG */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_OscInitTypeDef;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/**
+ * @brief RCC PLLI2S configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
+ This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
+ This parameter can be a value of @ref RCCEx_Prediv2_Factor */
+
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_PLLI2SInitTypeDef;
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t AdcClockSelection; /*!< ADC clock source
+ This parameter can be a value of @ref RCCEx_ADC_Prescaler */
+
+#if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+ uint32_t I2s2ClockSelection; /*!< I2S2 clock source
+ This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
+
+ uint32_t I2s3ClockSelection; /*!< I2S3 clock source
+ This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
+
+#if defined (STM32F105xC) || defined (STM32F107xC)
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
+
+#endif /* STM32F105xC || STM32F107xC */
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Prescaler */
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+} RCC_PeriphCLKInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
+ * @{
+ */
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
+#if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
+ * @{
+ */
+#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
+#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
+#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
+#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
+
+/**
+ * @}
+ */
+
+#if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
+ * @{
+ */
+#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
+ * @{
+ */
+#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+
+/** @defgroup RCCEx_USB_Prescaler USB Prescaler
+ * @{
+ */
+#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE
+#define RCC_USBPLLCLK_DIV1_5 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_USB_Prescaler USB Prescaler
+ * @{
+ */
+#define RCC_USBPLLCLK_DIV2 RCC_CFGR_OTGFSPRE
+#define RCC_USBPLLCLK_DIV3 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
+ * @{
+ */
+
+#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
+#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
+#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
+#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
+#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
+#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
+#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
+#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
+#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
+ * @{
+ */
+
+#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
+#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
+#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
+#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
+#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
+#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
+#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
+#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
+#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
+#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
+#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
+#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
+#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
+#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
+#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
+#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
+#else
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
+#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
+#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
+#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
+#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
+#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
+#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
+#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
+#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
+#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
+#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
+#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
+#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
+#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
+#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
+#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLL2_Config PLL Config
+ * @{
+ */
+#define RCC_PLL2_NONE ((uint32_t)0x00000000)
+#define RCC_PLL2_OFF ((uint32_t)0x00000001)
+#define RCC_PLL2_ON ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
+ * @{
+ */
+
+#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
+#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
+#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
+#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
+#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
+#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
+#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
+#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
+#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#else
+#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
+#endif /* STM32F105xC || STM32F107xC */
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
+#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
+#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
+#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
+#else
+#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
+#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
+#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
+#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
+#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
+#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
+#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
+#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
+#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
+#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
+#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
+#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
+#endif /* STM32F105xC || STM32F107xC*/
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Interrupt RCCEx Interrupt
+ * @{
+ */
+#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
+#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Flag RCCEx Flag
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XX : Register index
+ * - 01: CR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F100xE)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
+
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined (STM32F100xE)
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+
+#if defined (STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
+#endif /* STM32F105xC || STM32F107xC*/
+
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
+
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0)
+
+#endif /* STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F100xE)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined (STM32F100xE)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+#if defined (STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
+#endif /* STM32F103xE || STM32F103xG */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
+#endif /* STM32F105xC || STM32F107xC*/
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
+#endif /* STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) ||defined (STM32F107xC)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
+ defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#endif /* STM32F100xB || STM32F100xE */
+
+#ifdef STM32F100xE
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#endif /* STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) ||defined (STM32F107xC)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
+ defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#endif /* STM32F100xB || STM32F100xE */
+#ifdef STM32F100xE
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#endif /* STM32F100xE */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#endif /* STM32F105xC || STM32F107xC */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
+ defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined (STM32F100xE)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
+#endif /* STM32F100xE */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
+ defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+#if defined (STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#endif /* STM32F100xB || STM32F100xE */
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#endif /* STM32F103xE || STM32F103xG */
+#if defined (STM32F100xE)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
+#endif /* STM32F100xE */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
+#endif /* STM32F107xC */
+
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
+#endif /* STM32F107xC */
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) ||defined (STM32F107xC)
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
+ defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined (STM32F100xE)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#endif /* STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
+ defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
+
+#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+
+#if defined (STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+
+#if defined (STM32F103xE) || defined (STM32F103xG)
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined (STM32F100xE)
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
+#endif /* STM32F100xE */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
+#else
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
+
+#else
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
+
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLLI2S.
+ * @note After enabling the main PLLI2S, the application software should wait on
+ * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
+ * be used as system clock source.
+ * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+
+/** @brief Macros to disable the main PLLI2S.
+ * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+/** @brief macros to configure the main PLLI2S multiplication factor.
+ * @note This function must be used only when the main PLLI2S is disabled.
+ *
+ * @param __PLLI2SMUL__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLI2S_MUL8: PLLI2SVCO = PLLI2S clock entry x 8
+ * @arg RCC_PLLI2S_MUL9: PLLI2SVCO = PLLI2S clock entry x 9
+ * @arg RCC_PLLI2S_MUL10: PLLI2SVCO = PLLI2S clock entry x 10
+ * @arg RCC_PLLI2S_MUL11: PLLI2SVCO = PLLI2S clock entry x 11
+ * @arg RCC_PLLI2S_MUL12: PLLI2SVCO = PLLI2S clock entry x 12
+ * @arg RCC_PLLI2S_MUL13: PLLI2SVCO = PLLI2S clock entry x 13
+ * @arg RCC_PLLI2S_MUL14: PLLI2SVCO = PLLI2S clock entry x 14
+ * @arg RCC_PLLI2S_MUL16: PLLI2SVCO = PLLI2S clock entry x 16
+ * @arg RCC_PLLI2S_MUL20: PLLI2SVCO = PLLI2S clock entry x 20
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
+ * @brief Macros to configure clock source of different peripherals.
+ * @{
+ */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+/** @brief Macro to configure the USB clock.
+ * @param __USBCLKSOURCE__: specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
+ * @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
+
+/** @brief Macro to get the USB clock (USBCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
+ * @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @brief Macro to configure the USB OTSclock.
+ * @param __USBCLKSOURCE__: specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
+ * @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
+
+/** @brief Macro to get the USB clock (USBCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
+ * @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
+ * @param __ADCCLKSOURCE__: specifies the ADC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
+ */
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
+
+/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
+ * @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
+ */
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @addtogroup RCCEx_HSE_Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
+ * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
+ * then change the PREDIV2 factor.
+ * @param __HSE_PREDIV2_VALUE__: specifies the PREDIV2 value applied to PLL2 & PLLI2S.
+ * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
+
+/**
+ * @brief Macro to get prediv2 factor for PLL2 & PLL3.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_PLLI2S_Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLL2.
+ * @note After enabling the main PLL2, the application software should wait on
+ * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) CR_PLL2ON_BB = ENABLE)
+
+/** @brief Macros to disable the main PLL2.
+ * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
+ * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) CR_PLL2ON_BB = DISABLE)
+
+/** @brief macros to configure the main PLL2 multiplication factor.
+ * @note This function must be used only when the main PLL2 is disabled.
+ *
+ * @param __PLL2MUL__: specifies the multiplication factor for PLL2 VCO output clock
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL2_MUL8: PLL2VCO = PLL2 clock entry x 8
+ * @arg RCC_PLL2_MUL9: PLL2VCO = PLL2 clock entry x 9
+ * @arg RCC_PLL2_MUL10: PLL2VCO = PLL2 clock entry x 10
+ * @arg RCC_PLL2_MUL11: PLL2VCO = PLL2 clock entry x 11
+ * @arg RCC_PLL2_MUL12: PLL2VCO = PLL2 clock entry x 12
+ * @arg RCC_PLL2_MUL13: PLL2VCO = PLL2 clock entry x 13
+ * @arg RCC_PLL2_MUL14: PLL2VCO = PLL2 clock entry x 14
+ * @arg RCC_PLL2_MUL16: PLL2VCO = PLL2 clock entry x 16
+ * @arg RCC_PLL2_MUL20: PLL2VCO = PLL2 clock entry x 20
+ *
+ */
+#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Configuration I2S Configuration
+ * @brief Macros to configure clock source of I2S peripherals.
+ * @{
+ */
+
+/** @brief Macro to configure the I2S2 clock.
+ * @param __I2S2CLKSOURCE__: specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
+
+/** @brief Macro to get the I2S2 clock (I2S2CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
+
+/** @brief Macro to configure the I2S3 clock.
+ * @param __I2S2CLKSOURCE__: specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
+
+/** @brief Macro to get the I2S3 clock (I2S3CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.c
new file mode 100644
index 000000000..e4063df04
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.c
@@ -0,0 +1,1708 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rtc.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) peripheral:
+ * + Initialization and de-initialization functions
+ * + RTC Time and Date functions
+ * + RTC Alarm functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base)
+ using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper Level using the
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
+ mode using HAL_RTCEx_SetTamper_IT() function.
+ (+) The TAMPER1 alternate function can be mapped to PC13
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+
+ ##### WARNING: Drivers Restrictions #####
+ ==================================================================
+ [..] RTC version used on STM32F1 families is version V1. All the features supported by V2
+ (other families) will be not supported on F1.
+ [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely
+ managed by SW.
+ [..] Then, there are some restrictions compared to other families:
+ (+) Only format 24 hours supported in HAL (format 12 hours not supported)
+ (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost.
+ User should implement a way to save date before entering in low power mode (an
+ example is provided with firmware package based on backup registers)
+ (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called.
+ (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need
+ to program a new alarm)
+
+ ##### Backup Domain Operating Condition #####
+ ==============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
+ off, the VBAT pin powers the following blocks:
+ (+) The RTC
+ (+) The LSE oscillator
+ (+) PC13 I/O
+
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+ the following pins are available:
+ (+) PC13 can be used as a Tamper pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
+ because VDD is not present), the following pins are available:
+ (+) PC13 can be used as the Tamper pin
+
+ ##### Backup Domain Reset #####
+ ==================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+ to their reset values.
+ [..] A backup domain reset is generated when one of the following events occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
+ (#) Tamper detection event resets all data backup registers.
+
+ ##### Backup Domain Access #####
+ ==================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted write
+ accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for
+ PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE)
+ (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE()
+
+ ##### RTC and low power modes #####
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A),
+ and RTC tamper event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
+#define RTC_ALARM_RESETVALUE (uint32_t)0xFFFFFFFF
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
+static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
+static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc);
+static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter);
+static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc);
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+static uint8_t RTC_IsLeapYear(uint16_t nYear);
+static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed);
+static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay);
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Asynchronous), disable RTC registers Write protection,
+ enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by setting the CNF bit in the RTC_CRL register.
+ (#) To read the calendar after wakeup from low power modes (Standby or Stop)
+ the software must first wait for the RSF bit (Register Synchronized Flag)
+ in the RTC_CRL register to be set by hardware.
+ The HAL_RTC_WaitForSynchro() function implements the above software
+ sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t prescaler = 0;
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc-> Lock = HAL_UNLOCKED;
+
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Waiting for synchro */
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear Flags Bits */
+ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));
+
+ if(hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
+ {
+ /* Disable the selected Tamper pin */
+ CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+ }
+
+ /* Set the signal which will be routed to RTC Tamper pin*/
+ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
+
+ if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND)
+ {
+ /* RTC Prescaler provided directly by end-user*/
+ prescaler = hrtc->Init.AsynchPrediv;
+ }
+ else
+ {
+ /* RTC Prescaler will be automatically calculated to get 1 second timebase */
+ /* Get the RTCCLK frequency */
+ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
+
+ /* Check that RTC clock is enabled*/
+ if (prescaler == 0)
+ {
+ /* Should not happen. Frequency is not available*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* RTC period = RTCCLK/(RTC_PR + 1) */
+ prescaler = prescaler - 1;
+ }
+ }
+
+ /* Configure the RTC_PRLH / RTC_PRLL */
+ MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16));
+ MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL));
+
+ /* Wait for synchro */
+ if(RTC_ExitInitMode(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Initialize date to 1st of January 2000 */
+ hrtc->DateToUpdate.Year = 0x00;
+ hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
+ hrtc->DateToUpdate.Date = 0x01;
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief DeInitializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This function does not reset the RTC Backup Data registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ CLEAR_REG(hrtc->Instance->CNTL);
+ CLEAR_REG(hrtc->Instance->CNTH);
+ WRITE_REG(hrtc->Instance->PRLL, 0x00008000);
+ CLEAR_REG(hrtc->Instance->PRLH);
+
+ /* Reset All CRH/CRL bits */
+ CLEAR_REG(hrtc->Instance->CRH);
+ CLEAR_REG(hrtc->Instance->CRL);
+
+ if(RTC_ExitInitMode(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Wait for synchro*/
+ HAL_RTC_WaitForSynchro(hrtc);
+
+ /* Clear RSF flag */
+ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
+
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t counter_time = 0, counter_alarm = 0;
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sTime == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600) + \
+ ((uint32_t)sTime->Minutes * 60) + \
+ ((uint32_t)sTime->Seconds));
+ }
+ else
+ {
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+
+ counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds))));
+ }
+
+ /* Write time counter in RTC registers */
+ if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear Second and overflow flags */
+ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
+
+ /* Read current Alarm counter in RTC registers */
+ counter_alarm = RTC_ReadAlarmCounter(hrtc);
+
+ /* Set again alarm to match with new time if enabled */
+ if (counter_alarm != RTC_ALARM_RESETVALUE)
+ {
+ if(counter_alarm < counter_time)
+ {
+ /* Add 1 day to alarm counter*/
+ counter_alarm += (uint32_t)(24 * 3600);
+
+ /* Write new Alarm counter in RTC registers */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t counter_time = 0, counter_alarm = 0, days_elapsed = 0, hours = 0;
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sTime == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Check if counter overflow occurred */
+ if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read the time counter*/
+ counter_time = RTC_ReadTimeCounter(hrtc);
+
+ /* Fill the structure fields with the read parameters */
+ hours = counter_time / 3600;
+ sTime->Minutes = (uint8_t)((counter_time % 3600) / 60);
+ sTime->Seconds = (uint8_t)((counter_time % 3600) % 60);
+
+ if (hours >= 24)
+ {
+ /* Get number of days elapsed from last calculation */
+ days_elapsed = (hours / 24);
+
+ /* Set Hours in RTC_TimeTypeDef structure*/
+ sTime->Hours = (hours % 24);
+
+ /* Read Alarm counter in RTC registers */
+ counter_alarm = RTC_ReadAlarmCounter(hrtc);
+
+ /* Calculate remaining time to reach alarm (only if set and not yet expired)*/
+ if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time))
+ {
+ counter_alarm -= counter_time;
+ }
+ else
+ {
+ /* In case of counter_alarm < counter_time */
+ /* Alarm expiration already occurred but alarm not deactivated */
+ counter_alarm = RTC_ALARM_RESETVALUE;
+ }
+
+ /* Set updated time in decreasing counter by number of days elapsed */
+ counter_time -= (days_elapsed * 24 * 3600);
+
+ /* Write time counter in RTC registers */
+ if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set updated alarm to be set */
+ if (counter_alarm != RTC_ALARM_RESETVALUE)
+ {
+ counter_alarm += counter_time;
+
+ /* Write time counter in RTC registers */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Update date */
+ RTC_DateUpdate(hrtc, days_elapsed);
+ }
+ else
+ {
+ sTime->Hours = hours;
+ }
+
+ /* Check the input parameters format */
+ if(Format != RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to BCD format */
+ sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Sets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate: Pointer to date structure
+ * @param Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t counter_time = 0, counter_alarm = 0, hours = 0;
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sDate == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ /* Change the current date */
+ hrtc->DateToUpdate.Year = sDate->Year;
+ hrtc->DateToUpdate.Month = sDate->Month;
+ hrtc->DateToUpdate.Date = sDate->Date;
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+ /* Change the current date */
+ hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year);
+ hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month);
+ hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date);
+ }
+
+ /* WeekDay set by user can be ignored because automatically calculated */
+ hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date);
+ sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
+
+ /* Reset time to be aligned on the same day */
+ /* Read the time counter*/
+ counter_time = RTC_ReadTimeCounter(hrtc);
+
+ /* Fill the structure fields with the read parameters */
+ hours = counter_time / 3600;
+ if (hours > 24)
+ {
+ /* Set updated time in decreasing counter by number of days elapsed */
+ counter_time -= ((hours / 24) * 24 * 3600);
+ /* Write time counter in RTC registers */
+ if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Read current Alarm counter in RTC registers */
+ counter_alarm = RTC_ReadAlarmCounter(hrtc);
+
+ /* Set again alarm to match with new time if enabled */
+ if (counter_alarm != RTC_ALARM_RESETVALUE)
+ {
+ if(counter_alarm < counter_time)
+ {
+ /* Add 1 day to alarm counter*/
+ counter_alarm += (uint32_t)(24 * 3600);
+
+ /* Write new Alarm counter in RTC registers */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+
+ }
+
+ hrtc->State = HAL_RTC_STATE_READY ;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sDate: Pointer to Date structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ RTC_TimeTypeDef stime = {0};
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sDate == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
+ if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Fill the structure fields with the read parameters */
+ sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
+ sDate->Year = hrtc->DateToUpdate.Year;
+ sDate->Month = hrtc->DateToUpdate.Month;
+ sDate->Date = hrtc->DateToUpdate.Date;
+
+ /* Check the input parameters format */
+ if(Format != RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to BCD format */
+ sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year);
+ sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month);
+ sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 Alarm functions
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t counter_alarm = 0, counter_time;
+ RTC_TimeTypeDef stime = {0};
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sAlarm == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
+ if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Convert time in seconds */
+ counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \
+ ((uint32_t)stime.Minutes * 60) + \
+ ((uint32_t)stime.Seconds));
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \
+ ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \
+ ((uint32_t)sAlarm->AlarmTime.Seconds));
+ }
+ else
+ {
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \
+ ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+ }
+
+ /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
+ if (counter_alarm < counter_time)
+ {
+ /* Add 1 day to alarm counter*/
+ counter_alarm += (uint32_t)(24 * 3600);
+ }
+
+ /* Write Alarm counter in RTC registers */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Sets the specified RTC Alarm with Interrupt
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t counter_alarm = 0, counter_time;
+ RTC_TimeTypeDef stime = {0};
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sAlarm == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
+ if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Convert time in seconds */
+ counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \
+ ((uint32_t)stime.Minutes * 60) + \
+ ((uint32_t)stime.Seconds));
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \
+ ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \
+ ((uint32_t)sAlarm->AlarmTime.Seconds));
+ }
+ else
+ {
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \
+ ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+ }
+
+ /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
+ if (counter_alarm < counter_time)
+ {
+ /* Add 1 day to alarm counter*/
+ counter_alarm += (uint32_t)(24 * 3600);
+ }
+
+ /* Write alarm counter in RTC registers */
+ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Gets the RTC Alarm value and masks.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm: Pointer to Date structure
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: Alarm
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t counter_alarm = 0;
+
+ /* Check input parameters */
+ if((hrtc == NULL) || (sAlarm == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Read Alarm counter in RTC registers */
+ counter_alarm = RTC_ReadAlarmCounter(hrtc);
+
+ /* Fill the structure with the read parameters */
+ /* Set hours in a day range (between 0 to 24)*/
+ sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600) % 24);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600) / 60);
+ sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600) % 60);
+
+ if(Format != RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactive the specified RTC Alarm
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Set to default values ALRH & ALRL registers */
+ WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER);
+ WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER);
+
+ /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_DISABLE_IT();
+
+ /* Wait for synchro */
+ if(RTC_ExitInitMode(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Alarm interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA))
+ {
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
+ {
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmA Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Returns the RTC state.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+ * are synchronized with RTC APB clock.
+ * @note This function must be called before any read operation after an APB reset
+ * or an APB clock stop.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear RSF flag */
+ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief Read the time counter available in RTC_CNT registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval Time counter
+ */
+static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
+{
+ uint16_t high1 = 0, high2 = 0, low = 0;
+ uint32_t timecounter = 0;
+
+ high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
+ low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
+ high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
+
+ if (high1 != high2)
+ { /* In this case the counter roll over during reading of CNTL and CNTH registers,
+ read again CNTL register then return the counter value */
+ timecounter = (((uint32_t) high2 << 16 ) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
+ }
+ else
+ { /* No counter roll over during reading of CNTL and CNTH registers, counter
+ value is equal to first value of CNTL and CNTH */
+ timecounter = (((uint32_t) high1 << 16 ) | low);
+ }
+
+ return timecounter;
+}
+
+/**
+ * @brief Write the time counter in RTC_CNT registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param TimeCounter: Counter to write in RTC_CNT registers
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Set RTC COUNTER MSB word */
+ WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16));
+ /* Set RTC COUNTER LSB word */
+ WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
+
+ /* Wait for synchro */
+ if(RTC_ExitInitMode(hrtc) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Read the time counter available in RTC_ALR registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval Time counter
+ */
+static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc)
+{
+ uint16_t high1 = 0, low = 0;
+
+ high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
+ low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
+
+ return (((uint32_t) high1 << 16 ) | low);
+}
+
+/**
+ * @brief Write the time counter in RTC_ALR registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param AlarmCounter: Counter to write in RTC_ALR registers
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Set RTC COUNTER MSB word */
+ WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16));
+ /* Set RTC COUNTER LSB word */
+ WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
+
+ /* Wait for synchro */
+ if(RTC_ExitInitMode(hrtc) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value: Byte to be converted
+ * @retval Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0;
+
+ while(Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Converts from 2 digit BCD to Binary.
+ * @param Value: BCD value to be converted
+ * @retval Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+ * @brief Updates date when time is 23:59:59.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param DayElapsed: Number of days elapsed from last date update
+ * @retval None
+ */
+static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed)
+{
+ uint32_t year = 0, month = 0, day = 0;
+ uint32_t loop = 0;
+
+ /* Get the current year*/
+ year = hrtc->DateToUpdate.Year;
+
+ /* Get the current month and day */
+ month = hrtc->DateToUpdate.Month;
+ day = hrtc->DateToUpdate.Date;
+
+ for (loop = 0; loop < DayElapsed; loop++)
+ {
+ if((month == 1) || (month == 3) || (month == 5) || (month == 7) || \
+ (month == 8) || (month == 10) || (month == 12))
+ {
+ if(day < 31)
+ {
+ day++;
+ }
+ /* Date structure member: day = 31 */
+ else
+ {
+ if(month != 12)
+ {
+ month++;
+ day = 1;
+ }
+ /* Date structure member: day = 31 & month =12 */
+ else
+ {
+ month = 1;
+ day = 1;
+ year++;
+ }
+ }
+ }
+ else if((month == 4) || (month == 6) || (month == 9) || (month == 11))
+ {
+ if(day < 30)
+ {
+ day++;
+ }
+ /* Date structure member: day = 30 */
+ else
+ {
+ month++;
+ day = 1;
+ }
+ }
+ else if(month == 2)
+ {
+ if(day < 28)
+ {
+ day++;
+ }
+ else if(day == 28)
+ {
+ /* Leap year */
+ if(RTC_IsLeapYear(year))
+ {
+ day++;
+ }
+ else
+ {
+ month++;
+ day = 1;
+ }
+ }
+ else if(day == 29)
+ {
+ month++;
+ day = 1;
+ }
+ }
+ }
+
+ /* Update year */
+ hrtc->DateToUpdate.Year = year;
+
+ /* Update day and month */
+ hrtc->DateToUpdate.Month = month;
+ hrtc->DateToUpdate.Date = day;
+
+ /* Update day of the week */
+ hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day);
+}
+
+/**
+ * @brief Check whether the passed year is Leap or not.
+ * @param nYear year to check
+ * @retval 1: leap year
+ * 0: not leap year
+ */
+static uint8_t RTC_IsLeapYear(uint16_t nYear)
+{
+ if((nYear % 4) != 0)
+ {
+ return 0;
+ }
+
+ if((nYear % 100) != 0)
+ {
+ return 1;
+ }
+
+ if((nYear % 400) == 0)
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/**
+ * @brief Determines the week number, the day number and the week day number.
+ * @param nYear year to check
+ * @param nMonth Month to check
+ * @param nDay Day to check
+ * @note Day is calculated with hypothesis that year > 2000
+ * @retval Value which can take one of the following parameters:
+ * @arg RTC_WEEKDAY_MONDAY
+ * @arg RTC_WEEKDAY_TUESDAY
+ * @arg RTC_WEEKDAY_WEDNESDAY
+ * @arg RTC_WEEKDAY_THURSDAY
+ * @arg RTC_WEEKDAY_FRIDAY
+ * @arg RTC_WEEKDAY_SATURDAY
+ * @arg RTC_WEEKDAY_SUNDAY
+ */
+static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
+{
+ uint32_t year = 0, weekday = 0;
+
+ year = 2000 + nYear;
+
+ if(nMonth < 3)
+ {
+ /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
+ weekday = (((23 * nMonth)/9) + nDay + 4 + year + ((year-1)/4) - ((year-1)/100) + ((year-1)/400)) % 7;
+ }
+ else
+ {
+ /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
+ weekday = (((23 * nMonth)/9) + nDay + 4 + year + (year/4) - (year/100) + (year/400) - 2 ) % 7;
+ }
+
+ return (uint8_t)weekday;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.h
new file mode 100644
index 000000000..49a44fa15
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.h
@@ -0,0 +1,570 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rtc.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RTC_H
+#define __STM32F1xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/** @addtogroup RTC_Private_Macros
+ * @{
+ */
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= (uint32_t)0xFFFFF) || ((PREDIV) == RTC_AUTO_1_SECOND))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
+#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
+ ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
+ ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
+ ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Private_Constants
+ * @{
+ */
+/** @defgroup RTC_Timeout_Value Default Timeout Value
+ * @{
+ */
+#define RTC_TIMEOUT_VALUE 1000
+/**
+ * @}
+ */
+
+/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
+ * @{
+ */
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND
+ If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin.
+ This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
+
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief Time Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
+ * @{
+ */
+#define RTC_AUTO_1_SECOND ((uint32_t)0xFFFFFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions Month Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A 0 /*!< Specify alarm ID (mainly for legacy purposes) */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
+ * @{
+ */
+
+#define RTC_OUTPUTSOURCE_NONE ((uint32_t)0x00000000) /*!< No output on the TAMPER pin */
+#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
+#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
+#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */
+#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */
+#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */
+#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions Flags Definitions
+ * @{
+ */
+#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */
+#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */
+#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */
+#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
+
+/**
+ * @brief Enable interrupt on ALARM Exti Line 17.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable interrupt on ALARM Exti Line 17.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Enable event on ALARM Exti Line 17.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on ALARM Exti Line 17.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
+
+
+/**
+ * @brief ALARM EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
+
+
+/**
+ * @brief Disable the ALARM Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
+
+
+/**
+ * @brief ALARM EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable the ALARM Extended Interrupt Rising Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief ALARM EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()();
+
+/**
+ * @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
+ * @retval EXTI ALARM Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Clear the ALARM EXTI flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extension module */
+#include "stm32f1xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* RTC Time and Date functions ************************************************/
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+
+/* RTC Alarm functions ********************************************************/
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup RTC_Exported_Functions_Group4
+ * @{
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup RTC_Exported_Functions_Group5
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.c
new file mode 100644
index 000000000..bf06c8418
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.c
@@ -0,0 +1,576 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extension peripheral:
+ * + RTC Tamper functions
+ * + Extension Control functions
+ * + Extension RTC features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/** @defgroup RTCEx RTCEx
+ * @brief RTC Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions
+ * @brief RTC Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Tamper feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper: Pointer to Tamper Structure.
+ * @note Tamper can be enabled only if ASOE and CCO bit are reset
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ /* Check input parameters */
+ if((hrtc == NULL) || (sTamper == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
+ {
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets Tamper with interrupt.
+ * @note By calling this API we force the tamper interrupt for all tampers.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTamper: Pointer to RTC Tamper.
+ * @note Tamper can be enabled only if ASOE and CCO bit are reset
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ /* Check input parameters */
+ if((hrtc == NULL) || (sTamper == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
+ {
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
+
+ /* Configure the Tamper Interrupt in the BKP->CSR */
+ __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates Tamper.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Tamper: Selected tamper pin.
+ * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the selected Tamper pin */
+ CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+
+ /* Disable the Tamper Interrupt in the BKP->CSR */
+ /* Configure the Tamper Interrupt in the BKP->CSR */
+ __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+ SET_BIT(BKP->CSR, BKP_CSR_CTE);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Tamper interrupt request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1))
+ {
+ /* Get the TAMPER Interrupt enable bit and pending bit */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
+ {
+ /* Tamper callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles Tamper1 Polling.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions
+ * @brief RTC Second functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Second functions #####
+ ===============================================================================
+
+ [..] This section provides functions implementing second interupt handlers
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets Interrupt for second
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc)
+{
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Enable Second interuption */
+ __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates Second.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc)
+{
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Deactivate Second interuption*/
+ __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles second interrupt request.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ if(__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC))
+ {
+ /* Get the status of the Interrupt */
+ if(__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC))
+ {
+ /* Check if Overrun occurred */
+ if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW))
+ {
+ /* Second error callback */
+ HAL_RTCEx_RTCEventErrorCallback(hrtc);
+
+ /* Clear flag Second */
+ __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ }
+ else
+ {
+ /* Second callback */
+ HAL_RTCEx_RTCEventCallback(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Clear flag Second */
+ __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC);
+ }
+ }
+}
+
+/**
+ * @brief Second event callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_RTCEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Second event error callback.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extension Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Writes a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Sets the Smooth calibration parameters.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
+ * specify the register (depending devices).
+ * @param Data: Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += (BackupRegister * 4);
+
+ *(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
+ * specify the register (depending devices).
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t backupregister = 0;
+ uint32_t pvalue = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ backupregister = (uint32_t)BKP_BASE;
+ backupregister += (BackupRegister * 4);
+
+ pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
+
+ /* Read the specified register */
+ return pvalue;
+}
+
+
+/**
+ * @brief Sets the Smooth calibration parameters.
+ * @param hrtc: RTC handle
+ * @param SmoothCalibPeriod: Not used (only present for compatibility with another families)
+ * @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families)
+ * @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value.
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
+{
+ /* Check input parameters */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Sets RTC Clock Calibration value.*/
+ MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.h
new file mode 100644
index 000000000..d9b9b6040
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.h
@@ -0,0 +1,430 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of RTC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RTC_EX_H
+#define __STM32F1xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @{
+ */
+
+/** @addtogroup RTCEx_Private_Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
+ * @{
+ */
+#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
+
+#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+#if RTC_BKP_NUMBER > 10
+#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t) RTC_BKP_DR10) || (((BKP) >= (uint32_t) RTC_BKP_DR11) && ((BKP) <= (uint32_t) RTC_BKP_DR42)))
+#else
+#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t) RTC_BKP_NUMBER)
+#endif
+#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007F)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+ * @{
+ */
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+}RTC_TamperTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
+#define RTC_TAMPERTRIGGER_HIGHLEVEL ((uint32_t)0x00000000) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
+ * @{
+ */
+#if RTC_BKP_NUMBER > 0
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#endif /* RTC_BKP_NUMBER > 0 */
+
+#if RTC_BKP_NUMBER > 10
+#define RTC_BKP_DR11 ((uint32_t)0x00000010)
+#define RTC_BKP_DR12 ((uint32_t)0x00000011)
+#define RTC_BKP_DR13 ((uint32_t)0x00000012)
+#define RTC_BKP_DR14 ((uint32_t)0x00000013)
+#define RTC_BKP_DR15 ((uint32_t)0x00000014)
+#define RTC_BKP_DR16 ((uint32_t)0x00000015)
+#define RTC_BKP_DR17 ((uint32_t)0x00000016)
+#define RTC_BKP_DR18 ((uint32_t)0x00000017)
+#define RTC_BKP_DR19 ((uint32_t)0x00000018)
+#define RTC_BKP_DR20 ((uint32_t)0x00000019)
+#define RTC_BKP_DR21 ((uint32_t)0x0000001A)
+#define RTC_BKP_DR22 ((uint32_t)0x0000001B)
+#define RTC_BKP_DR23 ((uint32_t)0x0000001C)
+#define RTC_BKP_DR24 ((uint32_t)0x0000001D)
+#define RTC_BKP_DR25 ((uint32_t)0x0000001E)
+#define RTC_BKP_DR26 ((uint32_t)0x0000001F)
+#define RTC_BKP_DR27 ((uint32_t)0x00000020)
+#define RTC_BKP_DR28 ((uint32_t)0x00000021)
+#define RTC_BKP_DR29 ((uint32_t)0x00000022)
+#define RTC_BKP_DR30 ((uint32_t)0x00000023)
+#define RTC_BKP_DR31 ((uint32_t)0x00000024)
+#define RTC_BKP_DR32 ((uint32_t)0x00000025)
+#define RTC_BKP_DR33 ((uint32_t)0x00000026)
+#define RTC_BKP_DR34 ((uint32_t)0x00000027)
+#define RTC_BKP_DR35 ((uint32_t)0x00000028)
+#define RTC_BKP_DR36 ((uint32_t)0x00000029)
+#define RTC_BKP_DR37 ((uint32_t)0x0000002A)
+#define RTC_BKP_DR38 ((uint32_t)0x0000002B)
+#define RTC_BKP_DR39 ((uint32_t)0x0000002C)
+#define RTC_BKP_DR40 ((uint32_t)0x0000002D)
+#define RTC_BKP_DR41 ((uint32_t)0x0000002E)
+#define RTC_BKP_DR42 ((uint32_t)0x0000002F)
+#endif /* RTC_BKP_NUMBER > 10 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP1: Tamper A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP1: Tamper A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
+
+/**
+ * @brief Enable the RTC Second interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_SEC: Second A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Second interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_SEC: Second A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Second interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_SEC: Second A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Second's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_SEC
+ * @retval None
+ */
+#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Second's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_SEC
+ * @retval None
+ */
+#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
+
+/**
+ * @brief Enable the RTC Overflow interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Overflow interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Overflow interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_OW: Overflow A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Overflow's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_OW
+ * @retval None
+ */
+#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Overflow's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_OW
+ * @retval None
+ */
+#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+/* RTC Tamper functions *****************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/* RTC Second functions *****************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc);
+void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
+
+/**
+ * @}
+ */
+
+/* Extension Control functions ************************************************/
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.c
new file mode 100644
index 000000000..729bc0254
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.c
@@ -0,0 +1,3442 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_sd.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief SD card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (SD) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDIO memories which uses the HAL
+ SDIO driver functions to interface with SD and uSD cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
+ (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
+ (##) SDIO pins configuration for SD card
+ (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+ and HAL_SD_WriteBlocks_DMA() APIs).
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+ (+++) Configure the SDIO and DMA interrupt priorities using functions
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
+ (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT()
+ and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
+ (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
+ and __HAL_SD_SDIO_CLEAR_IT()
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+ *** SD Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ the SD Card and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+ type (Standard Capacity or High Capacity). You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ The SD Card frequency (SDIO_CK) is computed as follows:
+
+ SDIO_CK = SDIOCLK / (ClockDiv + 2)
+
+ In initialization mode and according to the SD Card standard,
+ make sure that the SDIO_CK frequency doesn't exceed 400KHz.
+
+ (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
+ structure. This structure provide also ready computed SD Card capacity
+ and Block size.
+
+ -@- These information are stored in SD handle structure in case of future use.
+
+ (#) Configure the SD Card Data transfer frequency. The card transfer
+ frequency is set to SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2). You can change or adapt this frequency by adjusting
+ the "ClockDiv" field.
+ The SD Card frequency (SDIO_CK) is computed as follows:
+
+ SDIO_CK = SDIOCLK / (ClockDiv + 2)
+
+ In transfer mode and according to the SD Card standard, make sure that the
+ SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+
+ (#) Select the corresponding SD Card according to the address read with the step 2.
+
+ (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+ *** SD Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+
+ (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
+ that the read transfer is done correctly in both DMA and SD sides.
+
+ *** SD Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+
+ (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 byte).
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
+ that the write transfer is done correctly in both DMA and SD sides.
+
+ *** SD card status ***
+ ======================
+ [..]
+ (+) At any time, you can check the SD Card status and get the SD card state
+ by using the HAL_SD_GetStatus() function. This function checks first if the
+ SD card is still connected and then get the internal SD Card transfer state.
+ (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
+ function.
+
+ *** SD HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SD HAL driver.
+ (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
+ (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
+ (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
+ (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
+ (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
+ (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
+ (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
+ (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
+
+ -@- You can refer to the SD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SD SD
+ * @brief SD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup SD_Private_Define SD Private Constant
+ * @{
+ */
+/**
+ * @brief SDIO Data block size
+ */
+#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
+/**
+ * @brief SDIO Static flags, TimeOut, FIFO Address
+ */
+#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+ SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
+ SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
+ SDIO_FLAG_DBCKEND))
+
+#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
+
+/**
+ * @brief Mask for errors Card Status R1 (OCR Register)
+ */
+#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
+#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
+#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
+#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
+#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
+#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
+
+/**
+ * @brief Masks for R6 Response
+ */
+#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
+#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
+#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
+
+#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
+#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)
+#define SD_STD_CAPACITY ((uint32_t)0x00000000)
+#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)
+
+#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
+#define SD_ALLZERO ((uint32_t)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
+#define SD_CARD_LOCKED ((uint32_t)0x02000000)
+
+#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
+#define SD_0TO7BITS ((uint32_t)0x000000FF)
+#define SD_8TO15BITS ((uint32_t)0x0000FF00)
+#define SD_16TO23BITS ((uint32_t)0x00FF0000)
+#define SD_24TO31BITS ((uint32_t)0xFF000000)
+#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
+
+#define SD_HALFFIFO ((uint32_t)0x00000008)
+#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)
+
+/**
+ * @brief Command Class Supported
+ */
+#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
+#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
+#define SD_CCCC_ERASE ((uint32_t)0x00000020)
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDIO_APP_CMD should be sent before sending these commands.
+ */
+#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr);
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions SD Exported Functions
+ * @{
+ */
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the SD
+ card device to be ready for use.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SD card according to the specified parameters in the
+ SD_HandleTypeDef and create the associated handle.
+ * @param hsd: SD handle
+ * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
+ * @retval HAL SD error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
+{
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SD_InitTypeDef tmpinit = {0};
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_SD_MspInit(hsd);
+
+ /* Default SDIO peripheral configuration for SD card initialization */
+ tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ tmpinit.BusWide = SDIO_BUS_WIDE_1B;
+ tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ tmpinit.ClockDiv = SDIO_INIT_CLK_DIV;
+
+ /* Initialize SDIO peripheral interface with default configuration */
+ SDIO_Init(hsd->Instance, tmpinit);
+
+ /* Identify card operating voltage */
+ errorstate = SD_PowerON(hsd);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Initialize the present SDIO card(s) and put them in idle state */
+ errorstate = SD_Initialize_Cards(hsd);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Read CSD/CID MSD registers */
+ errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
+
+ if (errorstate == SD_OK)
+ {
+ /* Select the Card */
+ errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
+ }
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hsd->Instance, hsd->Init);
+
+ return errorstate;
+}
+
+/**
+ * @brief De-Initializes the SD card.
+ * @param hsd: SD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+
+ /* Set SD power state to off */
+ SD_PowerOFF(hsd);
+
+ /* De-Initialize the MSP layer */
+ HAL_SD_MspDeInit(hsd);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the SD MSP.
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize SD MSP.
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfer functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to SD card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @param hsd: SD handle
+ * @param pReadBuffer: pointer to the buffer that will contain the received data
+ * @param ReadAddr: Address from where data is to be read
+ * @param BlockSize: SD card Data block size (in bytes)
+ * This parameter should be 512
+ * @param NumberOfBlocks: Number of SD blocks to read
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ BlockSize = 512;
+ ReadAddr /= 512;
+ }
+
+ /* Set Block Size for Card */
+ sdio_cmdinitstructure.Argument = (uint32_t) BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
+ sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ if(NumberOfBlocks > 1)
+ {
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+ }
+ else
+ {
+ /* Send CMD17 READ_SINGLE_BLOCK */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+ }
+
+ sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1)
+ {
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Poll on SDIO flags */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDIO Rx FIFO */
+ for (count = 0; count < 8; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ tempbuff += 8;
+ }
+ }
+ }
+ else
+ {
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* In case of single block transfer, no need of stop transfer at all */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDIO Rx FIFO */
+ for (count = 0; count < 8; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ tempbuff += 8;
+ }
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock read */
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
+ {
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
+ (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ {
+ /* Send stop transmission command */
+ errorstate = HAL_SD_StopTransfer(hsd);
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ errorstate = SD_DATA_TIMEOUT;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ errorstate = SD_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ errorstate = SD_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ errorstate = SD_START_BIT_ERR;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ count = SD_DATATIMEOUT;
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+ {
+ *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+ tempbuff++;
+ count--;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return errorstate;
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @param hsd: SD handle
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
+ * @param WriteAddr: Address from where data is to be written
+ * @param BlockSize: SD card Data block size (in bytes)
+ * This parameter should be 512.
+ * @param NumberOfBlocks: Number of SD blocks to write
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
+ uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
+ uint8_t cardstate = 0;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ BlockSize = 512;
+ WriteAddr /= 512;
+ }
+
+ /* Set Block Size for Card */
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ if(NumberOfBlocks > 1)
+ {
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+ }
+ else
+ {
+ /* Send CMD24 WRITE_SINGLE_BLOCK */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+ }
+
+ sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ if(NumberOfBlocks > 1)
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+ }
+ else
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+ }
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Set total number of bytes to write */
+ totalnumberofbytes = NumberOfBlocks * BlockSize;
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Write block(s) in polling mode */
+ if(NumberOfBlocks > 1)
+ {
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+ {
+ if ((totalnumberofbytes - bytestransferred) < 32)
+ {
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
+
+ /* Write data to SDIO Tx FIFO */
+ for (count = 0; count < restwords; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, tempbuff);
+ tempbuff++;
+ bytestransferred += 4;
+ }
+ }
+ else
+ {
+ /* Write data to SDIO Tx FIFO */
+ for (count = 0; count < 8; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+ }
+
+ tempbuff += 8;
+ bytestransferred += 32;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* In case of single data block transfer no need of stop command at all */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+ {
+ if ((totalnumberofbytes - bytestransferred) < 32)
+ {
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
+
+ /* Write data to SDIO Tx FIFO */
+ for (count = 0; count < restwords; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, tempbuff);
+ tempbuff++;
+ bytestransferred += 4;
+ }
+ }
+ else
+ {
+ /* Write data to SDIO Tx FIFO */
+ for (count = 0; count < 8; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+ }
+
+ tempbuff += 8;
+ bytestransferred += 32;
+ }
+ }
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock write */
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
+ {
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ {
+ /* Send stop transmission command */
+ errorstate = HAL_SD_StopTransfer(hsd);
+ }
+ }
+
+ /* Get error state */
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ errorstate = SD_DATA_TIMEOUT;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ errorstate = SD_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
+
+ errorstate = SD_TX_UNDERRUN;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ errorstate = SD_START_BIT_ERR;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Wait till the card is in programming state */
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
+
+ while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+ {
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by the function HAL_SD_CheckReadOperation()
+ * to check the completion of the read process
+ * @param hsd: SD handle
+ * @param pReadBuffer: Pointer to the buffer that will contain the received data
+ * @param ReadAddr: Address from where data is to be read
+ * @param BlockSize: SD card Data block size
+ * @note BlockSize must be 512 bytes.
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+
+ /* Initialize handle flags */
+ hsd->SdTransferCplt = 0;
+ hsd->DmaTransferCplt = 0;
+ hsd->SdTransferErr = SD_OK;
+
+ /* Initialize SD Read operation */
+ if(NumberOfBlocks > 1)
+ {
+ hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
+ }
+ else
+ {
+ hsd->SdOperation = SD_READ_SINGLE_BLOCK;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_RXOVERR |\
+ SDIO_IT_STBITERR));
+
+ /* Enable SDIO DMA transfer */
+ __HAL_SD_SDIO_DMA_ENABLE(hsd);
+
+ /* Configure DMA user callbacks */
+ hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt;
+ hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
+
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ BlockSize = 512;
+ ReadAddr /= 512;
+ }
+
+ /* Set Block Size for Card */
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Check number of blocks command */
+ if(NumberOfBlocks > 1)
+ {
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+ }
+ else
+ {
+ /* Send CMD17 READ_SINGLE_BLOCK */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+ }
+
+ sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ if(NumberOfBlocks > 1)
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+ }
+ else
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+ }
+
+ /* Update the SD transfer error in SD handle */
+ hsd->SdTransferErr = errorstate;
+
+ return errorstate;
+}
+
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by the function HAL_SD_CheckWriteOperation()
+ * to check the completion of the write process (by SD current status polling).
+ * @param hsd: SD handle
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
+ * @param WriteAddr: Address from where data is to be read
+ * @param BlockSize: the SD card Data block size
+ * @note BlockSize must be 512 bytes.
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0;
+
+ /* Initialize handle flags */
+ hsd->SdTransferCplt = 0;
+ hsd->DmaTransferCplt = 0;
+ hsd->SdTransferErr = SD_OK;
+
+ /* Initialize SD Write operation */
+ if(NumberOfBlocks > 1)
+ {
+ hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
+ }
+ else
+ {
+ hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
+ }
+
+ /* Enable transfer interrupts */
+ __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+ SDIO_IT_DTIMEOUT |\
+ SDIO_IT_DATAEND |\
+ SDIO_IT_TXUNDERR |\
+ SDIO_IT_STBITERR));
+
+ /* Configure DMA user callbacks */
+ hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
+ hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
+
+ /* Enable SDIO DMA transfer */
+ __HAL_SD_SDIO_DMA_ENABLE(hsd);
+
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ BlockSize = 512;
+ WriteAddr /= 512;
+ }
+
+ /* Set Block Size for Card */
+ sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Check number of blocks command */
+ if(NumberOfBlocks <= 1)
+ {
+ /* Send CMD24 WRITE_SINGLE_BLOCK */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+ }
+ else
+ {
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+ }
+
+ sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ if(NumberOfBlocks > 1)
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+ }
+ else
+ {
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+ }
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ hsd->SdTransferErr = errorstate;
+
+ return errorstate;
+}
+
+/**
+ * @brief This function waits until the SD DMA data read transfer is finished.
+ * This API should be called after HAL_SD_ReadBlocks_DMA() function
+ * to insure that all data sent by the card is already transferred by the
+ * DMA controller.
+ * @param hsd: SD handle
+ * @param Timeout: Timeout duration
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t timeout = Timeout;
+ uint32_t tmp1, tmp2;
+ HAL_SD_ErrorTypedef tmp3;
+
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
+ tmp1 = hsd->DmaTransferCplt;
+ tmp2 = hsd->SdTransferCplt;
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
+ {
+ tmp1 = hsd->DmaTransferCplt;
+ tmp2 = hsd->SdTransferCplt;
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+ timeout--;
+ }
+
+ timeout = Timeout;
+
+ /* Wait until the Rx transfer is no longer active */
+ while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0))
+ {
+ timeout--;
+ }
+
+ /* Send stop command in multiblock read */
+ if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
+ {
+ errorstate = HAL_SD_StopTransfer(hsd);
+ }
+
+ if ((timeout == 0) && (errorstate == SD_OK))
+ {
+ errorstate = SD_DATA_TIMEOUT;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Return error state */
+ if (hsd->SdTransferErr != SD_OK)
+ {
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief This function waits until the SD DMA data write transfer is finished.
+ * This API should be called after HAL_SD_WriteBlocks_DMA() function
+ * to insure that all data sent by the card is already transferred by the
+ * DMA controller.
+ * @param hsd: SD handle
+ * @param Timeout: Timeout duration
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t timeout = Timeout;
+ uint32_t tmp1, tmp2;
+ HAL_SD_ErrorTypedef tmp3;
+
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
+ tmp1 = hsd->DmaTransferCplt;
+ tmp2 = hsd->SdTransferCplt;
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
+ {
+ tmp1 = hsd->DmaTransferCplt;
+ tmp2 = hsd->SdTransferCplt;
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+ timeout--;
+ }
+
+ timeout = Timeout;
+
+ /* Wait until the Tx transfer is no longer active */
+ while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT)) && (timeout > 0))
+ {
+ timeout--;
+ }
+
+ /* Send stop command in multiblock write */
+ if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
+ {
+ errorstate = HAL_SD_StopTransfer(hsd);
+ }
+
+ if ((timeout == 0) && (errorstate == SD_OK))
+ {
+ errorstate = SD_DATA_TIMEOUT;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Return error state */
+ if (hsd->SdTransferErr != SD_OK)
+ {
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
+ }
+
+ /* Wait until write is complete */
+ while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
+ {
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Erases the specified memory area of the given SD card.
+ * @param hsd: SD handle
+ * @param Startaddr: Start byte address
+ * @param Endaddr: End byte address
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+
+ uint32_t delay = 0;
+ __IO uint32_t maxdelay = 0;
+ uint8_t cardstate = 0;
+
+ /* Check if the card command class supports erase command */
+ if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
+ {
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
+
+ return errorstate;
+ }
+
+ /* Get max delay value */
+ maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ {
+ errorstate = SD_LOCK_UNLOCK_FAILED;
+
+ return errorstate;
+ }
+
+ /* Get start and end block for high capacity cards */
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ Startaddr /= 512;
+ Endaddr /= 512;
+ }
+
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ {
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
+ sdio_cmdinitstructure.Argument =(uint32_t)Startaddr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
+ sdio_cmdinitstructure.Argument = (uint32_t)Endaddr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+ }
+
+ /* Send CMD38 ERASE */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ for (; delay < maxdelay; delay++)
+ {
+ }
+
+ /* Wait untill the card is in programming state */
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
+
+ delay = SD_DATATIMEOUT;
+
+ while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+ {
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);
+ delay--;
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief This function handles SD card interrupt request.
+ * @param hsd: SD handle
+ * @retval None
+ */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+ /* Check for SDIO interrupt flags */
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);
+
+ /* SD transfer is complete */
+ hsd->SdTransferCplt = 1;
+
+ /* No transfer error */
+ hsd->SdTransferErr = SD_OK;
+
+ HAL_SD_XferCpltCallback(hsd);
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ hsd->SdTransferErr = SD_DATA_CRC_FAIL;
+
+ HAL_SD_XferErrorCallback(hsd);
+
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ hsd->SdTransferErr = SD_DATA_TIMEOUT;
+
+ HAL_SD_XferErrorCallback(hsd);
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ hsd->SdTransferErr = SD_RX_OVERRUN;
+
+ HAL_SD_XferErrorCallback(hsd);
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
+
+ hsd->SdTransferErr = SD_TX_UNDERRUN;
+
+ HAL_SD_XferErrorCallback(hsd);
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ hsd->SdTransferErr = SD_START_BIT_ERR;
+
+ HAL_SD_XferErrorCallback(hsd);
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Disable all SDIO peripheral interrupt sources */
+ __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
+ SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
+ SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+}
+
+
+/**
+ * @brief SD end of transfer callback.
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD Transfer Error callback.
+ * @param hsd: SD handle
+ * @retval None
+ */
+__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD Transfer complete Rx callback in non blocking mode.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD DMA transfer complete Rx error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD Transfer complete Tx callback in non blocking mode.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD DMA transfer complete error Tx callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SD card
+ operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information about specific card.
+ * @param hsd: SD handle
+ * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
+ * contains all SD cardinformation
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t tmp = 0;
+
+ pCardInfo->CardType = (uint8_t)(hsd->CardType);
+ pCardInfo->RCA = (uint16_t)(hsd->RCA);
+
+ /* Byte 0 */
+ tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
+ pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
+ pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
+ pCardInfo->SD_csd.Reserved1 = tmp & 0x03;
+
+ /* Byte 1 */
+ tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
+ pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
+ pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
+
+ /* Byte 3 */
+ tmp = hsd->CSD[0] & 0x000000FF;
+ pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
+ pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
+
+ /* Byte 5 */
+ tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
+ pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
+ pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);
+
+ /* Byte 6 */
+ tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
+ pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
+ pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
+ pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
+ pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4);
+ pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */
+
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
+ {
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+ pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+ pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
+
+ pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
+ pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+ pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
+ pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
+ pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+ pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
+
+ pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;
+ pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
+ pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
+ pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
+ }
+ else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ {
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+
+ pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+
+ pCardInfo->SD_csd.DeviceSize |= (tmp);
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+
+ pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
+ pCardInfo->CardBlockSize = 512;
+ }
+ else
+ {
+ /* Not supported card type */
+ errorstate = SD_ERROR;
+ }
+
+ pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
+ pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
+ pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
+ pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
+ pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
+ pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
+ pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
+ pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
+ pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
+ pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
+ pCardInfo->SD_csd.Reserved3 = 0;
+ pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
+ pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
+ pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
+ pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
+ pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
+ pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
+ pCardInfo->SD_csd.ECC = (tmp & 0x03);
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
+ pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
+ pCardInfo->SD_csd.Reserved4 = 1;
+
+ /* Byte 0 */
+ tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
+ pCardInfo->SD_cid.ManufacturerID = tmp;
+
+ /* Byte 1 */
+ tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
+ pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
+
+ /* Byte 2 */
+ tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
+ pCardInfo->SD_cid.OEM_AppliID |= tmp;
+
+ /* Byte 3 */
+ tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
+ pCardInfo->SD_cid.ProdName1 = tmp << 24;
+
+ /* Byte 4 */
+ tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
+ pCardInfo->SD_cid.ProdName1 |= tmp << 16;
+
+ /* Byte 5 */
+ tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
+ pCardInfo->SD_cid.ProdName1 |= tmp << 8;
+
+ /* Byte 6 */
+ tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
+ pCardInfo->SD_cid.ProdName1 |= tmp;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
+ pCardInfo->SD_cid.ProdName2 = tmp;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
+ pCardInfo->SD_cid.ProdRev = tmp;
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
+ pCardInfo->SD_cid.ProdSN = tmp << 24;
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
+ pCardInfo->SD_cid.ProdSN |= tmp << 16;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
+ pCardInfo->SD_cid.ProdSN |= tmp << 8;
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
+ pCardInfo->SD_cid.ProdSN |= tmp;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
+ pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
+ pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
+ pCardInfo->SD_cid.ManufactDate |= tmp;
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
+ pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
+ pCardInfo->SD_cid.Reserved2 = 1;
+
+ return errorstate;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hsd: SD handle
+ * @param WideMode: Specifies the SD card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
+ * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_InitTypeDef init = {0};
+
+ /* MMC Card does not support this feature */
+ if (hsd->CardType == MULTIMEDIA_CARD)
+ {
+ errorstate = SD_UNSUPPORTED_FEATURE;
+ }
+ else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ {
+ if (WideMode == SDIO_BUS_WIDE_8B)
+ {
+ errorstate = SD_UNSUPPORTED_FEATURE;
+ }
+ else if (WideMode == SDIO_BUS_WIDE_4B)
+ {
+ errorstate = SD_WideBus_Enable(hsd);
+ }
+ else if (WideMode == SDIO_BUS_WIDE_1B)
+ {
+ errorstate = SD_WideBus_Disable(hsd);
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ errorstate = SD_INVALID_PARAMETER;
+ }
+
+ if (errorstate == SD_OK)
+ {
+ /* Configure the SDIO peripheral */
+ init.ClockEdge = hsd->Init.ClockEdge;
+ init.ClockBypass = hsd->Init.ClockBypass;
+ init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ init.BusWide = WideMode;
+ init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ init.ClockDiv = hsd->Init.ClockDiv;
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hsd->Instance, init);
+ }
+ else
+ {
+ /* An error occured while enabling/disabling the wide bus*/
+ }
+ }
+ else
+ {
+ /* Not supported card type */
+ errorstate = SD_ERROR;
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Aborts an ongoing data transfer.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ /* Send CMD12 STOP_TRANSMISSION */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
+
+ return errorstate;
+}
+
+/**
+ * @brief Switches the SD card to High Speed mode.
+ * This API must be used after "Transfer State"
+ * @note This operation should be followed by the configuration
+ * of PLL to have SDIOCK clock between 67 and 75 MHz
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+
+ uint8_t SD_hs[64] = {0};
+ uint32_t SD_scr[2] = {0, 0};
+ uint32_t SD_SPEC = 0 ;
+ uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
+
+ /* Initialize the Data control register */
+ hsd->Instance->DCTRL = 0;
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, SD_scr);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Test the Version supported by the card*/
+ SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000);
+
+ if (SD_SPEC != SD_ALLZERO)
+ {
+ /* Set Block Size for Card */
+ sdio_cmdinitstructure.Argument = (uint32_t)64;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 64;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Send CMD6 switch mode */
+ sdio_cmdinitstructure.Argument = 0x80FFFF01;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ for (count = 0; count < 8; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ tempbuff += 8;
+ }
+ }
+
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ errorstate = SD_DATA_TIMEOUT;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ errorstate = SD_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ errorstate = SD_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ errorstate = SD_START_BIT_ERR;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ count = SD_DATATIMEOUT;
+
+ while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+ {
+ *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+ tempbuff++;
+ count--;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Test if the switch mode HS is ok */
+ if ((SD_hs[13]& 2) != 2)
+ {
+ errorstate = SD_UNSUPPORTED_FEATURE;
+ }
+ }
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in runtime the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the current SD card's status.
+ * @param hsd: SD handle
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * SD Status register)
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t count = 0;
+
+ /* Check SD response */
+ if ((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ {
+ errorstate = SD_LOCK_UNLOCK_FAILED;
+
+ return errorstate;
+ }
+
+ /* Set block size for card if it is not equal to current block size for card */
+ sdio_cmdinitstructure.Argument = 64;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD55 */
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 64;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get status data */
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ {
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ for (count = 0; count < 8; count++)
+ {
+ *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ pSDstatus += 8;
+ }
+ }
+
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ errorstate = SD_DATA_TIMEOUT;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ errorstate = SD_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ errorstate = SD_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ errorstate = SD_START_BIT_ERR;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ count = SD_DATATIMEOUT;
+ while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+ {
+ *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
+ pSDstatus++;
+ count--;
+ }
+
+ /* Clear all the static status flags*/
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return errorstate;
+}
+
+/**
+ * @brief Gets the current sd card data status.
+ * @param hsd: SD handle
+ * @retval Data Transfer state
+ */
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER;
+
+ /* Get SD card state */
+ cardstate = SD_GetState(hsd);
+
+ /* Find SD status according to card state*/
+ if (cardstate == SD_CARD_TRANSFER)
+ {
+ return SD_TRANSFER_OK;
+ }
+ else if(cardstate == SD_CARD_ERROR)
+ {
+ return SD_TRANSFER_ERROR;
+ }
+ else
+ {
+ return SD_TRANSFER_BUSY;
+ }
+}
+
+/**
+ * @brief Gets the SD card status.
+ * @param hsd: SD handle
+ * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
+ * will contain the SD card status information
+ * @retval SD Card error state
+ */
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t tmp = 0;
+ uint32_t sd_status[16];
+
+ errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
+
+ if (errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Byte 0 */
+ tmp = (sd_status[0] & 0xC0) >> 6;
+ pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
+
+ /* Byte 0 */
+ tmp = (sd_status[0] & 0x20) >> 5;
+ pCardStatus->SECURED_MODE = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (sd_status[2] & 0xFF);
+ pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
+
+ /* Byte 3 */
+ tmp = (sd_status[3] & 0xFF);
+ pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (sd_status[4] & 0xFF);
+ pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
+
+ /* Byte 5 */
+ tmp = (sd_status[5] & 0xFF);
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
+
+ /* Byte 6 */
+ tmp = (sd_status[6] & 0xFF);
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
+
+ /* Byte 7 */
+ tmp = (sd_status[7] & 0xFF);
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
+
+ /* Byte 8 */
+ tmp = (sd_status[8] & 0xFF);
+ pCardStatus->SPEED_CLASS = (uint8_t)tmp;
+
+ /* Byte 9 */
+ tmp = (sd_status[9] & 0xFF);
+ pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
+
+ /* Byte 10 */
+ tmp = (sd_status[10] & 0xF0) >> 4;
+ pCardStatus->AU_SIZE = (uint8_t)tmp;
+
+ /* Byte 11 */
+ tmp = (sd_status[11] & 0xFF);
+ pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
+
+ /* Byte 12 */
+ tmp = (sd_status[12] & 0xFF);
+ pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[13] & 0xFC) >> 2;
+ pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[13] & 0x3);
+ pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief SD DMA transfer complete Rx callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* DMA transfer is complete */
+ hsd->DmaTransferCplt = 1;
+
+ /* Wait until SD transfer is complete */
+ while(hsd->SdTransferCplt == 0)
+ {
+ }
+
+ /* Transfer complete user callback */
+ HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
+}
+
+/**
+ * @brief SD DMA transfer Error Rx callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Transfer complete user callback */
+ HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
+}
+
+/**
+ * @brief SD DMA transfer complete Tx callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* DMA transfer is complete */
+ hsd->DmaTransferCplt = 1;
+
+ /* Wait until SD transfer is complete */
+ while(hsd->SdTransferCplt == 0)
+ {
+ }
+
+ /* Transfer complete user callback */
+ HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
+}
+
+/**
+ * @brief SD DMA transfer Error Tx callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Transfer complete user callback */
+ HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
+}
+
+/**
+ * @brief Returns the SD current state.
+ * @param hsd: SD handle
+ * @retval SD card current state
+ */
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
+{
+ uint32_t resp1 = 0;
+
+ if (SD_SendStatus(hsd, &resp1) != SD_OK)
+ {
+ return SD_CARD_ERROR;
+ }
+ else
+ {
+ return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
+ }
+}
+
+/**
+ * @brief Initializes all cards or single card as the case may be Card(s) come
+ * into standby state.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint16_t sd_rca = 1;
+
+ if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
+ {
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
+
+ return errorstate;
+ }
+
+ if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
+ {
+ /* Send CMD2 ALL_SEND_CID */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp2Error(hsd);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get Card identification number data */
+ hsd->CID[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CID[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CID[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CID[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
+
+ if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+ (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ {
+ /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* SD Card publishes its RCA. */
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+ }
+
+ if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
+ {
+ /* Get the SD card RCA */
+ hsd->RCA = sd_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp2Error(hsd);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get Card Specific Data */
+ hsd->CSD[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CSD[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CSD[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CSD[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
+
+ /* All cards are initialized */
+ return errorstate;
+}
+
+/**
+ * @brief Selects od Deselects the corresponding card.
+ * @param hsd: SD handle
+ * @param Addr: Address of the card to be selected
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ /* Send CMD7 SDIO_SEL_DESEL_CARD */
+ sdio_cmdinitstructure.Argument = (uint32_t)Addr;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
+
+ return errorstate;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores SD information that will be needed in future
+ * in the SD handle.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t response = 0, count = 0, validvoltage = 0;
+ uint32_t sdtype = SD_STD_CAPACITY;
+
+ /* Power ON Sequence -------------------------------------------------------*/
+ /* Disable SDIO Clock */
+ __HAL_SD_SDIO_DISABLE(hsd);
+
+ /* Set Power State to ON */
+ SDIO_PowerState_ON(hsd->Instance);
+
+ /* 1ms: required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(1);
+
+ /* Enable SDIO Clock */
+ __HAL_SD_SDIO_ENABLE(hsd);
+
+ /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
+ /* No CMD response required */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdError(hsd);
+
+ if(errorstate != SD_OK)
+ {
+ /* CMD Response TimeOut (wait for CMDSENT flag) */
+ return errorstate;
+ }
+
+ /* CMD8: SEND_IF_COND ------------------------------------------------------*/
+ /* Send CMD8 to verify SD card interface operating condition */
+ /* Argument: - [31:12]: Reserved (shall be set to '0')
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ - [7:0]: Check Pattern (recommended 0xAA) */
+ /* CMD Response: R7 */
+ sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN;
+ sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp7Error(hsd);
+
+ if (errorstate == SD_OK)
+ {
+ /* SD Card 2.0 */
+ hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
+ sdtype = SD_HIGH_CAPACITY;
+ }
+
+ /* Send CMD55 */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ /* If errorstate is Command TimeOut, it is a MMC card */
+ /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
+ or SD card 1.x */
+ if(errorstate == SD_OK)
+ {
+ /* SD CARD */
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
+ {
+
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD41 */
+ sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp3Error(hsd);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31) == 1) ? 1 : 0);
+
+ count++;
+ }
+
+ if(count >= SD_MAX_VOLT_TRIAL)
+ {
+ errorstate = SD_INVALID_VOLTRANGE;
+
+ return errorstate;
+ }
+
+ if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ {
+ hsd->CardType = HIGH_CAPACITY_SD_CARD;
+ }
+
+ } /* else MMC Card */
+
+ return errorstate;
+}
+
+/**
+ * @brief Turns the SDIO output signals off.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ /* Set Power State to OFF */
+ SDIO_PowerState_OFF(hsd->Instance);
+
+ return errorstate;
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hsd: SD handle
+ * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * status (Card Status register)
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ if(pCardStatus == NULL)
+ {
+ errorstate = SD_INVALID_PARAMETER;
+
+ return errorstate;
+ }
+
+ /* Send Status command */
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get SD card status */
+ *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
+
+ tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
+
+ while((timeout > 0) && (!tmp))
+ {
+ tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
+ timeout--;
+ }
+
+ if(timeout == 0)
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+ return errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for R7 response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_ERROR;
+ uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
+
+ tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
+
+ while((!tmp) && (timeout > 0))
+ {
+ tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
+ timeout--;
+ }
+
+ tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ if((timeout == 0) || tmp)
+ {
+ /* Card is not V2.0 compliant or card does not support the set voltage range */
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
+ {
+ /* Card is SD V2.0 compliant */
+ errorstate = SD_OK;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
+
+ return errorstate;
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for R1 response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t response_r1 = 0;
+
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ {
+ }
+
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+ {
+ errorstate = SD_CMD_CRC_FAIL;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
+ {
+ errorstate = SD_ILLEGAL_CMD;
+
+ return errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it for analysis */
+ response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+ {
+ return errorstate;
+ }
+
+ if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
+ {
+ return(SD_ADDR_OUT_OF_RANGE);
+ }
+
+ if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
+ {
+ return(SD_ADDR_MISALIGNED);
+ }
+
+ if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+ {
+ return(SD_BLOCK_LEN_ERR);
+ }
+
+ if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+ {
+ return(SD_ERASE_SEQ_ERR);
+ }
+
+ if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+ {
+ return(SD_BAD_ERASE_PARAM);
+ }
+
+ if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+ {
+ return(SD_WRITE_PROT_VIOLATION);
+ }
+
+ if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+ {
+ return(SD_LOCK_UNLOCK_FAILED);
+ }
+
+ if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+ {
+ return(SD_COM_CRC_FAILED);
+ }
+
+ if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+ {
+ return(SD_ILLEGAL_CMD);
+ }
+
+ if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+ {
+ return(SD_CARD_ECC_FAILED);
+ }
+
+ if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+ {
+ return(SD_CC_ERROR);
+ }
+
+ if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+ {
+ return(SD_GENERAL_UNKNOWN_ERROR);
+ }
+
+ if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+ {
+ return(SD_STREAM_READ_UNDERRUN);
+ }
+
+ if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+ {
+ return(SD_STREAM_WRITE_OVERRUN);
+ }
+
+ if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
+ {
+ return(SD_CID_CSD_OVERWRITE);
+ }
+
+ if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+ {
+ return(SD_WP_ERASE_SKIP);
+ }
+
+ if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+ {
+ return(SD_CARD_ECC_DISABLED);
+ }
+
+ if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+ {
+ return(SD_ERASE_RESET);
+ }
+
+ if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+ {
+ return(SD_AKE_SEQ_ERROR);
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for R3 (OCR) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ {
+ }
+
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for R2 (CID or CSD) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ {
+ }
+
+ if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+ else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+ {
+ errorstate = SD_CMD_CRC_FAIL;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks for error conditions for R6 (RCA) response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * address RCA
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
+{
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t response_r1 = 0;
+
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ {
+ }
+
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+ {
+ errorstate = SD_CMD_CRC_FAIL;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
+ {
+ errorstate = SD_ILLEGAL_CMD;
+
+ return errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it. */
+ response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
+ {
+ *pRCA = (uint16_t) (response_r1 >> 16);
+
+ return errorstate;
+ }
+
+ if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
+ {
+ return(SD_GENERAL_UNKNOWN_ERROR);
+ }
+
+ if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
+ {
+ return(SD_ILLEGAL_CMD);
+ }
+
+ if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
+ {
+ return(SD_COM_CRC_FAILED);
+ }
+
+ return errorstate;
+}
+
+/**
+ * @brief Enables the SDIO wide bus mode.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ uint32_t scr[2] = {0, 0};
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ {
+ errorstate = SD_LOCK_UNLOCK_FAILED;
+
+ return errorstate;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports wide bus operation */
+ if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA.*/
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+ sdio_cmdinitstructure.Argument = 2;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ return errorstate;
+ }
+ else
+ {
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
+
+ return errorstate;
+ }
+}
+
+/**
+ * @brief Disables the SDIO wide bus mode.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+
+ uint32_t scr[2] = {0, 0};
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ {
+ errorstate = SD_LOCK_UNLOCK_FAILED;
+
+ return errorstate;
+ }
+
+ /* Get SCR Register */
+ errorstate = SD_FindSCR(hsd, scr);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* If requested card supports 1 bit mode operation */
+ if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+ {
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ return errorstate;
+ }
+ else
+ {
+ errorstate = SD_REQUEST_NOT_APPLICABLE;
+
+ return errorstate;
+ }
+}
+
+
+/**
+ * @brief Finds the SD card SCR register value.
+ * @param hsd: SD handle
+ * @param pSCR: pointer to the buffer that will contain the SCR value
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ SDIO_DataInitTypeDef sdio_datainitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t index = 0;
+ uint32_t tempscr[2] = {0, 0};
+
+ /* Set Block Size To 8 Bytes */
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = (uint32_t)8;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD55 APP_CMD with argument as card's RCA */
+ sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
+ sdio_datainitstructure.DataLength = 8;
+ sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+ sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+ sdio_cmdinitstructure.Argument = 0;
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ /* Check for error conditions */
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
+
+ if(errorstate != SD_OK)
+ {
+ return errorstate;
+ }
+
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ {
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+ {
+ *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
+ index++;
+ }
+ }
+
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+ errorstate = SD_DATA_TIMEOUT;
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+ errorstate = SD_DATA_CRC_FAIL;
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+ errorstate = SD_RX_OVERRUN;
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+ {
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+
+ errorstate = SD_START_BIT_ERR;
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\
+ ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
+
+ *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\
+ ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks if the SD card is in programming state.
+ * @param hsd: SD handle
+ * @param pStatus: pointer to the variable that will contain the SD card state
+ * @retval SD Card error state
+ */
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
+{
+ SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ HAL_SD_ErrorTypedef errorstate = SD_OK;
+ __IO uint32_t responseR1 = 0;
+
+ sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
+ sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
+ sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
+ sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
+ sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+
+ while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ {
+ }
+
+ if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ {
+ errorstate = SD_CMD_RSP_TIMEOUT;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+
+ return errorstate;
+ }
+ else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+ {
+ errorstate = SD_CMD_CRC_FAIL;
+
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+
+ return errorstate;
+ }
+ else
+ {
+ /* No error flag set */
+ }
+
+ /* Check response received is of desired command */
+ if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
+ {
+ errorstate = SD_ILLEGAL_CMD;
+
+ return errorstate;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+
+ /* We have received response, retrieve it for analysis */
+ responseR1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Find out card status */
+ *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
+
+ if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+ {
+ return errorstate;
+ }
+
+ if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
+ {
+ return(SD_ADDR_OUT_OF_RANGE);
+ }
+
+ if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
+ {
+ return(SD_ADDR_MISALIGNED);
+ }
+
+ if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+ {
+ return(SD_BLOCK_LEN_ERR);
+ }
+
+ if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+ {
+ return(SD_ERASE_SEQ_ERR);
+ }
+
+ if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+ {
+ return(SD_BAD_ERASE_PARAM);
+ }
+
+ if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+ {
+ return(SD_WRITE_PROT_VIOLATION);
+ }
+
+ if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+ {
+ return(SD_LOCK_UNLOCK_FAILED);
+ }
+
+ if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+ {
+ return(SD_COM_CRC_FAILED);
+ }
+
+ if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+ {
+ return(SD_ILLEGAL_CMD);
+ }
+
+ if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+ {
+ return(SD_CARD_ECC_FAILED);
+ }
+
+ if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+ {
+ return(SD_CC_ERROR);
+ }
+
+ if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+ {
+ return(SD_GENERAL_UNKNOWN_ERROR);
+ }
+
+ if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+ {
+ return(SD_STREAM_READ_UNDERRUN);
+ }
+
+ if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+ {
+ return(SD_STREAM_WRITE_OVERRUN);
+ }
+
+ if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
+ {
+ return(SD_CID_CSD_OVERWRITE);
+ }
+
+ if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+ {
+ return(SD_WP_ERASE_SKIP);
+ }
+
+ if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+ {
+ return(SD_CARD_ECC_DISABLED);
+ }
+
+ if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+ {
+ return(SD_ERASE_RESET);
+ }
+
+ if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+ {
+ return(SD_AKE_SEQ_ERROR);
+ }
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.h
new file mode 100644
index 000000000..deb8fd5f2
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.h
@@ -0,0 +1,709 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_sd.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of SD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_SD_H
+#define __STM32F1xx_HAL_SD_H
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+ * @{
+ */
+
+#define SD_InitTypeDef SDIO_InitTypeDef
+#define SD_TypeDef SDIO_TypeDef
+
+/**
+ * @brief SDIO Handle Structure definition
+ */
+typedef struct
+{
+ SD_TypeDef *Instance; /*!< SDIO register base address */
+
+ SD_InitTypeDef Init; /*!< SD required parameters */
+
+ HAL_LockTypeDef Lock; /*!< SD locking object */
+
+ uint32_t CardType; /*!< SD card type */
+
+ uint32_t RCA; /*!< SD relative card address */
+
+ uint32_t CSD[4]; /*!< SD card specific data table */
+
+ uint32_t CID[4]; /*!< SD card identification number table */
+
+ __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
+
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+
+ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
+
+ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+}SD_HandleTypeDef;
+
+/**
+ * @brief Card Specific Data: CSD Register
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_SD_CSDTypedef;
+
+/**
+ * @brief Card Identification Data: CID Register
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_SD_CIDTypedef;
+
+/**
+ * @brief SD Card Status returned by ACMD13
+ */
+typedef struct
+{
+ __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
+ __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
+ __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
+ __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
+
+}HAL_SD_CardStatusTypedef;
+
+/**
+ * @brief SD Card information structure
+ */
+typedef struct
+{
+ HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
+ HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
+ uint64_t CardCapacity; /*!< Card capacity */
+ uint32_t CardBlockSize; /*!< Card block size */
+ uint16_t RCA; /*!< SD relative card address */
+ uint8_t CardType; /*!< SD card type */
+
+}HAL_SD_CardInfoTypedef;
+
+/**
+ * @brief SD Error status enumeration Structure definition
+ */
+typedef enum
+{
+/**
+ * @brief SD specific error defines
+ */
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
+ SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
+ SD_DATA_TIMEOUT = (4), /*!< Data timeout */
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
+ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
+ SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
+ SD_CC_ERROR = (18), /*!< Internal card controller error */
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
+ SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
+ SD_INVALID_VOLTRANGE = (27),
+ SD_ADDR_OUT_OF_RANGE = (28),
+ SD_SWITCH_ERROR = (29),
+ SD_SDIO_DISABLED = (30),
+ SD_SDIO_FUNCTION_BUSY = (31),
+ SD_SDIO_FUNCTION_FAILED = (32),
+ SD_SDIO_UNKNOWN_FUNCTION = (33),
+
+/**
+ * @brief Standard error defines
+ */
+ SD_INTERNAL_ERROR = (34),
+ SD_NOT_CONFIGURED = (35),
+ SD_REQUEST_PENDING = (36),
+ SD_REQUEST_NOT_APPLICABLE = (37),
+ SD_INVALID_PARAMETER = (38),
+ SD_UNSUPPORTED_FEATURE = (39),
+ SD_UNSUPPORTED_HW = (40),
+ SD_ERROR = (41),
+ SD_OK = (0)
+
+}HAL_SD_ErrorTypedef;
+
+/**
+ * @brief SD Transfer state enumeration structure
+ */
+typedef enum
+{
+ SD_TRANSFER_OK = 0, /*!< Transfer success */
+ SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
+ SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
+
+}HAL_SD_TransferStateTypedef;
+
+/**
+ * @brief SD Card State enumeration structure
+ */
+typedef enum
+{
+ SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */
+ SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */
+ SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */
+ SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
+
+}HAL_SD_CardStateTypedef;
+
+/**
+ * @brief SD Operation enumeration structure
+ */
+typedef enum
+{
+ SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
+ SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */
+ SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */
+ SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
+
+}HAL_SD_OperationTypedef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants SD Exported Constants
+ * @{
+ */
+
+/**
+ * @brief SD Commands Index
+ */
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
+#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
+#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
+#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
+#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
+#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SD_CMD_NO_CMD ((uint8_t)64)
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDIO_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
+#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
+#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SD_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */
+
+/**
+ * @brief Supported SD Memory Cards
+ */
+#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SD device.
+ * @param __HANDLE__: SD Handle
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SD device.
+ * @param __HANDLE__: SD Handle
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @param __HANDLE__: SD Handle
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @param __HANDLE__: SD Handle
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SD FLAG (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the SD's pending flags.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified SD interrupt has occurred or not.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
+
+/**
+ * @brief Clear the SD's interrupt pending bits.
+ * @param __HANDLE__ : SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions **********************************/
+/** @addtogroup SD_Exported_Functions_Group1
+ * @{
+ */
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup SD_Exported_Functions_Group2
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup SD_Exported_Functions_Group3
+ * @{
+ */
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions **************************************************/
+/** @addtogroup SD_Exported_Functions_Group4
+ * @{
+ */
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#endif /* __STM32F1xx_HAL_SD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.c
new file mode 100644
index 000000000..424486021
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.c
@@ -0,0 +1,1305 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (##) Enable the interface clock of the USARTx associated to the SMARTCARD.
+ (##) SMARTCARD pins configuration:
+ (+++) Enable the clock for the SMARTCARD GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
+
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_SMARTCARD_MspInit(&hsc) API.
+
+ -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether the specified SMARTCARD interrupt has occurred or not
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief HAL SMARTCARD module driver
+ * @{
+ */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros --------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in Smartcard mode.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) For the Smartcard mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length => Should be 9 bits (8 bits + parity)
+ (++) Stop Bit
+ (++) Parity: => Should be enabled
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | SMARTCARD frame |
+ |---------------------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+ (++) Prescaler
+ (++) GuardTime
+ (++) NACKState: The Smartcard NACK state
+
+ (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
+ (++) Word Length = 9 Bits
+ (++) 1.5 Stop Bit
+ (++) Even parity
+ (++) BaudRate = 12096 baud
+ (++) Tx and Rx enabled
+ [..]
+ Please refer to the ISO 7816-3 specification for more details.
+
+ -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching
+ between the two configurations.
+ [..]
+ The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
+ procedure (details for the procedure are available in reference manuals
+ (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SmartCard mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and create the associated handle.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check Wordlength, Parity and Stop bits parameters */
+ if ( (!(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)))
+ ||(!(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)))
+ ||(!(IS_SMARTCARD_PARITY(hsc->Init.Parity))) )
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+ assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+ assert_param(IS_SMARTCARD_PRESCALER(hsc->Init.Prescaler));
+
+ if(hsc->State == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsc-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_SMARTCARD_MspInit(hsc);
+ }
+
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsc);
+
+ /* Set the Prescaler */
+ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
+
+ /* Set the Guard Time */
+ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
+
+ /* Set the Smartcard Communication parameters */
+ SMARTCARD_SetConfig(hsc);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+
+ /* Enable the Peripharal */
+ __HAL_SMARTCARD_ENABLE(hsc);
+
+ /* Configure the Smartcard NACK state */
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
+
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);
+
+ /* Initialize the SMARTCARD state*/
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->State= HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SMARTCARD peripheral
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsc);
+
+ hsc->Instance->CR1 = 0x0;
+ hsc->Instance->CR2 = 0x0;
+ hsc->Instance->CR3 = 0x0;
+ hsc->Instance->BRR = 0x0;
+ hsc->Instance->GTPR = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_SMARTCARD_MspDeInit(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->State = HAL_SMARTCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SMARTCARD MSP Init.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD MSP DeInit.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (#) Blocking mode APIs are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends an amount of data in blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+ while(hsc->TxXferCount > 0)
+ {
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF));
+ hsc->TxXferCount--;
+ }
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ hsc->RxXferSize = Size;
+ hsc->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(hsc->RxXferCount > 0)
+ {
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+ hsc->RxXferCount--;
+ }
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pTxBuffPtr = pData;
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+ /* Enable the SMARTCARD Transmit data register empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pRxBuffPtr = pData;
+ hsc->RxXferSize = Size;
+ hsc->RxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Data Register not empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pTxBuffPtr = pData;
+ hsc->TxXferSize = Size;
+ hsc->TxXferCount = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp = 0;
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsc);
+
+ hsc->pRxBuffPtr = pData;
+ hsc->RxXferSize = Size;
+
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles SMARTCARD interrupt request.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t tmp_flag = 0, tmp_it_source = 0;
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE);
+ tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
+ /* SMARTCARD parity error interrupt occurred -----------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE);
+ tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
+ /* SMARTCARD frame error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE);
+ /* SMARTCARD noise error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE);
+ /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE);
+ tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
+ /* SMARTCARD in mode Receiver --------------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ SMARTCARD_Receive_IT(hsc);
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE);
+ tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
+ /* SMARTCARD in mode Transmitter -----------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsc);
+ }
+
+ tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC);
+ tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsc);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsc->State= HAL_SMARTCARD_STATE_READY;
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SMARTCARD state.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
+{
+ return hsc->State;
+}
+
+/**
+ * @brief Return the SMARTCARD error code
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD Error Code
+ */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
+{
+ return hsc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @brief SMARTCARD Private functions
+ * @{
+ */
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD CR3 register */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->RxXferCount = 0;
+ hsc->TxXferCount = 0;
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+ hsc->State= HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
+/**
+ * @brief This function handles SMARTCARD Communication Timeout.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag: specifies the SMARTCARD flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE and RXNE interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+
+ hsc->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE and RXNE interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+
+ hsc->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+ WRITE_REG(hsc->Instance->DR, (*hsc->pTxBuffPtr++ & (uint8_t)0xFF));
+
+ if(--hsc->TxXferCount == 0)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = hsc->State;
+ if((tmp_state == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+ *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+
+ if(--hsc->RxXferCount == 0)
+ {
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsc);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the SMARTCARD peripheral.
+ * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
+ assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
+ /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+ receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+ CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+ /*------ SMARTCARD-associated USART registers setting : CR2 Configuration ------*/
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
+ /* Set CPOL bit according to hsc->Init.CLKPolarity value */
+ /* Set CPHA bit according to hsc->Init.CLKPhase value */
+ /* Set LBCL bit according to hsc->Init.CLKLastBit value */
+ MODIFY_REG(hsc->Instance->CR2,
+ ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)),
+ ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) );
+
+ /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits));
+
+ /*------ SMARTCARD-associated USART registers setting : CR1 Configuration ------*/
+ /* Clear M, PCE, PS, TE and RE bits */
+ /* Configure the SMARTCARD Word Length, Parity and mode:
+ Set the M according to hsc->Init.WordLength value (forced to 1 as 9B data frame should be selected)
+ Set PCE and PS bits according to hsc->Init.Parity value (PCE bit forced to 1 as parity control should always be enabled)
+ Set TE and RE bits according to hsc->Init.Mode value */
+ MODIFY_REG(hsc->Instance->CR1,
+ ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
+ ((uint32_t)(USART_CR1_M | USART_CR1_PCE | hsc->Init.Parity | hsc->Init.Mode)) );
+
+ /*------ SMARTCARD-associated USART registers setting : CR3 Configuration ------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /*------ SMARTCARD-associated USART registers setting : BRR Configuration ------*/
+ if(hsc->Instance == USART1)
+ {
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ }
+ else
+ {
+ hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.h
new file mode 100644
index 000000000..8c8eb4ffd
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.h
@@ -0,0 +1,668 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_SMARTCARD_H
+#define __STM32F1xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref SMARTCARD_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits).*/
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
+ to provide the smartcard clock
+ This parameter can be a value of @ref SMARTCARD_Prescaler */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
+ The value given in the register (5 significant bits) is multiplied by 2
+ to give the division factor of the source clock frequency */
+
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
+ This parameter can be a value of @ref SMARTCARD_NACK_State */
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+}HAL_SMARTCARD_StateTypeDef;
+
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+}SMARTCARD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
+ * @{
+ */
+
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
+ * @{
+ */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
+#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
+#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask (16 bits) in the Y register
+ * - Y : Interrupt source register (4 bits)
+ * - 0001: CR1 register
+ * - 0010: CR3 register
+
+ *
+ * @{
+ */
+
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+
+/** @brief Reset SMARTCARD handle state
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief Flush the Smartcard DR register
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
+ * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified Smartcard pending flags.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
+ * @retval None
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
+ * error) flags are cleared by software sequence: a read operation to
+ * USART_SR register followed by a read operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+}while(0)
+
+
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified SmartCard interrupt.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief Disable the specified SmartCard interrupts.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+
+/** @brief Enable the SmartCard DMA request.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __REQUEST__: specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
+
+/** @brief Disable the SmartCard DMA request.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __REQUEST__: specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+#define SMARTCARD_CR1_REG_INDEX 1
+#define SMARTCARD_CR3_REG_INDEX 3
+
+#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
+#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100)
+#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
+#define SMARTCARD_BRR(__PCLK__, __BAUD__) ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
+
+/** Check the Baud rate range.
+ * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 16)
+ * __BAUDRATE__: Baud rate set by the configuration function.
+ * Return : TRUE or FALSE
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \
+ ((MODE) != (uint32_t)0x00000000))
+
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+
+#define IS_SMARTCARD_PRESCALER(PRESCALER) (((PRESCALER) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
+ ((PRESCALER) <= SMARTCARD_PRESCALER_SYSCLK_DIV62) )
+
+/** SMARTCARD interruptions flag mask
+ *
+ */
+#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR3_EIE )
+
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions functions *****************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c
new file mode 100644
index 000000000..75cbb4cd9
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c
@@ -0,0 +1,2398 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_spi.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief SPI HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Channel
+ (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
+
+ (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+
+ For 8 bits SPI data size transfers :
+ +--------------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==================================================================================================|
+ | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA |
+ | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 |
+ +--------------------------------------------------------------------------------------------------+
+
+ For 16 bits SPI data size transfers :
+ +--------------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==================================================================================================|
+ | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA |
+ | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
+ +--------------------------------------------------------------------------------------------------+
+
+ @note The max SPI frequency depend on SPI data size (8bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_TIMEOUT_VALUE 10
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR(SPI_HandleTypeDef *hspi);
+static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
+static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR(SPI_HandleTypeDef *hspi);
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx periperal.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and create the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+
+ if(hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disble the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
+
+ /* Configure : NSS management */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SPI peripheral
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SPI MSP Init
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+ {
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief SPI MSP DeInit
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->TxISR = 0;
+ hspi->RxISR = 0;
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ /* Configure communication direction : 1Line */
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ while(hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+ }
+ /* Transmit data in 16 Bit mode */
+ else
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+ }
+
+ while(hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+ }
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+ }
+
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ __IO uint16_t tmpreg = 0;
+
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = 0;
+ hspi->TxISR = 0;
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Receive data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ while(hspi->RxXferCount > 1)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ /* Enable CRC Reception */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+ }
+ /* Receive data in 16 Bit mode */
+ else
+ {
+ while(hspi->RxXferCount > 1)
+ {
+ /* Wait until RXNE flag is set to read data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ hspi->RxXferCount--;
+ }
+ /* Enable CRC Reception */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+ }
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Receive last data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ }
+ /* Receive last data in 16 Bit mode */
+ else
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ }
+ hspi->RxXferCount--;
+
+ /* If CRC computation is enabled */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set: CRC Received */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ return HAL_TIMEOUT;
+ }
+
+ /* Read CRC to clear RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer to be
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ __IO uint16_t tmpreg = 0;
+
+ if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Configure communication */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = 0;
+ hspi->TxISR = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+ }
+ if(hspi->TxXferCount == 0)
+ {
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ while(hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ hspi->RxXferCount--;
+ }
+ /* Receive the last byte */
+ if(hspi->Init.Mode == SPI_MODE_SLAVE)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ hspi->RxXferCount--;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ {
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+ if(hspi->TxXferCount == 0)
+ {
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ while(hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ if(hspi->Init.Mode == SPI_MODE_SLAVE)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ }
+ }
+
+ /* Read CRC from DR to close CRC calculation process */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ return HAL_TIMEOUT;
+ }
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+ }
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ SPI_RESET_CRC(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in no-blocking mode with Interrupt
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->TxISR = &SPI_TxISR;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = 0;
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
+ }
+ else
+ {
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->RxISR = &SPI_RxISR;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size ;
+
+ /*Init field not used in handle to zero */
+ hspi->TxISR = 0;
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+ else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer to be
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+
+ if((hspi->State == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Configure communication */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->TxISR = &SPI_TxISR;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ hspi->RxISR = &SPI_2LinesRxISR;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in no-blocking mode with DMA
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->TxISR = 0;
+ hspi->RxISR = 0;
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Reset content of SPI RxDMA descriptor */
+ hspi->hdmarx->XferHalfCpltCallback = 0;
+ hspi->hdmarx->XferCpltCallback = 0;
+ hspi->hdmarx->XferErrorCallback = 0;
+
+ /* Enable the Tx DMA Channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in no-blocking mode with DMA
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = 0;
+ hspi->TxISR = 0;
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+ else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Reset content of SPI TxDMA descriptor */
+ hspi->hdmatx->XferHalfCpltCallback = 0;
+ hspi->hdmatx->XferCpltCallback = 0;
+ hspi->hdmatx->XferErrorCallback = 0;
+
+ /* Enable the Rx DMA Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ if((hspi->State == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Configure communication */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ hspi->pTxBuffPtr = (uint8_t*)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ hspi->pRxBuffPtr = (uint8_t*)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = 0;
+ hspi->TxISR = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable the Rx DMA Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ }
+ else
+ {
+ hspi->hdmatx->XferErrorCallback = NULL;
+ }
+
+ /* Enable the Tx DMA Channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Channel */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx Channel */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SPI interrupt request.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
+ if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Tramitter ---------------------------------------------------*/
+ if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
+ {
+ /* SPI CRC error interrupt occurred ---------------------------------------*/
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ /* SPI Mode Fault error interrupt occurred --------------------------------*/
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Overrun error interrupt occurred -----------------------------------*/
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
+ {
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
+ {
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief SPI error callbacks
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : - This function Should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback() could be implenetd in the user file.
+ - The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI state
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI Error Code
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+
+ /**
+ * @brief Interrupt Handler to close Tx transfer
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+{
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
+
+ /* Disable ERR interrupt if Receive process is finished */
+ if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
+ {
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ /* Check if we are in Tx or in Rx/Tx Mode */
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ else
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call Error call back in case of Error */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Interrupt Handler to transmit amount of data in no-blocking mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ }
+ /* Transmit data in 16 Bit mode */
+ else
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr+=2;
+ }
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* calculate and transfer CRC on Tx line */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+ SPI_TxCloseIRQHandler(hspi);
+ }
+}
+
+/**
+ * @brief Interrupt Handler to close Rx transfer
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg = 0;
+
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set to read CRC data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Read CRC to reset RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Wait until RXNE flag is reset */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+ }
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
+
+ /* if Transmit process is finished */
+ if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
+ {
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ /* Check if we are in Rx or in Rx/Tx Mode */
+ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ else
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ /* Set state to READY before run the Callback Complete */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call Error call back in case of Error */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Interrupt Handler to receive amount of data in 2Lines mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ }
+ /* Receive data in 16 Bit mode */
+ else
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ }
+ hspi->RxXferCount--;
+
+ if(hspi->RxXferCount==0)
+ {
+ SPI_RxCloseIRQHandler(hspi);
+ }
+}
+
+/**
+ * @brief Interrupt Handler to receive amount of data in no-blocking mode
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ }
+ /* Receive data in 16 Bit mode */
+ else
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr+=2;
+ }
+ hspi->RxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set CRC Next to calculate CRC on Rx side */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+
+ if(hspi->RxXferCount == 0)
+ {
+ SPI_RxCloseIRQHandler(hspi);
+ }
+}
+
+/**
+ * @brief DMA SPI transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal Mode */
+ if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ hspi->TxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+ }
+
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @brief DMA SPI receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ __IO uint16_t tmpreg = 0;
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
+ {
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* CRC Calculation handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until RXNE flag is set (CRC ready) */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Wait until RXNE flag is reset */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+ }
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ __IO uint16_t tmpreg = 0;
+
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
+ {
+ /* CRC Calculation handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Check if CRC is done on going (RXNE flag set) */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /* Wait until RXNE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ }
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg);
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+
+ /* Wait until TXE flag is set to send data */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Wait until Busy flag is reset before disabling SPI */
+ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Half transmit receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+ hspi->State= HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief This function handles SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param Status: Flag status to check: RESET or set
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
+ * according to SPI instance, Device type, and revision ID.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
+*/
+__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
+{
+ return (SPI_VALID_CRC_ERROR);
+}
+/**
+ * @}
+ */
+
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.h
new file mode 100644
index 000000000..be40c041e
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.h
@@ -0,0 +1,674 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_spi.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_SPI_H
+#define __STM32F1xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint32_t Direction; /*!< Specifies the SPI Directional mode state.
+ This parameter can be a value of @ref SPI_Direction_mode */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+}SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
+ HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
+
+}HAL_SPI_StateTypeDef;
+
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx transfer size */
+
+ uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx transfer size */
+
+ uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
+
+ HAL_LockTypeDef Lock; /*!< SPI locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
+
+}SPI_HandleTypeDef;
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error_Codes SPI Error Codes
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */
+#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup SPI_mode SPI mode
+ * @{
+ */
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction_mode SPI Direction mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size SPI data size
+ * @{
+ */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
+#define SPI_DATASIZE_16BIT SPI_CR1_DFF
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI mode disable
+ * @brief SPI TI Mode not supported for STM32F1xx family
+ * @{
+ */
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flag_definition SPI Flag definition
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE
+#define SPI_FLAG_TXE SPI_SR_TXE
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR
+#define SPI_FLAG_MODF SPI_SR_MODF
+#define SPI_FLAG_OVR SPI_SR_OVR
+#define SPI_FLAG_BSY SPI_SR_BSY
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */
+#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Check if the specified SPI interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg); \
+}while(0)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+}while(0)
+
+
+/** @brief Enables the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/** @brief Disables the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/**
+ * @}
+ */
+
+
+/* Private macros -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Checks if SPI Mode parameter is in allowed range.
+ * @param __MODE__: specifies the SPI Mode.
+ * This parameter can be a value of @ref SPI_mode
+ * @retval None
+ */
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
+
+/** @brief Checks if SPI Direction Mode parameter is in allowed range.
+ * @param __MODE__: specifies the SPI Direction Mode.
+ * This parameter can be a value of @ref SPI_Direction_mode
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
+ * @param __MODE__: specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Direction Mode parameter is 2 lines.
+ * @param __MODE__: specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
+
+/** @brief Checks if SPI Data Size parameter is in allowed range.
+ * @param __DATASIZE__: specifies the SPI Data Size.
+ * This parameter can be a value of @ref SPI_data_size
+ * @retval None
+ */
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_8BIT))
+
+/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__: specifies the SPI serial clock steady state.
+ * This parameter can be a value of @ref SPI_Clock_Polarity
+ * @retval None
+ */
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
+
+/** @brief Checks if SPI Clock Phase parameter is in allowed range.
+ * @param __CPHA__: specifies the SPI Clock Phase.
+ * This parameter can be a value of @ref SPI_Clock_Phase
+ * @retval None
+ */
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
+
+/** @brief Checks if SPI Slave select parameter is in allowed range.
+ * @param __NSS__: specifies the SPI Slave Slelect management parameter.
+ * This parameter can be a value of @ref SPI_Slave_Select_management
+ * @retval None
+ */
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+
+/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
+ * @param __PRESCALER__: specifies the SPI Baudrate prescaler.
+ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ * @retval None
+ */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
+
+/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
+ * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
+ * This parameter can be a value of @ref SPI_MSB_LSB_transmission
+ * @retval None
+ */
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
+
+/** @brief Checks if SPI TI mode parameter is in allowed range.
+ * @param __MODE__: specifies the SPI TI mode.
+ * This parameter can be a value of @ref SPI_TI_mode
+ * @retval None
+ */
+#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
+
+/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
+ * @param __CALCULATION__: specifies the SPI CRC calculation enable state.
+ * This parameter can be a value of @ref SPI_CRC_Calculation
+ * @retval None
+ */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
+
+/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
+ * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
+ * @retval None
+ */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF))
+
+/** @brief Sets the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Sets the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Resets the CRC calculation of the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/* I/O operation functions *****************************************************/
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+
+/* Peripheral State and Control functions **************************************/
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions --------------------------------------------------------*/
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c
new file mode 100644
index 000000000..77d28232b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c
@@ -0,0 +1,217 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Extended SPI HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities SPI extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/** @defgroup SPI_Private_Variables SPI Private Variables
+ * @{
+ */
+/* Variable used to determine if device is impacted by implementation of workaround
+ related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
+ - STM32F101CDE/STM32F103CDE
+ - Revision ID : Z
+ - SPI2
+ - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
+ the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
+ + If the value is 0, the complete data transfer is successful.
+ + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
+ If CRCERR is found reset, the complete data transfer is considered successful.
+*/
+uint8_t uCRCErrorWorkaroundCheck = 0;
+/**
+ * @}
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1
+ *
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and create the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+
+ if(hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disble the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
+
+ /* Configure : NSS management */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+
+#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif
+
+#if defined (STM32F101xE) || defined (STM32F103xE)
+ /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
+ CRC errors wrongly detected */
+ /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
+ Revision ID information is only available in Debug mode, so Workaround could not be implemented
+ to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
+ So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
+ uCRCErrorWorkaroundCheck = 0;
+#else
+ uCRCErrorWorkaroundCheck = 0;
+#endif
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
+ * according to SPI instance, Device type, and revision ID.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
+*/
+uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
+{
+#if defined (STM32F101xE) || defined (STM32F103xE)
+ /* Check how to handle this CRC error (workaround to be applied or not) */
+ /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
+ if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) )
+ {
+ if (hspi->Instance->RXCRCR == 0)
+ {
+ return (SPI_INVALID_CRC_ERROR);
+ }
+ }
+ return (SPI_VALID_CRC_ERROR);
+#else
+ return (SPI_VALID_CRC_ERROR);
+#endif
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.c
new file mode 100644
index 000000000..adda09148
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.c
@@ -0,0 +1,684 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_sram.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief SRAM HAL module driver.
+ * This file provides a generic firmware to drive SRAM memories
+ * mounted as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SRAM memories. It uses the FSMC layer functions to interface
+ with SRAM devices.
+ The following sequence should be followed to configure the FSMC to interface
+ with SRAM/PSRAM memories:
+
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+ SRAM_HandleTypeDef hsram; and:
+
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SRAM device
+
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+ base register instance for NOR or SRAM extended mode
+
+ (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ mode timings; for example:
+ FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+ (##) Control register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Init()
+ (##) Timing register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
+ FSMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+ (#) You can continuously monitor the SRAM device HAL state by calling the function
+ HAL_SRAM_GetState()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
+
+/** @defgroup SRAM SRAM
+ * @brief SRAM driver modules
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to initialize/de-initialize
+ the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SRAM device initialization sequence
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param Timing: Pointer to SRAM control timing structure
+ * @param ExtTiming: Pointer to SRAM extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the SRAM handle parameter */
+ if(hsram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsram->State == HAL_SRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsram-> Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspInit(hsram);
+ }
+
+ /* Initialize SRAM control Interface */
+ FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+ /* Initialize SRAM timing Interface */
+ FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+ /* Initialize SRAM extended mode timing Interface */
+ FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Performs the SRAM device De-initialization sequence.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspDeInit(hsram);
+
+ /* Configure the SRAM registers with their reset values */
+ FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+ hsram->State = HAL_SRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SRAM MSP Init.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRAM MSP DeInit.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint8_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint8_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint16_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint16_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint32_t *)pAddress;
+ pDstBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint32_t *)pAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SRAM write operation.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Enable write operation */
+ FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SRAM write operation.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Disable write operation */
+ FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SRAM controller state
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
+ */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+ return hsram->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.h b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.h
new file mode 100644
index 000000000..0f75ca74b
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.h
@@ -0,0 +1,201 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_sram.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_SRAM_H
+#define __STM32F1xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_fsmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__: SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SRAM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group3
+ * @{
+ */
+
+/* SRAM Control functions ******************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group4
+ * @{
+ */
+
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c
new file mode 100644
index 000000000..303a0c567
--- /dev/null
+++ b/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c
@@ -0,0 +1,5329 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_tim.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 15-December-2014
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM OC handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The destination Buffer address.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM OnePulse handle
+ * @param OnePulseMode : Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim : TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @param htim : TIM Encoder Interface handle
+ * @param sConfig : TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim-> Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+
+ /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim : TIM Encoder handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 : The destination Buffer address for IC1.
+ * @param pData2 : The destination Buffer address for IC2.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim : TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM Output Compare handle
+ * @param sConfig : TIM Output Compare configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim : TIM IC handle
+ * @param sConfig : TIM Input Capture configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM handle
+ * @param sConfig : TIM PWM configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
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